diff --git a/COPYING b/COPYING new file mode 100755 index 0000000..3f63885 --- /dev/null +++ b/COPYING @@ -0,0 +1,637 @@ +LA_OPT_NXP_Software_License v16 October 2020 + +IMPORTANT. Read the following NXP Software License Agreement ("Agreement") +completely. By selecting the "I Accept" button at the end of this page, or by +downloading, installing, or using the Licensed Software, you indicate that you +accept the terms of the Agreement and you acknowledge that you have the +authority, for yourself or on behalf of your company, to bind your company to +these terms. You may then download or install the file. In the event of a +conflict between the terms of this Agreement and any license terms and +conditions for NXP's proprietary software embedded anywhere in the Licensed +Software file, the terms of this Agreement shall control. If a separate +license agreement for the Licensed Software has been signed by you and NXP, +then that agreement shall govern your use of the Licensed Software and shall +supersede this Agreement. + +NXP SOFTWARE LICENSE AGREEMENT + +This is a legal agreement between your employer, of which you are an authorized +representative, or, if you have no employer, you as an individual ("you" or +"Licensee"), and NXP B.V. ("NXP"). It concerns your rights to use the software +provided to you in binary or source code form and any accompanying written +materials (the "Licensed Software"). The Licensed Software may include any +updates or error corrections or documentation relating to the Licensed Software +provided to you by NXP under this Agreement. In consideration for NXP allowing +you to access the Licensed Software, you are agreeing to be bound by the terms +of this Agreement. If you do not agree to all of the terms of this Agreement, +do not download or install the Licensed Software. If you change your mind +later, stop using the Licensed Software and delete all copies of the Licensed +Software in your possession or control. Any copies of the Licensed Software +that you have already distributed, where permitted, and do not destroy will +continue to be governed by this Agreement. Your prior use will also continue to +be governed by this Agreement. + +1. DEFINITIONS + +1.1. "Affiliate" means, with respect to a party, any corporation or +other legal entity that now or hereafter Controls, is Controlled by or is under +common Control with such party; where "Control" means the direct or indirect +ownership of greater than fifty percent (50%) of the shares or similar +interests entitled to vote for the election of directors or other persons +performing similar functions. An entity is considered an Affiliate only so long +as such Control exists. + +1.2 "Authorized System" means either (i) Licensee's hardware product +which incorporates an NXP Product or (ii) Licensee's software program which is +used exclusively in connection with an NXP Product and with which the Licensed +Software will be integrated. + +1.3. "Derivative Work" means a work based upon one or more pre-existing +works. A work consisting of editorial revisions, annotations, elaborations, or +other modifications which, as a whole, represent an original work of +authorship, is a Derivative Work. + +1.4 "Intellectual Property Rights" means any and all rights under +statute, common law or equity in and under copyrights, trade secrets, and +patents (including utility models), and analogous rights throughout the world, +including any applications for and the right to apply for, any of the foregoing. + +1.5 "NXP Product" means a programmable processing unit (e.g. a +microprocessor, microcontroller, sensor or digital signal processor) supplied +directly or indirectly from NXP or an NXP Affiliate. + +1.6 "Software Content Register" means the documentation which may +accompany the Licensed Software which identifies the contents of the Licensed +Software, including but not limited to identification of any Third Party +Software, if any, and may also contain other related information as whether the +license in 2.3 is applicable. + +1.7 "Third Party Software" means, any software included in the Licensed +Software that is not NXP proprietary software, and is not open source software, +and to which different license terms may apply. + +2. LICENSE GRANT. + +2.1. If you are not expressly granted the distribution license in +Section 2.3 in the Software Content Register, then you are only granted the +rights in Section 2.2 and not in 2.3. If you are expressly granted the +distribution license in Section 2.3 in the Software Content Register, then you +are granted the rights in both Section 2.2 and 2.3. + +2.2. Standard License. Subject to the terms and conditions of this +Agreement, NXP grants you a worldwide, personal, non-transferable, +non-exclusive, non-sublicensable license, solely for the development of an +Authorized System: + +(a) to use and reproduce the Licensed Software (and its Derivative Works +prepared under the license in Section 2.2(b)); and + +(b) for Licensed Software provided to you in source code form (human +readable), to prepare Derivative Works of the Licensed Software. + +You may not distribute or sublicense the Licensed Software to others under the +license granted in this Section 2.2. + +2.3. Additional Distribution License. If expressly authorized in the +Software Content Register, subject to the terms and conditions of this +Agreement, NXP grants you a worldwide, personal, non-transferable, +non-exclusive, non-sublicensable license solely in connection with your +manufacturing and distribution of an Authorized System: + +(a) to manufacture (or have manufactured), distribute, and market +the Licensed Software (and its Derivative Works prepared under the license in +2.2(b)) in object code (machine readable format) only as part of, or embedded +within, Authorized Systems and not on a standalone basis. Notwithstanding the +foregoing, those files marked as .h files ("Header files") may be distributed +in source or object code form, but only as part of, or embedded within +Authorized Systems; and + +(b) to copy and distribute as needed, solely in connection with an +Authorized System, non-confidential NXP information provided as part of the +Licensed Software for the purpose of maintaining and supporting Authorized +Systems with which the Licensed Software is integrated. + +2.4 Separate license grants to Third Party Software, or other terms +applicable to the Licensed Software if different from those granted in this +Section 2, are contained in Appendix A. The Licensed Software may be +accompanied by a Software Content Register which will identify that portion of +the Licensed Software, if any, that is subject to the different terms in +Appendix A. + +2.5. You may use subcontractors on your premises to exercise your +rights under Section 2.2 and Section 2.3, if any, so long as you have an +agreement in place with the subcontractor containing confidentiality +restrictions no less stringent than those contained in this Agreement. You will +remain liable for your subcontractors' adherence to the terms of this Agreement +and for any and all acts and omissions of such subcontractors with respect to +this Agreement and the Licensed Software. + +3. LICENSE LIMITATIONS AND RESTRICTIONS. + +3.1. The licenses granted above in Section 2 only extend to NXP +Intellectual Property Rights that would be infringed by the unmodified Licensed +Software prior to your preparation of any Derivative Work. + +3.2. The Licensed Software is licensed to you, not sold. Title to +Licensed Software delivered hereunder remains vested in NXP or NXP's licensor +and cannot be assigned or transferred. You are expressly forbidden from selling +or otherwise distributing the Licensed Software, or any portion thereof, except +as expressly permitted herein. This Agreement does not grant to you any implied +rights under any NXP or third party Intellectual Property Rights. + +3.3. You may not translate, reverse engineer, decompile, or disassemble +the Licensed Software except to the extent applicable law specifically +prohibits such restriction. You must prohibit your subcontractors or customers +(if distribution is permitted) from translating, reverse engineering, +decompiling, or disassembling the Licensed Software except to the extent +applicable law specifically prohibits such restriction. + +3.4. You must reproduce any and all of NXP's (or its third-party +licensor's) copyright notices and other proprietary legends on copies of +Licensed Software. + +3.5. If you distribute the Licensed Software to the United States +Government, then the Licensed Software is "restricted computer software" and is +subject to FAR 52.227-19. + +3.6. You grant to NXP a non-exclusive, non-transferable, irrevocable, +perpetual, worldwide, royalty-free, sub-licensable license under your +Intellectual Property Rights to use without restriction and for any purpose any +suggestion, comment or other feedback related to the Licensed Software +(including, but not limited to, error corrections and bug fixes). + +3.7. You will not take or fail to take any action that could subject +the Licensed Software to an Excluded License. An Excluded License means any +license that requires, as a condition of use, modification or distribution of +software subject to the Excluded License, that such software or other software +combined and/or distributed with the software be (i) disclosed or distributed +in source code form; (ii) licensed for the purpose of making Derivative Works; +or (iii) redistributable at no charge. + +3.8. You may not publish or distribute reports associated with the use +of the Licensed Software to anyone other than NXP. You may advise NXP of any +results obtained from your use of the Licensed Software, including any problems +or suggested improvements thereof, and NXP retains the right to use such +results and related information in any manner it deems appropriate. + +4. OPEN SOURCE. Open source software included in the Licensed +Software is not licensed under the terms of this Agreement but is instead +licensed under the terms of the applicable open source license(s), such as the +BSD License, Apache License or the GNU Lesser General Public License. Your use +of the open source software is subject to the terms of each applicable license. +You must agree to the terms of each applicable license, or you cannot use the +open source software. + +5. INTELLECTUAL PROPERTY RIGHTS. Your modifications to the Licensed +Software, and all Intellectual Property Rights associated with, and title +thereto, will be the property of NXP. Upon request, you must provide NXP the +source code of any derivative of the Licensed Software. You agree to assign +all, and hereby do assign all rights, title, and interest to any such +modifications to the Licensed Software to NXP and agree to provide all +assistance reasonably requested by NXP to establish, preserve or enforce such +right. Further, you agree to waive all moral rights relating to your +modifications to the Licensed Software, including, without limitation, all +rights of identification of authorship and all rights of approval, restriction, +or limitation on use or subsequent modification. Notwithstanding the foregoing, +you will have the license rights granted in Section 2 hereto to any such +modifications made by you or your subcontractor. + +6. ESSENTIAL PATENTS. NXP has no obligation to identify or obtain any +license to any Intellectual Property Right of a third-party that may be +necessary for use in connection with technology that is incorporated into the +Authorized System (whether or not as part of the Licensed Software). + +7. TERM AND TERMINATION. This Agreement will remain in effect unless +terminated as provided in this Section. + +7.1. You may terminate this Agreement immediately upon written notice +to NXP at the address provided below. + +7.2. Either party may terminate this Agreement if the other party is in +default of any of the terms and conditions of this Agreement, and termination +is effective if the defaulting party fails to correct such default within 30 +days after written notice thereof by the non-defaulting party to the defaulting +party at the address below. + +7.3. Notwithstanding the foregoing, NXP may terminate this Agreement +immediately upon written notice if you: breach any of your confidentiality +obligations or the license restrictions under this Agreement; become bankrupt, +insolvent, or file a petition for bankruptcy or insolvency; make an assignment +for the benefit of its creditors; enter proceedings for winding up or +dissolution; are dissolved; or are nationalized or become subject to the +expropriation of all or substantially all of your business or assets. + +7.4. Upon termination of this Agreement, all licenses granted under +Section 2 will expire. + +7.5. After termination of this Agreement by either party you will +destroy all parts of Licensed Software and its Derivative Works (if any) and +will provide to NXP a statement certifying the same. + +7.6. Notwithstanding the termination of this Agreement for any reason, +the terms of Sections 1 and 3 through 24 will survive. + +8. SUPPORT. NXP is not obligated to provide any support, upgrades or +new releases of the Licensed Software under this Agreement. If you wish, you +may contact NXP and report problems and provide suggestions regarding the +Licensed Software. NXP has no obligation to respond to such a problem report or +suggestion. NXP may make changes to the Licensed Software at any time, without +any obligation to notify or provide updated versions of the Licensed Software +to you. + +9. NO WARRANTY. To the maximum extent permitted by law, NXP expressly +disclaims any warranty for the Licensed Software. The Licensed Software is +provided "AS IS", without warranty of any kind, either express or implied, +including without limitation the implied warranties of merchantability, fitness +for a particular purpose, or non-infringement. You assume the entire risk +arising out of the use or performance of the licensed software, or any systems +you design using the licensed software (if any). + +10. INDEMNITY. You agree to fully defend and indemnify NXP from all +claims, liabilities, and costs (including reasonable attorney's fees) related +to (1) your use (including your subcontractor's or distributee's use, if +permitted) of the Licensed Software or (2) your violation of the terms and +conditions of this Agreement. + +11. LIMITATION OF LIABILITY. EXCLUDING LIABILITY FOR A BREACH OF +SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS AND RESTRICTIONS), +SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER SECTION 10 (INDEMNITY), +IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN CONTRACT, TORT, OR +OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE +DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF +TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, TO +THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP'S TOTAL LIABILITY FOR ALL +COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION +WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO +THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION WITH THE LICENSED +SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. + +12. EXPORT COMPLIANCE. Each party shall comply with all applicable +export and import control laws and regulations including but not limited to the +US Export Administration Regulation (including restrictions on certain military +end uses and military end users as specified in Section 15 C.F.R. § 744.21 and +prohibited party lists issued by other federal governments), Catch-all +regulations and all national and international embargoes. Each party further +agrees that it will not knowingly transfer, divert, export or re-export, +directly or indirectly, any product, software, including software source code, +or technology restricted by such regulations or by other applicable national +regulations, received from the other party under this Agreement, or any direct +product of such software or technical data to any person, firm, entity, country +or destination to which such transfer, diversion, export or re-export is +restricted or prohibited, without obtaining prior written authorization from +the applicable competent government authorities to the extent required by those +laws. + +13. GOVERNMENT CONTRACT COMPLIANCE + +13.1. If you sell Authorized Systems directly to any government or public +entity, including U.S., state, local, foreign or international governments or +public entities, or indirectly via a prime contractor or subcontractor of such +governments or entities, NXP makes no representations, certifications, or +warranties whatsoever about compliance with government or public entity +acquisition statutes or regulations, including, without limitation, statutes or +regulations that may relate to pricing, quality, origin or content. + +13.2. The Licensed Software has been developed at private expense and is a +"Commercial Item" as defined in 48 C.F.R. Section 2.101, consisting of +"Commercial Computer Software", and/or "Commercial Computer Software +Documentation," as such terms are used in 48 C.F.R. Section 12.212 (or 48 +C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared +with U.S. Government end users in object code form as part of, or embedded +within, Authorized Systems. Any agreement pursuant to which you share the +Licensed Software will include a provision that reiterates the limitations of +this document and requires all sub-agreements to similarly contain such +limitations. + +14. CRITICAL APPLICATIONS. In some cases, NXP may promote certain +software for use in the development of, or for incorporation into, products or +services (a) used in applications requiring fail-safe performance or (b) in +which failure could lead to death, personal injury, or severe physical or +environmental damage (these products and services are referred to as "Critical +Applications"). NXP's goal is to educate customers so that they can design +their own end-product solutions to meet applicable functional safety standards +and requirements. Licensee makes the ultimate design decisions regarding its +products and is solely responsible for compliance with all legal, regulatory, +safety, and security related requirements concerning its products, regardless +of any information or support that may be provided by NXP. As such, Licensee +assumes all risk related to use of the Licensed Software in Critical +Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL +APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP +harmless from any claims, liabilities, damages and associated costs and +expenses (including attorneys' fees) that NXP may incur related to Licensee’s +incorporation of the Licensed Software in a Critical Application. + +15. CHOICE OF LAW; VENUE. This Agreement will be governed by, +construed, and enforced in accordance with the laws of The Netherlands, without +regard to conflicts of laws principles, will apply to all matters relating to +this Agreement or the Licensed Software, and you agree that any litigation will +be subject to the exclusive jurisdiction of the courts of Amsterdam, The +Netherlands. The United Nations Convention on Contracts for the International +Sale of Goods will not apply to this document. + +16. CONFIDENTIAL INFORMATION. Subject to the license grants and +restrictions contained herein, you must treat the Licensed Software as +confidential information and you agree to retain the Licensed Software in +confidence perpetually. You may not disclose any part of the Licensed Software +to anyone other than distributees in accordance with Section 2.3 and employees, +or subcontractors in accordance with Section 2.5, who have a need to know of +the Licensed Software and who have executed written agreements obligating them +to protect such Licensed Software to at least the same degree of +confidentiality as in this Agreement. You agree to use the same degree of care, +but no less than a reasonable degree of care, with the Licensed Software as you +do with your own confidential information. You may disclose Licensed Software +to the extent required by a court or under operation of law or order provided +that you notify NXP of such requirement prior to disclosure, which you only +disclose the minimum of the required information, and that you allow NXP the +opportunity to object to such court or other legal body requiring such +disclosure. + +17. TRADEMARKS. You are not authorized to use any NXP trademarks, brand +names, or logos. + +18. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement +between you and NXP regarding the subject matter of this Agreement, and +supersedes all prior communications, negotiations, understandings, agreements +or representations, either written or oral, if any. This Agreement may only be +amended in written form, signed by you and NXP. + +19. SEVERABILITY. If any provision of this Agreement is held for any +reason to be invalid or unenforceable, then the remaining provisions of this +Agreement will be unimpaired and, unless a modification or replacement of the +invalid or unenforceable provision is further held to deprive you or NXP of a +material benefit, in which case the Agreement will immediately terminate, the +invalid or unenforceable provision will be replaced with a provision that is +valid and enforceable and that comes closest to the intention underlying the +invalid or unenforceable provision. + +20. NO WAIVER. The waiver by NXP of any breach of any provision of this +Agreement will not operate or be construed as a waiver of any other or a +subsequent breach of the same or a different provision. + +21. AUDIT. You will keep full, clear and accurate records with respect +to your compliance with the limited license rights granted under this Agreement +for three years following expiration or termination of this Agreement. NXP will +have the right, either itself or through an independent certified public +accountant to examine and audit, at NXP's expense, not more than once a year, +and during normal business hours, all such records that may bear upon your +compliance with the limited license rights granted above. You must make prompt +adjustment to compensate for any errors and/or omissions disclosed by such +examination or audit. + +22. NOTICES. All notices and communications under this +Agreement will be made in writing, and will be effective when received at the +following addresses: + + NXP: NXP B.V. + High Tech Campus 60 + 5656 AG Eindhoven + The Netherlands + ATTN: Legal Department + + You: The address provided at registration will be used. + +23. RELATIONSHIP OF THE PARTIES. The parties are independent +contractors. Nothing in this Agreement will be construed to create any +partnership, joint venture, or similar relationship. Neither party is +authorized to bind the other to any obligations with third parties. + +24. SUCCESSION AND ASSIGNMENT. This Agreement will be binding upon and +inure to the benefit of the parties and their permitted successors and assigns. + You may not assign this Agreement, or any part of this Agreement, without the +prior written approval of NXP, which approval will not be unreasonably withheld +or delayed. NXP may assign this Agreement, or any part of this Agreement, in +its sole discretion. + +25. PRIVACY. By agreeing to this Agreement and/or utilizing the Licensed +Software, Licensee consents to use of certain personal information, including +but not limited to name, email address, and location, for the purpose of +NXP’s internal analysis regarding future software offerings. NXP’s +complete Privacy Statement can be found at: +https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACT +ICES. + +APPENDIX A + +Other License Grants and Restrictions: + +The Licensed Software may include some or all of the following software, which +is either 1) Third Party Software or 2) NXP proprietary software subject to +different terms than those in the Agreement. If the Software Content Register +that accompanies the Licensed Software identifies any of the following Third +Party Software or specific components of the NXP proprietary software, the +following terms apply to the extent they deviate from the terms in the +Agreement: + +Amazon: Use of the Amazon software constitutes your acceptance of the terms of +the Amazon Program Materials License Agreement (including the AVS Component +Schedule, if applicable), located at +https://developer.amazon.com/support/legal/pml. All Amazon software is hereby +designated "Amazon confidential". Amazon is a third-party beneficiary to this +Agreement with respect to the Amazon software. + +Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, +or embedded within, Authorized Systems that include an Amphion Video Decoder. + +Aquantia Corp.: You may use Aquantia's API binaries solely to flash the API +software to an NXP Product which mates with an Aquantia device. + +Atheros: Use of Atheros software is limited to evaluation and demonstration +only. Permitted distributions must be similarly limited. Further rights must +be obtained directly from Atheros. + +ATI (AMD): Distribution of ATI software must be a part of, or embedded within, +Authorized Systems that include a ATI graphics processor core. + +Broadcom Corporation: Your use of Broadcom Corporation software is restricted +to Authorized Systems that incorporate a compatible integrated circuit device +manufactured or sold by Broadcom. + +Cadence Design Systems: Use of Cadence audio codec software is limited to +distribution only of one copy per single NXP Product. The license granted +herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does +not include a license to the AAC family of technologies which you or your +customer may need to obtain. Configuration tool outputs may only be distributed +by licensees of the relevant Cadence SDK and distribution is limited to +distribution of one copy embedded in a single NXP Product. + +Cirque Corporation: Use of Cirque Corporation technology is limited to +evaluation, demonstration, or certification testing only. Permitted +distributions must be similarly limited. Further rights, including but not +limited to ANY commercial distribution rights, must be obtained directly from +Cirque Corporation. + +Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation +and demonstration only. Permitted distributions must be similarly limited. +Further rights must be obtained from Dolby Laboratories. + +CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to +evaluation and demonstration only. Permitted distributions must be similarly +limited. Further rights must be obtained directly from CSR. + +Crank: Use of Crank Software Inc. software is limited to evaluation and +demonstration only. Permitted distributions must be similarly limited. Further +rights must be obtained directly from Crank Software Inc. + +Cypress Semiconductor Corporation: WWD RTOS source code may only be used in +accordance with the Cypress IOT Community License Agreement located at +https://community.cypress.com/terms-and-conditions!input.jspa?displayOnly=true. + +Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject +to the acceptance of the license conditions described in the LICENSE.INFO file +distributed with all example projects and in the documentation and the +additional clause described below. + +Clause 1: Micro CANopen Plus may not be used for any competitive or comparative +purpose, including the publication of any form of run time or compile time +metric, without the express permission of EmSA. + +Future Technology Devices International Ltd.: Future Technology Devices +International software must be used consistent with the terms found here: +http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm + +Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is +limited to evaluation and demonstration only. Permitted distributions must be +similarly limited. Further rights must be obtained from Global Locate. + +Microsoft: Except for Microsoft PlayReady software, if the Licensed Software +includes software owned by Microsoft Corporation ("Microsoft"), it is subject +to the terms of your license with Microsoft (the "Microsoft Underlying Licensed +Software") and as such, NXP grants no license to you, beyond evaluation and +demonstration in connection with NXP processors, in the Microsoft Underlying +Licensed Software. You must separately obtain rights beyond evaluation and +demonstration in connection with the Microsoft Underlying Licensed Software +from Microsoft. Microsoft does not provide support services for the components +provided to you through this Agreement. If you have any questions or require +technical assistance, please contact NXP. Microsoft Corporation is a third +party beneficiary to this Agreement with the right to enforce the terms of this +Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS +AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED +SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS +AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY +DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, +INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, +INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING +FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With +respect to the Microsoft PlayReady software, you will have the license rights +granted in Section 2, provided that you may not use the Microsoft PlayReady +software unless you have entered into a Microsoft PlayReady Master Agreement +and license directly with Microsoft. + +MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the +Licensed Software includes proprietary software of MindTree in source code +format, Licensee may make modifications and create derivative works only to the +extent necessary for debugging of the Licensed Software. + +MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto +White Balance) software is limited to demonstration, testing, and evaluation +only. In no event may Licensee distribute or sublicense the MM SOLUTIONS +software. Further rights must be obtained directly from MM SOLUTIONS. + +MPEG LA: Use of MPEG LA audio or video codec technology is limited to +evaluation and demonstration only. Permitted distributions must be similarly +limited. Further rights must be obtained directly from MPEG LA. + +MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP +Licensee under any circumstance, even by a signed written amendment to this +Agreement. + +NXP Wireless Charging Library: License to the Software is limited to use in +inductive coupling or wireless charging applications + +Opus: Use of Opus software must be consistent with the terms of the Opus +license which can be found at: http://www.opus-codec.org/license/ + +Oracle JRE (Java): The Oracle JRE must be used consistent with terms found +here: http://java.com/license + +P&E Micro: P&E Software must be used consistent with the terms found here: +http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf + +Pro Design Electronic: Licensee may not modify, create derivative works based +on, or copy the Pro Design software, documentation, hardware execution key or +the accompanying materials. Licensee shall not use Pro Design's or any of its +licensors names, logos or trademarks to market the Authorized System. Only NXP +customers and distributors are permitted to further redistribute the Pro Design +software and only as part of an Authorized System which contains the Pro Design +software. + +Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm +Atheros, Inc. Wi-Fi software must be used strictly in accordance with the +Qualcomm Atheros, Inc. Technology License Agreement that accompanies such +software. Any other use is expressly prohibited. + +Real Networks - GStreamer Optimized Real Format Client Code implementation or +OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real +Format Client Code, or OpenMax Optimized Real Format Client code is restricted +to applications in the automotive market. Licensee must be a final +manufacturer in good standing with a current license with Real Networks for the +commercial use and distribution of products containing the GStreamer Optimized +Real Format Client Code implementation or OpenMax Optimized Real Format Client +Code + +RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not +use the RivieraWaves intellectual property licensed under this Agreement if you +develop, market, and/or license products similar to such RivieraWaves +intellectual property. Such use constitutes a breach of this Agreement. Any +such use rights must be obtained directly from RivieraWaves. + +SanDisk Corporation: If the Licensed Software includes software developed by +SanDisk Corporation ("SanDisk"), you must separately obtain the rights to +reproduce and distribute this software in source code form from SanDisk. +Please follow these easy steps to obtain the license and software: + +(1) Contact your local SanDisk sales representative to obtain the SanDisk +License Agreement. + +(2) Sign the license agreement. Fax the signed agreement to SanDisk USA +marketing department at 408-542-0403. The license will be valid when fully +executed by SanDisk. + +(3) If you have specific questions, please send an email to sales@sandisk.com + +You may only use the SanDisk Corporation Licensed Software on products +compatible with a SanDisk Secure Digital Card. You may not use the SanDisk +Corporation Licensed Software on any memory device product. SanDisk retains +all rights to any modifications or derivative works to the SanDisk Corporation +Licensed Software that you may create. + +SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and +components is restricted for development of NXP ARM7, ARM9, Cortex-M0, +Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only. + +SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used +consistent with the terms found here: http://www.segger.com/jlink-software.html + +Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler +Technologies Licensed Software and related documentation is subject to the +following: + +(1) Duration of the license for the Licensed Software is limited to 12 months, +unless otherwise specified in the license file. + +(2) The Licensed Software is usable by one user at a time on a single +designated computer, unless otherwise agreed by Synopsys. + +(3) Licensed Software and documentation are to be used only on a designated +computer at the designated physical address provided by you on the APEX license +form. + +(4) The Licensed Software is not sub-licensable. + +TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to +evaluation and demonstration only. Permitted distributions must be similarly +limited. Further rights must be obtained directly from TARA Systems. + +Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software +is restricted to NXP SoC based systems that include a compatible connectivity +device manufactured by TI. + +TES Electronic Solutions Germany (TES): TES 3D Surround View software and +associated data and documentation may only be used for evaluation purposes and +for demonstration to third parties in integrated form on a board package +containing an NXP S32V234 device. Licensee may not distribute or sublicense the +TES software. Your license to the TES software may be terminated at any time +upon notice. + +Vivante: Distribution of Vivante software must be a part of, or embedded +within, Authorized Systems that include a Vivante Graphics Processing Unit. diff --git a/MANIFEST b/MANIFEST new file mode 100644 index 0000000..eda89b3 --- /dev/null +++ b/MANIFEST @@ -0,0 +1,48 @@ +38caeaa780dab401ebef3a3da9d70780 platform/drivers/pmic/fsl_pmic.c +82bf356db93bfa49f529d0c76a0d8a0a platform/drivers/pmic/fsl_pmic.h +ea4484cc511d659b34986b50f7e73fb2 platform/drivers/pmic/pf100/fsl_pf100.c +b354dc9fb00475c88586fdc2b588bfde platform/drivers/pmic/pf100/fsl_pf100.h +5ad77c435b37ffd21f8c1955bf9d7a8b platform/drivers/pmic/pf8100/fsl_pf8100.c +b14862703128d8eff0b5d9d23bde1986 platform/drivers/pmic/pf8100/fsl_pf8100.h +88d7f1eb36d25e375eac2b6ff91f099c platform/svc/irq/api.h +813d7ab5458c8f44ffba05a611852ccd platform/svc/irq/rpc.h +600bc1d6fe07fec1c6b296ffaa63ef65 platform/svc/irq/rpc_clnt.c +fa494beafdb946f7012d422c2bb68e16 platform/svc/irq/rpc_srv.c +0a2816ead0cb66d22421c6054c2f1102 platform/svc/irq/svc.c +1bb4e752b57f41f875cfa9c883779911 platform/svc/irq/svc.h +992c19260d200d34bc1619b979587191 platform/svc/misc/api.h +1fc0fb8a3b26bd9c04a8fb750e288665 platform/svc/misc/rpc.h +f1a3e517c6d7ebb5fd10449893126ba7 platform/svc/misc/rpc_clnt.c +102b74b2bd00fdf644f2c26744591668 platform/svc/misc/rpc_srv.c +7db4e398adb76f97323063b3702c7ab0 platform/svc/misc/svc.c +9b4fb3f8448ca3f1f962cc5412631147 platform/svc/misc/svc.h +e58921623b77a8f7c9fdb9c978b6befe platform/svc/pad/api.h +2b5798909a98d184151d4f8180bbdf61 platform/svc/pad/rpc.h +3fb4259ea648dedae38854fde3b2e935 platform/svc/pad/rpc_clnt.c +794de06fb2f52d5fc00a03e4edf552f4 platform/svc/pad/rpc_srv.c +7c7ef45c2492dbeab5b7f87ef3d6751c platform/svc/pad/svc.c +11c5303759c83ffe5f4a1ac64a930862 platform/svc/pad/svc.h +9472e8313cfc90d6c9eee3c35bf0b37e platform/svc/pm/api.h +5f2bbdbc3c9076a3123a83b4e25c4863 platform/svc/pm/rpc.h +32a5025ce0e9806bdc5233e365ebd2ff platform/svc/pm/rpc_clnt.c +04b99e848feff9837353364f36c5b166 platform/svc/pm/rpc_srv.c +0f166dc9af5dd1388b5b9064da41d1f4 platform/svc/pm/svc.c +e70fc5ea40fe60d80c76f61a80862499 platform/svc/pm/svc.h +b837e88c0c48c4aff822fcb4889c659d platform/svc/rm/api.h +3ab95a3542e47f0f389de824ba6ed68c platform/svc/rm/rpc.h +627a61f2a25e01b2fac5f765f6b290fb platform/svc/rm/rpc_clnt.c +9d8f0b421c2c072d8426bd4098c5d551 platform/svc/rm/rpc_srv.c +f41b344707e75a8ee59065805fbe9b2a platform/svc/rm/svc.c +921ebb45be5f5f8c99c237c55006d198 platform/svc/rm/svc.h +6e31778eb5bb9094aadf467bc11c849a platform/svc/seco/api.h +dd6efc20df99ab32183afe984914f3d8 platform/svc/seco/rpc.h +2ce894bf04554f4c8897c443aa43882c platform/svc/seco/rpc_clnt.c +038d084a239b3d8616445bd2ab7e57be platform/svc/seco/rpc_srv.c +b9d1ceb45df9d51e0c4b123d02a777d5 platform/svc/seco/svc.c +03c0afdd9a3eca7732b51afba8f14b7b platform/svc/seco/svc.h +16e95255ac43e3741b48ad37f67efbf8 platform/svc/timer/api.h +0a0bb7020011f894d936e3695f8f66d2 platform/svc/timer/rpc.h +d772586141a305cdc8b5fe8db8a1f77d platform/svc/timer/rpc_clnt.c +b147740cebe0654ec4ba21d4882de201 platform/svc/timer/rpc_srv.c +15fd6a4703e96ebcce4fddc156ca0978 platform/svc/timer/svc.c +8077ad38d8cde0a24f5b6740088d36d9 platform/svc/timer/svc.h diff --git a/Makefile b/Makefile new file mode 100755 index 0000000..dacced8 --- /dev/null +++ b/Makefile @@ -0,0 +1,669 @@ +## ################################################################### +## +## Copyright 2019-2020 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +# This Makefile will build the System Controller and Test + +SHELL=/bin/bash -o pipefail + +# Configure Si Rev +DEF_SREV := B0 +ifdef r + R := $(r) +endif +LOWER_R := $(shell echo $(R) | tr A-Z a-z) +UPPER_R := $(shell echo $(R) | tr a-z A-Z) +export R LOWER_R UPPER_R + +# Configure emul +ifdef z + Z := $(z) +endif +ifndef Z + Z = 0 +endif +ifeq ($(Z),1) + FLAGS += -DEMUL +endif + +# Include config makefiles +HELP := "" +HELP_OPT := "" +MAKECONFIG := $(shell find makefiles -name Makefile.config) +MAKECONFIG += $(shell find makefiles -name Makefile.full) +include $(foreach makeconfig,$(MAKECONFIG),$(makeconfig)) + +# Default config +CONFIG ?= mx8qm +DEVICE ?= ALL +OUT ?= build_api +HW ?= SIMU +PROJ ?= "" +SREC_OFFSET ?= 0x00000000 +DOXYGEN ?= doxygen +DOX_OUT = $(OUT)/docs +FLAGS += -DCPU_$(DEVICE) $(OPT) -DECC_CLEAN + +# Configure verbose logging + +ifdef v + V := $(v) +endif +ifeq ($(V),1) + AT := +else + AT := @ +endif +export AT + +# Configure forced error +ifdef f + F := $(f) +endif +ifndef F + F = 0 +endif +ifeq ($(F),1) + FLAGS += -DFORCE_COMPILE_ERROR +endif +ifeq ($(F),2) + FLAGS += -DFORCE_TEST_ERROR +endif + +# Configure board +ifdef b + B := $(b) +endif +ifdef ALIAS_B +ifeq ($(B), $(ALIAS_B)) + override B = $(MAP_B) +endif +endif +ifeq ($(HW), SIMU) + override B := none +endif +ifndef DEF_B + DEF_B := val +endif +ifndef B + B := $(DEF_B) +endif +LOWER_B := $(shell echo $(B) | tr A-Z a-z) +export B +export LOWER_B +ifeq ($(LOWER_B),none) + BOARD = none +else + BOARD = $(CONFIG)_$(LOWER_B) +endif +FLAGS += -DBOARD_$(shell echo $(B) | tr a-z A-Z) + +# Configure SS +ifdef c + C := $(c) +endif +ifndef C + C := ALL +endif +LOWER_C := $(shell echo $(C) | tr A-Z a-z) +UPPER_C := $(shell echo $(C) | tr a-z A-Z) +export C LOWER_C UPPER_C + +# Configure debug +ifdef d + D := $(d) +endif +ifndef D + D = 1 +endif +ifeq ($(D),1) + DEBUG = -g -DDEBUG -Os +else + DEBUG = -Os +endif +ifeq ($(COVERAGE),1) + DEBUG = -DGCOV -fprofile-arcs -ftest-coverage + LDFLAGS = -lgcov --coverage +endif +ifdef dl + DL := $(dl) +endif +ifdef DL + FLAGS += -DDL=$(DL) +endif +ifdef tl + TL := $(tl) +endif +ifdef TL + FLAGS += -DTL=$(TL) +endif + +#configure LTO (link time optimization) +ifdef lto + LTO := $(lto) +endif +ifndef lto + LTO = 0 +endif +ifeq ($(LTO),1) + CFLAG_LTO = -flto + FLAGS += -DLTO +endif + +# Configure tests +ifdef t + T := $(t) +endif +ifndef T + T := NONE +else + FLAGS += -DHAS_TEST +endif +LOWER_T := $(shell echo $(T) | tr A-Z a-z) +UPPER_T := $(shell echo $(T) | tr a-z A-Z) +export T LOWER_T UPPER_T +ifeq ($(LOWER_T),all) + FLAGS += -DTEST_ALL +endif +ifeq ($(LOWER_T),boottime) + FLAGS += -DTEST_BOOTTIME +endif +FLAGS += -DTEST=$(LOWER_T) + +# Configure XRDC +ifdef x + X := $(x) +endif +ifndef X + X = 1 +endif +ifeq ($(X),1) + FLAGS += -DXRDC_SUPPORT +endif +ifeq ($(X),2) + FLAGS += -DXRDC_SUPPORT -DXRDC_NOCHECK +endif + +# Configure UART +ifdef u + U := $(u) +endif +ifndef U + U = 0 +endif +ifeq ($(D),0) + FLAGS += -DDEBUG_UART=0 +else + FLAGS += -DDEBUG_UART=$(U) +endif + +# Configure MSI posted writes +ifdef w + W := $(w) +endif +ifndef W + W = 1 +endif +FLAGS += -DPOST_WR_LIMIT=$(W) + +# Configure AutoCal +ifdef ac + AC := $(ac) +endif +ifndef AC + AC = 0 +endif +ifeq ($(AC),1) + FLAGS += -DAUTOCAL +endif + +# Configure manifest +MANIFEST := $(shell md5sum --status -c MANIFEST 1>&2 2> /dev/null; echo $$?) +ifeq ($(MANIFEST),1) + FLAGS += -DDIRTY +endif + +FLAGS += -DSREV_$(UPPER_R) + +OUT := $(OUT)_$(LOWER_R) + +# Configure monitor +ifdef m + M := $(m) +endif +ifndef M + M = 0 +endif +ifndef EM + EM = 0 +endif +ifeq ($(M),1) + FLAGS += -DMONITOR + DCDFLAGS += -DMINIMIZE +endif +ifeq ($(EM),1) + FLAGS += -DEXPORT_MONITOR + DCDFLAGS += -DMINIMIZE +endif + +ifdef NO_OVLY + FLAGS += -DNO_OVLY +endif + +ifdef NO_WDOG_DIS + FLAGS += -DNO_WDOG_DIS +endif + +# Check config +ifeq ($(D),0) +ifeq ($(M),1) +$(error M=1 and D=0 are mutually exclusive) +endif +endif + +WARNS = -Wall -Wextra -Wno-missing-braces -Wno-missing-field-initializers \ + -Wfloat-equal -Wswitch-default -Wcast-align \ + -Wpointer-arith -Wredundant-decls -Wbad-function-cast -Wstrict-prototypes \ + -Wundef -Wcast-qual -Wshadow \ + -Wold-style-definition -Wno-unused-parameter -Werror + +ifneq ($(HW), SIMU) + WARNS += -Wstack-usage=1024 +endif + +# Set common flags +rootdir := $(CURDIR) +SRC = platform +DOC = doc +FLAGS += $(DEBUG) ${WARNS} +# Configure tools +ifeq ($(wildcard $(TOOLS)/srec/srec_cat),) + SREC_CAT = srec_cat +else + SREC_CAT = $(TOOLS)/srec/srec_cat +endif +ifeq ($(wildcard $(TOOLS)/cppcheck/cppcheck),) + CPPCHECK = cppcheck +else + CPPCHECK = $(TOOLS)/cppcheck/cppcheck +endif + +# Configure compiler +ifeq ($(HW), SIMU) + #GNU GCC + AS = as + LD = ld + CC = gcc + CPP = cpp + AR = ar + NM = nm + LDR = ldr + STRIP = strip + OBJCOPY = objcopy + OBJDUMP = objdump + GCOV = gcov + + INCLUDE = -I$(rootdir)/platform/ \ + -I$(rootdir)/platform/CMSIS/Include/ \ + -I$(rootdir)/platform/drivers/common/ \ + -I$(rootdir)/platform/devices/ \ + -I$(rootdir)/platform/devices/$(DEVICE)/ \ + -I$(rootdir)/platform/devices/MX8/ \ + -I$(rootdir)/platform/config/$(CONFIG)/ \ + -I$(rootdir)/platform/config/$(CONFIG)/$(UPPER_C) \ + -I$(rootdir)/platform/board/$(BOARD) + +ifneq ($(COVERAGE),1) +ifneq ($(NO_ASAN),1) + CFLAGS += -fsanitize=address -fno-omit-frame-pointer -fsanitize=undefined + LDFLAGS += -lasan -lubsan +endif +endif + + CFLAGS += $(FLAGS) -std=gnu99 -m32 -fshort-enums + LDFLAGS += -m32 -Wl,-lrt + FLAGS += -DSIMU -DNO_DEVICE_ACCESS + WARNS += -Wformat=2 -Wnested-externs + TEST_CFLAGS := $(CFLAGS) +else + CROSS_COMPILE = $(TOOLS)/gcc-arm-none-eabi-*/bin/arm-none-eabi- + #GNU GCC + AS = $(CROSS_COMPILE)as + LD = $(CROSS_COMPILE)ld + CC = $(CROSS_COMPILE)gcc + CPP = $(CROSS_COMPILE)cpp + AR = $(CROSS_COMPILE)ar + NM = $(CROSS_COMPILE)nm + LDR = $(CROSS_COMPILE)ldr + STRIP = $(CROSS_COMPILE)strip + OBJCOPY = $(CROSS_COMPILE)objcopy + OBJDUMP = $(CROSS_COMPILE)objdump + CPPCHECK = $(TOOLS)/cppcheck/cppcheck + + SYSROOT := $(shell $(CC) -print-sysroot) + INCLUDE = -I$(SYSROOT)/usr/include \ + -I$(rootdir)/platform/ \ + -I$(rootdir)/platform/CMSIS/Include/ \ + -I$(rootdir)/platform/drivers/common/ \ + -I$(rootdir)/platform/devices/ \ + -I$(rootdir)/platform/devices/$(DEVICE)/ \ + -I$(rootdir)/platform/devices/MX8/ \ + -I$(rootdir)/platform/config/$(CONFIG)/ \ + -I$(rootdir)/platform/config/$(CONFIG)/$(UPPER_C) \ + -I$(rootdir)/platform/board/$(BOARD) + ARCHFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=softfp -mfpu=fpv4-sp-d16 + CFLAGS = $(INCLUDE) $(ARCHFLAGS) $(FLAGS) -ffunction-sections -std=c99 -mno-unaligned-access -pipe -fno-common -ffunction-sections -fdata-sections -ffreestanding -mapcs -std=c99 -fno-builtin -fshort-enums -DNDEBUG + TEST_CFLAGS := $(CFLAGS) + CFLAGS += $(CFLAG_LTO) + AFLAGS = $(INCLUDE) $(ARCHFLAGS) $(FLAGS) -fno-common -ffunction-sections -fdata-sections -mno-unaligned-access -ffreestanding -fno-builtin -std=c99 -pipe + LDFLAGS += -Wl,--defsym=__ram_vector_table__=1 -Wl,-Bstatic -Wl,--gc-sections -nostdlib +ifeq ($(D),1) + LIB_C := $(shell $(CC) $(ARCHFLAGS) --print-file-name=libc_nano.a) + LIB_GCC := $(shell $(CC) $(ARCHFLAGS) --print-file-name=libgcc.a) + LCNANO := -lc_nano +else + LCNANO := +endif + WARNS += -Wformat=0 -Wunreachable-code +endif + +export $(CFLAGS) + +# Define Components to build +SUBCOMPS := devices test + +SUBCOMPS += main + +ifeq ($(HW), REAL) + SUBCOMPS += utilities +endif + +# Define drivers, subsystems, and services to build for the SoC + +include $(SRC)/config/$(CONFIG)/soc.bom + +# Define drivers, subsystems, and services to build for the board + +include $(SRC)/board/$(BOARD)/board.bom + +SUBCOMPS += soc/$(SOC) + +include $(foreach subcomp,$(SUBCOMPS),$(rootdir)/$(SRC)/$(subcomp)/Makefile) + +ifeq ($(HW), REAL) + DRV += $(DRV2) +endif + +ifeq ($(DEVICE), ALL) + DRV := $(shell find $(SRC)/drivers -name Makefile) + SS := $(shell find $(SRC)/ss -name Makefile) + BRD := $(shell find $(SRC)/board -name Makefile) + SVC := $(shell find $(SRC)/svc -mindepth 1 -type d) + DOX_API := $(foreach svc,$(SVC),$(svc)/api.h) + include $(foreach drv,$(DRV),$(drv)) + include $(foreach ss,$(SS),$(ss)) + include $(foreach brd,$(BRD),$(brd)) + include $(foreach svc,$(SVC),$(svc)/Makefile) +else + include $(foreach drv,$(DRV),$(SRC)/drivers/$(drv)/Makefile) + include $(SRC)/ss/inf/Makefile + include $(foreach ss,$(SS),$(rootdir)/$(SRC)/ss/$(ss)/Makefile) + include $(SRC)/board/$(BOARD)/Makefile + include $(foreach svc,$(SVC),$(rootdir)/$(SRC)/svc/$(svc)/Makefile) + DOX_API := $(foreach svc,$(SVC),platform/svc/$(svc)/api.h) + DOX_ADD := platform/config/$(CONFIG) + DOX_ADD += $(foreach drv,$(DRV),platform/drivers/$(drv)) + DOX_ADD += $(foreach drv,$(DRV2),platform/drivers/$(drv)) + DOX_ADD += platform/drivers/snvs/doxygen//fsl_snvs.dox + DOX_ADD += platform/drivers/snvs/fsl_snvs.h + DOX_ADD += platform/drivers/seco/doxygen + DOX_ADD += platform/drivers/seco/fsl_seco.h + DOX_ADD += platform/ss/inf + DOX_ADD += $(foreach ss,$(SS),platform/ss/$(ss)) + DOX_ADD += $(DOX_ADD_COMMON) + DOX_ADD += platform/board/$(BOARD) + DOX_ADD += $(foreach svc,$(SVC),platform/svc/$(svc)) +endif + +# Dox input files + +DOX_SOC := doc/resources.md doc/clocks.md doc/controls.md doc/pads.md + +ifdef EXP + DOX_SOC += doc/memmap.md + MD += doc/memmap.md +endif + +ifeq ($(LOWER_T),all) + TCM_LD = $(SRC)/devices/$(DEVICE)/linker/gcc/$(DEVICE)_overlay.ld +else + TCM_LD = $(SRC)/devices/$(DEVICE)/linker/gcc/$(DEVICE)_tcm.ld +endif + +ifdef NO_OVLY + TCM_LD = $(SRC)/devices/$(DEVICE)/linker/gcc/$(DEVICE)_tcm.ld +endif + +FUSE_DIRNAME=../test_files +ifneq "$(wildcard $(FUSE_DIRNAME) )" "" + FIRST_R := $(shell echo $(UPPER_R) | cut -c1-1) + FUSEFILES += $(shell find ../test_files/$(CONFIG)/fuses -name "*$(FIRST_R).txt") + FUSELOGS += $(FUSEFILES:../test_files/$(CONFIG)/%=$(OUT)/%) +endif + +CONFIG_DIRNAME=../test_files +ifneq "$(wildcard $(CONFIG_DIRNAME) )" "" + CONFIGFILES += $(shell find ../test_files/$(CONFIG)/configs -name "*.txt") + CONFIGLOGS += $(CONFIGFILES:../test_files/$(CONFIG)/%=$(OUT)/%) +endif + +# Build rules + +all : help + +ifndef NO_IPC + OBJS += ${RPCS} ${RPCL} +endif + +CONFIGH+=$(SRC)/config/$(CONFIG)/pads.h +CONFIGH+=$(SRC)/config/$(CONFIG)/pad_data.h +CONFIGH+=$(SRC)/config/$(CONFIG)/pad_priority.h +TPROTOH+=$(SRC)/test/$(CONFIG)/test_all.c $(SRC)/test/common/test.h $(SRC)/devices/$(DEVICE)/linker/gcc/$(DEVICE)_overlay.ld +PAD_MD += $(SRC)/config/pad.txt +MEMMAP_MD += $(SRC)/devices/$(DEVICE)/memmap_md.txt + +BIH+=$(SRC)/main/build_info.h + +INCH+= $(SRC)/config/$(CONFIG)/all_api.h $(SRC)/config/$(CONFIG)/all_svc.h \ + $(SRC)/config/$(CONFIG)/all_ss.h $(SRC)/config/$(CONFIG)/all_config.h \ + $(SRC)/config/$(CONFIG)/ss_ver.h + +MD+=doc/resources.md doc/clocks.md doc/controls.md doc/pads.md + +.SECONDARY : ${INCH} ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${RPCHDR} ${RSRC_MD} ${CLK_MD} $(CTRL_MD) $(MEMMAP_MD) $(TPROTOH) + +.INTERMEDIATE : ${MD} $(SRC)/test/board_system_config.c + +.PRECIOUS : ${DCDH} + +GCOV_OUT := $(OBJS:.o=.gcov) + +# Include config makefiles +MAKERULE := $(shell find makefiles -name Makefile.rules) +include $(foreach makerule,$(MAKERULE),$(makerule)) + +$(OUT)/sc : ${OBJS} + ${CC} -o "$@" ${OBJS} ${LDFLAGS} + +-include $(OBJS:.o=.d) + +.SUFFIXES : + +# Include pkit makefiles +MAKERULE2 := $(shell find makefiles -name Makefile.rules2) +include $(foreach makerule,$(MAKERULE2),$(makerule)) + +$(OUT)/board/board_common.o : $(SRC)/board/board_common.c ${INCH} ${INFH} ${CONFIGH} ${BIH} ${DCDH} $(SRC)/test/common/test.h + @echo "Compiling $<" + $(AT)${CC} ${CFLAGS} ${INCLUDE} -c $< -o $@ + +$(SRC)/board/$(CONFIG)_$(B)/dcd/%.h : $(SRC)/board/$(CONFIG)_$(B)/dcd/%.cfg + @echo "Generating $@" + $(AT)rm -f $(*F).temp + $(AT)${CPP} -P -I$(SRC)/devices $(DCDFLAGS) $< $(*F).temp + $(AT)sed -i -f bin/dcd.sed $(*F).temp + $(AT)echo "#ifndef $(subst .,_,$(*F))_H" > $@ + $(AT)echo "#define $(subst .,_,$(*F))_H" >> $@ + $(AT)cat $(*F).temp >> $@ + $(AT)echo '#endif' >> $@ + $(AT)rm -f $(*F).temp + +$(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h : $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h + @echo "Generating $@ from $<" + $(AT)rm -f $@ + $(AT)echo "#ifndef DCD_H" > $@ + $(AT)echo "#define DCD_H" >> $@ + $(AT)echo "#include \"$(DDR_CON).h\"" >> $@ + $(AT)echo '#endif' >> $@ + +$(SRC)/board/$(CONFIG)_$(B)/dcd/%_retention.h : $(SRC)/board/$(CONFIG)_$(B)/dcd/%.cfg + @echo "Generating $@" + $(AT)rm -f $(*F)_ret.temp + $(AT)${CPP} -P -I$(SRC)/devices $(DCDFLAGS) $< $(*F)_ret.temp + $(AT)sed -i -f bin/retention.sed $(*F)_ret.temp + $(AT)echo "#ifndef $(subst .,_,$(*F))_RET_H" > $@ + $(AT)echo "#define $(subst .,_,$(*F))_RET_H" >> $@ + $(AT)cat $(*F)_ret.temp >> $@ + $(AT)echo '#endif' >> $@ + $(AT)rm -f $(*F)_ret.temp + +$(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h : $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h + @echo "Generating $@ from $<" + $(AT)rm -f $@ + $(AT)echo "#ifndef DDR_RETENTION_H" > $@ + $(AT)echo "#define DDR_RETENTION_H" >> $@ + $(AT)echo "#include \"$(DDR_CON)_retention.h\"" >> $@ + $(AT)echo '#endif' >> $@ + +$(OUT)/fuses/%.txt : $(OUT)/ $(OUT)/sc + $(AT)mkdir -p $(OUT)/fuses + $(OUT)/sc -r 0 -f ../test_files/$(CONFIG)/fuses/$*.txt 2> $(OUT)/fuses/$*.txt + $(OUT)/sc -r 1 -f ../test_files/$(CONFIG)/fuses/$*.txt 2> $(OUT)/fuses/$*.txt + +$(OUT)/configs/%.txt : $(OUT)/ $(OUT)/sc + $(AT)mkdir -p $(OUT)/configs + $(OUT)/sc -r 0 -c ../test_files/$(CONFIG)/configs/$*.txt 2> $(OUT)/configs/$*.txt + $(OUT)/sc -r 1 -c ../test_files/$(CONFIG)/configs/$*.txt 2> $(OUT)/configs/$*.txt + +$(OUT)/%.gcov : $(FUSELOGS) $(CONFIGLOGS) + @echo "Coverage $@" + $(AT)${GCOV} -p platform/$*.c -o $(OUT)/$* + + +$(OUT)/%.o : $(SRC)/%.S + @echo "Assembling $<" + $(AT)${CC} ${AFLAGS} ${INCLUDE} -c $< -o $@ + +$(OUT)/scfw.bin : $(OUT)/scfw.elf + @echo "Objcopy $@ ...." + $(AT)$(OBJCOPY) -O binary --gap-fill 0x0 $(OUT)/scfw.elf $(OUT)/scfw.bin --strip-debug + +$(OUT)/scfw_tcm.bin : $(OUT)/scfw_tcm.elf + @echo "Objcopy $@ ...." + $(AT)$(OBJCOPY) -O binary --gap-fill 0x0 -R .test* $(OUT)/scfw_tcm.elf $(OUT)/scfw_tcm.bin --strip-debug + +$(OUT)/scfw_tests.bin : $(OUT)/scfw_tcm.elf + @echo "Objcopy $@ ...." + $(AT)$(OBJCOPY) -O binary --gap-fill 0x0 -j .test* $(OUT)/scfw_tcm.elf $(OUT)/scfw_tests.bin --strip-debug + +$(OUT)/scfw.hex : $(OUT)/scfw.srec + @echo "Generating hex $@ ...." + @-rm -f $(OUT)/scfw.hex + $(AT)$(SREC_CAT) $(OUT)/scfw.srec -byte_swap 4 -crop 0x00000000 0xffffffff -offset $(SREC_OFFSET) -Line_Length=82 -output $(OUT)/scfw.hex -vmem 32 + +$(OUT)/scfw_tcm.hex : $(OUT)/scfw_tcm.srec + @echo "Generating hex $@ ...." + $(AT)$(SREC_CAT) $(OUT)/scfw_tcm.srec -byte_swap 4 -crop 0x00000000 0xffffffff -offset 0x11000000 -Line_Length=82 -output $(OUT)/scfw_tcm.hex -vmem 32 + +$(OUT)/scfw_tests.hex : $(OUT)/scfw_tests.srec + @echo "Generating hex $@ ...." + $(AT)$(SREC_CAT) $(OUT)/scfw_tests.srec -byte_swap 4 -crop 0x00000000 0xffffffff -offset 0x11000000 -Line_Length=82 -output $(OUT)/scfw_tests.hex -vmem 32 + +$(OUT)/scfw.srec : $(OUT)/scfw.elf + @echo "Generating srec $@ ...." + $(AT)-rm -f $(OUT)/scfw_fb.bin + $(AT)$(OBJCOPY) -O srec --gap-fill 0x0 --pad-to 0x10000 $(OUT)/scfw.elf $(OUT)/scfw.srec --strip-debug + +$(OUT)/scfw_tcm.srec : $(OUT)/scfw_tcm.elf + @echo "Objcopy $@ ...." + $(AT)$(OBJCOPY) -O srec --gap-fill 0x0 -R .test* --pad-to 0x30000 $(OUT)/scfw_tcm.elf $(OUT)/scfw_tcm.srec --strip-debug + +$(OUT)/scfw_tests.srec : $(OUT)/scfw_tcm.elf + @echo "Objcopy $@ ...." + $(AT)$(OBJCOPY) -O srec --gap-fill 0x0 -j .test* --pad-to 0x30000 $(OUT)/scfw_tcm.elf $(OUT)/scfw_tests.srec --strip-debug + +$(OUT)/scfw.elf : $(OUT)/devices/$(DEVICE)/gcc/startup_$(DEVICE).o $(SRC)/devices/$(DEVICE)/linker/gcc/$(DEVICE)_flash.ld + @echo "Linking $@ ...." + $(AT)$(CC) $(ARCHFLAGS) $(LDFLAGS) -o $@ -T $(SRC)/devices/$(DEVICE)/linker/gcc/$(DEVICE)_flash.ld $(OUT)/devices/$(DEVICE)/gcc/startup_$(DEVICE).o -lgcc -Wl,-Map=$(OUT)/scfw.map + +$(OUT)/scfw_tcm.elf : $(OBJS) $(TCM_LD) + @echo "Linking $@ ...." + $(AT)$(CC) $(ARCHFLAGS) $(LDFLAGS) -o $@ -T $(TCM_LD) $(OBJS) $(LCNANO) -lgcc -Wl,-Map=$(OUT)/scfw_tcm.map + +$(OUT)/ : FORCE + $(AT)-rm -f log.txt + $(AT)-mkdir -p $(DIRS) + +FORCE: + +help : + @/bin/echo -e "Usage: make TARGET OPTIONS\n" + @/bin/echo -e "Targets:" + @/bin/echo -e "\thelp : display help text" + @/bin/echo -e "\tclean : remove all build files\n" + @/bin/echo -en $(HELP) + @/bin/echo -e "\nOptions:" + @/bin/echo -e "\tV=0 : quite output (default)" + @/bin/echo -e "\tV=1 : verbose output" + @/bin/echo -e "\tD=0 : configure for no debug" + @/bin/echo -e "\tD=1 : configure for debug (default)" + @/bin/echo -e "\tDL= : configure debug level (0-5)" + @/bin/echo -e "\tB= : configure board (default=val)" + @/bin/echo -e "\tU= : configure debug UART (default=0)" + @/bin/echo -e "\tDDR_CON= : specify DDR config file" + @/bin/echo -e "\tR= : silicon revision (default=A0)" + @/bin/echo -e "\tM=0 : no debug monitor (default)" + @/bin/echo -e "\tM=1 : include debug monitor" + @/bin/echo -e "\tLTO=0 : build without link-time optimization (default)" + @/bin/echo -e "\tLTO=1 : build with link-time optimization" + @/bin/echo -e "\tT= : run tests rather than boot next core" + @/bin/echo -en $(HELP_OPT) + diff --git a/SCR-imx-scfw-porting-kit.txt b/SCR-imx-scfw-porting-kit.txt new file mode 100755 index 0000000..cf30a74 --- /dev/null +++ b/SCR-imx-scfw-porting-kit.txt @@ -0,0 +1,13 @@ +NXP Software Content Register + +-------------------------------------------- + +Package: imx-scfw-porting-kit*.bin +Outgoing License: LA_OPT_NXP_Software_License - Production Use, Section 2.3 applies +License File: COPYING +Type of content: Binary +Description and comments: System Controller firmware +Release Location: NXP.com +Origin: NXP (proprietary) + Freescale Semiconductor, Inc. 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zk!HJ2e|fHR%VQZ|p9wnp<$!NrezgaD?sl(o*%?b&qTL_*$y*C~j%*Yq`pb2M?K@@l z;B)%u<{R9PuNi#%8jpPNx%GSAWfv@K3H|syo4ef;Adi0MTp-oOb<53n1`6Evb99{q zCU?89x!Ns+B=T{5xbC^-ZT|^*^ZLnq*CnsWC6DW-Ti(u}khi9vypLS+A})D{gO7ST zagFC^r;o@^q_;@B%;QDA$0zGF->DO?evJHS_herA+g3%C7GxuklKK zHlVzbcscU^)KA`C$Q$VhamnLzkZ%1xf;`3q$}4rrd%mB%@Iw4ZF!pQC<%nh+bIW_} zYQs1IOq9np$kFdDkynX4UiEc`@f4n=a4yQ@>!1Djs*cgW+tZ)#OW||!cY<#-1<1vA zc`=T;^;>(5-aAr1>f-3fzugMo>tr2X!;aJCno5obn*eL#;tvm9=GE)^4CGQC=PBES dyu|hSNr)RR{hTDW_kH+UaU(I;)qunIzW~*>4QBuV literal 0 HcmV?d00001 diff --git a/makefiles/mx8dxl/Makefile.config b/makefiles/mx8dxl/Makefile.config new file mode 100755 index 0000000..8291c19 --- /dev/null +++ b/makefiles/mx8dxl/Makefile.config @@ -0,0 +1,40 @@ + +# Local settings +LLC := dxl +LUC := DXL +LOPT := -DHAS_SECO -DHAS_V2X +LSOFF := 0x32060000 + +# Determine configs +ifeq ($(MAKECMDGOALS), $(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + DEF_B := evk + ALIAS_B := mek + MAP_B := evk + TEST_B := evk + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), clean-obj-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + LC := $(LLC) + UC := $(LUC) +endif + +#Help text +HELP += \ + "\t$(LLC) : build for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" + diff --git a/makefiles/mx8dxl/Makefile.full b/makefiles/mx8dxl/Makefile.full new file mode 100755 index 0000000..104288d --- /dev/null +++ b/makefiles/mx8dxl/Makefile.full @@ -0,0 +1,214 @@ + +# Local settings +LLC := dxl +LUC := DXL +LOPT := -DHAS_SECO -DHAS_V2X +LSOFF := 0x32060000 + +ifeq ($(MAKECMDGOALS), clean-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), $(LLC)e) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + TEST_B := evk + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), gcov-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + TEST_B := evk + COVERAGE := 1 + SIMUCFG := serial + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), $(LLC)m4) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) -DM4_BOOT + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), dox-api-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + PROJ := "i.MX8DXL Die" + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), dox-hw-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + PROJ := "i.MX8DXL Die" + LC := $(LLC) + UC := $(LUC) + EXP := hw_ + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), dox-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + PROJ := "i.MX8DXL Die" + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), obj-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + B ?= mek + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), cppcheck-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), cppcheck-dump-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), info-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), memmap-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), export-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + B ?= evk + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + DL ?= 0 + TL ?= 0 + EM ?= 1 + TEST_B := evk + ifneq ($(UPPER_R),A0) + ifneq ($(UPPER_R),A1) + $(error Invalid revision) + endif + endif +endif + +#Help text +HELP += \ + "\tclean-$(LLC) : remove all build files for the i.MX8$(LUC) build\n" \ + "\t$(LLC)e : build for i.MX8$(LUC) die simulation, output in build_mx8$(LLC)\n" \ + "\tdox-api-$(LLC) : generate API docs for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" \ + "\tdox-hw-$(LLC) : generate HW docs for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" \ + "\tdox-$(LLC) : generate docs for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" \ + "\tcppcheck-$(LLC) : run cppcheck to do static code analysis for i.MX8$(LUC) die\n" \ + "\tinfo-$(LLC) : display info for i.MX8$(LUC) die port\n" \ + "\texport-$(LLC) : export files for i.MX8$(LUC) die customer package\n" + diff --git a/makefiles/mx8dxl/Makefile.rules b/makefiles/mx8dxl/Makefile.rules new file mode 100755 index 0000000..08227e5 --- /dev/null +++ b/makefiles/mx8dxl/Makefile.rules @@ -0,0 +1,143 @@ + +# Local settings +LLC := dxl + +# Build rules + +ifeq ($(Z),1) + +ifeq ($(LOWER_T),all) + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw_tests.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex $(OUT)/scfw_tests.hex + @echo "done." + +else + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex + @echo "done." + +$(LLC)m4 : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex + @echo "done." + +endif + +else + +ifeq ($(LOWER_T),all) + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw_tests.bin + @echo "done." + +else + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin + @echo "done." + +endif + +endif + +$(LLC)e : $(OUT)/ $(OUT)/sc + @echo "done." + +gcov-$(LLC) : $(GCOV_OUT) + $(AT)-mkdir $(OUT)/gcov + $(AT)-mv *.gcov $(OUT)/gcov + @echo "done." + +clean-$(LLC) : scrub + $(AT)-rm -rf $(OUT)/ + +clean-obj-$(LLC) : + $(AT)xargs -a bin/pkit_keep -I % rm -rf $(OUT)/%/ + $(AT)-rm -f $(OUT)/scfw*.* + +dox-api-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} doc/protocol.md $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) API $(SRC)/main/rpc.h $(DOX_SOC) $(DOX_API) doc/protocol.md $(SRC)/config/$(CONFIG)/pads.h + $(DOXYGEN) doc/dox/api.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_api_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_api_$(LC)_$(LOWER_R).tar.gz sc_fw_api_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_api_$(LC)_$(LOWER_R) $(OUT)/docs/html + $(AT)sed -i -f doc/dox/refman.sed $(OUT)/docs/latex/refman.tex + $(AT)cd $(OUT)/docs/latex && $(MAKE) + $(AT)-mkdir -p $(DOC)/pdf + $(AT)cp $(OUT)/docs/latex/refman.pdf $(DOC)/pdf/sc_fw_api_$(LC)_$(LOWER_R).pdf + +dox-hw-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) $(UPPER_R) $(SRC)/main/rpc.h $(DOX_SOC) + $(AT)sed -i -f doc/dox/clocks.sed doc/clocks.md + $(DOXYGEN) doc/dox/hw.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_hw_$(LC)_$(LOWER_R).tar.gz sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) $(OUT)/docs/html + $(AT)-mkdir -p $(DOC)/xml + $(AT)mv $(OUT)/docs/xml $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/xml/sc_fw_hw_$(LC)_$(LOWER_R).xml.tar.gz sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) $(OUT)/docs/xml + +dox-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} doc/protocol.md $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) $(UPPER_R) $(SRC)/main/rpc.h $(DOX_ADD) doc/protocol.md + $(DOXYGEN) doc/dox/full.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_$(LC)_$(LOWER_R).tar.gz sc_fw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_$(LC)_$(LOWER_R) $(OUT)/docs/html + +cppcheck-$(LLC) : $(LLC)e + $(AT)$(CPPCHECK) --error-exitcode=1 -q -j 4 --std=c99 -UDSC_VERIFICATION -UNO_DEVICE_ACCESS -USIMU -UDOX -UDOXYGEN -U__cplusplus --enable=warning,performance,style --inline-suppr --suppress=unreadVariable --suppress=unusedStructMember --suppress=redundantAssignment --template='{file}:{line}: ({id}) {message}' -i$(SRC)/test -i$(SRC)/CMSIS -i$(SRC)/drivers/common -i$(SRC)/drivers/lpi2c -i$(SRC)/drivers/lpuart -i$(SRC)/drivers/wdog32 -I$(SRC) $(SRC) 2>&1 | tee -a log.txt + +cppcheck-dump-$(LLC) : $(LLC)e + $(AT)$(CPPCHECK) --dump --max-configs=1 -q -j 4 --std=c99 -UDSC_VERIFICATION -UNO_DEVICE_ACCESS -USIMU -UDOX -UDOXYGEN -U__cplusplus -i$(SRC)/test -i$(SRC)/CMSIS -I$(SRC) $(SRC) + +obj-$(LLC) : $(LLC) + $(AT)$(OBJDUMP) -h $(OUT)/scfw.elf + $(AT)$(OBJDUMP) -t -j .data $(OUT)/scfw.elf + $(AT)$(OBJDUMP) -t -j .bss $(OUT)/scfw.elf + +info-$(LLC) : $(SRC)/config/$(CONFIG)/soc.h + $(AT)perl bin/perl/pll_info.pl $(SRC)/config/$(CONFIG)/soc.h $(SS) + +memmap-$(LLC) : $(SRC)/config/$(CONFIG)/soc.h $(SRC)/devices/$(DEVICE)/memmap.txt + $(AT)perl bin/perl/memmap.pl $(SRC)/config/$(CONFIG)/soc.h $(SRC)/devices/$(DEVICE)/memmap.txt $(SS) + +export-$(LLC) : clean dxl $(TPROTOH) $(EOBJS) + $(AT)mkdir -p scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp -f doc/EULA.txt scfw_export_$(CONFIG)_$(LOWER_R)/COPYING + $(AT)cp -f doc/SCR-imx-scfw-porting-kit.txt scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)cp bin/dcd.sed scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp bin/retention.sed scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp bin/pkit_keep scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)mkdir -p scfw_export_$(CONFIG)_$(LOWER_R)/platform + $(AT)cp -f Makefile scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)sed -i -f bin/export.sed scfw_export_$(CONFIG)_$(LOWER_R)/Makefile + $(AT)cp -rf $(OUT) scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/$(OUT)/scfw*.* + $(AT)xargs -a bin/pkit_keep -I % rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/$(OUT)/% + $(AT)find scfw_export_$(CONFIG)_$(LOWER_R) -name "*.d" -type f -delete + $(AT)find platform -name "*.h" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "*.bom" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "*.ld" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "Makefile" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*.c" -type f -exec md5sum {} + > scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*.h" -type f -exec md5sum {} + >> scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)grep -v platform/board/ scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST > scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp + $(AT)-sort -k 2 scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp -o scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp + $(AT)find makefiles -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find scfw_export_$(CONFIG)_$(LOWER_R)/platform/board -name "*dcd*.h" -type f -exec rm {} + + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/dox + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/export + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/full + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/$(CONFIG)/*.full + $(AT)mv scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.config.unused scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.config + $(AT)mv scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules.unused scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules + $(AT)perl bin/perl/makefile_rules2.pl bin/pkit_keep scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules2 + $(AT)tar --exclude=*.bak -czf ../scfw_export_$(CONFIG)_$(LOWER_R).tar.gz scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R) + diff --git a/makefiles/mx8qm/Makefile.config b/makefiles/mx8qm/Makefile.config new file mode 100755 index 0000000..84a607c --- /dev/null +++ b/makefiles/mx8qm/Makefile.config @@ -0,0 +1,36 @@ + +# Local settings +LLC := qm +LUC := QM +LOPT := -DHAS_SECO +LSOFF := 0x32060000 + +# Determine configs +ifeq ($(MAKECMDGOALS), $(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + DEF_B := val + TEST_B := mek + ifneq ($(UPPER_R),B0) + $(error Invalid revision) + endif +endif +ifeq ($(MAKECMDGOALS), clean-obj-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + LC := $(LLC) + UC := $(LUC) +endif + +#Help text +HELP += \ + "\t$(LLC) : build for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" + diff --git a/makefiles/mx8qm/Makefile.rules b/makefiles/mx8qm/Makefile.rules new file mode 100755 index 0000000..937a6e0 --- /dev/null +++ b/makefiles/mx8qm/Makefile.rules @@ -0,0 +1,143 @@ + +# Local settings +LLC := qm + +# Build rules + +ifeq ($(Z),1) + +ifeq ($(LOWER_T),all) + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw_tests.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex $(OUT)/scfw_tests.hex + @echo "done." + +else + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex + @echo "done." + +$(LLC)m4 : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex + @echo "done." + +endif + +else + +ifeq ($(LOWER_T),all) + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw_tests.bin + @echo "done." + +else + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin + @echo "done." +endif + +endif + +$(LLC)e : $(OUT)/ $(OUT)/sc + @echo "done." + +gcov-$(LLC) : $(GCOV_OUT) + $(AT)-mkdir $(OUT)/gcov + $(AT)-mv *.gcov $(OUT)/gcov + @echo "done." + +clean-$(LLC) : scrub + $(AT)-rm -rf $(OUT)/ + +clean-obj-$(LLC) : + $(AT)xargs -a bin/pkit_keep -I % rm -rf $(OUT)/%/ + $(AT)-rm -f $(OUT)/scfw*.* + +dox-api-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} doc/protocol.md $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) API $(SRC)/main/rpc.h $(DOX_SOC) $(DOX_API) doc/protocol.md $(SRC)/config/$(CONFIG)/pads.h + $(DOXYGEN) doc/dox/api.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_api_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_api_$(LC)_$(LOWER_R).tar.gz sc_fw_api_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_api_$(LC)_$(LOWER_R) $(OUT)/docs/html + $(AT)sed -i -f doc/dox/refman.sed $(OUT)/docs/latex/refman.tex + $(AT)cd $(OUT)/docs/latex && $(MAKE) + $(AT)-mkdir -p $(DOC)/pdf + $(AT)cp $(OUT)/docs/latex/refman.pdf $(DOC)/pdf/sc_fw_api_$(LC)_$(LOWER_R).pdf + +dox-hw-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) $(UPPER_R) $(SRC)/main/rpc.h $(DOX_SOC) + $(AT)sed -i -f doc/dox/clocks.sed doc/clocks.md + $(DOXYGEN) doc/dox/hw.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_hw_$(LC)_$(LOWER_R).tar.gz sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) $(OUT)/docs/html + $(AT)-mkdir -p $(DOC)/xml + $(AT)mv $(OUT)/docs/xml $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/xml/sc_fw_hw_$(LC)_$(LOWER_R).xml.tar.gz sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) $(OUT)/docs/xml + +dox-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} doc/protocol.md $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) $(UPPER_R) $(SRC)/main/rpc.h $(DOX_ADD) doc/protocol.md + $(DOXYGEN) doc/dox/full.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_$(LC)_$(LOWER_R).tar.gz sc_fw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_$(LC)_$(LOWER_R) $(OUT)/docs/html + +cppcheck-$(LLC) : $(LLC)e + $(AT)$(CPPCHECK) --error-exitcode=1 -q -j 4 --std=c99 -UDSC_VERIFICATION -UNO_DEVICE_ACCESS -USIMU -UDOX -UDOXYGEN -U__cplusplus --enable=warning,performance,style --inline-suppr --suppress=unreadVariable --suppress=unusedStructMember --suppress=redundantAssignment --template='{file}:{line}: ({id}) {message}' -i$(SRC)/test -i$(SRC)/CMSIS -i$(SRC)/drivers/common -i$(SRC)/drivers/lpi2c -i$(SRC)/drivers/lpuart -i$(SRC)/drivers/wdog32 -I$(SRC) $(SRC) 2>&1 | tee -a log.txt + +cppcheck-dump-$(LLC) : $(LLC)e + $(AT)$(CPPCHECK) --dump --max-configs=1 -q -j 4 --std=c99 -UDSC_VERIFICATION -UNO_DEVICE_ACCESS -USIMU -UDOX -UDOXYGEN -U__cplusplus -i$(SRC)/test -i$(SRC)/CMSIS -i$(SRC)/drivers/common -i$(SRC)/drivers/lpi2c -i$(SRC)/drivers/lpuart -i$(SRC)/drivers/wdog32 -I$(SRC) $(SRC) + +obj-$(LLC) : $(LLC) + $(AT)$(OBJDUMP) -h $(OUT)/scfw.elf + $(AT)$(OBJDUMP) -t -j .data $(OUT)/scfw.elf + $(AT)$(OBJDUMP) -t -j .bss $(OUT)/scfw.elf + +info-$(LLC) : $(SRC)/config/$(CONFIG)/soc.h + $(AT)perl bin/perl/pll_info.pl $(SRC)/config/$(CONFIG)/soc.h $(SS) + +memmap-$(LLC) : $(SRC)/config/$(CONFIG)/soc.h $(SRC)/devices/$(DEVICE)/memmap.txt + $(AT)perl bin/perl/memmap.pl $(SRC)/config/$(CONFIG)/soc.h $(SRC)/devices/$(DEVICE)/memmap.txt $(SS) + +export-$(LLC) : clean qm $(TPROTOH) $(EOBJS) + $(AT)mkdir -p scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp -f doc/EULA.txt scfw_export_$(CONFIG)_$(LOWER_R)/COPYING + $(AT)cp -f doc/SCR-imx-scfw-porting-kit.txt scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)cp bin/dcd.sed scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp bin/retention.sed scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp bin/pkit_keep scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)mkdir -p scfw_export_$(CONFIG)_$(LOWER_R)/platform + $(AT)cp -f Makefile scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)sed -i -f bin/export.sed scfw_export_$(CONFIG)_$(LOWER_R)/Makefile + $(AT)cp -rf $(OUT) scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/$(OUT)/scfw*.* + $(AT)xargs -a bin/pkit_keep -I % rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/$(OUT)/% + $(AT)find scfw_export_$(CONFIG)_$(LOWER_R) -name "*.d" -type f -delete + $(AT)find platform -name "*.h" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "*.bom" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "*.ld" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "Makefile" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find makefiles -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*.c" -type f -exec md5sum {} + > scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*.h" -type f -exec md5sum {} + >> scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)grep -v platform/board/ scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST > scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp + $(AT)-sort -k 2 scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp -o scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp + $(AT)find makefiles -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find scfw_export_$(CONFIG)_$(LOWER_R)/platform/board -name "*dcd*.h" -type f -exec rm {} + + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/dox + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/export + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/full + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/$(CONFIG)/*.full + $(AT)mv scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.config.unused scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.config + $(AT)mv scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules.unused scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules + $(AT)perl bin/perl/makefile_rules2.pl bin/pkit_keep scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules2 + $(AT)tar --exclude=*.bak -czf ../scfw_export_$(CONFIG)_$(LOWER_R).tar.gz scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R) + diff --git a/makefiles/mx8qx/Makefile.config b/makefiles/mx8qx/Makefile.config new file mode 100755 index 0000000..3e2f423 --- /dev/null +++ b/makefiles/mx8qx/Makefile.config @@ -0,0 +1,38 @@ + +# Local settings +LLC := qx +LUC := QX +LOPT := -DHAS_SECO +LSOFF := 0x32060000 + +# Determine configs +ifeq ($(MAKECMDGOALS), $(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + DEF_B := val + TEST_B := mek + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), clean-obj-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + LC := $(LLC) + UC := $(LUC) +endif + +#Help text +HELP += \ + "\t$(LLC) : build for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" + diff --git a/makefiles/mx8qx/Makefile.full b/makefiles/mx8qx/Makefile.full new file mode 100755 index 0000000..53e993f --- /dev/null +++ b/makefiles/mx8qx/Makefile.full @@ -0,0 +1,212 @@ + +# Local settings +LLC := qx +LUC := QX +LOPT := -DHAS_SECO +LSOFF := 0x32060000 + +ifeq ($(MAKECMDGOALS), clean-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), $(LLC)e) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + TEST_B := mek + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), gcov-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + TEST_B := mek + COVERAGE := 1 + SIMUCFG := secondary + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), $(LLC)m4) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) -DM4_BOOT + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), dox-api-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + PROJ := "i.MX8QXP Die" + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), dox-hw-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + PROJ := "i.MX8QXP Die" + LC := $(LLC) + UC := $(LUC) + EXP := hw_ + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), dox-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + PROJ := "i.MX8QXP Die" + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), obj-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), cppcheck-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), cppcheck-dump-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), info-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), memmap-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := SIMU + OPT := $(LOPT) + LC := $(LLC) + UC := $(LUC) + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif +ifeq ($(MAKECMDGOALS), export-$(LLC)) + CONFIG := mx8$(LLC) + DEVICE := MX8$(LUC) + OUT := build_mx8$(LLC) + HW := REAL + OPT := $(LOPT) + SREC_OFFSET := $(LSOFF) + LC := $(LLC) + UC := $(LUC) + DL ?= 0 + TL ?= 0 + EM ?= 1 + TEST_B := mek + ifneq ($(UPPER_R),B0) + ifneq ($(UPPER_R),C0) + $(error Invalid revision) + endif + endif +endif + +#Help text +HELP += \ + "\tclean-$(LLC) : remove all build files for the i.MX8$(LUC) build\n" \ + "\t$(LLC)e : build for i.MX8$(LUC) die simulation, output in build_mx8$(LLC)\n" \ + "\tdox-api-$(LLC) : generate API docs for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" \ + "\tdox-hw-$(LLC) : generate HW docs for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" \ + "\tdox-$(LLC) : generate docs for i.MX8$(LUC) die, output in build_mx8$(LLC)\n" \ + "\tcppcheck-$(LLC) : run cppcheck to do static code analysis for i.MX8$(LUC) die\n" \ + "\tinfo-$(LLC) : display info for i.MX8$(LUC) die port\n" \ + "\texport-$(LLC) : export files for i.MX8$(LUC) die customer package\n" + diff --git a/makefiles/mx8qx/Makefile.rules b/makefiles/mx8qx/Makefile.rules new file mode 100755 index 0000000..f14f595 --- /dev/null +++ b/makefiles/mx8qx/Makefile.rules @@ -0,0 +1,144 @@ + +# Local settings +LLC := qx + +# Build rules + +ifeq ($(Z),1) + +ifeq ($(LOWER_T),all) + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw_tests.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex $(OUT)/scfw_tests.hex + @echo "done." + +else + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex + @echo "done." + +$(LLC)m4 : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw.hex $(OUT)/scfw_tcm.hex + @echo "done." + +endif + +else + +ifeq ($(LOWER_T),all) + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin $(OUT)/scfw_tests.bin + @echo "done." + +else + +$(LLC) : $(OUT)/ $(OUT)/scfw_tcm.bin + @echo "done." + +endif + +endif + +$(LLC)e : $(OUT)/ $(OUT)/sc + @echo "done." + +gcov-$(LLC) : $(GCOV_OUT) + $(AT)-mkdir $(OUT)/gcov + $(AT)-mv *.gcov $(OUT)/gcov + @echo "done." + +clean-$(LLC) : scrub + $(AT)-rm -rf $(OUT)/ + +clean-obj-$(LLC) : + $(AT)xargs -a bin/pkit_keep -I % rm -rf $(OUT)/%/ + $(AT)-rm -f $(OUT)/scfw*.* + +dox-api-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} doc/protocol.md $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) API $(SRC)/main/rpc.h $(DOX_SOC) $(DOX_API) doc/protocol.md $(SRC)/config/$(CONFIG)/pads.h + $(DOXYGEN) doc/dox/api.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_api_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_api_$(LC)_$(LOWER_R).tar.gz sc_fw_api_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_api_$(LC)_$(LOWER_R) $(OUT)/docs/html + $(AT)sed -i -f doc/dox/refman.sed $(OUT)/docs/latex/refman.tex + $(AT)cd $(OUT)/docs/latex && $(MAKE) + $(AT)-mkdir -p $(DOC)/pdf + $(AT)cp $(OUT)/docs/latex/refman.pdf $(DOC)/pdf/sc_fw_api_$(LC)_$(LOWER_R).pdf + +dox-hw-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) $(UPPER_R) $(SRC)/main/rpc.h $(DOX_SOC) + $(AT)sed -i -f doc/dox/clocks.sed doc/clocks.md + $(DOXYGEN) doc/dox/hw.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_hw_$(LC)_$(LOWER_R).tar.gz sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) $(OUT)/docs/html + $(AT)-mkdir -p $(DOC)/xml + $(AT)mv $(OUT)/docs/xml $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/xml/sc_fw_hw_$(LC)_$(LOWER_R).xml.tar.gz sc_fw_hw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_hw_$(LC)_$(LOWER_R) $(OUT)/docs/xml + +dox-$(LLC) : clean $(OUT)/ ${INFH} ${CONFIGH} ${RPCH} ${RPCC} ${MD} doc/protocol.md $(SRC)/main/rpc.h + $(AT)perl bin/perl/addendum_cfg.pl doc/dox/addendum.cfg $(DOX_OUT) $(PROJ) $(UPPER_R) $(SRC)/main/rpc.h $(DOX_ADD) doc/protocol.md + $(DOXYGEN) doc/dox/full.cfg + $(AT)rm -f doc/dox/addendum.cfg + $(AT)-mkdir -p $(DOC)/html + $(AT)mv $(OUT)/docs/html $(OUT)/docs/sc_fw_$(LC)_$(LOWER_R) + $(AT)tar --directory=$(OUT)/docs -czf $(DOC)/html/sc_fw_$(LC)_$(LOWER_R).tar.gz sc_fw_$(LC)_$(LOWER_R) + $(AT)mv $(OUT)/docs/sc_fw_$(LC)_$(LOWER_R) $(OUT)/docs/html + +cppcheck-$(LLC) : $(LLC)e + $(AT)$(CPPCHECK) --error-exitcode=1 -q -j 4 --std=c99 -UDSC_VERIFICATION -UNO_DEVICE_ACCESS -USIMU -UDOX -UDOXYGEN -U__cplusplus --enable=warning,performance,style --inline-suppr --suppress=unreadVariable --suppress=unusedStructMember --suppress=redundantAssignment --template='{file}:{line}: ({id}) {message}' -i$(SRC)/test -i$(SRC)/CMSIS -i$(SRC)/drivers/common -i$(SRC)/drivers/lpi2c -i$(SRC)/drivers/lpuart -i$(SRC)/drivers/wdog32 -I$(SRC) $(SRC) 2>&1 | tee -a log.txt + +cppcheck-dump-$(LLC) : $(LLC)e + $(AT)$(CPPCHECK) --dump --max-configs=1 -q -j 4 --std=c99 -UDSC_VERIFICATION -UNO_DEVICE_ACCESS -USIMU -UDOX -UDOXYGEN -U__cplusplus -i$(SRC)/test -i$(SRC)/CMSIS -I$(SRC) $(SRC) + +obj-$(LLC) : $(LLC) + $(AT)$(OBJDUMP) -h $(OUT)/scfw.elf + $(AT)$(OBJDUMP) -t -j .data $(OUT)/scfw.elf + $(AT)$(OBJDUMP) -t -j .bss $(OUT)/scfw.elf + +info-$(LLC) : $(SRC)/config/$(CONFIG)/soc.h + $(AT)perl bin/perl/pll_info.pl $(SRC)/config/$(CONFIG)/soc.h $(SS) + +memmap-$(LLC) : $(SRC)/config/$(CONFIG)/soc.h $(SRC)/devices/$(DEVICE)/memmap.txt + $(AT)perl bin/perl/memmap.pl $(SRC)/config/$(CONFIG)/soc.h $(SRC)/devices/$(DEVICE)/memmap.txt $(SS) + +export-$(LLC) : clean qx $(TPROTOH) $(EOBJS) + $(AT)mkdir -p scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp -f doc/EULA.txt scfw_export_$(CONFIG)_$(LOWER_R)/COPYING + $(AT)cp -f doc/SCR-imx-scfw-porting-kit.txt scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)cp bin/dcd.sed scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp bin/retention.sed scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)cp bin/pkit_keep scfw_export_$(CONFIG)_$(LOWER_R)/bin + $(AT)mkdir -p scfw_export_$(CONFIG)_$(LOWER_R)/platform + $(AT)cp -f Makefile scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)sed -i -f bin/export.sed scfw_export_$(CONFIG)_$(LOWER_R)/Makefile + $(AT)cp -rf $(OUT) scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/$(OUT)/scfw*.* + $(AT)xargs -a bin/pkit_keep -I % rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/$(OUT)/% + $(AT)find scfw_export_$(CONFIG)_$(LOWER_R) -name "*.d" -type f -delete + $(AT)find platform -name "*.h" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "*.bom" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "*.ld" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find platform -name "Makefile" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find makefiles -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*.c" -type f -exec md5sum {} + > scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)xargs -a bin/pkit_keep -I % find platform/% -name "*.h" -type f -exec md5sum {} + >> scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)grep -v platform/board/ scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST > scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp + $(AT)-sort -k 2 scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp -o scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/MANIFEST.tmp + $(AT)find makefiles -name "*" -type f -exec cp --parents -ft scfw_export_$(CONFIG)_$(LOWER_R) {} + + $(AT)find scfw_export_$(CONFIG)_$(LOWER_R)/platform/board -name "*dcd*.h" -type f -exec rm {} + + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/dox + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/export + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/full + $(AT)rm -f scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/$(CONFIG)/*.full + $(AT)mv scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.config.unused scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.config + $(AT)mv scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules.unused scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules + $(AT)perl bin/perl/makefile_rules2.pl bin/pkit_keep scfw_export_$(CONFIG)_$(LOWER_R)/makefiles/obj/Makefile.rules2 + $(AT)tar --exclude=*.bak -czf ../scfw_export_$(CONFIG)_$(LOWER_R).tar.gz scfw_export_$(CONFIG)_$(LOWER_R) + $(AT)rm -rf scfw_export_$(CONFIG)_$(LOWER_R) + diff --git a/makefiles/obj/Makefile.config b/makefiles/obj/Makefile.config new file mode 100755 index 0000000..8b13789 --- /dev/null +++ b/makefiles/obj/Makefile.config @@ -0,0 +1 @@ + diff --git a/makefiles/obj/Makefile.rules b/makefiles/obj/Makefile.rules new file mode 100755 index 0000000..efec6cd --- /dev/null +++ b/makefiles/obj/Makefile.rules @@ -0,0 +1,26 @@ + +# Build rules + +clean : + $(AT)-rm -f log.txt + $(AT)${MAKE} --no-print-directory clean-obj-qm R=B0 + $(AT)${MAKE} --no-print-directory clean-obj-qx R=B0 + $(AT)${MAKE} --no-print-directory clean-obj-qx R=C0 + $(AT)${MAKE} --no-print-directory clean-obj-dxl R=A0 + +scrub : + $(AT)-rm -f sc_fw.tar.gz + $(AT)-rm -f scfw_export_*.tar.gz + $(AT)-rm -f out.txt + $(AT)-rm -f *.stackdump + $(AT)-rm -f doc/resources.md + $(AT)-rm -f doc/clocks.md + $(AT)-rm -f doc/controls.md + $(AT)-rm -f doc/pad.md + $(AT)-rm -f doc/memmap.md + $(AT)-rm -f doc/protocol.md + $(AT)-find platform/board -name *dcd*.h -exec rm {} \; + $(AT)-find platform/board -name *_retention.h -exec rm {} \; + $(AT)-find platform/board -name *_parser.h -exec rm {} \; + $(AT)-find platform -name *.dump -exec rm {} \; + diff --git a/makefiles/obj/Makefile.rules2 b/makefiles/obj/Makefile.rules2 new file mode 100644 index 0000000..d47d8c2 --- /dev/null +++ b/makefiles/obj/Makefile.rules2 @@ -0,0 +1,15 @@ + +# Pkit build rules + +$(OUT)/board/%.o : $(SRC)/board/%.c ${INCH} ${INFH} ${CONFIGH} ${BIH} ${DCDH} + @echo "Compiling $<" + $(AT)${CC} ${CFLAGS} ${INCLUDE} -c $< -o $@ + +$(OUT)/drivers/pmic/%.o : $(SRC)/drivers/pmic/%.c ${INCH} ${INFH} ${CONFIGH} ${BIH} ${DCDH} + @echo "Compiling $<" + $(AT)${CC} ${CFLAGS} ${INCLUDE} -c $< -o $@ + +$(OUT)/svc/%.o : $(SRC)/svc/%.c ${INCH} ${INFH} ${CONFIGH} ${BIH} ${DCDH} + @echo "Compiling $<" + $(AT)${CC} ${CFLAGS} ${INCLUDE} -c $< -o $@ + diff --git a/platform/CMSIS/Include/Core_A/cmsis_armcc.h b/platform/CMSIS/Include/Core_A/cmsis_armcc.h new file mode 100755 index 0000000..7c4c948 --- /dev/null +++ b/platform/CMSIS/Include/Core_A/cmsis_armcc.h @@ -0,0 +1,544 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) + #define __ARM_ARCH_7A__ 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __wfi + +/** + \brief Wait For Event + */ +#define __WFE __wfe + +/** + \brief Send Event + */ +#define __SEV __sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + +/** + \brief Rotate Right in unsigned value (32 bit) + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +/** \brief Set CPSR (Current Program Status Register) + \param [in] cpsr CPSR value to set + */ +__STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + register uint32_t __regCPSR __ASM("cpsr"); + __regCPSR = cpsr; +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ + MOV r1, lr + MSR CPSR_C, r0 + BX r1 +} + +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP(uint32_t stack) +{ + MOV sp, r0 + BX lr +} + + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + +/** \brief Set FPEXC (Floating Point Exception Control Register) + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) + +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + ENDIF + + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR +} + +#endif /* __CMSIS_ARMCC_H */ diff --git a/platform/CMSIS/Include/Core_A/cmsis_armclang.h b/platform/CMSIS/Include/Core_A/cmsis_armclang.h new file mode 100755 index 0000000..5883364 --- /dev/null +++ b/platform/CMSIS/Include/Core_A/cmsis_armclang.h @@ -0,0 +1,503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __builtin_arm_wfi + +/** + \brief Wait For Event + */ +#define __WFE __builtin_arm_wfe + +/** + \brief Send Event + */ +#define __SEV __builtin_arm_sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __builtin_arm_isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __builtin_arm_dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __builtin_arm_dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP() +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr() +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if __ARM_NEON == 1 + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 " + ); +} + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/platform/CMSIS/Include/Core_A/cmsis_compiler.h b/platform/CMSIS/Include/Core_A/cmsis_compiler.h new file mode 100755 index 0000000..b00c6ba --- /dev/null +++ b/platform/CMSIS/Include/Core_A/cmsis_compiler.h @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/platform/CMSIS/Include/Core_A/cmsis_cp15.h b/platform/CMSIS/Include/Core_A/cmsis_cp15.h new file mode 100755 index 0000000..891bec2 --- /dev/null +++ b/platform/CMSIS/Include/Core_A/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/platform/CMSIS/Include/Core_A/cmsis_gcc.h b/platform/CMSIS/Include/Core_A/cmsis_gcc.h new file mode 100755 index 0000000..5ac93d1 --- /dev/null +++ b/platform/CMSIS/Include/Core_A/cmsis_gcc.h @@ -0,0 +1,675 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 " + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/platform/CMSIS/Include/Core_A/cmsis_iccarm.h b/platform/CMSIS/Include/Core_A/cmsis_iccarm.h new file mode 100755 index 0000000..a441e2d --- /dev/null +++ b/platform/CMSIS/Include/Core_A/cmsis_iccarm.h @@ -0,0 +1,559 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 \n"); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/platform/CMSIS/Include/Core_A/core_ca.h b/platform/CMSIS/Include/Core_A/core_ca.h new file mode 100755 index 0000000..c7c4b51 --- /dev/null +++ b/platform/CMSIS/Include/Core_A/core_ca.h @@ -0,0 +1,2616 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.00 + * @date 22. Feb 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/Core_A/irq_ctrl.h b/platform/CMSIS/Include/Core_A/irq_ctrl.h new file mode 100755 index 0000000..b171ef0 --- /dev/null +++ b/platform/CMSIS/Include/Core_A/irq_ctrl.h @@ -0,0 +1,186 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.0.0 + * @date 23. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/platform/CMSIS/Include/arm_common_tables.h b/platform/CMSIS/Include/arm_common_tables.h new file mode 100755 index 0000000..dfea746 --- /dev/null +++ b/platform/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/platform/CMSIS/Include/arm_const_structs.h b/platform/CMSIS/Include/arm_const_structs.h new file mode 100755 index 0000000..80a3e8b --- /dev/null +++ b/platform/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/platform/CMSIS/Include/arm_math.h b/platform/CMSIS/Include/arm_math.h new file mode 100755 index 0000000..62f87be --- /dev/null +++ b/platform/CMSIS/Include/arm_math.h @@ -0,0 +1,7160 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *

    + * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
    + * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM33) + #include "core_cm33.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/platform/CMSIS/Include/cmsis_armcc.h b/platform/CMSIS/Include/cmsis_armcc.h new file mode 100755 index 0000000..093d35b --- /dev/null +++ b/platform/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/platform/CMSIS/Include/cmsis_armclang.h b/platform/CMSIS/Include/cmsis_armclang.h new file mode 100755 index 0000000..5c4c20e --- /dev/null +++ b/platform/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/platform/CMSIS/Include/cmsis_compiler.h b/platform/CMSIS/Include/cmsis_compiler.h new file mode 100755 index 0000000..94212eb --- /dev/null +++ b/platform/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/platform/CMSIS/Include/cmsis_gcc.h b/platform/CMSIS/Include/cmsis_gcc.h new file mode 100755 index 0000000..91a7c9c --- /dev/null +++ b/platform/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2092 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/platform/CMSIS/Include/cmsis_iccarm.h b/platform/CMSIS/Include/cmsis_iccarm.h new file mode 100755 index 0000000..edcaee3 --- /dev/null +++ b/platform/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/platform/CMSIS/Include/cmsis_version.h b/platform/CMSIS/Include/cmsis_version.h new file mode 100755 index 0000000..660f612 --- /dev/null +++ b/platform/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/platform/CMSIS/Include/core_armv8mbl.h b/platform/CMSIS/Include/core_armv8mbl.h new file mode 100755 index 0000000..47a3989 --- /dev/null +++ b/platform/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_armv8mml.h b/platform/CMSIS/Include/core_armv8mml.h new file mode 100755 index 0000000..0951a1f --- /dev/null +++ b/platform/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm0.h b/platform/CMSIS/Include/core_cm0.h new file mode 100755 index 0000000..a3f1b9a --- /dev/null +++ b/platform/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm0plus.h b/platform/CMSIS/Include/core_cm0plus.h new file mode 100755 index 0000000..f8f30c3 --- /dev/null +++ b/platform/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm23.h b/platform/CMSIS/Include/core_cm23.h new file mode 100755 index 0000000..7d1d478 --- /dev/null +++ b/platform/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm3.h b/platform/CMSIS/Include/core_cm3.h new file mode 100755 index 0000000..a2c0d08 --- /dev/null +++ b/platform/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm33.h b/platform/CMSIS/Include/core_cm33.h new file mode 100755 index 0000000..b1efbca --- /dev/null +++ b/platform/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm4.h b/platform/CMSIS/Include/core_cm4.h new file mode 100755 index 0000000..a11a381 --- /dev/null +++ b/platform/CMSIS/Include/core_cm4.h @@ -0,0 +1,2118 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_cm7.h b/platform/CMSIS/Include/core_cm7.h new file mode 100755 index 0000000..1fe53bf --- /dev/null +++ b/platform/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_sc000.h b/platform/CMSIS/Include/core_sc000.h new file mode 100755 index 0000000..9aab5e5 --- /dev/null +++ b/platform/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/core_sc300.h b/platform/CMSIS/Include/core_sc300.h new file mode 100755 index 0000000..a569ef2 --- /dev/null +++ b/platform/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/platform/CMSIS/Include/mpu_armv7.h b/platform/CMSIS/Include/mpu_armv7.h new file mode 100755 index 0000000..aa180c9 --- /dev/null +++ b/platform/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/platform/CMSIS/Include/mpu_armv8.h b/platform/CMSIS/Include/mpu_armv8.h new file mode 100755 index 0000000..0ccfc74 --- /dev/null +++ b/platform/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/platform/CMSIS/Include/tz_context.h b/platform/CMSIS/Include/tz_context.h new file mode 100755 index 0000000..0d09749 --- /dev/null +++ b/platform/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/platform/board/board.S b/platform/board/board.S new file mode 100755 index 0000000..1b4dd3a --- /dev/null +++ b/platform/board/board.S @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: board.S */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 2015 , Freescale Semiconductor, Inc. */ +/* Copyright 2017-2020 NXP */ +/* */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + +#define ASM_CODE + + .syntax unified + .arch armv7-m + .text + + .align 4 + .globl board_lib_init_array + .weak board_lib_init_array + .type board_lib_init_array, %function +board_lib_init_array: + push {lr} +#ifdef DEBUG + bl __libc_init_array +#endif + pop {lr} + bx lr + diff --git a/platform/board/board_common.c b/platform/board/board_common.c new file mode 100755 index 0000000..8972f16 --- /dev/null +++ b/platform/board/board_common.c @@ -0,0 +1,303 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Implementation file containing the board API. + * + * @addtogroup BRD_SVC BRD: Board Interface + * + * Common code used by all board ports. Common shims for object package + * recompile (tests, monitor, etc.) Some common DRC code. + */ +/*==========================================================================*/ + +/* Includes */ + +#ifdef DEBUG + #include +#endif +#include "main/main.h" +#include "main/board.h" +#include "main/monitor.h" +#include "test/common/test.h" +#include "drivers/wdog32/fsl_wdog32.h" + +/* Forced Error */ + +#ifdef FORCE_COMPILE_ERROR + #error Forced error for testing +#endif + +/* Local Defines */ + +#define CALL_TEST_DRV(X) TEMP_TEST_DRV(X) +#define TEMP_TEST_DRV(X) test_drv_##X + +#define CALL_TEST_SC(X) TEMP_TEST_SC(X) +#define TEMP_TEST_SC(X) test_sc_##X + +#define CALL_TEST_AP(X) TEMP_TEST_AP(X) +#define TEMP_TEST_AP(X) test_ap_##X + +/* Local Functions */ + +/* Local Variables */ + +static sc_bool_t ddr_tick_enable = SC_FALSE; +static sc_bool_t ddr_derate_tick_enable = SC_FALSE; + +/* Global Variables */ + +#ifdef DEBUG + sc_bool_t debug = SC_TRUE; +#else + sc_bool_t debug = SC_FALSE; +#endif + +int8_t debug_level = DEBUG_LEVEL; + +#ifdef HAS_TEST + sc_bool_t has_test = SC_TRUE; +#else + sc_bool_t has_test = SC_FALSE; +#endif + +#ifdef TEST_ALL + sc_bool_t test_all = SC_TRUE; +#else + sc_bool_t test_all = SC_FALSE; +#endif + +#if defined(MONITOR) || defined(EXPORT_MONITOR) + sc_bool_t has_monitor = SC_TRUE; +#else + sc_bool_t has_monitor = SC_FALSE; +#endif + +#ifdef XRDC_NOCHECK + sc_bool_t xrdc_nocheck = SC_TRUE; +#else + sc_bool_t xrdc_nocheck = SC_FALSE; +#endif + +#ifdef DIRTY + sc_bool_t pkit_dirty = SC_TRUE; +#else + sc_bool_t pkit_dirty = SC_FALSE; +#endif + +/*--------------------------------------------------------------------------*/ +/* Driver test shim */ +/*--------------------------------------------------------------------------*/ +sc_err_t test_drv(sc_bool_t *const stop) +{ + #ifdef HAS_TEST + CALL_TEST_DRV(TEST)(stop); + #else + *stop = SC_FALSE; + #endif + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* SCU test shim */ +/*--------------------------------------------------------------------------*/ +sc_err_t test_sc(sc_bool_t *const stop) +{ + #ifdef HAS_TEST + CALL_TEST_SC(TEST)(stop); + #else + *stop = SC_FALSE; + #endif + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* AP test shim */ +/*--------------------------------------------------------------------------*/ +sc_err_t test_ap(sc_bool_t *const stop) +{ + #ifdef HAS_TEST + CALL_TEST_AP(TEST)(stop); + #else + *stop = SC_FALSE; + #endif + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Run monitor */ +/*--------------------------------------------------------------------------*/ +void board_monitor(void) +{ + #ifdef MONITOR + monitor(); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Shim for system exit */ +/*--------------------------------------------------------------------------*/ +void board_exit(int32_t status) +{ + #ifdef DEBUG + exit((int) status); + #else + board_fault(SC_FALSE, BOARD_BFAULT_EXIT, SC_PT); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Shim for setvbuf */ +/*--------------------------------------------------------------------------*/ +void board_stdio(void) +{ + #ifdef DEBUG + (void) setvbuf(stdin, NULL, _IONBF, 0); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Shim for system exit */ +/*--------------------------------------------------------------------------*/ +void board_wdog_disable(sc_bool_t lp) +{ + /* Watchdog disable is called from nowhere else in the code but here. + This can be modified if concerned about watchdog disable. */ + +#if !defined(SIMU) && !defined(NO_WDOG_DIS) + #ifndef DEBUG + if (lp != SC_FALSE) + #endif + { + /* Disable the WDOG */ + WDOG32_Deinit(WDOG_SC); + } +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Conditional printf */ +/*--------------------------------------------------------------------------*/ +void board_printf(const char *fmt, ...) +{ + #ifdef DEBUG + va_list args; + + if (debug == SC_FALSE) + { + return; + } + + va_start(args, fmt); + + #if defined(SIMU) + (void) vfprintf(stderr, fmt, args); + #else + if (SCFW_DBG_READY != 0U) + { + (void) vfprintf(stderr, fmt, args); + } + else + { + SCFW_DBG_SKIPS++; + } + #endif + + va_end(args); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* DDR periodic enable */ +/*--------------------------------------------------------------------------*/ +void board_ddr_periodic_enable(sc_bool_t enb) +{ + if (board_ddr_period_ms != 0U) + { + ddr_tick_enable = enb; + } +} + +/* DDR derate periodic enable */ +/*--------------------------------------------------------------------------*/ +void board_ddr_derate_periodic_enable(sc_bool_t enb) +{ + if (board_ddr_derate_period_ms != 0U) + { + ddr_derate_tick_enable = enb; + } +} + +/*--------------------------------------------------------------------------*/ +/* Common board tick */ +/*--------------------------------------------------------------------------*/ +void board_common_tick(uint16_t msec) +{ + if ((ddr_tick_enable != SC_FALSE) || (ddr_derate_tick_enable != SC_FALSE)) + { + static uint32_t ddr_mseconds = 0U; + static uint32_t ddr_derate_mseconds = 0U; + + /* Tick DDR */ + ddr_mseconds += msec; + ddr_derate_mseconds += msec; + + /* Handle DDR periodic tick */ + if ((ddr_tick_enable != SC_FALSE) && (board_ddr_period_ms != 0U) && (ddr_mseconds >= board_ddr_period_ms)) + { + ddr_mseconds = 0U; + + (void) board_ddr_config(SC_FALSE, BOARD_DDR_PERIODIC); + } + + /* Handle DDR derate periodic tick */ + if ((ddr_derate_tick_enable != SC_FALSE) && (board_ddr_derate_period_ms != 0U) && (ddr_derate_mseconds >= board_ddr_derate_period_ms)) + { + ddr_derate_mseconds = 0U; + + (void) board_ddr_config(SC_FALSE, BOARD_DDR_DERATE_PERIODIC); + } + } + + /* User tick */ + board_tick(msec); +} + diff --git a/platform/board/board_common.h b/platform/board/board_common.h new file mode 100755 index 0000000..30a9b68 --- /dev/null +++ b/platform/board/board_common.h @@ -0,0 +1,157 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing some common board funtions. + * + * @addtogroup BRD_SVC BRD: Board Interface + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_COMMON_H +#define SC_BOARD_COMMON_H + +/* Includes */ + +/* Defines */ + +/* External variables */ + +/*! Shim debug variable (to allow object package config) */ +extern sc_bool_t debug; + +/*! Shim debug level variable (to allow object package config) */ +extern int8_t debug_level; + +/*! Shim has_test variable (to allow object package config) */ +extern sc_bool_t has_test; + +/*! Shim test_all variable (to allow object package config) */ +extern sc_bool_t test_all; + +/*! Shim has_monitor variable (to allow object package config) */ +extern sc_bool_t has_monitor; + +/*! Shim xrdc_nocheck variable (to allow object package config) */ +extern sc_bool_t xrdc_nocheck; + +/*! Shim pkit_dirty variable (to allow object package config) */ +extern sc_bool_t pkit_dirty; + +/* Functions */ + +/*! + * Shim test function (to allow test inclusion from object packages) + * + * @param[in] stop flag indicating if test run should stop + * + * @return Returns an error code (SC_ERR_NONE = success) + */ +sc_err_t test_drv(sc_bool_t *const stop); + +/*! + * Shim test function (to allow test inclusion from object packages) + * + * @param[in] stop flag indicating if test run should stop + * + * @return Returns an error code (SC_ERR_NONE = success) + */ +sc_err_t test_sc(sc_bool_t *const stop); + +/*! + * Shim test function (to allow test inclusion from object packages) + * + * @param[in] stop flag indicating if test run should stop + * + * @return Returns an error code (SC_ERR_NONE = success) + */ +sc_err_t test_ap(sc_bool_t *const stop); + +/*! + * Shim monitor function (to allow monitor inclusion from object packages) + */ +void board_monitor(void); + +/*! + * Shim for exit() + */ +void board_exit(int32_t status); + +/*! + * Shim for setvbuf() + */ +void board_stdio(void); + +/*! + * Shim for watchdog disable + * + * @param[in] lp SC_TRUE = entry of KS1 LP mode + */ +void board_wdog_disable(sc_bool_t lp); + +/*! + * Conditional printf + */ +void board_printf(const char *fmt, ...); + +/*! + * Enable/disable the DDR periodic tick. + * + * @param[in] enb enable flag (SC_TRUE = on) + */ +void board_ddr_periodic_enable(sc_bool_t enb); + +/*! + * Enable/disable the DDR derate periodic tick. + * + * @param[in] enb enable flag (SC_TRUE = on) + */ +void board_ddr_derate_periodic_enable(sc_bool_t enb); + +/*! + * Common function to tick the board. + * + * @param[in] msec number of mS to increment + */ +void board_common_tick(uint16_t msec); + +/** @} */ + +#endif /* SC_BOARD_COMMON_H */ + diff --git a/platform/board/config.h b/platform/board/config.h new file mode 100755 index 0000000..0fcf2b6 --- /dev/null +++ b/platform/board/config.h @@ -0,0 +1,78 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the board subsystem. + * + * @addtogroup BOARD + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_BRD_CONFIG_H +#define SC_BRD_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define BRD_NUM_RSRC_BRD 11U + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_BRD \ + "PMIC_0", \ + "PMIC_1", \ + "PMIC_2", \ + "BOARD_R0", \ + "BOARD_R1", \ + "BOARD_R2", \ + "BOARD_R3", \ + "BOARD_R4", \ + "BOARD_R5", \ + "BOARD_R6", \ + "BOARD_R7", \ + +#endif + +#endif /* SC_BRD_CONFIG_H */ + +/** @} */ + diff --git a/platform/board/drivers/pca6416a/pca6416a.c b/platform/board/drivers/pca6416a/pca6416a.c new file mode 100755 index 0000000..d0b35d9 --- /dev/null +++ b/platform/board/drivers/pca6416a/pca6416a.c @@ -0,0 +1,135 @@ +/* +** ################################################################### +** +** Copyright 2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Implementation of PCA6416A functions + */ +/*==========================================================================*/ + +/* Includes */ + +#include "drivers/pmic/fsl_pmic.h" +#include "board/drivers/pca6416a/pca6416a.h" + +/* Local Defines */ + +/*! + * @name I2C Bus Expander Registers + */ +/** @{ */ +#define BUS_EXP_IN_REG 0x00U +#define BUS_EXP_OUT_REG 0x02U +#define BUS_EXP_POL_REG 0x04U +#define BUS_EXP_CONF_REG 0x06U +/** @} */ + +/*--------------------------------------------------------------------------*/ +/* Write pin direction register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_WritePinDirection(uint8_t device_addr, uint8_t port, + uint8_t dir) +{ + uint8_t temp = dir; + + /* Return result */ + return i2c_write(device_addr, BUS_EXP_CONF_REG + port, &temp, 1U); +} + +/*--------------------------------------------------------------------------*/ +/* Read pin direction register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_ReadPinDirection(uint8_t device_addr, uint8_t port, + uint8_t *dir) +{ + /* Return result */ + return i2c_read(device_addr, BUS_EXP_CONF_REG + port, dir, 1U); +} + +/*--------------------------------------------------------------------------*/ +/* Write pin polarity register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_WritePinPolarity(uint8_t device_addr, uint8_t port, + uint8_t pol) +{ + uint8_t temp = pol; + + /* Return result */ + return i2c_write(device_addr, BUS_EXP_POL_REG + port, &temp, 1U); +} + +/*--------------------------------------------------------------------------*/ +/* Read pin polarity register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_ReadPinPolarity(uint8_t device_addr, uint8_t port, + uint8_t *pol) +{ + /* Return result */ + return i2c_read(device_addr, BUS_EXP_POL_REG + port, pol, 1U); +} + +/*--------------------------------------------------------------------------*/ +/* Write pin output register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_WritePinOutput(uint8_t device_addr, uint8_t port, + uint8_t out) +{ + uint8_t temp = out; + + /* Return result */ + return i2c_write(device_addr, BUS_EXP_OUT_REG + port, &temp, 1U); +} + +/*--------------------------------------------------------------------------*/ +/* Read pin output register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_ReadPinOutput(uint8_t device_addr, uint8_t port, + uint8_t *out) +{ + /* Return result */ + return i2c_read(device_addr, BUS_EXP_OUT_REG + port, out, 1U); +} + +/*--------------------------------------------------------------------------*/ +/* Read pin input register */ +/*--------------------------------------------------------------------------*/ +status_t PCA6416A_ReadPinInput(uint8_t device_addr, uint8_t port, + uint8_t *in) +{ + /* Return result */ + return i2c_read(device_addr, BUS_EXP_IN_REG + port, in, 1U); +} + diff --git a/platform/board/drivers/pca6416a/pca6416a.h b/platform/board/drivers/pca6416a/pca6416a.h new file mode 100755 index 0000000..cd7e0b2 --- /dev/null +++ b/platform/board/drivers/pca6416a/pca6416a.h @@ -0,0 +1,142 @@ +/* +** ################################################################### +** +** Copyright 2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * @brief Functions for PCA6416A. + * + * @addtogroup pca6416a_driver PCA6416A: PCA6416A Driver + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_PCA6416A_H +#define SC_PCA6416A_H + +/* Includes */ + +#include "drivers/pmic/fsl_pmic.h" + +/* Functions */ + +/*! + * This function writes the pin direction regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[in] dir direction (0=output, 1=input) + * + * @return Returns the I2C status. + */ +status_t PCA6416A_WritePinDirection(uint8_t device_addr, uint8_t port, + uint8_t dir); + +/*! + * This function reads the pin direction regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[out] dir pointer to return the direction (0=output, 1=input) + * + * @return Returns the I2C status. + */ +status_t PCA6416A_ReadPinDirection(uint8_t device_addr, uint8_t port, + uint8_t *dir); + +/*! + * This function writes the pin polarity regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[in] pol polarity (1=invert) + * + * @return Returns the I2C status. + */ +status_t PCA6416A_WritePinPolarity(uint8_t device_addr, uint8_t port, + uint8_t pol); + +/*! + * This function reads the pin polarity regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[out] pol pointer to return the polarity (1=invert) + * + * @return Returns the I2C status. + */ +status_t PCA6416A_ReadPinPolarity(uint8_t device_addr, uint8_t port, + uint8_t *pol); + +/*! + * This function writes the pin output regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[in] out output value + * + * @return Returns the I2C status. + */ +status_t PCA6416A_WritePinOutput(uint8_t device_addr, uint8_t port, + uint8_t out); + +/*! + * This function reads the pin output regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[out] out pointer to return the output + * + * @return Returns the I2C status. + */ +status_t PCA6416A_ReadPinOutput(uint8_t device_addr, uint8_t port, + uint8_t *out); + +/*! + * This function reads the pin input regsiter. + * + * @param[in] device_addr I2C address + * @param[in] port expander port + * @param[out] in input + * + * @return Returns the I2C status. + */ +status_t PCA6416A_ReadPinInput(uint8_t device_addr, uint8_t port, + uint8_t *in); + + /** @} */ + + #endif /* SC_PCA6416A_H */ + diff --git a/platform/board/mx8dxl_evk/Makefile b/platform/board/mx8dxl_evk/Makefile new file mode 100755 index 0000000..a1f4813 --- /dev/null +++ b/platform/board/mx8dxl_evk/Makefile @@ -0,0 +1,63 @@ +## ################################################################### +## +## Copyright 2019-2020 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8dxl_dcd_emul +else + DDR_CON ?= imx8dxl_dcd_1.2GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o \ + $(OUT)/board/drivers/pca6416a/pca6416a.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) \ + $(OUT)/board/drivers/pca6416a + +ifeq ($(M),1) + OBJS += $(OUT)/board/pmic.o +endif + diff --git a/platform/board/mx8dxl_evk/board.bom b/platform/board/mx8dxl_evk/board.bom new file mode 100755 index 0000000..4062849 --- /dev/null +++ b/platform/board/mx8dxl_evk/board.bom @@ -0,0 +1,39 @@ +## ################################################################### +## +## Copyright 2019-2020 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf8100 + +ifeq ($(M),1) + DRV2 += pmic/pf100 +endif diff --git a/platform/board/mx8dxl_evk/board.c b/platform/board/mx8dxl_evk/board.c new file mode 100755 index 0000000..2013765 --- /dev/null +++ b/platform/board/mx8dxl_evk/board.c @@ -0,0 +1,1483 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8DXL EVK board. + * + * @addtogroup MX8DXL_EVK_BRD BRD: MX8DXL EVK Board + * + * Module for MX8DXL EVK board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00130 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/igpio/fsl_gpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" +#include "drivers/systick/fsl_systick.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "board/drivers/pca6416a/pca6416a.h" +#include "drivers/nic400/fsl_nic400.h" +#ifdef HAS_SECO +#include "drivers/seco/fsl_seco.h" +#endif + +/* Local Defines */ + +#if defined(BD_DDR_RET_REGION1_SIZE) && (BD_DDR_RET_REGION1_SIZE <= 12) + #ifndef BD_DDR_SIZE + /*! NXP DXL DDR3L EVK board */ + #define BD_DDR_SIZE SC_512MB + #endif +#else + /*! NXP DXL LPDDR4 EVK board */ + #ifndef BD_DDR_SIZE + #define BD_DDR_SIZE SC_1GB + #endif + #define HAS_VDD_MII_SELECT +#endif + +/*! I2C Bus Expander Address */ +#define BUS_EXP_ADDR 0x20U + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_R0 3U /*!< PCA9548APW - U75 */ +#define BRD_R_BOARD_R1 4U /*!< PCA6416APW - U80 */ +#define BRD_R_BOARD_R2 5U /*!< PCA6416APW - U84 */ +#define BRD_R_BOARD_R3 6U /*!< PCA9548APW - U76 */ +#define BRD_R_BOARD_R4 7U /*!< PCA6416APW - U82 */ +#define BRD_R_BOARD_R5 8U /*!< PCA6416APW - U101 (rev A) */ +#define BRD_R_BOARD_R6 9U /*!< VDD_MII_SELECT (rev B) */ +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 3 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif +#if DEBUG_UART == 2 + /*! Use alternate debug UART */ + #define ALT_DEBUG_SCU_UART +#endif +#if (defined(MONITOR) || defined(EXPORT_MONITOR) || defined(HAS_TEST) \ + || (DEBUG_UART == 1)) && !defined(DEBUG_TERM_EMUL) \ + && !defined(ALT_DEBUG_SCU_UART) + #define ALT_DEBUG_SCU_UART +#endif + +/*! Configure debug UART */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG LPUART_SC +#else + #define LPUART_DEBUG LPUART_MCU_0 +#endif + +/*! Configure debug UART instance */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG_INST 0U +#else + #define LPUART_DEBUG_INST 2U +#endif + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +static void board_get_pmic_info(sc_sub_t ss, uint32_t *pmic_reg, + uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t temp_alarm; +static uint8_t dir_cache = 0xFFU; +static uint8_t out_cache = 0xFFU; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 0U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + ss_print(3, "board_init(%d)\n", phase); + + if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #if defined(ALT_DEBUG_SCU_UART) \ + && !defined(DEBUG_TERM_EMUL) + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(ALT_DEBUG_SCU_UART) && !defined(DEBUG_TERM_EMUL) \ + && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Check if debug disabled */ + if (SCFW_DBG_READY == 0U) + { + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + } + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SCL, SC_P_PMIC_I2C_SDA, + SC_FALSE); + #ifdef ALT_DEBUG_SCU_UART + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_INTERNAL; + break; + /* Spread Spectrum SPREAD value for PCIE DPLL */ + case BOARD_PARM_PCIE_DPLL_SS: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + rtn = BOARD_KS1_RESUME_USEC; + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; +#ifndef EMUL + /* VDD_MEMC voltage */ + case BOARD_PARM_VDD_MEMC: + rtn = BOARD_PARM_RTN_VDD_MEMC_OD; + break; +#endif + /* Control if SC WDOG configuration during KS1 */ + case BOARD_PARM_KS1_WDOG_WAKE: + rtn = BOARD_PARM_KS1_WDOG_WAKE_ENABLE; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + +#ifdef EMUL + if(rsrc == SC_R_PMIC_0) + { + rtn = SC_FALSE; + } +#endif + if(rsrc == SC_R_PMIC_1) + { + rtn = SC_FALSE; + } + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. + */ + + sc_err_t err = SC_ERR_NONE; + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR0_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + default: + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_mr_t mr_temp; + sc_saddr_t fw_addr = 0UL; + sc_saddr_t fw_start = 0x87FC0000UL; + sc_saddr_t fw_end = 0x87FFFFFFUL; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Note this code is system specific. Customers should statically define + the V2X FW space. */ + + /* Query V2X for FW address */ + if (soc_aux_get_fw_addr(SOC_IDX_AUX_0, &fw_addr) == SC_ERR_NONE) + { + /* DDR? */ + if (fw_addr >= DDR_BASE0) + { + fw_start = fw_addr & ~0xFFFUL; + } + /* FlexSPI? */ + else if (fw_addr >= FSPI0_MEM_BASE) + { + /* SCFW must be able to reload the V2X FW each time the V2X is powered + * down. It also has to be reloaded if V2X generates a serious error + * IRQ. The owner of the FlexSPI must insure it remains accessible + * (configured and clocked). Otherwise, use the mkimage dummy target + * to relocate the V2X FW out of FlexSPI to OCRAM or DDR. + */ + fw_start = fw_addr & ~0xFFFUL; + /* Assumes 128K for V2X FW and following is SCFW */ + fw_end = fw_start + 0x1FFFFUL; + } + /* OCRAM? */ + else if (fw_addr >= OCRAM_BASE) + { + fw_start = fw_addr & ~0xFFFUL; + fw_end = 0x0013FFFFUL; + } + /* Unknown */ + else + { + fw_start = 0UL; + } + } + + /* Allocate V2X memory */ + if ((fw_start != 0UL) && (ddrtest == SC_FALSE)) + { + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, + U64(fw_start), U64(fw_end))); + BRD_ERR(rm_assign_memreg(pt_boot, SECO_PT, mr_temp)); + /*! @todo remove when V2X using IDs correctly */ + BRD_ERR(rm_set_memreg_permissions(SECO_PT, mr_temp, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + } + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[13U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_8B, + SC_R_GPT_4, + RM_RANGE(SC_R_CAN_0, SC_R_CAN_2), + SC_R_I2C_3, + SC_R_FSPI_0, + SC_R_SECO_MU_4, + SC_R_BOARD_R3, + SC_R_BOARD_R4, + SC_R_BOARD_R7 + }; + + /* List of pads */ + static const sc_pad_t pad_list[8U] = + { + RM_RANGE(SC_P_ADC_IN1, SC_P_ADC_IN2), + RM_RANGE(SC_P_FLEXCAN2_RX, SC_P_FLEXCAN2_TX), + RM_RANGE(SC_P_SPI1_SDI, SC_P_SPI1_CS0), + RM_RANGE(SC_P_QSPI0A_DATA0, SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x08FFFFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Move the M4 UART pads if not used for debug out */ + #ifndef ALT_DEBUG_SCU_UART + BRD_ERR(rm_assign_pad(pt_boot, pt_m4_0, SC_P_SCU_GPIO0_00)); + BRD_ERR(rm_assign_pad(pt_boot, pt_m4_0, SC_P_SCU_GPIO0_01)); + #endif + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[2U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + } + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } + +#ifdef ERR050601_WORKAROUND + /* Power up M4 MU for ddr stress test tool */ + if (ddrtest != SC_FALSE) + { + pm_force_resource_power_mode_v(SC_R_M4_0_MU_1A, + SC_PM_PW_MODE_ON); + } +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + uint32_t pmic_reg = 0U; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, &pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, pmic_reg, + SW_RUN_PWM | SW_STBY_PWM)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, pmic_reg, + SW_RUN_OFF)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process bus expander resources */ + if ((pmic_ver.device_id != 0U) && (idx >= BRD_R_BOARD_R0) + && (idx <= BRD_R_BOARD_R4)) + { + uint8_t mask; + + /* Calculate mask */ + mask = BIT8(U8(idx) - BRD_R_BOARD_R0); + + /* Configure bus expander direction */ + if ((dir_cache & mask) != 0U) + { + out_cache &= ~mask; + (void) PCA6416A_WritePinOutput(BUS_EXP_ADDR, 0U, + out_cache); + dir_cache &= ~mask; + (void) PCA6416A_WritePinDirection(BUS_EXP_ADDR, 0U, + dir_cache); + } + + /* Flip bits */ + if (from_mode == SC_PM_PW_MODE_OFF) + { + out_cache |= mask; + } + else + { + out_cache &= ~mask; + } + + /* Write output */ + (void) PCA6416A_WritePinOutput(BUS_EXP_ADDR, 0U, + out_cache); + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else if ((type == SC_PM_RESET_TYPE_WARM) + && (reason == SC_PM_RESET_REASON_V2X_DEBUG)) + { + /* Disable WDOG_OUT */ + PAD_SetMux(IOMUXD__JTAG_TRST_B, 4U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if (resource == SC_R_M4_0_PID0) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; +#ifdef HAS_VDD_MII_SELECT + case SC_R_BOARD_R6 : + if (val == 0U) + { + out_cache &= ~BIT8(5U); + } + else + { + out_cache |= BIT8(5U); + } + (void) PCA6416A_WritePinOutput(BUS_EXP_ADDR, 0U, + out_cache); + dir_cache &= ~BIT8(5U); + (void) PCA6416A_WritePinDirection(BUS_EXP_ADDR, 0U, + dir_cache); + break; +#endif + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; +#ifdef HAS_VDD_MII_SELECT + case SC_R_BOARD_R6 : + *val = (U32(out_cache) >> 5UL) & 0x1UL; + break; +#endif + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Temp alarm */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR)) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC0_HIGH, + SC_PT_ALL); + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + + /* EVK board spec is for 1M baud for PMIC I2C bus */ + lpi2c_masterConfig.baudRate_Hz = 1000000U; + lpi2c_masterConfig.sdaGlitchFilterWidth_ns = 100U; + lpi2c_masterConfig.sclGlitchFilterWidth_ns = 100U; + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + temp_alarm = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, + PMIC_TEMP_MAX); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + + if (err != SC_ERR_NONE) + { + /* Loop so WDOG will expire */ + HALT; + } + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + uint32_t ks1_volt = 800U; + + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, ks1_volt, + REG_STBY_MODE)); + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + + +/*--------------------------------------------------------------------------*/ +/* Get the PMIC IDs and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss, uint32_t *pmic_reg, + uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A35 : + case SC_SUBSYS_DRC_0 : + case SC_SUBSYS_DB : + pmic_init(); + *pmic_reg = PF8100_SW2; + *num_regs = 1U; + break; + default: + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8dxl_evk/board.h b/platform/board/mx8dxl_evk/board.h new file mode 100755 index 0000000..d7d8a50 --- /dev/null +++ b/platform/board/mx8dxl_evk/board.h @@ -0,0 +1,92 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC pf8100 +#define PMIC_0_ADDR 0x8U + +#define PMIC_TEMP_MAX 135U + +#define PF8100_REGULATORS 12U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8dxl_evk/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8dxl_evk/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..2a4c4a7 --- /dev/null +++ b/platform/board/mx8dxl_evk/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,137 @@ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, // DXL does not require RDBI deskew, but need it defined here to aign the enum properly to allow VREF training command to be parsed + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + + diff --git a/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz.cfg b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz.cfg new file mode 100755 index 0000000..61d5d94 --- /dev/null +++ b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz.cfg @@ -0,0 +1,480 @@ +#define __ASSEMBLY__ + +#include +#include + + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80000420 +DEFINE BD_DDR_RET_REGION2_SIZE 8 + + + +/* + * Device Configuration Data (DCD) Version 1.24 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 1200MHz. */ + uint32_t rate2 = 600000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 1200MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x000000C8); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 // Gate functional clocks +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset (register configuration must be done with DDRC core under reset) +DATA 4 0x41C80204 0x1 // Ungate functional clocks + +//------------------------------------------- +// Configure controller registers +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +DATA 4 DDRC_MSTR_0 0x81080020 // Set LPDDR4, Burst length and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 // REFRESH_BURST +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke, post_cke +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000063F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1718141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000302 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020010 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // DFI control update settings +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00050505 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x13131300 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x04040404 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x04040404 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ADDRMAP7_0 0x00000F0F // addrmap_row_b17, addrmap_row_b16 +DATA 4 DDRC_DBICTL_0 0x00000007 // read DBI, write DBI, Data Mask +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// Performance optimizations +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) + +// Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x07009100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config +//DDR power management settings +DATA 4 DDRC_PWRTMG_0 0x00402010 // Timers for automatic entry into powerdown, self-refresh +DATA 4 DDRC_PWRCTL_0 0x0000010A // Enable DDR low power feature (clock disabling, power down) +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + + + + + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00010002 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00080123 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004567 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00085601 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004327 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // ADCP +DATA 4 DDR_PHY_PGCR2_0 0x00F00F2C // tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x01021080 // CKEN/CKNEN toggling and polarity +DATA 4 DDR_PHY_PGCR7_0 0x00000010 // AC read clock mode +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001BBBB // Impedance control for DQ bus + +//------------------------------------------- +// Configure and launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put AC PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 // Put DQ PLL in power down state +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x09604B10 +DATA 4 DDR_PHY_PTR1_0 0x075302A3 + +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR4, MR5 and MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength +DATA 4 DDR_PHY_MR11_0 0x66 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x06 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +DATA 4 DDR_PHY_MR12_0 0x12 // VREF(CA) +DATA 4 DDR_PHY_MR14_0 0x10 // VREF(DQ) +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x00696159 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000493E0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000012C // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00007530 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00096 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// No ODT signal for LPDDR4 DQ. So disable it. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM, ACRANKCLKSEL +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode +DATA 4 DDR_PHY_ACIOCR1_0 0x00000000 // A[15:0] OE mode selection +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0x90032010 // tVREF, DVINIT, DVMIN, DVMAX, DVINIT +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO, tVREFIO, SHREN, SHRNK +// Set-up PHY General Configuration Registers +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 // Internal VREF generator range selection (1'b1 = 7.69% - 53.49% of VDDQ) +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09090913 // Set VREF value in DXREFISELR0, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090913 // Set VREF value in DXREFISELR0, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL, DXREFSSELRANGE, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL, DXREFSSELRANGE, maintain other defaults +// Set-up DATX8 DX Control Registers +DATA 4 DDR_PHY_DX8SLbDXCTL1_0 0x00840000 // DXRCLKMD +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1200 // POSOEX, PREOEX, LPWAKEUP_THRSH + +// Enable AC PHY PLL and/or IO to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x00190091 // LPWAKEUP_THRSH, LPPLLPD, LPIOPD + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM reset + DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM initialization +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// Wait DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch second DRAM initialization +DATA 4 DDR_PHY_PTR3_0 0x0000012C // tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 // Launch DRAM init + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +// Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Wait disabling of VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00000100 // BMRANK (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // DTRPTN, RFSHDT +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// VREF training +//---------------------------------------------------------------// +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +// Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//---------------------------------------------------------------// +// DQS Drift registers +//---------------------------------------------------------------// +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 // Disable Read DQS Gating LCDL Delay VT Compensation +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 // DFTDLY, DFTB2BRD, DFTIDLRD, DFTDTEN +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 // Disable Drift idle read cycle and Drift back-to-back read cycles +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 // DFTTHRSH, DFTMNTPRD + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +// Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +//---------------------------------------------------------------// +// Check that controller is ready to operate +//---------------------------------------------------------------// +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +//---------------------------------------------------------------// +// Configure ECC (if enable required) +//---------------------------------------------------------------// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//---------------------------------------------------------------// +// DRC configuration end +//---------------------------------------------------------------// + + + + diff --git a/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz_nocbt.cfg b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz_nocbt.cfg new file mode 100755 index 0000000..775804f --- /dev/null +++ b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz_nocbt.cfg @@ -0,0 +1,317 @@ +#define __ASSEMBLY__ + +#include +#include + + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80000420 +DEFINE BD_DDR_RET_REGION2_SIZE 8 + + + +/* + * Device Configuration Data (DCD) Version 1.5 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 // Gate functional clocks +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset (register configuration must be done with DDRC core under reset) +DATA 4 0x41C80204 0x1 // Ungate functional clocks + +//------------------------------------------- +// Configure controller registers +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +DATA 4 DDRC_MSTR_0 0x81080020 // Set LPDDR4, Burst length and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 // REFRESH_BURST +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke, post_cke +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000063F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060C // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000302 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // DFI control update settings +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00050505 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x13131300 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x04040404 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x04040404 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ADDRMAP7_0 0x00000F0F // addrmap_row_b17, addrmap_row_b16 +DATA 4 DDRC_DBICTL_0 0x00000007 // read DBI, write DBI, Data Mask +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// Performance optimizations +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +// Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x07009100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config +// DDR power management settings +DATA 4 DDRC_PWRTMG_0 0x00402010 // Timers for automatic entry into powerdown, self-refresh, … +DATA 4 DDRC_PWRCTL_0 0x0000010A // Enable DDR low power feature (clock disabling, power down, …) +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00010001 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00008765 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004231 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00008765 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004321 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // ADCP +DATA 4 DDR_PHY_PGCR2_0 0x00F00F2C // tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x01021080 // CKEN/CKNEN toggling and polarity +DATA 4 DDR_PHY_PGCR7_0 0x00000010 // AC read clock mode +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BB7B // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001BB5B // Impedance control for DQ bus + +//------------------------------------------- +// Configure and launch ZCAL + PLLINIT + DCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x32 +DATA 4 DDR_PHY_PIR_0 0x33 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR4, MR5 and MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength +DATA 4 DDR_PHY_MR11_0 0x66 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x06 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +DATA 4 DDR_PHY_MR12_0 0x12 // VREF(CA) +DATA 4 DDR_PHY_MR14_0 0x10 // VREF(DQ) +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x00726159 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// No ODT signal for LPDDR4 DQ. So disable it. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM, ACRANKCLKSEL +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode +DATA 4 DDR_PHY_ACIOCR1_0 0x00000000 // A[15:0] OE mode selection +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0x90032010 // tVREF, DVINIT, DVMIN, DVMAX, DVINIT set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO, tVREFIO, SHREN, SHRNK +// Set-up PHY General Configuration Registers +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 // Internal VREF generator range selection (1'b1 = 7.69% - 53.49% of VDDQ) +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09090913 // Set VREF value in DXREFISELR0, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090913 // Set VREF value in DXREFISELR0, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL, DXREFSSELRANGE, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL, DXREFSSELRANGE, maintain other defaults +// Set-up DATX8 DX Control Registers +DATA 4 DDR_PHY_DX8SLbDXCTL1_0 0x00840000 // DXRCLKMD +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1200 // POSOEX, PREOEX, LPWAKEUP_THRSH + +// Enable AC PHY PLL and/or IO to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x00190091 // LPWAKEUP_THRSH, LPPLLPD, LPIOPD + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM reset + DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM initialization +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// Wait DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch second DRAM initialization +DATA 4 DDR_PHY_PTR3_0 0x00000960 // tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 // Launch DRAM init + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Wait disabling of VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 // BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // DTRPTN, RFSHDT +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// VREF training +//---------------------------------------------------------------// +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +// Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//---------------------------------------------------------------// +// DQS Drift registers +//---------------------------------------------------------------// +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 // Disable Read DQS Gating LCDL Delay VT Compensation +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 // DFTDLY, DFTB2BRD, DFTIDLRD, DFTDTEN +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 // Disable Drift idle read cycle and Drift back-to-back read cycles +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 // DFTTHRSH, DFTMNTPRD + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +// Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +//---------------------------------------------------------------// +// Check that controller is ready to operate +//---------------------------------------------------------------// +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + diff --git a/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz_proto_1a.cfg b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz_proto_1a.cfg new file mode 100755 index 0000000..f06d69e --- /dev/null +++ b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_1.2GHz_proto_1a.cfg @@ -0,0 +1,478 @@ +#define __ASSEMBLY__ + +#include +#include + + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80000420 +DEFINE BD_DDR_RET_REGION2_SIZE 8 + + + +/* + * Device Configuration Data (DCD) Version 1.19 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 1200MHz. */ + uint32_t rate2 = 600000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 1200MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x000000C8); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 // Gate functional clocks +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset (register configuration must be done with DDRC core under reset) +DATA 4 0x41C80204 0x1 // Ungate functional clocks + +//------------------------------------------- +// Configure controller registers +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +DATA 4 DDRC_MSTR_0 0x81080020 // Set LPDDR4, Burst length and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 // REFRESH_BURST +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke, post_cke +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000063F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1718141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000302 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020010 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // DFI control update settings +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00050505 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x13131300 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x04040404 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x04040404 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ADDRMAP7_0 0x00000F0F // addrmap_row_b17, addrmap_row_b16 +DATA 4 DDRC_DBICTL_0 0x00000007 // read DBI, write DBI, Data Mask +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// Performance optimizations +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) + +// Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x07009100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config +//DDR power management settings +DATA 4 DDRC_PWRTMG_0 0x00402010 // Timers for automatic entry into powerdown, self-refresh, … +DATA 4 DDRC_PWRCTL_0 0x0000010A // Enable DDR low power feature (clock disabling, power down, …) +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + + + + + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00010001 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00008765 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004231 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00008765 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004321 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // ADCP +DATA 4 DDR_PHY_PGCR2_0 0x00F00F2C // tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x01021080 // CKEN/CKNEN toggling and polarity +DATA 4 DDR_PHY_PGCR7_0 0x00000010 // AC read clock mode +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BB7B // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001BB5B // Impedance control for DQ bus + +//------------------------------------------- +// Configure and launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put AC PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 // Put DQ PLL in power down state +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x09604B10 +DATA 4 DDR_PHY_PTR1_0 0x075302A3 + +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR4, MR5 and MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength +DATA 4 DDR_PHY_MR11_0 0x66 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x06 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +DATA 4 DDR_PHY_MR12_0 0x12 // VREF(CA) +DATA 4 DDR_PHY_MR14_0 0x10 // VREF(DQ) +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x00696159 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000493E0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000012C // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00007530 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00096 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// No ODT signal for LPDDR4 DQ. So disable it. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM, ACRANKCLKSEL +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode +DATA 4 DDR_PHY_ACIOCR1_0 0x00000000 // A[15:0] OE mode selection +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0x90032010 // tVREF, DVINIT, DVMIN, DVMAX, DVINIT +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO, tVREFIO, SHREN, SHRNK +// Set-up PHY General Configuration Registers +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 // Internal VREF generator range selection (1'b1 = 7.69% - 53.49% of VDDQ) +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09090913 // Set VREF value in DXREFISELR0, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090913 // Set VREF value in DXREFISELR0, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL, DXREFSSELRANGE, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL, DXREFSSELRANGE, maintain other defaults +// Set-up DATX8 DX Control Registers +DATA 4 DDR_PHY_DX8SLbDXCTL1_0 0x00840000 // DXRCLKMD +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1200 // POSOEX, PREOEX, LPWAKEUP_THRSH + +// Enable AC PHY PLL and/or IO to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x00190091 // LPWAKEUP_THRSH, LPPLLPD, LPIOPD + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM reset + DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM initialization +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// Wait DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch second DRAM initialization +DATA 4 DDR_PHY_PTR3_0 0x0000012C // tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 // Launch DRAM init + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +// Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Wait disabling of VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00000100 // BMRANK (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // DTRPTN, RFSHDT +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// VREF training +//---------------------------------------------------------------// +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +// Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//---------------------------------------------------------------// +// DQS Drift registers +//---------------------------------------------------------------// +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 // Disable Read DQS Gating LCDL Delay VT Compensation +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 // DFTDLY, DFTB2BRD, DFTIDLRD, DFTDTEN +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 // Disable Drift idle read cycle and Drift back-to-back read cycles +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 // DFTTHRSH, DFTMNTPRD + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +// Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +//---------------------------------------------------------------// +// Check that controller is ready to operate +//---------------------------------------------------------------// +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +//---------------------------------------------------------------// +// Configure ECC (if enable required) +//---------------------------------------------------------------// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//---------------------------------------------------------------// +// DRC configuration end +//---------------------------------------------------------------// + + + diff --git a/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_emul.cfg b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_emul.cfg new file mode 100755 index 0000000..098b4c2 --- /dev/null +++ b/platform/board/mx8dxl_evk/dcd/imx8dxl_dcd_emul.cfg @@ -0,0 +1,115 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +// DSC RESET +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + + // This is for lpddr4 controller 600MHz 1.67ns and ddr 1200MHz 0.83ns +DATA 4 DDRC_MSTR_0 0x83080020 // Set LPDDR4, BL = 16 and active ranks = 2 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x00020010 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00100000 // dram_rstn = 20us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1=0x44: nWR=24 ? BL=16; MR2=0x24: RL=24 WL=12 ? +DATA 4 DDRC_INIT4_0 0x00310000 // MR3, MR13 PDDS 110 PU-CAL VddQ/3 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr roundup((WL 12 + BL/2 8 + nWR 18ns)/2) = 20 hex 14 , tFAW (40ns /2) 25 hex 19 , tRASmax 8.7885us 4 , tRASmin 42ns (42ns/tCK)/2 26 hex 19 +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP 7.5ns roundup(tXP/2) 4, rd2pre roundup((BL/2 +8ns - 8)/2) = 5 , tRC 42ns +21ns roundup(63ns/2) = 38 hex +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL 12/2, RL 24/2, rd2wr roundup((RL 24 +BL/2 8 +RU tDQSCK 3.6ns/0.83ns 4.3 +WR_PREAMBLE 2tck + RD_POSTAMBLE 0.5tck -WL 12)/2) = 14, wr2rd RU(WL 12 +BL/2 8+tWTR 10ns +1)/2 17 hex +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw tMRW ? tMRWCKEL 10CK, tmrd 10tck, tmod present on DDR3/4 only +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd 18ns 11, tccd 8tck, trrd 10ns 7, trp 21ns 13 +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tcksrx 3tck, tcksre 5tck, tckesr 7.5ns tSR TBD, tcke 7.5/0.83/2 +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx 7.5ns +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde 5tck, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE 3tck, tCKEHCMD (=tXP?) ? +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff ODT disable, tCCDMW 4*8tck 16, tPPD 4tCK +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr tRFCAB 180ns+ 7.5ns +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL 1us, tZQLAT 30ns 18 +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset 50ns f, tzq_short_interval 0.4s lpddr3 ? +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000017 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP4_0 0x00001f1f // addrmap_col_b11, addrmap_col_b10 +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ADDRMAP7_0 0x00000f0f + +DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// Toggle Reset ... +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + + //Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// dram_init_inst() +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000021 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 + + //Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 diff --git a/platform/board/mx8dxl_evk/dcd/imx8dxl_ddr3l_dcd_933MHz.cfg b/platform/board/mx8dxl_evk/dcd/imx8dxl_ddr3l_dcd_933MHz.cfg new file mode 100755 index 0000000..709a194 --- /dev/null +++ b/platform/board/mx8dxl_evk/dcd/imx8dxl_ddr3l_dcd_933MHz.cfg @@ -0,0 +1,385 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x020000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 12 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80000800 +DEFINE BD_DDR_RET_REGION2_SIZE 12 + +/* + * Device Configuration Data (DCD) Version 1.0 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +// DXL default is 933MHz, hence when configured for 933MHz, the following is commented. It is uncommented when configured for 800MHz operation. +//if (rom_caller == SC_FALSE) +//{ +// /* Set the DRC rate to achieve a DRAM rate as close as possible to 933MHz. */ +// uint32_t rate2 = 465000000U; +// (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +//} +//else +//{ +// /* gate the cslice and ssslice */ +// CLR_BIT 4 0x41C83800 0xDC000000 +// CLR_BIT 4 0x41C82C00 0xDC00001F +// +// /* relock HP PLL to 930MHz */ +// /* Enable PLL isolation */ +// DSC_AIRegisterWrite(0x24,0,8,0x40000000); +// /* power down PLL and clear dividers */ +// DSC_AIRegisterWrite(0x24,0,8,0x000020FF); +// /* Set the divider */ +// DSC_AIRegisterWrite(0x24,0,4,0x0000009B); +// /* power up PLL and set hold ring off */ +// DSC_AIRegisterWrite(0x24,0,4,0x00003000); +// SYSCTR_TimeDelay(25); +// /* clear hold ring off */ +// DSC_AIRegisterWrite(0x24,0,8,0x00001000); +// SYSCTR_TimeDelay(50); +// /* disable PLL isolation */ +// DSC_AIRegisterWrite(0x24,0,4,0x40000000); +// +// /* Ungate cslice and ssslice */ +// SET_BIT 4 0x41C82C00 0x4C000002 +// SET_BIT 4 0x41C83800 0x4C000000 +//} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +//------------------------------------------- +// Configure controller registers +// Timings are computed for 933MHz DRAM operation +//-------------------------------------------- +DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x0072007A // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300E5 // pre_cke +DATA 4 DDRC_INIT1_0 0x005D0000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0E140046 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00200000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x000B0000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0E112010 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000C0417 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x07020307 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x05050303 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40960026 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200E3F5 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04898206 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000704 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00040401 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP2_0 0x00000700 // addrmap_col_b5, addrmap_col_b4, addrmap_col_b3, addrmap_col_b2 +DATA 4 DDRC_ADDRMAP3_0 0x12121200 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x04040403 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0F040404 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ODTCFG_0 0x06000610 +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// Performance optimizations +DATA 4 DDRC_SCHED_0 0x00001F05 // lpr_num_entries + +// Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x07009100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config +// DDR power management settings +DATA 4 DDRC_PWRTMG_0 0x00402010 // Timers for automatic entry into powerdown, self-refresh, … +DATA 4 DDRC_PWRCTL_0 0x0000000A // Enable DDR low power feature (clock disabling, power down, …) +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + + + + + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 933MHz DRAM operation +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00053210 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004876 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0E207 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x3A61D310 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x2D98106A // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus or when ECC disabled + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x00007799 // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x00007B99 // Impedance control for DQ bus + +//------------------------------------------- +// Configure and launch PLL init, DCAL, ZCAL and PHYRST +//-------------------------------------------- +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000E14 +DATA 4 DDR_PHY_MR1_0 0x00000046 +DATA 4 DDR_PHY_MR2_0 0x00000020 +DATA 4 DDR_PHY_MR3_0 0x00000000 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x06200D08 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28210300 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x00F30C17 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x002D0D09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00071FA6 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x000000F3 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0002D976 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x040003A6 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up PHY General Configuration Registers +DATA 4 DDR_PHY_PGCR5_0 0x01010004 +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 + +// Enable AC PHY PLL and/or IO to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x00190091 // LPWAKEUP_THRSH, LPPLLPD, LPIOPD + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM reset + DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +// Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +//---------------------------------------------------------------// +// Check that controller is ready to operate +//---------------------------------------------------------------// +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +//---------------------------------------------------------------// +// Configure ECC (if enable required) +//---------------------------------------------------------------// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//---------------------------------------------------------------// +// DRC configuration end +//---------------------------------------------------------------// + diff --git a/platform/board/mx8qm_mek/Makefile b/platform/board/mx8qm_mek/Makefile new file mode 100755 index 0000000..1c37faf --- /dev/null +++ b/platform/board/mx8qm_mek/Makefile @@ -0,0 +1,61 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8qm_dcd_emul +else + DDR_CON ?= imx8qm_dcd_1.6GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + +ifeq ($(M),1) + OBJS += $(OUT)/board/pmic.o +endif + diff --git a/platform/board/mx8qm_mek/board.bom b/platform/board/mx8qm_mek/board.bom new file mode 100755 index 0000000..6879226 --- /dev/null +++ b/platform/board/mx8qm_mek/board.bom @@ -0,0 +1,40 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf8100 + +ifeq ($(M),1) + DRV2 += pmic/pf100 +endif + diff --git a/platform/board/mx8qm_mek/board.c b/platform/board/mx8qm_mek/board.c new file mode 100755 index 0000000..1983876 --- /dev/null +++ b/platform/board/mx8qm_mek/board.c @@ -0,0 +1,1946 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QM MEK board. + * + * @addtogroup MX8QM_MEK_BRD BRD: MX8QM MEK Board + * + * Module for MX8QM MEK board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00090 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "drivers/systick/fsl_systick.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" + +/* Local Defines */ + +/*! Memory size */ +#ifndef BD_DDR_SIZE + #define BD_DDR_SIZE SC_6GB +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_PMIC_1 1U +#define BRD_R_BOARD_PMIC_2 2U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U /*!< EMVSIM */ +#define BRD_R_BOARD_R3 6U /*!< USDHC2 on Base board */ +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 3 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif +#if DEBUG_UART == 2 + /*! Use alternate debug UART */ + #define ALT_DEBUG_SCU_UART +#endif +#if (defined(MONITOR) || defined(EXPORT_MONITOR) || defined(HAS_TEST) \ + || (DEBUG_UART == 1)) && !defined(DEBUG_TERM_EMUL) \ + && !defined(ALT_DEBUG_SCU_UART) + #define ALT_DEBUG_UART +#endif + +/*! Configure debug UART */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG LPUART_SC +#else + #define LPUART_DEBUG LPUART_MCU_0 +#endif + +/*! Configure debug UART instance */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG_INST 0U +#else + #define LPUART_DEBUG_INST 2U +#endif + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +static sc_err_t pmic_ignore_current_limit(uint8_t address); +static sc_err_t pmic_update_timing(uint8_t address); +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver); +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t temp_alarm0; +static uint32_t temp_alarm1; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + /*rgpio_pin_config_t config; + config.pinDirection = kRGPIO_DigitalOutput;*/ + + ss_print(3, "board_init(%d)\n", phase); + + /*if (phase == BOOT_PHASE_HW_INIT) + { + #ifndef ALT_DEBUG_SCU_UART + pad_force_mux(SC_P_SCU_GPIO0_01, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + #endif*/ + /*pad_force_mux(SC_P_SCU_GPIO0_02, 0, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF);*/ + + /* Toggle base board reset SC_GPIO_01, >= 30nS */ + /*config.outputLogic = 0U; + FGPIO_PinInit(FGPIOA, 1U, &config); + SYSTICK_CycleDelay(SC_SYSTICK_NSEC_TO_TICKS(30U) + 1U); + FGPIO_PinWrite(FGPIOA, 1U, 1U);*/ + + /* SCU_LED on SC_GPIO_02 */ + /*config.outputLogic = 1U; + FGPIO_PinInit(FGPIOA, 2U, &config); + + SystemTimeDelay(2U); + } + else if (phase == BOOT_PHASE_FINAL_INIT)*/ + if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #if (defined(ALT_DEBUG_UART) || defined(ALT_DEBUG_SCU_UART)) \ + && !defined(DEBUG_TERM_EMUL) + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(ALT_DEBUG_SCU_UART) && !defined(DEBUG_TERM_EMUL) \ + && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Check if debug disabled */ + if (SCFW_DBG_READY == 0U) + { + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + } + #elif defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Use M4 UART if ALT_DEBUG_UART defined */ + /* Return if debug already enabled */ + if ((SCFW_DBG_READY == 0U) && (early_phase == SC_FALSE)) + { + sc_pm_clock_rate_t rate = SC_24MHZ; + static sc_bool_t banner = SC_FALSE; + + /* Configure pads */ + pad_force_mux(SC_P_M40_I2C0_SDA, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M40_I2C0_SCL, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M41_I2C0_SDA, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M41_I2C0_SCL, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + + /* Power and enable clock */ + pm_force_resource_power_mode_v(SC_R_SC_PID0, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DBLOGIC, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DB, SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + pm_force_resource_power_mode_v(SC_R_M4_1_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_1_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_1_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + + /* Configure UART */ + main_config_debug_uart(LPUART_DEBUG, rate); + + if (banner == SC_FALSE) + { + debug_print(1, + "\nHello from SCU (Build %u, Commit %08x, %s %s)\n\n", + SCFW_BUILD, SCFW_COMMIT, SCFW_DATE, SCFW_TIME); + banner = SC_TRUE; + } + } + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ + /* Use M4 UART if ALT_DEBUG_UART defined */ + #if defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Return if debug already disabled */ + if (SCFW_DBG_READY != 0U) + { + /* Disable use of UART */ + SCFW_DBG_READY = 0U; + + // UART deinit to flush TX buffers + LPUART_Deinit(LPUART_DEBUG); + + /* Turn off UART */ + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_OFF); + pm_force_resource_power_mode_v(SC_R_M4_1_UART, + SC_PM_PW_MODE_OFF); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + #ifdef ALT_DEBUG_UART + (void) rm_set_resource_movable(SC_PT, SC_R_M4_0_UART, SC_R_M4_0_UART, + SC_FALSE); + (void) rm_set_pad_movable(SC_PT, SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA, + SC_FALSE); + #endif + + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SDA, SC_P_PMIC_I2C_SCL, + SC_FALSE); + #ifdef ALT_DEBUG_SCU_UART + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_EXTERNAL; + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + rtn = BOARD_KS1_RESUME_USEC; + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + /* DC0 PLL0 spread spectrum config */ + case BOARD_PARM_DC0_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC0 PLL1 spread spectrum config */ + case BOARD_PARM_DC0_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL0 spread spectrum config */ + case BOARD_PARM_DC1_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL1 spread spectrum config */ + case BOARD_PARM_DC1_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* Control if SC WDOG configuration during KS1 */ + case BOARD_PARM_KS1_WDOG_WAKE: + rtn = BOARD_PARM_KS1_WDOG_WAKE_ENABLE; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. - DDR_00060 */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + #if defined(BD_DDR_RET_NUM_DRC) && (BD_DDR_RET_NUM_DRC == 1U) + if(rsrc == SC_R_DRC_1) + { + rtn = SC_FALSE; + } + #endif + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + static uint32_t board_ddr_ret_buf4[BD_DDR_RET_REGION4_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + static uint32_t board_ddr_ret_buf5[BD_DDR_RET_REGION5_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + static uint32_t board_ddr_ret_buf6[BD_DDR_RET_REGION6_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 }, + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + { BD_DDR_RET_REGION4_ADDR, BD_DDR_RET_REGION4_SIZE, board_ddr_ret_buf4 }, + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + { BD_DDR_RET_REGION5_ADDR, BD_DDR_RET_REGION5_SIZE, board_ddr_ret_buf5 }, + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + { BD_DDR_RET_REGION6_ADDR, BD_DDR_RET_REGION6_SIZE, board_ddr_ret_buf6 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + else if (rm_is_resource_avail(SC_R_DRC_1)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_1, + SC_PM_CLK_SLV_BUS, &rate); + } + else + { + ; /* Intentional empty else */ + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + /* DDR_00040 */ + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. See DDR_00010. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + /* Supports stress test tool - DDR_00070 */ + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + case BOARD_DDR1_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(1); + #else + // Run vref training + DRAM_VREF_training_sw(1); + #endif + break; + default: + /* DDR_00020 */ + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + sc_rm_pt_t pt_m4_1 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[7U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_7A, + SC_R_MU_8B, + SC_R_GPT_4, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x0887FFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Create M4 1 partition */ + if (rm_is_resource_avail(SC_R_M4_1_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[5U] = + { + SC_R_IRQSTR_M4_1, + SC_R_MU_6B, + SC_R_MU_7B, + SC_R_MU_9B, + SC_R_GPT_3, + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M41_I2C0_SCL, SC_P_M41_I2C0_SDA), + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088800000ULL, 0x08FFFFFFFULL}, + {0x008181000ULL, 0x008280FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_1, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_1_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_1, "MCU1"); + + /* Allow M4 1 to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_m4_1, SC_RM_PERM_SEC_RW)); + + /* Move M4 1 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x038FE0000ULL, + 0x038FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_1, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_1, SC_PT)); + } + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[4U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4), + RM_RANGE(SC_R_M4_1_PID1, SC_R_M4_1_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + if (pt_m4_1 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_1, + SC_RM_PERM_FULL)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_1_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + SW_RUN_PWM | SW_STBY_PWM)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + SW_RUN_OFF)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(pmic_id[idx], pmic_reg[idx], new_volt, + REG_RUN_MODE)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ + static uint32_t vdd_memc_mode = 0U; + + if (mode == SC_PM_PW_MODE_STBY) + { + /* + * System standby (KS1) entry allows VDD_MEMC to be gated off. + * Save current mode and switch off supply. + */ + if (PMIC_GET_MODE(PMIC_1_ADDR, PF8100_SW5, &vdd_memc_mode) + == SC_ERR_NONE) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, SW_STBY_OFF + | SW_RUN_OFF); + } + } + else if (mode == SC_PM_PW_MODE_ON) + { + /* + * System standby (KS1) exit should switch on VDD_MEMC. Restore + * previous mode saved during KS1 entry. + */ + if (vdd_memc_mode != 0U) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, vdd_memc_mode); + } + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + switch (idx) + { + case BRD_R_BOARD_R2 : /* EMVSIM */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_LDO1, + 3000, REG_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_EN_STBY_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_OFF_STBY_OFF)); + } + break; + case BRD_R_BOARD_R3 : /* USDHC2 on Base Board */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_EN_STBY_EN | VSELECT_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_OFF_STBY_OFF)); + } + break; + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + ; /* Intentional empty default */ + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + #endif + #ifdef ALT_DEBUG_UART + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if ((resource == SC_R_M4_0_PID0) || (resource == SC_R_M4_1_PID0)) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm0 = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm1 = + SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + /* PMIC 0 */ + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm0; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* PMIC 1 */ + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_1_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm1; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_1_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* Board R7 - only here for testing */ + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Temp alarm from PMIC 1 */ + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC1_HIGH, + SC_PT_ALL); + } + /* Temp alarm from PMIC 0 */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC0_HIGH, + SC_PT_ALL); + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + + /* MEK board spec is for 1M baud for PMIC I2C bus */ + lpi2c_masterConfig.baudRate_Hz = 1000000U; + lpi2c_masterConfig.sdaGlitchFilterWidth_ns = 100U; + lpi2c_masterConfig.sclGlitchFilterWidth_ns = 100U; + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + + err |= pmic_ignore_current_limit(PMIC_0_ADDR); + err |= pmic_ignore_current_limit(PMIC_1_ADDR); + + /* Adjust startup timing */ + err |= pmic_update_timing(PMIC_0_ADDR); + err |= pmic_update_timing(PMIC_1_ADDR); + + err |= pmic_match_otp(PMIC_0_ADDR, pmic_ver); + err |= pmic_match_otp(PMIC_1_ADDR, pmic_ver); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + err |= pf8100_pmic_wdog_enable(PMIC_1_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + + if (err != SC_ERR_NONE) + { + /* Loop so WDOG will expire */ + HALT; + } + + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW7, SW_RUN_PWM + | SW_STBY_PWM)); + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, 800, + REG_STBY_MODE)); + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + val |= 0x20U; /* set xx_ILIM_BYPASS */ + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update power timing for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_update_timing(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + + /* + * Add 60ms stable time for power down for: + * PMIC 1 : LDO2, SW6, SW7 + * PMIC 2 : LDO2, SW5, SW6, SW7 + * on i.mx8QM-mek + * board, otherwise system may reboot fail by mmc not power off + * clean + */ + if (address == PMIC_0_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 0 */ + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else if (address == PMIC_1_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 1 */ + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x6F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else + { + /* Return error */ + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check correct version of OTP for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver) +{ + uint8_t reg_value = 0U; + uint16_t prog_id, match; + sc_err_t err = SC_ERR_NONE; + + if (address == PMIC_0_ADDR) + { + match = EP_PROG_ID; + } + else + { + match = EQ_PROG_ID; + } + + /* Read Prog ID */ + err |= PMIC_REGISTER_ACCESS(address, 0x2, SC_FALSE, ®_value); + prog_id = (((uint16_t)reg_value << 4U) & 0x0F00U); + err |= PMIC_REGISTER_ACCESS(address, 0x3U, SC_FALSE, ®_value); + prog_id |= reg_value; + + /* test against calibration fusing */ + if (OTP_PROG_FUSE_VERSION_1_7V_CAL != 0U) + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + /* if C1 PMIC test for correct OTP */ + if(prog_id != match){/* allow only 1.7v OTP */ + error_print("PMIC INVALID!\n"); + } + } + else + { + error_print("PMIC INVALID!\n"); + } + } + else + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + if(prog_id == match){/* prohibit only 1.7V OTP */ + error_print("PMIC INVALID!\n"); + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A53 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW5; + *num_regs = 1U; + } + break; + case SC_SUBSYS_A72 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW1; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW2; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_1 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + default : + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qm_mek/board.h b/platform/board/mx8qm_mek/board.h new file mode 100755 index 0000000..841c97a --- /dev/null +++ b/platform/board/mx8qm_mek/board.h @@ -0,0 +1,115 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC pf8100 +#define PMIC_0_ADDR 0x8U +#define PMIC_1_ADDR 0x9U + +#define PF8100_C1_SI_REV 0x31U +#define EP_PROG_ID 0x0417U +#define EQ_PROG_ID 0x0418U + +#define PMIC_TEMP_MAX 135U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qm_mek/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qm_mek/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..896973b --- /dev/null +++ b/platform/board/mx8qm_mek/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,143 @@ +DEFINE BD_DDR_RET_NUM_DRC 2 // Number of DRCs in the SoC + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_mek/dcd/ddr_stress_test_parser_DRC0_only.cfg b/platform/board/mx8qm_mek/dcd/ddr_stress_test_parser_DRC0_only.cfg new file mode 100755 index 0000000..119af25 --- /dev/null +++ b/platform/board/mx8qm_mek/dcd/ddr_stress_test_parser_DRC0_only.cfg @@ -0,0 +1,142 @@ +DEFINE BD_DDR_RET_NUM_DRC 1 // One DRC in the SoC; DRC0 only + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_mek/dcd/imx8qm_dcd_1.6GHz.cfg b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_1.6GHz.cfg new file mode 100755 index 0000000..cb0c950 --- /dev/null +++ b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_1.6GHz.cfg @@ -0,0 +1,590 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x03201901 +DATA 4 DDR_PHY_PTR1_0 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x03201901 +DATA 4 DDR_PHY_PTR1_1 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00032 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00032 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x64032010, 0x4E201C20, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_mek/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg new file mode 100755 index 0000000..eb1ae49 --- /dev/null +++ b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg @@ -0,0 +1,513 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_1 0x00808000 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------=------------ +// Set-up DRAM 1 PHY Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_1 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x33 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF +DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x03300640 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x03300640 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 +// Launch DRAM 1 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch a second time DRAM initialization due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait (second time) DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_mek/dcd/imx8qm_dcd_800MHz.cfg b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_800MHz.cfg new file mode 100755 index 0000000..0fc3ead --- /dev/null +++ b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_800MHz.cfg @@ -0,0 +1,624 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to 800MHz. */ + uint32_t rate2 = SC_400MHZ; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2); +} +else +{ +/* Change to div4 output */ +DATA 4 0x41A43800 0x4C000000 +DATA 4 0x41D03800 0x4C000000 +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_0 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_1 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x01A00C81 +DATA 4 DDR_PHY_PTR1_0 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x01A00C81 +DATA 4 DDR_PHY_PTR1_1 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00019 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00019 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x32019010, 0x27100E10, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + + + + + + + + + + + + + + + + + + + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + diff --git a/platform/board/mx8qm_mek/dcd/imx8qm_dcd_emul.cfg b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_emul.cfg new file mode 100755 index 0000000..26e3098 --- /dev/null +++ b/platform/board/mx8qm_mek/dcd/imx8qm_dcd_emul.cfg @@ -0,0 +1,214 @@ +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// Reset Should not be needed for ZEBU. +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 + +// ddrc_lpddr4_init(0) +DATA 4 0x5C000000 0xC3080020 +DATA 4 0x5C000064 0x006100E0 +DATA 4 0x5C0000D0 0x40020010 +DATA 4 0x5C0000D4 0x00100000 +DATA 4 0x5C0000DC 0x0054002D +DATA 4 0x5C0000E0 0x00310000 +DATA 4 0x5C0000F4 0x000006CF +DATA 4 0x5C000100 0x1A201B22 +DATA 4 0x5C000104 0x00060633 +DATA 4 0x5C000108 0x070E1014 +DATA 4 0x5C00010C 0x0170C00C +DATA 4 0x5C000110 0x0F04080F +DATA 4 0x5C000114 0x03040C0C +DATA 4 0x5C000118 0x02020007 +DATA 4 0x5C00011C 0x00000401 +DATA 4 0x5C000130 0x00020610 +DATA 4 0x5C000134 0x0C100002 +DATA 4 0x5C000138 0x000000E6 +DATA 4 0x5C000180 0x03200018 +DATA 4 0x5C000184 0x02800100 +DATA 4 0x5C000190 0x049C820C +DATA 4 0x5C000194 0x00060303 +DATA 4 0x5C0001B4 0x00001A0A +DATA 4 0x5C0001B0 0x00000005 +DATA 4 0x5C0001A0 0x80400003 +DATA 4 0x5C0001A4 0x00010002 +DATA 4 0x5C0001A8 0x80000000 +DATA 4 0x5C000200 0x00000017 +DATA 4 0x5C000204 0x00080808 +DATA 4 0x5C000214 0x07070707 +DATA 4 0x5C000218 0x07070707 +DATA 4 0x5C000244 0x00002211 +DATA 4 0x5C000490 0x00000001 +DATA 4 0x5C002190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 +//DATA 4 0x5C0001B0 0x00000004 +//DATA 4 0x5C0000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(0) +DATA 4 0x5C010100 0x0000040D +DATA 4 0x5C010018 0x00F0DA09 +DATA 4 0x5C01001C 0x050A1080 +DATA 4 0x5C010040 0x64032010 +DATA 4 0x5C010044 0x0D701C20 +DATA 4 0x5C010068 0x08000000 +DATA 4 0x5C0117C4 0x08000000 +DATA 4 0x5C010680 0x001FEC58 + +//ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00000040 +DATA 4 0x5C010004 0x00000041 + +//ddr_phy_lpddr4_dram_init(0) +DATA 4 0x5C010184 0x00000054 +DATA 4 0x5C010188 0x0000002D +DATA 4 0x5C01018C 0x00000031 +DATA 4 0x5C010110 0x1044220C +DATA 4 0x5C010114 0x28408C17 +DATA 4 0x5C010118 0x003C01CC +DATA 4 0x5C01011C 0x01800604 +DATA 4 0x5C010120 0x01C0000C +DATA 4 0x5C010124 0x00651D10 +DATA 4 0x5C01004C 0x00007D00 +DATA 4 0x5C010050 0x00000C90 +DATA 4 0x5C010054 0x00007D00 +DATA 4 0x5C010058 0x03000641 +DATA 4 0x5C010500 0x30070800 +DATA 4 0x5C010514 0x09000000 +DATA 4 0x5C010528 0xF0032019 +DATA 4 0x5C01052C 0x07F00173 +DATA 4 0x5C0117EC 0x00081800 +DATA 4 0x5C0117F0 0x09000000 +DATA 4 0x5C0117DC 0x013E4091 + +//ddr_phy_wait_init_done(0) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00040000 +DATA 4 0x5C010004 0x00040001 + +// SECOND DRC SYSTEM + +// ddrc_lpddr4_init(1) +DATA 4 0x5C100000 0xC3080020 +DATA 4 0x5C100064 0x006100E0 +DATA 4 0x5C1000D0 0x40020010 +DATA 4 0x5C1000D4 0x00100000 +DATA 4 0x5C1000DC 0x0054002D +DATA 4 0x5C1000E0 0x00310000 +DATA 4 0x5C1000F4 0x000006CF +DATA 4 0x5C100100 0x1A201B22 +DATA 4 0x5C100104 0x00060633 +DATA 4 0x5C100108 0x070E1014 +DATA 4 0x5C10010C 0x0170C00C +DATA 4 0x5C100110 0x0F04080F +DATA 4 0x5C100114 0x03040C0C +DATA 4 0x5C100118 0x02020007 +DATA 4 0x5C10011C 0x00000401 +DATA 4 0x5C100130 0x00020610 +DATA 4 0x5C100134 0x0C100002 +DATA 4 0x5C100138 0x000000E6 +DATA 4 0x5C100180 0x03200018 +DATA 4 0x5C100184 0x02800100 +DATA 4 0x5C100190 0x049C820C +DATA 4 0x5C100194 0x00060303 +DATA 4 0x5C1001B4 0x00001A0A +DATA 4 0x5C1001B0 0x00000005 +DATA 4 0x5C1001A0 0x80400003 +DATA 4 0x5C1001A4 0x00010002 +DATA 4 0x5C1001A8 0x80000000 +DATA 4 0x5C100200 0x00000017 +DATA 4 0x5C100204 0x00080808 +DATA 4 0x5C100214 0x07070707 +DATA 4 0x5C100218 0x07070707 +DATA 4 0x5C100244 0x00002211 +DATA 4 0x5C100490 0x00000001 +DATA 4 0x5C102190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_1 0x00000001 +CLR_BIT 4 DDRC_INIT0_1 0xC0000000 +//DATA 4 0x5C1001B0 0x00000004 +//DATA 4 0x5C1000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(1) +DATA 4 0x5C110100 0x0000040D +DATA 4 0x5C110018 0x00F0DA09 +DATA 4 0x5C11001C 0x050A1080 +DATA 4 0x5C110040 0x64032010 +DATA 4 0x5C110044 0x0D701C20 +DATA 4 0x5C110068 0x08000000 +DATA 4 0x5C1117C4 0x08000000 +DATA 4 0x5C110680 0x001FEC58 + +//ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00000040 +DATA 4 0x5C110004 0x00000041 + + +//ddr_phy_lpddr4_dram_init(1) +DATA 4 0x5C110184 0x00000054 +DATA 4 0x5C110188 0x0000002D +DATA 4 0x5C11018C 0x00000031 +DATA 4 0x5C110110 0x1044220C +DATA 4 0x5C110114 0x28408C17 +DATA 4 0x5C110118 0x003C01CC +DATA 4 0x5C11011C 0x01800604 +DATA 4 0x5C110120 0x01C0000C +DATA 4 0x5C110124 0x00651D10 +DATA 4 0x5C11004C 0x00007D00 +DATA 4 0x5C110050 0x00000C90 +DATA 4 0x5C110054 0x00007D00 +DATA 4 0x5C110058 0x03000641 +DATA 4 0x5C110500 0x30070800 +DATA 4 0x5C110514 0x09000000 +DATA 4 0x5C110528 0xF0032019 +DATA 4 0x5C11052C 0x07F00173 +DATA 4 0x5C1117EC 0x00081800 +DATA 4 0x5C1117F0 0x09000000 +DATA 4 0x5C1117DC 0x013E4091 + +//ddr_phy_wait_init_done(1) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00040000 +DATA 4 0x5C110004 0x00040001 + +// RESET +DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DSC_SetReset(SC_DSC_DRC_1, BIT(RST_DDR_CRESETN), SC_TRUE); +//DATA 4 0x41a40044 0x4 +//DATA 4 0x41d00044 0x4 + +// dram_init_inst(0) +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// dram_init_inst(1) +CLR_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_1 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_1 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +//DATA 4 0x5C000320 0x00000000 +//DATA 4 0x5C0001B0 0x00000005 +//DATA 4 0x5C000320 0x00000001 +//DATA 4 0x5C100320 0x00000000 +//DATA 4 0x5C1001B0 0x00000005 +//DATA 4 0x5C100320 0x00000001 + diff --git a/platform/board/mx8qm_smarc_4g/Makefile b/platform/board/mx8qm_smarc_4g/Makefile new file mode 100755 index 0000000..1c37faf --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/Makefile @@ -0,0 +1,61 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8qm_dcd_emul +else + DDR_CON ?= imx8qm_dcd_1.6GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + +ifeq ($(M),1) + OBJS += $(OUT)/board/pmic.o +endif + diff --git a/platform/board/mx8qm_smarc_4g/board.bom b/platform/board/mx8qm_smarc_4g/board.bom new file mode 100755 index 0000000..6879226 --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/board.bom @@ -0,0 +1,40 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf8100 + +ifeq ($(M),1) + DRV2 += pmic/pf100 +endif + diff --git a/platform/board/mx8qm_smarc_4g/board.c b/platform/board/mx8qm_smarc_4g/board.c new file mode 100755 index 0000000..e29ab97 --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/board.c @@ -0,0 +1,2007 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QM MEK board. + * + * @addtogroup MX8QM_MEK_BRD BRD: MX8QM MEK Board + * + * Module for MX8QM MEK board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00090 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "drivers/systick/fsl_systick.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" + +/* ------------------------------------------------------------------------------------------------------------------ + * ----- iMX8QM: eDMA limitation USE CASE ----- + * ------------------------------------------------------------------------------------------------------------------ + * In the new kernel NXP use the "edma2" in the lpspi driver. The same dma controller is used from M core in FreeRTOS + * This generate a conflict and than a kernel crash + * ------------------------------------------------------------------------------------------------------------------ + * To add a clarification regarding eDMA: + * - The "edma2" node in the Linux device tree refers to the device at BAR 0x5a1f0000 described in the DMA memory map + * as "eDMA0" (i.MX 8QuadMax reference manual rev.F pp.32) + * - DMA0_BASE in imx-sc-firmware/src/scfw_export_mx8qm_b0/platform/devices/MX8QM/MX8QM.h also points to the + * RM's "eDMA0" at 0x5a1f0000. + * This confirms the eDMA conflict. + * + * How to use use eDMA0 in the FreeRTOS: + * - USE_DMA_0 must be defined + * - eDMA0 must be disabled in the Linux device tree overriding the nodes that use "edma2" or disabling the nodes + * that using it + * ------------------------------------------------------------------------------------------------------------------ + * The eDMA conflict affect the below FreeRTOS examples: + * - lpspi_edma_b2b_transfer_master.c + * - lpspi_edma_b2b_transfer_slave.c + * - lpuart_edma_transfer.c + * - edma_memory_to_memory.c + * - edma_scatter_gather.c + * - cmsis_usart_edma_transfer.c + * ------------------------------------------------------------------------------------------------------------------ + */ + +/* Local Defines */ + +#undef USE_DMA_0 /* Before define USE_DMA_0, read "iMX8QM: eDMA limitation USE CASE" above */ + +#undef M41_USES_SPI0 +#undef M41_USES_I2C3 +#undef M41_USES_GPIO3_24 +#undef M41_USES_CAN0 +#undef M41_USES_EDMA + +#ifndef USE_DMA_0 + #undef M41_USES_EDMA +#endif + +/*! Memory size */ +#ifndef BD_DDR_SIZE + #define BD_DDR_SIZE SC_4GB +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_PMIC_1 1U +#define BRD_R_BOARD_PMIC_2 2U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U /*!< EMVSIM */ +#define BRD_R_BOARD_R3 6U /*!< USDHC2 on Base board */ +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 3 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif +#if DEBUG_UART == 2 + /*! Use alternate debug UART */ + #define ALT_DEBUG_SCU_UART +#endif +#if (defined(MONITOR) || defined(EXPORT_MONITOR) || defined(HAS_TEST) \ + || (DEBUG_UART == 1)) && !defined(DEBUG_TERM_EMUL) \ + && !defined(ALT_DEBUG_SCU_UART) + #define ALT_DEBUG_UART +#endif + +/*! Configure debug UART */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG LPUART_SC +#else + #define LPUART_DEBUG LPUART_MCU_0 +#endif + +/*! Configure debug UART instance */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG_INST 0U +#else + #define LPUART_DEBUG_INST 2U +#endif + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +static sc_err_t pmic_ignore_current_limit(uint8_t address); +static sc_err_t pmic_update_timing(uint8_t address); +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver); +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t temp_alarm0; +static uint32_t temp_alarm1; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + /*rgpio_pin_config_t config; + config.pinDirection = kRGPIO_DigitalOutput;*/ + + ss_print(3, "board_init(%d)\n", phase); + + /*if (phase == BOOT_PHASE_HW_INIT) + { + #ifndef ALT_DEBUG_SCU_UART + pad_force_mux(SC_P_SCU_GPIO0_01, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + #endif*/ + /*pad_force_mux(SC_P_SCU_GPIO0_02, 0, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF);*/ + + /* Toggle base board reset SC_GPIO_01, >= 30nS */ + /*config.outputLogic = 0U; + FGPIO_PinInit(FGPIOA, 1U, &config); + SYSTICK_CycleDelay(SC_SYSTICK_NSEC_TO_TICKS(30U) + 1U); + FGPIO_PinWrite(FGPIOA, 1U, 1U);*/ + + /* SCU_LED on SC_GPIO_02 */ + /*config.outputLogic = 1U; + FGPIO_PinInit(FGPIOA, 2U, &config); + + SystemTimeDelay(2U); + } + else if (phase == BOOT_PHASE_FINAL_INIT)*/ + if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #if (defined(ALT_DEBUG_UART) || defined(ALT_DEBUG_SCU_UART)) \ + && !defined(DEBUG_TERM_EMUL) + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(ALT_DEBUG_SCU_UART) && !defined(DEBUG_TERM_EMUL) \ + && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Check if debug disabled */ + if (SCFW_DBG_READY == 0U) + { + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + } + #elif defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Use M4 UART if ALT_DEBUG_UART defined */ + /* Return if debug already enabled */ + if ((SCFW_DBG_READY == 0U) && (early_phase == SC_FALSE)) + { + sc_pm_clock_rate_t rate = SC_24MHZ; + static sc_bool_t banner = SC_FALSE; + + /* Configure pads */ + pad_force_mux(SC_P_M40_I2C0_SDA, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M40_I2C0_SCL, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M41_I2C0_SDA, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M41_I2C0_SCL, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + + /* Power and enable clock */ + pm_force_resource_power_mode_v(SC_R_SC_PID0, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DBLOGIC, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DB, SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + pm_force_resource_power_mode_v(SC_R_M4_1_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_1_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_1_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + + /* Configure UART */ + main_config_debug_uart(LPUART_DEBUG, rate); + + if (banner == SC_FALSE) + { + debug_print(1, + "\nHello from SCU (Build %u, Commit %08x, %s %s)\n\n", + SCFW_BUILD, SCFW_COMMIT, SCFW_DATE, SCFW_TIME); + banner = SC_TRUE; + } + } + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ + /* Use M4 UART if ALT_DEBUG_UART defined */ + #if defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Return if debug already disabled */ + if (SCFW_DBG_READY != 0U) + { + /* Disable use of UART */ + SCFW_DBG_READY = 0U; + + // UART deinit to flush TX buffers + LPUART_Deinit(LPUART_DEBUG); + + /* Turn off UART */ + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_OFF); + pm_force_resource_power_mode_v(SC_R_M4_1_UART, + SC_PM_PW_MODE_OFF); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + #ifdef ALT_DEBUG_UART + (void) rm_set_resource_movable(SC_PT, SC_R_M4_0_UART, SC_R_M4_0_UART, + SC_FALSE); + (void) rm_set_pad_movable(SC_PT, SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA, + SC_FALSE); + #endif + + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SDA, SC_P_PMIC_I2C_SCL, + SC_FALSE); + #ifdef ALT_DEBUG_SCU_UART + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_EXTERNAL; + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + rtn = BOARD_KS1_RESUME_USEC; + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + /* DC0 PLL0 spread spectrum config */ + case BOARD_PARM_DC0_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC0 PLL1 spread spectrum config */ + case BOARD_PARM_DC0_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL0 spread spectrum config */ + case BOARD_PARM_DC1_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL1 spread spectrum config */ + case BOARD_PARM_DC1_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* Control if SC WDOG configuration during KS1 */ + case BOARD_PARM_KS1_WDOG_WAKE: + rtn = BOARD_PARM_KS1_WDOG_WAKE_ENABLE; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. - DDR_00060 */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + #if defined(BD_DDR_RET_NUM_DRC) && (BD_DDR_RET_NUM_DRC == 1U) + if(rsrc == SC_R_DRC_1) + { + rtn = SC_FALSE; + } + #endif + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + static uint32_t board_ddr_ret_buf4[BD_DDR_RET_REGION4_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + static uint32_t board_ddr_ret_buf5[BD_DDR_RET_REGION5_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + static uint32_t board_ddr_ret_buf6[BD_DDR_RET_REGION6_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 }, + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + { BD_DDR_RET_REGION4_ADDR, BD_DDR_RET_REGION4_SIZE, board_ddr_ret_buf4 }, + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + { BD_DDR_RET_REGION5_ADDR, BD_DDR_RET_REGION5_SIZE, board_ddr_ret_buf5 }, + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + { BD_DDR_RET_REGION6_ADDR, BD_DDR_RET_REGION6_SIZE, board_ddr_ret_buf6 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + else if (rm_is_resource_avail(SC_R_DRC_1)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_1, + SC_PM_CLK_SLV_BUS, &rate); + } + else + { + ; /* Intentional empty else */ + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + /* DDR_00040 */ + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. See DDR_00010. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + /* Supports stress test tool - DDR_00070 */ + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + case BOARD_DDR1_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(1); + #else + // Run vref training + DRAM_VREF_training_sw(1); + #endif + break; + default: + /* DDR_00020 */ + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + sc_rm_pt_t pt_m4_1 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[7U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_7A, + SC_R_MU_8B, + SC_R_GPT_4, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x0887FFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Create M4 1 partition */ + if (rm_is_resource_avail(SC_R_M4_1_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[5U] = + { + SC_R_IRQSTR_M4_1, +#ifdef M41_USES_SPI0 +#ifdef USE_DMA_0 + SC_R_DMA_0_CH0, + SC_R_DMA_0_CH1, /* DMA0 channels for SPI0 */ +#endif + SC_R_SPI_0, +#endif +#ifdef M41_USES_I2C3 + SC_R_DMA_1_CH0, + SC_R_DMA_1_CH1, /* DMA1 channels for I2C3 */ + SC_R_I2C_3, +#endif +#ifdef M41_USES_GPIO3_24 + SC_R_GPIO_3, +#endif + SC_R_MU_6B, + SC_R_MU_7B, + SC_R_MU_9B, +#ifdef M41_USES_EDMA + SC_R_DMA_0_CH30, /* DMA0 channel for EDMA sample code */ +#endif +#ifdef M41_USES_CAN0 + SC_R_CAN_0, +#endif + SC_R_GPT_3, + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M41_I2C0_SCL, SC_P_M41_I2C0_SDA), + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088800000ULL, 0x08FFFFFFFULL}, + {0x008181000ULL, 0x008280FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_1, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_1_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_1, "MCU1"); + + /* Allow M4 1 to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_m4_1, SC_RM_PERM_SEC_RW)); + + /* Move M4 1 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x038FE0000ULL, + 0x038FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_1, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_1, SC_PT)); + } + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[4U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4), + RM_RANGE(SC_R_M4_1_PID1, SC_R_M4_1_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + if (pt_m4_1 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_1, + SC_RM_PERM_FULL)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_1_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + SW_RUN_PWM | SW_STBY_PWM)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + SW_RUN_OFF)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(pmic_id[idx], pmic_reg[idx], new_volt, + REG_RUN_MODE)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ + static uint32_t vdd_memc_mode = 0U; + + if (mode == SC_PM_PW_MODE_STBY) + { + /* + * System standby (KS1) entry allows VDD_MEMC to be gated off. + * Save current mode and switch off supply. + */ + if (PMIC_GET_MODE(PMIC_1_ADDR, PF8100_SW5, &vdd_memc_mode) + == SC_ERR_NONE) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, SW_STBY_OFF + | SW_RUN_OFF); + } + } + else if (mode == SC_PM_PW_MODE_ON) + { + /* + * System standby (KS1) exit should switch on VDD_MEMC. Restore + * previous mode saved during KS1 entry. + */ + if (vdd_memc_mode != 0U) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, vdd_memc_mode); + } + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + switch (idx) + { + case BRD_R_BOARD_R2 : /* EMVSIM */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_LDO1, + 3000, REG_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_EN_STBY_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_OFF_STBY_OFF)); + } + break; + case BRD_R_BOARD_R3 : /* USDHC2 on Base Board */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_EN_STBY_EN | VSELECT_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_OFF_STBY_OFF)); + } + break; + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + ; /* Intentional empty default */ + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + #endif + #ifdef ALT_DEBUG_UART + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if ((resource == SC_R_M4_0_PID0) || (resource == SC_R_M4_1_PID0)) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm0 = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm1 = + SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + /* PMIC 0 */ + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm0; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* PMIC 1 */ + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_1_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm1; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_1_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* Board R7 - only here for testing */ + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Temp alarm from PMIC 1 */ + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC1_HIGH, + SC_PT_ALL); + } + /* Temp alarm from PMIC 0 */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC0_HIGH, + SC_PT_ALL); + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + + /* MEK board spec is for 1M baud for PMIC I2C bus */ + lpi2c_masterConfig.baudRate_Hz = 1000000U; + lpi2c_masterConfig.sdaGlitchFilterWidth_ns = 100U; + lpi2c_masterConfig.sclGlitchFilterWidth_ns = 100U; + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + + err |= pmic_ignore_current_limit(PMIC_0_ADDR); + err |= pmic_ignore_current_limit(PMIC_1_ADDR); + + /* Adjust startup timing */ + err |= pmic_update_timing(PMIC_0_ADDR); + err |= pmic_update_timing(PMIC_1_ADDR); + + err |= pmic_match_otp(PMIC_0_ADDR, pmic_ver); + err |= pmic_match_otp(PMIC_1_ADDR, pmic_ver); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + err |= pf8100_pmic_wdog_enable(PMIC_1_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + + if (err != SC_ERR_NONE) + { + /* Loop so WDOG will expire */ + HALT; + } + + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW7, SW_RUN_PWM + | SW_STBY_PWM)); + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, 800, + REG_STBY_MODE)); + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + val |= 0x20U; /* set xx_ILIM_BYPASS */ + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update power timing for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_update_timing(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + + /* + * Add 60ms stable time for power down for: + * PMIC 1 : LDO2, SW6, SW7 + * PMIC 2 : LDO2, SW5, SW6, SW7 + * on i.mx8QM-mek + * board, otherwise system may reboot fail by mmc not power off + * clean + */ + if (address == PMIC_0_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 0 */ + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else if (address == PMIC_1_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 1 */ + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x6F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else + { + /* Return error */ + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check correct version of OTP for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver) +{ + uint8_t reg_value = 0U; + uint16_t prog_id, match; + sc_err_t err = SC_ERR_NONE; + + if (address == PMIC_0_ADDR) + { + match = EP_PROG_ID; + } + else + { + match = EQ_PROG_ID; + } + + /* Read Prog ID */ + err |= PMIC_REGISTER_ACCESS(address, 0x2, SC_FALSE, ®_value); + prog_id = (((uint16_t)reg_value << 4U) & 0x0F00U); + err |= PMIC_REGISTER_ACCESS(address, 0x3U, SC_FALSE, ®_value); + prog_id |= reg_value; + + /* test against calibration fusing */ + if (OTP_PROG_FUSE_VERSION_1_7V_CAL != 0U) + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + /* if C1 PMIC test for correct OTP */ + if(prog_id != match){/* allow only 1.7v OTP */ + error_print("PMIC INVALID!\n"); + } + } + else + { + error_print("PMIC INVALID!\n"); + } + } + else + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + if(prog_id == match){/* prohibit only 1.7V OTP */ + error_print("PMIC INVALID!\n"); + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A53 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW5; + *num_regs = 1U; + } + break; + case SC_SUBSYS_A72 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW1; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW2; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_1 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + default : + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qm_smarc_4g/board.h b/platform/board/mx8qm_smarc_4g/board.h new file mode 100755 index 0000000..841c97a --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/board.h @@ -0,0 +1,115 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC pf8100 +#define PMIC_0_ADDR 0x8U +#define PMIC_1_ADDR 0x9U + +#define PF8100_C1_SI_REV 0x31U +#define EP_PROG_ID 0x0417U +#define EQ_PROG_ID 0x0418U + +#define PMIC_TEMP_MAX 135U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qm_smarc_4g/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qm_smarc_4g/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..896973b --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,143 @@ +DEFINE BD_DDR_RET_NUM_DRC 2 // Number of DRCs in the SoC + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_smarc_4g/dcd/ddr_stress_test_parser_DRC0_only.cfg b/platform/board/mx8qm_smarc_4g/dcd/ddr_stress_test_parser_DRC0_only.cfg new file mode 100755 index 0000000..119af25 --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/dcd/ddr_stress_test_parser_DRC0_only.cfg @@ -0,0 +1,142 @@ +DEFINE BD_DDR_RET_NUM_DRC 1 // One DRC in the SoC; DRC0 only + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_1.6GHz.cfg b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_1.6GHz.cfg new file mode 100644 index 0000000..54c4006 --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_1.6GHz.cfg @@ -0,0 +1,593 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x100000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 4 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 + + +DEFINE BD_DDR_RET_REGION3_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION3_SIZE 64 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION4_SIZE 16 + + + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 // Gate functional clocks +DATA 4 0x41d00208 0x1 // Gate functional clocks +DATA 4 0x41a40044 0x8 // De-assert DDR PHY reset and keep DDR Controller in reset for its programming requirements +DATA 4 0x41d00044 0x8 // De-assert DDR PHY reset and keep DDR Controller in reset for its programming requirements +DATA 4 0x41a40204 0x1 // Ungate functional clocks +DATA 4 0x41d00204 0x1 // Ungate functional clocks + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC1080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC1080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 // De-assert DDR Controller reset +DATA 4 0x41d00044 0x4 // De-assert DDR Controller reset +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x03201901 +DATA 4 DDR_PHY_PTR1_0 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x03201901 +DATA 4 DDR_PHY_PTR1_1 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00032 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AB // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00032 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AB // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x64032010, 0x4E201C20, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00010236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg new file mode 100755 index 0000000..eb1ae49 --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg @@ -0,0 +1,513 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_1 0x00808000 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------=------------ +// Set-up DRAM 1 PHY Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_1 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x33 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF +DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x03300640 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x03300640 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 +// Launch DRAM 1 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch a second time DRAM initialization due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait (second time) DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_800MHz.cfg b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_800MHz.cfg new file mode 100755 index 0000000..0fc3ead --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_800MHz.cfg @@ -0,0 +1,624 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to 800MHz. */ + uint32_t rate2 = SC_400MHZ; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2); +} +else +{ +/* Change to div4 output */ +DATA 4 0x41A43800 0x4C000000 +DATA 4 0x41D03800 0x4C000000 +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_0 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_1 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x01A00C81 +DATA 4 DDR_PHY_PTR1_0 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x01A00C81 +DATA 4 DDR_PHY_PTR1_1 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00019 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00019 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x32019010, 0x27100E10, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + + + + + + + + + + + + + + + + + + + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + diff --git a/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_emul.cfg b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_emul.cfg new file mode 100755 index 0000000..26e3098 --- /dev/null +++ b/platform/board/mx8qm_smarc_4g/dcd/imx8qm_dcd_emul.cfg @@ -0,0 +1,214 @@ +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// Reset Should not be needed for ZEBU. +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 + +// ddrc_lpddr4_init(0) +DATA 4 0x5C000000 0xC3080020 +DATA 4 0x5C000064 0x006100E0 +DATA 4 0x5C0000D0 0x40020010 +DATA 4 0x5C0000D4 0x00100000 +DATA 4 0x5C0000DC 0x0054002D +DATA 4 0x5C0000E0 0x00310000 +DATA 4 0x5C0000F4 0x000006CF +DATA 4 0x5C000100 0x1A201B22 +DATA 4 0x5C000104 0x00060633 +DATA 4 0x5C000108 0x070E1014 +DATA 4 0x5C00010C 0x0170C00C +DATA 4 0x5C000110 0x0F04080F +DATA 4 0x5C000114 0x03040C0C +DATA 4 0x5C000118 0x02020007 +DATA 4 0x5C00011C 0x00000401 +DATA 4 0x5C000130 0x00020610 +DATA 4 0x5C000134 0x0C100002 +DATA 4 0x5C000138 0x000000E6 +DATA 4 0x5C000180 0x03200018 +DATA 4 0x5C000184 0x02800100 +DATA 4 0x5C000190 0x049C820C +DATA 4 0x5C000194 0x00060303 +DATA 4 0x5C0001B4 0x00001A0A +DATA 4 0x5C0001B0 0x00000005 +DATA 4 0x5C0001A0 0x80400003 +DATA 4 0x5C0001A4 0x00010002 +DATA 4 0x5C0001A8 0x80000000 +DATA 4 0x5C000200 0x00000017 +DATA 4 0x5C000204 0x00080808 +DATA 4 0x5C000214 0x07070707 +DATA 4 0x5C000218 0x07070707 +DATA 4 0x5C000244 0x00002211 +DATA 4 0x5C000490 0x00000001 +DATA 4 0x5C002190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 +//DATA 4 0x5C0001B0 0x00000004 +//DATA 4 0x5C0000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(0) +DATA 4 0x5C010100 0x0000040D +DATA 4 0x5C010018 0x00F0DA09 +DATA 4 0x5C01001C 0x050A1080 +DATA 4 0x5C010040 0x64032010 +DATA 4 0x5C010044 0x0D701C20 +DATA 4 0x5C010068 0x08000000 +DATA 4 0x5C0117C4 0x08000000 +DATA 4 0x5C010680 0x001FEC58 + +//ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00000040 +DATA 4 0x5C010004 0x00000041 + +//ddr_phy_lpddr4_dram_init(0) +DATA 4 0x5C010184 0x00000054 +DATA 4 0x5C010188 0x0000002D +DATA 4 0x5C01018C 0x00000031 +DATA 4 0x5C010110 0x1044220C +DATA 4 0x5C010114 0x28408C17 +DATA 4 0x5C010118 0x003C01CC +DATA 4 0x5C01011C 0x01800604 +DATA 4 0x5C010120 0x01C0000C +DATA 4 0x5C010124 0x00651D10 +DATA 4 0x5C01004C 0x00007D00 +DATA 4 0x5C010050 0x00000C90 +DATA 4 0x5C010054 0x00007D00 +DATA 4 0x5C010058 0x03000641 +DATA 4 0x5C010500 0x30070800 +DATA 4 0x5C010514 0x09000000 +DATA 4 0x5C010528 0xF0032019 +DATA 4 0x5C01052C 0x07F00173 +DATA 4 0x5C0117EC 0x00081800 +DATA 4 0x5C0117F0 0x09000000 +DATA 4 0x5C0117DC 0x013E4091 + +//ddr_phy_wait_init_done(0) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00040000 +DATA 4 0x5C010004 0x00040001 + +// SECOND DRC SYSTEM + +// ddrc_lpddr4_init(1) +DATA 4 0x5C100000 0xC3080020 +DATA 4 0x5C100064 0x006100E0 +DATA 4 0x5C1000D0 0x40020010 +DATA 4 0x5C1000D4 0x00100000 +DATA 4 0x5C1000DC 0x0054002D +DATA 4 0x5C1000E0 0x00310000 +DATA 4 0x5C1000F4 0x000006CF +DATA 4 0x5C100100 0x1A201B22 +DATA 4 0x5C100104 0x00060633 +DATA 4 0x5C100108 0x070E1014 +DATA 4 0x5C10010C 0x0170C00C +DATA 4 0x5C100110 0x0F04080F +DATA 4 0x5C100114 0x03040C0C +DATA 4 0x5C100118 0x02020007 +DATA 4 0x5C10011C 0x00000401 +DATA 4 0x5C100130 0x00020610 +DATA 4 0x5C100134 0x0C100002 +DATA 4 0x5C100138 0x000000E6 +DATA 4 0x5C100180 0x03200018 +DATA 4 0x5C100184 0x02800100 +DATA 4 0x5C100190 0x049C820C +DATA 4 0x5C100194 0x00060303 +DATA 4 0x5C1001B4 0x00001A0A +DATA 4 0x5C1001B0 0x00000005 +DATA 4 0x5C1001A0 0x80400003 +DATA 4 0x5C1001A4 0x00010002 +DATA 4 0x5C1001A8 0x80000000 +DATA 4 0x5C100200 0x00000017 +DATA 4 0x5C100204 0x00080808 +DATA 4 0x5C100214 0x07070707 +DATA 4 0x5C100218 0x07070707 +DATA 4 0x5C100244 0x00002211 +DATA 4 0x5C100490 0x00000001 +DATA 4 0x5C102190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_1 0x00000001 +CLR_BIT 4 DDRC_INIT0_1 0xC0000000 +//DATA 4 0x5C1001B0 0x00000004 +//DATA 4 0x5C1000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(1) +DATA 4 0x5C110100 0x0000040D +DATA 4 0x5C110018 0x00F0DA09 +DATA 4 0x5C11001C 0x050A1080 +DATA 4 0x5C110040 0x64032010 +DATA 4 0x5C110044 0x0D701C20 +DATA 4 0x5C110068 0x08000000 +DATA 4 0x5C1117C4 0x08000000 +DATA 4 0x5C110680 0x001FEC58 + +//ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00000040 +DATA 4 0x5C110004 0x00000041 + + +//ddr_phy_lpddr4_dram_init(1) +DATA 4 0x5C110184 0x00000054 +DATA 4 0x5C110188 0x0000002D +DATA 4 0x5C11018C 0x00000031 +DATA 4 0x5C110110 0x1044220C +DATA 4 0x5C110114 0x28408C17 +DATA 4 0x5C110118 0x003C01CC +DATA 4 0x5C11011C 0x01800604 +DATA 4 0x5C110120 0x01C0000C +DATA 4 0x5C110124 0x00651D10 +DATA 4 0x5C11004C 0x00007D00 +DATA 4 0x5C110050 0x00000C90 +DATA 4 0x5C110054 0x00007D00 +DATA 4 0x5C110058 0x03000641 +DATA 4 0x5C110500 0x30070800 +DATA 4 0x5C110514 0x09000000 +DATA 4 0x5C110528 0xF0032019 +DATA 4 0x5C11052C 0x07F00173 +DATA 4 0x5C1117EC 0x00081800 +DATA 4 0x5C1117F0 0x09000000 +DATA 4 0x5C1117DC 0x013E4091 + +//ddr_phy_wait_init_done(1) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00040000 +DATA 4 0x5C110004 0x00040001 + +// RESET +DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DSC_SetReset(SC_DSC_DRC_1, BIT(RST_DDR_CRESETN), SC_TRUE); +//DATA 4 0x41a40044 0x4 +//DATA 4 0x41d00044 0x4 + +// dram_init_inst(0) +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// dram_init_inst(1) +CLR_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_1 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_1 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +//DATA 4 0x5C000320 0x00000000 +//DATA 4 0x5C0001B0 0x00000005 +//DATA 4 0x5C000320 0x00000001 +//DATA 4 0x5C100320 0x00000000 +//DATA 4 0x5C1001B0 0x00000005 +//DATA 4 0x5C100320 0x00000001 + diff --git a/platform/board/mx8qm_smarc_8g/Makefile b/platform/board/mx8qm_smarc_8g/Makefile new file mode 100755 index 0000000..1c37faf --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/Makefile @@ -0,0 +1,61 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8qm_dcd_emul +else + DDR_CON ?= imx8qm_dcd_1.6GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + +ifeq ($(M),1) + OBJS += $(OUT)/board/pmic.o +endif + diff --git a/platform/board/mx8qm_smarc_8g/board.bom b/platform/board/mx8qm_smarc_8g/board.bom new file mode 100755 index 0000000..6879226 --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/board.bom @@ -0,0 +1,40 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf8100 + +ifeq ($(M),1) + DRV2 += pmic/pf100 +endif + diff --git a/platform/board/mx8qm_smarc_8g/board.c b/platform/board/mx8qm_smarc_8g/board.c new file mode 100755 index 0000000..40a7617 --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/board.c @@ -0,0 +1,2007 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QM MEK board. + * + * @addtogroup MX8QM_MEK_BRD BRD: MX8QM MEK Board + * + * Module for MX8QM MEK board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00090 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "drivers/systick/fsl_systick.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" + +/* ------------------------------------------------------------------------------------------------------------------ + * ----- iMX8QM: eDMA limitation USE CASE ----- + * ------------------------------------------------------------------------------------------------------------------ + * In the new kernel NXP use the "edma2" in the lpspi driver. The same dma controller is used from M core in FreeRTOS + * This generate a conflict and than a kernel crash + * ------------------------------------------------------------------------------------------------------------------ + * To add a clarification regarding eDMA: + * - The "edma2" node in the Linux device tree refers to the device at BAR 0x5a1f0000 described in the DMA memory map + * as "eDMA0" (i.MX 8QuadMax reference manual rev.F pp.32) + * - DMA0_BASE in imx-sc-firmware/src/scfw_export_mx8qm_b0/platform/devices/MX8QM/MX8QM.h also points to the + * RM's "eDMA0" at 0x5a1f0000. + * This confirms the eDMA conflict. + * + * How to use use eDMA0 in the FreeRTOS: + * - USE_DMA_0 must be defined + * - eDMA0 must be disabled in the Linux device tree overriding the nodes that use "edma2" or disabling the nodes + * that using it + * ------------------------------------------------------------------------------------------------------------------ + * The eDMA conflict affect the below FreeRTOS examples: + * - lpspi_edma_b2b_transfer_master.c + * - lpspi_edma_b2b_transfer_slave.c + * - lpuart_edma_transfer.c + * - edma_memory_to_memory.c + * - edma_scatter_gather.c + * - cmsis_usart_edma_transfer.c + * ------------------------------------------------------------------------------------------------------------------ + */ + +/* Local Defines */ + +#undef USE_DMA_0 /* Before define USE_DMA_0, read "iMX8QM: eDMA limitation USE CASE" above */ + +#undef M41_USES_SPI0 +#undef M41_USES_I2C3 +#undef M41_USES_GPIO3_24 +#undef M41_USES_CAN0 +#undef M41_USES_EDMA + +#ifndef USE_DMA_0 + #undef M41_USES_EDMA +#endif + +/*! Memory size */ +#ifndef BD_DDR_SIZE + #define BD_DDR_SIZE SC_8GB +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_PMIC_1 1U +#define BRD_R_BOARD_PMIC_2 2U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U /*!< EMVSIM */ +#define BRD_R_BOARD_R3 6U /*!< USDHC2 on Base board */ +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 3 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif +#if DEBUG_UART == 2 + /*! Use alternate debug UART */ + #define ALT_DEBUG_SCU_UART +#endif +#if (defined(MONITOR) || defined(EXPORT_MONITOR) || defined(HAS_TEST) \ + || (DEBUG_UART == 1)) && !defined(DEBUG_TERM_EMUL) \ + && !defined(ALT_DEBUG_SCU_UART) + #define ALT_DEBUG_UART +#endif + +/*! Configure debug UART */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG LPUART_SC +#else + #define LPUART_DEBUG LPUART_MCU_0 +#endif + +/*! Configure debug UART instance */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG_INST 0U +#else + #define LPUART_DEBUG_INST 2U +#endif + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +static sc_err_t pmic_ignore_current_limit(uint8_t address); +static sc_err_t pmic_update_timing(uint8_t address); +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver); +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t temp_alarm0; +static uint32_t temp_alarm1; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + /*rgpio_pin_config_t config; + config.pinDirection = kRGPIO_DigitalOutput;*/ + + ss_print(3, "board_init(%d)\n", phase); + + /*if (phase == BOOT_PHASE_HW_INIT) + { + #ifndef ALT_DEBUG_SCU_UART + pad_force_mux(SC_P_SCU_GPIO0_01, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + #endif*/ + /*pad_force_mux(SC_P_SCU_GPIO0_02, 0, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF);*/ + + /* Toggle base board reset SC_GPIO_01, >= 30nS */ + /*config.outputLogic = 0U; + FGPIO_PinInit(FGPIOA, 1U, &config); + SYSTICK_CycleDelay(SC_SYSTICK_NSEC_TO_TICKS(30U) + 1U); + FGPIO_PinWrite(FGPIOA, 1U, 1U);*/ + + /* SCU_LED on SC_GPIO_02 */ + /*config.outputLogic = 1U; + FGPIO_PinInit(FGPIOA, 2U, &config); + + SystemTimeDelay(2U); + } + else if (phase == BOOT_PHASE_FINAL_INIT)*/ + if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #if (defined(ALT_DEBUG_UART) || defined(ALT_DEBUG_SCU_UART)) \ + && !defined(DEBUG_TERM_EMUL) + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(ALT_DEBUG_SCU_UART) && !defined(DEBUG_TERM_EMUL) \ + && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Check if debug disabled */ + if (SCFW_DBG_READY == 0U) + { + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + } + #elif defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Use M4 UART if ALT_DEBUG_UART defined */ + /* Return if debug already enabled */ + if ((SCFW_DBG_READY == 0U) && (early_phase == SC_FALSE)) + { + sc_pm_clock_rate_t rate = SC_24MHZ; + static sc_bool_t banner = SC_FALSE; + + /* Configure pads */ + pad_force_mux(SC_P_M40_I2C0_SDA, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M40_I2C0_SCL, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M41_I2C0_SDA, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + pad_force_mux(SC_P_M41_I2C0_SCL, 1, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + + /* Power and enable clock */ + pm_force_resource_power_mode_v(SC_R_SC_PID0, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DBLOGIC, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DB, SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + pm_force_resource_power_mode_v(SC_R_M4_1_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_1_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_1_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + + /* Configure UART */ + main_config_debug_uart(LPUART_DEBUG, rate); + + if (banner == SC_FALSE) + { + debug_print(1, + "\nHello from SCU (Build %u, Commit %08x, %s %s)\n\n", + SCFW_BUILD, SCFW_COMMIT, SCFW_DATE, SCFW_TIME); + banner = SC_TRUE; + } + } + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ + /* Use M4 UART if ALT_DEBUG_UART defined */ + #if defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Return if debug already disabled */ + if (SCFW_DBG_READY != 0U) + { + /* Disable use of UART */ + SCFW_DBG_READY = 0U; + + // UART deinit to flush TX buffers + LPUART_Deinit(LPUART_DEBUG); + + /* Turn off UART */ + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_OFF); + pm_force_resource_power_mode_v(SC_R_M4_1_UART, + SC_PM_PW_MODE_OFF); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + #ifdef ALT_DEBUG_UART + (void) rm_set_resource_movable(SC_PT, SC_R_M4_0_UART, SC_R_M4_0_UART, + SC_FALSE); + (void) rm_set_pad_movable(SC_PT, SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA, + SC_FALSE); + #endif + + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SDA, SC_P_PMIC_I2C_SCL, + SC_FALSE); + #ifdef ALT_DEBUG_SCU_UART + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_EXTERNAL; + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + rtn = BOARD_KS1_RESUME_USEC; + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + /* DC0 PLL0 spread spectrum config */ + case BOARD_PARM_DC0_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC0 PLL1 spread spectrum config */ + case BOARD_PARM_DC0_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL0 spread spectrum config */ + case BOARD_PARM_DC1_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL1 spread spectrum config */ + case BOARD_PARM_DC1_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* Control if SC WDOG configuration during KS1 */ + case BOARD_PARM_KS1_WDOG_WAKE: + rtn = BOARD_PARM_KS1_WDOG_WAKE_ENABLE; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. - DDR_00060 */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + #if defined(BD_DDR_RET_NUM_DRC) && (BD_DDR_RET_NUM_DRC == 1U) + if(rsrc == SC_R_DRC_1) + { + rtn = SC_FALSE; + } + #endif + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + static uint32_t board_ddr_ret_buf4[BD_DDR_RET_REGION4_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + static uint32_t board_ddr_ret_buf5[BD_DDR_RET_REGION5_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + static uint32_t board_ddr_ret_buf6[BD_DDR_RET_REGION6_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 }, + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + { BD_DDR_RET_REGION4_ADDR, BD_DDR_RET_REGION4_SIZE, board_ddr_ret_buf4 }, + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + { BD_DDR_RET_REGION5_ADDR, BD_DDR_RET_REGION5_SIZE, board_ddr_ret_buf5 }, + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + { BD_DDR_RET_REGION6_ADDR, BD_DDR_RET_REGION6_SIZE, board_ddr_ret_buf6 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + else if (rm_is_resource_avail(SC_R_DRC_1)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_1, + SC_PM_CLK_SLV_BUS, &rate); + } + else + { + ; /* Intentional empty else */ + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + /* DDR_00040 */ + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. See DDR_00010. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + /* Supports stress test tool - DDR_00070 */ + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + case BOARD_DDR1_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(1); + #else + // Run vref training + DRAM_VREF_training_sw(1); + #endif + break; + default: + /* DDR_00020 */ + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + sc_rm_pt_t pt_m4_1 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[7U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_7A, + SC_R_MU_8B, + SC_R_GPT_4, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x0887FFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Create M4 1 partition */ + if (rm_is_resource_avail(SC_R_M4_1_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[5U] = + { + SC_R_IRQSTR_M4_1, +#ifdef M41_USES_SPI0 +#ifdef USE_DMA_0 + SC_R_DMA_0_CH0, + SC_R_DMA_0_CH1, /* DMA0 channels for SPI0 */ +#endif + SC_R_SPI_0, +#endif +#ifdef M41_USES_I2C3 + SC_R_DMA_1_CH0, + SC_R_DMA_1_CH1, /* DMA1 channels for I2C3 */ + SC_R_I2C_3, +#endif +#ifdef M41_USES_GPIO3_24 + SC_R_GPIO_3, +#endif + SC_R_MU_6B, + SC_R_MU_7B, + SC_R_MU_9B, +#ifdef M41_USES_EDMA + SC_R_DMA_0_CH30, /* DMA0 channel for EDMA sample code */ +#endif +#ifdef M41_USES_CAN0 + SC_R_CAN_0, +#endif + SC_R_GPT_3, + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M41_I2C0_SCL, SC_P_M41_I2C0_SDA), + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088800000ULL, 0x08FFFFFFFULL}, + {0x008181000ULL, 0x008280FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_1, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_1_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_1, "MCU1"); + + /* Allow M4 1 to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_m4_1, SC_RM_PERM_SEC_RW)); + + /* Move M4 1 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x038FE0000ULL, + 0x038FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_1, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_1, SC_PT)); + } + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[4U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4), + RM_RANGE(SC_R_M4_1_PID1, SC_R_M4_1_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + if (pt_m4_1 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_1, + SC_RM_PERM_FULL)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_1_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + SW_RUN_PWM | SW_STBY_PWM)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + SW_RUN_OFF)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(pmic_id[idx], pmic_reg[idx], new_volt, + REG_RUN_MODE)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ + static uint32_t vdd_memc_mode = 0U; + + if (mode == SC_PM_PW_MODE_STBY) + { + /* + * System standby (KS1) entry allows VDD_MEMC to be gated off. + * Save current mode and switch off supply. + */ + if (PMIC_GET_MODE(PMIC_1_ADDR, PF8100_SW5, &vdd_memc_mode) + == SC_ERR_NONE) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, SW_STBY_OFF + | SW_RUN_OFF); + } + } + else if (mode == SC_PM_PW_MODE_ON) + { + /* + * System standby (KS1) exit should switch on VDD_MEMC. Restore + * previous mode saved during KS1 entry. + */ + if (vdd_memc_mode != 0U) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, vdd_memc_mode); + } + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + switch (idx) + { + case BRD_R_BOARD_R2 : /* EMVSIM */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_LDO1, + 3000, REG_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_EN_STBY_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_OFF_STBY_OFF)); + } + break; + case BRD_R_BOARD_R3 : /* USDHC2 on Base Board */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_EN_STBY_EN | VSELECT_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_OFF_STBY_OFF)); + } + break; + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + ; /* Intentional empty default */ + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + #endif + #ifdef ALT_DEBUG_UART + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if ((resource == SC_R_M4_0_PID0) || (resource == SC_R_M4_1_PID0)) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm0 = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm1 = + SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + /* PMIC 0 */ + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm0; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* PMIC 1 */ + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_1_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm1; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_1_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* Board R7 - only here for testing */ + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Temp alarm from PMIC 1 */ + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC1_HIGH, + SC_PT_ALL); + } + /* Temp alarm from PMIC 0 */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC0_HIGH, + SC_PT_ALL); + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + + /* MEK board spec is for 1M baud for PMIC I2C bus */ + lpi2c_masterConfig.baudRate_Hz = 1000000U; + lpi2c_masterConfig.sdaGlitchFilterWidth_ns = 100U; + lpi2c_masterConfig.sclGlitchFilterWidth_ns = 100U; + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + + err |= pmic_ignore_current_limit(PMIC_0_ADDR); + err |= pmic_ignore_current_limit(PMIC_1_ADDR); + + /* Adjust startup timing */ + err |= pmic_update_timing(PMIC_0_ADDR); + err |= pmic_update_timing(PMIC_1_ADDR); + + err |= pmic_match_otp(PMIC_0_ADDR, pmic_ver); + err |= pmic_match_otp(PMIC_1_ADDR, pmic_ver); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + err |= pf8100_pmic_wdog_enable(PMIC_1_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + + if (err != SC_ERR_NONE) + { + /* Loop so WDOG will expire */ + HALT; + } + + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW7, SW_RUN_PWM + | SW_STBY_PWM)); + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, 800, + REG_STBY_MODE)); + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + val |= 0x20U; /* set xx_ILIM_BYPASS */ + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update power timing for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_update_timing(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + + /* + * Add 60ms stable time for power down for: + * PMIC 1 : LDO2, SW6, SW7 + * PMIC 2 : LDO2, SW5, SW6, SW7 + * on i.mx8QM-mek + * board, otherwise system may reboot fail by mmc not power off + * clean + */ + if (address == PMIC_0_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 0 */ + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else if (address == PMIC_1_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 1 */ + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x6F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else + { + /* Return error */ + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check correct version of OTP for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver) +{ + uint8_t reg_value = 0U; + uint16_t prog_id, match; + sc_err_t err = SC_ERR_NONE; + + if (address == PMIC_0_ADDR) + { + match = EP_PROG_ID; + } + else + { + match = EQ_PROG_ID; + } + + /* Read Prog ID */ + err |= PMIC_REGISTER_ACCESS(address, 0x2, SC_FALSE, ®_value); + prog_id = (((uint16_t)reg_value << 4U) & 0x0F00U); + err |= PMIC_REGISTER_ACCESS(address, 0x3U, SC_FALSE, ®_value); + prog_id |= reg_value; + + /* test against calibration fusing */ + if (OTP_PROG_FUSE_VERSION_1_7V_CAL != 0U) + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + /* if C1 PMIC test for correct OTP */ + if(prog_id != match){/* allow only 1.7v OTP */ + error_print("PMIC INVALID!\n"); + } + } + else + { + error_print("PMIC INVALID!\n"); + } + } + else + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + if(prog_id == match){/* prohibit only 1.7V OTP */ + error_print("PMIC INVALID!\n"); + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A53 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW5; + *num_regs = 1U; + } + break; + case SC_SUBSYS_A72 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW1; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW2; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_1 : + pmic_init(); + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + default : + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qm_smarc_8g/board.h b/platform/board/mx8qm_smarc_8g/board.h new file mode 100755 index 0000000..841c97a --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/board.h @@ -0,0 +1,115 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC pf8100 +#define PMIC_0_ADDR 0x8U +#define PMIC_1_ADDR 0x9U + +#define PF8100_C1_SI_REV 0x31U +#define EP_PROG_ID 0x0417U +#define EQ_PROG_ID 0x0418U + +#define PMIC_TEMP_MAX 135U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qm_smarc_8g/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qm_smarc_8g/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..896973b --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,143 @@ +DEFINE BD_DDR_RET_NUM_DRC 2 // Number of DRCs in the SoC + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_smarc_8g/dcd/ddr_stress_test_parser_DRC0_only.cfg b/platform/board/mx8qm_smarc_8g/dcd/ddr_stress_test_parser_DRC0_only.cfg new file mode 100755 index 0000000..119af25 --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/dcd/ddr_stress_test_parser_DRC0_only.cfg @@ -0,0 +1,142 @@ +DEFINE BD_DDR_RET_NUM_DRC 1 // One DRC in the SoC; DRC0 only + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_1.6GHz.cfg b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_1.6GHz.cfg new file mode 100644 index 0000000..70100e3 --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_1.6GHz.cfg @@ -0,0 +1,591 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x200000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 // Gate functional clocks +DATA 4 0x41d00208 0x1 // Gate functional clocks +DATA 4 0x41a40044 0x8 // De-assert DDR PHY reset and keep DDR Controller in reset for its programming requirements +DATA 4 0x41d00044 0x8 // De-assert DDR PHY reset and keep DDR Controller in reset for its programming requirements +DATA 4 0x41a40204 0x1 // Ungate functional clocks +DATA 4 0x41d00204 0x1 // Ungate functional clocks + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x08080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x08080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 // De-assert DDR Controller reset +DATA 4 0x41d00044 0x4 // De-assert DDR Controller reset +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x03201901 +DATA 4 DDR_PHY_PTR1_0 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x03201901 +DATA 4 DDR_PHY_PTR1_1 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00032 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AB // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00032 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AB // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x64032010, 0x4E201C20, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg new file mode 100755 index 0000000..eb1ae49 --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg @@ -0,0 +1,513 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_1 0x00808000 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------=------------ +// Set-up DRAM 1 PHY Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_1 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x33 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF +DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x03300640 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x03300640 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 +// Launch DRAM 1 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch a second time DRAM initialization due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait (second time) DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_800MHz.cfg b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_800MHz.cfg new file mode 100755 index 0000000..0fc3ead --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_800MHz.cfg @@ -0,0 +1,624 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to 800MHz. */ + uint32_t rate2 = SC_400MHZ; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2); +} +else +{ +/* Change to div4 output */ +DATA 4 0x41A43800 0x4C000000 +DATA 4 0x41D03800 0x4C000000 +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_0 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_1 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x01A00C81 +DATA 4 DDR_PHY_PTR1_0 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x01A00C81 +DATA 4 DDR_PHY_PTR1_1 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00019 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00019 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x32019010, 0x27100E10, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + + + + + + + + + + + + + + + + + + + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + diff --git a/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_emul.cfg b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_emul.cfg new file mode 100755 index 0000000..26e3098 --- /dev/null +++ b/platform/board/mx8qm_smarc_8g/dcd/imx8qm_dcd_emul.cfg @@ -0,0 +1,214 @@ +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// Reset Should not be needed for ZEBU. +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 + +// ddrc_lpddr4_init(0) +DATA 4 0x5C000000 0xC3080020 +DATA 4 0x5C000064 0x006100E0 +DATA 4 0x5C0000D0 0x40020010 +DATA 4 0x5C0000D4 0x00100000 +DATA 4 0x5C0000DC 0x0054002D +DATA 4 0x5C0000E0 0x00310000 +DATA 4 0x5C0000F4 0x000006CF +DATA 4 0x5C000100 0x1A201B22 +DATA 4 0x5C000104 0x00060633 +DATA 4 0x5C000108 0x070E1014 +DATA 4 0x5C00010C 0x0170C00C +DATA 4 0x5C000110 0x0F04080F +DATA 4 0x5C000114 0x03040C0C +DATA 4 0x5C000118 0x02020007 +DATA 4 0x5C00011C 0x00000401 +DATA 4 0x5C000130 0x00020610 +DATA 4 0x5C000134 0x0C100002 +DATA 4 0x5C000138 0x000000E6 +DATA 4 0x5C000180 0x03200018 +DATA 4 0x5C000184 0x02800100 +DATA 4 0x5C000190 0x049C820C +DATA 4 0x5C000194 0x00060303 +DATA 4 0x5C0001B4 0x00001A0A +DATA 4 0x5C0001B0 0x00000005 +DATA 4 0x5C0001A0 0x80400003 +DATA 4 0x5C0001A4 0x00010002 +DATA 4 0x5C0001A8 0x80000000 +DATA 4 0x5C000200 0x00000017 +DATA 4 0x5C000204 0x00080808 +DATA 4 0x5C000214 0x07070707 +DATA 4 0x5C000218 0x07070707 +DATA 4 0x5C000244 0x00002211 +DATA 4 0x5C000490 0x00000001 +DATA 4 0x5C002190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 +//DATA 4 0x5C0001B0 0x00000004 +//DATA 4 0x5C0000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(0) +DATA 4 0x5C010100 0x0000040D +DATA 4 0x5C010018 0x00F0DA09 +DATA 4 0x5C01001C 0x050A1080 +DATA 4 0x5C010040 0x64032010 +DATA 4 0x5C010044 0x0D701C20 +DATA 4 0x5C010068 0x08000000 +DATA 4 0x5C0117C4 0x08000000 +DATA 4 0x5C010680 0x001FEC58 + +//ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00000040 +DATA 4 0x5C010004 0x00000041 + +//ddr_phy_lpddr4_dram_init(0) +DATA 4 0x5C010184 0x00000054 +DATA 4 0x5C010188 0x0000002D +DATA 4 0x5C01018C 0x00000031 +DATA 4 0x5C010110 0x1044220C +DATA 4 0x5C010114 0x28408C17 +DATA 4 0x5C010118 0x003C01CC +DATA 4 0x5C01011C 0x01800604 +DATA 4 0x5C010120 0x01C0000C +DATA 4 0x5C010124 0x00651D10 +DATA 4 0x5C01004C 0x00007D00 +DATA 4 0x5C010050 0x00000C90 +DATA 4 0x5C010054 0x00007D00 +DATA 4 0x5C010058 0x03000641 +DATA 4 0x5C010500 0x30070800 +DATA 4 0x5C010514 0x09000000 +DATA 4 0x5C010528 0xF0032019 +DATA 4 0x5C01052C 0x07F00173 +DATA 4 0x5C0117EC 0x00081800 +DATA 4 0x5C0117F0 0x09000000 +DATA 4 0x5C0117DC 0x013E4091 + +//ddr_phy_wait_init_done(0) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00040000 +DATA 4 0x5C010004 0x00040001 + +// SECOND DRC SYSTEM + +// ddrc_lpddr4_init(1) +DATA 4 0x5C100000 0xC3080020 +DATA 4 0x5C100064 0x006100E0 +DATA 4 0x5C1000D0 0x40020010 +DATA 4 0x5C1000D4 0x00100000 +DATA 4 0x5C1000DC 0x0054002D +DATA 4 0x5C1000E0 0x00310000 +DATA 4 0x5C1000F4 0x000006CF +DATA 4 0x5C100100 0x1A201B22 +DATA 4 0x5C100104 0x00060633 +DATA 4 0x5C100108 0x070E1014 +DATA 4 0x5C10010C 0x0170C00C +DATA 4 0x5C100110 0x0F04080F +DATA 4 0x5C100114 0x03040C0C +DATA 4 0x5C100118 0x02020007 +DATA 4 0x5C10011C 0x00000401 +DATA 4 0x5C100130 0x00020610 +DATA 4 0x5C100134 0x0C100002 +DATA 4 0x5C100138 0x000000E6 +DATA 4 0x5C100180 0x03200018 +DATA 4 0x5C100184 0x02800100 +DATA 4 0x5C100190 0x049C820C +DATA 4 0x5C100194 0x00060303 +DATA 4 0x5C1001B4 0x00001A0A +DATA 4 0x5C1001B0 0x00000005 +DATA 4 0x5C1001A0 0x80400003 +DATA 4 0x5C1001A4 0x00010002 +DATA 4 0x5C1001A8 0x80000000 +DATA 4 0x5C100200 0x00000017 +DATA 4 0x5C100204 0x00080808 +DATA 4 0x5C100214 0x07070707 +DATA 4 0x5C100218 0x07070707 +DATA 4 0x5C100244 0x00002211 +DATA 4 0x5C100490 0x00000001 +DATA 4 0x5C102190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_1 0x00000001 +CLR_BIT 4 DDRC_INIT0_1 0xC0000000 +//DATA 4 0x5C1001B0 0x00000004 +//DATA 4 0x5C1000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(1) +DATA 4 0x5C110100 0x0000040D +DATA 4 0x5C110018 0x00F0DA09 +DATA 4 0x5C11001C 0x050A1080 +DATA 4 0x5C110040 0x64032010 +DATA 4 0x5C110044 0x0D701C20 +DATA 4 0x5C110068 0x08000000 +DATA 4 0x5C1117C4 0x08000000 +DATA 4 0x5C110680 0x001FEC58 + +//ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00000040 +DATA 4 0x5C110004 0x00000041 + + +//ddr_phy_lpddr4_dram_init(1) +DATA 4 0x5C110184 0x00000054 +DATA 4 0x5C110188 0x0000002D +DATA 4 0x5C11018C 0x00000031 +DATA 4 0x5C110110 0x1044220C +DATA 4 0x5C110114 0x28408C17 +DATA 4 0x5C110118 0x003C01CC +DATA 4 0x5C11011C 0x01800604 +DATA 4 0x5C110120 0x01C0000C +DATA 4 0x5C110124 0x00651D10 +DATA 4 0x5C11004C 0x00007D00 +DATA 4 0x5C110050 0x00000C90 +DATA 4 0x5C110054 0x00007D00 +DATA 4 0x5C110058 0x03000641 +DATA 4 0x5C110500 0x30070800 +DATA 4 0x5C110514 0x09000000 +DATA 4 0x5C110528 0xF0032019 +DATA 4 0x5C11052C 0x07F00173 +DATA 4 0x5C1117EC 0x00081800 +DATA 4 0x5C1117F0 0x09000000 +DATA 4 0x5C1117DC 0x013E4091 + +//ddr_phy_wait_init_done(1) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00040000 +DATA 4 0x5C110004 0x00040001 + +// RESET +DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DSC_SetReset(SC_DSC_DRC_1, BIT(RST_DDR_CRESETN), SC_TRUE); +//DATA 4 0x41a40044 0x4 +//DATA 4 0x41d00044 0x4 + +// dram_init_inst(0) +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// dram_init_inst(1) +CLR_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_1 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_1 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +//DATA 4 0x5C000320 0x00000000 +//DATA 4 0x5C0001B0 0x00000005 +//DATA 4 0x5C000320 0x00000001 +//DATA 4 0x5C100320 0x00000000 +//DATA 4 0x5C1001B0 0x00000005 +//DATA 4 0x5C100320 0x00000001 + diff --git a/platform/board/mx8qm_val/Makefile b/platform/board/mx8qm_val/Makefile new file mode 100755 index 0000000..ef0845a --- /dev/null +++ b/platform/board/mx8qm_val/Makefile @@ -0,0 +1,58 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8qm_dcd_emul +else + DDR_CON ?= imx8qm_dcd_1.6GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o \ + $(OUT)/board/pmic.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + diff --git a/platform/board/mx8qm_val/board.bom b/platform/board/mx8qm_val/board.bom new file mode 100755 index 0000000..fbff4e9 --- /dev/null +++ b/platform/board/mx8qm_val/board.bom @@ -0,0 +1,37 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf100 \ + pmic/pf8100 + diff --git a/platform/board/mx8qm_val/board.c b/platform/board/mx8qm_val/board.c new file mode 100755 index 0000000..9d13076 --- /dev/null +++ b/platform/board/mx8qm_val/board.c @@ -0,0 +1,2086 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QM validation board. + * + * @addtogroup MX8QM_VAL_BRD BRD: MX8QM Validation Board + * + * Module for MX8QM validation board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00080, DDR_00030 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "all_ss.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf100/fsl_pf100.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" + +/* Local Defines */ + +/*! Memory size */ +#ifndef BD_DDR_SIZE + #define BD_DDR_SIZE SC_6GB +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_PMIC_1 1U +#define BRD_R_BOARD_PMIC_2 2U +#define BRD_R_BOARD_R0 3U /*!< PTN5150 */ +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U /*!< HSIC */ +#define BRD_R_BOARD_R3 6U /*!< USDHC2 on Base board */ +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 1 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif + +/*! Configure debug UART */ +#define LPUART_DEBUG LPUART_SC + +/*! Configure debug UART instance */ +#define LPUART_DEBUG_INST 0U + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +#ifndef EMUL + static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver); + static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver); +#endif +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t pmic_card; +static uint32_t temp_alarm0; +static uint32_t temp_alarm1; +static uint32_t temp_alarm2; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + rgpio_pin_config_t config; + config.pinDirection = kRGPIO_DigitalOutput; + config.outputLogic = 1U; + + ss_print(3, "board_init(%d)\n", phase); + + if (phase == BOOT_PHASE_HW_INIT) + { + pad_force_mux(SC_P_SCU_GPIO0_02, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + pad_force_mux(SC_P_SCU_GPIO0_03, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + + /* DELAYED_3V3_EN SC_GPIO_03 */ + FGPIO_PinInit(FGPIOA, 3U, &config); + + /* SCU_LED on */ + FGPIO_PinInit(FGPIOA, 2U, &config); + + SystemTimeDelay(2U); + } + else if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #ifndef DEBUG_TERM_EMUL + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if !defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Return if debug enabled */ + ASRT(SCFW_DBG_READY == 0U); + + /* Configure SCU UART */ + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SDA, SC_P_PMIC_I2C_SCL, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, SC_P_SCU_GPIO0_07, + SC_FALSE); +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + /* There are two versions of the val board. The DDR4 version uses + * an internal PCIe clock. This is a way to tell the boards + * apart from their DDR configuration. */ + #if defined(BD_DDR_RET_NUM_REGION) && (BD_DDR_RET_NUM_REGION == 4) + rtn = BOARD_PARM_RTN_INTERNAL; + #else + rtn = BOARD_PARM_RTN_EXTERNAL; + #endif + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + rtn = BOARD_KS1_RESUME_USEC; + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + /* DC0 PLL0 spread spectrum config */ + case BOARD_PARM_DC0_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC0 PLL1 spread spectrum config */ + case BOARD_PARM_DC0_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL0 spread spectrum config */ + case BOARD_PARM_DC1_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC1 PLL1 spread spectrum config */ + case BOARD_PARM_DC1_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. - DDR_00060 */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + #if defined(BD_DDR_RET_NUM_DRC) && (BD_DDR_RET_NUM_DRC == 1U) + if(rsrc == SC_R_DRC_1) + { + rtn = SC_FALSE; + } + #endif + #ifdef EMUL + if(rsrc == SC_R_PMIC_0) + { + rtn = SC_FALSE; + } + if(rsrc == SC_R_PMIC_1) + { + rtn = SC_FALSE; + } + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } + #endif + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + static uint32_t board_ddr_ret_buf4[BD_DDR_RET_REGION4_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + static uint32_t board_ddr_ret_buf5[BD_DDR_RET_REGION5_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + static uint32_t board_ddr_ret_buf6[BD_DDR_RET_REGION6_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 }, + #endif + #ifdef BD_DDR_RET_REGION4_SIZE + { BD_DDR_RET_REGION4_ADDR, BD_DDR_RET_REGION4_SIZE, board_ddr_ret_buf4 }, + #endif + #ifdef BD_DDR_RET_REGION5_SIZE + { BD_DDR_RET_REGION5_ADDR, BD_DDR_RET_REGION5_SIZE, board_ddr_ret_buf5 }, + #endif + #ifdef BD_DDR_RET_REGION6_SIZE + { BD_DDR_RET_REGION6_ADDR, BD_DDR_RET_REGION6_SIZE, board_ddr_ret_buf6 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + else if (rm_is_resource_avail(SC_R_DRC_1)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_1, + SC_PM_CLK_SLV_BUS, &rate); + } + else + { + ; /* Intentional empty else */ + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + /* DDR_00040 */ + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. See DDR_00010. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + /* Supports stress test tool - DDR_00070 */ + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + case BOARD_DDR1_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(1); + #else + // Run vref training + DRAM_VREF_training_sw(1); + #endif + break; + default: + /* DDR_00020 */ + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + sc_rm_pt_t pt_m4_1 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[7U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_7A, + SC_R_MU_8B, + SC_R_GPT_4, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[2U] = + { + RM_RANGE(SC_P_M40_I2C0_SCL, SC_P_M40_GPIO0_01) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x0887FFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Create M4 1 partition */ + if (rm_is_resource_avail(SC_R_M4_1_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[8U] = + { + SC_R_IRQSTR_M4_1, + SC_R_MU_6B, + SC_R_MU_7B, + SC_R_MU_9B, + SC_R_GPT_3, + RM_RANGE(SC_R_CAN_0, SC_R_CAN_2), + SC_R_FSPI_0 + }; + + /* List of pads */ + static const sc_pad_t pad_list[6U] = + { + RM_RANGE(SC_P_M41_I2C0_SCL, SC_P_M41_GPIO0_01), + RM_RANGE(SC_P_FLEXCAN0_RX, SC_P_FLEXCAN2_TX), + RM_RANGE(SC_P_QSPI0A_DATA0, SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088800000ULL, 0x08FFFFFFFULL}, + {0x008181000ULL, 0x008280FFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_1, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_1_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_1, "MCU1"); + + /* Allow M4 1 to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_m4_1, SC_RM_PERM_SEC_RW)); + + /* Move M4 1 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x038FE0000ULL, + 0x038FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_1, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_1, SC_PT)); + } + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[4U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4), + RM_RANGE(SC_R_M4_1_PID1, SC_R_M4_1_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + if (pt_m4_1 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_1, + SC_RM_PERM_FULL)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_1_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + uint8_t mode; + + if (pmic_ver.device_id == PF100_DEV_ID) + { + mode = SW_MODE_PWM_STBY_PWM; + } + else + { + mode = SW_RUN_PWM | SW_STBY_PWM; + } + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + mode)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + mode = 0U; + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + mode)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + uint8_t mode; + + if (pmic_ver.device_id == PF100_DEV_ID) + { + mode = SW_RUN_MODE; + } + else + { + mode = REG_RUN_MODE;/* run mode programming */ + } + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(pmic_id[idx], pmic_reg[idx], new_volt, + mode)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ + static uint32_t vdd_memc_mode = 0U; + + if (mode == SC_PM_PW_MODE_STBY) + { + /* + * System standby (KS1) entry allows VDD_MEMC to be gated off. + * Save current mode and switch off supply. + */ + if (PMIC_GET_MODE(PMIC_1_ADDR, PF8100_SW5, &vdd_memc_mode) + == SC_ERR_NONE) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, SW_STBY_OFF + | SW_RUN_OFF); + } + } + else if (mode == SC_PM_PW_MODE_ON) + { + /* + * System standby (KS1) exit should switch on VDD_MEMC. Restore + * previous mode saved during KS1 entry. + */ + if (vdd_memc_mode != 0U) + { + (void) PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW5, vdd_memc_mode); + } + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + switch (idx) + { + case BRD_R_BOARD_R0 : /* PTN5150 (use SC_R_BOARD_R0) */ + if (pmic_ver.device_id == PF100_DEV_ID) + { + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_2_ADDR, VGEN6, + 3000, SW_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_2_ADDR, VGEN6, + VGEN_MODE_ON)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_2_ADDR, VGEN6, + VGEN_MODE_OFF)); + } + } + else + {/* PF8100_dual Card */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_LDO1, + 3000, REG_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_EN_STBY_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO1, + RUN_OFF_STBY_OFF)); + } + } + break; + case BRD_R_BOARD_R2 : /* HSIC (use SC_R_BOARD_R2) */ + if (pmic_ver.device_id == PF100_DEV_ID) + { + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, VGEN1, + 1200, SW_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, VGEN1, + VGEN_MODE_ON)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, VGEN1, + VGEN_MODE_OFF)); + } + } + else + {/* PF8100_dual Card */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW7, + 1200, REG_RUN_MODE)); + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW7, + RUN_EN_STBY_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_SW7, + RUN_OFF_STBY_OFF)); + } + } + break; + case BRD_R_BOARD_R3 : /* USDHC2 on Base Board */ + if (pmic_card == PF8100_DUAL) + { + if (to_mode > SC_PM_PW_MODE_OFF) + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_EN_STBY_EN | VSELECT_EN)); + } + else + { + BRD_ERR(PMIC_SET_MODE(PMIC_1_ADDR, PF8100_LDO2, + RUN_OFF_STBY_OFF)); + } + } + break; + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + ; /* Intentional empty default */ + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if ((resource == SC_R_M4_0_PID0) || (resource == SC_R_M4_1_PID0)) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm0 = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm1 = + SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_2 : + if (ctrl == SC_C_TEMP_HI) + { + if (pmic_card == PF100_TRIPLE) + { + temp_alarm2 = + SET_PMIC_TEMP_ALARM(PMIC_2_ADDR, val); + } + else + { + temp_alarm2 = val; /* Fake the set if not there */ + } + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + /* PMIC 0 */ + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm0; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + /* PMIC 1 */ + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_1_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm1; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_1_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_2 : + if (ctrl == SC_C_TEMP) + { + if (pmic_card == PF100_TRIPLE) + { + *val = GET_PMIC_TEMP(PMIC_2_ADDR); + } + else + { + err = SC_ERR_PARM; + } + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm2; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_2_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R0 : + if (ctrl == SC_C_VOLTAGE) + { + /* For debug, get voltage */ + if (pmic_card == PF100_TRIPLE) + { + (void) PMIC_GET_VOLTAGE(PMIC_2_ADDR, VGEN6, val, + SW_RUN_MODE); + } + else + { + (void) PMIC_GET_VOLTAGE(PMIC_1_ADDR, PF8100_LDO1, + val, REG_RUN_MODE); + } + } + else + { + err = SC_ERR_PARM; + } + break; + /* Board R7 - only here for testing */ + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Handle IRQ */ + switch (pmic_card) + { + case PF100_TRIPLE : + /* Temp alarm from PMIC 2 */ + if (PMIC_IRQ_SERVICE(PMIC_2_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC2_HIGH, SC_PT_ALL); + } + /* Temp alarm from PMIC 1 */ + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC1_HIGH, SC_PT_ALL); + } + /* Temp alarm from PMIC 0 */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC0_HIGH, SC_PT_ALL); + } + break; + case PF8100_DUAL : + /* Temp alarm from PMIC 1 */ + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC1_HIGH, SC_PT_ALL); + } + /* Temp alarm from PMIC 0 */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC0_HIGH, SC_PT_ALL); + } + break; + default : + ; /* Intentional empty default */ + break; + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + /* Probe for PMIC 0 */ + if (pmic_get_device_id(PMIC_0_ADDR) == PF100_DEV_ID) + { /* probe for pmic at 0x8 */ + board_print(2, "Found Triple PF100 PMIC Card \n"); + pmic_card = PF100_TRIPLE; + PMIC_TYPE = PF100; + /* Probe for PMIC 1 */ + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + + /* Configure temp alarms */ + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + temp_alarm2 = SET_PMIC_TEMP_ALARM(PMIC_2_ADDR, PMIC_TEMP_MAX); + + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, SW1AB, SW_MODE_PWM_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, SW1C, SW_MODE_PWM_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_2_ADDR, SW3A, SW_MODE_PWM_STBY_PWM)); + } + /* Isolate Device Family to support 8100 & 8200 */ + else if ((pmic_get_device_id(PMIC_1_ADDR) & FAM_ID_MASK) == PF8X00_FAM_ID) + { + pmic_card = PF8100_DUAL; + PMIC_TYPE = PF8100; + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + board_print(2, "Found Dual PF8100 PMIC Card Rev:0x%x\n",pmic_ver.si_rev); + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + + err = SC_ERR_NONE; + + /* ignore OV/UV for A0/B0 & bypass current limit for A0 */ + err |= pmic_ignore_current_limit(PMIC_0_ADDR, pmic_ver); + err |= pmic_ignore_current_limit(PMIC_1_ADDR, pmic_ver); + + err |= pmic_match_otp(PMIC_0_ADDR, pmic_ver); + err |= pmic_match_otp(PMIC_1_ADDR, pmic_ver); + + if(pmic_ver.si_rev == PF8100_A0_REV) + { + /* set Regulation modes for MAIN and 1.8V rails */ + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, SW_RUN_PWM + | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW7, SW_RUN_PWM + | SW_STBY_PWM)); + } + + if (err != SC_ERR_NONE) + { + error_print("PMIC Initialization Error!\n"); + + #ifndef EMUL + /* Loop so WDOG will expire */ + HALT; + #else + return; + #endif + } + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, + 800, REG_STBY_MODE)); + } + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + err |= pf8100_pmic_wdog_enable(PMIC_1_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + } + /* Isolate Device Family to support 8100 & 8200 */ + else if ((pmic_get_device_id(PMIC_0_ADDR) & FAM_ID_MASK) + == PF8X00_FAM_ID) + { + board_print(2, "Found Single PF8100 PMIC Card\n"); + error_print("Single PF8100 PMIC NOT Supported!\n"); + + #ifndef EMUL + /* Loop so WDOG will expire */ + HALT; + #else + return; + #endif + } + else + { + error_print("PMIC Card not found!\n"); + + #ifndef EMUL + /* Loop so WDOG will expire */ + HALT; + #else + return; + #endif + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + +#ifndef EMUL +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address, pmic_version_t ver) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + /* Only bypass current limit on A0 silicon */ + if (ver.si_rev == PF8100_A0_REV) + { + val |= 0x20U; /* set xx_ILIM_BYPASS */ + } + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check correct version of OTP for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver) +{ + uint8_t reg_value = 0U; + uint16_t prog_id, match; + sc_err_t err = SC_ERR_NONE; + + if (address == PMIC_0_ADDR) + { + match = EP_PROG_ID; + } + else + { + match = EQ_PROG_ID; + } + + /* Read Prog ID */ + err |= PMIC_REGISTER_ACCESS(address, 0x2, SC_FALSE, ®_value); + prog_id = (((uint16_t)reg_value << 4U) & 0x0F00U); + err |= PMIC_REGISTER_ACCESS(address, 0x3U, SC_FALSE, ®_value); + prog_id |= reg_value; + + /* test against calibration fusing */ + if (OTP_PROG_FUSE_VERSION_1_7V_CAL != 0U) + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + /* if C1 PMIC test for correct OTP */ + if(prog_id != match){/* allow only 1.7v OTP */ + error_print("PMIC INVALID!\n"); + } + } + else + { + error_print("PMIC INVALID!\n"); + } + } + else + { + if (ver.si_rev >= PF8100_C1_SI_REV) + { + if(prog_id == match){/* prohibit only 1.7V OTP */ + error_print("PMIC INVALID!\n"); + } + } + } + + return err; +} + +#endif + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A53 : + pmic_init(); + if (pmic_card == PF100_TRIPLE) + { + pmic_id[0] = PMIC_2_ADDR; + pmic_reg[0] = SW2; + *num_regs = 1U; + } + else + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW5; + *num_regs = 1U; + } + break; + case SC_SUBSYS_A72 : + pmic_init(); + if (pmic_card == PF100_TRIPLE) + { + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = SW3A; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = SW3B; + *num_regs = 2U; + } + else + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + if (pmic_card == PF100_TRIPLE) + { + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = SW1AB; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = SW1C; + *num_regs = 2U; + } + else + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW1; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW2; + *num_regs = 2U; + } + break; + case SC_SUBSYS_GPU_1 : + pmic_init(); + if (pmic_card == PF100_TRIPLE) + { + pmic_id[0] = PMIC_2_ADDR; + pmic_reg[0] = SW1AB; + pmic_id[1] = PMIC_2_ADDR; + pmic_reg[1] = SW1C; + *num_regs = 2U; + } + else + {/* PF8100_dual Card */ + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + break; + default : + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qm_val/board.h b/platform/board/mx8qm_val/board.h new file mode 100755 index 0000000..0c59775 --- /dev/null +++ b/platform/board/mx8qm_val/board.h @@ -0,0 +1,125 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +#define PMIC_0_ADDR 0x8U +#define PMIC_1_ADDR 0x9U +#define PMIC_2_ADDR 0xAU + +#define PMIC_TEMP_MAX 135U + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +#define SW1ABC_STEP 25U +#define SW2_STEP 25U +#define SW3_STEP 25U +#define PMIC0_SW4_STEP 25U +#define PMIC1_SW4_STEP 50U +#define VGEN12_STEP 50U +#define VGEN3456_STEP 100U + +#define PF100_TRIPLE 0U +#define PF8100_DUAL 1U +#define PF8100_SINGLE 2U + +#define PF8100_C1_SI_REV 0x31U +#define EP_PROG_ID 0x0417U +#define EQ_PROG_ID 0x0418U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qm_val/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qm_val/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..896973b --- /dev/null +++ b/platform/board/mx8qm_val/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,143 @@ +DEFINE BD_DDR_RET_NUM_DRC 2 // Number of DRCs in the SoC + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_val/dcd/ddr_stress_test_parser_DRC0_only.cfg b/platform/board/mx8qm_val/dcd/ddr_stress_test_parser_DRC0_only.cfg new file mode 100755 index 0000000..119af25 --- /dev/null +++ b/platform/board/mx8qm_val/dcd/ddr_stress_test_parser_DRC0_only.cfg @@ -0,0 +1,142 @@ +DEFINE BD_DDR_RET_NUM_DRC 1 // One DRC in the SoC; DRC0 only + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + diff --git a/platform/board/mx8qm_val/dcd/imx8qm_dcd_1.6GHz.cfg b/platform/board/mx8qm_val/dcd/imx8qm_dcd_1.6GHz.cfg new file mode 100755 index 0000000..cb0c950 --- /dev/null +++ b/platform/board/mx8qm_val/dcd/imx8qm_dcd_1.6GHz.cfg @@ -0,0 +1,590 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x801C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x03201901 +DATA 4 DDR_PHY_PTR1_0 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x03201901 +DATA 4 DDR_PHY_PTR1_1 0x027100E1 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00032 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x000186A0 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000064 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00002710 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00032 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000064 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x64032010, 0x4E201C20, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_val/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg b/platform/board/mx8qm_val/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg new file mode 100755 index 0000000..eb1ae49 --- /dev/null +++ b/platform/board/mx8qm_val/dcd/imx8qm_dcd_1.6GHz_nocbt.cfg @@ -0,0 +1,513 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000213 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x006100E0 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x000000E6 // txsr +DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 +DATA 4 DDRC_DFITMG0_SHADOW_1 0x00808000 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------=------------ +// Set-up DRAM 1 PHY Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x001C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_1 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x33 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF +DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x03300640 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006CA1CC // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x01C02B0F // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0030D400 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000C80 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x0004E200 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x03300640 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 +// Launch DRAM 1 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// Launch a second time DRAM initialization due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Wait (second time) DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qm_val/dcd/imx8qm_dcd_800MHz.cfg b/platform/board/mx8qm_val/dcd/imx8qm_dcd_800MHz.cfg new file mode 100755 index 0000000..0fc3ead --- /dev/null +++ b/platform/board/mx8qm_val/dcd/imx8qm_dcd_800MHz.cfg @@ -0,0 +1,624 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x180000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 +DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 +DEFINE BD_DDR_RET_REGION4_SIZE 64 +DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 +DEFINE BD_DDR_RET_REGION5_SIZE 16 +DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 +DEFINE BD_DDR_RET_REGION6_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 23 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to 800MHz. */ + uint32_t rate2 = SC_400MHZ; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &rate2); +} +else +{ +/* Change to div4 output */ +DATA 4 0x41A43800 0x4C000000 +DATA 4 0x41D03800 0x4C000000 +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_0 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +/* DRAM 1 controller initialization */ +DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_1 0x00000111 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_1 0x00C35000 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_1 0x0021F000 +DATA 4 DDRC_RFSHTMG_1 0x00300070 // tREFI, tRFC +DATA 4 DDRC_INIT0_1 0x4002030F // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_1 0x00500000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_1 0x00240012 // MR1, MR2 +DATA 4 DDRC_INIT4_1 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_1 0x10100D11 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_1 0x0003041A // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_1 0x0408100F // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_1 0x00606000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_1 0x08040408 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_1 0x02030606 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_1 0x02020004 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_1 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_1 0x00020310 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_1 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_1 0x00000073 // txsr +DATA 4 DDRC_ZQCTL0_1 0x0190000C // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_1 0x014030D4 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_1 0x048D8206 // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_1 0x00000B04 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_1 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRCTL_1 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_PWRTMG_1 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x06FF0001 +DATA 4 DDRC_HWLPCTL_1 0x06FF0001 + +DATA 4 DDRC_SCHED_0 0x00001F05 // CAM (32 entries) +DATA 4 DDRC_SCHED_1 0x00001F05 // CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 +DATA 4 DDRC_DFILPCFG0_1 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41a40208 0x1 +DATA 4 0x41d00208 0x1 +DATA 4 0x41a40044 0x4 +DATA 4 0x41d00044 0x4 +DATA 4 0x41a40204 0x1 +DATA 4 0x41d00204 0x1 + +//------------------------------------------- +// Configure PHY registers for PHY initialization +//-------------------------------------------- +/* DRAM 0 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register + +/* DRAM 1 controller configuration begin */ +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_1 0x000F0009 +DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_1 0x00F06AAC // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_1 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_1 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_1 0x811C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x811C0000 +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_1 0x008A2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus + + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 +DATA 4 DDR_PHY_PIR_1 0x10 +DATA 4 DDR_PHY_PIR_1 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +/* DRAM 0 */ +DATA 4 DDR_PHY_PLLCR0_0 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41a40204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x01A00C81 +DATA 4 DDR_PHY_PTR1_0 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +/* DRAM 1 */ +DATA 4 DDR_PHY_PLLCR0_1 0xA11C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA11C0000 +// Switch to boot frequency +DATA 4 0x41d00208 0x1 +DATA 4 0x41d00504 0x00800000 +DATA 4 0x41d00204 0x1 +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_1 0x01A00C81 +DATA 4 DDR_PHY_PTR1_1 0x01390071 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_1 0x22 +DATA 4 DDR_PHY_PIR_1 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00019 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +/* DRAM 1 */ +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_1 0x24 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_1 0x12 // Set RL/WL +DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT +DATA 4 DDR_PHY_MR13_1 0x40 +DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_1 0x48 +DATA 4 DDR_PHY_MR14_1 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_1 0x08221108 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_1 0x2820040C // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_1 0x006640E6 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_1 0x01800301 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_1 0x00E02B09 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_1 0x11330F09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_1 0x000A3DEF +DATA 4 DDR_PHY_PTR3_1 0x0000C350 // tDINIT0 +DATA 4 DDR_PHY_PTR4_1 0x00000032 // tDINIT1 +DATA 4 DDR_PHY_PTR5_1 0x00001388 // tDINIT2 +DATA 4 DDR_PHY_PTR6_1 0x00B00019 // tDINIT4, tDINIT3 (1us) +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_1 0x07F0016F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_1 0x4 +DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH +DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 +DATA 4 DDR_PHY_PGCR4_1 0x001900B1 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x180 +DATA 4 DDR_PHY_PIR_1 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- + +/* DRAM 0 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +/* DRAM 1 */ +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_1 0x00000032 +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_1 0x100 +DATA 4 DDR_PHY_PIR_1 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// DRAM 1 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x32019010, 0x27100E10, 2); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN +DATA 4 DDR_PHY_DTCR0_1 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +DATA 4 DDR_PHY_PIR_1 0x200 +DATA 4 DDR_PHY_PIR_1 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 + +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 +// Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_1 0x400 +DATA 4 DDR_PHY_PIR_1 0x401 + +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 + +// Wait Read DQS training to complete PHY1 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY1 +DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_1 0x0010F800 +DATA 4 DDR_PHY_PIR_1 0x0010F801 + +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); +RDBI_bit_deskew(1); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +DRAM_VREF_training_hw(1); +#else +// Run vref training +DRAM_VREF_training_sw(0); +DRAM_VREF_training_sw(1); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 +CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 +//DQS Drift Registers PHY1 +CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 +// Enable DQS drift detection PHY1 +DATA 4 DDR_PHY_DQSDR0_1 0x20188005 +DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_1 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41A40504 0x400 +DATA 4 0x41D00504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 +CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + + + + + + + + + + + + + + + + + + + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + diff --git a/platform/board/mx8qm_val/dcd/imx8qm_dcd_emul.cfg b/platform/board/mx8qm_val/dcd/imx8qm_dcd_emul.cfg new file mode 100755 index 0000000..26e3098 --- /dev/null +++ b/platform/board/mx8qm_val/dcd/imx8qm_dcd_emul.cfg @@ -0,0 +1,214 @@ +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// Reset Should not be needed for ZEBU. +DATA 4 0x41a40044 0x8 +DATA 4 0x41d00044 0x8 + +// ddrc_lpddr4_init(0) +DATA 4 0x5C000000 0xC3080020 +DATA 4 0x5C000064 0x006100E0 +DATA 4 0x5C0000D0 0x40020010 +DATA 4 0x5C0000D4 0x00100000 +DATA 4 0x5C0000DC 0x0054002D +DATA 4 0x5C0000E0 0x00310000 +DATA 4 0x5C0000F4 0x000006CF +DATA 4 0x5C000100 0x1A201B22 +DATA 4 0x5C000104 0x00060633 +DATA 4 0x5C000108 0x070E1014 +DATA 4 0x5C00010C 0x0170C00C +DATA 4 0x5C000110 0x0F04080F +DATA 4 0x5C000114 0x03040C0C +DATA 4 0x5C000118 0x02020007 +DATA 4 0x5C00011C 0x00000401 +DATA 4 0x5C000130 0x00020610 +DATA 4 0x5C000134 0x0C100002 +DATA 4 0x5C000138 0x000000E6 +DATA 4 0x5C000180 0x03200018 +DATA 4 0x5C000184 0x02800100 +DATA 4 0x5C000190 0x049C820C +DATA 4 0x5C000194 0x00060303 +DATA 4 0x5C0001B4 0x00001A0A +DATA 4 0x5C0001B0 0x00000005 +DATA 4 0x5C0001A0 0x80400003 +DATA 4 0x5C0001A4 0x00010002 +DATA 4 0x5C0001A8 0x80000000 +DATA 4 0x5C000200 0x00000017 +DATA 4 0x5C000204 0x00080808 +DATA 4 0x5C000214 0x07070707 +DATA 4 0x5C000218 0x07070707 +DATA 4 0x5C000244 0x00002211 +DATA 4 0x5C000490 0x00000001 +DATA 4 0x5C002190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 +//DATA 4 0x5C0001B0 0x00000004 +//DATA 4 0x5C0000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(0) +DATA 4 0x5C010100 0x0000040D +DATA 4 0x5C010018 0x00F0DA09 +DATA 4 0x5C01001C 0x050A1080 +DATA 4 0x5C010040 0x64032010 +DATA 4 0x5C010044 0x0D701C20 +DATA 4 0x5C010068 0x08000000 +DATA 4 0x5C0117C4 0x08000000 +DATA 4 0x5C010680 0x001FEC58 + +//ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00000040 +DATA 4 0x5C010004 0x00000041 + +//ddr_phy_lpddr4_dram_init(0) +DATA 4 0x5C010184 0x00000054 +DATA 4 0x5C010188 0x0000002D +DATA 4 0x5C01018C 0x00000031 +DATA 4 0x5C010110 0x1044220C +DATA 4 0x5C010114 0x28408C17 +DATA 4 0x5C010118 0x003C01CC +DATA 4 0x5C01011C 0x01800604 +DATA 4 0x5C010120 0x01C0000C +DATA 4 0x5C010124 0x00651D10 +DATA 4 0x5C01004C 0x00007D00 +DATA 4 0x5C010050 0x00000C90 +DATA 4 0x5C010054 0x00007D00 +DATA 4 0x5C010058 0x03000641 +DATA 4 0x5C010500 0x30070800 +DATA 4 0x5C010514 0x09000000 +DATA 4 0x5C010528 0xF0032019 +DATA 4 0x5C01052C 0x07F00173 +DATA 4 0x5C0117EC 0x00081800 +DATA 4 0x5C0117F0 0x09000000 +DATA 4 0x5C0117DC 0x013E4091 + +//ddr_phy_wait_init_done(0) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init(0) +DATA 4 0x5C010004 0x00040000 +DATA 4 0x5C010004 0x00040001 + +// SECOND DRC SYSTEM + +// ddrc_lpddr4_init(1) +DATA 4 0x5C100000 0xC3080020 +DATA 4 0x5C100064 0x006100E0 +DATA 4 0x5C1000D0 0x40020010 +DATA 4 0x5C1000D4 0x00100000 +DATA 4 0x5C1000DC 0x0054002D +DATA 4 0x5C1000E0 0x00310000 +DATA 4 0x5C1000F4 0x000006CF +DATA 4 0x5C100100 0x1A201B22 +DATA 4 0x5C100104 0x00060633 +DATA 4 0x5C100108 0x070E1014 +DATA 4 0x5C10010C 0x0170C00C +DATA 4 0x5C100110 0x0F04080F +DATA 4 0x5C100114 0x03040C0C +DATA 4 0x5C100118 0x02020007 +DATA 4 0x5C10011C 0x00000401 +DATA 4 0x5C100130 0x00020610 +DATA 4 0x5C100134 0x0C100002 +DATA 4 0x5C100138 0x000000E6 +DATA 4 0x5C100180 0x03200018 +DATA 4 0x5C100184 0x02800100 +DATA 4 0x5C100190 0x049C820C +DATA 4 0x5C100194 0x00060303 +DATA 4 0x5C1001B4 0x00001A0A +DATA 4 0x5C1001B0 0x00000005 +DATA 4 0x5C1001A0 0x80400003 +DATA 4 0x5C1001A4 0x00010002 +DATA 4 0x5C1001A8 0x80000000 +DATA 4 0x5C100200 0x00000017 +DATA 4 0x5C100204 0x00080808 +DATA 4 0x5C100214 0x07070707 +DATA 4 0x5C100218 0x07070707 +DATA 4 0x5C100244 0x00002211 +DATA 4 0x5C100490 0x00000001 +DATA 4 0x5C102190 0x00808000 + +// Correct CLR settings +CLR_BIT 4 DDRC_DFIMISC_1 0x00000001 +CLR_BIT 4 DDRC_INIT0_1 0xC0000000 +//DATA 4 0x5C1001B0 0x00000004 +//DATA 4 0x5C1000D0 0x00020010 + +// ddr_phy_lpddr4_phy_init(1) +DATA 4 0x5C110100 0x0000040D +DATA 4 0x5C110018 0x00F0DA09 +DATA 4 0x5C11001C 0x050A1080 +DATA 4 0x5C110040 0x64032010 +DATA 4 0x5C110044 0x0D701C20 +DATA 4 0x5C110068 0x08000000 +DATA 4 0x5C1117C4 0x08000000 +DATA 4 0x5C110680 0x001FEC58 + +//ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00000040 +DATA 4 0x5C110004 0x00000041 + + +//ddr_phy_lpddr4_dram_init(1) +DATA 4 0x5C110184 0x00000054 +DATA 4 0x5C110188 0x0000002D +DATA 4 0x5C11018C 0x00000031 +DATA 4 0x5C110110 0x1044220C +DATA 4 0x5C110114 0x28408C17 +DATA 4 0x5C110118 0x003C01CC +DATA 4 0x5C11011C 0x01800604 +DATA 4 0x5C110120 0x01C0000C +DATA 4 0x5C110124 0x00651D10 +DATA 4 0x5C11004C 0x00007D00 +DATA 4 0x5C110050 0x00000C90 +DATA 4 0x5C110054 0x00007D00 +DATA 4 0x5C110058 0x03000641 +DATA 4 0x5C110500 0x30070800 +DATA 4 0x5C110514 0x09000000 +DATA 4 0x5C110528 0xF0032019 +DATA 4 0x5C11052C 0x07F00173 +DATA 4 0x5C1117EC 0x00081800 +DATA 4 0x5C1117F0 0x09000000 +DATA 4 0x5C1117DC 0x013E4091 + +//ddr_phy_wait_init_done(1) +CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 + +// ddr_phy_launch_init(1) +DATA 4 0x5C110004 0x00040000 +DATA 4 0x5C110004 0x00040001 + +// RESET +DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DSC_SetReset(SC_DSC_DRC_1, BIT(RST_DDR_CRESETN), SC_TRUE); +//DATA 4 0x41a40044 0x4 +//DATA 4 0x41d00044 0x4 + +// dram_init_inst(0) +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// dram_init_inst(1) +CLR_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_1 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_1 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_1 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 +CHECK_BITS_SET 4 DDRC_STAT_1 0x1 + +//DATA 4 0x5C000320 0x00000000 +//DATA 4 0x5C0001B0 0x00000005 +//DATA 4 0x5C000320 0x00000001 +//DATA 4 0x5C100320 0x00000000 +//DATA 4 0x5C1001B0 0x00000005 +//DATA 4 0x5C100320 0x00000001 + diff --git a/platform/board/mx8qx_dxl_phantom/Makefile b/platform/board/mx8qx_dxl_phantom/Makefile new file mode 100755 index 0000000..0a95b08 --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/Makefile @@ -0,0 +1,61 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8dxl_dcd_emul +else + DDR_CON ?= imx8dxl_dcd_lpddr4_16bit_1.2GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + +ifeq ($(M),1) + OBJS += $(OUT)/board/pmic.o +endif + diff --git a/platform/board/mx8qx_dxl_phantom/board.bom b/platform/board/mx8qx_dxl_phantom/board.bom new file mode 100755 index 0000000..496815c --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/board.bom @@ -0,0 +1,9 @@ + +DRV2 += \ + pmic \ + pmic/pf8100 + +ifeq ($(M),1) + DRV2 += pmic/pf100 +endif + diff --git a/platform/board/mx8qx_dxl_phantom/board.c b/platform/board/mx8qx_dxl_phantom/board.c new file mode 100755 index 0000000..6319e65 --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/board.c @@ -0,0 +1,1668 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QX MEK board. + * + * @addtogroup MX8QX_MEK_BRD BRD: MX8QX MEK Board + * + * Module for MX8QX MEK board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00120 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/igpio/fsl_gpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" +#include "drivers/systick/fsl_systick.h" + +/* Local Defines */ + +/*! Memory size */ +#ifndef BD_DDR_SIZE + #define BD_DDR_SIZE SC_1GB +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U +#define BRD_R_BOARD_R3 6U +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 3 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif +#if DEBUG_UART == 2 + /*! Use alternate debug UART */ + #define ALT_DEBUG_SCU_UART +#endif +#if (defined(MONITOR) || defined(EXPORT_MONITOR) || defined(HAS_TEST) \ + || (DEBUG_UART == 1)) && !defined(DEBUG_TERM_EMUL) \ + && !defined(ALT_DEBUG_SCU_UART) + #define ALT_DEBUG_UART +#endif + +/*! Configure debug UART */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG LPUART_SC +#else + #define LPUART_DEBUG LPUART_MCU_0 +#endif + +/*! Configure debug UART instance */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG_INST 0U +#else + #define LPUART_DEBUG_INST 2U +#endif + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +#ifndef EMUL +static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver); +static sc_err_t pmic_update_timing(uint8_t address); +#endif +static void board_get_pmic_info(sc_sub_t ss, uint32_t *pmic_reg, + uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t temp_alarm; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + ss_print(3, "board_init(%d)\n", phase); + + if (phase == BOOT_PHASE_HW_INIT) + { + /* Remove SS not available on DXL */ + soc_ss_notavail(SC_SUBSYS_MIPI_0); + soc_ss_notavail(SC_SUBSYS_MIPI_1); + soc_ss_notavail(SC_SUBSYS_IMG); + soc_ss_notavail(SC_SUBSYS_CSI_0); + soc_ss_notavail(SC_SUBSYS_PI_0); + } + else if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_EARLY_INIT) + { + gpio_pin_config_t config; + config.direction = kGPIO_DigitalOutput; + + /* Power on GPIO */ + pm_force_resource_power_mode_v(SC_R_GPIO_1, SC_PM_PW_MODE_ON); + + /* Mux SPI2_SDO to GPIO */ + pad_force_mux(SC_P_SPI2_SDO, 4, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + + /* Toggle base board reset, >= 30nS */ + config.outputLogic = 0U; + GPIO_PinInit(GPIO1, 1U, &config); + SYSTICK_CycleDelay(SC_SYSTICK_NSEC_TO_TICKS(30U) + 1U); + GPIO_WritePinOutput(GPIO1, 1U, 1U); + + /* Latch output */ + pad_force_mux(SC_P_SPI2_SDO, 4, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_ON); + + /* Power off GPIO */ + pm_force_resource_power_mode_v(SC_R_GPIO_1, SC_PM_PW_MODE_OFF); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #if (defined(ALT_DEBUG_UART) || defined(ALT_DEBUG_SCU_UART)) \ + && !defined(DEBUG_TERM_EMUL) + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(ALT_DEBUG_SCU_UART) && !defined(DEBUG_TERM_EMUL) \ + && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Check if debug disabled */ + if (SCFW_DBG_READY == 0U) + { + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + } + #elif defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Use M4 UART if ALT_DEBUG_UART defined */ + /* Return if debug already enabled */ + if ((SCFW_DBG_READY == 0U) && (early_phase == SC_FALSE)) + { + sc_pm_clock_rate_t rate = SC_24MHZ; + static sc_bool_t banner = SC_FALSE; + + /* Configure pads */ + pad_force_mux(SC_P_ADC_IN2, 1, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + pad_force_mux(SC_P_ADC_IN3, 1, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + + /* Power and enable clock */ + pm_force_resource_power_mode_v(SC_R_SC_PID0, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DBLOGIC, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DB, SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + + /* Configure UART */ + main_config_debug_uart(LPUART_DEBUG, rate); + + if (banner == SC_FALSE) + { + debug_print(1, + "\nHello from SCU (Build %u, Commit %08x, %s %s)\n\n", + SCFW_BUILD, SCFW_COMMIT, SCFW_DATE, SCFW_TIME); + banner = SC_TRUE; + } + } + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ + /* Use M4 UART if ALT_DEBUG_UART defined */ + #if defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Return if debug already disabled */ + if (SCFW_DBG_READY != 0U) + { + /* Disable use of UART */ + SCFW_DBG_READY = 0U; + + // UART deinit to flush TX buffers + LPUART_Deinit(LPUART_DEBUG); + + /* Turn off UART */ + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_OFF); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + #ifdef ALT_DEBUG_UART + (void) rm_set_resource_movable(SC_PT, SC_R_M4_0_UART, SC_R_M4_0_UART, + SC_FALSE); + (void) rm_set_pad_movable(SC_PT, SC_P_ADC_IN3, SC_P_ADC_IN2, + SC_FALSE); + #endif + + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SCL, SC_P_PMIC_I2C_SDA, + SC_FALSE); + #ifdef ALT_DEBUG_SCU_UART + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_EXTERNAL; + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + if (OTP_KS1_07V_SUPPORT == 1U) /* KS1 0.7V support */ + { + rtn = BOARD_KS1_07V_RESUME_USEC; + } + else + { + rtn = BOARD_KS1_RESUME_USEC; + } + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (rsrc) + { + case SC_R_GPT_9 : + case SC_R_GPT_10 : + case SC_R_DSP_RAM : + case SC_R_IRQSTR_DSP : + case SC_R_PMIC_1 : + case SC_R_PMIC_2 : + rtn = SC_FALSE; + break; + default : + rtn = SC_TRUE; + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + /* Init the analog repeater from ROM stage, mandatory! */ + if (action == BOARD_DDR_COLD_INIT) + { + ANA_WRITE(0x01U, 12U, 0U, 0xef17U); //SC + ANA_WRITE(0x28U, 12U, 0U, 0xef17U); //VPU + ANA_WRITE(0x24U, 12U, 0U, 0xef13U); //DRC + } + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + default: + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Keep baseboard reset */ + BRD_ERR(rm_assign_pad(pt_boot, SC_PT, SC_P_SPI2_SDO)); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[9U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_8B, + SC_R_GPT_4, + RM_RANGE(SC_R_CAN_0, SC_R_CAN_2), + SC_R_FSPI_0, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[9U] = + { + RM_RANGE(SC_P_ADC_IN1, SC_P_ADC_IN2), + SC_P_ADC_IN5, + RM_RANGE(SC_P_FLEXCAN0_RX, SC_P_FLEXCAN0_TX), + SC_P_USB_SS3_TC1, + SC_P_USB_SS3_TC3, + RM_RANGE(SC_P_QSPI0A_DATA0, SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x08FFFFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[2U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + } + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + uint32_t pmic_reg = 0U; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, &pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, pmic_reg, + SW_RUN_PWM | SW_STBY_PWM)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, pmic_reg, + SW_RUN_OFF)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + uint32_t pmic_reg = 0U; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, &pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, pmic_reg, + new_volt, REG_RUN_MODE)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + switch (idx) + { + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + ; /* Intentional empty default */ + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + #endif + #ifdef ALT_DEBUG_UART + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if (resource == SC_R_M4_0_PID0) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR)) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC0_HIGH, + SC_PT_ALL); + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + + /* MEK board spec is for 1M baud for PMIC I2C bus */ + lpi2c_masterConfig.baudRate_Hz = 1000000U; + lpi2c_masterConfig.sdaGlitchFilterWidth_ns = 100U; + lpi2c_masterConfig.sclGlitchFilterWidth_ns = 100U; + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + temp_alarm = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, + PMIC_TEMP_MAX); + + /* Ignore OV/UV detection for A0/B0 & ignore current limit for A0 */ + err |= pmic_ignore_current_limit(PMIC_0_ADDR, pmic_ver); + + if(pmic_ver.si_rev == PF8100_A0_REV) + { + /* Set Regulation modes for MAIN and 1.8V rails */ + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW6, + SW_RUN_PWM | SW_STBY_PWM)); + } + + /* Adjust startup timing */ + err |= pmic_update_timing(PMIC_0_ADDR); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + + if (err != SC_ERR_NONE) + { + /* Loop so WDOG will expire */ + HALT; + } + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + uint32_t ks1_volt = 800U; + + if (OTP_KS1_07V_SUPPORT == 1U) + { + ks1_volt = 700U; + } + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, ks1_volt, + REG_STBY_MODE)); + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} +#ifndef EMUL +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + /* Only bypass current limit for A0 silicon */ + if (ver.si_rev == PF8100_A0_REV) + { + val |= 0x20U; /* set xx_ILIM_BYPASS */ + } + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update power timing for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_update_timing(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + + /* + * Add 60ms stable time for power down SW5/6/7/LDO2 on i.mx8QXP-MEK + * board, otherwise system may reboot fail by mmc not power off + * clean + */ + if (address == PMIC_0_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 0 */ + err |= PMIC_REGISTER_ACCESS(address, 0x6F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else + { + /* Return error */ + err = SC_ERR_PARM; + } + + return err; +} + +#endif + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss, uint32_t *pmic_reg, + uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A35 : + pmic_init(); + *pmic_reg = PF8100_SW3; + *num_regs = 1U; + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + *pmic_reg = PF8100_SW3; + *num_regs = 1U; + break; + default: + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qx_dxl_phantom/board.h b/platform/board/mx8qx_dxl_phantom/board.h new file mode 100755 index 0000000..b3555e9 --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/board.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC pf8100 +#define PMIC_0_ADDR 0x8U + +#define PMIC_TEMP_MAX 135U + +#define PF8100_REGULATORS 12U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U + +/* + * Resume from KS1 ramps VDD_MAIN 300 mV (700 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 300 mV / 7.813 mV/us = 38.4 us ==> 39 us + * + */ +#define BOARD_KS1_07V_RESUME_USEC 39U + +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qx_dxl_phantom/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qx_dxl_phantom/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..ec954a4 --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,129 @@ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + + diff --git a/platform/board/mx8qx_dxl_phantom/dcd/imx8dxl_dcd_emul.cfg b/platform/board/mx8qx_dxl_phantom/dcd/imx8dxl_dcd_emul.cfg new file mode 100755 index 0000000..b5b9d82 --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/dcd/imx8dxl_dcd_emul.cfg @@ -0,0 +1,263 @@ +/* +** ################################################################### +** +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + + +// DSC RESET +// First reset ? ZEBU dont know if we need this first reset. 1 +//DATA 4 0x41C80208 0x1 +//DATA 4 0x41C80044 0x8 +//DATA 4 0x41C80204 0x1 + +//ddrc_lpddr4_init(inst); + + // This is for lpddr4 controller 600MHz 1.67ns and ddr 1200MHz 0.83ns +DATA 4 DDRC_MSTR_0 0x03080020 // Set LPDDR4, BL = 16 and active ranks = 2 +DATA 4 DDRC_RFSHTMG_0 0x0049006D // tREFI noroundup(3.904us/tCK)/2 36 = 24, tRFC 180ns RoundUp(tRFCmin/tCK)/2 (180/0.83)/2 134 = 86 +DATA 4 DDRC_INIT0_0 0x0002000c // post cke roundup(2us/tCK)/2 pre_cke = 2ms is too long - LPDDR4 model hacked for 20us 00-SDRAM initialization routine is run after power up . 00 and 10 the same ? +DATA 4 DDRC_INIT1_0 0x000c0000 // dram_rstn - LPDDR4 model hacked for 20us; +DATA 4 DDRC_INIT3_0 0x00440024 // MR1=0x44: nWR=24 ? BL=16; MR2=0x24: RL=24 WL=12 ? +DATA 4 DDRC_INIT4_0 0x00310000 // MR3, MR13 PDDS 110 PU-CAL VddQ/3 +DATA 4 DDRC_RANKCTL_0 0x000006cf // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1519041a // wr2pr roundup((WL 12 + BL/2 8 + nWR 18ns)/2) = 20 hex 14 , tFAW (40ns /2) 25 hex 19 , tRASmax 8.7885us 4 , tRASmin 42ns (42ns/tCK)/2 26 hex 19 +DATA 4 DDRC_DRAMTMG1_0 0x00040526 // tXP 7.5ns roundup(tXP/2) 4, rd2pre roundup((BL/2 +8ns - 8)/2) = 5 , tRC 42ns +21ns roundup(63ns/2) = 38 hex +DATA 4 DDRC_DRAMTMG2_0 0x060b0e11 // WL 12/2, RL 24/2, rd2wr roundup((RL 24 +BL/2 8 +RU tDQSCK 3.6ns/0.83ns 4.3 +WR_PREAMBLE 2tck + RD_POSTAMBLE 0.5tck -WL 12)/2) = 14, wr2rd RU(WL 12 +BL/2 8+tWTR 10ns +1)/2 17 hex +DATA 4 DDRC_DRAMTMG3_0 0x0170c000 // tmrw tMRW ? tMRWCKEL 10CK, tmrd 10tck, tmod present on DDR3/4 only +DATA 4 DDRC_DRAMTMG4_0 0x0b04070d // trcd 18ns 11, tccd 8tck, trrd 10ns 7, trp 21ns 13 +DATA 4 DDRC_DRAMTMG5_0 0x03040305 // tcksrx 3tck, tcksre 5tck, tckesr 7.5ns tSR TBD, tcke 7.5/0.83/2 +DATA 4 DDRC_DRAMTMG6_0 0x00000004 // tckdpde, tckdpdx, tckcsx 7.5ns +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde 5tck, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE 3tck, tCKEHCMD (=tXP?) ? +DATA 4 DDRC_DRAMTMG13_0 0x00100002 // tODTLoff ODT disable, tCCDMW 4*8tck 16, tPPD 4tCK +DATA 4 DDRC_DRAMTMG14_0 0x00000039 // txsr tRFCAB 180ns+ 7.5ns +DATA 4 DDRC_ZQCTL0_0 0x025b0012 // tZQCAL 1us, tZQLAT 30ns 18 +DATA 4 DDRC_ZQCTL1_0 0x03d72e68 // tZQReset 50ns f, tzq_short_interval 0.4s lpddr3 ? +DATA 4 DDRC_DFITMG0_0 0x0498820a // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001608 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x80400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x00010002 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000016 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080202 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP2_0 0x02020000 +DATA 4 DDRC_ADDRMAP3_0 0x02020202 +DATA 4 DDRC_ADDRMAP4_0 0x00001f1f // addrmap_col_b11, addrmap_col_b10 +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0f070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 + +// These should not be here +//DATA 4 DDRC_ADDRMAP1_0 0x00171717 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +//DATA 4 DDRC_ADDRMAP5_0 0x03030303 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +//DATA 4 DDRC_ADDRMAP6_0 0x03030303 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 + +DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// in ddrc_init_inst() +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +// As DRAM init sequence will be run by controller set 0x0 to skip_dram_init field +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 + + +// Do we need this as well? Didnt need to set before ZEBU 2 +DATA 4 DDRC_PWRCTL_0 0x10D + +// Toggle Reset ... ZEBU NEED THIS? 3 +//DATA 4 0x41C80208 0x1 +//DATA 4 0x41C80044 0x4 +//DATA 4 0x41C80204 0x1 + + //------------------------------------------- + // Configure registers for PHY initialization + // Timings are computed for a PHY at 600MHz (DRAM at 1200MHz) 600MHz 1.67ns ddr 1200MHz 0.83ns + //------------------------------------------- + +//ddr_phy_lpddr4_phy_init() + + // Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank + + // Set-up PHY General Configuration Register + // PGCR0,1,4,5,6,7 are untouched +DATA 4 DDR_PHY_PGCR0_0 0x87001e00 // address copy +DATA 4 DDR_PHY_PGCR2_0 0x00F0A3CC // Set tREFPRD (9*3.904us) +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity + + // Set-up PHY Timing Register + // PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST + // CAST32(DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK=25us, tPLLRST=9us +DATA 4 DDR_PHY_PTR1_0 0x0D701C20 // tPLLLOCK reduced to 4.3us, tPLLRST=9us + + // Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x00000000 // FREQSEL=0 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x08000000 + + // Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x001FEC58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) + + // Set-up Impedance Controller Program Register + // ZQnPR0, ZQnPR1 are untouched, lpddr4 PD_REFSEL should not be default value, FIXME + +// ddr_phy_launch_init() + // Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x40 + + // Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x41 + + //------------------------------------------- + // Configure registers for DRAM initialization + //------------------------------------------- + //ddr 1200MHz 0.83ns + +// ddr_phy_lpddr4_dram_init() + + // Set-up Mode Register + // MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL=24/WL=12 +DATA 4 DDR_PHY_MR3_0 0x31 // Set drive strength to 40 ohms typical pull-down/pull-up + + // Set-up DRAM Timing Parameters Register + // DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0d331a05 // tRRD (10/0.83 = 13), tRAS (42ns/0.83 = 51 ), tRP (21ns/0.83 = 26 1A), tRTP (101) +DATA 4 DDR_PHY_DTPR1_0 0x28318C0a // tWLMRD, tFAW(40ns/0.83 = 49 31), tODTUP(odt is disable), tMRD(10 tck) +DATA 4 DDR_PHY_DTPR2_0 0x003a00E2 // tRTW, tRTODT, tCMDCKE, tCKE (7.5 / 0.83 = 10 a), tXS(180ns + 7.5ns / 0.83 = 226 ) +DATA 4 DDR_PHY_DTPR3_0 0x01800502 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (3.6ns / 0.83 ) (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x01C0000a // tRFC(180ns/0.83), tWLO, tXP (7.5ns / 0.83 ) +DATA 4 DDR_PHY_DTPR5_0 0x004c160d // tRC (tRAS + tRPab = (42+21)/0.83 = 76 ), tRCD (18ns / 0.83 = 22 ), tWTR (10ns / 0.83 13 d) + + // Set-up PHY Timing Register + // DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 - 2ms +DATA 4 DDR_PHY_PTR3_0 0x00005E21 // tDINIT0 - memory model hacked to 20us 25097 +DATA 4 DDR_PHY_PTR4_0 0x0000096A // tDINIT1 (2000ns) 2410 +DATA 4 DDR_PHY_PTR5_0 0x00005E21 // tDINIT2 - normally 200us but memory model hacked to 20us +DATA 4 DDR_PHY_PTR6_0 0x025004B5 // tDINIT4 (30ns) 37, tDINIT3 (1us) 1205 + + // RDIMMGCR0-2 RDIMMGCR0-4?? + + // Set-up DATX8 Common Configuration Register + // DXCCR is untouched + + // Set-up DDR System General Configuration Register + // DSGCR is untouched + + // Set-up ODT Configuration Register + // ODTCR is untouched + + // Set-up Anti-Aging Control Register + // AACR is untouched + + // Set-up Data Training Address Register + // DTAR0-3 are untouched + // !! DTAR3 is not described in spec !! + + // Set-up AC I/O Configuration Register + // ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 + + // IOVCR0-1, DXnGCR0-4??, CALBYP + + // Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032019 // CK1, CK0 +DATA 4 DDR_PHY_VTCR1_0 0x07F00173 // HVIO=1, SHREN=1, SHRNK=0 + + // Set-up DATX8 General Configuration Registers + // DXnGCR0-4 are untouched + + // Set-up DATX8 DX Control Register 2 +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x081800 // PREOEX=2tCK, POSOEX=0.5tCK + + // Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x09000000 // I/O mode = LPDDR4 + + // Set-up DATX8 DQS Control Register +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x013E4091 // DQS resistor + +//ddr_phy_wait_init_done() + // Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init() + // Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x40000 + + // Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x40001 + +// ddr_phy_wait_init_done + // Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + + +// Toggle Reset? ZEBU dont know if correct reset inserted here. 4 +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0xF +//DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DATA 4 0x41C80204 0x1 + + +// dram_init_inst() +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 + + //Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 diff --git a/platform/board/mx8qx_dxl_phantom/dcd/imx8dxl_dcd_lpddr4_16bit_1.2GHz.cfg b/platform/board/mx8qx_dxl_phantom/dcd/imx8dxl_dcd_lpddr4_16bit_1.2GHz.cfg new file mode 100755 index 0000000..47bf40e --- /dev/null +++ b/platform/board/mx8qx_dxl_phantom/dcd/imx8dxl_dcd_lpddr4_16bit_1.2GHz.cfg @@ -0,0 +1,326 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80002020 +DEFINE BD_DDR_RET_REGION2_SIZE 8 + + + +/* + * Device Configuration Data (DCD) Version 11 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81081020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 // REFRESH_BURST = 7 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x1F000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00070707 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x06060606 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x06060606 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR2_0 0xAAAA0000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR2_0 0xAAAA0000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAA0000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR3_0 0xFFE18587 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR3_0 0xFFE18587 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0xFFE18587 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00010002 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00082013 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004567 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00081302 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004756 // DQ bit 5/6/7 and DM remapping +// DATA 4 DDR_PHY_DX2DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +// DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004000 // DQ bit 5/6/7 and DM remapping +// DATA 4 DDR_PHY_DX3DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +// DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// Launch a second time DRAM initialization due to following Synopsys PHY bug: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + + + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +DATA 4 0x41c80504 0x400 +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qx_mek/Makefile b/platform/board/mx8qx_mek/Makefile new file mode 100755 index 0000000..e76e411 --- /dev/null +++ b/platform/board/mx8qx_mek/Makefile @@ -0,0 +1,61 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8qx_dcd_emul +else + DDR_CON ?= imx8qx_dcd_1.2GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + +ifeq ($(M),1) + OBJS += $(OUT)/board/pmic.o +endif + diff --git a/platform/board/mx8qx_mek/board.bom b/platform/board/mx8qx_mek/board.bom new file mode 100755 index 0000000..68d9ada --- /dev/null +++ b/platform/board/mx8qx_mek/board.bom @@ -0,0 +1,39 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf8100 + +ifeq ($(M),1) + DRV2 += pmic/pf100 +endif diff --git a/platform/board/mx8qx_mek/board.c b/platform/board/mx8qx_mek/board.c new file mode 100755 index 0000000..a2d2235 --- /dev/null +++ b/platform/board/mx8qx_mek/board.c @@ -0,0 +1,1672 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QX MEK board. + * + * @addtogroup MX8QX_MEK_BRD BRD: MX8QX MEK Board + * + * Module for MX8QX MEK board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00110 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/rgpio/fsl_rgpio.h" +#include "drivers/igpio/fsl_gpio.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "dcd/dcd_retention.h" +#include "drivers/systick/fsl_systick.h" + +/* Local Defines */ + +#ifndef BD_DDR_SIZE +#if defined(BD_DDR_RET_REGION1_SIZE) && (BD_DDR_RET_REGION1_SIZE <= 32) + /*! NXP QXP 16-bit LPDDR4 MEK board */ + #define BD_DDR_SIZE SC_1GB +#else + /*! Other NXP QXP MEK boards */ + #define BD_DDR_SIZE SC_3GB +#endif +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U +#define BRD_R_BOARD_R3 6U +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 3 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif +#if DEBUG_UART == 2 + /*! Use alternate debug UART */ + #define ALT_DEBUG_SCU_UART +#endif +#if (defined(MONITOR) || defined(EXPORT_MONITOR) || defined(HAS_TEST) \ + || (DEBUG_UART == 1)) && !defined(DEBUG_TERM_EMUL) \ + && !defined(ALT_DEBUG_SCU_UART) + #define ALT_DEBUG_UART +#endif + +/*! Configure debug UART */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG LPUART_SC +#else + #define LPUART_DEBUG LPUART_MCU_0 +#endif + +/*! Configure debug UART instance */ +#ifdef ALT_DEBUG_SCU_UART + #define LPUART_DEBUG_INST 0U +#else + #define LPUART_DEBUG_INST 1U +#endif + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +#ifndef EMUL +static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver); +static sc_err_t pmic_update_timing(uint8_t address); +#endif +static void board_get_pmic_info(sc_sub_t ss, uint32_t *pmic_reg, + uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t temp_alarm; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + ss_print(3, "board_init(%d)\n", phase); + + if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_EARLY_INIT) + { + gpio_pin_config_t config; + config.direction = kGPIO_DigitalOutput; + + /* Power on GPIO */ + pm_force_resource_power_mode_v(SC_R_GPIO_1, SC_PM_PW_MODE_ON); + + /* Mux SPI2_SDO to GPIO */ + pad_force_mux(SC_P_SPI2_SDO, 4, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + + /* Toggle base board reset, >= 30nS */ + config.outputLogic = 0U; + GPIO_PinInit(GPIO1, 1U, &config); + SYSTICK_CycleDelay(SC_SYSTICK_NSEC_TO_TICKS(30U) + 1U); + GPIO_WritePinOutput(GPIO1, 1U, 1U); + + /* Latch output */ + pad_force_mux(SC_P_SPI2_SDO, 4, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_ON); + + /* Power off GPIO */ + pm_force_resource_power_mode_v(SC_R_GPIO_1, SC_PM_PW_MODE_OFF); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #if (defined(ALT_DEBUG_UART) || defined(ALT_DEBUG_SCU_UART)) \ + && !defined(DEBUG_TERM_EMUL) + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(ALT_DEBUG_SCU_UART) && !defined(DEBUG_TERM_EMUL) \ + && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Check if debug disabled */ + if (SCFW_DBG_READY == 0U) + { + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + } + #elif defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Use M4 UART if ALT_DEBUG_UART defined */ + /* Return if debug already enabled */ + if ((SCFW_DBG_READY == 0U) && (early_phase == SC_FALSE)) + { + sc_pm_clock_rate_t rate = SC_24MHZ; + static sc_bool_t banner = SC_FALSE; + + /* Configure pads */ + pad_force_mux(SC_P_ADC_IN2, 1, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + pad_force_mux(SC_P_ADC_IN3, 1, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + + /* Power and enable clock */ + pm_force_resource_power_mode_v(SC_R_SC_PID0, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DBLOGIC, + SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_DB, SC_PM_PW_MODE_ON); + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + &rate); + (void) pm_clock_enable(SC_PT, SC_R_M4_0_UART, SC_PM_CLK_PER, + SC_TRUE, SC_FALSE); + + /* Configure UART */ + main_config_debug_uart(LPUART_DEBUG, rate); + + if (banner == SC_FALSE) + { + debug_print(1, + "\nHello from SCU (Build %u, Commit %08x, %s %s)\n\n", + SCFW_BUILD, SCFW_COMMIT, SCFW_DATE, SCFW_TIME); + banner = SC_TRUE; + } + } + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ + /* Use M4 UART if ALT_DEBUG_UART defined */ + #if defined(ALT_DEBUG_UART) && defined(DEBUG) && !defined(SIMU) + /* Return if debug already disabled */ + if (SCFW_DBG_READY != 0U) + { + /* Disable use of UART */ + SCFW_DBG_READY = 0U; + + // UART deinit to flush TX buffers + LPUART_Deinit(LPUART_DEBUG); + + /* Turn off UART */ + pm_force_resource_power_mode_v(SC_R_M4_0_UART, + SC_PM_PW_MODE_OFF); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + #ifdef ALT_DEBUG_UART + (void) rm_set_resource_movable(SC_PT, SC_R_M4_0_UART, SC_R_M4_0_UART, + SC_FALSE); + (void) rm_set_pad_movable(SC_PT, SC_P_ADC_IN3, SC_P_ADC_IN2, + SC_FALSE); + #endif + + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SCL, SC_P_PMIC_I2C_SDA, + SC_FALSE); + #ifdef ALT_DEBUG_SCU_UART + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_EXTERNAL; + break; + /* Supply ramp delay in usec for KS1 exit */ + case BOARD_PARM_KS1_RESUME_USEC: + if (OTP_KS1_07V_SUPPORT == 1U) /* KS1 0.7V support */ + { + rtn = BOARD_KS1_07V_RESUME_USEC; + } + else + { + rtn = BOARD_KS1_RESUME_USEC; + } + break; + /* Control if retention is applied during KS1 */ + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + /* Control if ONOFF button can wake from KS1 */ + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + /* DC0 PLL0 spread spectrum config */ + case BOARD_PARM_DC0_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* DC0 PLL1 spread spectrum config */ + case BOARD_PARM_DC0_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + /* Control if SC WDOG configuration during KS1 */ + case BOARD_PARM_KS1_WDOG_WAKE: + rtn = BOARD_PARM_KS1_WDOG_WAKE_ENABLE; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + if(rsrc == SC_R_PMIC_1) + { + rtn = SC_FALSE; + } + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + /* Init the analog repeater from ROM stage, mandatory! */ + if (action == BOARD_DDR_COLD_INIT) + { + ANA_WRITE(0x01U, 12U, 0U, 0xef17U); //SC + ANA_WRITE(0x28U, 12U, 0U, 0xef17U); //VPU + ANA_WRITE(0x24U, 12U, 0U, 0xef13U); //DRC + } + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + default: + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Keep baseboard reset */ + BRD_ERR(rm_assign_pad(pt_boot, SC_PT, SC_P_SPI2_SDO)); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[10U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_8B, + SC_R_GPT_4, + RM_RANGE(SC_R_CAN_0, SC_R_CAN_2), + SC_R_I2C_1, + SC_R_FSPI_0, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[8U] = + { + RM_RANGE(SC_P_ADC_IN1, SC_P_ADC_IN2), + RM_RANGE(SC_P_FLEXCAN0_RX, SC_P_FLEXCAN2_TX), + SC_P_USB_SS3_TC1, + SC_P_USB_SS3_TC3, + RM_RANGE(SC_P_QSPI0A_DATA0, SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x08FFFFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[2U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + } + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + uint32_t pmic_reg = 0U; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, &pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, pmic_reg, + SW_RUN_PWM | SW_STBY_PWM)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, pmic_reg, + SW_RUN_OFF)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + uint32_t pmic_reg = 0U; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, &pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, pmic_reg, + new_volt, REG_RUN_MODE)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + switch (idx) + { + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + ; /* Intentional empty default */ + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + #endif + #ifdef ALT_DEBUG_UART + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if (resource == SC_R_M4_0_PID0) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Temp alarm */ + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR)) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, SC_IRQ_TEMP_PMIC0_HIGH, + SC_PT_ALL); + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + + /* MEK board spec is for 1M baud for PMIC I2C bus */ + lpi2c_masterConfig.baudRate_Hz = 1000000U; + lpi2c_masterConfig.sdaGlitchFilterWidth_ns = 100U; + lpi2c_masterConfig.sclGlitchFilterWidth_ns = 100U; + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + temp_alarm = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, + PMIC_TEMP_MAX); + + /* Ignore OV/UV detection for A0/B0 & ignore current limit for A0 */ + err |= pmic_ignore_current_limit(PMIC_0_ADDR, pmic_ver); + + if(pmic_ver.si_rev == PF8100_A0_REV) + { + /* Set Regulation modes for MAIN and 1.8V rails */ + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW6, + SW_RUN_PWM | SW_STBY_PWM)); + } + + /* Adjust startup timing */ + err |= pmic_update_timing(PMIC_0_ADDR); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + + if (err != SC_ERR_NONE) + { + /* Loop so WDOG will expire */ + HALT; + } + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + uint32_t ks1_volt = 800U; + + if (OTP_KS1_07V_SUPPORT == 1U) + { + ks1_volt = 700U; + } + + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, ks1_volt, + REG_STBY_MODE)); + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + +#ifndef EMUL +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + if (ver.si_rev == PF8100_A0_REV) + { /* only bypass current limit for A0 silicon */ + val |= 0x20U; /* set xx_ILIM_BYPASS */ + } + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update power timing for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_update_timing(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + + /* + * Add 60ms stable time for power down SW5/6/7/LDO2 on i.mx8QXP-MEK + * board, otherwise system may reboot fail by mmc not power off + * clean + */ + if (address == PMIC_0_ADDR) + { + uint8_t val = 0xED; + + /* Update for PMIC 0 */ + err |= PMIC_REGISTER_ACCESS(address, 0x6F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x77, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x7F, SC_TRUE, &val); + err |= PMIC_REGISTER_ACCESS(address, 0x8D, SC_TRUE, &val); + val = 0x29; + err |= PMIC_REGISTER_ACCESS(address, 0x3C, SC_TRUE, &val); + } + else + { + /* Return error */ + err = SC_ERR_PARM; + } + + return err; +} + +#endif + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss, uint32_t *pmic_reg, + uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A35 : + pmic_init(); + *pmic_reg = PF8100_SW4; + *num_regs = 1U; + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + *pmic_reg = PF8100_SW3; + *num_regs = 1U; + break; + default: + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qx_mek/board.h b/platform/board/mx8qx_mek/board.h new file mode 100755 index 0000000..b3555e9 --- /dev/null +++ b/platform/board/mx8qx_mek/board.h @@ -0,0 +1,121 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC pf8100 +#define PMIC_0_ADDR 0x8U + +#define PMIC_TEMP_MAX 135U + +#define PF8100_REGULATORS 12U + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U + +/* + * Resume from KS1 ramps VDD_MAIN 300 mV (700 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 300 mV / 7.813 mV/us = 38.4 us ==> 39 us + * + */ +#define BOARD_KS1_07V_RESUME_USEC 39U + +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qx_mek/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qx_mek/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..85a23c7 --- /dev/null +++ b/platform/board/mx8qx_mek/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,143 @@ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + + diff --git a/platform/board/mx8qx_mek/dcd/imx8dx_dcd_lpddr4_16bit_1.2GHz.cfg b/platform/board/mx8qx_mek/dcd/imx8dx_dcd_lpddr4_16bit_1.2GHz.cfg new file mode 100755 index 0000000..79f363e --- /dev/null +++ b/platform/board/mx8qx_mek/dcd/imx8dx_dcd_lpddr4_16bit_1.2GHz.cfg @@ -0,0 +1,373 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80002020 +DEFINE BD_DDR_RET_REGION2_SIZE 8 + + + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81081020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x1F000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00070707 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x06060606 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x06060606 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00010002 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x026012C1 +DATA 4 DDR_PHY_PTR1_0 0x01D500A9 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000124F8 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000004B // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001D4C // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00026 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x0000004B +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + diff --git a/platform/board/mx8qx_mek/dcd/imx8qx_dcd_1.2GHz.cfg b/platform/board/mx8qx_mek/dcd/imx8qx_dcd_1.2GHz.cfg new file mode 100755 index 0000000..d692183 --- /dev/null +++ b/platform/board/mx8qx_mek/dcd/imx8qx_dcd_1.2GHz.cfg @@ -0,0 +1,372 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x0C0000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 3 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80004040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80008000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x0003000A +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00016578 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004203 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00015867 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004320 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x026012C1 +DATA 4 DDR_PHY_PTR1_0 0x01D500A9 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000124F8 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000004B // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001D4C // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00026 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x0000004B +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qx_mek/dcd/imx8qx_dcd_1.2GHz_nocbt.cfg b/platform/board/mx8qx_mek/dcd/imx8qx_dcd_1.2GHz_nocbt.cfg new file mode 100755 index 0000000..613d51b --- /dev/null +++ b/platform/board/mx8qx_mek/dcd/imx8qx_dcd_1.2GHz_nocbt.cfg @@ -0,0 +1,330 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x0C0000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 3 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80004040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80008000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 // REFRESH_BURST = 7 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x0003000A +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00016578 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004203 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00015867 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004320 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// Launch a second time DRAM initialization due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +DATA 4 0x41c80504 0x400 +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qx_mek/dcd/imx8qx_dcd_emul.cfg b/platform/board/mx8qx_mek/dcd/imx8qx_dcd_emul.cfg new file mode 100755 index 0000000..389d8bb --- /dev/null +++ b/platform/board/mx8qx_mek/dcd/imx8qx_dcd_emul.cfg @@ -0,0 +1,263 @@ +/* +** ################################################################### +** +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + + +// DSC RESET +// First reset ? ZEBU dont know if we need this first reset. 1 +//DATA 4 0x41C80208 0x1 +//DATA 4 0x41C80044 0x8 +//DATA 4 0x41C80204 0x1 + +//ddrc_lpddr4_init(inst); + + // This is for lpddr4 controller 600MHz 1.67ns and ddr 1200MHz 0.83ns +DATA 4 DDRC_MSTR_0 0x03080020 // Set LPDDR4, BL = 16 and active ranks = 2 +DATA 4 DDRC_RFSHTMG_0 0x0049006D // tREFI noroundup(3.904us/tCK)/2 36 = 24, tRFC 180ns RoundUp(tRFCmin/tCK)/2 (180/0.83)/2 134 = 86 +DATA 4 DDRC_INIT0_0 0x0002000c // post cke roundup(2us/tCK)/2 pre_cke = 2ms is too long - LPDDR4 model hacked for 20us 00-SDRAM initialization routine is run after power up . 00 and 10 the same ? +DATA 4 DDRC_INIT1_0 0x000c0000 // dram_rstn - LPDDR4 model hacked for 20us; +DATA 4 DDRC_INIT3_0 0x00440024 // MR1=0x44: nWR=24 ? BL=16; MR2=0x24: RL=24 WL=12 ? +DATA 4 DDRC_INIT4_0 0x00310000 // MR3, MR13 PDDS 110 PU-CAL VddQ/3 +DATA 4 DDRC_RANKCTL_0 0x000006cf // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1519041a // wr2pr roundup((WL 12 + BL/2 8 + nWR 18ns)/2) = 20 hex 14 , tFAW (40ns /2) 25 hex 19 , tRASmax 8.7885us 4 , tRASmin 42ns (42ns/tCK)/2 26 hex 19 +DATA 4 DDRC_DRAMTMG1_0 0x00040526 // tXP 7.5ns roundup(tXP/2) 4, rd2pre roundup((BL/2 +8ns - 8)/2) = 5 , tRC 42ns +21ns roundup(63ns/2) = 38 hex +DATA 4 DDRC_DRAMTMG2_0 0x060b0e11 // WL 12/2, RL 24/2, rd2wr roundup((RL 24 +BL/2 8 +RU tDQSCK 3.6ns/0.83ns 4.3 +WR_PREAMBLE 2tck + RD_POSTAMBLE 0.5tck -WL 12)/2) = 14, wr2rd RU(WL 12 +BL/2 8+tWTR 10ns +1)/2 17 hex +DATA 4 DDRC_DRAMTMG3_0 0x0170c000 // tmrw tMRW ? tMRWCKEL 10CK, tmrd 10tck, tmod present on DDR3/4 only +DATA 4 DDRC_DRAMTMG4_0 0x0b04070d // trcd 18ns 11, tccd 8tck, trrd 10ns 7, trp 21ns 13 +DATA 4 DDRC_DRAMTMG5_0 0x03040305 // tcksrx 3tck, tcksre 5tck, tckesr 7.5ns tSR TBD, tcke 7.5/0.83/2 +DATA 4 DDRC_DRAMTMG6_0 0x00000004 // tckdpde, tckdpdx, tckcsx 7.5ns +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde 5tck, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE 3tck, tCKEHCMD (=tXP?) ? +DATA 4 DDRC_DRAMTMG13_0 0x00100002 // tODTLoff ODT disable, tCCDMW 4*8tck 16, tPPD 4tCK +DATA 4 DDRC_DRAMTMG14_0 0x00000039 // txsr tRFCAB 180ns+ 7.5ns +DATA 4 DDRC_ZQCTL0_0 0x025b0012 // tZQCAL 1us, tZQLAT 30ns 18 +DATA 4 DDRC_ZQCTL1_0 0x03d72e68 // tZQReset 50ns f, tzq_short_interval 0.4s lpddr3 ? +DATA 4 DDRC_DFITMG0_0 0x0498820a // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001608 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x80400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x00010002 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000016 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080202 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP2_0 0x02020000 +DATA 4 DDRC_ADDRMAP3_0 0x02020202 +DATA 4 DDRC_ADDRMAP4_0 0x00001f1f // addrmap_col_b11, addrmap_col_b10 +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0f070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 + +// These should not be here +//DATA 4 DDRC_ADDRMAP1_0 0x00171717 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +//DATA 4 DDRC_ADDRMAP5_0 0x03030303 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +//DATA 4 DDRC_ADDRMAP6_0 0x03030303 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 + +DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// in ddrc_init_inst() +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +// As DRAM init sequence will be run by controller set 0x0 to skip_dram_init field +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 + + +// Do we need this as well? Didnt need to set before ZEBU 2 +DATA 4 DDRC_PWRCTL_0 0x10D + +// Toggle Reset ... ZEBU NEED THIS? 3 +//DATA 4 0x41C80208 0x1 +//DATA 4 0x41C80044 0x4 +//DATA 4 0x41C80204 0x1 + + //------------------------------------------- + // Configure registers for PHY initialization + // Timings are computed for a PHY at 600MHz (DRAM at 1200MHz) 600MHz 1.67ns ddr 1200MHz 0.83ns + //------------------------------------------- + +//ddr_phy_lpddr4_phy_init() + + // Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank + + // Set-up PHY General Configuration Register + // PGCR0,1,4,5,6,7 are untouched +DATA 4 DDR_PHY_PGCR0_0 0x87001e00 // address copy +DATA 4 DDR_PHY_PGCR2_0 0x00F0A3CC // Set tREFPRD (9*3.904us) +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity + + // Set-up PHY Timing Register + // PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST + // CAST32(DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK=25us, tPLLRST=9us +DATA 4 DDR_PHY_PTR1_0 0x0D701C20 // tPLLLOCK reduced to 4.3us, tPLLRST=9us + + // Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x00000000 // FREQSEL=0 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x08000000 + + // Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x001FEC58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) + + // Set-up Impedance Controller Program Register + // ZQnPR0, ZQnPR1 are untouched, lpddr4 PD_REFSEL should not be default value, FIXME + +// ddr_phy_launch_init() + // Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x40 + + // Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x41 + + //------------------------------------------- + // Configure registers for DRAM initialization + //------------------------------------------- + //ddr 1200MHz 0.83ns + +// ddr_phy_lpddr4_dram_init() + + // Set-up Mode Register + // MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL=24/WL=12 +DATA 4 DDR_PHY_MR3_0 0x31 // Set drive strength to 40 ohms typical pull-down/pull-up + + // Set-up DRAM Timing Parameters Register + // DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0d331a05 // tRRD (10/0.83 = 13), tRAS (42ns/0.83 = 51 ), tRP (21ns/0.83 = 26 1A), tRTP (101) +DATA 4 DDR_PHY_DTPR1_0 0x28318C0a // tWLMRD, tFAW(40ns/0.83 = 49 31), tODTUP(odt is disable), tMRD(10 tck) +DATA 4 DDR_PHY_DTPR2_0 0x003a00E2 // tRTW, tRTODT, tCMDCKE, tCKE (7.5 / 0.83 = 10 a), tXS(180ns + 7.5ns / 0.83 = 226 ) +DATA 4 DDR_PHY_DTPR3_0 0x01800502 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (3.6ns / 0.83 ) (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x01C0000a // tRFC(180ns/0.83), tWLO, tXP (7.5ns / 0.83 ) +DATA 4 DDR_PHY_DTPR5_0 0x004c160d // tRC (tRAS + tRPab = (42+21)/0.83 = 76 ), tRCD (18ns / 0.83 = 22 ), tWTR (10ns / 0.83 13 d) + + // Set-up PHY Timing Register + // DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 - 2ms +DATA 4 DDR_PHY_PTR3_0 0x00005E21 // tDINIT0 - memory model hacked to 20us 25097 +DATA 4 DDR_PHY_PTR4_0 0x0000096A // tDINIT1 (2000ns) 2410 +DATA 4 DDR_PHY_PTR5_0 0x00005E21 // tDINIT2 - normally 200us but memory model hacked to 20us +DATA 4 DDR_PHY_PTR6_0 0x025004B5 // tDINIT4 (30ns) 37, tDINIT3 (1us) 1205 + + // RDIMMGCR0-2 RDIMMGCR0-4?? + + // Set-up DATX8 Common Configuration Register + // DXCCR is untouched + + // Set-up DDR System General Configuration Register + // DSGCR is untouched + + // Set-up ODT Configuration Register + // ODTCR is untouched + + // Set-up Anti-Aging Control Register + // AACR is untouched + + // Set-up Data Training Address Register + // DTAR0-3 are untouched + // !! DTAR3 is not described in spec !! + + // Set-up AC I/O Configuration Register + // ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 + + // IOVCR0-1, DXnGCR0-4??, CALBYP + + // Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032019 // CK1, CK0 +DATA 4 DDR_PHY_VTCR1_0 0x07F00173 // HVIO=1, SHREN=1, SHRNK=0 + + // Set-up DATX8 General Configuration Registers + // DXnGCR0-4 are untouched + + // Set-up DATX8 DX Control Register 2 +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x081800 // PREOEX=2tCK, POSOEX=0.5tCK + + // Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x09000000 // I/O mode = LPDDR4 + + // Set-up DATX8 DQS Control Register +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x013E4091 // DQS resistor + +//ddr_phy_wait_init_done() + // Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init() + // Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x40000 + + // Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x40001 + +// ddr_phy_wait_init_done + // Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + + +// Toggle Reset? ZEBU dont know if correct reset inserted here. 4 +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0xF +//DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DATA 4 0x41C80204 0x1 + + +// dram_init_inst() +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 + + //Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 diff --git a/platform/board/mx8qx_val/Makefile b/platform/board/mx8qx_val/Makefile new file mode 100755 index 0000000..5c44ce5 --- /dev/null +++ b/platform/board/mx8qx_val/Makefile @@ -0,0 +1,58 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +#Set Default DDR config file +ifeq ($(Z),1) + DDR_CON ?= imx8qx_dcd_emul +else + DDR_CON ?= imx8qx_dcd_1.2GHz +endif + +OBJS += $(OUT)/board/$(CONFIG)_$(B)/board.o \ + $(OUT)/board/board_common.o \ + $(OUT)/board/pmic.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DCDH += $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON).h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/$(DDR_CON)_retention.h \ + $(SRC)/board/$(CONFIG)_$(B)/dcd/dcd_retention.h + +RSRC_MD += $(SRC)/board/$(CONFIG)_$(B)/resource.txt + +CTRL_MD += $(SRC)/board/$(CONFIG)_$(B)/control.txt + +DIRS += $(OUT)/board/$(CONFIG)_$(B) + diff --git a/platform/board/mx8qx_val/board.bom b/platform/board/mx8qx_val/board.bom new file mode 100755 index 0000000..fbff4e9 --- /dev/null +++ b/platform/board/mx8qx_val/board.bom @@ -0,0 +1,37 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +DRV2 += \ + pmic \ + pmic/pf100 \ + pmic/pf8100 + diff --git a/platform/board/mx8qx_val/board.c b/platform/board/mx8qx_val/board.c new file mode 100755 index 0000000..aa80e23 --- /dev/null +++ b/platform/board/mx8qx_val/board.c @@ -0,0 +1,1871 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the implementation of the MX8QX validation board. + * + * @addtogroup MX8QX_VAL_BRD BRD: MX8QX Validation Board + * + * Module for MX8QX validation board access. + * + * @{ + */ +/*==========================================================================*/ + +/* This port meets SRS requirement PRD_00100 */ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "board/pmic.h" +#include "all_svc.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf100/fsl_pf100.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "drivers/snvs/fsl_snvs.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "drivers/sysctr/fsl_sysctr.h" +#include "drivers/drc/fsl_drc_cbt.h" +#include "drivers/drc/fsl_drc_derate.h" +#include "drivers/drc/fsl_drc_rdbi_deskew.h" +#include "drivers/drc/fsl_drc_dram_vref.h" +#include "pads.h" +#include "drivers/pad/fsl_pad.h" +#include "ss/drc/v2/dsc.h" +#include "dcd/dcd_retention.h" + +/* Local Defines */ + +#ifndef BD_DDR_SIZE +#if defined(BD_DDR_RET_REGION1_SIZE) && (BD_DDR_RET_REGION1_SIZE == 64) + /*! NXP QXP LPDDR4 VAL board */ + #define BD_DDR_SIZE SC_3GB +#elif defined(BD_DDR_RET_REGION1_SIZE) && (BD_DDR_RET_REGION1_SIZE == 16) + /*! NXP QXP 16-bit DDR3L VAL board */ + #define BD_DDR_SIZE SC_2GB +#elif defined(BD_DDR_RET_REGION3_SIZE) && (BD_DDR_RET_REGION3_SIZE == 24) + /*! NXP QXP 16-bit LPDDR4 VAL board */ + #define BD_DDR_SIZE SC_1P5GB +#else + /*! NXP QXP DDR3L VAL boards */ + #define BD_DDR_SIZE SC_1GB +#endif +#endif + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_PMIC_1 1U +#define BRD_R_BOARD_PMIC_2 2U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U +#define BRD_R_BOARD_R3 6U +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U /*!< Test */ +/** @} */ + +#if DEBUG_UART == 1 + /*! Use debugger terminal emulation */ + #define DEBUG_TERM_EMUL +#endif + +/*! Configure debug UART */ +#define LPUART_DEBUG LPUART_SC + +/*! Configure debug UART instance */ +#define LPUART_DEBUG_INST 0U + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +static void pmic_init(void); +#ifndef EMUL + static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver); + static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver); +#endif +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs); + +/* Local Variables */ + +static pmic_version_t pmic_ver; +static uint32_t pmic_card; +static uint32_t temp_alarm0; +static uint32_t temp_alarm1; +static uint32_t temp_alarm2; + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +#ifdef BD_LPDDR4_INC_DQS2DQ +const uint32_t board_ddr_period_ms = 3000U; +#else +const uint32_t board_ddr_period_ms = 0U; +#endif + +const uint32_t board_ddr_derate_period_ms = 1000U; + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + ss_print(3, "board_init(%d)\n", phase); + + if (phase == BOOT_PHASE_FINAL_INIT) + { + /* Configure SNVS button for rising edge */ + SNVS_ConfigButton(SNVS_DRV_BTN_CONFIG_RISINGEDGE, SC_TRUE); + + /* Init PMIC if not already done */ + pmic_init(); + } + else if (phase == BOOT_PHASE_TEST_INIT) + { + /* Configure board for SCFW tests - only called in a unit test + * image. Called just before SC tests are run. + */ + + /* Configure ADMA UART pads. Needed for test_dma. + * NOTE: Even though UART is ALT0, the TX output will not work + * until the pad mux is configured. + */ + PAD_SetMux(IOMUXD__UART0_TX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + PAD_SetMux(IOMUXD__UART0_RX, 0U, SC_PAD_CONFIG_NORMAL, + SC_PAD_ISO_OFF); + } + else + { + ; /* Intentional empty else */ + } +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + #ifndef DEBUG_TERM_EMUL + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; + #else + return NULL; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if !defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Return if debug enabled */ + ASRT(SCFW_DBG_READY == 0U); + + /* Configure SCU UART */ + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + #elif defined(DEBUG_TERM_EMUL) && defined(DEBUG) && !defined(SIMU) + *SCFW_DBG_TX_PTR = 0U; + *SCFW_DBG_RX_PTR = 0U; + /* Set to 2 for JTAG emulation */ + SCFW_DBG_READY = 2U; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ + /* By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ + (void) rm_set_resource_movable(pt_sc, SC_R_SC_I2C, SC_R_SC_I2C, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_PMIC_I2C_SCL, SC_P_PMIC_I2C_SDA, + SC_FALSE); + (void) rm_set_pad_movable(pt_sc, SC_P_SCU_GPIO0_00, + SC_P_SCU_GPIO0_01, SC_FALSE); +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + board_parm_rtn_t rtn = BOARD_PARM_RTN_NOT_USED; + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + switch (parm) + { + /* Used whenever HSIO SS powered up. Valid return values are + BOARD_PARM_RTN_EXTERNAL or BOARD_PARM_RTN_INTERNAL */ + case BOARD_PARM_PCIE_PLL : + rtn = BOARD_PARM_RTN_EXTERNAL; + break; + case BOARD_PARM_KS1_RESUME_USEC: + if (OTP_KS1_07V_SUPPORT == 1U) /* KS1 0.7V support */ + { + rtn = BOARD_KS1_07V_RESUME_USEC; + } + else + { + rtn = BOARD_KS1_RESUME_USEC; + } + break; + case BOARD_PARM_KS1_RETENTION: + rtn = BOARD_KS1_RETENTION; + break; + case BOARD_PARM_KS1_ONOFF_WAKE: + rtn = BOARD_KS1_ONOFF_WAKE; + break; + case BOARD_PARM_DC0_PLL0_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + case BOARD_PARM_DC0_PLL1_SSC: + rtn = BOARD_PARM_RTN_NOT_USED; + break; + default : + ; /* Intentional empty default */ + break; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + sc_bool_t rtn = SC_TRUE; + + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + +#ifdef EMUL + if(rsrc == SC_R_PMIC_0) + { + rtn = SC_FALSE; + } + if(rsrc == SC_R_PMIC_1) + { + rtn = SC_FALSE; + } + if(rsrc == SC_R_PMIC_2) + { + rtn = SC_FALSE; + } +#endif + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized) +{ + /* + * Variables for DDR retention + */ + #if defined(BD_DDR_RET) & !defined(SKIP_DDR) + /* Storage for DRC registers */ + static ddrc board_ddr_ret_drc_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DRC PHY registers */ + static ddr_phy board_ddr_ret_drc_phy_inst[BD_DDR_RET_NUM_DRC]; + + /* Storage for DDR regions */ + static uint32_t board_ddr_ret_buf1[BD_DDR_RET_REGION1_SIZE]; + #ifdef BD_DDR_RET_REGION2_SIZE + static uint32_t board_ddr_ret_buf2[BD_DDR_RET_REGION2_SIZE]; + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + static uint32_t board_ddr_ret_buf3[BD_DDR_RET_REGION3_SIZE]; + #endif + + /* DDR region descriptors */ + static const soc_ddr_ret_region_t board_ddr_ret_region[BD_DDR_RET_NUM_REGION] = + { + { BD_DDR_RET_REGION1_ADDR, BD_DDR_RET_REGION1_SIZE, board_ddr_ret_buf1 }, + #ifdef BD_DDR_RET_REGION2_SIZE + { BD_DDR_RET_REGION2_ADDR, BD_DDR_RET_REGION2_SIZE, board_ddr_ret_buf2 }, + #endif + #ifdef BD_DDR_RET_REGION3_SIZE + { BD_DDR_RET_REGION3_ADDR, BD_DDR_RET_REGION3_SIZE, board_ddr_ret_buf3 } + #endif + }; + + /* DDR retention descriptor passed to SCFW */ + static soc_ddr_ret_info_t board_ddr_ret_info = + { + BD_DDR_RET_NUM_DRC, board_ddr_ret_drc_inst, board_ddr_ret_drc_phy_inst, + BD_DDR_RET_NUM_REGION, board_ddr_ret_region + }; + #endif + + #if defined(BD_LPDDR4_INC_DQS2DQ) && defined(BOARD_DQS2DQ_SYNC) + static soc_dqs2dq_sync_info_t board_dqs2dq_sync_info = + { + BOARD_DQS2DQ_ISI_RSRC, BOARD_DQS2DQ_ISI_REG, BOARD_DQS2DQ_SYNC_TIME + }; + #endif + + board_print(3, "board_init_ddr(%d)\n", early); + + #ifdef SKIP_DDR + return SC_ERR_UNAVAILABLE; + #else + sc_err_t err = SC_ERR_NONE; + + /* Don't power up DDR for M4s */ + ASRT_ERR(early == SC_FALSE, SC_ERR_UNAVAILABLE); + + if ((err == SC_ERR_NONE) && (ddr_initialized == SC_FALSE)) + { + board_print(1, "SCFW: "); + err = board_ddr_config(SC_FALSE, BOARD_DDR_COLD_INIT); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + #endif + } + + #ifdef DEBUG_BOARD + if (err == SC_ERR_NONE) + { + uint32_t rate = 0U; + sc_err_t rate_err = SC_ERR_FAIL; + + if (rm_is_resource_avail(SC_R_DRC_0)) + { + rate_err = pm_get_clock_rate(SC_PT, SC_R_DRC_0, + SC_PM_CLK_SLV_BUS, &rate); + } + if (rate_err == SC_ERR_NONE) + { + board_print(1, "DDR frequency = %u\n", rate * 2U); + } + } + #endif + + if (err == SC_ERR_NONE) + { + #ifdef BD_DDR_RET + soc_ddr_config_retention(&board_ddr_ret_info); + #endif + + #ifdef BD_LPDDR4_INC_DQS2DQ + #ifdef BOARD_DQS2DQ_SYNC + soc_ddr_dqs2dq_config(&board_dqs2dq_sync_info); + #endif + if (board_ddr_period_ms != 0U) + { + soc_ddr_dqs2dq_init(); + } + #endif + } + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + + return err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. + */ + + sc_err_t err = SC_ERR_NONE; +#ifdef LP4_MANUAL_DERATE_WORKAROUND + sc_bool_t polling = SC_FALSE; +#endif + + /* Init the analog repeater from ROM stage, mandatory! */ + if (action == BOARD_DDR_COLD_INIT) + { + ANA_WRITE(0x01U, 12U, 0U, 0xef17U); //SC + ANA_WRITE(0x28U, 12U, 0U, 0xef17U); //VPU + ANA_WRITE(0x24U, 12U, 0U, 0xef13U); //DRC + } + + switch(action) + { + case BOARD_DDR_PERIODIC: + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + #ifdef BD_DDR_RET + soc_ddr_enter_retention(); + #endif + break; + case BOARD_DDR_SR_DRC_OFF_EXIT: + #ifdef BD_DDR_RET + soc_ddr_exit_retention(); + #endif + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_init(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_SR_DRC_ON_ENTER: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + soc_self_refresh_power_down_clk_disable_entry(); + break; + case BOARD_DDR_SR_DRC_ON_EXIT: + soc_refresh_power_down_clk_disable_exit(); + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + case BOARD_DDR_PERIODIC_HALT: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + board_ddr_derate_periodic_enable(SC_FALSE); + #endif + board_ddr_periodic_enable(SC_FALSE); + break; + case BOARD_DDR_PERIODIC_RESTART: + #ifdef LP4_MANUAL_DERATE_WORKAROUND + ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + board_ddr_derate_periodic_enable(SC_TRUE); + #endif + #ifdef BD_LPDDR4_INC_DQS2DQ + soc_ddr_dqs2dq_periodic(); + #endif + board_ddr_periodic_enable(SC_TRUE); + break; + #ifdef LP4_MANUAL_DERATE_WORKAROUND + case BOARD_DDR_DERATE_PERIODIC: + polling = ddrc_lpddr4_derate_periodic(BD_DDR_RET_NUM_DRC); + if (polling != SC_TRUE) + { + board_ddr_derate_periodic_enable(SC_FALSE); + } + break; + #endif + case BOARD_DDR0_VREF: + #if defined(MONITOR) || defined(EXPORT_MONITOR) + // Launch VREF training + DRAM_VREF_training_hw(0); + #else + // Run vref training + DRAM_VREF_training_sw(0); + #endif + break; + default: + #include "dcd/dcd.h" + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + sc_err_t err = SC_ERR_NONE; + + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + /* Note the configuration here is for NXP test purposes */ + + sc_bool_t alt_config = SC_FALSE; + sc_bool_t no_ap = SC_FALSE; + sc_bool_t ddrtest = SC_FALSE; + + /* Get boot parameters. See the Boot Flags section for definition + of these flags.*/ + boot_get_data(NULL, NULL, NULL, NULL, NULL, NULL, &alt_config, + NULL, &ddrtest, &no_ap, NULL); + + board_print(3, "board_system_config(%d, %d)\n", early, alt_config); + + #if !defined(EMUL) + if (ddrtest == SC_FALSE) + { + sc_rm_mr_t mr_temp; + + #if BD_DDR_SIZE < SC_2GB + /* Board has less than 2GB so fragment lower region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE0 + BD_DDR_SIZE, + DDR_BASE0_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + #if BD_DDR_SIZE <= SC_2GB + /* Board has 2GB memory or less so delete upper memory region */ + BRD_ERR(rm_find_memreg(pt_boot, &mr_temp, DDR_BASE1, DDR_BASE1)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #else + /* Fragment upper region and delete */ + BRD_ERR(rm_memreg_frag(pt_boot, &mr_temp, DDR_BASE1 + BD_DDR_SIZE + - SC_2GB, DDR_BASE1_END)); + BRD_ERR(rm_memreg_free(pt_boot, mr_temp)); + #endif + } + #endif + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); + + /* Configure initial resource allocation (note additional allocation + and assignments can be made by the SCFW clients at run-time */ + if (alt_config != SC_FALSE) + { + sc_rm_pt_t pt_m4_0 = SC_RM_NUM_PARTITION; + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + + /* Name boot partition */ + PARTITION_NAME(pt_boot, "AP0"); + + /* Create M4 0 partition */ + if (rm_is_resource_avail(SC_R_M4_0_PID0) != SC_FALSE) + { + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[9U] = + { + SC_R_SYSTEM, + SC_R_IRQSTR_M4_0, + SC_R_MU_5B, + SC_R_MU_8B, + SC_R_GPT_4, + RM_RANGE(SC_R_CAN_0, SC_R_CAN_2), + SC_R_FSPI_0, + SC_R_SECO_MU_4 + }; + + /* List of pads */ + static const sc_pad_t pad_list[6U] = + { + RM_RANGE(SC_P_ADC_IN3, SC_P_ADC_IN2), + RM_RANGE(SC_P_FLEXCAN0_RX, SC_P_FLEXCAN2_TX), + RM_RANGE(SC_P_QSPI0A_DATA0, SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[2U] = + { + {0x088000000ULL, 0x08FFFFFFFULL}, + {0x008081000ULL, 0x008180FFFULL} + }; + + /* Create partition */ + BRD_ERR(rm_partition_create(pt_boot, &pt_m4_0, SC_FALSE, + SC_TRUE, SC_FALSE, SC_TRUE, SC_FALSE, SC_R_M4_0_PID0, + rsrc_list, ARRAY_SIZE(rsrc_list), + pad_list, ARRAY_SIZE(pad_list), + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt_m4_0, "MCU0"); + + /* Allow AP to use SYSTEM (not production!) */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_SYSTEM, + pt_boot, SC_RM_PERM_SEC_RW)); + + /* Move M4 0 TCM */ + BRD_ERR(rm_find_memreg(pt_boot, &mr, 0x034FE0000ULL, + 0x034FE0000ULL)); + BRD_ERR(rm_assign_memreg(pt_boot, pt_m4_0, mr)); + + /* Move partition to be owned by SC */ + BRD_ERR(rm_set_parent(pt_boot, pt_m4_0, SC_PT)); + + /* Check if booting with the no_ap flag set */ + if (no_ap != SC_FALSE) + { + /* Move boot to be owned by M4 0 for Android Automotive */ + BRD_ERR(rm_set_parent(SC_PT, pt_boot, pt_m4_0)); + } + } + + /* Allow all to access the SEMA42s */ + BRD_ERR(rm_set_peripheral_permissions(SC_PT, SC_R_M4_0_SEMA42, + SC_RM_PT_ALL, SC_RM_PERM_FULL)); + + /* Create partition for shared/hidden resources */ + { + sc_rm_pt_t pt; + sc_rm_mr_t mr; + + /* List of resources */ + static const sc_rsrc_t rsrc_list[2U] = + { + RM_RANGE(SC_R_M4_0_PID1, SC_R_M4_0_PID4) + }; + + /* List of memory regions */ + static const sc_rm_mem_list_t mem_list[1U] = + { + {0x090000000ULL, 0x091FFFFFFULL} + }; + + /* Create shared partition */ + BRD_ERR(rm_partition_create(SC_PT, &pt, SC_FALSE, SC_TRUE, + SC_FALSE, SC_FALSE, SC_FALSE, SC_NUM_RESOURCE, + rsrc_list, ARRAY_SIZE(rsrc_list), NULL, 0U, + mem_list, ARRAY_SIZE(mem_list))); + + /* Name partition for debug */ + PARTITION_NAME(pt, "Shared"); + + /* Share memory space */ + BRD_ERR(rm_find_memreg(SC_PT, &mr, + mem_list[0U].addr_start, mem_list[0U].addr_start)); + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_boot, + SC_RM_PERM_FULL)); + if (pt_m4_0 != SC_RM_NUM_PARTITION) + { + BRD_ERR(rm_set_memreg_permissions(pt, mr, pt_m4_0, + SC_RM_PERM_FULL)); + } + } + + #ifdef BOARD_RM_DUMP + rm_dump(pt_boot); + #endif + } + +#if 0 + BRD_ERR(rm_set_pad_movable(pt_boot,SC_P_ADC_IN3,SC_P_ADC_IN2, + SC_TRUE)); + + /* Move some pads not in the M4_0 subsystem */ + BRD_ERR(rm_set_pad_movable(pt_boot, SC_P_FLEXCAN0_RX, + SC_P_FLEXCAN2_TX, SC_TRUE)); + BRD_ERR(rm_set_pad_movable(pt_boot, SC_P_QSPI0A_DATA0, + SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B, SC_TRUE)); + +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + sc_bool_t rtn = SC_FALSE; + + if ((cpu == SC_R_M4_0_PID0) || (cpu == SC_R_M4_1_PID0)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id != 0U) + { + sc_err_t err = SC_ERR_NONE; + uint8_t mode; + + if (pmic_ver.device_id == PF100_DEV_ID) + { + mode = SW_MODE_PWM_STBY_PWM; + } + else + { + mode = SW_RUN_PWM | SW_STBY_PWM; + } + + /* Flip switch */ + if (to_mode > SC_PM_PW_MODE_OFF) + { + uint8_t idx = 0U; + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + mode)); + idx++; + } + SystemTimeDelay(PMIC_MAX_RAMP); + } + else + { + uint8_t idx = 0U; + + mode = 0U; + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_MODE(pmic_id[idx], pmic_reg[idx], + mode)); + idx++; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + sc_err_t err = SC_ERR_NONE; + pmic_id_t pmic_id[2] = {0U, 0U}; + uint32_t pmic_reg[2] = {0U, 0U}; + uint8_t num_regs = 0U; + + board_print(3, "board_set_voltage(%s, %u, %u)\n", snames[ss], new_volt, + old_volt); + + board_get_pmic_info(ss, pmic_id, pmic_reg, &num_regs); + + /* Check for PMIC */ + if (pmic_ver.device_id == 0U) + { + err = SC_ERR_NOTFOUND; + } + else + { + uint8_t idx = 0U; + uint8_t mode; + + if (pmic_ver.device_id == PF100_DEV_ID) + { + mode = SW_RUN_MODE; + } + else + { + mode = REG_RUN_MODE;/* run mode programming */ + } + + while (idx < num_regs) + { + BRD_ERR(PMIC_SET_VOLTAGE(pmic_id[idx], pmic_reg[idx], + new_volt, mode)); + idx++; + } + if ((old_volt != 0U) && (new_volt > old_volt)) + { + /* PMIC_MAX_RAMP_RATE is in nano Volts. */ + uint32_t ramp_time = ((new_volt - old_volt) * 1000U) + / PMIC_MAX_RAMP_RATE; + SystemTimeDelay(ramp_time + 1U); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %u, %u)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); + + /* Init PMIC */ + pmic_init(); + + /* Process resource */ + if (pmic_ver.device_id != 0U) + { + switch (idx) + { + case BRD_R_BOARD_R7 : + /* Example for testing (use SC_R_BOARD_R7) */ + board_print(3, "SC_R_BOARD_R7 from %u to %u\n", + from_mode, to_mode); + break; + default : + break; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + if (mode == SC_PM_PW_MODE_OFF) + { + /* Request power off */ + SNVS_PowerOff(); + err = snvs_err; + + /* Loop forever */ + while(err == SC_ERR_NONE) + { + ; /* Intentional empty while */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + if (type == SC_PM_RESET_TYPE_BOARD) + { + /* Request PMIC do a board reset */ + } + else if (type == SC_PM_RESET_TYPE_COLD) + { + /* Request PMIC do a cold reset */ + } + else + { + ; /* Intentional empty else */ + } + + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for M4 reset event */ + if (resource == SC_R_M4_0_PID0) + { + always_print("CM4 reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + (void) board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + HALT; + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + (void) board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SNVS_GetButtonStatus(); +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_set_control(%s, %u, %u)\n", rnames[rsrc_idx], ctrl, val); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP_HI) + { + temp_alarm0 = + SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, val); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP_HI) + { + if (pmic_card != PF8100_SINGLE) + { + temp_alarm1 = + SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, val); + } + else + { + temp_alarm1 = val;/* Fake the set if not there */ + } + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_2 : + if (ctrl == SC_C_TEMP_HI) + { + if (pmic_card == PF100_TRIPLE) + { + temp_alarm2 = + SET_PMIC_TEMP_ALARM(PMIC_2_ADDR, val); + } + else + { + temp_alarm2 = val; /* Fake the set if not there */ + } + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage set to %u\n", + val); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + /* Init PMIC */ + pmic_init(); + + /* Check if PMIC available */ + ASRT_ERR(pmic_ver.device_id != 0U, SC_ERR_NOTFOUND); + + if (err == SC_ERR_NONE) + { + /* Process control */ + switch (resource) + { + case SC_R_PMIC_0 : + if (ctrl == SC_C_TEMP) + { + *val = GET_PMIC_TEMP(PMIC_0_ADDR); + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm0; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_0_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_1 : + if (ctrl == SC_C_TEMP) + { + if (pmic_card != PF8100_SINGLE) + { + *val = GET_PMIC_TEMP(PMIC_1_ADDR); + } + else + { + err = SC_ERR_PARM; + } + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm1; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_1_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_PMIC_2 : + if (ctrl == SC_C_TEMP) + { + if (pmic_card == PF100_TRIPLE) + { + *val = GET_PMIC_TEMP(PMIC_2_ADDR); + } + else + { + err = SC_ERR_PARM; + } + } + else if (ctrl == SC_C_TEMP_HI) + { + *val = temp_alarm2; + } + else if (ctrl == SC_C_ID) + { + pmic_version_t v = GET_PMIC_VERSION(PMIC_2_ADDR); + + *val = (U32(v.device_id) << 8U) | U32(v.si_rev); + } + else + { + err = SC_ERR_PARM; + } + break; + case SC_R_BOARD_R7 : + if (ctrl == SC_C_VOLTAGE) + { + /* Example (used for testing) */ + board_print(3, "SC_R_BOARD_R7 voltage get\n"); + } + else + { + err = SC_ERR_PARM; + } + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* PMIC Interrupt (INTB) handler */ +/*--------------------------------------------------------------------------*/ +void PMIC_IRQHandler(void) +{ + /* Handle IRQ */ + switch (pmic_card) + { + case PF100_TRIPLE : + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC0_HIGH, SC_PT_ALL); + } + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC1_HIGH, SC_PT_ALL); + } + if (PMIC_IRQ_SERVICE(PMIC_2_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC2_HIGH, SC_PT_ALL); + } + break; + case PF8100_DUAL : + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC0_HIGH, SC_PT_ALL); + } + if (PMIC_IRQ_SERVICE(PMIC_1_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC1_HIGH, SC_PT_ALL); + } + break; + case PF8100_SINGLE : + if (PMIC_IRQ_SERVICE(PMIC_0_ADDR) != SC_FALSE) + { + /* Trigger client interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_TEMP, + SC_IRQ_TEMP_PMIC0_HIGH, SC_PT_ALL); + } + break; + default : + ; /* Intentional empty default */ + break; + } + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(PMIC_INT_IRQn); +} + +/*--------------------------------------------------------------------------*/ +/* Button Handler */ +/*--------------------------------------------------------------------------*/ +void SNVS_Button_IRQHandler(void) +{ + SNVS_ClearButtonIRQ(); + + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_BUTTON, SC_PT_ALL); +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Init the PMIC interface */ +/*--------------------------------------------------------------------------*/ +static void pmic_init(void) +{ + #ifndef EMUL + static sc_bool_t pmic_checked = SC_FALSE; + static lpi2c_master_config_t lpi2c_masterConfig; + sc_pm_clock_rate_t rate = SC_24MHZ; + + /* See if we already checked for the PMIC */ + if (pmic_checked == SC_FALSE) + { + sc_err_t err = SC_ERR_NONE; + + pmic_checked = SC_TRUE; + + /* Initialize the PMIC */ + board_print(3, "Start PMIC init\n"); + + /* Power up the I2C and configure clocks */ + pm_force_resource_power_mode_v(SC_R_SC_I2C, + SC_PM_PW_MODE_ON); + (void) pm_set_clock_rate(SC_PT, SC_R_SC_I2C, + SC_PM_CLK_PER, &rate); + pm_force_clock_enable(SC_R_SC_I2C, SC_PM_CLK_PER, + SC_TRUE); + + /* Initialize the pads used to communicate with the PMIC */ + pad_force_mux(SC_P_PMIC_I2C_SDA, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SDA, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + pad_force_mux(SC_P_PMIC_I2C_SCL, 0, + SC_PAD_CONFIG_OD_IN, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_I2C_SCL, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the PMIC interrupt pad */ + pad_force_mux(SC_P_PMIC_INT_B, 0, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + (void) pad_set_gp_28fdsoi(SC_PT, SC_P_PMIC_INT_B, + SC_PAD_28FDSOI_DSE_18V_1MA, SC_PAD_28FDSOI_PS_PU); + + /* Initialize the I2C used to communicate with the PMIC */ + LPI2C_MasterGetDefaultConfig(&lpi2c_masterConfig); + LPI2C_MasterInit(LPI2C_PMIC, &lpi2c_masterConfig, SC_24MHZ); + + /* Delay to allow I2C to settle */ + SystemTimeDelay(2U); + + /* Probe for PMIC 0 */ + if (pmic_get_device_id(PMIC_0_ADDR) == PF100_DEV_ID) + { /* probe for pmic at 0x8 */ + board_print(2, "Found Triple PF100 PMIC Card \n"); + PMIC_TYPE = PF100; + pmic_card = PF100_TRIPLE; + /* Probe for PMIC 1 */ + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + + /* Configure temp alarms */ + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + temp_alarm2 = SET_PMIC_TEMP_ALARM(PMIC_2_ADDR, PMIC_TEMP_MAX); + + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, SW1AB, SW_MODE_PWM_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, SW1C, SW_MODE_PWM_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_2_ADDR, SW3A, SW_MODE_PWM_STBY_PWM)); + } + /* Isolate Device Family to support 8100 & 8200 */ + else if (((pmic_get_device_id(PMIC_1_ADDR) & FAM_ID_MASK) == PF8X00_FAM_ID)) + { + PMIC_TYPE = PF8100; + pmic_card = PF8100_DUAL; + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + board_print(2, "Found Dual PF8100 PMIC Card Rev:0x%x\n",pmic_ver.si_rev); + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + temp_alarm1 = SET_PMIC_TEMP_ALARM(PMIC_1_ADDR, PMIC_TEMP_MAX); + + /* ignore OV/UV for A0/B0 & bypass current limit for A0 */ + err |= pmic_ignore_current_limit(PMIC_0_ADDR, pmic_ver); + err |= pmic_ignore_current_limit(PMIC_1_ADDR, pmic_ver); + + /* Make sure not 1.7V OTP */ + err |= pmic_match_otp(PMIC_0_ADDR, pmic_ver); + err |= pmic_match_otp(PMIC_1_ADDR, pmic_ver); + + if (pmic_ver.si_rev == PF8100_A0_REV) + { + /* set Regulation modes for MAIN and 1.8V rails */ + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW7, + SW_RUN_PWM | SW_STBY_PWM)); + } + + if (err != SC_ERR_NONE) + { + error_print("PMIC Initialization Error!\n"); + + #ifndef EMUL + /* Loop so WDOG will expire */ + HALT; + #else + return; + #endif + } + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, + 800, REG_STBY_MODE)); + } + + /* Configure GPU voltage for Dual PF8100 ( only GPU0 needed at 1.1v ) */ + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW1, + 1100, REG_RUN_MODE)); + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_1_ADDR, PF8100_SW2, + 1100, REG_RUN_MODE)); + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + err |= pf8100_pmic_wdog_enable(PMIC_1_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + } + /* Isolate Device Family to support 8100 & 8200 */ + else if ((pmic_get_device_id(PMIC_0_ADDR) & FAM_ID_MASK) + == PF8X00_FAM_ID) + { + pmic_card = PF8100_SINGLE; + PMIC_TYPE = PF8100;//set dynamic functions to use PF8100 + pmic_ver = GET_PMIC_VERSION(PMIC_0_ADDR); + board_print(2, "Found Single PF8100 PMIC Card Rev:0x%x\n",pmic_ver.si_rev); + temp_alarm0 = SET_PMIC_TEMP_ALARM(PMIC_0_ADDR, PMIC_TEMP_MAX); + + err = SC_ERR_NONE; + + /* ignore OV/UV for A0/B0 & ignore current limit for A0 */ + err |= pmic_ignore_current_limit(PMIC_0_ADDR, pmic_ver); + + if (pmic_ver.si_rev == PF8100_A0_REV) + { + /* set Regulation modes for MAIN and 1.8V rails */ + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW1, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW2, + SW_RUN_PWM | SW_STBY_PWM)); + BRD_ERR(PMIC_SET_MODE(PMIC_0_ADDR, PF8100_SW6, + SW_RUN_PWM | SW_STBY_PWM)); + } + + if (err != SC_ERR_NONE) + { + error_print("PMIC Initialization Error!\n"); + + #ifndef EMUL + /* Loop so WDOG will expire */ + HALT; + #else + return; + #endif + } + + /* Configure STBY voltage for SW1 (VDD_MAIN) */ + if (board_parameter(BOARD_PARM_KS1_RETENTION) + == BOARD_PARM_KS1_RETENTION_ENABLE) + { + uint32_t ks1_volt = 800U; + + if (OTP_KS1_07V_SUPPORT == 1U) + { + ks1_volt = 700U; + } + BRD_ERR(PMIC_SET_VOLTAGE(PMIC_0_ADDR, PF8100_SW1, + ks1_volt, REG_STBY_MODE)); + } + + /* Enable WDI detection in Standby */ + err |= pf8100_pmic_wdog_enable(PMIC_0_ADDR, SC_FALSE, SC_FALSE, SC_TRUE); + } + else + { + error_print("PMIC Card not found!\n"); + + #ifndef EMUL + /* Loop so WDOG will expire */ + HALT; + #else + return; + #endif + } + + /* Enable PMIC IRQ at NVIC level */ + NVIC_EnableIRQ(PMIC_INT_IRQn); + + board_print(3, "Finished PMIC init\n\n"); + } + #endif +} + +#ifndef EMUL +/*--------------------------------------------------------------------------*/ +/* Bypass current limit for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_ignore_current_limit(uint8_t address, + pmic_version_t ver) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t idx; + uint8_t val = 0U; + static const pf8100_vregs_t switchers[11] = + { + PF8100_SW1, + PF8100_SW2, + PF8100_SW3, + PF8100_SW4, + PF8100_SW5, + PF8100_SW6, + PF8100_SW7, + PF8100_LDO1, + PF8100_LDO2, + PF8100_LDO3, + PF8100_LDO4 + }; + + /* Loop over supplies */ + for (idx = 0U; idx < 11U; idx++) + { + /* Read the config register first */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_FALSE, + &val); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + /* Only bypass current limit for A0 silicon */ + if (ver.si_rev == PF8100_A0_REV) + { + val |= 0x20U; /* set xx_ILIM_BYPASS */ + } + + /* + * Enable the UV_BYPASS and OV_BYPASS for all LDOs. + * The SDHC LDO2 constantly switches between 3.3V and 1.8V and + * the counters are incorrectly triggered. + * Also any other LDOs (like LDO1 on the board) that is + * enabled/disabled during suspend/resume can trigger the counters. + */ + if ((switchers[idx] == PF8100_LDO1) || + (switchers[idx] == PF8100_LDO2) || + (switchers[idx] == PF8100_LDO3) || + (switchers[idx] == PF8100_LDO4)) + { + val |= 0xC0U; + } + + /* Write the config register */ + err = PMIC_REGISTER_ACCESS(address, switchers[idx], SC_TRUE, + &val); + } + + /* Stop loop if there is an error */ + if (err != SC_ERR_NONE) + { + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check correct version of OTP for PF8100 */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pmic_match_otp(uint8_t address, pmic_version_t ver) +{ + uint8_t reg_value = 0; + uint16_t match; + sc_err_t err = SC_ERR_NONE; + + if (address == PMIC_0_ADDR) + { + match = EP_PROG_ID; + } + else + { + match = EQ_PROG_ID; + } + + /* Check if C1 or later */ + if (ver.si_rev >= PF8100_C1_SI_REV) + { + uint16_t prog_id; + + /* Read Prog ID */ + err |= PMIC_REGISTER_ACCESS(address, 0x2, SC_FALSE, ®_value); + prog_id = ((reg_value << 4U) & 0x0F00U); + err |= PMIC_REGISTER_ACCESS(address, 0x3, SC_FALSE, ®_value); + prog_id |= reg_value; + + /* Test for correct OTP */ + if(prog_id == match){/* display error if 1.7v OTP */ + error_print("PMIC INVALID!\n"); + } + } + + return err; +} + +#endif + +/*--------------------------------------------------------------------------*/ +/* Get the pmic ids and switchers connected to SS. */ +/*--------------------------------------------------------------------------*/ +static void board_get_pmic_info(sc_sub_t ss,pmic_id_t *pmic_id, + uint32_t *pmic_reg, uint8_t *num_regs) +{ + /* Map SS/PD to PMIC switch */ + switch (ss) + { + case SC_SUBSYS_A35 : + pmic_init(); + if (pmic_card == PF100_TRIPLE) + { + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = SW3A; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = SW3B; + *num_regs = 2U; + } + else if (pmic_card == PF8100_DUAL) + { + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW3; + pmic_id[1] = PMIC_0_ADDR; + pmic_reg[1] = PF8100_SW4; + *num_regs = 2U; + } + else + { + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW4; + *num_regs = 1U; + } + break; + case SC_SUBSYS_GPU_0 : + pmic_init(); + if (pmic_card == PF100_TRIPLE) + { + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = SW1AB; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = SW1C; + *num_regs = 2U; + } + else if (pmic_card == PF8100_DUAL) + { + pmic_id[0] = PMIC_1_ADDR; + pmic_reg[0] = PF8100_SW1; + pmic_id[1] = PMIC_1_ADDR; + pmic_reg[1] = PF8100_SW2; + *num_regs = 2U; + } + else + { + pmic_id[0] = PMIC_0_ADDR; + pmic_reg[0] = PF8100_SW3; + *num_regs = 1U; + } + break; + default: + ; /* Intentional empty default */ + break; + } +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + +#ifdef HAS_TEST + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + /* For test_wdog */ + else if (*parm1 == 0xFFFFFFFBU) + { + HALT; + } + else + { + err = SC_ERR_PARM; + } +#endif + + return err; +} + +/** @} */ + diff --git a/platform/board/mx8qx_val/board.h b/platform/board/mx8qx_val/board.h new file mode 100755 index 0000000..1552d37 --- /dev/null +++ b/platform/board/mx8qx_val/board.h @@ -0,0 +1,140 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ + +#include "drivers/pmic/fsl_pmic.h" + +/* Defines */ + +#if 0 + #define SKIP_DDR +#endif + +/*! Configure PMIC I2C */ +#define LPI2C_PMIC LPI2C_SC + +/*! Configure PMIC I2C instance */ +#define LPI2C_PMIC_INST 0U + +/* PMIC related defines */ +#define PMIC_0_ADDR 0x8U +#define PMIC_1_ADDR 0x9U +#define PMIC_2_ADDR 0xAU + +/* + * Configure Maximum Delay based on PMIC OTP settings: + * clock freq = 20MHZ, Regulator-freq = 2.5MHz, SWxDVS Ramp = 0, + * results in a ramp rate of 7,813mV/us. + * 1100 mV / 7.813 mV/us => 140.791 us + */ +#define PMIC_MAX_RAMP 141U /* Max PMIC ramp delay in uS */ +#define PMIC_MAX_RAMP_RATE 7813U /* PMIC voltage ramp (nV) per uS */ + +/* Declare if PMIC transactions will include CRC */ +//#define PMIC_CRC +/* Declare if PMIC Secure Writes are enabled */ +//#define PMIC_SECURE_WRITE + +#define PMIC_TEMP_MAX 135U + +#define SW1ABC_STEP 25U +#define SW2_STEP 25U +#define SW3_STEP 25U +#define SW4_STEP 25U +#define VGEN12_STEP 50U +#define VGEN3456_STEP 100U + + +#define PF8100_REGULATORS 12U +#define PF100_REGULATORS 12U + +#define PF100_TRIPLE 0U +#define PF8100_DUAL 1U +#define PF8100_SINGLE 2U + +#define PF8100_C1_SI_REV 0x31U +#define EP_PROG_ID 0x0417U +#define EQ_PROG_ID 0x0418U + +/* + * Resume from KS1 ramps VDD_MAIN 200 mV (800 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 200 mV / 7.813 mV/us = 25.6 us ==> 26 us + * + */ +#define BOARD_KS1_RESUME_USEC 26U + +/* + * Resume from KS1 ramps VDD_MAIN 300 mV (700 mV to 1000 mV) + * PF8100 reg freq = 2.5 MHz, SWxDVS_RAMP = 0 => 7.813 mV/us + * 300 mV / 7.813 mV/us = 38.4 us ==> 39 us + * + */ +#define BOARD_KS1_07V_RESUME_USEC 39U + +#define BOARD_KS1_RETENTION BOARD_PARM_KS1_RETENTION_ENABLE +#define BOARD_KS1_ONOFF_WAKE BOARD_PARM_KS1_ONOFF_WAKE_ENABLE + +/* DQS2DQ can be synchronized to the ISI to avoid DDR bus contention. Define + * BOARD_DQS2DQ_SYNC to enable synchronization and configure parameters + * using the BOARD_DQS2DQ defines below. Note these defines only apply + * if BD_LPDDR4_INC_DQS2DQ is defined. BOARD_DQS2DQ_ISI_RSRC and + * BOARD_DQS2DQ_ISI_REG must be assigned to the same respective ISI + * channel. BOARD_DQS2DQ_SYNC_TIME determines the search window for ISI + * synchronization before firmware will yield to other service requests. + * Decreasing BOARD_DQS2DQ_SYNC_TIME will lower latency of other service + * requests when periodic DQS2DQ is active, but will decrease the likelihood + * of synchronizing to the ISI frame. + */ +#define BOARD_DQS2DQ_SYNC /* DQS2DQ sync enable */ +#define BOARD_DQS2DQ_ISI_RSRC SC_R_ISI_CH0 /* DQS2DQ sync ISI resource */ +#define BOARD_DQS2DQ_ISI_REG ISI0 /* DQS2DQ sync ISI registers */ +#define BOARD_DQS2DQ_SYNC_TIME 100U /* DQS2DQ sync usec timeout */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/mx8qx_val/dcd/ddr_stress_test_parser.cfg b/platform/board/mx8qx_val/dcd/ddr_stress_test_parser.cfg new file mode 100755 index 0000000..85a23c7 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/ddr_stress_test_parser.cfg @@ -0,0 +1,143 @@ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +// DDR Stress Test Parser to obtain information from the OCRAM loaded by the stress test to initialize DDR + +typedef enum { + CMD_WRITE_DATA, + CMD_SET_BIT, + CMD_CLR_BIT, + CMD_CHECK_BIT_SET, + CMD_CHECK_BIT_CLR, + CMD_COPY_BIT, + CMD_DDR_PARAM, + CMD_RUN_CBT, + CMD_RUN_RDBI_DESKEW, + CMD_RUN_VREF_TRAINING, + CMD_END=0xA5A5A5A5 +}dcd_cmd; + +typedef struct { + dcd_cmd cmd; + uint32_t addr; + uint32_t val; + uint32_t bit; +} dcd_node; + +enum{ + DRAM_TYPE, + TRAIN_INFO, + LP4X_MODE, + DATA_WIDTH, + NUM_PSTAT, + FREQUENCY0 +}; + +volatile dcd_node* dcd_ptr = (volatile dcd_node*)0x0011c000; + volatile uint32_t* dst_addr; + uint32_t regval,val,bitmask; + bool quit = false; + uint32_t ddr_pll; + board_print(1,"ddrc_init_dcd: 0x%x\r\n",(uint32_t)dcd_ptr); + + while(!quit){ + dst_addr = (volatile uint32_t*)dcd_ptr->addr; + val = dcd_ptr->val; + bitmask = dcd_ptr->bit; + + switch (dcd_ptr->cmd){ + case CMD_END: + boot_print(1,"DCD command finished\r\n"); + err = SC_ERR_NONE; + quit = true; + break; + + case CMD_WRITE_DATA: + boot_print(1,"CMD_WRITE_DATA: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + *dst_addr = val; + break; + + case CMD_SET_BIT: + boot_print(1,"CMD_SET_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval |= val; + *dst_addr = regval; + break; + + case CMD_CLR_BIT: + boot_print(1,"CMD_CLR_BIT: dst_addr=0x%x,bitmask=0x%x,val=0x%x\r\n",dst_addr,bitmask,val); + regval = *dst_addr; + regval &= ~val; + *dst_addr = regval; + break; + + case CMD_CHECK_BIT_SET: + boot_print(1,"CMD_CHECK_BIT_SET: dst_addr=0x%x,bitmask=0x%x,val=0x%x ...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval&val)==val) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_CHECK_BIT_CLR: + boot_print(1,"CMD_CHECK_BIT_CLR: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + do{ + regval = *dst_addr; + if((regval & val)==0) + break; + }while(1); + boot_print(1,"Done\r\n"); + break; + + case CMD_DDR_PARAM: + boot_print(1,"CMD_DDR_PARAM: dst_addr=0x%x,bitmask=0x%x,val=0x%x...",dst_addr,bitmask,val); + if(dcd_ptr->addr != FREQUENCY0) + { + err = SC_ERR_UNAVAILABLE; + quit = true; + boot_print(1,"Failed\r\n"); + break; + } + ddr_pll = val*1000000/2; + pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &ddr_pll); + pm_set_clock_rate(SC_PT, SC_R_DRC_1, SC_PM_CLK_MISC0, &ddr_pll); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_CBT: + boot_print(1,"CMD_RUN_CBT: param_1=0x%x,param_2=0x%x,param_3=0x%x...",dcd_ptr->addr,dcd_ptr->bit,dcd_ptr->val); + run_cbt(dcd_ptr->addr, dcd_ptr->bit, dcd_ptr->val); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_RDBI_DESKEW: + boot_print(1,"CMD_RUN_RDBI_DESKEW: param_1=0x%x...",dcd_ptr->addr); + RDBI_bit_deskew(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + case CMD_RUN_VREF_TRAINING: + boot_print(1,"CMD_RUN_VREF_TRAINING: param_1=0x%x...",dcd_ptr->addr); + DRAM_VREF_training_sw(dcd_ptr->addr); + boot_print(1,"Done\r\n"); + break; + + default: + boot_print(1,"Unknown DCD command(0x%x):dst_addr=0x%x,bit=0x%x,val=0x%x\r\n",dcd_ptr->cmd,dst_addr,bitmask,val); + err = SC_ERR_UNAVAILABLE; + quit = true; + break; + } + + dcd_ptr++; + } + + + + + diff --git a/platform/board/mx8qx_val/dcd/imx8dx_dcd_lpddr4_16bit_1.2GHz.cfg b/platform/board/mx8qx_val/dcd/imx8dx_dcd_lpddr4_16bit_1.2GHz.cfg new file mode 100755 index 0000000..574a235 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8dx_dcd_lpddr4_16bit_1.2GHz.cfg @@ -0,0 +1,373 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 2 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80002020 +DEFINE BD_DDR_RET_REGION2_SIZE 8 + + + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81081020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x1F000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00070707 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x06060606 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x06060606 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00010002 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00082013 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004567 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00081302 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004756 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x026012C1 +DATA 4 DDR_PHY_PTR1_0 0x01D500A9 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000124F8 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000004B // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001D4C // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00026 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x0000004B +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); + diff --git a/platform/board/mx8qx_val/dcd/imx8dx_ddr3_dcd_16bit_933MHz.cfg b/platform/board/mx8qx_val/dcd/imx8dx_ddr3_dcd_16bit_933MHz.cfg new file mode 100755 index 0000000..d03d31a --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8dx_ddr3_dcd_16bit_933MHz.cfg @@ -0,0 +1,302 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x080000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 1 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 16 + +/* + * Device Configuration Data (DCD) Version 20 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 933MHz. */ + uint32_t rate2 = 465000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 930MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x0000009b); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x41041001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x007200A4 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300E5 // pre_cke +DATA 4 DDRC_INIT1_0 0x005D0000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0E140006 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00200000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x000B0000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0E112010 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000C0417 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x07020307 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x05050303 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030907 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40960026 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200E3F5 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04898206 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000704 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x07070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +// DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled) + +DATA 4 DDRC_ODTCFG_0 0x06000610 +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x00000000 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 933MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 when configured for 16-bit data bus + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00026051 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004837 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00063527 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004081 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0E207 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x3A61D310 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x2D98106A // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x000077BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x000077BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000E14 +DATA 4 DDR_PHY_MR1_0 0x00000006 +DATA 4 DDR_PHY_MR2_0 0x00000020 +DATA 4 DDR_PHY_MR3_0 0x00000000 + +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x06200D08 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28210300 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x01470C17 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x002D0D09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00071FA6 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000147 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0002D976 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x040003A7 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +DATA 4 DDR_PHY_PGCR5_0 0x01010004 + +// Byte lanes 2 and 3 are commented out when configured for 16-bit data bus. Byte lane 4 commented out when ECC disabled +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults + +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// ECC Support (the following lines are uncommented when ECC is enabled) +// DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0 +// DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1 +// DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA +// DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +// CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +// CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +// DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 +// DATA 4 DDRC_SBRCTL_0 0x000FFF10 // Scrub_interval = 1 +// DATA 4 DDRC_SBRCTL_0 0x000FFF11 // Scrub_en = 1 +// DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0 diff --git a/platform/board/mx8qx_val/dcd/imx8qx_dcd_1.2GHz.cfg b/platform/board/mx8qx_val/dcd/imx8qx_dcd_1.2GHz.cfg new file mode 100755 index 0000000..7e735d7 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_dcd_1.2GHz.cfg @@ -0,0 +1,372 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x0C0000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 3 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80004040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80008000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x0003000A +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00016578 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004203 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00015867 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004320 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus + +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x026012C1 +DATA 4 DDR_PHY_PTR1_0 0x01D500A9 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000124F8 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000004B // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001D4C // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00026 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x0000004B +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qx_val/dcd/imx8qx_dcd_1.2GHz_nocbt.cfg b/platform/board/mx8qx_val/dcd/imx8qx_dcd_1.2GHz_nocbt.cfg new file mode 100755 index 0000000..20d500b --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_dcd_1.2GHz_nocbt.cfg @@ -0,0 +1,330 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x0C0000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 3 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 64 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80004040 +DEFINE BD_DDR_RET_REGION2_SIZE 16 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80008000 +DEFINE BD_DDR_RET_REGION3_SIZE 48 + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 // REFRESH_BURST = 7 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10000 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x48080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 // Enable Hardware idle period + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 // dfi_lp_en_sr, dfi_lp_wakeup_sr config + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 1200MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x0003000A +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00016578 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004203 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00015867 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004320 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0000 // DISDIC=1 (no uMCTL2 commands can go to memory) and WDQSEXT=1 +DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x001C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x001C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x32 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x33 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x00249F00 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x00000960 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0003A980 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x027004B0 // tDINIT4, tDINIT3 +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// Launch a second time DRAM initialization due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +// Wait (second time) DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +DATA 4 0x41c80504 0x400 +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qx_val/dcd/imx8qx_dcd_16bit_1.2GHz.cfg b/platform/board/mx8qx_val/dcd/imx8qx_dcd_16bit_1.2GHz.cfg new file mode 100755 index 0000000..f419ff5 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_dcd_16bit_1.2GHz.cfg @@ -0,0 +1,371 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Enable LPDDR4 derate workaround */ +DEFINE LP4_MANUAL_DERATE_WORKAROUND + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x060000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 3 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 +DEFINE BD_DDR_RET_REGION2_ADDR 0x80002020 +DEFINE BD_DDR_RET_REGION2_SIZE 8 +DEFINE BD_DDR_RET_REGION3_ADDR 0x80004000 +DEFINE BD_DDR_RET_REGION3_SIZE 24 + +/* + * Device Configuration Data (DCD) Version 16 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +//------------------------------------------- +// Reset controller core domain (required to configure it) +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure controller registers +//-------------------------------------------- +/* DRAM controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x83081020 // Set LPDDR4, BL = 16 and active ranks +DATA 4 DDRC_DERATEEN_0 0x00000203 // derate enable, derate values, byte to read MRR data +DATA 4 DDRC_DERATEINT_0 0x0124F800 // derate MR4 interval read +DATA 4 DDRC_RFSHCTL0_0 0x0021F000 +DATA 4 DDRC_RFSHTMG_0 0x004900A8 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x40030495 // pre_cke = 2ms, post_cke = 2us +DATA 4 DDRC_INIT1_0 0x00770000 // dram_rstn = 200us +DATA 4 DDRC_INIT3_0 0x00440024 // MR1, MR2 +DATA 4 DDRC_INIT4_0 0x00F10040 // MR3, MR13 +DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1618141A // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x00050526 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x060E1514 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00909000 // tmrw, tmrd, tmod +DATA 4 DDRC_DRAMTMG4_0 0x0B04060B // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x02030909 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG6_0 0x02020006 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_DRAMTMG7_0 0x00000301 // tckpde, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020510 // tCMDCKE, tCKEHCMD +DATA 4 DDRC_DRAMTMG13_0 0x0B100002 // tODTLoff, tCCDMW, tPPD +DATA 4 DDRC_DRAMTMG14_0 0x000000AD // txsr +DATA 4 DDRC_ZQCTL0_0 0x02580012 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x01E0493E // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x0499820A // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001708 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000006 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP3_0 0x1F000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP1_0 0x00070707 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x47070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 +DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 +//Performance optimizations +DATA 4 DDRC_PWRCTL_0 0x0000010A +DATA 4 DDRC_PWRTMG_0 0x00402010 +DATA 4 DDRC_HWLPCTL_0 0x003F0001 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +//Enables DFI Low Power interface +DATA 4 DDRC_DFILPCFG0_0 0x0700B100 + +//------------------------------------------- +// Release reset of controller core domain +//-------------------------------------------- +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 since it is not used for LPDDR4 +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_PGCR8_0 0x00030002 +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00061032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004578 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00071032 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004685 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // Clear these as they are unused for LPDDR4 +DATA 4 DDR_PHY_CATR0_0 0x00141000 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +DATA 4 DDR_PHY_CATR1_0 0x0103AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY +// Set-up PHY General Configuration Register +SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) if 32-bit, else 0 if 16-bit data bus +DATA 4 DDR_PHY_PGCR2_0 0x00F0A193 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR0_0 0x4B025810 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x3A981518 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 +SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008B2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x0001BBBB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus +//------------------------------------------- +// Launch PLL init +//-------------------------------------------- +DATA 4 DDR_PHY_PIR_0 0x10 +DATA 4 DDR_PHY_PIR_0 0x11 + +// Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Switch to boot frequency and launch DCAL+ZCAL +//-------------------------------------------- +DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 +// Switch to boot frequency +DATA 4 0x41C80208 0x1 // Gate functional clock to avoid glitches +DATA 4 0x41C80504 0x00800000 // Set bypass mode in DSC GPR control register +DATA 4 0x41C80204 0x1 // Ungate functional clock +// Set PLL timings for boot frequency +DATA 4 DDR_PHY_PTR0_0 0x026012C1 +DATA 4 DDR_PHY_PTR1_0 0x01D500A9 +// Launch DCAL+ZCAL +DATA 4 DDR_PHY_PIR_0 0x22 +DATA 4 DDR_PHY_PIR_0 0x23 + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL/WL +DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength + +DATA 4 DDR_PHY_MR11_0 0x54 // Set CA and DQ ODT +DATA 4 DDR_PHY_MR13_0 0x40 +DATA 4 DDR_PHY_MR22_0 0x15 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) +/* LPDDR4 mode register writes for CA and DQ VREF settings */ +DATA 4 DDR_PHY_MR12_0 0x48 +DATA 4 DDR_PHY_MR14_0 0x48 +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0C331A09 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28300411 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x0069615A // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x01800501 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK +DATA 4 DDR_PHY_DTPR4_0 0x01502B0C // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x194C160D // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS +DATA 4 DDR_PHY_PTR3_0 0x000124F8 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x0000004B // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00001D4C // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x00B00026 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 +// Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. +DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 +// Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 +DATA 4 DDR_PHY_VTCR1_0 0x07F0018F // HVIO=1, SHREN=1, SHRNK=0 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +SET_BIT 4 DDR_PHY_PGCR5_0 0x4 +DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit +// Set-up DATX8 General Configuration Registers +DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 + +//Enable PHY PLL to go into power down on DFI low power request +DATA 4 DDR_PHY_PGCR4_0 0x001900B1 + +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 + +//------------------------------------------- +// Wait end of PHY initialization then launch DRAM initialization +//------------------------------------------- +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +//------------------------------------------- +// Wait end of DRAM initialization then launch second DRAM initialization +// This is required due to errata e10945: +// Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" +// Workaround: "Run DRAM Initialization twice" +//------------------------------------------- +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +// tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. +DATA 4 DDR_PHY_PTR3_0 0x0000004B + +// Launch DRAM initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x100 +DATA 4 DDR_PHY_PIR_0 0x101 + +//------------------------------------------- +// Wait end of second DRAM initialization +//------------------------------------------- +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +//------------------------------------------- +// Run CBT (Command Bus Training) +//------------------------------------------- +//Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here +run_cbt(0x4B025810, 0x3A981518, 1); +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// configure PHY for data training +// The following register writes are recommended by SNPS prior to running training +CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift +SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation +CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 +// Per SNPS initialize BIST registers for VREF training +DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) +DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) +DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) + +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys +// case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). +DATA 4 DDR_PHY_DTCR0_0 0x000031C7 // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 + +// DQS2DQ training, Write leveling, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0010F800 +DATA 4 DDR_PHY_PIR_0 0x0010F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +// run rdbi deskew training +RDBI_bit_deskew(0); + +#ifdef MINIMIZE +// Launch VREF training +DRAM_VREF_training_hw(0); +#else +// Run vref training +DRAM_VREF_training_sw(0); +#endif + +DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 + +//DQS Drift Registers PHY0 +CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 +CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 +// Enable DQS drift detection PHY0 +DATA 4 DDR_PHY_DQSDR0_0 0x20188005 +DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 +DATA 4 DDR_PHY_DQSDR2_0 0x00070200 + +//Enable QCHAN HWidle +DATA 4 0x41c80504 0x400 +// Enable VT compensation +CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC); diff --git a/platform/board/mx8qx_val/dcd/imx8qx_dcd_emul.cfg b/platform/board/mx8qx_val/dcd/imx8qx_dcd_emul.cfg new file mode 100644 index 0000000..c7dea51 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_dcd_emul.cfg @@ -0,0 +1,263 @@ +/* +** ################################################################### +** +** Copyright 2017-2018 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#define __ASSEMBLY__ + +#include +#include + +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + + +// DSC RESET +// First reset ? ZEBU dont know if we need this first reset. 1 +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 +DATA 4 0x41C80204 0x1 + +//ddrc_lpddr4_init(inst); + + // This is for lpddr4 controller 600MHz 1.67ns and ddr 1200MHz 0.83ns +DATA 4 DDRC_MSTR_0 0x03080020 // Set LPDDR4, BL = 16 and active ranks = 2 +DATA 4 DDRC_RFSHTMG_0 0x0049006D // tREFI noroundup(3.904us/tCK)/2 36 = 24, tRFC 180ns RoundUp(tRFCmin/tCK)/2 (180/0.83)/2 134 = 86 +DATA 4 DDRC_INIT0_0 0x0002000c // post cke roundup(2us/tCK)/2 pre_cke = 2ms is too long - LPDDR4 model hacked for 20us 00-SDRAM initialization routine is run after power up . 00 and 10 the same ? +DATA 4 DDRC_INIT1_0 0x000c0000 // dram_rstn - LPDDR4 model hacked for 20us; +DATA 4 DDRC_INIT3_0 0x00440024 // MR1=0x44: nWR=24 ? BL=16; MR2=0x24: RL=24 WL=12 ? +DATA 4 DDRC_INIT4_0 0x00310000 // MR3, MR13 PDDS 110 PU-CAL VddQ/3 +DATA 4 DDRC_RANKCTL_0 0x000006cf // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x1519041a // wr2pr roundup((WL 12 + BL/2 8 + nWR 18ns)/2) = 20 hex 14 , tFAW (40ns /2) 25 hex 19 , tRASmax 8.7885us 4 , tRASmin 42ns (42ns/tCK)/2 26 hex 19 +DATA 4 DDRC_DRAMTMG1_0 0x00040526 // tXP 7.5ns roundup(tXP/2) 4, rd2pre roundup((BL/2 +8ns - 8)/2) = 5 , tRC 42ns +21ns roundup(63ns/2) = 38 hex +DATA 4 DDRC_DRAMTMG2_0 0x060b0e11 // WL 12/2, RL 24/2, rd2wr roundup((RL 24 +BL/2 8 +RU tDQSCK 3.6ns/0.83ns 4.3 +WR_PREAMBLE 2tck + RD_POSTAMBLE 0.5tck -WL 12)/2) = 14, wr2rd RU(WL 12 +BL/2 8+tWTR 10ns +1)/2 17 hex +DATA 4 DDRC_DRAMTMG3_0 0x0170c000 // tmrw tMRW ? tMRWCKEL 10CK, tmrd 10tck, tmod present on DDR3/4 only +DATA 4 DDRC_DRAMTMG4_0 0x0b04070d // trcd 18ns 11, tccd 8tck, trrd 10ns 7, trp 21ns 13 +DATA 4 DDRC_DRAMTMG5_0 0x03040305 // tcksrx 3tck, tcksre 5tck, tckesr 7.5ns tSR TBD, tcke 7.5/0.83/2 +DATA 4 DDRC_DRAMTMG6_0 0x00000004 // tckdpde, tckdpdx, tckcsx 7.5ns +DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde 5tck, tckpdx +DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE 3tck, tCKEHCMD (=tXP?) ? +DATA 4 DDRC_DRAMTMG13_0 0x00100002 // tODTLoff ODT disable, tCCDMW 4*8tck 16, tPPD 4tCK +DATA 4 DDRC_DRAMTMG14_0 0x00000039 // txsr tRFCAB 180ns+ 7.5ns +DATA 4 DDRC_ZQCTL0_0 0x025b0012 // tZQCAL 1us, tZQLAT 30ns 18 +DATA 4 DDRC_ZQCTL1_0 0x03d72e68 // tZQReset 50ns f, tzq_short_interval 0.4s lpddr3 ? +DATA 4 DDRC_DFITMG0_0 0x0498820a // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00001608 // dfi_tphy_rdcslat, dfi_tphy_wrcslat +DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0x80400003 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x00010002 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x00000016 // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080202 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP2_0 0x02020000 +DATA 4 DDRC_ADDRMAP3_0 0x02020202 +DATA 4 DDRC_ADDRMAP4_0 0x00001f1f // addrmap_col_b11, addrmap_col_b10 +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0f070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 + +// These should not be here +//DATA 4 DDRC_ADDRMAP1_0 0x00171717 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +//DATA 4 DDRC_ADDRMAP5_0 0x03030303 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +//DATA 4 DDRC_ADDRMAP6_0 0x03030303 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 + +DATA 4 DDRC_ODTMAP_0 0x00002211 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +// in ddrc_init_inst() +CLR_BIT 4 DDRC_DFIMISC_0 0x00000001 +// As DRAM init sequence will be run by controller set 0x0 to skip_dram_init field +CLR_BIT 4 DDRC_INIT0_0 0xC0000000 + + +// Do we need this as well? Didnt need to set before ZEBU 2 +DATA 4 DDRC_PWRCTL_0 0x10D + +// Toggle Reset ... ZEBU NEED THIS? 3 +//DATA 4 0x41C80208 0x1 +//DATA 4 0x41C80044 0x4 +//DATA 4 0x41C80204 0x1 + + //------------------------------------------- + // Configure registers for PHY initialization + // Timings are computed for a PHY at 600MHz (DRAM at 1200MHz) 600MHz 1.67ns ddr 1200MHz 0.83ns + //------------------------------------------- + +//ddr_phy_lpddr4_phy_init() + + // Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank + + // Set-up PHY General Configuration Register + // PGCR0,1,4,5,6,7 are untouched +DATA 4 DDR_PHY_PGCR0_0 0x87001e00 // address copy +DATA 4 DDR_PHY_PGCR2_0 0x00F0A3CC // Set tREFPRD (9*3.904us) +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity + + // Set-up PHY Timing Register + // PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST + // CAST32(DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK=25us, tPLLRST=9us +DATA 4 DDR_PHY_PTR1_0 0x0D701C20 // tPLLLOCK reduced to 4.3us, tPLLRST=9us + + // Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x00000000 // FREQSEL=0 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x08000000 + + // Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x001FEC58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) + + // Set-up Impedance Controller Program Register + // ZQnPR0, ZQnPR1 are untouched, lpddr4 PD_REFSEL should not be default value, FIXME + +// ddr_phy_launch_init() + // Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x40 + + // Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x41 + + //------------------------------------------- + // Configure registers for DRAM initialization + //------------------------------------------- + //ddr 1200MHz 0.83ns + +// ddr_phy_lpddr4_dram_init() + + // Set-up Mode Register + // MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR1_0 0x44 // Set BL, WR-PRE, nWR, RPST +DATA 4 DDR_PHY_MR2_0 0x24 // Set RL=24/WL=12 +DATA 4 DDR_PHY_MR3_0 0x31 // Set drive strength to 40 ohms typical pull-down/pull-up + + // Set-up DRAM Timing Parameters Register + // DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x0d331a05 // tRRD (10/0.83 = 13), tRAS (42ns/0.83 = 51 ), tRP (21ns/0.83 = 26 1A), tRTP (101) +DATA 4 DDR_PHY_DTPR1_0 0x28318C0a // tWLMRD, tFAW(40ns/0.83 = 49 31), tODTUP(odt is disable), tMRD(10 tck) +DATA 4 DDR_PHY_DTPR2_0 0x003a00E2 // tRTW, tRTODT, tCMDCKE, tCKE (7.5 / 0.83 = 10 a), tXS(180ns + 7.5ns / 0.83 = 226 ) +DATA 4 DDR_PHY_DTPR3_0 0x01800502 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (3.6ns / 0.83 ) (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x01C0000a // tRFC(180ns/0.83), tWLO, tXP (7.5ns / 0.83 ) +DATA 4 DDR_PHY_DTPR5_0 0x004c160d // tRC (tRAS + tRPab = (42+21)/0.83 = 76 ), tRCD (18ns / 0.83 = 22 ), tWTR (10ns / 0.83 13 d) + + // Set-up PHY Timing Register + // DATA 4 DDR_PHY_PTR3_0 0x0030D400 // tDINIT0 - 2ms +DATA 4 DDR_PHY_PTR3_0 0x00005E21 // tDINIT0 - memory model hacked to 20us 25097 +DATA 4 DDR_PHY_PTR4_0 0x0000096A // tDINIT1 (2000ns) 2410 +DATA 4 DDR_PHY_PTR5_0 0x00005E21 // tDINIT2 - normally 200us but memory model hacked to 20us +DATA 4 DDR_PHY_PTR6_0 0x025004B5 // tDINIT4 (30ns) 37, tDINIT3 (1us) 1205 + + // RDIMMGCR0-2 RDIMMGCR0-4?? + + // Set-up DATX8 Common Configuration Register + // DXCCR is untouched + + // Set-up DDR System General Configuration Register + // DSGCR is untouched + + // Set-up ODT Configuration Register + // ODTCR is untouched + + // Set-up Anti-Aging Control Register + // AACR is untouched + + // Set-up Data Training Address Register + // DTAR0-3 are untouched + // !! DTAR3 is not described in spec !! + + // Set-up AC I/O Configuration Register + // ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070800 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 + + // IOVCR0-1, DXnGCR0-4??, CALBYP + + // Set-up VREF Training Control Registers +DATA 4 DDR_PHY_VTCR0_0 0xF0032019 // CK1, CK0 +DATA 4 DDR_PHY_VTCR1_0 0x07F00173 // HVIO=1, SHREN=1, SHRNK=0 + + // Set-up DATX8 General Configuration Registers + // DXnGCR0-4 are untouched + + // Set-up DATX8 DX Control Register 2 +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x081800 // PREOEX=2tCK, POSOEX=0.5tCK + + // Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x09000000 // I/O mode = LPDDR4 + + // Set-up DATX8 DQS Control Register +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x013E4091 // DQS resistor + +//ddr_phy_wait_init_done() + // Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + +// ddr_phy_launch_init() + // Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x40000 + + // Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x40001 + +// ddr_phy_wait_init_done + // Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 + + +// Toggle Reset? ZEBU dont know if correct reset inserted here. 4 +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0xF +//DSC_SetReset(SC_DSC_DRC_0, BIT(RST_DDR_CRESETN), SC_TRUE); +DATA 4 0x41C80204 0x1 + + +// dram_init_inst() +CLR_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 0 +SET_BIT 4 DDRC_DFIMISC_0 0x00000001 // Set DFIMISC.dfi_init_complete_en to 1 - Trigger DRAM initialization +SET_BIT 4 DDRC_SWCTL_0 0x00000001 // Set SWCTL.sw_done to 1 +CHECK_BITS_SET 4 DDRC_SWSTAT_0 0x00000001 // Wait for SWSTAT.sw_done_ack to become 1 + + //Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 diff --git a/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_800MHz.cfg b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_800MHz.cfg new file mode 100755 index 0000000..bea7d33 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_800MHz.cfg @@ -0,0 +1,303 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 1 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 + +/* + * Device Configuration Data (DCD) Version 22 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 800MHz. */ + uint32_t rate2 = 400000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 800MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x00000085); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x00620068 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300C5 // pre_cke +DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0C700006 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00180000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x00090000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0C101B0E // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000A0314 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x04060609 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002006 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x06020306 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x04040302 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40800020 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200C350 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04878205 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000503 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +// DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled) + +DATA 4 DDRC_ODTCFG_0 0x0600060C +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x00000000 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 800MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0C170 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus or when ECC disabled + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x000077BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x000077BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000C70 +DATA 4 DDR_PHY_MR1_0 0x00000006 +DATA 4 DDR_PHY_MR2_0 0x00000018 +DATA 4 DDR_PHY_MR3_0 0x00000000 + +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x061C0B06 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28200000 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01040200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x00D00C14 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x00270B07 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00061A80 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x000000D0 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00027100 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x04000321 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +DATA 4 DDR_PHY_PGCR5_0 0x01010004 + +// Byte lanes 2 and 3 are commented out when configured for 16-bit data bus. Byte lane 4 commented out when ECC disabled +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults + +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// ECC Support (the following lines are uncommented when ECC is enabled) +// DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0 +// DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1 +// DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA +// DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +// CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +// CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +// DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 +// DATA 4 DDRC_SBRCTL_0 0x000FFF10 // Scrub_interval = 1 +// DATA 4 DDRC_SBRCTL_0 0x000FFF11 // Scrub_en = 1 +// DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0 + diff --git a/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_800MHz_ecc.cfg b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_800MHz_ecc.cfg new file mode 100755 index 0000000..9c7bddb --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_800MHz_ecc.cfg @@ -0,0 +1,303 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 1 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 + +/* + * Device Configuration Data (DCD) Version 22 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 800MHz. */ + uint32_t rate2 = 400000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 800MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x00000085); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x00620068 // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300C5 // pre_cke +DATA 4 DDRC_INIT1_0 0x00500000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0C700006 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00180000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x00090000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0C101B0E // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000A0314 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x04060609 // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002006 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x06020306 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x04040302 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40800020 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200C350 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04878205 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000503 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled) + +DATA 4 DDRC_ODTCFG_0 0x0600060C +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x00000000 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 800MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00005281 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00004736 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0C170 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x32019010 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x27100E10 // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus or when ECC disabled + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x000077BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x000077BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000C70 +DATA 4 DDR_PHY_MR1_0 0x00000006 +DATA 4 DDR_PHY_MR2_0 0x00000018 +DATA 4 DDR_PHY_MR3_0 0x00000000 + +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x061C0B06 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28200000 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01040200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x00D00C14 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x00270B07 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00061A80 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x000000D0 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x00027100 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x04000321 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +DATA 4 DDR_PHY_PGCR5_0 0x01010004 + +// Byte lanes 2 and 3 are commented out when configured for 16-bit data bus. Byte lane 4 commented out when ECC disabled +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults + +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// ECC Support (the following lines are uncommented when ECC is enabled) +DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0 +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1 +DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA +DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 +DATA 4 DDRC_SBRCTL_0 0x000FFF10 // Scrub_interval = 1 +DATA 4 DDRC_SBRCTL_0 0x000FFF11 // Scrub_en = 1 +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0 + diff --git a/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz.cfg b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz.cfg new file mode 100755 index 0000000..e49a16f --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz.cfg @@ -0,0 +1,303 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 1 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 + +/* + * Device Configuration Data (DCD) Version 22 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 933MHz. */ + uint32_t rate2 = 465000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 930MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x0000009B); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x0072007A // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300E5 // pre_cke +DATA 4 DDRC_INIT1_0 0x005D0000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0E140006 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00200000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x000B0000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0E112010 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000C0417 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x07020307 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x05050303 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40960026 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200E3F5 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04898206 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000704 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +// DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled) + +DATA 4 DDRC_ODTCFG_0 0x06000610 +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x00000000 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 933MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled + +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00000000 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00000000 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0E207 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x3A61D310 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x2D98106A // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus or when ECC disabled + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x000077BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x000077BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000E14 +DATA 4 DDR_PHY_MR1_0 0x00000006 +DATA 4 DDR_PHY_MR2_0 0x00000020 +DATA 4 DDR_PHY_MR3_0 0x00000000 + +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x06200D08 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28210300 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x00F30C17 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x002D0D09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00071FA6 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x000000F3 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0002D976 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x040003A7 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +DATA 4 DDR_PHY_PGCR5_0 0x01010004 + +// Byte lanes 2 and 3 are commented out when configured for 16-bit data bus. Byte lane 4 commented out when ECC disabled +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +// DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +// DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults + +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// ECC Support (the following lines are uncommented when ECC is enabled) +// DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0 +// DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1 +// DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA +// DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +// CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +// CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +// DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 +// DATA 4 DDRC_SBRCTL_0 0x000FFF10 // Scrub_interval = 1 +// DATA 4 DDRC_SBRCTL_0 0x000FFF11 // Scrub_en = 1 +// DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0 + diff --git a/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz_ecc.cfg b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz_ecc.cfg new file mode 100755 index 0000000..36d25c7 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz_ecc.cfg @@ -0,0 +1,302 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 1 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 + +/* + * Device Configuration Data (DCD) Version 22 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 933MHz. */ + uint32_t rate2 = 465000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 930MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x0000009B); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x0072007A // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300E5 // pre_cke +DATA 4 DDRC_INIT1_0 0x005D0000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0E140006 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00200000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x000B0000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0E112010 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000C0417 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x07020307 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x05050303 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40960026 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200E3F5 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04898206 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000704 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled) + +DATA 4 DDRC_ODTCFG_0 0x06000610 +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x00000000 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 933MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00005281 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00004736 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0E207 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x3A61D310 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x2D98106A // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus or when ECC disabled + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x000077BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x000077BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000E14 +DATA 4 DDR_PHY_MR1_0 0x00000006 +DATA 4 DDR_PHY_MR2_0 0x00000020 +DATA 4 DDR_PHY_MR3_0 0x00000000 + +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x06200D08 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28210300 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x00F30C17 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x002D0D09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00071FA6 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x000000F3 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0002D976 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x040003A7 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +DATA 4 DDR_PHY_PGCR5_0 0x01010004 + +// Byte lanes 2 and 3 are commented out when configured for 16-bit data bus. Byte lane 4 commented out when ECC disabled +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults + +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// ECC Support (the following lines are uncommented when ECC is enabled) +DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0 +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = 1 +DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA +DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 +DATA 4 DDRC_SBRCTL_0 0x000FFF10 // Scrub_interval = 1 +DATA 4 DDRC_SBRCTL_0 0x000FFF11 // Scrub_en = 1 +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0 + diff --git a/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz_ecc_early_cpu.cfg b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz_ecc_early_cpu.cfg new file mode 100755 index 0000000..84c9b45 --- /dev/null +++ b/platform/board/mx8qx_val/dcd/imx8qx_ddr3_dcd_933MHz_ecc_early_cpu.cfg @@ -0,0 +1,382 @@ +#define __ASSEMBLY__ + +#include +#include + +/*! Configure DDR retention support */ +DEFINE BD_DDR_RET /* Add/remove DDR retention */ + +DEFINE BD_DDR_SIZE 0x040000000 /* Total board DDR density (bytes) calculated based on RPA config */ +DEFINE BD_DDR_RET_NUM_DRC 1 /* Number for DRCs to retain */ +DEFINE BD_DDR_RET_NUM_REGION 1 /* DDR regions to save/restore */ + +/* Descriptor values for DDR regions saved/restored during retention */ +DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 +DEFINE BD_DDR_RET_REGION1_SIZE 32 + +/* + * Device Configuration Data (DCD) Version 19 + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Only valid if called by SCFW */ +if (action != BOARD_DDR_COLD_INIT) +{ + return SC_ERR_NONE; +} +if (rom_caller == SC_FALSE) +{ + /* Set the DRC rate to achieve a DRAM rate as close as possible to 933MHz. */ + uint32_t rate2 = 465000000U; + (void) pm_set_clock_rate(SC_PT, SC_R_DRC_0, SC_PM_CLK_MISC0, &rate2); +} +else +{ + /* gate the cslice and ssslice */ + CLR_BIT 4 0x41C83800 0xDC000000 + CLR_BIT 4 0x41C82C00 0xDC00001F + + /* relock HP PLL to 930MHz */ + /* Enable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,8,0x40000000); + /* power down PLL and clear dividers */ + DSC_AIRegisterWrite(0x24,0,8,0x000020FF); + /* Set the divider */ + DSC_AIRegisterWrite(0x24,0,4,0x0000009B); + /* power up PLL and set hold ring off */ + DSC_AIRegisterWrite(0x24,0,4,0x00003000); + SYSCTR_TimeDelay(25); + /* clear hold ring off */ + DSC_AIRegisterWrite(0x24,0,8,0x00001000); + SYSCTR_TimeDelay(50); + /* disable PLL isolation */ + DSC_AIRegisterWrite(0x24,0,4,0x40000000); + + /* Ungate cslice and ssslice */ + SET_BIT 4 0x41C82C00 0x4C000002 + SET_BIT 4 0x41C83800 0x4C000000 +} + +if (rom_caller == SC_TRUE) +{ +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x8 // Assert uMCTL2 core reset +DATA 4 0x41C80204 0x1 // Start functional clocks. + +/* DRAM 0 controller configuration begin */ +DATA 4 DDRC_MSTR_0 0x81040001 // Set DDR3l, BL = 16 and active ranks +DATA 4 DDRC_RFSHTMG_0 0x0072007A // tREFI, tRFC +DATA 4 DDRC_INIT0_0 0x400300E5 // pre_cke +DATA 4 DDRC_INIT1_0 0x005D0000 // dram_rstn +DATA 4 DDRC_INIT3_0 0x0E140006 // MR0, MR1 +DATA 4 DDRC_INIT4_0 0x00200000 // MR2, MR3 +DATA 4 DDRC_INIT5_0 0x000B0000 // ZQINIT +DATA 4 DDRC_DIMMCTL_0 0x00000000 // DIMMCTL register for address mirroring +DATA 4 DDRC_RANKCTL_0 0x0000072F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd +DATA 4 DDRC_DRAMTMG0_0 0x0E112010 // wr2pr, tFAW, tRASmax, tRASmin +DATA 4 DDRC_DRAMTMG1_0 0x000C0417 // tXP, rd2pre, tRC +DATA 4 DDRC_DRAMTMG2_0 0x0507060B // WL, RL, rd2wr, wr2rd +DATA 4 DDRC_DRAMTMG3_0 0x00002008 // T_MOD, T_MRD +DATA 4 DDRC_DRAMTMG4_0 0x07020307 // trcd, tccd, trrd, trp +DATA 4 DDRC_DRAMTMG5_0 0x05050303 // tCKCKEH, tCKCKEL, tckesr, tcke +DATA 4 DDRC_DRAMTMG8_0 0x03030905 // tckdpde, tckdpdx, tckcsx +DATA 4 DDRC_ZQCTL0_0 0x40960026 // tZQCAL, tZQLAT +DATA 4 DDRC_ZQCTL1_0 0x0200E3F5 // tZQReset, tzq_short_interval +DATA 4 DDRC_DFITMG0_0 0x04898206 +DATA 4 DDRC_DFITMG1_0 0x00060303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable +DATA 4 DDRC_DFITMG2_0 0x00000704 +DATA 4 DDRC_DFIMISC_0 0x00000001 // dfi_data_cs_polarity +DATA 4 DDRC_DFIUPD0_0 0xE0400018 // Disable the automatic dfi_ctrlupd_req generation +DATA 4 DDRC_DFIUPD1_0 0x001A0057 // dfi_ctrlupd_req generation interval generation (min and max) +DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en +DATA 4 DDRC_ADDRMAP0_0 0x0000001F // addrmap_cs_bit0 +DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 +DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 +DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated +DATA 4 DDRC_ADDRMAP5_0 0x07070707 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 +DATA 4 DDRC_ADDRMAP6_0 0x0F070707 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 +DATA 4 DDRC_ECCCFG0_0 0x044FFFC4 // ecc support (uncommented when ECC is enabled) + +DATA 4 DDRC_ODTCFG_0 0x06000610 +DATA 4 DDRC_ODTMAP_0 0x00000001 // rank[3:0]_wr_odt, rank[3:0]_wr_odt +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 + +DATA 4 DDRC_SCHED_0 0x7F001F05 // 30ns delay upon read store empty if write pending, CAM (32 entries) + +DATA 4 DDRC_DFITMG0_SHADOW_0 0x00808000 + +DATA 4 DDRC_PWRCTL_0 0x00000000 + +DATA 4 0x41C80208 0x1 +DATA 4 0x41C80044 0x4 +DATA 4 0x41C80204 0x1 + +//------------------------------------------- +// Configure registers for PHY initialization +// Timings are computed for 933MHz DRAM operation +//-------------------------------------------- +// Following are uncommented (to disable) or commented (to enable) particular byte lanes +// DATA 4 DDR_PHY_DX2GCR1_0 0x55556000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR1_0 0x55556000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR1_0 0x55556000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR2_0 0xAAAAAAAA // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR3_0 0x0029A4A4 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR3_0 0x0029A4A4 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR3_0 0x0029A4A4 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR4_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR4_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR4_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// DATA 4 DDR_PHY_DX2GCR5_0 0x00000000 // uncommented to disable byte lane 2 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX3GCR5_0 0x00000000 // uncommented to disable byte lane 3 when configured for 16-bit data bus +// DATA 4 DDR_PHY_DX4GCR5_0 0x00000000 // uncommented to disable byte lane 4 when ECC disabled +// Set-up DRAM Configuration Register +DATA 4 DDR_PHY_DCR_0 0x0000040B // DDR3 selection with 8 bank +// Set-up byte and bit swapping registers +DATA 4 DDR_PHY_DX0DQMAP0_0 0x00071628 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX0DQMAP1_0 0x00004053 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX1DQMAP0_0 0x00073826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX1DQMAP1_0 0x00004150 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX2DQMAP0_0 0x00053608 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX2DQMAP1_0 0x00004271 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX3DQMAP0_0 0x00053826 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX3DQMAP1_0 0x00004170 // DQ bit 5/6/7 and DM remapping +DATA 4 DDR_PHY_DX4DQMAP0_0 0x00005281 // DQ bit 0/1/2/3/4 remapping +DATA 4 DDR_PHY_DX4DQMAP1_0 0x00004736 // DQ bit 5/6/7 and DM remapping +// Set-up PHY General Configuration Register +// PGCR1,4,5,6,7 are untouched +SET_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=1 (no uMCTL2 commands can go to memory) +DATA 4 DDR_PHY_PGCR0_0 0x07001E00 // Set ADCP=1 (Address Copy) +DATA 4 DDR_PHY_PGCR2_0 0x00F0E207 // Set tREFPRD +DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity +// Set-up PHY Timing Register +// PTR2 is untouched +DATA 4 DDR_PHY_PTR0_0 0x3A61D310 // tPLLPD, tPLLGS, tPHYRST +DATA 4 DDR_PHY_PTR1_0 0x2D98106A // tPLLLOCK, tPLLRST +// Set-up PLL Control Register +DATA 4 DDR_PHY_PLLCR0_0 0x011C0000 +DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x011C0000 +// SET_BIT 4 DDR_PHY_DX8SL1PLLCR0_0 0x20000000 // uncommented to disable byte lanes 2 and 3 PLL when configured for 16-bit data bus +// SET_BIT 4 DDR_PHY_DX8SL2PLLCR0_0 0x20000000 // uncommented to disable byte lanes 4 and 5 PLL when configured for 16-bit data bus or when ECC disabled + +// Set-up Impedance Control Register +DATA 4 DDR_PHY_ZQCR_0 0x008A2858 // Set ODT_MODE=0b10(DDR3 stype pullup) +// ZPROG_DRAM_ODT and ZPROG_HOST_ODT +DATA 4 DDR_PHY_ZQ0PR0_0 0x000077BB // Impedance control for CA bus +DATA 4 DDR_PHY_ZQ1PR0_0 0x000077BB // Impedance control for DQ bus +// Set-up PHY Initialization Register +DATA 4 DDR_PHY_PIR_0 0x72 +// Launch initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x73 + + +//------------------------------------------- +// Configure registers for DRAM initialization +//------------------------------------------- +// Set-up Mode Register +// MR0, MR3, MR4, MR5 MR6 are untouched +DATA 4 DDR_PHY_MR0_0 0x00000E14 +DATA 4 DDR_PHY_MR1_0 0x00000006 +DATA 4 DDR_PHY_MR2_0 0x00000020 +DATA 4 DDR_PHY_MR3_0 0x00000000 + +// Set-up DRAM Timing Parameters Register +// DTPR6 is untouched +DATA 4 DDR_PHY_DTPR0_0 0x06200D08 // tRRD, tRAS, tRP, tRTP +DATA 4 DDR_PHY_DTPR1_0 0x28210300 // tWLMRD, tFAW, tODTUP, tMRD +DATA 4 DDR_PHY_DTPR2_0 0x01060200 // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS +DATA 4 DDR_PHY_DTPR3_0 0x02000000 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK (FIXME double check tDLLK) +DATA 4 DDR_PHY_DTPR4_0 0x00F30C17 // tRFC, tWLO, tXP +DATA 4 DDR_PHY_DTPR5_0 0x002D0D09 // tRC, tRCD, tWTR +// Set-up PHY Timing Register +DATA 4 DDR_PHY_PTR3_0 0x00071FA6 // tDINIT0 +DATA 4 DDR_PHY_PTR4_0 0x000000F3 // tDINIT1 +DATA 4 DDR_PHY_PTR5_0 0x0002D976 // tDINIT2 +DATA 4 DDR_PHY_PTR6_0 0x040003A7 // tDINIT4, tDINIT3 + + +// Set-up ODT Configuration Register +// DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. +DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write +DATA 4 DDR_PHY_ODTCR_0 0x00010000 // ODT of rank1 disabled + + +// Set-up AC I/O Configuration Register +// ACIOCR1-4 are untouched +DATA 4 DDR_PHY_ACIOCR0_0 0x30070400 // PNUM2 (i.e.DDR3) selection [10:11] = 0x2 +DATA 4 DDR_PHY_ACIOCR5_0 0x00000000 // I/O mode = DDR3 +DATA 4 DDR_PHY_IOVCR0_0 0x03000000 +// Set-up DATX8 General Configuration Registers +// DXnGCR0-4 are untouched +DATA 4 DDR_PHY_PGCR5_0 0x01010004 + +// Byte lanes 2 and 3 are commented out when configured for 16-bit data bus. Byte lane 4 commented out when ECC disabled +DATA 4 DDR_PHY_DX0GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX1GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX2GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX3GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX4GCR5_0 0x09090930 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults +DATA 4 DDR_PHY_DX0GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX1GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX2GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX3GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults +DATA 4 DDR_PHY_DX4GCR4_0 0x020BBF04 // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults + +// Set-up DATX8 DX Control Register 2 +// PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH=0xA +DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1400 +// Set-up DATX8 IO Control Register +DATA 4 DDR_PHY_DX8SLbIOCR_0 0x00000000 // I/O mode = DDR3 + +// Wait PHY initialization end then launch DRAM initialization +// Wait for bit 0 of PGSR0 to be '1' +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 // Check that no error occured + +// Launch DRAM 0 initialization (set bit 0) +DATA 4 DDR_PHY_PIR_0 0x180 +DATA 4 DDR_PHY_PIR_0 0x181 + +// DRAM 0 initialization end +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//---------------------------------------------------------------// +// DATA training +//---------------------------------------------------------------// +// Set-up Data Training Configuration Register +// Note that DTCR0.RFSHDT are set to 0x0 as a workaround for PHY bug (Synopsys +// case 9001045655: Design limitation in DDR3 mode: REFRESH must be disabled during DQS2DQ training). +// (FYI avoiding refresh during training leads to Denali error (CUMULATIVE_REFRESH_POSTPONE_EXCEEDS_MAX_ALLOWED). +DATA 4 DDR_PHY_DTCR0_0 0x800031CF // Set DTRPTN to 0x7. RFSHDT=0 +DATA 4 DDR_PHY_DTCR1_0 0x00010237 // Set RANKEN=3 + +// Launch Write leveling +DATA 4 DDR_PHY_PIR_0 0x200 +DATA 4 DDR_PHY_PIR_0 0x201 +// Wait Write leveling to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 + +// Set DQS/DQSn glitch suppression resistor for training PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012640F7 +// Launch Read DQS training +DATA 4 DDR_PHY_PIR_0 0x400 +DATA 4 DDR_PHY_PIR_0 0x401 +// Wait Read DQS training to complete PHY0 +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 +// Remove DQS/DQSn glitch suppression resistor PHY0 +DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01264000 + +// Write leveling adjust, Deskew and eye trainings +DATA 4 DDR_PHY_PIR_0 0x0000F800 +DATA 4 DDR_PHY_PIR_0 0x0000F801 +// Wait for training to complete +CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 +CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 + +//Re-allow uMCTL2 to send commands to DDR +CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020000 // DISDIC=0, PUBMODE=0 + +//Check that controller is ready to operate +CHECK_BITS_SET 4 DDRC_STAT_0 0x1 + +// ECC Support for the ROM portion of the DDR initialization + /* Initialize DDR sections for early CPUs. + * These sections are only for the first images to be loaded into DDR and should be minimized to optimize for boot time. + */ + +DATA 4 DDRC_PCTRL_0_0 0x00000000 // Disable Port 0 +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_mode = write, scub_en = 0 +DATA 4 DDRC_SBRWDATA0_0 0x55AA55AA // SBRWDATA0 = 55AA55AA + + +//========================== Init 4MB from start_addr 0x00000000 =============================// + +/* Set DSC_GPRCTRL to make sure: + * + * Note that: + * sbr_address_start_mask[35:31] is forced to 0. + * sbr_address_start_mask[30:20] is controlled through DSC_GPRCTRL.Bit39,38,37,36,35,34,33,32,26,25,24. + * sbr_address_start_mask[19:00] is forced to 0. + * + * Note that: + * sbr_address_range_mask[35:31] is forced to 0. + * sbr_address_range_mask[30:20] is controlled through DSC_GPRCTRL.Bit47,46,45,44,43,42,41,40,31,30,29. + * sbr_address_range_mask[19:00] is controlled through DSC_GPRCTRL.Bit21 + * + * GPRCTRL is accessed through 2 separate transactions 0x41C80500 for bits [31:0] + * and 0x41C80510 for bits [63:32]. + * Note that we use the clear and the set offsets which are 8 and 4 respectively. + * + */ + +/* Scrub the first 32MB + *sbr_address_start_mask = 0x000000000 + *sbr_address_range_mask = 0x0007FFFFF + */ + +DATA 4 0x41C80508 0xE7200000 //clear all the start/range masks +DATA 4 0x41C80518 0x0000FFFF //clear all the start/range masks +DATA 4 0x41C80504 0xE0200000 //scrub only 32MB at beginning +DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 + +// Scrub the last 32MB +DATA 4 0x41C80508 0xE7200000 //clear all the start/range masks +DATA 4 0x41C80518 0x0000FFFF //clear all the start/range masks +DATA 4 0x41C80504 0xE0200000 //scrub last 32 MB +DATA 4 0x41C80514 0x1F1F //scrub last 32 MB +DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 +CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 + +// Enable AXI port so that we can start to load images into first 32MB and last 32MB +DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable Port 0 + + +// Scrub the uninitialized space (i.e. [32MB, 1GB-32MB]) +DATA 4 0x41C80508 0xE7200000 //clear all the start/range masks +DATA 4 0x41C80518 0x0000FFFF //clear all the start/range masks +DATA 4 0x41C80504 0xE0200000 //configure start_mask to 0x800000 and range_mask to 0xF7FFFFF +DATA 4 0x41C80514 0x00001E01 //configure start_mask to 0x800000 and range_mask to 0xF7FFFFF +DATA 4 DDRC_SBRCTL_0 0x00000015 // Scrub_en = 1 + +/* note that at this point only the first and last 32 MB is accessible. + * This is done to help with the boot time of early CPUs that need to use a small portion of DDR. + * Also at this time the DDR controller is scrubbing the remaining DDR. + * So, during this period, there is a competition for ddr bandwidth between "early CPUs access" versus "remaining DDR scrubbing". + */ +//========= End of DCD ==============// +} +else +{ +/* This portion of the DCD is run after any early CPUs + * do this once weve booted early cpus + * This section takes quite a bit ~200 ms + */ + +CHECK_BITS_SET 4 DDRC_SBRSTAT_0 0x2 // Wait for Scrub done +CHECK_BITS_CLR 4 DDRC_SBRSTAT_0 0x1 // Wait for Scrub done +DATA 4 DDRC_SBRCTL_0 0x00000014 // Scrub_en = 0 +//at this time, all the DDR space have been initialized. + +// Enable the ECC protect for full ddr space +DATA 4 DDRC_SBRCTL_0 0x000FFF10 // Scrub_interval = 1 +DATA 4 0x41C80508 0xE7200000 //clear all the start/range masks +DATA 4 0x41C80518 0x0000FFFF //clear all the start/range masks +DATA 4 DDRC_SBRCTL_0 0x000FFF11 // Scrub_en = 1 + +} diff --git a/platform/board/none/Makefile b/platform/board/none/Makefile new file mode 100755 index 0000000..776f391 --- /dev/null +++ b/platform/board/none/Makefile @@ -0,0 +1,44 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +OBJS += $(OUT)/board/none/board.o $(OUT)/board/board_common.o + +ifneq ($(HW), SIMU) + OBJS += $(OUT)/board/board.o +endif + +DIRS += $(OUT)/board/none + +RSRC_MD += $(SRC)/board/none/resource.txt + +CTRL_MD += $(SRC)/board/none/control.txt + diff --git a/platform/board/none/board.bom b/platform/board/none/board.bom new file mode 100755 index 0000000..dd4ca27 --- /dev/null +++ b/platform/board/none/board.bom @@ -0,0 +1,33 @@ +## ################################################################### +## +## Copyright 2019 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + + diff --git a/platform/board/none/board.c b/platform/board/none/board.c new file mode 100755 index 0000000..da11e44 --- /dev/null +++ b/platform/board/none/board.c @@ -0,0 +1,589 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing empty implementation of the board. + * + * @addtogroup NO_BRD BRD: No Board + * + * Module for no board access. + * + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/build_info.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#ifdef SIMU + #include "main/simu.h" +#endif +#include "all_svc.h" +#include "drivers/lpuart/fsl_lpuart.h" +#include "pads.h" + +/* Local Defines */ + +/*! + * @name Board Configuration + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_NUM_RSRC 11U +#define BRD_NUM_CTRL 6U +/** @} */ + +/*! + * @name Board Resources + * DO NOT CHANGE - must match object code. + */ +/** @{ */ +#define BRD_R_BOARD_PMIC_0 0U +#define BRD_R_BOARD_PMIC_1 1U +#define BRD_R_BOARD_PMIC_2 2U +#define BRD_R_BOARD_R0 3U +#define BRD_R_BOARD_R1 4U +#define BRD_R_BOARD_R2 5U +#define BRD_R_BOARD_R3 6U +#define BRD_R_BOARD_R4 7U +#define BRD_R_BOARD_R5 8U +#define BRD_R_BOARD_R6 9U +#define BRD_R_BOARD_R7 10U +/** @} */ + +/*! Configure debug UART */ +#define LPUART_DEBUG LPUART_SC + +/*! Configure debug UART instance */ +#define LPUART_DEBUG_INST 0 + +#ifdef EMUL + /*! Configure debug baud rate */ + #define DEBUG_BAUD 4000000U +#else + /*! Configure debug baud rate */ + #define DEBUG_BAUD 115200U +#endif + +/* Local Types */ + +/* Local Functions */ + +/* Local Variables */ + +/*! + * This constant contains info to map resources to the board. + * DO NOT CHANGE - must match object code. + */ +const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD] = +{ + RSRC(PMIC_0, 0, 0), + RSRC(PMIC_1, 0, 1), + RSRC(PMIC_2, 0, 2), + RSRC(BOARD_R0, 0, 3), + RSRC(BOARD_R1, 0, 4), + RSRC(BOARD_R2, 0, 5), + RSRC(BOARD_R3, 0, 6), + RSRC(BOARD_R4, 0, 7), + RSRC(BOARD_R5, 0, 8), + RSRC(BOARD_R6, 0, 9), + RSRC(BOARD_R7, 0, 10) +}; + +/* Block of comments that get processed for documentation + DO NOT CHANGE - must match object code. */ +#ifdef DOX + RNFO() /* PMIC 0 */ + RNFO() /* PMIC 1 */ + RNFO() /* PMIC 2 */ + RNFO() /* Misc. board component 0 */ + RNFO() /* Misc. board component 1 */ + RNFO() /* Misc. board component 2 */ + RNFO() /* Misc. board component 3 */ + RNFO() /* Misc. board component 4 */ + RNFO() /* Misc. board component 5 */ + RNFO() /* Misc. board component 6 */ + RNFO() /* Misc. board component 7 */ + TNFO(PMIC_0, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_0, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_1, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_1, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ + TNFO(PMIC_2, TEMP, RO, x, 8) /* Temperature sensor temp */ + TNFO(PMIC_2, TEMP_HI, RW, x, 8) /* Temperature sensor high limit alarm temp */ +#endif + +/* External Variables */ + +const sc_rm_idx_t board_num_rsrc = BRD_NUM_RSRC_BRD; + +/*! + * External variable for specing DDR periodic training. + */ +const uint32_t board_ddr_period_ms = 0U; + +const uint32_t board_ddr_derate_period_ms = 0U; + +/* External Functions */ + +/*--------------------------------------------------------------------------*/ +/* Init */ +/*--------------------------------------------------------------------------*/ +void board_init(boot_phase_t phase) +{ + ss_print(3, "board_init(%d)\n", phase); + +#ifdef SIMU + if (phase == BOOT_PHASE_API_INIT) + { + main_simu_load_board(); + } +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Return the debug UART info */ +/*--------------------------------------------------------------------------*/ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud) +{ + *inst = LPUART_DEBUG_INST; + *baud = DEBUG_BAUD; + + return LPUART_DEBUG; +} + +/*--------------------------------------------------------------------------*/ +/* Configure debug UART */ +/*--------------------------------------------------------------------------*/ +void board_config_debug_uart(sc_bool_t early_phase) +{ + #if defined(DEBUG) && !defined(SIMU) + /* Power up UART */ + pm_force_resource_power_mode_v(SC_R_SC_UART, + SC_PM_PW_MODE_ON); + + /* Return if debug enabled */ + if (SCFW_DBG_READY) + { + return; + } + + /* Configure SCU UART */ + main_config_debug_uart(LPUART_DEBUG, SC_24MHZ); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Disable debug UART */ +/*--------------------------------------------------------------------------*/ +void board_disable_debug_uart(void) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Configure SCFW resource/pins */ +/*--------------------------------------------------------------------------*/ +void board_config_sc(sc_rm_pt_t pt_sc) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Get board parameter */ +/*--------------------------------------------------------------------------*/ +board_parm_rtn_t board_parameter(board_parm_t parm) +{ + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + return main_board_parameter(parm); +} + +/*--------------------------------------------------------------------------*/ +/* Get resource avaiability info */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc) +{ + /* Return SC_FALSE here if a resource isn't available due to board + connections (typically lack of power). Examples incluse DRC_0/1 + and ADC. */ + + /* The value here may be overridden by SoC fuses or emulation config */ + + /* Note return values are usually static. Can be made dynamic by storing + return in a global variable and setting using board_set_control() */ + + return SC_TRUE; +} + +/*--------------------------------------------------------------------------*/ +/* Override QoS configuration */ +/*--------------------------------------------------------------------------*/ +void board_qos_config(sc_sub_t ss) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Init DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initalized) +{ + board_print(3, "board_init_ddr(%d)\n", early); + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Take action on DDR */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action) +{ + /* Note this is called by the ROM before the SCFW is initialized. + * Do NOT make any unqualified calls to any other APIs. + */ + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the system (inc. additional resource partitions) */ +/*--------------------------------------------------------------------------*/ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot) +{ + /* This function configures the system. It usually partitions + resources according to the system design. It must be modified by + customers. Partitions should then be specified using the mkimage + -p option. */ + + board_print(3, "board_system_config(%d)\n", early); + + /* Name default partitions */ + PARTITION_NAME(SC_PT, "SCU"); + PARTITION_NAME(SECO_PT, "SECO"); + PARTITION_NAME(pt_boot, "BOOT"); +} + +/*--------------------------------------------------------------------------*/ +/* Early CPU query */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_early_cpu(sc_rsrc_t cpu) +{ + return SC_FALSE; +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level SoC power domain */ +/*--------------------------------------------------------------------------*/ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_set_power_mode(%s, %d, %d, %d)\n", snames[ss], + pd, from_mode, to_mode); +} + +/*--------------------------------------------------------------------------*/ +/* Set the voltage for the given SS. */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt) +{ + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Set board power supplies when enter/exit low-power mode */ +/*--------------------------------------------------------------------------*/ +void board_lpm(sc_pm_power_mode_t mode) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Transition external board-level supply for board component */ +/*--------------------------------------------------------------------------*/ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode) +{ + board_print(3, "board_trans_resource_power(%d, %s, %d, %d)\n", idx, + rnames[rsrc_idx], from_mode, to_mode); +} + +/*--------------------------------------------------------------------------*/ +/* Reset a board resource */ +/*--------------------------------------------------------------------------*/ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Set board power mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_power(sc_pm_power_mode_t mode) +{ + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Reset board */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt) +{ + #ifndef SIMU + #ifdef DEBUG + /* Dump out caller of reset request */ + always_print("Board reset (%u, caller = 0x%08X)\n", reason, + __builtin_return_address(0)); + + /* Invoke LPUART deinit to drain TX buffers if a warm reset follows */ + LPUART_Deinit(LPUART_DEBUG); + #endif + + /* Request a warm reset */ + soc_set_reset_info(reason, pt); + NVIC_SystemReset(); + #endif + + return SC_ERR_UNAVAILABLE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle CPU reset event */ +/*--------------------------------------------------------------------------*/ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt) +{ + /* Note: Production code should decide the response for each type + * of reset event. Options include allowing the SCFW to + * reset the CPU or forcing a full system reset. Additionally, + * the number of reset attempts can be tracked to determine the + * reset response. + */ + + /* Check for MCU reset event */ + if ((resource == SC_R_MCU_0_PID0) || (resource == SC_R_MCU_1_PID0)) + { + always_print("MCU reset event (rsrc = %d, event = %d)\n", resource, + reset_event); + + /* Treat lockups or parity/ECC reset events as board faults */ + if ((reset_event == BOARD_CPU_RESET_LOCKUP) || + (reset_event == BOARD_CPU_RESET_MEM_ERR)) + { + board_fault(SC_FALSE, BOARD_BFAULT_CPU, pt); + } + } + + /* Returning from this function will result in an attempt reset the + partition or board depending on the event and wdog action. */ +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask) +{ + /* Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + */ + *mask = 0UL; +} + +/*--------------------------------------------------------------------------*/ +/* Trap partition reboot continue */ +/*--------------------------------------------------------------------------*/ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr) +{ + /* Code can modify boot parameters on a reboot. Called after partition + * is powered off but before it is powered back on and started. + */ +} + +/*--------------------------------------------------------------------------*/ +/* Return partition reboot timeout action */ +/*--------------------------------------------------------------------------*/ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt) +{ + /* Return the action to take if a partition reboot requires continue + * ack for others and does not happen before timeout */ + return BOARD_REBOOT_TO_FORCE; +} + +/*--------------------------------------------------------------------------*/ +/* Handle panic temp alarm */ +/*--------------------------------------------------------------------------*/ +void board_panic(sc_dsc_t dsc) +{ + /* See Porting Guide for more info on panic alarms */ + #ifdef DEBUG + error_print("Panic temp (dsc=%d)\n", dsc); + #endif + + board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_TEMP, + SC_PT); +} + +/*--------------------------------------------------------------------------*/ +/* Handle fault or return from main() */ +/*--------------------------------------------------------------------------*/ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt) +{ + /* Note, delete the DEBUG case if fault behavior should be like + typical production build even if DEBUG defined */ + + #ifdef DEBUG + /* Disable the watchdog */ + board_wdog_disable(SC_FALSE); + + board_print(1, "board fault(%u, %u, %u)\n", restarted, reason, pt); + + /* Stop so developer can see WDOG occurred */ + #ifndef SIMU + HALT; + #endif + #else + /* Was this called to report a previous WDOG restart? */ + if (restarted == SC_FALSE) + { + /* Fault just occurred, need to reset */ + board_reset(SC_PM_RESET_TYPE_BOARD, + SC_PM_RESET_REASON_SCFW_FAULT, pt); + + /* Wait for reset */ + HALT; + } + /* Issue was before restart so just return */ + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Handle SECO/SNVS security violation */ +/*--------------------------------------------------------------------------*/ +void board_security_violation(void) +{ + always_print("SNVS security violation\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Get the status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +sc_bool_t board_get_button_status(void) +{ + return SC_FALSE; +} + +/*--------------------------------------------------------------------------*/ +/* Set control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NOTFOUND; + + board_print(3, + "board_set_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + +#ifdef SIMU + if (resource == SC_R_PMIC_0) + { + err = SC_ERR_NONE; + } +#endif + + return err;; +} + +/*--------------------------------------------------------------------------*/ +/* Get control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NOTFOUND; + + board_print(3, + "board_get_control(%s, %u)\n", rnames[rsrc_idx], ctrl); + + #ifdef SIMU + if (resource == SC_R_PMIC_0) + { + err = SC_ERR_NONE; + } + #endif + + return err;; +} + +/*--------------------------------------------------------------------------*/ +/* Board tick */ +/*--------------------------------------------------------------------------*/ +void board_tick(uint16_t msec) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Board IOCTL function */ +/*--------------------------------------------------------------------------*/ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + + /* For test_misc */ + if (*parm1 == 0xFFFFFFFEU) + { + *parm1 = *parm2 + *parm3; + *parm2 = mu; + *parm3 = caller_pt; + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/** @} */ + diff --git a/platform/board/none/board.h b/platform/board/none/board.h new file mode 100755 index 0000000..0473288 --- /dev/null +++ b/platform/board/none/board.h @@ -0,0 +1,53 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure board specific features of the SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_H +#define SC_BOARD_H + +/* Includes */ + +/* Defines */ + +#endif /* SC_BOARD_H */ + diff --git a/platform/board/pmic.c b/platform/board/pmic.c new file mode 100755 index 0000000..a53e561 --- /dev/null +++ b/platform/board/pmic.c @@ -0,0 +1,423 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Implementation of the system controller PMIC interface layer including + * dynamic PMIC handling + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/main.h" +#include "test/common/test.h" +#include "board/pmic.h" + +/* Declare a Global PMIC identifier for dynamic functions */ +uint8_t PMIC_TYPE = PMIC_NONE; + +/* Initialize PMIC_TYPE if not done from board file */ +static sc_err_t get_pmic_type(pmic_id_t id); + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Regulator Voltage */ +/*--------------------------------------------------------------------------*/ +sc_err_t dynamic_pmic_set_voltage(pmic_id_t id, uint32_t pmic_reg, + uint32_t vol_mv, uint32_t mode_to_set) +{ + sc_err_t rtn = SC_ERR_NONE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = SC_ERR_FAIL; + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == SC_ERR_NONE) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_pmic_set_voltage(id, pmic_reg, vol_mv, + mode_to_set); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_pmic_set_voltage(id, pmic_reg, vol_mv, + mode_to_set); + break; + default : + rtn = SC_ERR_NOTFOUND; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC Regulator Voltage */ +/*--------------------------------------------------------------------------*/ +sc_err_t dynamic_pmic_get_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t *vol_mv, + uint32_t mode_to_get) +{ + sc_err_t rtn = SC_ERR_NONE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = SC_ERR_FAIL; + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == SC_ERR_NONE) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_pmic_get_voltage(id, pmic_reg, vol_mv, mode_to_get); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_pmic_get_voltage(id, pmic_reg, vol_mv, mode_to_get); + break; + default : + rtn = SC_ERR_NOTFOUND; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Regulator Mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t dynamic_pmic_set_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t mode) +{ + sc_err_t rtn = SC_ERR_NONE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = SC_ERR_FAIL; + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == SC_ERR_NONE) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_pmic_set_mode(id, pmic_reg, mode); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_pmic_set_mode(id, pmic_reg, mode); + break; + default : + rtn = SC_ERR_NOTFOUND; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC Regulator Mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t dynamic_pmic_get_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t *mode) +{ + sc_err_t rtn = SC_ERR_NONE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = SC_ERR_FAIL; + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == SC_ERR_NONE) + { + switch (PMIC_TYPE) + { + case PF100 : /* get mode not supported for pf100 */ + rtn = SC_ERR_NOTFOUND; + break; + case PF8100 : + case PF8200 : + rtn = pf8100_pmic_get_mode(id, pmic_reg, mode); + break; + default : + rtn = SC_ERR_NOTFOUND; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Service PMIC IRQ */ +/*--------------------------------------------------------------------------*/ +sc_bool_t dynamic_pmic_irq_service(pmic_id_t id) +{ + sc_bool_t rtn = SC_TRUE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = SC_FALSE; + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == SC_TRUE) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_pmic_irq_service(id); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_pmic_irq_service(id); + break; + default : + rtn = SC_FALSE; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Access PMIC register */ +/*--------------------------------------------------------------------------*/ +sc_err_t dynamic_pmic_register_access(pmic_id_t id, uint32_t address, + sc_bool_t read_write, uint8_t* value) +{ + sc_err_t rtn = SC_ERR_NONE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = SC_ERR_FAIL; + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == SC_ERR_NONE) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_pmic_register_access(id, address, read_write, value); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_pmic_register_access(id, address, read_write, value); + break; + default : + rtn = SC_ERR_NOTFOUND; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC version */ +/*--------------------------------------------------------------------------*/ +pmic_version_t dynamic_get_pmic_version(pmic_id_t id) +{ + pmic_version_t rtn = {0, 0}; /* initialize to empty as err return */ + sc_bool_t set = SC_TRUE; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + set = SC_FALSE; + } + } + + /* skip switch statement if PMIC type not detected */ + if (set != SC_FALSE) + { + /* Call specific function based on established PMIC_TYPE */ + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_get_pmic_version(id); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_get_pmic_version(id); + break; + default : + /* default case leaves rtn as empty version */ + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC temperature */ +/*--------------------------------------------------------------------------*/ +uint32_t dynamic_get_pmic_temp(pmic_id_t id) +{ + uint32_t rtn = 0U; + uint32_t default_temp = 25U; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = default_temp; /* default to room temp */ + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == 0U) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_get_pmic_temp(id); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_get_pmic_temp(id); + break; + default : + rtn = default_temp; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Temperature Alarm */ +/*--------------------------------------------------------------------------*/ +uint32_t dynamic_set_pmic_temp_alarm(pmic_id_t id, uint32_t temp) +{ + uint32_t rtn = 0U; + + if (PMIC_TYPE == PMIC_NONE) + { + /* Initialize PMIC_TYPE if not already */ + if(get_pmic_type(id) != SC_ERR_NONE) + { + rtn = temp; /* return temp called with */ + } + } + + /* Call specific function based on established PMIC_TYPE */ + if (rtn == 0U) + { + switch (PMIC_TYPE) + { + case PF100 : + rtn = pf100_set_pmic_temp_alarm(id, temp); + break; + case PF8100 : + case PF8200 : + rtn = pf8100_set_pmic_temp_alarm(id, temp); + break; + default : + rtn = temp; + break; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Determine PMIC type at address */ +/*--------------------------------------------------------------------------*/ +static sc_err_t get_pmic_type(pmic_id_t id) +{ + uint8_t dev_id = pmic_get_device_id(id); + sc_err_t rtn = SC_ERR_NONE; + + switch (dev_id) + { + case PF100_DEV_ID : + PMIC_TYPE = PF100; + break; + case PF8100_DEV_ID : + PMIC_TYPE = PF8100; + break; + case PF8200_DEV_ID : + PMIC_TYPE = PF8200; + break; + default : + PMIC_TYPE = PMIC_NONE; + rtn = SC_ERR_NOTFOUND; + break; + } + + return rtn; +} diff --git a/platform/board/pmic.h b/platform/board/pmic.h new file mode 100755 index 0000000..af77562 --- /dev/null +++ b/platform/board/pmic.h @@ -0,0 +1,249 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * PMIC include for PMIC interface layer. This API is used to abstract the + * PMIC driver. It also supports dynamic PMIC identification and function + * binding (normally only used for dev boards). + * + * @addtogroup pmic_driver + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_PMIC_H +#define SC_PMIC_H + +/* Includes */ + +#include "main/main.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/pmic/pf100/fsl_pf100.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" + +/* Defines */ + +/*! + * @name Defines for supported PMIC devices + */ +/** @{ */ +#define PMIC_NONE 0U +#define PF100 1U +#define PF8100 2U +#define PF8200 3U +/** @} */ + +/*! + * @name Defines for PMIC configuration + */ +/** @{ */ +#define PF100_DEV_ID 0x10U +#define PF8100_DEV_ID 0x40U +#define PF8200_DEV_ID 0x48U +#define PF8X00_FAM_ID 0x40U +#define PF7X00_FAM_ID 0x80U +#define PF8100_A0_REV 0x10U +#define FAM_ID_MASK 0xF0U +/** @} */ + +/*! Global PMIC type identifier */ +extern uint8_t PMIC_TYPE; + +/* Table for dynamic PMIC functionality */ +#ifdef PMIC /* Replace function prefix with defined PMIC */ + #define FUNC_PRE(name, function) FUNC_PREPRE(name,function) + #define FUNC_PREPRE(name, function) name ## function + #define PMIC_SET_MODE FUNC_PRE(PMIC, _pmic_set_mode) + #define PMIC_GET_MODE FUNC_PRE(PMIC, _pmic_get_mode) + #define PMIC_SET_VOLTAGE FUNC_PRE(PMIC, _pmic_set_voltage) + #define PMIC_GET_VOLTAGE FUNC_PRE(PMIC, _pmic_get_voltage) + #define PMIC_IRQ_SERVICE FUNC_PRE(PMIC, _pmic_irq_service) + #define PMIC_REGISTER_ACCESS FUNC_PRE(PMIC, _pmic_register_access) + #define GET_PMIC_VERSION FUNC_PRE(PMIC, _get_pmic_version) + #define GET_PMIC_TEMP FUNC_PRE(PMIC, _get_pmic_temp) + #define SET_PMIC_TEMP_ALARM FUNC_PRE(PMIC, _set_pmic_temp_alarm) +#else /* Point MACROS at the dynamic function for run time decision */ + #define PMIC_SET_VOLTAGE dynamic_pmic_set_voltage + #define PMIC_GET_VOLTAGE dynamic_pmic_get_voltage + #define PMIC_SET_MODE dynamic_pmic_set_mode + #define PMIC_GET_MODE dynamic_pmic_get_mode + #define PMIC_IRQ_SERVICE dynamic_pmic_irq_service + #define PMIC_REGISTER_ACCESS dynamic_pmic_register_access + #define GET_PMIC_VERSION dynamic_get_pmic_version + #define GET_PMIC_TEMP dynamic_get_pmic_temp + #define SET_PMIC_TEMP_ALARM dynamic_set_pmic_temp_alarm +#endif + +/*! + * This function sets the voltage of a corresponding voltage regulator for the + * supported PMIC types + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator + * e.g [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[in] vol_mv New voltage setpoint for the regulator in millivolts + * @param[in] mode_to_set Which mode to change setpoint for. Refer to each + * PMIC for valid modes + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t dynamic_pmic_set_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t vol_mv, + uint32_t mode_to_set); + +/*! + * This function gets the voltage on a corresponding voltage regulator of the + * PMIC + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator + * e.g [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[out] vol_mv pointer to return voltage in millivolts + * @param[in] mode_to_get Mode for which to get the voltage. Refer to each + * PMIC for valid modes. + * + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + */ +sc_err_t dynamic_pmic_get_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t *vol_mv, + uint32_t mode_to_get); + +/*! + * This function sets the mode of the specified regulator. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + e.g [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[in] mode mode to set the regulator; Refer to each + * PMIC for valid modes. + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t dynamic_pmic_set_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t mode); + +/*! + * This function gets the mode of the specified regulator. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + e.g [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[in] mode pointer to return mode in raw hex form + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t dynamic_pmic_get_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t *mode); + +/*! + * This function services the interrupt for the temp alarm + * + * @param[in] id I2C address of PMIC device + * + * @return Returns SC_TRUE if there was a temperature interrupt to be cleared + */ +sc_bool_t dynamic_pmic_irq_service(pmic_id_t id); + +/*! + * This function allows access to individual registers of the PMIC + * + * @param[in] id I2C address of PMIC device + * @param[in] address register address to access + * @param[in] read_write bool indicating read(SC_FALSE/0) or write(SC_TRUE/1) + * @param[in,out] value value to read or to set + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + */ +sc_err_t dynamic_pmic_register_access(pmic_id_t id, uint32_t address, + sc_bool_t read_write, uint8_t* value); + +/*! + * This function returns the device ID and revision for the PMIC. + * + * @param[in] id I2C address of PMIC device + * + * @return Returns a structure with the device ID and revision. + */ +pmic_version_t dynamic_get_pmic_version(pmic_id_t id); + +/*! + * This function gets the current PMIC temperature as sensed by the + * PMIC temperature sensor. + * + * @param[in] id I2C address of PMIC device + * + * @return returns the temp sensed by the PMIC in a UINT32 in Celsius + * + * Note: Refer to Refer to each PMIC for temperature details + * + * Return errors: + * - SC_ERR_CONFIG if temperature monitor is not enabled + * + */ +uint32_t dynamic_get_pmic_temp(pmic_id_t id); + +/*! + * This function sets the temp alarm for the PMIC in Celsius + * + * @param[in] id I2C address of PMIC device + * @param[in] temp Temperature to set the alarm + * + * Note: Refer to Refer to each PMIC for temperature details + * + * @return Returns the temperature that the alarm is set to in Celsius + */ + uint32_t dynamic_set_pmic_temp_alarm(pmic_id_t id, uint32_t temp); + + /** @} */ + + #endif /* SC_PMIC_H */ + diff --git a/platform/config/config.h b/platform/config/config.h new file mode 100755 index 0000000..0be26d3 --- /dev/null +++ b/platform/config/config.h @@ -0,0 +1,118 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure the top-level SCFW. + * + */ +/*==========================================================================*/ + +#ifndef SC_CONFIG_H +#define SC_CONFIG_H + +/* Includes */ + +#include "main/debug.h" +#include "soc.h" +#include "board.h" +#include "pads.h" +#include "pad_data.h" + +/* Test Switches */ + +#if DEBUG_LEVEL > 1 + #define HAS_CHECK_CONFIG +#endif +#if 0 + #define HAS_TEST_PTIM + #define HAS_TEST_PCNT +#endif + +/* Hardware Switches */ + +#define HAS_XRDC_HW +#define HAS_PAD_HW + +/* Configure Debugging & Profiling */ + +#ifdef SIMU + #define TEST_PROF_THRESH_NS 2000U +#else + #define TEST_PROF_THRESH_NS 10000U +#endif + +/* Configure Addressing */ + +#define SC_SADDR_W 32U + +typedef uintptr_t sc_saddr_t; + +/* Configure System Controller */ + +#define SC_PT 0U +#define SC_DID 2U +#define SECO_PT 2U +#define SECO_DID 1U +#define BOOT_PT 1U +#define BOOT_DID 0U +#define SC_STATIC_PT 0U +#define SC_STATIC_DID 2U +#define SC_BYPASS_SID 0U +#define SC_SA SC_RM_SPA_ASSERT +#define SC_PA SC_RM_SPA_PASSTHRU +#define SC_MAX_SS_CLKS 32U + +/* Configure IPC */ + +#define SC_IPC_LOOPBACK SC_IPC_AP_CH0 + +/* Configure Resource Manager */ + +#define SC_RM_IDX_W 16U //!< Width of sc_rm_idx_t +typedef uint16_t sc_rm_idx_t; //!< Unified resource index + +#define SC_RMS_IDX_W 8U //!< Width of sc_rms_idx_t +typedef uint8_t sc_rms_idx_t; //!< Unified small resource index + +#define SC_RM_MATCH_W 16U //!< Width of sc_rm_match_t +typedef uint16_t sc_rm_match_t; //!< RDC match value + +#define SC_RM_SID_MASK 0x3FU //!< Mask for StreamID + +#endif /* SC_CONFIG_H */ + diff --git a/platform/config/mx8dxl/ALL/has_ss.h b/platform/config/mx8dxl/ALL/has_ss.h new file mode 100755 index 0000000..c30fe45 --- /dev/null +++ b/platform/config/mx8dxl/ALL/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 0 +#define HAS_SS_CCI 0 +#define HAS_SS_AP_0 0 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 1 +#define HAS_SS_GPU_0 0 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 0 +#define HAS_SS_DC_0 0 +#define HAS_SS_DC_1 0 +#define HAS_SS_IMG_0 0 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 1 +#define HAS_SS_DMA 0 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 0 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 0 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 1 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 0 +#define HAS_SS_LVDS_1 0 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 0 +#define HAS_SS_CSI_1 0 +#define HAS_SS_HDMI_RX 0 +#define HAS_SS_HDMI 0 +#define HAS_SS_MIPI_0 0 +#define HAS_SS_MIPI_1 0 +#define HAS_SS_V2X 1 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8dxl/CORES/has_ss.h b/platform/config/mx8dxl/CORES/has_ss.h new file mode 100755 index 0000000..c30fe45 --- /dev/null +++ b/platform/config/mx8dxl/CORES/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 0 +#define HAS_SS_CCI 0 +#define HAS_SS_AP_0 0 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 1 +#define HAS_SS_GPU_0 0 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 0 +#define HAS_SS_DC_0 0 +#define HAS_SS_DC_1 0 +#define HAS_SS_IMG_0 0 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 1 +#define HAS_SS_DMA 0 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 0 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 0 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 1 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 0 +#define HAS_SS_LVDS_1 0 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 0 +#define HAS_SS_CSI_1 0 +#define HAS_SS_HDMI_RX 0 +#define HAS_SS_HDMI 0 +#define HAS_SS_MIPI_0 0 +#define HAS_SS_MIPI_1 0 +#define HAS_SS_V2X 1 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8dxl/iomuxd.h b/platform/config/mx8dxl/iomuxd.h new file mode 100755 index 0000000..19f8511 --- /dev/null +++ b/platform/config/mx8dxl/iomuxd.h @@ -0,0 +1,197 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef IOMUXD_H +#define IOMUXD_H + + +#ifndef IOMUXD_REG_BASE + #ifdef SCU_RESOURCES + #define IOMUXD_REG_BASE 0x41F80000U + #else + #define IOMUXD_REG_BASE 0x33F80000U + #endif +#endif + + // NUM RING GROUP PAD | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | +#define IOMUXD__PCIE_CTRL0_PERST_B REG32(IOMUXD_REG_BASE+0x00000000U) // 0 0 0 0 | HSIO.PCIE0.PERST_B | | | | LSIO.GPIO4.IO00 | LSIO.GPIO7.IO00 | | | | +#define IOMUXD__PCIE_CTRL0_CLKREQ_B REG32(IOMUXD_REG_BASE+0x00000040U) // 0 0 0 1 | HSIO.PCIE0.CLKREQ_B | | | | LSIO.GPIO4.IO01 | LSIO.GPIO7.IO01 | | | | +#define IOMUXD__PCIE_CTRL0_WAKE_B REG32(IOMUXD_REG_BASE+0x00000080U) // 0 0 0 2 | HSIO.PCIE0.WAKE_B | | | | LSIO.GPIO4.IO02 | LSIO.GPIO7.IO02 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP REG32(IOMUXD_REG_BASE+0x000000C0U) // 0 0 0 3 | | | | | | | | | | +#define IOMUXD__USB_SS3_TC0 REG32(IOMUXD_REG_BASE+0x00020000U) // 1 1 0 0 | ADMA.I2C1.SCL | CONN.USB_OTG1.PWR | CONN.USB_OTG2.PWR | | LSIO.GPIO4.IO03 | LSIO.GPIO7.IO03 | | | | +#define IOMUXD__USB_SS3_TC1 REG32(IOMUXD_REG_BASE+0x00020040U) // 1 1 0 1 | ADMA.I2C1.SCL | CONN.USB_OTG2.PWR | | | LSIO.GPIO4.IO04 | LSIO.GPIO7.IO04 | | | | +#define IOMUXD__USB_SS3_TC2 REG32(IOMUXD_REG_BASE+0x00020080U) // 1 1 0 2 | ADMA.I2C1.SDA | CONN.USB_OTG1.OC | CONN.USB_OTG2.OC | | LSIO.GPIO4.IO05 | LSIO.GPIO7.IO05 | | | | +#define IOMUXD__USB_SS3_TC3 REG32(IOMUXD_REG_BASE+0x000200C0U) // 1 1 0 3 | ADMA.I2C1.SDA | CONN.USB_OTG2.OC | | | LSIO.GPIO4.IO06 | LSIO.GPIO7.IO06 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_3V3_USB3IO REG32(IOMUXD_REG_BASE+0x00020100U) // 1 1 0 4 | | | | | | | | | | +#define IOMUXD__EMMC0_CLK REG32(IOMUXD_REG_BASE+0x00020140U) // 1 1 0 5 | CONN.EMMC0.CLK | CONN.NAND.READY_B | | | LSIO.GPIO4.IO07 | | | | | +#define IOMUXD__EMMC0_CMD REG32(IOMUXD_REG_BASE+0x00020180U) // 1 1 0 6 | CONN.EMMC0.CMD | CONN.NAND.DQS | | | LSIO.GPIO4.IO08 | | | | | +#define IOMUXD__EMMC0_DATA0 REG32(IOMUXD_REG_BASE+0x000201C0U) // 1 1 0 7 | CONN.EMMC0.DATA0 | CONN.NAND.DATA00 | | | LSIO.GPIO4.IO09 | | | | | +#define IOMUXD__EMMC0_DATA1 REG32(IOMUXD_REG_BASE+0x00020200U) // 1 1 0 8 | CONN.EMMC0.DATA1 | CONN.NAND.DATA01 | | | LSIO.GPIO4.IO10 | | | | | +#define IOMUXD__EMMC0_DATA2 REG32(IOMUXD_REG_BASE+0x00020240U) // 1 1 0 9 | CONN.EMMC0.DATA2 | CONN.NAND.DATA02 | | | LSIO.GPIO4.IO11 | | | | | +#define IOMUXD__EMMC0_DATA3 REG32(IOMUXD_REG_BASE+0x00020280U) // 1 1 0 10 | CONN.EMMC0.DATA3 | CONN.NAND.DATA03 | | | LSIO.GPIO4.IO12 | | | | | +#define IOMUXD__EMMC0_DATA4 REG32(IOMUXD_REG_BASE+0x000202C0U) // 1 1 0 11 | CONN.EMMC0.DATA4 | CONN.NAND.DATA04 | | | LSIO.GPIO4.IO13 | | | | | +#define IOMUXD__EMMC0_DATA5 REG32(IOMUXD_REG_BASE+0x00020300U) // 1 1 0 12 | CONN.EMMC0.DATA5 | CONN.NAND.DATA05 | | | LSIO.GPIO4.IO14 | | | | | +#define IOMUXD__EMMC0_DATA6 REG32(IOMUXD_REG_BASE+0x00020340U) // 1 1 0 13 | CONN.EMMC0.DATA6 | CONN.NAND.DATA06 | | | LSIO.GPIO4.IO15 | | | | | +#define IOMUXD__EMMC0_DATA7 REG32(IOMUXD_REG_BASE+0x00020380U) // 1 1 0 14 | CONN.EMMC0.DATA7 | CONN.NAND.DATA07 | | | LSIO.GPIO4.IO16 | | | | | +#define IOMUXD__EMMC0_STROBE REG32(IOMUXD_REG_BASE+0x000203C0U) // 1 1 0 15 | CONN.EMMC0.STROBE | CONN.NAND.CLE | | | LSIO.GPIO4.IO17 | | | | | +#define IOMUXD__EMMC0_RESET_B REG32(IOMUXD_REG_BASE+0x00021000U) // 2 1 1 0 | CONN.EMMC0.RESET_B | CONN.NAND.WP_B | | | LSIO.GPIO4.IO18 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 REG32(IOMUXD_REG_BASE+0x00021040U) // 2 1 1 1 | | | | | | | | | | +#define IOMUXD__USDHC1_RESET_B REG32(IOMUXD_REG_BASE+0x00021080U) // 2 1 1 2 | CONN.USDHC1.RESET_B | CONN.NAND.RE_N | ADMA.SPI2.SCK | CONN.NAND.WE_B | LSIO.GPIO4.IO19 | LSIO.GPIO7.IO08 | | | | +#define IOMUXD__USDHC1_VSELECT REG32(IOMUXD_REG_BASE+0x000210C0U) // 2 1 1 3 | CONN.USDHC1.VSELECT | CONN.NAND.RE_P | ADMA.SPI2.SDO | CONN.NAND.RE_B | LSIO.GPIO4.IO20 | LSIO.GPIO7.IO09 | | | | +#define IOMUXD__IOMUXD_CTL_NAND_RE_P_N REG32(IOMUXD_REG_BASE+0x00021100U) // 2 1 1 4 | | | | | | | | | | +#define IOMUXD__USDHC1_WP REG32(IOMUXD_REG_BASE+0x00021140U) // 2 1 1 5 | CONN.USDHC1.WP | CONN.NAND.DQS_N | ADMA.SPI2.SDI | CONN.NAND.ALE | LSIO.GPIO4.IO21 | LSIO.GPIO7.IO10 | | | | +#define IOMUXD__USDHC1_CD_B REG32(IOMUXD_REG_BASE+0x00021180U) // 2 1 1 6 | CONN.USDHC1.CD_B | CONN.NAND.DQS_P | ADMA.SPI2.CS0 | CONN.NAND.DQS | LSIO.GPIO4.IO22 | LSIO.GPIO7.IO11 | | | | +#define IOMUXD__IOMUXD_CTL_NAND_DQS_P_N REG32(IOMUXD_REG_BASE+0x000211C0U) // 2 1 1 7 | | | | | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP REG32(IOMUXD_REG_BASE+0x00021200U) // 2 1 1 8 | | | | | | | | | | +#define IOMUXD__ENET0_RGMII_TXC REG32(IOMUXD_REG_BASE+0x00021240U) // 2 1 1 9 | CONN.ENET0.RGMII_TXC | CONN.ENET0.RCLK50M_OUT | CONN.ENET0.RCLK50M_IN | CONN.NAND.CE1_B | LSIO.GPIO4.IO29 | CONN.USDHC2.CLK | | | | +#define IOMUXD__ENET0_RGMII_TX_CTL REG32(IOMUXD_REG_BASE+0x00021280U) // 2 1 1 10 | CONN.ENET0.RGMII_TX_CTL | | | CONN.USDHC1.RESET_B | LSIO.GPIO4.IO30 | CONN.USDHC2.CMD | | | | +#define IOMUXD__ENET0_RGMII_TXD0 REG32(IOMUXD_REG_BASE+0x000212C0U) // 2 1 1 11 | CONN.ENET0.RGMII_TXD0 | | | CONN.USDHC1.VSELECT | LSIO.GPIO4.IO31 | CONN.USDHC2.DATA0 | | | | +#define IOMUXD__ENET0_RGMII_TXD1 REG32(IOMUXD_REG_BASE+0x00021300U) // 2 1 1 12 | CONN.ENET0.RGMII_TXD1 | | | CONN.USDHC1.WP | LSIO.GPIO5.IO00 | CONN.USDHC2.DATA1 | | | | +#define IOMUXD__ENET0_RGMII_TXD2 REG32(IOMUXD_REG_BASE+0x00021340U) // 2 1 1 13 | CONN.ENET0.RGMII_TXD2 | | CONN.NAND.CE0_B | CONN.USDHC1.CD_B | LSIO.GPIO5.IO01 | CONN.USDHC2.DATA2 | | | | +#define IOMUXD__ENET0_RGMII_TXD3 REG32(IOMUXD_REG_BASE+0x00021380U) // 2 1 1 14 | CONN.ENET0.RGMII_TXD3 | | CONN.NAND.RE_B | | LSIO.GPIO5.IO02 | CONN.USDHC2.DATA3 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 REG32(IOMUXD_REG_BASE+0x000213C0U) // 2 1 1 15 | | | | | | | | | | +#define IOMUXD__ENET0_RGMII_RXC REG32(IOMUXD_REG_BASE+0x00022000U) // 3 1 2 0 | CONN.ENET0.RGMII_RXC | | CONN.NAND.WE_B | CONN.USDHC1.CLK | LSIO.GPIO5.IO03 | | | | | +#define IOMUXD__ENET0_RGMII_RX_CTL REG32(IOMUXD_REG_BASE+0x00022040U) // 3 1 2 1 | CONN.ENET0.RGMII_RX_CTL | | | CONN.USDHC1.CMD | LSIO.GPIO5.IO04 | | | | | +#define IOMUXD__ENET0_RGMII_RXD0 REG32(IOMUXD_REG_BASE+0x00022080U) // 3 1 2 2 | CONN.ENET0.RGMII_RXD0 | | | CONN.USDHC1.DATA0 | LSIO.GPIO5.IO05 | | | | | +#define IOMUXD__ENET0_RGMII_RXD1 REG32(IOMUXD_REG_BASE+0x000220C0U) // 3 1 2 3 | CONN.ENET0.RGMII_RXD1 | | | CONN.USDHC1.DATA1 | LSIO.GPIO5.IO06 | | | | | +#define IOMUXD__ENET0_RGMII_RXD2 REG32(IOMUXD_REG_BASE+0x00022100U) // 3 1 2 4 | CONN.ENET0.RGMII_RXD2 | CONN.ENET0.RMII_RX_ER | | CONN.USDHC1.DATA2 | LSIO.GPIO5.IO07 | | | | | +#define IOMUXD__ENET0_RGMII_RXD3 REG32(IOMUXD_REG_BASE+0x00022140U) // 3 1 2 5 | CONN.ENET0.RGMII_RXD3 | | CONN.NAND.ALE | CONN.USDHC1.DATA3 | LSIO.GPIO5.IO08 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 REG32(IOMUXD_REG_BASE+0x00022180U) // 3 1 2 6 | | | | | | | | | | +#define IOMUXD__ENET0_REFCLK_125M_25M REG32(IOMUXD_REG_BASE+0x000221C0U) // 3 1 2 7 | CONN.ENET0.REFCLK_125M_25M | CONN.ENET0.PPS | CONN.EQOS.PPS_IN | CONN.EQOS.PPS_OUT | LSIO.GPIO5.IO09 | | | | | +#define IOMUXD__ENET0_MDIO REG32(IOMUXD_REG_BASE+0x00022200U) // 3 1 2 8 | CONN.ENET0.MDIO | ADMA.I2C3.SDA | CONN.EQOS.MDIO | | LSIO.GPIO5.IO10 | LSIO.GPIO7.IO16 | | | | +#define IOMUXD__ENET0_MDC REG32(IOMUXD_REG_BASE+0x00022240U) // 3 1 2 9 | CONN.ENET0.MDC | ADMA.I2C3.SCL | CONN.EQOS.MDC | | LSIO.GPIO5.IO11 | LSIO.GPIO7.IO17 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT REG32(IOMUXD_REG_BASE+0x00022280U) // 3 1 2 10 | | | | | | | | | | +#define IOMUXD__ENET1_RGMII_TXC REG32(IOMUXD_REG_BASE+0x00023000U) // 4 1 3 0 | LSIO.GPIO0.IO00 | CONN.EQOS.RCLK50M_OUT | ADMA.LCDIF.D00 | CONN.EQOS.RGMII_TXC | CONN.EQOS.RCLK50M_IN | | | | | +#define IOMUXD__ENET1_RGMII_TXD2 REG32(IOMUXD_REG_BASE+0x00023040U) // 4 1 3 1 | | | ADMA.LCDIF.D01 | CONN.EQOS.RGMII_TXD2 | LSIO.GPIO0.IO01 | | | | | +#define IOMUXD__ENET1_RGMII_TX_CTL REG32(IOMUXD_REG_BASE+0x00023080U) // 4 1 3 2 | | | ADMA.LCDIF.D02 | CONN.EQOS.RGMII_TX_CTL | LSIO.GPIO0.IO02 | | | | | +#define IOMUXD__ENET1_RGMII_TXD3 REG32(IOMUXD_REG_BASE+0x000230C0U) // 4 1 3 3 | | | ADMA.LCDIF.D03 | CONN.EQOS.RGMII_TXD3 | LSIO.GPIO0.IO03 | | | | | +#define IOMUXD__ENET1_RGMII_RXC REG32(IOMUXD_REG_BASE+0x00023100U) // 4 1 3 4 | | | ADMA.LCDIF.D04 | CONN.EQOS.RGMII_RXC | LSIO.GPIO0.IO04 | | | | | +#define IOMUXD__ENET1_RGMII_RXD3 REG32(IOMUXD_REG_BASE+0x00023140U) // 4 1 3 5 | | | ADMA.LCDIF.D05 | CONN.EQOS.RGMII_RXD3 | LSIO.GPIO0.IO05 | | | | | +#define IOMUXD__ENET1_RGMII_RXD2 REG32(IOMUXD_REG_BASE+0x00023180U) // 4 1 3 6 | | | ADMA.LCDIF.D06 | CONN.EQOS.RGMII_RXD2 | LSIO.GPIO0.IO06 | LSIO.GPIO6.IO00 | | | | +#define IOMUXD__ENET1_RGMII_RXD1 REG32(IOMUXD_REG_BASE+0x000231C0U) // 4 1 3 7 | | | ADMA.LCDIF.D07 | CONN.EQOS.RGMII_RXD1 | LSIO.GPIO0.IO07 | LSIO.GPIO6.IO01 | | | | +#define IOMUXD__ENET1_RGMII_TXD0 REG32(IOMUXD_REG_BASE+0x00023200U) // 4 1 3 8 | | | ADMA.LCDIF.D08 | CONN.EQOS.RGMII_TXD0 | LSIO.GPIO0.IO08 | LSIO.GPIO6.IO02 | | | | +#define IOMUXD__ENET1_RGMII_TXD1 REG32(IOMUXD_REG_BASE+0x00023240U) // 4 1 3 9 | | | ADMA.LCDIF.D09 | CONN.EQOS.RGMII_TXD1 | LSIO.GPIO0.IO09 | LSIO.GPIO6.IO03 | | | | +#define IOMUXD__ENET1_RGMII_RXD0 REG32(IOMUXD_REG_BASE+0x00023280U) // 4 1 3 10 | ADMA.SPDIF0.RX | ADMA.MQS.R | ADMA.LCDIF.D10 | CONN.EQOS.RGMII_RXD0 | LSIO.GPIO0.IO10 | LSIO.GPIO6.IO04 | | | | +#define IOMUXD__ENET1_RGMII_RX_CTL REG32(IOMUXD_REG_BASE+0x000232C0U) // 4 1 3 11 | ADMA.SPDIF0.TX | ADMA.MQS.L | ADMA.LCDIF.D11 | CONN.EQOS.RGMII_RX_CTL | LSIO.GPIO0.IO11 | LSIO.GPIO6.IO05 | | | | +#define IOMUXD__ENET1_REFCLK_125M_25M REG32(IOMUXD_REG_BASE+0x00023300U) // 4 1 3 12 | ADMA.SPDIF0.EXT_CLK | | ADMA.LCDIF.D12 | CONN.EQOS.REFCLK_125M_25M | LSIO.GPIO0.IO12 | LSIO.GPIO6.IO06 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB REG32(IOMUXD_REG_BASE+0x00023340U) // 4 1 3 13 | | | | | | | | | | +#define IOMUXD__SPI3_SCK REG32(IOMUXD_REG_BASE+0x00040000U) // 5 2 0 0 | ADMA.SPI3.SCK | | ADMA.LCDIF.D13 | | LSIO.GPIO0.IO13 | ADMA.LCDIF.D00 | | | | +#define IOMUXD__SPI3_SDO REG32(IOMUXD_REG_BASE+0x00040040U) // 5 2 0 1 | ADMA.SPI3.SDO | | ADMA.LCDIF.D14 | | LSIO.GPIO0.IO14 | ADMA.LCDIF.D01 | | | | +#define IOMUXD__SPI3_SDI REG32(IOMUXD_REG_BASE+0x00040080U) // 5 2 0 2 | ADMA.SPI3.SDI | | ADMA.LCDIF.D15 | | LSIO.GPIO0.IO15 | ADMA.LCDIF.D02 | | | | +#define IOMUXD__SPI3_CS0 REG32(IOMUXD_REG_BASE+0x000400C0U) // 5 2 0 3 | ADMA.SPI3.CS0 | ADMA.ACM.MCLK_OUT1 | ADMA.LCDIF.HSYNC | | LSIO.GPIO0.IO16 | ADMA.LCDIF.CS | | | | +#define IOMUXD__SPI3_CS1 REG32(IOMUXD_REG_BASE+0x00040100U) // 5 2 0 4 | ADMA.SPI3.CS1 | ADMA.I2C3.SCL | ADMA.LCDIF.RESET | ADMA.SPI2.CS0 | ADMA.LCDIF.D16 | ADMA.LCDIF.RD_E | | | | +#define IOMUXD__MCLK_IN1 REG32(IOMUXD_REG_BASE+0x00040140U) // 5 2 0 5 | ADMA.ACM.MCLK_IN1 | ADMA.I2C3.SDA | ADMA.LCDIF.EN | ADMA.SPI2.SCK | ADMA.LCDIF.D17 | ADMA.LCDIF.D03 | | | | +#define IOMUXD__MCLK_IN0 REG32(IOMUXD_REG_BASE+0x00040180U) // 5 2 0 6 | ADMA.ACM.MCLK_IN0 | | ADMA.LCDIF.VSYNC | ADMA.SPI2.SDI | LSIO.GPIO0.IO19 | ADMA.LCDIF.RS | | | | +#define IOMUXD__MCLK_OUT0 REG32(IOMUXD_REG_BASE+0x000401C0U) // 5 2 0 7 | ADMA.ACM.MCLK_OUT0 | | ADMA.LCDIF.CLK | ADMA.SPI2.SDO | LSIO.GPIO0.IO20 | ADMA.LCDIF.WR_RWN | | | | +#define IOMUXD__UART1_TX REG32(IOMUXD_REG_BASE+0x00040200U) // 5 2 0 8 | ADMA.UART1.TX | LSIO.PWM0.OUT | LSIO.GPT0.CAPTURE | | LSIO.GPIO0.IO21 | ADMA.LCDIF.D04 | | | | +#define IOMUXD__UART1_RX REG32(IOMUXD_REG_BASE+0x00040240U) // 5 2 0 9 | ADMA.UART1.RX | LSIO.PWM1.OUT | LSIO.GPT0.COMPARE | LSIO.GPT1.CLK | LSIO.GPIO0.IO22 | ADMA.LCDIF.D05 | | | | +#define IOMUXD__UART1_RTS_B REG32(IOMUXD_REG_BASE+0x00040280U) // 5 2 0 10 | ADMA.UART1.RTS_B | LSIO.PWM2.OUT | ADMA.LCDIF.D16 | LSIO.GPT1.CAPTURE | LSIO.GPT0.CLK | ADMA.LCDIF.D06 | | | | +#define IOMUXD__UART1_CTS_B REG32(IOMUXD_REG_BASE+0x000402C0U) // 5 2 0 11 | ADMA.UART1.CTS_B | LSIO.PWM3.OUT | ADMA.LCDIF.D17 | LSIO.GPT1.COMPARE | LSIO.GPIO0.IO24 | ADMA.LCDIF.D07 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK REG32(IOMUXD_REG_BASE+0x00040300U) // 5 2 0 12 | | | | | | | | | | +#define IOMUXD__SPI0_SCK REG32(IOMUXD_REG_BASE+0x00040340U) // 5 2 0 13 | ADMA.SPI0.SCK | ADMA.SAI0.TXC | M40.I2C0.SCL | M40.GPIO0.IO00 | LSIO.GPIO1.IO04 | ADMA.LCDIF.D08 | | | | +#define IOMUXD__SPI0_SDI REG32(IOMUXD_REG_BASE+0x00040380U) // 5 2 0 14 | ADMA.SPI0.SDI | ADMA.SAI0.TXD | M40.TPM0.CH0 | M40.GPIO0.IO02 | LSIO.GPIO1.IO05 | ADMA.LCDIF.D09 | | | | +#define IOMUXD__SPI0_SDO REG32(IOMUXD_REG_BASE+0x000403C0U) // 5 2 0 15 | ADMA.SPI0.SDO | ADMA.SAI0.TXFS | M40.I2C0.SDA | M40.GPIO0.IO01 | LSIO.GPIO1.IO06 | ADMA.LCDIF.D10 | | | | +#define IOMUXD__SPI0_CS1 REG32(IOMUXD_REG_BASE+0x00041000U) // 6 2 1 0 | ADMA.SPI0.CS1 | ADMA.SAI0.RXC | ADMA.SAI1.TXD | ADMA.LCD_PWM0.OUT | LSIO.GPIO1.IO07 | ADMA.LCDIF.D11 | | | | +#define IOMUXD__SPI0_CS0 REG32(IOMUXD_REG_BASE+0x00041040U) // 6 2 1 1 | ADMA.SPI0.CS0 | ADMA.SAI0.RXD | M40.TPM0.CH1 | M40.GPIO0.IO03 | LSIO.GPIO1.IO08 | ADMA.LCDIF.D12 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT REG32(IOMUXD_REG_BASE+0x00041080U) // 6 2 1 2 | | | | | | | | | | +#define IOMUXD__ADC_IN1 REG32(IOMUXD_REG_BASE+0x000410C0U) // 6 2 1 3 | ADMA.ADC.IN1 | M40.I2C0.SDA | M40.GPIO0.IO01 | ADMA.I2C0.SDA | LSIO.GPIO1.IO09 | ADMA.LCDIF.D13 | | | | +#define IOMUXD__ADC_IN0 REG32(IOMUXD_REG_BASE+0x00041100U) // 6 2 1 4 | ADMA.ADC.IN0 | M40.I2C0.SCL | M40.GPIO0.IO00 | ADMA.I2C0.SCL | LSIO.GPIO1.IO10 | ADMA.LCDIF.D14 | | | | +#define IOMUXD__ADC_IN3 REG32(IOMUXD_REG_BASE+0x00041140U) // 6 2 1 5 | ADMA.ADC.IN3 | M40.UART0.TX | M40.GPIO0.IO03 | ADMA.ACM.MCLK_OUT0 | LSIO.GPIO1.IO11 | ADMA.LCDIF.D15 | | | | +#define IOMUXD__ADC_IN2 REG32(IOMUXD_REG_BASE+0x00041180U) // 6 2 1 6 | ADMA.ADC.IN2 | M40.UART0.RX | M40.GPIO0.IO02 | ADMA.ACM.MCLK_IN0 | LSIO.GPIO1.IO12 | ADMA.LCDIF.D16 | | | | +#define IOMUXD__ADC_IN5 REG32(IOMUXD_REG_BASE+0x000411C0U) // 6 2 1 7 | ADMA.ADC.IN5 | M40.TPM0.CH1 | M40.GPIO0.IO05 | ADMA.LCDIF.LCDBUSY | LSIO.GPIO1.IO13 | ADMA.LCDIF.D17 | | | | +#define IOMUXD__ADC_IN4 REG32(IOMUXD_REG_BASE+0x00041200U) // 6 2 1 8 | ADMA.ADC.IN4 | M40.TPM0.CH0 | M40.GPIO0.IO04 | ADMA.LCDIF.LCDRESET | LSIO.GPIO1.IO14 | | | | | +#define IOMUXD__FLEXCAN0_RX REG32(IOMUXD_REG_BASE+0x00041240U) // 6 2 1 9 | ADMA.FLEXCAN0.RX | ADMA.SAI2.RXC | ADMA.UART0.RTS_B | ADMA.SAI1.TXC | LSIO.GPIO1.IO15 | LSIO.GPIO6.IO08 | | | | +#define IOMUXD__FLEXCAN0_TX REG32(IOMUXD_REG_BASE+0x00041280U) // 6 2 1 10 | ADMA.FLEXCAN0.TX | ADMA.SAI2.RXD | ADMA.UART0.CTS_B | ADMA.SAI1.TXFS | LSIO.GPIO1.IO16 | LSIO.GPIO6.IO09 | | | | +#define IOMUXD__FLEXCAN1_RX REG32(IOMUXD_REG_BASE+0x000412C0U) // 6 2 1 11 | ADMA.FLEXCAN1.RX | ADMA.SAI2.RXFS | ADMA.FTM.CH2 | ADMA.SAI1.TXD | LSIO.GPIO1.IO17 | LSIO.GPIO6.IO10 | | | | +#define IOMUXD__FLEXCAN1_TX REG32(IOMUXD_REG_BASE+0x00041300U) // 6 2 1 12 | ADMA.FLEXCAN1.TX | ADMA.SAI3.RXC | ADMA.DMA0.REQ_IN0 | ADMA.SAI1.RXD | LSIO.GPIO1.IO18 | LSIO.GPIO6.IO11 | | | | +#define IOMUXD__FLEXCAN2_RX REG32(IOMUXD_REG_BASE+0x00041340U) // 6 2 1 13 | ADMA.FLEXCAN2.RX | ADMA.SAI3.RXD | ADMA.UART3.RX | ADMA.SAI1.RXFS | LSIO.GPIO1.IO19 | LSIO.GPIO6.IO12 | | | | +#define IOMUXD__FLEXCAN2_TX REG32(IOMUXD_REG_BASE+0x00041380U) // 6 2 1 14 | ADMA.FLEXCAN2.TX | ADMA.SAI3.RXFS | ADMA.UART3.TX | ADMA.SAI1.RXC | LSIO.GPIO1.IO20 | LSIO.GPIO6.IO13 | | | | +#define IOMUXD__UART0_RX REG32(IOMUXD_REG_BASE+0x000413C0U) // 6 2 1 15 | ADMA.UART0.RX | ADMA.MQS.R | ADMA.FLEXCAN0.RX | SCU.UART0.RX | LSIO.GPIO1.IO21 | LSIO.GPIO6.IO14 | | | | +#define IOMUXD__UART0_TX REG32(IOMUXD_REG_BASE+0x00042000U) // 7 2 2 0 | ADMA.UART0.TX | ADMA.MQS.L | ADMA.FLEXCAN0.TX | SCU.UART0.TX | LSIO.GPIO1.IO22 | LSIO.GPIO6.IO15 | | | | +#define IOMUXD__UART2_TX REG32(IOMUXD_REG_BASE+0x00042040U) // 7 2 2 1 | ADMA.UART2.TX | ADMA.FTM.CH1 | ADMA.FLEXCAN1.TX | | LSIO.GPIO1.IO23 | LSIO.GPIO6.IO16 | | | | +#define IOMUXD__UART2_RX REG32(IOMUXD_REG_BASE+0x00042080U) // 7 2 2 2 | ADMA.UART2.RX | ADMA.FTM.CH0 | ADMA.FLEXCAN1.RX | | LSIO.GPIO1.IO24 | LSIO.GPIO6.IO17 | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH REG32(IOMUXD_REG_BASE+0x000420C0U) // 7 2 2 3 | | | | | | | | | | +#define IOMUXD__JTAG_TRST_B REG32(IOMUXD_REG_BASE+0x00042100U) // 7 2 2 4 | SCU.JTAG.TRST_B | SCU.WDOG0.WDOG_OUT | | | | | | | | +#define IOMUXD__PMIC_I2C_SCL REG32(IOMUXD_REG_BASE+0x00042140U) // 7 2 2 5 | SCU.PMIC_I2C.SCL | SCU.GPIO0.IOXX_PMIC_A35_ON | | | LSIO.GPIO2.IO01 | | | | | +#define IOMUXD__PMIC_I2C_SDA REG32(IOMUXD_REG_BASE+0x00042180U) // 7 2 2 6 | SCU.PMIC_I2C.SDA | SCU.GPIO0.IOXX_PMIC_GPU_ON | | | LSIO.GPIO2.IO02 | | | | | +#define IOMUXD__PMIC_INT_B REG32(IOMUXD_REG_BASE+0x000421C0U) // 7 2 2 7 | SCU.DSC.PMIC_INT_B | | | | | | | | | +#define IOMUXD__SCU_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00042200U) // 7 2 2 8 | SCU.GPIO0.IO00 | SCU.UART0.RX | M40.UART0.RX | ADMA.UART3.RX | LSIO.GPIO2.IO03 | | | | | +#define IOMUXD__SCU_GPIO0_01 REG32(IOMUXD_REG_BASE+0x00042240U) // 7 2 2 9 | SCU.GPIO0.IO01 | SCU.UART0.TX | M40.UART0.TX | ADMA.UART3.TX | SCU.WDOG0.WDOG_OUT | | | | | +#define IOMUXD__SCU_PMIC_STANDBY REG32(IOMUXD_REG_BASE+0x00042280U) // 7 2 2 10 | SCU.DSC.PMIC_STANDBY | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE1 REG32(IOMUXD_REG_BASE+0x000422C0U) // 7 2 2 11 | SCU.DSC.BOOT_MODE1 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE0 REG32(IOMUXD_REG_BASE+0x00042300U) // 7 2 2 12 | SCU.DSC.BOOT_MODE0 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE2 REG32(IOMUXD_REG_BASE+0x00042340U) // 7 2 2 13 | SCU.DSC.BOOT_MODE2 | SCU.DSC.RTC_CLOCK_OUTPUT_32K | | | | | | | | +#define IOMUXD__SNVS_TAMPER_OUT1 REG32(IOMUXD_REG_BASE+0x00060000U) // 8 3 0 0 | | | | | LSIO.GPIO2.IO05_IN | LSIO.GPIO6.IO19_IN | | | | +#define IOMUXD__SNVS_TAMPER_OUT2 REG32(IOMUXD_REG_BASE+0x00060040U) // 8 3 0 1 | | | | | LSIO.GPIO2.IO06_IN | LSIO.GPIO6.IO20_IN | | | | +#define IOMUXD__SNVS_TAMPER_OUT3 REG32(IOMUXD_REG_BASE+0x00060080U) // 8 3 0 2 | | | ADMA.SAI2.RXC | | LSIO.GPIO2.IO07_IN | LSIO.GPIO6.IO21_IN | | | | +#define IOMUXD__SNVS_TAMPER_OUT4 REG32(IOMUXD_REG_BASE+0x000600C0U) // 8 3 0 3 | | | ADMA.SAI2.RXD | | LSIO.GPIO2.IO08_IN | LSIO.GPIO6.IO22_IN | | | | +#define IOMUXD__SNVS_TAMPER_IN0 REG32(IOMUXD_REG_BASE+0x00060100U) // 8 3 0 4 | | | ADMA.SAI2.RXFS | | LSIO.GPIO2.IO09_IN | LSIO.GPIO6.IO23_IN | | | | +#define IOMUXD__SNVS_TAMPER_IN1 REG32(IOMUXD_REG_BASE+0x00060140U) // 8 3 0 5 | | | ADMA.SAI3.RXC | | LSIO.GPIO2.IO10_IN | LSIO.GPIO6.IO24_IN | | | | +#define IOMUXD__SNVS_TAMPER_IN2 REG32(IOMUXD_REG_BASE+0x00060180U) // 8 3 0 6 | | | ADMA.SAI3.RXD | | LSIO.GPIO2.IO11_IN | LSIO.GPIO6.IO25_IN | | | | +#define IOMUXD__SNVS_TAMPER_IN3 REG32(IOMUXD_REG_BASE+0x000601C0U) // 8 3 0 7 | | | ADMA.SAI3.RXFS | | LSIO.GPIO2.IO12_IN | LSIO.GPIO6.IO26_IN | | | | +#define IOMUXD__SPI1_SCK REG32(IOMUXD_REG_BASE+0x00060200U) // 8 3 0 8 | | | ADMA.I2C2.SDA | ADMA.SPI1.SCK | LSIO.GPIO3.IO00 | | | | | +#define IOMUXD__SPI1_SDO REG32(IOMUXD_REG_BASE+0x00060240U) // 8 3 0 9 | | | ADMA.I2C2.SCL | ADMA.SPI1.SDO | LSIO.GPIO3.IO01 | | | | | +#define IOMUXD__SPI1_SDI REG32(IOMUXD_REG_BASE+0x00060280U) // 8 3 0 10 | | | ADMA.I2C3.SCL | ADMA.SPI1.SDI | LSIO.GPIO3.IO02 | | | | | +#define IOMUXD__SPI1_CS0 REG32(IOMUXD_REG_BASE+0x000602C0U) // 8 3 0 11 | | | ADMA.I2C3.SDA | ADMA.SPI1.CS0 | LSIO.GPIO3.IO03 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD REG32(IOMUXD_REG_BASE+0x00060300U) // 8 3 0 12 | | | | | | | | | | +#define IOMUXD__QSPI0A_DATA1 REG32(IOMUXD_REG_BASE+0x00061000U) // 9 3 1 0 | LSIO.QSPI0A.DATA1 | | | | LSIO.GPIO3.IO10 | | | | | +#define IOMUXD__QSPI0A_DATA0 REG32(IOMUXD_REG_BASE+0x00061040U) // 9 3 1 1 | LSIO.QSPI0A.DATA0 | | | | LSIO.GPIO3.IO09 | | | | | +#define IOMUXD__QSPI0A_DATA3 REG32(IOMUXD_REG_BASE+0x00061080U) // 9 3 1 2 | LSIO.QSPI0A.DATA3 | | | | LSIO.GPIO3.IO12 | | | | | +#define IOMUXD__QSPI0A_DATA2 REG32(IOMUXD_REG_BASE+0x000610C0U) // 9 3 1 3 | LSIO.QSPI0A.DATA2 | | | | LSIO.GPIO3.IO11 | | | | | +#define IOMUXD__QSPI0A_SS0_B REG32(IOMUXD_REG_BASE+0x00061100U) // 9 3 1 4 | LSIO.QSPI0A.SS0_B | | | | LSIO.GPIO3.IO14 | | | | | +#define IOMUXD__QSPI0A_DQS REG32(IOMUXD_REG_BASE+0x00061140U) // 9 3 1 5 | LSIO.QSPI0A.DQS | | | | LSIO.GPIO3.IO13 | | | | | +#define IOMUXD__QSPI0A_SCLK REG32(IOMUXD_REG_BASE+0x00061180U) // 9 3 1 6 | LSIO.QSPI0A.SCLK | | | | LSIO.GPIO3.IO16 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A REG32(IOMUXD_REG_BASE+0x000611C0U) // 9 3 1 7 | | | | | | | | | | +#define IOMUXD__QSPI0B_SCLK REG32(IOMUXD_REG_BASE+0x00061200U) // 9 3 1 8 | LSIO.QSPI0B.SCLK | | | | LSIO.GPIO3.IO17 | | | | | +#define IOMUXD__QSPI0B_DQS REG32(IOMUXD_REG_BASE+0x00061240U) // 9 3 1 9 | LSIO.QSPI0B.DQS | | | | LSIO.GPIO3.IO22 | | | | | +#define IOMUXD__QSPI0B_DATA1 REG32(IOMUXD_REG_BASE+0x00061280U) // 9 3 1 10 | LSIO.QSPI0B.DATA1 | | | | LSIO.GPIO3.IO19 | | | | | +#define IOMUXD__QSPI0B_DATA0 REG32(IOMUXD_REG_BASE+0x000612C0U) // 9 3 1 11 | LSIO.QSPI0B.DATA0 | | | | LSIO.GPIO3.IO18 | | | | | +#define IOMUXD__QSPI0B_DATA3 REG32(IOMUXD_REG_BASE+0x00061300U) // 9 3 1 12 | LSIO.QSPI0B.DATA3 | | | | LSIO.GPIO3.IO21 | | | | | +#define IOMUXD__QSPI0B_DATA2 REG32(IOMUXD_REG_BASE+0x00061340U) // 9 3 1 13 | LSIO.QSPI0B.DATA2 | | | | LSIO.GPIO3.IO20 | | | | | +#define IOMUXD__QSPI0B_SS0_B REG32(IOMUXD_REG_BASE+0x00061380U) // 9 3 1 14 | LSIO.QSPI0B.SS0_B | | | | LSIO.GPIO3.IO23 | LSIO.QSPI0A.SS1_B | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B REG32(IOMUXD_REG_BASE+0x000613C0U) // 9 3 1 15 | | | | | | | | | | + +// GROUP REGISTERS FOR WAKEUP CONTROL +#define IOMUXD__GROUP_0_0 REG32(IOMUXD_REG_BASE+0x00000400U) // 0 0 0 0 | +#define IOMUXD__GROUP_1_0 REG32(IOMUXD_REG_BASE+0x00020400U) // 1 1 0 0 | +#define IOMUXD__GROUP_1_1 REG32(IOMUXD_REG_BASE+0x00021400U) // 2 1 1 0 | +#define IOMUXD__GROUP_1_2 REG32(IOMUXD_REG_BASE+0x00022400U) // 3 1 2 0 | +#define IOMUXD__GROUP_1_3 REG32(IOMUXD_REG_BASE+0x00023400U) // 4 1 3 0 | +#define IOMUXD__GROUP_2_0 REG32(IOMUXD_REG_BASE+0x00040400U) // 5 2 0 0 | +#define IOMUXD__GROUP_2_1 REG32(IOMUXD_REG_BASE+0x00041400U) // 6 2 1 0 | +#define IOMUXD__GROUP_2_2 REG32(IOMUXD_REG_BASE+0x00042400U) // 7 2 2 0 | +#define IOMUXD__GROUP_3_0 REG32(IOMUXD_REG_BASE+0x00060400U) // 8 3 0 0 | +#define IOMUXD__GROUP_3_1 REG32(IOMUXD_REG_BASE+0x00061400U) // 9 3 1 0 | + +#endif diff --git a/platform/config/mx8dxl/lpcg.h b/platform/config/mx8dxl/lpcg.h new file mode 100755 index 0000000..d0e0a18 --- /dev/null +++ b/platform/config/mx8dxl/lpcg.h @@ -0,0 +1,148 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef LPCG_H +#define LPCG_H + +// NOTE: Content below comes from cprog file of the SCU design database + +// LPCG______REG +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__REG 0x0000 // IPS_SLOT=CLK_SECO +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__BIT 0 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__STOP 3 + +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__REG 0x0004 // IPS_SLOT=CLK_SECO +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__BIT 0 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__HWEN 0 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__SWEN 1 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__RSVD 2 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__STOP 3 + +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__REG 0x0000 // IPS_SLOT=CLK_MMCAU_HCLK +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__BIT 0 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__STOP 3 + +#define LPCG__SS_SCU__CM4__TCMC_HCLK__REG 0x0000 // IPS_SLOT=CLK_TCMC_HCLK +#define LPCG__SS_SCU__CM4__TCMC_HCLK__BIT 0 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__STOP 3 + +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__BIT 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__HWEN 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__SWEN 1 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__RSVD 2 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__STOP 3 + +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__BIT 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__HWEN 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__SWEN 1 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__RSVD 2 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__STOP 3 + +#define LPCG__SS_SCU__LPIT1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__BIT 0 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__HWEN 0 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__SWEN 1 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__RSVD 2 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__STOP 3 + +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__BIT 0 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__HWEN 0 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__SWEN 1 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__RSVD 2 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__STOP 3 + +#define LPCG__SS_SCU__LPUART1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__BIT 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__HWEN 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__SWEN 1 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__RSVD 2 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__STOP 3 + +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__BIT 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__HWEN 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__SWEN 1 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__RSVD 2 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__STOP 3 + +#define LPCG__SS_SCU__TPM1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_TPM +#define LPCG__SS_SCU__TPM1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__TPM1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__TPM1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__TPM1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__TPM1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__REG 0x0000 // IPS_SLOT=CLK_TPM +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__BIT 0 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__HWEN 0 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__SWEN 1 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__RSVD 2 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__STOP 3 + +#endif + diff --git a/platform/config/mx8dxl/soc.bom b/platform/config/mx8dxl/soc.bom new file mode 100755 index 0000000..4cb4282 --- /dev/null +++ b/platform/config/mx8dxl/soc.bom @@ -0,0 +1,52 @@ + +SOC = MX8DXL + +DRV += \ + analog \ + csr \ + dsc \ + mtr \ + otp \ + pad \ + reset \ + snvs/v2 \ + seco/v2 \ + sysctr \ + xrdc2 \ + v2x + +DRV2 += \ + rgpio \ + igpio \ + lmem \ + lpi2c \ + lpit \ + lpcg \ + lpuart \ + mu \ + systick \ + drc \ + wdog32 \ + nic400 + +SS += \ + a35/v2 \ + adma/v3 \ + base/v1 \ + conn/v2 \ + db/v4 \ + drc/v3 \ + hsio/v2 \ + lsio/v2 \ + m4/v1 \ + sc/v2 + +SVC += \ + irq \ + misc \ + pad \ + pm \ + rm \ + seco \ + timer + diff --git a/platform/config/mx8dxl/soc.h b/platform/config/mx8dxl/soc.h new file mode 100755 index 0000000..37317fc --- /dev/null +++ b/platform/config/mx8dxl/soc.h @@ -0,0 +1,575 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure SoC specific features of the SCFW. + * Includes info on memory map, DSC mapping, subsystem mapping, etc. + * + */ +/*==========================================================================*/ + +#ifndef SC_SOC_H +#define SC_SOC_H + +/* Includes */ +#include "main/types.h" +#include "has_ss.h" +#include "fsl_device_registers.h" +#include "ss/drc/v3/dsc.h" + +/* Configure DSCs */ + +/*! Macro to calculate DSC index */ +#define DSC_IDX(X) ((sc_dsc_t) ((((uint32_t) (X)) - ((uint32_t) MSI0_BASE)) / 131072U)) + +/*! Macro to define AI_READ/WRITE */ +#define ANA_READ(BASE_IDX, TOG, ADDRESS, RDATA) DSC_AIRegisterRead(BASE_IDX, TOG, ADDRESS, RDATA) +#define ANA_WRITE(BASE_IDX, TOG, ADDRESS, DATAWORD) DSC_AIRegisterWrite(BASE_IDX, TOG, ADDRESS, DATAWORD) +#define ANA_ENABLE_ANAMIX_AI(BASE_IDX) DSC_EnableAnamixAI(BASE_IDX) +#define ANA_ENABLE_PHYMIX_AI(BASE_IDX) DSC_EnablePhymixAI(BASE_IDX) + +/*! Define for Refgen default trim in case of unfused part */ +#define REFGEN_DEFAULT_TRIM 0x2BU + +/*! + * @name Defines for sc_dsc_t + */ +/** @{ */ +#define SC_DSC_SC DSC_IDX(DSC_SC) /* 0x01 */ +#define SC_DSC_ADMA DSC_IDX(DSC_ADMA) /* 0x13 */ +#define SC_DSC_MCU_0 DSC_IDX(DSC_MCU_0) /* 0x16 */ +#define SC_DSC_CONN DSC_IDX(DSC_CONN) /* 0x19 */ +#define SC_DSC_DRC_0 DSC_IDX(DSC_DRC_0) /* 0x24 */ +#define SC_DSC_HSIO DSC_IDX(DSC_HSIO) /* 0x26 */ +#define SC_DSC_DB DSC_IDX(DSC_DB) /* 0x32 */ +#define SC_DSC_AP_2 DSC_IDX(DSC_AP_2) /* 0x35 */ +#define SC_DSC_LSIO DSC_IDX(DSC_LSIO) /* 0x38 */ +#define SC_DSC_LAST 0x3FU +#define SC_DSC_DRC_1 0x3FU +#define SC_DSC_NA SC_DSC_LAST +#define SC_DSC_W 6U +/** @} */ + +/*! + * DSC Type. This type is a used to indicate a Distributed Slave + * Controller (DSC). + */ +typedef uint8_t sc_dsc_t; + +/*! + * @name Defines for sc_ai_t + */ +/** @{ */ +#define SC_AI_HP_PLL 0U +#define SC_AI_DIG_PLL 1U +#define SC_AI_AV_PLL 2U +#define SC_AI_LVDS_TRANS 3U +#define SC_AI_BANDGAP_REF 4U +#define SC_AI_VA_REFGEN 5U +#define SC_AI_NEG_CHARGE_PUMP 6U +#define SC_AI_WELL_LEVEL_SOURCE 7U +#define SC_AI_DIFFCLK_ROOT 8U +#define SC_AI_DIFFCLK_RPTR 9U +#define SC_AI_DIFFCLK_TERM 10U +#define SC_AI_PHY_LDO 11U +#define SC_AI_OSC24M 12U +#define SC_AI_RC200OSC 13U +#define SC_AI_TEMP_SENSE 14U +#define SC_AI_VDROP_PROCMON 15U +#define SC_AI_LAST 16U +/** @} */ + +/*! + * Analog Interface Modules Types. + */ +typedef uint8_t sc_ai_t; + +/* Configure Subsystems */ + +typedef uint8_t sc_ss_inst_t; + +#define SC_SS_INST_W 1U + +/*! + * @name Defines for sc_sub_t + */ +/** @{ */ +#define SC_SUBSYS_SC 0U +#define SC_SUBSYS_MCU_0 1U +#define SC_SUBSYS_A35 2U +#define SC_SUBSYS_ADMA 3U +#define SC_SUBSYS_CONN 4U +#define SC_SUBSYS_DB 5U +#define SC_SUBSYS_DRC_0 6U +#define SC_SUBSYS_LSIO 7U +#define SC_SUBSYS_HSIO 8U +#define SC_SUBSYS_LAST SC_SUBSYS_HSIO +#define SC_SUBSYS_W 4U +#define SC_SUBSYS_NA 15U +/** @} */ + +/*! + * Subsystem Type. This type is used to indicate a subsystem. + */ +typedef uint8_t sc_sub_t; + +#define SC_PGP_00 0U +#define SC_PGP_01 1U +#define SC_PGP_02 2U +#define SC_PGP_03 3U +#define SC_PGP_04 4U +#define SC_PGP_05 5U +#define SC_PGP_06 6U + +#define SC_PGP_W 3U +#define SC_PGP_NA 7U + +#define MTR_PWR_PLAN_SEL_SCU0 0U +#define MTR_PWR_PLAN_SEL_DB 1U +#define MTR_PWR_PLAN_SEL_HSIO 2U +#define MTR_PWR_PLAN_SEL_MCU_0 3U +#define MTR_PWR_PLAN_SEL_LSIO 4U +#define MTR_PWR_PLAN_SEL_CA35 6U +#define MTR_PWR_PLAN_SEL_CONNECTIVITY 7U +#define MTR_PWR_PLAN_SEL_DRC_0 9U +#define MTR_PWR_PLAN_SEL_ADMA 13U + +#define SC_SS_INFO_INIT \ + {HAS_SS_SC, 0, SC_PGP_00, SC_SUBSYS_NA, 0, 0, SC_DSC_SC}, /* SC_SUBSYS_SC */ \ + {HAS_SS_MCU_0, 0, SC_PGP_01, SC_SUBSYS_NA, 0, 0, SC_DSC_MCU_0}, /* SC_SUBSYS_MCU_0 */ \ + {HAS_SS_AP_2, 0, SC_PGP_06, SC_SUBSYS_NA, 0, 0, SC_DSC_AP_2}, /* SC_SUBSYS_A35 */ \ + {HAS_SS_ADMA, 0, SC_PGP_02, SC_SUBSYS_NA, 0, 0, SC_DSC_ADMA}, /* SC_SUBSYS_ADMA */ \ + {HAS_SS_CONN, 0, SC_PGP_03, SC_SUBSYS_NA, 0, 0, SC_DSC_CONN}, /* SC_SUBSYS_CONN */ \ + {HAS_SS_DB, 0, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DB}, /* SC_SUBSYS_DB */ \ + {HAS_SS_DRC_0, 0, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DRC_0}, /* SC_SUBSYS_DRC_0 */ \ + {HAS_SS_LSIO, 0, SC_PGP_05, SC_SUBSYS_NA, 0, 0, SC_DSC_LSIO}, /* SC_SUBSYS_LSIO */ \ + {HAS_SS_HSIO_0, 0, SC_PGP_04, SC_SUBSYS_NA, 0, 0, SC_DSC_HSIO} /* SC_SUBSYS_HSIO */ + +/*! Number of DB */ +#define SC_NUM_DB 1U + +/*! + * DB Connect Type. Stores a subsystem connection mask. + */ +typedef uint32_t sc_db_connect_t; + +/*! DB connect mask */ +#define SC_DB_CONNECT \ + ( BIT(SC_SUBSYS_SC) \ + | BIT(SC_SUBSYS_MCU_0) \ + | BIT(SC_SUBSYS_A35) \ + | BIT(SC_SUBSYS_ADMA) \ + | BIT(SC_SUBSYS_CONN) \ + | BIT(SC_SUBSYS_DRC_0) \ + | BIT(SC_SUBSYS_LSIO) \ + | BIT(SC_SUBSYS_HSIO)) + +/*! Init order of DB (SCU outward) */ +#define SC_DB_INIT \ + {SC_R_DB, SC_SUBSYS_DB, SC_DB_CONNECT} + +#define SC_SS_EP_INIT \ + SS_EP_INIT_SC, /* SC_SUBSYS_SC */ \ + SS_EP_INIT_M4, /* SC_SUBSYS_MCU_0 */ \ + SS_EP_INIT_A35, /* SC_SUBSYS_A35 */ \ + SS_EP_INIT_ADMA, /* SC_SUBSYS_ADMA */ \ + SS_EP_INIT_CONN, /* SC_SUBSYS_CONN */ \ + SS_EP_INIT_DB, /* SC_SUBSYS_DB */ \ + SS_EP_INIT_DRC, /* SC_SUBSYS_DRC_0 */ \ + SS_EP_INIT_LSIO, /* SC_SUBSYS_LSIO */ \ + SS_EP_INIT_HSIO /* SC_SUBSYS_HSIO */ + +#define SC_SS_BASE_INFO_INIT \ + &ss_base_info_sc, /* SC_SUBSYS_SC */ \ + &ss_base_info_m4, /* SC_SUBSYS_MCU_0 */ \ + &ss_base_info_a35, /* SC_SUBSYS_A35 */ \ + &ss_base_info_adma, /* SC_SUBSYS_ADMA */ \ + &ss_base_info_conn, /* SC_SUBSYS_CONN */ \ + &ss_base_info_db, /* SC_SUBSYS_DB */ \ + &ss_base_info_drc, /* SC_SUBSYS_DRC_0 */ \ + &ss_base_info_lsio, /* SC_SUBSYS_LSIO */ \ + &ss_base_info_hsio /* SC_SUBSYS_HSIO */ + +#ifdef DEBUG + #define SNAME_INIT \ + "SC", \ + "M4_0", \ + "A35", \ + "ADMA", \ + "CONN", \ + "DB", \ + "DRC_0", \ + "LSIO", \ + "HSIO" + + #define RNAME_INIT \ + RNAME_INIT_SC_0 \ + RNAME_INIT_M4_0 \ + RNAME_INIT_A35_0 \ + RNAME_INIT_ADMA_0 \ + RNAME_INIT_CONN_0 \ + RNAME_INIT_DB_0 \ + RNAME_INIT_DRC_0 \ + RNAME_INIT_LSIO_0 \ + RNAME_INIT_HSIO_0 \ + RNAME_INIT_BRD + +#endif + +#define SC_R_DDR SC_R_DRC_0 +#define SC_R_DDR_PLL SC_R_DRC_0_PLL + +/*! Chip versions */ +#define CHIP_VER_A0 0x0U +#define CHIP_VER_A1 0x1U + +/*! Macro to get JTAG ID */ +#ifndef SIMU + #define JTAG_ID (DSC_SC->GPR_STAT[2].RW & 0x1FFU) +#else + #ifdef SREV_A0 + #define JTAG_ID ((CHIP_VER_A0 << 5U) | CHIP_ID_DXL) + #endif + #ifdef SREV_A1 + #define JTAG_ID ((CHIP_VER_A1 << 5U) | CHIP_ID_DXL) + #endif +#endif + +/*! Macros to get chip ID and version */ +#define CHIP_ID ((JTAG_ID >> 0U) & 0x1FU) +#define CHIP_VER ((JTAG_ID >> 5U) & 0xFU) + +/* Configure Top Level Memory Map */ + +#define SC_MEMMAP_INIT \ + { LSIO_SS_BASE1, 0x1C000000U, 1, 1, 30, 1, 0x00, SC_SUBSYS_LSIO}, \ + { SCU_SS_BASE0, 0x4000000U, 0, 1, 26, 0, 0x00, SC_SUBSYS_SC}, \ + { MCU_0_SS_BASE0, 0x4000000U, 1, 1, 26, 0, 0x00, SC_SUBSYS_MCU_0}, \ + {HSIO_0_SS_BASE2, 0x10000000U, 1, 1, 28, 2, 0x00, SC_SUBSYS_HSIO}, \ + { DDR_BASE0, 0x80000000U, 1, 0, 0, 0, 0x00, SC_SUBSYS_DB}, \ + { DDR_BASE1, 0x780000000ULL, 1, 0, 0, 0, 0x00, SC_SUBSYS_DB}, \ + { SC_NA, SC_NA, 0, 0, 0, 0, 0, 0} + +#define SC_BOOT_ADDR_INIT \ + {OCRAM_ALIAS_BASE, 0x17FFFU, SC_R_OCRAM, SC_SUBSYS_LSIO}, \ + { OCRAM_BASE, 0x3FFFFU, SC_R_OCRAM, SC_SUBSYS_LSIO}, \ + { FSPI0_MEM_BASE, 0x10000000U, SC_R_FSPI_0, SC_SUBSYS_LSIO}, \ + { TCML_MCU_0, 0x4000000U, SC_R_MCU_0_PID0, SC_SUBSYS_MCU_0}, \ + { DDR_BASE0, 0x80000000U, SC_R_DRC_0, SC_SUBSYS_DRC_0}, \ + { DDR_BASE1, 0x780000000ULL, SC_R_DRC_0, SC_SUBSYS_DRC_0}, \ + { SC_NA, SC_NA, 0U, 0U} + +/* Configure Features */ + +/* Configure RM */ +#define SC_RM_NUM_PARTITION 20U //!< Number of resource partitions +#define SC_RM_NUM_MEMREG 64U //!< Number of memory regions +#define SC_RM_NUM_DOMAIN 16U //!< Number of resource domains + +/*! PLL frequencies */ +#define MIN_PLL_RATE 648000000U +#define MAX_PLL_RATE 1344000000U +#define MIN_HP_PLL_RATE 1250000000U +#define MAX_HP_PLL_RATE 2500000000U +#define MIN_HP_PLL_1P5_RATE 833333333U +#define PLL_RATE_DEN 960000U +#define DIV_FACTOR_NUM 2U +#define DIV_FACTOR_DEN 3U + +/*! + * Define operating points for A35. + */ +#define NUM_A35_OPP 1 + +/*! Has 28FDSOI in SCFW API */ +#define API_HAS_28FDSOI + +/*! Has V2X in SCFW API */ +#define API_HAS_V2X + +/*! Has V2X in DB */ +#define V2X_IN_DB + +/*! Requires V2X FW copy from FlexSPI */ +#define FLEXSPI_V2X_ADDR 0x1400UL +#define FLEXSPI_DUMMY_ADDR 0x1800UL + +/*! Support partitioning naming for debug */ +#define HAS_PARTITION_NAMES + +/*! Enhanced monitor support */ +#define MONITOR_HAS_CMD_OFF +#define MONITOR_HAS_CMD_MSG +#define MONITOR_HAS_CMD_VDETECT +#define MONITOR_HAS_CMD_WDOG +#define MONITOR_HAS_CMD_PANIC +#define MONITOR_HAS_CMD_MRC +#define MONITOR_HAS_CMD_BOOT +#define MONITOR_HAS_CMD_WAKE +#define MONITOR_HAS_CMD_GRANT + +/*! Define to use SECO FW */ +#define HAS_SECO_FW + +/*! Defines for FW versions */ +#define SECO_FW_VERSION ((0UL << 16) | (7UL << 4) | 4UL) +#define V2X_FW_VERSION ((0UL << 16) | (0UL << 4) | 7UL) + +/*! Define DDR DATX8 Lanes */ +#define DWC_NO_OF_BYTES 2U + +/*! Defines for AI temp sensor */ +#define FUSE_TEMP_AUTO 0x0 +#define FUSE_TEMP_INDUSL 0x1 +#define FUSE_TEMP_CONS 0x2 +#define FUSE_TEMP_EX_CONS 0x3 +#define AI_TEMP_RATE 1000U +#define AI_TEMP_NP 1915 +#define AI_TEMP_NT 25 +#define AI_TEMP_PANIC 127 +#define AI_TEMP_PANIC_AUTO 127 +#define AI_TEMP_PANIC_INDUS 107 +#define AI_TEMP_PANIC_CONS 97 +#define AI_TEMP_PANIC_EX_CONS 107 + +/*! Define to indicate timer services required */ +#define HAS_TIMER_SERVICES + +/*! Number of boot images supported by ROM */ +#define SC_BOOT_MAX_LIST 8U + +/* Define boot cpu and address based on whether or + not we're running the DDR stress test */ +#ifdef M4_BOOT + #define BOOT_CPU SC_R_MCU_0_PID0 + #define BOOT_ADDR 0x000000000ULL + #define BOOT_MU SC_R_MCU_0_MU_1A + #define BOOT_CPU_STARTS 1U + #define BOOT_SRC 0x00040000U + #define BOOT_DST 0x34FE0000U + #define BOOT_SIZE 0x20000U + #define BOOT_FLAGS 0x00000000U +#elif defined(TEST_BOOTTIME) + #define BOOT_CPU SC_R_MCU_0_PID0 + #define BOOT_ADDR 0x000000000ULL + #define BOOT_MU SC_R_MCU_0_MU_1A + #define BOOT_CPU_STARTS 1U + #define BOOT_FLAGS 0x00400000U +#else + #define BOOT_CPU SC_R_AP_2_0 + #define BOOT_ADDR 0x080000000UL + #define BOOT_MU SC_R_MU_0A + #define BOOT_CPU_STARTS 1U + #define BOOT_FLAGS 0x00000000U +#endif + +/* Boot data address */ +#define SC_BOOT_DATA_ADDR_PTR 0x000005F0U +#define SC_BOOT_DATA_ADDR 0x2001FC00U +#define SC_BOOT_DATA2_ADDR 0x2001FD00U + +/*! Rom uses patch headers */ +#define ROM_PATCH_HEADER + +/*! OTP patch areas */ +#define SOC_PATCH_AREA_CNT 3U + +/*! OTP patch area list */ +#define SOC_PATCH_AREA_INIT \ + {OTP_ROM_PATCH, OTP_ROM_PATCH_SIZE}, \ + {OTP_SECO_PATCH2, OTP_SECO_PATCH2_SIZE}, \ + {OTP_SECO_PATCH, OTP_SECO_PATCH_SIZE} + +/*! Rom boot device mappings */ +/** @{ */ +#define ROM_SDHC_0 SC_R_SDHC_0 +#define ROM_SDHC_1 SC_R_SDHC_1 +#define ROM_SDHC_2 SC_R_SDHC_2 +#define ROM_FSPI_0 SC_R_FSPI_0 +#define ROM_FSPI_1 SC_R_FSPI_1 +#define ROM_USB_0 SC_R_USB_0 +#define ROM_USB_1 SC_R_USB_0 +#define ROM_USB_2 SC_R_USB_1 +/** @} */ + +/* Configure Tests */ +#define TEST_HSIO0_PCIE SC_R_PCIE_B +#define TEST_HSIO0_SERDES SC_R_SERDES_1 +#define TEST_HSIO0_MATCH_0 SC_R_MATCH_0 +#define SC_P_TEST_PAD SC_P_UART1_RX +#define SC_P_TEST_PAD_COMP SC_P_COMP_CTL_GPIO_3V3_USB3IO +#define TEST_LSIO HAS_SS_LSIO +#define TEST_DMA HAS_SS_ADMA +#define TEST_BOARD_ALT2 SC_FALSE + +/* Max MRC regions */ +#define SC_MAX_NUM_MEMREG \ +( \ + 16U /* DB */ \ + + 32U /* HSIO */ \ + + 48U /* LSIO */ \ + + 4U /* MCU */ \ + + 4U /* SC */ \ +) + +/*! Define to indicate number of CAAM job rings */ +#define SC_CAAM_JR 4U + +/*! Define to indicate number of MU */ +#define SC_SECO_MU 4U + +/*! Enable FAKE_TBU use by MCU */ +#define SC_FAKE_TBU + +/*! Disable AP access to LSIO memory for ERR050601 */ +#define ERR050601_WORKAROUND + +/* Configure Resources */ +#define SC_NO_DTCP + +/* Define CPU topology */ +#define SOC_NUM_CLUSTER 1U +#define SOC_IDX_AP_2 0U +#define SOC_NUM_AP_2 2U +#define SOC_NUM_DIG_AUD_PLL 2U + +/* Define MCU topology */ +#define SOC_NUM_MCU 1U +#define SOC_IDX_MCU_0 0U + +/* Define auxiliary processor topology */ +#define SOC_NUM_AUX 1U +#define SOC_IDX_AUX_0 0U /* AUX_0 is mapped to V2X */ + +/* Define HMP topology */ +#define SOC_NUM_HMP_NODES 4U +#define SOC_HMP_IDX_SCU 0U /* SCU must be index 0 */ +#define SOC_HMP_IDX_MCU_0 1U /* MCU order must follow topology above */ +#define SOC_HMP_IDX_AP_2 2U +#define SOC_HMP_IDX_AUX_0 3U +#define SOC_HMP_IDX_MCU SOC_HMP_IDX_MCU_0 +#define SOC_HMP_IDX_AP SOC_HMP_IDX_AP_2 +#define SOC_HMP_IDX_AUX SOC_HMP_IDX_AUX_0 + +/* Define system-level interface topology */ +#define SOC_NUM_SYS_IF 4U /* Number of system-level interfaces */ +#define SOC_SYS_IF_MU_RSRC 5U /* Number of AP -> SCU message unit resources */ +#define SOC_SYS_IF_ICN_RSRC 1U /* Number of interconnect resources */ +#define SOC_SYS_IF_OCMEM_RSRC 3U /* Number of on-chip memory resources */ +#define SOC_SYS_IF_DDR_RSRC 1U /* Number of DDR resources */ +#define SOC_SYS_IF_CPU_HPM SC_PM_PW_MODE_LP /* CPU power mode threshold for HPM */ + +/* Define wakeup bindings */ +#define SOC_GIC_DSC SC_DSC_ADMA /* DSC for GIC wakeups */ +#define SOC_IRQSTEER_DSC SC_DSC_ADMA /* DSC for IRQSTEER wakeup */ +#define SOC_GIC_WAKEUP00 REGBIT64(1, 0) /* DSC IRQ for GIC wakeups */ +#define SOC_IRQSTEER_AP_WAKEUP REGBIT64(1, 11) /* DSC IRQ for AP IRQSTEER wakeup */ +#define SOC_IRQSTEER_MCU_WAKEUP REGBIT64(1, 9) /* DSC IRQ for MCU IRQSTEER wakeup */ +#define SOC_WAKEUP_PW_MODE SC_PM_PW_MODE_STBY /* CPU power mode limit for GIC wakeup */ +#define SOC_RESUME_PW_MODE SC_PM_PW_MODE_ON /* CPU power mode for resume */ +#define SOC_MCU_STOPM_PDN 3U /* STOPM >= 3 will power down MCU core */ +#define SOC_MCU_STOPM_MEMSR 3U /* STOPM == 3 will retain memories */ +#define SOC_SNVS_PWR_ON_WAKEUP REGBIT64(1, 10) /* DSC IRQ for SNVS_LP set_pwr_on_irq */ + +/* Define ADMA mbist */ +#define SS_ADMA_BIST1 (((uint32_t)DSC_ADMA) + 0x8020U) +#define SS_ADMA_BIST1_START 230U +#define SS_ADMA_BIST1_END 233U + +#define SS_ADMA_BIST3 (((uint32_t)DSC_ADMA) + 0x8040U) +#define SS_ADMA_BIST3_START 234U +#define SS_ADMA_BIST3_END 266U + +/* Defines for DDR training */ +#define DQS_TIMER_DURATION_512 1U /* 512 * tCK = 2048 * (1/1200) = 1 us (round up) */ +#define DQS_TIMER_DURATION_1008 1U /* 1008 * tCK = 1008 * (1/1200) = 1 us (round up) */ +#define DQS_TIMER_DURATION_2048 2U /* 2048 * tCK = 2048 * (1/1200) = 2 us (round up) */ +#define DQS_TIMER_DURATION_8192 7U /* 8192 * tCK = 8192 * (1/1200) = 7 us (round up) */ + +/* Include SS configs */ + +#include "all_config.h" +#include "board/config.h" +#include "handlers_MX8DXL.h" /* Device specific handlers */ + +/* Configure Resources */ + +#define SC_NUM_RSRC \ + (SS_NUM_RSRC_SC \ + + SS_NUM_RSRC_M4 \ + + SS_NUM_RSRC_A35 \ + + SS_NUM_RSRC_ADMA \ + + SS_NUM_RSRC_CONN \ + + SS_NUM_RSRC_DB \ + + SS_NUM_RSRC_DRC \ + + SS_NUM_RSRC_LSIO \ + + SS_NUM_RSRC_HSIO \ + + BRD_NUM_RSRC_BRD) + +#define SC_PAD_INIT_INIT \ + {SC_P_USB_SS3_TC0, 4, 0}, \ + {SC_P_USB_SS3_TC1, 4, 0}, \ + {SC_P_USB_SS3_TC2, 4, 0}, \ + {SC_P_USB_SS3_TC3, 4, 0}, \ + {SC_P_USDHC1_RESET_B, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_VSELECT, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_WP, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_CD_B, 4, SC_R_SDHC_1}, \ + {SC_P_MCLK_IN0, 4, 0}, \ + {SC_P_MCLK_OUT0, 4, 0}, \ + {SC_P_FLEXCAN0_RX, 4, SC_R_CAN_0}, \ + {SC_P_FLEXCAN0_TX, 4, SC_R_CAN_0}, \ + {SC_P_FLEXCAN1_RX, 4, SC_R_CAN_1}, \ + {SC_P_FLEXCAN1_TX, 4, SC_R_CAN_1}, \ + {0, 0, 0} + +#define SC_ROM_SS_INIT \ + 0, /* SC_SUBSYS_SC */ \ + 1, /* SC_SUBSYS_MCU_0 */ \ + 2, /* SC_SUBSYS_A35 */ \ + 7, /* SC_SUBSYS_ADMA */ \ + 8, /* SC_SUBSYS_CONN */ \ + 9, /* SC_SUBSYS_DB */ \ + 10, /* SC_SUBSYS_DRC_0 */ \ + 11, /* SC_SUBSYS_LSIO */ \ + 12 /* SC_SUBSYS_HSIO */ + +#define DB_NIC0_AP_PORT_IDX 6 + +#endif /* SC_SOC_H */ + diff --git a/platform/config/mx8qm/ALL/has_ss.h b/platform/config/mx8qm/ALL/has_ss.h new file mode 100755 index 0000000..8bbea8a --- /dev/null +++ b/platform/config/mx8qm/ALL/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 1 +#define HAS_SS_CCI 1 +#define HAS_SS_AP_0 1 +#define HAS_SS_AP_1 1 +#define HAS_SS_AP_2 0 +#define HAS_SS_GPU_0 1 +#define HAS_SS_GPU_1 1 +#define HAS_SS_VPU 1 +#define HAS_SS_DC_0 1 +#define HAS_SS_DC_1 1 +#define HAS_SS_IMG_0 1 +#define HAS_SS_AUDIO 1 +#define HAS_SS_ADMA 0 +#define HAS_SS_DMA 1 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 1 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 1 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 1 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 1 +#define HAS_SS_LVDS_1 1 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 1 +#define HAS_SS_CSI_1 1 +#define HAS_SS_HDMI_RX 1 +#define HAS_SS_HDMI 1 +#define HAS_SS_MIPI_0 1 +#define HAS_SS_MIPI_1 1 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qm/AP/has_ss.h b/platform/config/mx8qm/AP/has_ss.h new file mode 100755 index 0000000..7204607 --- /dev/null +++ b/platform/config/mx8qm/AP/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 0 +#define HAS_SS_MCU_1 0 +#define HAS_SS_CCI 1 +#define HAS_SS_AP_0 1 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 0 +#define HAS_SS_GPU_0 0 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 0 +#define HAS_SS_DC_0 0 +#define HAS_SS_DC_1 0 +#define HAS_SS_IMG_0 0 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 0 +#define HAS_SS_DMA 1 +#define HAS_SS_CONN 0 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 1 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 1 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 0 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 0 +#define HAS_SS_LVDS_1 0 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 0 +#define HAS_SS_CSI_1 0 +#define HAS_SS_HDMI_RX 0 +#define HAS_SS_HDMI 0 +#define HAS_SS_MIPI_0 0 +#define HAS_SS_MIPI_1 0 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qm/AV/has_ss.h b/platform/config/mx8qm/AV/has_ss.h new file mode 100755 index 0000000..ea40407 --- /dev/null +++ b/platform/config/mx8qm/AV/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 1 +#define HAS_SS_CCI 1 +#define HAS_SS_AP_0 1 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 0 +#define HAS_SS_GPU_0 0 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 1 +#define HAS_SS_DC_0 1 +#define HAS_SS_DC_1 1 +#define HAS_SS_IMG_0 1 +#define HAS_SS_AUDIO 1 +#define HAS_SS_ADMA 0 +#define HAS_SS_DMA 1 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 1 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 1 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 0 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 1 +#define HAS_SS_LVDS_1 1 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 1 +#define HAS_SS_CSI_1 1 +#define HAS_SS_HDMI_RX 1 +#define HAS_SS_HDMI 1 +#define HAS_SS_MIPI_0 1 +#define HAS_SS_MIPI_1 1 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qm/CORES/has_ss.h b/platform/config/mx8qm/CORES/has_ss.h new file mode 100755 index 0000000..5802aa9 --- /dev/null +++ b/platform/config/mx8qm/CORES/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 1 +#define HAS_SS_CCI 1 +#define HAS_SS_AP_0 1 +#define HAS_SS_AP_1 1 +#define HAS_SS_AP_2 0 +#define HAS_SS_GPU_0 0 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 0 +#define HAS_SS_DC_0 0 +#define HAS_SS_DC_1 0 +#define HAS_SS_IMG_0 0 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 0 +#define HAS_SS_DMA 1 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 1 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 1 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 1 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 0 +#define HAS_SS_LVDS_1 0 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 0 +#define HAS_SS_CSI_1 0 +#define HAS_SS_HDMI_RX 0 +#define HAS_SS_HDMI 0 +#define HAS_SS_MIPI_0 0 +#define HAS_SS_MIPI_1 0 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qm/GFX/has_ss.h b/platform/config/mx8qm/GFX/has_ss.h new file mode 100755 index 0000000..2257ede --- /dev/null +++ b/platform/config/mx8qm/GFX/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 1 +#define HAS_SS_CCI 1 +#define HAS_SS_AP_0 1 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 0 +#define HAS_SS_GPU_0 1 +#define HAS_SS_GPU_1 1 +#define HAS_SS_VPU 0 +#define HAS_SS_DC_0 1 +#define HAS_SS_DC_1 1 +#define HAS_SS_IMG_0 1 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 0 +#define HAS_SS_DMA 1 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 1 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 1 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 0 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 1 +#define HAS_SS_LVDS_1 1 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 1 +#define HAS_SS_CSI_1 1 +#define HAS_SS_HDMI_RX 1 +#define HAS_SS_HDMI 1 +#define HAS_SS_MIPI_0 1 +#define HAS_SS_MIPI_1 1 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qm/all_api.h b/platform/config/mx8qm/all_api.h new file mode 100644 index 0000000..1098e72 --- /dev/null +++ b/platform/config/mx8qm/all_api.h @@ -0,0 +1,60 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing includes. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/include_h.pl */ + +#ifndef SC_PLATFORM_CONFIG_MX8QM_ALL_API_H +#define SC_PLATFORM_CONFIG_MX8QM_ALL_API_H + +/* Includes */ + +#include "svc/irq/api.h" +#include "svc/misc/api.h" +#include "svc/pad/api.h" +#include "svc/pm/api.h" +#include "svc/rm/api.h" +#include "svc/seco/api.h" +#include "svc/timer/api.h" + +#endif /* SC_PLATFORM_CONFIG_MX8QM_ALL_API_H */ + diff --git a/platform/config/mx8qm/all_config.h b/platform/config/mx8qm/all_config.h new file mode 100644 index 0000000..f46508f --- /dev/null +++ b/platform/config/mx8qm/all_config.h @@ -0,0 +1,76 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing includes. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/include_h.pl */ + +#ifndef SC_PLATFORM_CONFIG_MX8QM_ALL_CONFIG_H +#define SC_PLATFORM_CONFIG_MX8QM_ALL_CONFIG_H + +/* Includes */ + +#include "ss/a53/v1/config.h" +#include "ss/a72/v1/config.h" +#include "ss/audio/v1/config.h" +#include "ss/base/v1/config.h" +#include "ss/cci/v1/config.h" +#include "ss/conn/v1/config.h" +#include "ss/csi/v1/config.h" +#include "ss/db/v1/config.h" +#include "ss/dblogic/v1/config.h" +#include "ss/dc/v1/config.h" +#include "ss/dma/v1/config.h" +#include "ss/drc/v1/config.h" +#include "ss/gpu/v1/config.h" +#include "ss/hdmi/v1/config.h" +#include "ss/hdmi_rx/v1/config.h" +#include "ss/hsio/v1/config.h" +#include "ss/img/v1/config.h" +#include "ss/lsio/v2/config.h" +#include "ss/lvds/v1/config.h" +#include "ss/m4/v1/config.h" +#include "ss/mipi/v1/config.h" +#include "ss/sc/v2/config.h" +#include "ss/vpu/v3/config.h" + +#endif /* SC_PLATFORM_CONFIG_MX8QM_ALL_CONFIG_H */ + diff --git a/platform/config/mx8qm/all_ss.h b/platform/config/mx8qm/all_ss.h new file mode 100644 index 0000000..3ac851e --- /dev/null +++ b/platform/config/mx8qm/all_ss.h @@ -0,0 +1,76 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing includes. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/include_h.pl */ + +#ifndef SC_PLATFORM_CONFIG_MX8QM_ALL_SS_H +#define SC_PLATFORM_CONFIG_MX8QM_ALL_SS_H + +/* Includes */ + +#include "ss/a53/v1/ss.h" +#include "ss/a72/v1/ss.h" +#include "ss/audio/v1/ss.h" +#include "ss/base/v1/ss.h" +#include "ss/cci/v1/ss.h" +#include "ss/conn/v1/ss.h" +#include "ss/csi/v1/ss.h" +#include "ss/db/v1/ss.h" +#include "ss/dblogic/v1/ss.h" +#include "ss/dc/v1/ss.h" +#include "ss/dma/v1/ss.h" +#include "ss/drc/v1/ss.h" +#include "ss/gpu/v1/ss.h" +#include "ss/hdmi/v1/ss.h" +#include "ss/hdmi_rx/v1/ss.h" +#include "ss/hsio/v1/ss.h" +#include "ss/img/v1/ss.h" +#include "ss/lsio/v2/ss.h" +#include "ss/lvds/v1/ss.h" +#include "ss/m4/v1/ss.h" +#include "ss/mipi/v1/ss.h" +#include "ss/sc/v2/ss.h" +#include "ss/vpu/v3/ss.h" + +#endif /* SC_PLATFORM_CONFIG_MX8QM_ALL_SS_H */ + diff --git a/platform/config/mx8qm/all_svc.h b/platform/config/mx8qm/all_svc.h new file mode 100644 index 0000000..0ba8d62 --- /dev/null +++ b/platform/config/mx8qm/all_svc.h @@ -0,0 +1,60 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing includes. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/include_h.pl */ + +#ifndef SC_PLATFORM_CONFIG_MX8QM_ALL_SVC_H +#define SC_PLATFORM_CONFIG_MX8QM_ALL_SVC_H + +/* Includes */ + +#include "svc/irq/svc.h" +#include "svc/misc/svc.h" +#include "svc/pad/svc.h" +#include "svc/pm/svc.h" +#include "svc/rm/svc.h" +#include "svc/seco/svc.h" +#include "svc/timer/svc.h" + +#endif /* SC_PLATFORM_CONFIG_MX8QM_ALL_SVC_H */ + diff --git a/platform/config/mx8qm/iomuxd.h b/platform/config/mx8qm/iomuxd.h new file mode 100755 index 0000000..552c6c3 --- /dev/null +++ b/platform/config/mx8qm/iomuxd.h @@ -0,0 +1,342 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef IOMUXD_H +#define IOMUXD_H + +#ifndef IOMUXD_REG_BASE + #ifdef SCU_RESOURCES + #define IOMUXD_REG_BASE 0x41F80000U + #else + #define IOMUXD_REG_BASE 0x33F80000U + #endif +#endif + + // NUM RING GROUP PAD | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | +#define IOMUXD__SIM0_CLK REG32(IOMUXD_REG_BASE+0x00000000U) // 0 0 0 0 | DMA.SIM0.CLK | | | LSIO.GPIO0.IO00 | | | | | | +#define IOMUXD__SIM0_RST REG32(IOMUXD_REG_BASE+0x00000040U) // 0 0 0 1 | DMA.SIM0.RST | | | LSIO.GPIO0.IO01 | | | | | | +#define IOMUXD__SIM0_IO REG32(IOMUXD_REG_BASE+0x00000080U) // 0 0 0 2 | DMA.SIM0.IO | | | LSIO.GPIO0.IO02 | | | | | | +#define IOMUXD__SIM0_PD REG32(IOMUXD_REG_BASE+0x000000C0U) // 0 0 0 3 | DMA.SIM0.PD | DMA.I2C3.SCL | | LSIO.GPIO0.IO03 | | | | | | +#define IOMUXD__SIM0_POWER_EN REG32(IOMUXD_REG_BASE+0x00000100U) // 0 0 0 4 | DMA.SIM0.POWER_EN | DMA.I2C3.SDA | | LSIO.GPIO0.IO04 | | | | | | +#define IOMUXD__SIM0_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00000140U) // 0 0 0 5 | DMA.SIM0.POWER_EN | | | LSIO.GPIO0.IO05 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM REG32(IOMUXD_REG_BASE+0x00000180U) // 0 0 0 6 | | | | | | | | | | +#define IOMUXD__M40_I2C0_SCL REG32(IOMUXD_REG_BASE+0x000001C0U) // 0 0 0 7 | M40.I2C0.SCL | M40.UART0.RX | M40.GPIO0.IO02 | LSIO.GPIO0.IO06 | | | | | | +#define IOMUXD__M40_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00000200U) // 0 0 0 8 | M40.I2C0.SDA | M40.UART0.TX | M40.GPIO0.IO03 | LSIO.GPIO0.IO07 | | | | | | +#define IOMUXD__M40_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00000240U) // 0 0 0 9 | M40.GPIO0.IO00 | M40.TPM0.CH0 | DMA.UART4.RX | LSIO.GPIO0.IO08 | | | | | | +#define IOMUXD__M40_GPIO0_01 REG32(IOMUXD_REG_BASE+0x00000280U) // 0 0 0 10 | M40.GPIO0.IO01 | M40.TPM0.CH1 | DMA.UART4.TX | LSIO.GPIO0.IO09 | | | | | | +#define IOMUXD__M41_I2C0_SCL REG32(IOMUXD_REG_BASE+0x000002C0U) // 0 0 0 11 | M41.I2C0.SCL | M41.UART0.RX | M41.GPIO0.IO02 | LSIO.GPIO0.IO10 | | | | | | +#define IOMUXD__M41_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00000300U) // 0 0 0 12 | M41.I2C0.SDA | M41.UART0.TX | M41.GPIO0.IO03 | LSIO.GPIO0.IO11 | | | | | | +#define IOMUXD__M41_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00000340U) // 0 0 0 13 | M41.GPIO0.IO00 | M41.TPM0.CH0 | DMA.UART3.RX | LSIO.GPIO0.IO12 | | | | | | +#define IOMUXD__M41_GPIO0_01 REG32(IOMUXD_REG_BASE+0x00000380U) // 0 0 0 14 | M41.GPIO0.IO01 | M41.TPM0.CH1 | DMA.UART3.TX | LSIO.GPIO0.IO13 | | | | | | +#define IOMUXD__GPT0_CLK REG32(IOMUXD_REG_BASE+0x00001000U) // 1 0 1 0 | LSIO.GPT0.CLK | DMA.I2C1.SCL | LSIO.KPP0.COL4 | LSIO.GPIO0.IO14 | | | | | | +#define IOMUXD__GPT0_CAPTURE REG32(IOMUXD_REG_BASE+0x00001040U) // 1 0 1 1 | LSIO.GPT0.CAPTURE | DMA.I2C1.SDA | LSIO.KPP0.COL5 | LSIO.GPIO0.IO15 | | | | | | +#define IOMUXD__GPT0_COMPARE REG32(IOMUXD_REG_BASE+0x00001080U) // 1 0 1 2 | LSIO.GPT0.COMPARE | LSIO.PWM3.OUT | LSIO.KPP0.COL6 | LSIO.GPIO0.IO16 | | | | | | +#define IOMUXD__GPT1_CLK REG32(IOMUXD_REG_BASE+0x000010C0U) // 1 0 1 3 | LSIO.GPT1.CLK | DMA.I2C2.SCL | LSIO.KPP0.COL7 | LSIO.GPIO0.IO17 | | | | | | +#define IOMUXD__GPT1_CAPTURE REG32(IOMUXD_REG_BASE+0x00001100U) // 1 0 1 4 | LSIO.GPT1.CAPTURE | DMA.I2C2.SDA | LSIO.KPP0.ROW4 | LSIO.GPIO0.IO18 | | | | | | +#define IOMUXD__GPT1_COMPARE REG32(IOMUXD_REG_BASE+0x00001140U) // 1 0 1 5 | LSIO.GPT1.COMPARE | LSIO.PWM2.OUT | LSIO.KPP0.ROW5 | LSIO.GPIO0.IO19 | | | | | | +#define IOMUXD__UART0_RX REG32(IOMUXD_REG_BASE+0x00001180U) // 1 0 1 6 | DMA.UART0.RX | SCU.UART0.RX | | LSIO.GPIO0.IO20 | | | | | | +#define IOMUXD__UART0_TX REG32(IOMUXD_REG_BASE+0x000011C0U) // 1 0 1 7 | DMA.UART0.TX | SCU.UART0.TX | | LSIO.GPIO0.IO21 | | | | | | +#define IOMUXD__UART0_RTS_B REG32(IOMUXD_REG_BASE+0x00001200U) // 1 0 1 8 | DMA.UART0.RTS_B | LSIO.PWM0.OUT | DMA.UART2.RX | LSIO.GPIO0.IO22 | | | | | | +#define IOMUXD__UART0_CTS_B REG32(IOMUXD_REG_BASE+0x00001240U) // 1 0 1 9 | DMA.UART0.CTS_B | LSIO.PWM1.OUT | DMA.UART2.TX | LSIO.GPIO0.IO23 | | | | | | +#define IOMUXD__UART1_TX REG32(IOMUXD_REG_BASE+0x00001280U) // 1 0 1 10 | DMA.UART1.TX | DMA.SPI3.SCK | | LSIO.GPIO0.IO24 | | | | | | +#define IOMUXD__UART1_RX REG32(IOMUXD_REG_BASE+0x000012C0U) // 1 0 1 11 | DMA.UART1.RX | DMA.SPI3.SDO | | LSIO.GPIO0.IO25 | | | | | | +#define IOMUXD__UART1_RTS_B REG32(IOMUXD_REG_BASE+0x00001300U) // 1 0 1 12 | DMA.UART1.RTS_B | DMA.SPI3.SDI | DMA.UART1.CTS_B | LSIO.GPIO0.IO26 | | | | | | +#define IOMUXD__UART1_CTS_B REG32(IOMUXD_REG_BASE+0x00001340U) // 1 0 1 13 | DMA.UART1.CTS_B | DMA.SPI3.CS0 | DMA.UART1.RTS_B | LSIO.GPIO0.IO27 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH REG32(IOMUXD_REG_BASE+0x00001380U) // 1 0 1 14 | | | | | | | | | | +#define IOMUXD__SCU_PMIC_MEMC_ON REG32(IOMUXD_REG_BASE+0x000013C0U) // 1 0 1 15 | SCU.GPIO0.IOXX_PMIC_MEMC_ON | | | | | | | | | +#define IOMUXD__SCU_WDOG_OUT REG32(IOMUXD_REG_BASE+0x00002000U) // 2 0 2 0 | SCU.WDOG0.WDOG_OUT | | | | | | | | | +#define IOMUXD__PMIC_I2C_SDA REG32(IOMUXD_REG_BASE+0x00002040U) // 2 0 2 1 | SCU.PMIC_I2C.SDA | | | | | | | | | +#define IOMUXD__PMIC_I2C_SCL REG32(IOMUXD_REG_BASE+0x00002080U) // 2 0 2 2 | SCU.PMIC_I2C.SCL | | | | | | | | | +#define IOMUXD__PMIC_EARLY_WARNING REG32(IOMUXD_REG_BASE+0x000020C0U) // 2 0 2 3 | SCU.PMIC_EARLY_WARNING | | | | | | | | | +#define IOMUXD__PMIC_INT_B REG32(IOMUXD_REG_BASE+0x00002100U) // 2 0 2 4 | SCU.DSC.PMIC_INT_B | | | | | | | | | +#define IOMUXD__SCU_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00002140U) // 2 0 2 5 | SCU.GPIO0.IO00 | SCU.UART0.RX | | LSIO.GPIO0.IO28 | | | | | | +#define IOMUXD__SCU_GPIO0_01 REG32(IOMUXD_REG_BASE+0x00002180U) // 2 0 2 6 | SCU.GPIO0.IO01 | SCU.UART0.TX | | LSIO.GPIO0.IO29 | | | | | | +#define IOMUXD__SCU_GPIO0_02 REG32(IOMUXD_REG_BASE+0x00003000U) // 3 0 3 0 | SCU.GPIO0.IO02 | SCU.GPIO0.IOXX_PMIC_GPU0_ON | | LSIO.GPIO0.IO30 | | | | | | +#define IOMUXD__SCU_GPIO0_03 REG32(IOMUXD_REG_BASE+0x00003040U) // 3 0 3 1 | SCU.GPIO0.IO03 | SCU.GPIO0.IOXX_PMIC_GPU1_ON | | LSIO.GPIO0.IO31 | | | | | | +#define IOMUXD__SCU_GPIO0_04 REG32(IOMUXD_REG_BASE+0x00003080U) // 3 0 3 2 | SCU.GPIO0.IO04 | SCU.GPIO0.IOXX_PMIC_A72_ON | | LSIO.GPIO1.IO00 | | | | | | +#define IOMUXD__SCU_GPIO0_05 REG32(IOMUXD_REG_BASE+0x000030C0U) // 3 0 3 3 | SCU.GPIO0.IO05 | SCU.GPIO0.IOXX_PMIC_A53_ON | | LSIO.GPIO1.IO01 | | | | | | +#define IOMUXD__SCU_GPIO0_06 REG32(IOMUXD_REG_BASE+0x00003100U) // 3 0 3 4 | SCU.GPIO0.IO06 | SCU.TPM0.CH0 | | LSIO.GPIO1.IO02 | | | | | | +#define IOMUXD__SCU_GPIO0_07 REG32(IOMUXD_REG_BASE+0x00003140U) // 3 0 3 5 | SCU.GPIO0.IO07 | SCU.TPM0.CH1 | SCU.DSC.RTC_CLOCK_OUTPUT_32K | LSIO.GPIO1.IO03 | | | | | | +#define IOMUXD__SCU_BOOT_MODE0 REG32(IOMUXD_REG_BASE+0x00003180U) // 3 0 3 6 | SCU.DSC.BOOT_MODE0 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE1 REG32(IOMUXD_REG_BASE+0x000031C0U) // 3 0 3 7 | SCU.DSC.BOOT_MODE1 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE2 REG32(IOMUXD_REG_BASE+0x00003200U) // 3 0 3 8 | SCU.DSC.BOOT_MODE2 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE3 REG32(IOMUXD_REG_BASE+0x00003240U) // 3 0 3 9 | SCU.DSC.BOOT_MODE3 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE4 REG32(IOMUXD_REG_BASE+0x00003280U) // 3 0 3 10 | SCU.DSC.BOOT_MODE4 | SCU.PMIC_I2C.SCL | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE5 REG32(IOMUXD_REG_BASE+0x000032C0U) // 3 0 3 11 | SCU.DSC.BOOT_MODE5 | SCU.PMIC_I2C.SDA | | | | | | | | +#define IOMUXD__LVDS0_GPIO00 REG32(IOMUXD_REG_BASE+0x00004000U) // 4 0 4 0 | LVDS0.GPIO0.IO00 | LVDS0.PWM0.OUT | | LSIO.GPIO1.IO04 | | | | | | +#define IOMUXD__LVDS0_GPIO01 REG32(IOMUXD_REG_BASE+0x00004040U) // 4 0 4 1 | LVDS0.GPIO0.IO01 | | | LSIO.GPIO1.IO05 | | | | | | +#define IOMUXD__LVDS0_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00004080U) // 4 0 4 2 | LVDS0.I2C0.SCL | LVDS0.GPIO0.IO02 | | LSIO.GPIO1.IO06 | | | | | | +#define IOMUXD__LVDS0_I2C0_SDA REG32(IOMUXD_REG_BASE+0x000040C0U) // 4 0 4 3 | LVDS0.I2C0.SDA | LVDS0.GPIO0.IO03 | | LSIO.GPIO1.IO07 | | | | | | +#define IOMUXD__LVDS0_I2C1_SCL REG32(IOMUXD_REG_BASE+0x00004100U) // 4 0 4 4 | LVDS0.I2C1.SCL | DMA.UART2.TX | | LSIO.GPIO1.IO08 | | | | | | +#define IOMUXD__LVDS0_I2C1_SDA REG32(IOMUXD_REG_BASE+0x00004140U) // 4 0 4 5 | LVDS0.I2C1.SDA | DMA.UART2.RX | | LSIO.GPIO1.IO09 | | | | | | +#define IOMUXD__LVDS1_GPIO00 REG32(IOMUXD_REG_BASE+0x00004180U) // 4 0 4 6 | LVDS1.GPIO0.IO00 | LVDS1.PWM0.OUT | | LSIO.GPIO1.IO10 | | | | | | +#define IOMUXD__LVDS1_GPIO01 REG32(IOMUXD_REG_BASE+0x000041C0U) // 4 0 4 7 | LVDS1.GPIO0.IO01 | | | LSIO.GPIO1.IO11 | | | | | | +#define IOMUXD__LVDS1_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00004200U) // 4 0 4 8 | LVDS1.I2C0.SCL | LVDS1.GPIO0.IO02 | | LSIO.GPIO1.IO12 | | | | | | +#define IOMUXD__LVDS1_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00004240U) // 4 0 4 9 | LVDS1.I2C0.SDA | LVDS1.GPIO0.IO03 | | LSIO.GPIO1.IO13 | | | | | | +#define IOMUXD__LVDS1_I2C1_SCL REG32(IOMUXD_REG_BASE+0x00004280U) // 4 0 4 10 | LVDS1.I2C1.SCL | DMA.UART3.TX | | LSIO.GPIO1.IO14 | | | | | | +#define IOMUXD__LVDS1_I2C1_SDA REG32(IOMUXD_REG_BASE+0x000042C0U) // 4 0 4 11 | LVDS1.I2C1.SDA | DMA.UART3.RX | | LSIO.GPIO1.IO15 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO REG32(IOMUXD_REG_BASE+0x00004300U) // 4 0 4 12 | | | | | | | | | | +#define IOMUXD__MIPI_DSI0_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00020000U) // 5 1 0 0 | MIPI_DSI0.I2C0.SCL | | | LSIO.GPIO1.IO16 | | | | | | +#define IOMUXD__MIPI_DSI0_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00020040U) // 5 1 0 1 | MIPI_DSI0.I2C0.SDA | | | LSIO.GPIO1.IO17 | | | | | | +#define IOMUXD__MIPI_DSI0_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00020080U) // 5 1 0 2 | MIPI_DSI0.GPIO0.IO00 | MIPI_DSI0.PWM0.OUT | | LSIO.GPIO1.IO18 | | | | | | +#define IOMUXD__MIPI_DSI0_GPIO0_01 REG32(IOMUXD_REG_BASE+0x000200C0U) // 5 1 0 3 | MIPI_DSI0.GPIO0.IO01 | | | LSIO.GPIO1.IO19 | | | | | | +#define IOMUXD__MIPI_DSI1_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00020100U) // 5 1 0 4 | MIPI_DSI1.I2C0.SCL | | | LSIO.GPIO1.IO20 | | | | | | +#define IOMUXD__MIPI_DSI1_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00020140U) // 5 1 0 5 | MIPI_DSI1.I2C0.SDA | | | LSIO.GPIO1.IO21 | | | | | | +#define IOMUXD__MIPI_DSI1_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00020180U) // 5 1 0 6 | MIPI_DSI1.GPIO0.IO00 | MIPI_DSI1.PWM0.OUT | | LSIO.GPIO1.IO22 | | | | | | +#define IOMUXD__MIPI_DSI1_GPIO0_01 REG32(IOMUXD_REG_BASE+0x000201C0U) // 5 1 0 7 | MIPI_DSI1.GPIO0.IO01 | | | LSIO.GPIO1.IO23 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO REG32(IOMUXD_REG_BASE+0x00020200U) // 5 1 0 8 | | | | | | | | | | +#define IOMUXD__MIPI_CSI0_MCLK_OUT REG32(IOMUXD_REG_BASE+0x00021000U) // 6 1 1 0 | MIPI_CSI0.ACM.MCLK_OUT | | | LSIO.GPIO1.IO24 | | | | | | +#define IOMUXD__MIPI_CSI0_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00021040U) // 6 1 1 1 | MIPI_CSI0.I2C0.SCL | | | LSIO.GPIO1.IO25 | | | | | | +#define IOMUXD__MIPI_CSI0_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00021080U) // 6 1 1 2 | MIPI_CSI0.I2C0.SDA | | | LSIO.GPIO1.IO26 | | | | | | +#define IOMUXD__MIPI_CSI0_GPIO0_00 REG32(IOMUXD_REG_BASE+0x000210C0U) // 6 1 1 3 | MIPI_CSI0.GPIO0.IO00 | DMA.I2C0.SCL | MIPI_CSI1.I2C0.SCL | LSIO.GPIO1.IO27 | | | | | | +#define IOMUXD__MIPI_CSI0_GPIO0_01 REG32(IOMUXD_REG_BASE+0x00021100U) // 6 1 1 4 | MIPI_CSI0.GPIO0.IO01 | DMA.I2C0.SDA | MIPI_CSI1.I2C0.SDA | LSIO.GPIO1.IO28 | | | | | | +#define IOMUXD__MIPI_CSI1_MCLK_OUT REG32(IOMUXD_REG_BASE+0x00021140U) // 6 1 1 5 | MIPI_CSI1.ACM.MCLK_OUT | | | LSIO.GPIO1.IO29 | | | | | | +#define IOMUXD__MIPI_CSI1_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00021180U) // 6 1 1 6 | MIPI_CSI1.GPIO0.IO00 | DMA.UART4.RX | | LSIO.GPIO1.IO30 | | | | | | +#define IOMUXD__MIPI_CSI1_GPIO0_01 REG32(IOMUXD_REG_BASE+0x000211C0U) // 6 1 1 7 | MIPI_CSI1.GPIO0.IO01 | DMA.UART4.TX | | LSIO.GPIO1.IO31 | | | | | | +#define IOMUXD__MIPI_CSI1_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00021200U) // 6 1 1 8 | MIPI_CSI1.I2C0.SCL | | | LSIO.GPIO2.IO00 | | | | | | +#define IOMUXD__MIPI_CSI1_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00021240U) // 6 1 1 9 | MIPI_CSI1.I2C0.SDA | | | LSIO.GPIO2.IO01 | | | | | | +#define IOMUXD__HDMI_TX0_TS_SCL REG32(IOMUXD_REG_BASE+0x00021280U) // 6 1 1 10 | HDMI_TX0.I2C0.SCL | DMA.I2C0.SCL | | LSIO.GPIO2.IO02 | | | | | | +#define IOMUXD__HDMI_TX0_TS_SDA REG32(IOMUXD_REG_BASE+0x000212C0U) // 6 1 1 11 | HDMI_TX0.I2C0.SDA | DMA.I2C0.SDA | | LSIO.GPIO2.IO03 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO REG32(IOMUXD_REG_BASE+0x00021300U) // 6 1 1 12 | | | | | | | | | | +#define IOMUXD__ESAI1_FSR REG32(IOMUXD_REG_BASE+0x00022000U) // 7 1 2 0 | AUD.ESAI1.FSR | | | LSIO.GPIO2.IO04 | | | | | | +#define IOMUXD__ESAI1_FST REG32(IOMUXD_REG_BASE+0x00022040U) // 7 1 2 1 | AUD.ESAI1.FST | AUD.SPDIF0.EXT_CLK | | LSIO.GPIO2.IO05 | | | | | | +#define IOMUXD__ESAI1_SCKR REG32(IOMUXD_REG_BASE+0x00022080U) // 7 1 2 2 | AUD.ESAI1.SCKR | | | LSIO.GPIO2.IO06 | | | | | | +#define IOMUXD__ESAI1_SCKT REG32(IOMUXD_REG_BASE+0x000220C0U) // 7 1 2 3 | AUD.ESAI1.SCKT | AUD.SAI2.RXC | AUD.SPDIF0.EXT_CLK | LSIO.GPIO2.IO07 | | | | | | +#define IOMUXD__ESAI1_TX0 REG32(IOMUXD_REG_BASE+0x00022100U) // 7 1 2 4 | AUD.ESAI1.TX0 | AUD.SAI2.RXD | AUD.SPDIF0.RX | LSIO.GPIO2.IO08 | | | | | | +#define IOMUXD__ESAI1_TX1 REG32(IOMUXD_REG_BASE+0x00022140U) // 7 1 2 5 | AUD.ESAI1.TX1 | AUD.SAI2.RXFS | AUD.SPDIF0.TX | LSIO.GPIO2.IO09 | | | | | | +#define IOMUXD__ESAI1_TX2_RX3 REG32(IOMUXD_REG_BASE+0x00022180U) // 7 1 2 6 | AUD.ESAI1.TX2_RX3 | AUD.SPDIF0.RX | | LSIO.GPIO2.IO10 | | | | | | +#define IOMUXD__ESAI1_TX3_RX2 REG32(IOMUXD_REG_BASE+0x000221C0U) // 7 1 2 7 | AUD.ESAI1.TX3_RX2 | AUD.SPDIF0.TX | | LSIO.GPIO2.IO11 | | | | | | +#define IOMUXD__ESAI1_TX4_RX1 REG32(IOMUXD_REG_BASE+0x00022200U) // 7 1 2 8 | AUD.ESAI1.TX4_RX1 | | | LSIO.GPIO2.IO12 | | | | | | +#define IOMUXD__ESAI1_TX5_RX0 REG32(IOMUXD_REG_BASE+0x00022240U) // 7 1 2 9 | AUD.ESAI1.TX5_RX0 | | | LSIO.GPIO2.IO13 | | | | | | +#define IOMUXD__SPDIF0_RX REG32(IOMUXD_REG_BASE+0x00022280U) // 7 1 2 10 | AUD.SPDIF0.RX | AUD.MQS.R | AUD.ACM.MCLK_IN1 | LSIO.GPIO2.IO14 | | | | | | +#define IOMUXD__SPDIF0_TX REG32(IOMUXD_REG_BASE+0x000222C0U) // 7 1 2 11 | AUD.SPDIF0.TX | AUD.MQS.L | AUD.ACM.MCLK_OUT1 | LSIO.GPIO2.IO15 | | | | | | +#define IOMUXD__SPDIF0_EXT_CLK REG32(IOMUXD_REG_BASE+0x00022300U) // 7 1 2 12 | AUD.SPDIF0.EXT_CLK | DMA.DMA0.REQ_IN0 | | LSIO.GPIO2.IO16 | | | | | | +#define IOMUXD__SPI3_SCK REG32(IOMUXD_REG_BASE+0x00022340U) // 7 1 2 13 | DMA.SPI3.SCK | | | LSIO.GPIO2.IO17 | | | | | | +#define IOMUXD__SPI3_SDO REG32(IOMUXD_REG_BASE+0x00022380U) // 7 1 2 14 | DMA.SPI3.SDO | DMA.FTM.CH0 | | LSIO.GPIO2.IO18 | | | | | | +#define IOMUXD__SPI3_SDI REG32(IOMUXD_REG_BASE+0x00023000U) // 8 1 3 0 | DMA.SPI3.SDI | DMA.FTM.CH1 | | LSIO.GPIO2.IO19 | | | | | | +#define IOMUXD__SPI3_CS0 REG32(IOMUXD_REG_BASE+0x00023040U) // 8 1 3 1 | DMA.SPI3.CS0 | DMA.FTM.CH2 | | LSIO.GPIO2.IO20 | | | | | | +#define IOMUXD__SPI3_CS1 REG32(IOMUXD_REG_BASE+0x00023080U) // 8 1 3 2 | DMA.SPI3.CS1 | | | LSIO.GPIO2.IO21 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB REG32(IOMUXD_REG_BASE+0x000230C0U) // 8 1 3 3 | | | | | | | | | | +#define IOMUXD__ESAI0_FSR REG32(IOMUXD_REG_BASE+0x00023100U) // 8 1 3 4 | AUD.ESAI0.FSR | | | LSIO.GPIO2.IO22 | | | | | | +#define IOMUXD__ESAI0_FST REG32(IOMUXD_REG_BASE+0x00023140U) // 8 1 3 5 | AUD.ESAI0.FST | | | LSIO.GPIO2.IO23 | | | | | | +#define IOMUXD__ESAI0_SCKR REG32(IOMUXD_REG_BASE+0x00023180U) // 8 1 3 6 | AUD.ESAI0.SCKR | | | LSIO.GPIO2.IO24 | | | | | | +#define IOMUXD__ESAI0_SCKT REG32(IOMUXD_REG_BASE+0x000231C0U) // 8 1 3 7 | AUD.ESAI0.SCKT | | | LSIO.GPIO2.IO25 | | | | | | +#define IOMUXD__ESAI0_TX0 REG32(IOMUXD_REG_BASE+0x00023200U) // 8 1 3 8 | AUD.ESAI0.TX0 | | | LSIO.GPIO2.IO26 | | | | | | +#define IOMUXD__ESAI0_TX1 REG32(IOMUXD_REG_BASE+0x00023240U) // 8 1 3 9 | AUD.ESAI0.TX1 | | | LSIO.GPIO2.IO27 | | | | | | +#define IOMUXD__ESAI0_TX2_RX3 REG32(IOMUXD_REG_BASE+0x00023280U) // 8 1 3 10 | AUD.ESAI0.TX2_RX3 | | | LSIO.GPIO2.IO28 | | | | | | +#define IOMUXD__ESAI0_TX3_RX2 REG32(IOMUXD_REG_BASE+0x000232C0U) // 8 1 3 11 | AUD.ESAI0.TX3_RX2 | | | LSIO.GPIO2.IO29 | | | | | | +#define IOMUXD__ESAI0_TX4_RX1 REG32(IOMUXD_REG_BASE+0x00023300U) // 8 1 3 12 | AUD.ESAI0.TX4_RX1 | | | LSIO.GPIO2.IO30 | | | | | | +#define IOMUXD__ESAI0_TX5_RX0 REG32(IOMUXD_REG_BASE+0x00023340U) // 8 1 3 13 | AUD.ESAI0.TX5_RX0 | | | LSIO.GPIO2.IO31 | | | | | | +#define IOMUXD__MCLK_IN0 REG32(IOMUXD_REG_BASE+0x00023380U) // 8 1 3 14 | AUD.ACM.MCLK_IN0 | AUD.ESAI0.RX_HF_CLK | AUD.ESAI1.RX_HF_CLK | LSIO.GPIO3.IO00 | | | | | | +#define IOMUXD__MCLK_OUT0 REG32(IOMUXD_REG_BASE+0x00024000U) // 9 1 4 0 | AUD.ACM.MCLK_OUT0 | AUD.ESAI0.TX_HF_CLK | AUD.ESAI1.TX_HF_CLK | LSIO.GPIO3.IO01 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC REG32(IOMUXD_REG_BASE+0x00024040U) // 9 1 4 1 | | | | | | | | | | +#define IOMUXD__SPI0_SCK REG32(IOMUXD_REG_BASE+0x00024080U) // 9 1 4 2 | DMA.SPI0.SCK | AUD.SAI0.RXC | | LSIO.GPIO3.IO02 | | | | | | +#define IOMUXD__SPI0_SDO REG32(IOMUXD_REG_BASE+0x000240C0U) // 9 1 4 3 | DMA.SPI0.SDO | AUD.SAI0.TXD | | LSIO.GPIO3.IO03 | | | | | | +#define IOMUXD__SPI0_SDI REG32(IOMUXD_REG_BASE+0x00024100U) // 9 1 4 4 | DMA.SPI0.SDI | AUD.SAI0.RXD | | LSIO.GPIO3.IO04 | | | | | | +#define IOMUXD__SPI0_CS0 REG32(IOMUXD_REG_BASE+0x00024140U) // 9 1 4 5 | DMA.SPI0.CS0 | AUD.SAI0.RXFS | | LSIO.GPIO3.IO05 | | | | | | +#define IOMUXD__SPI0_CS1 REG32(IOMUXD_REG_BASE+0x00024180U) // 9 1 4 6 | DMA.SPI0.CS1 | AUD.SAI0.TXC | | LSIO.GPIO3.IO06 | | | | | | +#define IOMUXD__SPI2_SCK REG32(IOMUXD_REG_BASE+0x000241C0U) // 9 1 4 7 | DMA.SPI2.SCK | | | LSIO.GPIO3.IO07 | | | | | | +#define IOMUXD__SPI2_SDO REG32(IOMUXD_REG_BASE+0x00024200U) // 9 1 4 8 | DMA.SPI2.SDO | | | LSIO.GPIO3.IO08 | | | | | | +#define IOMUXD__SPI2_SDI REG32(IOMUXD_REG_BASE+0x00024240U) // 9 1 4 9 | DMA.SPI2.SDI | | | LSIO.GPIO3.IO09 | | | | | | +#define IOMUXD__SPI2_CS0 REG32(IOMUXD_REG_BASE+0x00024280U) // 9 1 4 10 | DMA.SPI2.CS0 | | | LSIO.GPIO3.IO10 | | | | | | +#define IOMUXD__SPI2_CS1 REG32(IOMUXD_REG_BASE+0x000242C0U) // 9 1 4 11 | DMA.SPI2.CS1 | AUD.SAI0.TXFS | | LSIO.GPIO3.IO11 | | | | | | +#define IOMUXD__SAI1_RXC REG32(IOMUXD_REG_BASE+0x00024300U) // 9 1 4 12 | AUD.SAI1.RXC | AUD.SAI0.TXD | | LSIO.GPIO3.IO12 | | | | | | +#define IOMUXD__SAI1_RXD REG32(IOMUXD_REG_BASE+0x00024340U) // 9 1 4 13 | AUD.SAI1.RXD | AUD.SAI0.TXFS | | LSIO.GPIO3.IO13 | | | | | | +#define IOMUXD__SAI1_RXFS REG32(IOMUXD_REG_BASE+0x00024380U) // 9 1 4 14 | AUD.SAI1.RXFS | AUD.SAI0.RXD | | LSIO.GPIO3.IO14 | | | | | | +#define IOMUXD__SAI1_TXC REG32(IOMUXD_REG_BASE+0x00025000U) // 10 1 5 0 | AUD.SAI1.TXC | AUD.SAI0.TXC | | LSIO.GPIO3.IO15 | | | | | | +#define IOMUXD__SAI1_TXD REG32(IOMUXD_REG_BASE+0x00025040U) // 10 1 5 1 | AUD.SAI1.TXD | AUD.SAI1.RXC | | LSIO.GPIO3.IO16 | | | | | | +#define IOMUXD__SAI1_TXFS REG32(IOMUXD_REG_BASE+0x00025080U) // 10 1 5 2 | AUD.SAI1.TXFS | AUD.SAI1.RXFS | | LSIO.GPIO3.IO17 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT REG32(IOMUXD_REG_BASE+0x000250C0U) // 10 1 5 3 | | | | | | | | | | +#define IOMUXD__ADC_IN7 REG32(IOMUXD_REG_BASE+0x00025100U) // 10 1 5 4 | DMA.ADC1.IN3 | DMA.SPI1.CS1 | LSIO.KPP0.ROW3 | LSIO.GPIO3.IO25 | | | | | | +#define IOMUXD__ADC_IN6 REG32(IOMUXD_REG_BASE+0x00025140U) // 10 1 5 5 | DMA.ADC1.IN2 | DMA.SPI1.CS0 | LSIO.KPP0.ROW2 | LSIO.GPIO3.IO24 | | | | | | +#define IOMUXD__ADC_IN5 REG32(IOMUXD_REG_BASE+0x00025180U) // 10 1 5 6 | DMA.ADC1.IN1 | DMA.SPI1.SDI | LSIO.KPP0.ROW1 | LSIO.GPIO3.IO23 | | | | | | +#define IOMUXD__ADC_IN4 REG32(IOMUXD_REG_BASE+0x000251C0U) // 10 1 5 7 | DMA.ADC1.IN0 | DMA.SPI1.SDO | LSIO.KPP0.ROW0 | LSIO.GPIO3.IO22 | | | | | | +#define IOMUXD__ADC_IN3 REG32(IOMUXD_REG_BASE+0x00025200U) // 10 1 5 8 | DMA.ADC0.IN3 | DMA.SPI1.SCK | LSIO.KPP0.COL3 | LSIO.GPIO3.IO21 | | | | | | +#define IOMUXD__ADC_IN2 REG32(IOMUXD_REG_BASE+0x00025240U) // 10 1 5 9 | DMA.ADC0.IN2 | | LSIO.KPP0.COL2 | LSIO.GPIO3.IO20 | | | | | | +#define IOMUXD__ADC_IN1 REG32(IOMUXD_REG_BASE+0x00025280U) // 10 1 5 10 | DMA.ADC0.IN1 | | LSIO.KPP0.COL1 | LSIO.GPIO3.IO19 | | | | | | +#define IOMUXD__ADC_IN0 REG32(IOMUXD_REG_BASE+0x000252C0U) // 10 1 5 11 | DMA.ADC0.IN0 | | LSIO.KPP0.COL0 | LSIO.GPIO3.IO18 | | | | | | +#define IOMUXD__MLB_SIG REG32(IOMUXD_REG_BASE+0x00040000U) // 11 2 0 0 | CONN.MLB.SIG | AUD.SAI3.RXC | | LSIO.GPIO3.IO26 | | | | | | +#define IOMUXD__MLB_CLK REG32(IOMUXD_REG_BASE+0x00040040U) // 11 2 0 1 | CONN.MLB.CLK | AUD.SAI3.RXFS | | LSIO.GPIO3.IO27 | | | | | | +#define IOMUXD__MLB_DATA REG32(IOMUXD_REG_BASE+0x00040080U) // 11 2 0 2 | CONN.MLB.DATA | AUD.SAI3.RXD | | LSIO.GPIO3.IO28 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT REG32(IOMUXD_REG_BASE+0x000400C0U) // 11 2 0 3 | | | | | | | | | | +#define IOMUXD__FLEXCAN0_RX REG32(IOMUXD_REG_BASE+0x00040100U) // 11 2 0 4 | DMA.FLEXCAN0.RX | | | LSIO.GPIO3.IO29 | | | | | | +#define IOMUXD__FLEXCAN0_TX REG32(IOMUXD_REG_BASE+0x00040140U) // 11 2 0 5 | DMA.FLEXCAN0.TX | | | LSIO.GPIO3.IO30 | | | | | | +#define IOMUXD__FLEXCAN1_RX REG32(IOMUXD_REG_BASE+0x00040180U) // 11 2 0 6 | DMA.FLEXCAN1.RX | | | LSIO.GPIO3.IO31 | | | | | | +#define IOMUXD__FLEXCAN1_TX REG32(IOMUXD_REG_BASE+0x000401C0U) // 11 2 0 7 | DMA.FLEXCAN1.TX | | | LSIO.GPIO4.IO00 | | | | | | +#define IOMUXD__FLEXCAN2_RX REG32(IOMUXD_REG_BASE+0x00040200U) // 11 2 0 8 | DMA.FLEXCAN2.RX | | | LSIO.GPIO4.IO01 | | | | | | +#define IOMUXD__FLEXCAN2_TX REG32(IOMUXD_REG_BASE+0x00040240U) // 11 2 0 9 | DMA.FLEXCAN2.TX | | | LSIO.GPIO4.IO02 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR REG32(IOMUXD_REG_BASE+0x00040280U) // 11 2 0 10 | | | | | | | | | | +#define IOMUXD__USB_SS3_TC0 REG32(IOMUXD_REG_BASE+0x000402C0U) // 11 2 0 11 | DMA.I2C1.SCL | CONN.USB_OTG1.PWR | | LSIO.GPIO4.IO03 | | | | | | +#define IOMUXD__USB_SS3_TC1 REG32(IOMUXD_REG_BASE+0x00040300U) // 11 2 0 12 | DMA.I2C1.SCL | CONN.USB_OTG2.PWR | | LSIO.GPIO4.IO04 | | | | | | +#define IOMUXD__USB_SS3_TC2 REG32(IOMUXD_REG_BASE+0x00040340U) // 11 2 0 13 | DMA.I2C1.SDA | CONN.USB_OTG1.OC | | LSIO.GPIO4.IO05 | | | | | | +#define IOMUXD__USB_SS3_TC3 REG32(IOMUXD_REG_BASE+0x00040380U) // 11 2 0 14 | DMA.I2C1.SDA | CONN.USB_OTG2.OC | | LSIO.GPIO4.IO06 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_3V3_USB3IO REG32(IOMUXD_REG_BASE+0x000403C0U) // 11 2 0 15 | | | | | | | | | | +#define IOMUXD__USDHC1_RESET_B REG32(IOMUXD_REG_BASE+0x00041000U) // 12 2 1 0 | CONN.USDHC1.RESET_B | | | LSIO.GPIO4.IO07 | | | | | | +#define IOMUXD__USDHC1_VSELECT REG32(IOMUXD_REG_BASE+0x00041040U) // 12 2 1 1 | CONN.USDHC1.VSELECT | | | LSIO.GPIO4.IO08 | | | | | | +#define IOMUXD__USDHC2_RESET_B REG32(IOMUXD_REG_BASE+0x00041080U) // 12 2 1 2 | CONN.USDHC2.RESET_B | | | LSIO.GPIO4.IO09 | | | | | | +#define IOMUXD__USDHC2_VSELECT REG32(IOMUXD_REG_BASE+0x000410C0U) // 12 2 1 3 | CONN.USDHC2.VSELECT | | | LSIO.GPIO4.IO10 | | | | | | +#define IOMUXD__USDHC2_WP REG32(IOMUXD_REG_BASE+0x00041100U) // 12 2 1 4 | CONN.USDHC2.WP | | | LSIO.GPIO4.IO11 | | | | | | +#define IOMUXD__USDHC2_CD_B REG32(IOMUXD_REG_BASE+0x00041140U) // 12 2 1 5 | CONN.USDHC2.CD_B | | | LSIO.GPIO4.IO12 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP REG32(IOMUXD_REG_BASE+0x00041180U) // 12 2 1 6 | | | | | | | | | | +#define IOMUXD__ENET0_MDIO REG32(IOMUXD_REG_BASE+0x000411C0U) // 12 2 1 7 | CONN.ENET0.MDIO | DMA.I2C4.SDA | | LSIO.GPIO4.IO13 | | | | | | +#define IOMUXD__ENET0_MDC REG32(IOMUXD_REG_BASE+0x00041200U) // 12 2 1 8 | CONN.ENET0.MDC | DMA.I2C4.SCL | | LSIO.GPIO4.IO14 | | | | | | +#define IOMUXD__ENET0_REFCLK_125M_25M REG32(IOMUXD_REG_BASE+0x00041240U) // 12 2 1 9 | CONN.ENET0.REFCLK_125M_25M | CONN.ENET0.PPS | | LSIO.GPIO4.IO15 | | | | | | +#define IOMUXD__ENET1_REFCLK_125M_25M REG32(IOMUXD_REG_BASE+0x00041280U) // 12 2 1 10 | CONN.ENET1.REFCLK_125M_25M | CONN.ENET1.PPS | | LSIO.GPIO4.IO16 | | | | | | +#define IOMUXD__ENET1_MDIO REG32(IOMUXD_REG_BASE+0x000412C0U) // 12 2 1 11 | CONN.ENET1.MDIO | DMA.I2C4.SDA | | LSIO.GPIO4.IO17 | | | | | | +#define IOMUXD__ENET1_MDC REG32(IOMUXD_REG_BASE+0x00041300U) // 12 2 1 12 | CONN.ENET1.MDC | DMA.I2C4.SCL | | LSIO.GPIO4.IO18 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT REG32(IOMUXD_REG_BASE+0x00041340U) // 12 2 1 13 | | | | | | | | | | +#define IOMUXD__QSPI1A_SS0_B REG32(IOMUXD_REG_BASE+0x00041380U) // 12 2 1 14 | LSIO.QSPI1A.SS0_B | | | LSIO.GPIO4.IO19 | | | | | | +#define IOMUXD__QSPI1A_SS1_B REG32(IOMUXD_REG_BASE+0x00042000U) // 13 2 2 0 | LSIO.QSPI1A.SS1_B | LSIO.QSPI1A.SCLK2 | | LSIO.GPIO4.IO20 | | | | | | +#define IOMUXD__QSPI1A_SCLK REG32(IOMUXD_REG_BASE+0x00042040U) // 13 2 2 1 | LSIO.QSPI1A.SCLK | | | LSIO.GPIO4.IO21 | | | | | | +#define IOMUXD__QSPI1A_DQS REG32(IOMUXD_REG_BASE+0x00042080U) // 13 2 2 2 | LSIO.QSPI1A.DQS | | | LSIO.GPIO4.IO22 | | | | | | +#define IOMUXD__QSPI1A_DATA3 REG32(IOMUXD_REG_BASE+0x000420C0U) // 13 2 2 3 | LSIO.QSPI1A.DATA3 | DMA.I2C1.SDA | CONN.USB_OTG1.OC | LSIO.GPIO4.IO23 | | | | | | +#define IOMUXD__QSPI1A_DATA2 REG32(IOMUXD_REG_BASE+0x00042100U) // 13 2 2 4 | LSIO.QSPI1A.DATA2 | DMA.I2C1.SCL | CONN.USB_OTG2.PWR | LSIO.GPIO4.IO24 | | | | | | +#define IOMUXD__QSPI1A_DATA1 REG32(IOMUXD_REG_BASE+0x00042140U) // 13 2 2 5 | LSIO.QSPI1A.DATA1 | DMA.I2C1.SDA | CONN.USB_OTG2.OC | LSIO.GPIO4.IO25 | | | | | | +#define IOMUXD__QSPI1A_DATA0 REG32(IOMUXD_REG_BASE+0x00042180U) // 13 2 2 6 | LSIO.QSPI1A.DATA0 | | | LSIO.GPIO4.IO26 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1 REG32(IOMUXD_REG_BASE+0x000421C0U) // 13 2 2 7 | | | | | | | | | | +#define IOMUXD__QSPI0A_DATA0 REG32(IOMUXD_REG_BASE+0x00043000U) // 14 2 3 0 | LSIO.QSPI0A.DATA0 | | | | | | | | | +#define IOMUXD__QSPI0A_DATA1 REG32(IOMUXD_REG_BASE+0x00043040U) // 14 2 3 1 | LSIO.QSPI0A.DATA1 | | | | | | | | | +#define IOMUXD__QSPI0A_DATA2 REG32(IOMUXD_REG_BASE+0x00043080U) // 14 2 3 2 | LSIO.QSPI0A.DATA2 | | | | | | | | | +#define IOMUXD__QSPI0A_DATA3 REG32(IOMUXD_REG_BASE+0x000430C0U) // 14 2 3 3 | LSIO.QSPI0A.DATA3 | | | | | | | | | +#define IOMUXD__QSPI0A_DQS REG32(IOMUXD_REG_BASE+0x00043100U) // 14 2 3 4 | LSIO.QSPI0A.DQS | | | | | | | | | +#define IOMUXD__QSPI0A_SS0_B REG32(IOMUXD_REG_BASE+0x00043140U) // 14 2 3 5 | LSIO.QSPI0A.SS0_B | | | | | | | | | +#define IOMUXD__QSPI0A_SS1_B REG32(IOMUXD_REG_BASE+0x00043180U) // 14 2 3 6 | LSIO.QSPI0A.SS1_B | LSIO.QSPI0A.SCLK2 | | | | | | | | +#define IOMUXD__QSPI0A_SCLK REG32(IOMUXD_REG_BASE+0x000431C0U) // 14 2 3 7 | LSIO.QSPI0A.SCLK | | | | | | | | | +#define IOMUXD__QSPI0B_SCLK REG32(IOMUXD_REG_BASE+0x00043200U) // 14 2 3 8 | LSIO.QSPI0B.SCLK | | | | | | | | | +#define IOMUXD__QSPI0B_DATA0 REG32(IOMUXD_REG_BASE+0x00043240U) // 14 2 3 9 | LSIO.QSPI0B.DATA0 | | | | | | | | | +#define IOMUXD__QSPI0B_DATA1 REG32(IOMUXD_REG_BASE+0x00043280U) // 14 2 3 10 | LSIO.QSPI0B.DATA1 | | | | | | | | | +#define IOMUXD__QSPI0B_DATA2 REG32(IOMUXD_REG_BASE+0x000432C0U) // 14 2 3 11 | LSIO.QSPI0B.DATA2 | | | | | | | | | +#define IOMUXD__QSPI0B_DATA3 REG32(IOMUXD_REG_BASE+0x00043300U) // 14 2 3 12 | LSIO.QSPI0B.DATA3 | | | | | | | | | +#define IOMUXD__QSPI0B_DQS REG32(IOMUXD_REG_BASE+0x00043340U) // 14 2 3 13 | LSIO.QSPI0B.DQS | | | | | | | | | +#define IOMUXD__QSPI0B_SS0_B REG32(IOMUXD_REG_BASE+0x00043380U) // 14 2 3 14 | LSIO.QSPI0B.SS0_B | | | | | | | | | +#define IOMUXD__QSPI0B_SS1_B REG32(IOMUXD_REG_BASE+0x00044000U) // 15 2 4 0 | LSIO.QSPI0B.SS1_B | LSIO.QSPI0B.SCLK2 | | | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0 REG32(IOMUXD_REG_BASE+0x00044040U) // 15 2 4 1 | | | | | | | | | | +#define IOMUXD__PCIE_CTRL0_CLKREQ_B REG32(IOMUXD_REG_BASE+0x00044080U) // 15 2 4 2 | HSIO.PCIE0.CLKREQ_B | | | LSIO.GPIO4.IO27 | | | | | | +#define IOMUXD__PCIE_CTRL0_WAKE_B REG32(IOMUXD_REG_BASE+0x000440C0U) // 15 2 4 3 | HSIO.PCIE0.WAKE_B | | | LSIO.GPIO4.IO28 | | | | | | +#define IOMUXD__PCIE_CTRL0_PERST_B REG32(IOMUXD_REG_BASE+0x00044100U) // 15 2 4 4 | HSIO.PCIE0.PERST_B | | | LSIO.GPIO4.IO29 | | | | | | +#define IOMUXD__PCIE_CTRL1_CLKREQ_B REG32(IOMUXD_REG_BASE+0x00044140U) // 15 2 4 5 | HSIO.PCIE1.CLKREQ_B | DMA.I2C1.SDA | CONN.USB_OTG2.OC | LSIO.GPIO4.IO30 | | | | | | +#define IOMUXD__PCIE_CTRL1_WAKE_B REG32(IOMUXD_REG_BASE+0x00044180U) // 15 2 4 6 | HSIO.PCIE1.WAKE_B | DMA.I2C1.SCL | CONN.USB_OTG2.PWR | LSIO.GPIO4.IO31 | | | | | | +#define IOMUXD__PCIE_CTRL1_PERST_B REG32(IOMUXD_REG_BASE+0x000441C0U) // 15 2 4 7 | HSIO.PCIE1.PERST_B | DMA.I2C1.SCL | CONN.USB_OTG1.PWR | LSIO.GPIO5.IO00 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP REG32(IOMUXD_REG_BASE+0x00044200U) // 15 2 4 8 | | | | | | | | | | +#define IOMUXD__USB_HSIC0_DATA REG32(IOMUXD_REG_BASE+0x00045000U) // 16 2 5 0 | CONN.USB_HSIC0.DATA | DMA.I2C1.SDA | | LSIO.GPIO5.IO01 | | | | | | +#define IOMUXD__USB_HSIC0_STROBE REG32(IOMUXD_REG_BASE+0x00045040U) // 16 2 5 1 | CONN.USB_HSIC0.STROBE | DMA.I2C1.SCL | | LSIO.GPIO5.IO02 | | | | | | +#define IOMUXD__IOMUXD_CALIBRATION_0_HSIC REG32(IOMUXD_REG_BASE+0x00045080U) // 16 2 5 2 | | | | | | | | | | +#define IOMUXD__IOMUXD_CALIBRATION_1_HSIC REG32(IOMUXD_REG_BASE+0x000450C0U) // 16 2 5 3 | | | | | | | | | | +#define IOMUXD__EMMC0_CLK REG32(IOMUXD_REG_BASE+0x00060000U) // 17 3 0 0 | CONN.EMMC0.CLK | CONN.NAND.READY_B | | | | | | | | +#define IOMUXD__EMMC0_CMD REG32(IOMUXD_REG_BASE+0x00060040U) // 17 3 0 1 | CONN.EMMC0.CMD | CONN.NAND.DQS | AUD.MQS.R | LSIO.GPIO5.IO03 | | | | | | +#define IOMUXD__EMMC0_DATA0 REG32(IOMUXD_REG_BASE+0x00060080U) // 17 3 0 2 | CONN.EMMC0.DATA0 | CONN.NAND.DATA00 | | LSIO.GPIO5.IO04 | | | | | | +#define IOMUXD__EMMC0_DATA1 REG32(IOMUXD_REG_BASE+0x000600C0U) // 17 3 0 3 | CONN.EMMC0.DATA1 | CONN.NAND.DATA01 | | LSIO.GPIO5.IO05 | | | | | | +#define IOMUXD__EMMC0_DATA2 REG32(IOMUXD_REG_BASE+0x00060100U) // 17 3 0 4 | CONN.EMMC0.DATA2 | CONN.NAND.DATA02 | | LSIO.GPIO5.IO06 | | | | | | +#define IOMUXD__EMMC0_DATA3 REG32(IOMUXD_REG_BASE+0x00060140U) // 17 3 0 5 | CONN.EMMC0.DATA3 | CONN.NAND.DATA03 | | LSIO.GPIO5.IO07 | | | | | | +#define IOMUXD__EMMC0_DATA4 REG32(IOMUXD_REG_BASE+0x00060180U) // 17 3 0 6 | CONN.EMMC0.DATA4 | CONN.NAND.DATA04 | | LSIO.GPIO5.IO08 | | | | | | +#define IOMUXD__EMMC0_DATA5 REG32(IOMUXD_REG_BASE+0x000601C0U) // 17 3 0 7 | CONN.EMMC0.DATA5 | CONN.NAND.DATA05 | | LSIO.GPIO5.IO09 | | | | | | +#define IOMUXD__EMMC0_DATA6 REG32(IOMUXD_REG_BASE+0x00060200U) // 17 3 0 8 | CONN.EMMC0.DATA6 | CONN.NAND.DATA06 | | LSIO.GPIO5.IO10 | | | | | | +#define IOMUXD__EMMC0_DATA7 REG32(IOMUXD_REG_BASE+0x00060240U) // 17 3 0 9 | CONN.EMMC0.DATA7 | CONN.NAND.DATA07 | | LSIO.GPIO5.IO11 | | | | | | +#define IOMUXD__EMMC0_STROBE REG32(IOMUXD_REG_BASE+0x00060280U) // 17 3 0 10 | CONN.EMMC0.STROBE | CONN.NAND.CLE | | LSIO.GPIO5.IO12 | | | | | | +#define IOMUXD__EMMC0_RESET_B REG32(IOMUXD_REG_BASE+0x000602C0U) // 17 3 0 11 | CONN.EMMC0.RESET_B | CONN.NAND.WP_B | CONN.USDHC1.VSELECT | LSIO.GPIO5.IO13 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX REG32(IOMUXD_REG_BASE+0x00060300U) // 17 3 0 12 | | | | | | | | | | +#define IOMUXD__USDHC1_CLK REG32(IOMUXD_REG_BASE+0x00060340U) // 17 3 0 13 | CONN.USDHC1.CLK | AUD.MQS.R | | | | | | | | +#define IOMUXD__USDHC1_CMD REG32(IOMUXD_REG_BASE+0x00060380U) // 17 3 0 14 | CONN.USDHC1.CMD | AUD.MQS.L | | LSIO.GPIO5.IO14 | | | | | | +#define IOMUXD__USDHC1_DATA0 REG32(IOMUXD_REG_BASE+0x000603C0U) // 17 3 0 15 | CONN.USDHC1.DATA0 | CONN.NAND.RE_N | | LSIO.GPIO5.IO15 | | | | | | +#define IOMUXD__USDHC1_DATA1 REG32(IOMUXD_REG_BASE+0x00061000U) // 18 3 1 0 | CONN.USDHC1.DATA1 | CONN.NAND.RE_P | | LSIO.GPIO5.IO16 | | | | | | +#define IOMUXD__IOMUXD_CTL_NAND_RE_P_N REG32(IOMUXD_REG_BASE+0x00061040U) // 18 3 1 1 | | | | | | | | | | +#define IOMUXD__USDHC1_DATA2 REG32(IOMUXD_REG_BASE+0x00061080U) // 18 3 1 2 | CONN.USDHC1.DATA2 | CONN.NAND.DQS_N | | LSIO.GPIO5.IO17 | | | | | | +#define IOMUXD__USDHC1_DATA3 REG32(IOMUXD_REG_BASE+0x000610C0U) // 18 3 1 3 | CONN.USDHC1.DATA3 | CONN.NAND.DQS_P | | LSIO.GPIO5.IO18 | | | | | | +#define IOMUXD__IOMUXD_CTL_NAND_DQS_P_N REG32(IOMUXD_REG_BASE+0x00061100U) // 18 3 1 4 | | | | | | | | | | +#define IOMUXD__USDHC1_DATA4 REG32(IOMUXD_REG_BASE+0x00061140U) // 18 3 1 5 | CONN.USDHC1.DATA4 | CONN.NAND.CE0_B | AUD.MQS.R | LSIO.GPIO5.IO19 | | | | | | +#define IOMUXD__USDHC1_DATA5 REG32(IOMUXD_REG_BASE+0x00061180U) // 18 3 1 6 | CONN.USDHC1.DATA5 | CONN.NAND.RE_B | AUD.MQS.L | LSIO.GPIO5.IO20 | | | | | | +#define IOMUXD__USDHC1_DATA6 REG32(IOMUXD_REG_BASE+0x000611C0U) // 18 3 1 7 | CONN.USDHC1.DATA6 | CONN.NAND.WE_B | CONN.USDHC1.WP | LSIO.GPIO5.IO21 | | | | | | +#define IOMUXD__USDHC1_DATA7 REG32(IOMUXD_REG_BASE+0x00061200U) // 18 3 1 8 | CONN.USDHC1.DATA7 | CONN.NAND.ALE | CONN.USDHC1.CD_B | LSIO.GPIO5.IO22 | | | | | | +#define IOMUXD__USDHC1_STROBE REG32(IOMUXD_REG_BASE+0x00061240U) // 18 3 1 9 | CONN.USDHC1.STROBE | CONN.NAND.CE1_B | CONN.USDHC1.RESET_B | LSIO.GPIO5.IO23 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2 REG32(IOMUXD_REG_BASE+0x00061280U) // 18 3 1 10 | | | | | | | | | | +#define IOMUXD__USDHC2_CLK REG32(IOMUXD_REG_BASE+0x000612C0U) // 18 3 1 11 | CONN.USDHC2.CLK | AUD.MQS.R | | LSIO.GPIO5.IO24 | | | | | | +#define IOMUXD__USDHC2_CMD REG32(IOMUXD_REG_BASE+0x00061300U) // 18 3 1 12 | CONN.USDHC2.CMD | AUD.MQS.L | | LSIO.GPIO5.IO25 | | | | | | +#define IOMUXD__USDHC2_DATA0 REG32(IOMUXD_REG_BASE+0x00061340U) // 18 3 1 13 | CONN.USDHC2.DATA0 | DMA.UART4.RX | | LSIO.GPIO5.IO26 | | | | | | +#define IOMUXD__USDHC2_DATA1 REG32(IOMUXD_REG_BASE+0x00061380U) // 18 3 1 14 | CONN.USDHC2.DATA1 | DMA.UART4.TX | | LSIO.GPIO5.IO27 | | | | | | +#define IOMUXD__USDHC2_DATA2 REG32(IOMUXD_REG_BASE+0x000613C0U) // 18 3 1 15 | CONN.USDHC2.DATA2 | DMA.UART4.CTS_B | | LSIO.GPIO5.IO28 | | | | | | +#define IOMUXD__USDHC2_DATA3 REG32(IOMUXD_REG_BASE+0x00062000U) // 19 3 2 0 | CONN.USDHC2.DATA3 | DMA.UART4.RTS_B | | LSIO.GPIO5.IO29 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 REG32(IOMUXD_REG_BASE+0x00062040U) // 19 3 2 1 | | | | | | | | | | +#define IOMUXD__ENET0_RGMII_TXC REG32(IOMUXD_REG_BASE+0x00062080U) // 19 3 2 2 | CONN.ENET0.RGMII_TXC | CONN.ENET0.RCLK50M_OUT | CONN.ENET0.RCLK50M_IN | LSIO.GPIO5.IO30 | | | | | | +#define IOMUXD__ENET0_RGMII_TX_CTL REG32(IOMUXD_REG_BASE+0x000620C0U) // 19 3 2 3 | CONN.ENET0.RGMII_TX_CTL | | | LSIO.GPIO5.IO31 | | | | | | +#define IOMUXD__ENET0_RGMII_TXD0 REG32(IOMUXD_REG_BASE+0x00062100U) // 19 3 2 4 | CONN.ENET0.RGMII_TXD0 | | | LSIO.GPIO6.IO00 | | | | | | +#define IOMUXD__ENET0_RGMII_TXD1 REG32(IOMUXD_REG_BASE+0x00062140U) // 19 3 2 5 | CONN.ENET0.RGMII_TXD1 | | | LSIO.GPIO6.IO01 | | | | | | +#define IOMUXD__ENET0_RGMII_TXD2 REG32(IOMUXD_REG_BASE+0x00062180U) // 19 3 2 6 | CONN.ENET0.RGMII_TXD2 | DMA.UART3.TX | VPU.TSI_S1.VID | LSIO.GPIO6.IO02 | | | | | | +#define IOMUXD__ENET0_RGMII_TXD3 REG32(IOMUXD_REG_BASE+0x000621C0U) // 19 3 2 7 | CONN.ENET0.RGMII_TXD3 | DMA.UART3.RTS_B | VPU.TSI_S1.SYNC | LSIO.GPIO6.IO03 | | | | | | +#define IOMUXD__ENET0_RGMII_RXC REG32(IOMUXD_REG_BASE+0x00062200U) // 19 3 2 8 | CONN.ENET0.RGMII_RXC | DMA.UART3.CTS_B | VPU.TSI_S1.DATA | LSIO.GPIO6.IO04 | | | | | | +#define IOMUXD__ENET0_RGMII_RX_CTL REG32(IOMUXD_REG_BASE+0x00062240U) // 19 3 2 9 | CONN.ENET0.RGMII_RX_CTL | | VPU.TSI_S0.VID | LSIO.GPIO6.IO05 | | | | | | +#define IOMUXD__ENET0_RGMII_RXD0 REG32(IOMUXD_REG_BASE+0x00062280U) // 19 3 2 10 | CONN.ENET0.RGMII_RXD0 | | VPU.TSI_S0.SYNC | LSIO.GPIO6.IO06 | | | | | | +#define IOMUXD__ENET0_RGMII_RXD1 REG32(IOMUXD_REG_BASE+0x000622C0U) // 19 3 2 11 | CONN.ENET0.RGMII_RXD1 | | VPU.TSI_S0.DATA | LSIO.GPIO6.IO07 | | | | | | +#define IOMUXD__ENET0_RGMII_RXD2 REG32(IOMUXD_REG_BASE+0x00062300U) // 19 3 2 12 | CONN.ENET0.RGMII_RXD2 | CONN.ENET0.RMII_RX_ER | VPU.TSI_S0.CLK | LSIO.GPIO6.IO08 | | | | | | +#define IOMUXD__ENET0_RGMII_RXD3 REG32(IOMUXD_REG_BASE+0x00062340U) // 19 3 2 13 | CONN.ENET0.RGMII_RXD3 | DMA.UART3.RX | VPU.TSI_S1.CLK | LSIO.GPIO6.IO09 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB REG32(IOMUXD_REG_BASE+0x00062380U) // 19 3 2 14 | | | | | | | | | | +#define IOMUXD__ENET1_RGMII_TXC REG32(IOMUXD_REG_BASE+0x000623C0U) // 19 3 2 15 | CONN.ENET1.RGMII_TXC | CONN.ENET1.RCLK50M_OUT | CONN.ENET1.RCLK50M_IN | LSIO.GPIO6.IO10 | | | | | | +#define IOMUXD__ENET1_RGMII_TX_CTL REG32(IOMUXD_REG_BASE+0x00063000U) // 20 3 3 0 | CONN.ENET1.RGMII_TX_CTL | | | LSIO.GPIO6.IO11 | | | | | | +#define IOMUXD__ENET1_RGMII_TXD0 REG32(IOMUXD_REG_BASE+0x00063040U) // 20 3 3 1 | CONN.ENET1.RGMII_TXD0 | | | LSIO.GPIO6.IO12 | | | | | | +#define IOMUXD__ENET1_RGMII_TXD1 REG32(IOMUXD_REG_BASE+0x00063080U) // 20 3 3 2 | CONN.ENET1.RGMII_TXD1 | | | LSIO.GPIO6.IO13 | | | | | | +#define IOMUXD__ENET1_RGMII_TXD2 REG32(IOMUXD_REG_BASE+0x000630C0U) // 20 3 3 3 | CONN.ENET1.RGMII_TXD2 | DMA.UART3.TX | VPU.TSI_S1.VID | LSIO.GPIO6.IO14 | | | | | | +#define IOMUXD__ENET1_RGMII_TXD3 REG32(IOMUXD_REG_BASE+0x00063100U) // 20 3 3 4 | CONN.ENET1.RGMII_TXD3 | DMA.UART3.RTS_B | VPU.TSI_S1.SYNC | LSIO.GPIO6.IO15 | | | | | | +#define IOMUXD__ENET1_RGMII_RXC REG32(IOMUXD_REG_BASE+0x00063140U) // 20 3 3 5 | CONN.ENET1.RGMII_RXC | DMA.UART3.CTS_B | VPU.TSI_S1.DATA | LSIO.GPIO6.IO16 | | | | | | +#define IOMUXD__ENET1_RGMII_RX_CTL REG32(IOMUXD_REG_BASE+0x00063180U) // 20 3 3 6 | CONN.ENET1.RGMII_RX_CTL | | VPU.TSI_S0.VID | LSIO.GPIO6.IO17 | | | | | | +#define IOMUXD__ENET1_RGMII_RXD0 REG32(IOMUXD_REG_BASE+0x000631C0U) // 20 3 3 7 | CONN.ENET1.RGMII_RXD0 | | VPU.TSI_S0.SYNC | LSIO.GPIO6.IO18 | | | | | | +#define IOMUXD__ENET1_RGMII_RXD1 REG32(IOMUXD_REG_BASE+0x00063200U) // 20 3 3 8 | CONN.ENET1.RGMII_RXD1 | | VPU.TSI_S0.DATA | LSIO.GPIO6.IO19 | | | | | | +#define IOMUXD__ENET1_RGMII_RXD2 REG32(IOMUXD_REG_BASE+0x00063240U) // 20 3 3 9 | CONN.ENET1.RGMII_RXD2 | CONN.ENET1.RMII_RX_ER | VPU.TSI_S0.CLK | LSIO.GPIO6.IO20 | | | | | | +#define IOMUXD__ENET1_RGMII_RXD3 REG32(IOMUXD_REG_BASE+0x00063280U) // 20 3 3 10 | CONN.ENET1.RGMII_RXD3 | DMA.UART3.RX | VPU.TSI_S1.CLK | LSIO.GPIO6.IO21 | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA REG32(IOMUXD_REG_BASE+0x000632C0U) // 20 3 3 11 | | | | | | | | | | + +// GROUP REGISTERS FOR WAKEUP CONTROL +#define IOMUXD__GROUP_0_0 REG32(IOMUXD_REG_BASE+0x00000400U) // 0 0 0 0 | +#define IOMUXD__GROUP_0_1 REG32(IOMUXD_REG_BASE+0x00001400U) // 1 0 1 0 | +#define IOMUXD__GROUP_0_2 REG32(IOMUXD_REG_BASE+0x00002400U) // 2 0 2 0 | +#define IOMUXD__GROUP_0_3 REG32(IOMUXD_REG_BASE+0x00003400U) // 3 0 3 0 | +#define IOMUXD__GROUP_0_4 REG32(IOMUXD_REG_BASE+0x00004400U) // 4 0 4 0 | +#define IOMUXD__GROUP_1_0 REG32(IOMUXD_REG_BASE+0x00020400U) // 5 1 0 0 | +#define IOMUXD__GROUP_1_1 REG32(IOMUXD_REG_BASE+0x00021400U) // 6 1 1 0 | +#define IOMUXD__GROUP_1_2 REG32(IOMUXD_REG_BASE+0x00022400U) // 7 1 2 0 | +#define IOMUXD__GROUP_1_3 REG32(IOMUXD_REG_BASE+0x00023400U) // 8 1 3 0 | +#define IOMUXD__GROUP_1_4 REG32(IOMUXD_REG_BASE+0x00024400U) // 9 1 4 0 | +#define IOMUXD__GROUP_1_5 REG32(IOMUXD_REG_BASE+0x00025400U) // 10 1 5 0 | +#define IOMUXD__GROUP_2_0 REG32(IOMUXD_REG_BASE+0x00040400U) // 11 2 0 0 | +#define IOMUXD__GROUP_2_1 REG32(IOMUXD_REG_BASE+0x00041400U) // 12 2 1 0 | +#define IOMUXD__GROUP_2_2 REG32(IOMUXD_REG_BASE+0x00042400U) // 13 2 2 0 | +#define IOMUXD__GROUP_2_3 REG32(IOMUXD_REG_BASE+0x00043400U) // 14 2 3 0 | +#define IOMUXD__GROUP_2_4 REG32(IOMUXD_REG_BASE+0x00044400U) // 15 2 4 0 | +#define IOMUXD__GROUP_2_5 REG32(IOMUXD_REG_BASE+0x00045400U) // 16 2 5 0 | +#define IOMUXD__GROUP_3_0 REG32(IOMUXD_REG_BASE+0x00060400U) // 17 3 0 0 | +#define IOMUXD__GROUP_3_1 REG32(IOMUXD_REG_BASE+0x00061400U) // 18 3 1 0 | +#define IOMUXD__GROUP_3_2 REG32(IOMUXD_REG_BASE+0x00062400U) // 19 3 2 0 | +#define IOMUXD__GROUP_3_3 REG32(IOMUXD_REG_BASE+0x00063400U) // 20 3 3 0 | + +#endif + diff --git a/platform/config/mx8qm/lpcg.h b/platform/config/mx8qm/lpcg.h new file mode 100755 index 0000000..d0e0a18 --- /dev/null +++ b/platform/config/mx8qm/lpcg.h @@ -0,0 +1,148 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef LPCG_H +#define LPCG_H + +// NOTE: Content below comes from cprog file of the SCU design database + +// LPCG______REG +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__REG 0x0000 // IPS_SLOT=CLK_SECO +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__BIT 0 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__STOP 3 + +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__REG 0x0004 // IPS_SLOT=CLK_SECO +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__BIT 0 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__HWEN 0 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__SWEN 1 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__RSVD 2 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__STOP 3 + +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__REG 0x0000 // IPS_SLOT=CLK_MMCAU_HCLK +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__BIT 0 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__STOP 3 + +#define LPCG__SS_SCU__CM4__TCMC_HCLK__REG 0x0000 // IPS_SLOT=CLK_TCMC_HCLK +#define LPCG__SS_SCU__CM4__TCMC_HCLK__BIT 0 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__STOP 3 + +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__BIT 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__HWEN 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__SWEN 1 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__RSVD 2 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__STOP 3 + +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__BIT 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__HWEN 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__SWEN 1 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__RSVD 2 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__STOP 3 + +#define LPCG__SS_SCU__LPIT1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__BIT 0 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__HWEN 0 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__SWEN 1 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__RSVD 2 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__STOP 3 + +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__BIT 0 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__HWEN 0 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__SWEN 1 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__RSVD 2 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__STOP 3 + +#define LPCG__SS_SCU__LPUART1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__BIT 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__HWEN 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__SWEN 1 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__RSVD 2 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__STOP 3 + +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__BIT 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__HWEN 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__SWEN 1 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__RSVD 2 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__STOP 3 + +#define LPCG__SS_SCU__TPM1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_TPM +#define LPCG__SS_SCU__TPM1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__TPM1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__TPM1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__TPM1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__TPM1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__REG 0x0000 // IPS_SLOT=CLK_TPM +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__BIT 0 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__HWEN 0 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__SWEN 1 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__RSVD 2 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__STOP 3 + +#endif + diff --git a/platform/config/mx8qm/pad_data.h b/platform/config/mx8qm/pad_data.h new file mode 100644 index 0000000..bb36565 --- /dev/null +++ b/platform/config/mx8qm/pad_data.h @@ -0,0 +1,643 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to map pads and print debug output. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/pad_data_h.pl */ + +#ifndef SC_PAD_DATA_H +#define SC_PAD_DATA_H + +/* Defines */ + +/*! + * This define is used to initialize the pad mapping array. + */ +#define SC_SVC_PAD_INIT \ + U16((IOMUXD__SIM0_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SIM0_RST >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SIM0_IO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SIM0_PD >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SIM0_POWER_EN >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SIM0_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SIM >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M40_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M40_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M40_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M40_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M41_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M41_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M41_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__M41_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__GPT0_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__GPT0_CAPTURE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__GPT0_COMPARE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__GPT1_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__GPT1_CAPTURE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__GPT1_COMPARE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART0_RX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART0_TX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART0_RTS_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART0_CTS_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART1_TX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART1_RX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART1_RTS_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__UART1_CTS_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_PMIC_MEMC_ON >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_WDOG_OUT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PMIC_I2C_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PMIC_I2C_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PMIC_EARLY_WARNING >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PMIC_INT_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_02 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_03 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_04 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_05 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_06 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_GPIO0_07 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_BOOT_MODE0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_BOOT_MODE1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_BOOT_MODE2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_BOOT_MODE3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_BOOT_MODE4 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SCU_BOOT_MODE5 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS0_GPIO00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS0_GPIO01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS0_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS0_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS0_I2C1_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS0_I2C1_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS1_GPIO00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS1_GPIO01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS1_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS1_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS1_I2C1_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__LVDS1_I2C1_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI0_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI0_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI0_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI0_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI1_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI1_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI1_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_DSI1_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI0_MCLK_OUT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI0_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI0_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI0_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI0_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI1_MCLK_OUT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI1_GPIO0_00 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI1_GPIO0_01 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI1_I2C0_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MIPI_CSI1_I2C0_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__HDMI_TX0_TS_SCL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__HDMI_TX0_TS_SDA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_3V3_HDMIGPIO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_FSR >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_FST >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_SCKR >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_SCKT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_TX0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_TX1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_TX2_RX3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_TX3_RX2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_TX4_RX1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI1_TX5_RX0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPDIF0_RX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPDIF0_TX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPDIF0_EXT_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI3_SCK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI3_SDO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI3_SDI >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI3_CS0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI3_CS1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_FSR >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_FST >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_SCKR >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_SCKT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_TX0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_TX1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_TX2_RX3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_TX3_RX2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_TX4_RX1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ESAI0_TX5_RX0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MCLK_IN0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MCLK_OUT0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI0_SCK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI0_SDO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI0_SDI >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI0_CS0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI0_CS1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI2_SCK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI2_SDO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI2_SDI >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI2_CS0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SPI2_CS1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SAI1_RXC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SAI1_RXD >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SAI1_RXFS >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SAI1_TXC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SAI1_TXD >> 4U) & 0xFFFFU), \ + U16((IOMUXD__SAI1_TXFS >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN7 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN6 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN5 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN4 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ADC_IN0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MLB_SIG >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MLB_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__MLB_DATA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLHT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__FLEXCAN0_RX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__FLEXCAN0_TX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__FLEXCAN1_RX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__FLEXCAN1_TX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__FLEXCAN2_RX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__FLEXCAN2_TX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOTHR >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USB_SS3_TC0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USB_SS3_TC1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USB_SS3_TC2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USB_SS3_TC3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_3V3_USB3IO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_RESET_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_VSELECT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_RESET_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_VSELECT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_WP >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_CD_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_MDIO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_MDC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_REFCLK_125M_25M >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_REFCLK_125M_25M >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_MDIO >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_MDC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_SS0_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_SS1_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_SCLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_DQS >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_DATA3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_DATA2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_DATA1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI1A_DATA0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_DATA0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_DATA1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_DATA2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_DATA3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_DQS >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_SS0_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_SS1_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0A_SCLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_SCLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_DATA0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_DATA1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_DATA2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_DATA3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_DQS >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_SS0_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__QSPI0B_SS1_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PCIE_CTRL0_CLKREQ_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PCIE_CTRL0_WAKE_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PCIE_CTRL0_PERST_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PCIE_CTRL1_CLKREQ_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PCIE_CTRL1_WAKE_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__PCIE_CTRL1_PERST_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USB_HSIC0_DATA >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USB_HSIC0_STROBE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_CALIBRATION_0_HSIC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_CALIBRATION_1_HSIC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_CMD >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA4 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA5 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA6 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_DATA7 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_STROBE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__EMMC0_RESET_B >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_CMD >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_CTL_NAND_RE_P_N >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_CTL_NAND_DQS_P_N >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA4 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA5 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA6 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_DATA7 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC1_STROBE >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_CLK >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_CMD >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_DATA0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_DATA1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_DATA2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__USDHC2_DATA3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_TXC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_TX_CTL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_TXD0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_TXD1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_TXD2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_TXD3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_RXC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_RX_CTL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_RXD0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_RXD1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_RXD2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET0_RGMII_RXD3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_TXC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_TX_CTL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_TXD0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_TXD1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_TXD2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_TXD3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_RXC >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_RX_CTL >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_RXD0 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_RXD1 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_RXD2 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__ENET1_RGMII_RXD3 >> 4U) & 0xFFFFU), \ + U16((IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA >> 4U) & 0xFFFFU) + +/*! + * This define is used indicate the number of pads. + */ +#define SC_NUM_PAD 269U + +/*! + * This define is used to indicate the bit width required to contain a pad. + */ +#define SC_PAD_W 9 + +/*! + * This define is used to initialize the pad group array. + */ +#define SC_SVC_PAD_IRQ_INIT \ + SC_P_SIM0_CLK, \ + SC_P_GPT0_CLK, \ + SC_P_SCU_WDOG_OUT, \ + SC_P_SCU_GPIO0_02, \ + SC_P_LVDS0_GPIO00, \ + SC_P_MIPI_DSI0_I2C0_SCL, \ + SC_P_MIPI_CSI0_MCLK_OUT, \ + SC_P_ESAI1_FSR, \ + SC_P_SPI3_SDI, \ + SC_P_MCLK_OUT0, \ + SC_P_SAI1_TXC, \ + SC_P_MLB_SIG, \ + SC_P_USDHC1_RESET_B, \ + SC_P_QSPI1A_SS1_B, \ + SC_P_QSPI0A_DATA0, \ + SC_P_QSPI0B_SS1_B, \ + SC_P_USB_HSIC0_DATA, \ + SC_P_EMMC0_CLK, \ + SC_P_USDHC1_DATA1, \ + SC_P_USDHC2_DATA3, \ + SC_P_ENET1_RGMII_TX_CTL + +/*! + * This define is used indicate the number of pad interrupts. + */ +#define SC_NUM_PAD_IRQS 21U + +/*! + * This define is used to initialize the pad debug output array. + */ +#ifdef DEBUG + #define PNAME_INIT \ + "SIM0_CLK", \ + "SIM0_RST", \ + "SIM0_IO", \ + "SIM0_PD", \ + "SIM0_POWER_EN", \ + "SIM0_GPIO0_00", \ + "COMP_CTL_GPIO_1V8_3V3_SIM", \ + "M40_I2C0_SCL", \ + "M40_I2C0_SDA", \ + "M40_GPIO0_00", \ + "M40_GPIO0_01", \ + "M41_I2C0_SCL", \ + "M41_I2C0_SDA", \ + "M41_GPIO0_00", \ + "M41_GPIO0_01", \ + "GPT0_CLK", \ + "GPT0_CAPTURE", \ + "GPT0_COMPARE", \ + "GPT1_CLK", \ + "GPT1_CAPTURE", \ + "GPT1_COMPARE", \ + "UART0_RX", \ + "UART0_TX", \ + "UART0_RTS_B", \ + "UART0_CTS_B", \ + "UART1_TX", \ + "UART1_RX", \ + "UART1_RTS_B", \ + "UART1_CTS_B", \ + "COMP_CTL_GPIO_1V8_3V3_GPIOLH", \ + "SCU_PMIC_MEMC_ON", \ + "SCU_WDOG_OUT", \ + "PMIC_I2C_SDA", \ + "PMIC_I2C_SCL", \ + "PMIC_EARLY_WARNING", \ + "PMIC_INT_B", \ + "SCU_GPIO0_00", \ + "SCU_GPIO0_01", \ + "SCU_GPIO0_02", \ + "SCU_GPIO0_03", \ + "SCU_GPIO0_04", \ + "SCU_GPIO0_05", \ + "SCU_GPIO0_06", \ + "SCU_GPIO0_07", \ + "SCU_BOOT_MODE0", \ + "SCU_BOOT_MODE1", \ + "SCU_BOOT_MODE2", \ + "SCU_BOOT_MODE3", \ + "SCU_BOOT_MODE4", \ + "SCU_BOOT_MODE5", \ + "LVDS0_GPIO00", \ + "LVDS0_GPIO01", \ + "LVDS0_I2C0_SCL", \ + "LVDS0_I2C0_SDA", \ + "LVDS0_I2C1_SCL", \ + "LVDS0_I2C1_SDA", \ + "LVDS1_GPIO00", \ + "LVDS1_GPIO01", \ + "LVDS1_I2C0_SCL", \ + "LVDS1_I2C0_SDA", \ + "LVDS1_I2C1_SCL", \ + "LVDS1_I2C1_SDA", \ + "COMP_CTL_GPIO_1V8_3V3_LVDSGPIO", \ + "MIPI_DSI0_I2C0_SCL", \ + "MIPI_DSI0_I2C0_SDA", \ + "MIPI_DSI0_GPIO0_00", \ + "MIPI_DSI0_GPIO0_01", \ + "MIPI_DSI1_I2C0_SCL", \ + "MIPI_DSI1_I2C0_SDA", \ + "MIPI_DSI1_GPIO0_00", \ + "MIPI_DSI1_GPIO0_01", \ + "COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO", \ + "MIPI_CSI0_MCLK_OUT", \ + "MIPI_CSI0_I2C0_SCL", \ + "MIPI_CSI0_I2C0_SDA", \ + "MIPI_CSI0_GPIO0_00", \ + "MIPI_CSI0_GPIO0_01", \ + "MIPI_CSI1_MCLK_OUT", \ + "MIPI_CSI1_GPIO0_00", \ + "MIPI_CSI1_GPIO0_01", \ + "MIPI_CSI1_I2C0_SCL", \ + "MIPI_CSI1_I2C0_SDA", \ + "HDMI_TX0_TS_SCL", \ + "HDMI_TX0_TS_SDA", \ + "COMP_CTL_GPIO_3V3_HDMIGPIO", \ + "ESAI1_FSR", \ + "ESAI1_FST", \ + "ESAI1_SCKR", \ + "ESAI1_SCKT", \ + "ESAI1_TX0", \ + "ESAI1_TX1", \ + "ESAI1_TX2_RX3", \ + "ESAI1_TX3_RX2", \ + "ESAI1_TX4_RX1", \ + "ESAI1_TX5_RX0", \ + "SPDIF0_RX", \ + "SPDIF0_TX", \ + "SPDIF0_EXT_CLK", \ + "SPI3_SCK", \ + "SPI3_SDO", \ + "SPI3_SDI", \ + "SPI3_CS0", \ + "SPI3_CS1", \ + "COMP_CTL_GPIO_1V8_3V3_GPIORHB", \ + "ESAI0_FSR", \ + "ESAI0_FST", \ + "ESAI0_SCKR", \ + "ESAI0_SCKT", \ + "ESAI0_TX0", \ + "ESAI0_TX1", \ + "ESAI0_TX2_RX3", \ + "ESAI0_TX3_RX2", \ + "ESAI0_TX4_RX1", \ + "ESAI0_TX5_RX0", \ + "MCLK_IN0", \ + "MCLK_OUT0", \ + "COMP_CTL_GPIO_1V8_3V3_GPIORHC", \ + "SPI0_SCK", \ + "SPI0_SDO", \ + "SPI0_SDI", \ + "SPI0_CS0", \ + "SPI0_CS1", \ + "SPI2_SCK", \ + "SPI2_SDO", \ + "SPI2_SDI", \ + "SPI2_CS0", \ + "SPI2_CS1", \ + "SAI1_RXC", \ + "SAI1_RXD", \ + "SAI1_RXFS", \ + "SAI1_TXC", \ + "SAI1_TXD", \ + "SAI1_TXFS", \ + "COMP_CTL_GPIO_1V8_3V3_GPIORHT", \ + "ADC_IN7", \ + "ADC_IN6", \ + "ADC_IN5", \ + "ADC_IN4", \ + "ADC_IN3", \ + "ADC_IN2", \ + "ADC_IN1", \ + "ADC_IN0", \ + "MLB_SIG", \ + "MLB_CLK", \ + "MLB_DATA", \ + "COMP_CTL_GPIO_1V8_3V3_GPIOLHT", \ + "FLEXCAN0_RX", \ + "FLEXCAN0_TX", \ + "FLEXCAN1_RX", \ + "FLEXCAN1_TX", \ + "FLEXCAN2_RX", \ + "FLEXCAN2_TX", \ + "COMP_CTL_GPIO_1V8_3V3_GPIOTHR", \ + "USB_SS3_TC0", \ + "USB_SS3_TC1", \ + "USB_SS3_TC2", \ + "USB_SS3_TC3", \ + "COMP_CTL_GPIO_3V3_USB3IO", \ + "USDHC1_RESET_B", \ + "USDHC1_VSELECT", \ + "USDHC2_RESET_B", \ + "USDHC2_VSELECT", \ + "USDHC2_WP", \ + "USDHC2_CD_B", \ + "COMP_CTL_GPIO_1V8_3V3_VSELSEP", \ + "ENET0_MDIO", \ + "ENET0_MDC", \ + "ENET0_REFCLK_125M_25M", \ + "ENET1_REFCLK_125M_25M", \ + "ENET1_MDIO", \ + "ENET1_MDC", \ + "COMP_CTL_GPIO_1V8_3V3_GPIOCT", \ + "QSPI1A_SS0_B", \ + "QSPI1A_SS1_B", \ + "QSPI1A_SCLK", \ + "QSPI1A_DQS", \ + "QSPI1A_DATA3", \ + "QSPI1A_DATA2", \ + "QSPI1A_DATA1", \ + "QSPI1A_DATA0", \ + "COMP_CTL_GPIO_1V8_3V3_QSPI1", \ + "QSPI0A_DATA0", \ + "QSPI0A_DATA1", \ + "QSPI0A_DATA2", \ + "QSPI0A_DATA3", \ + "QSPI0A_DQS", \ + "QSPI0A_SS0_B", \ + "QSPI0A_SS1_B", \ + "QSPI0A_SCLK", \ + "QSPI0B_SCLK", \ + "QSPI0B_DATA0", \ + "QSPI0B_DATA1", \ + "QSPI0B_DATA2", \ + "QSPI0B_DATA3", \ + "QSPI0B_DQS", \ + "QSPI0B_SS0_B", \ + "QSPI0B_SS1_B", \ + "COMP_CTL_GPIO_1V8_3V3_QSPI0", \ + "PCIE_CTRL0_CLKREQ_B", \ + "PCIE_CTRL0_WAKE_B", \ + "PCIE_CTRL0_PERST_B", \ + "PCIE_CTRL1_CLKREQ_B", \ + "PCIE_CTRL1_WAKE_B", \ + "PCIE_CTRL1_PERST_B", \ + "COMP_CTL_GPIO_1V8_3V3_PCIESEP", \ + "USB_HSIC0_DATA", \ + "USB_HSIC0_STROBE", \ + "CALIBRATION_0_HSIC", \ + "CALIBRATION_1_HSIC", \ + "EMMC0_CLK", \ + "EMMC0_CMD", \ + "EMMC0_DATA0", \ + "EMMC0_DATA1", \ + "EMMC0_DATA2", \ + "EMMC0_DATA3", \ + "EMMC0_DATA4", \ + "EMMC0_DATA5", \ + "EMMC0_DATA6", \ + "EMMC0_DATA7", \ + "EMMC0_STROBE", \ + "EMMC0_RESET_B", \ + "COMP_CTL_GPIO_1V8_3V3_SD1FIX", \ + "USDHC1_CLK", \ + "USDHC1_CMD", \ + "USDHC1_DATA0", \ + "USDHC1_DATA1", \ + "CTL_NAND_RE_P_N", \ + "USDHC1_DATA2", \ + "USDHC1_DATA3", \ + "CTL_NAND_DQS_P_N", \ + "USDHC1_DATA4", \ + "USDHC1_DATA5", \ + "USDHC1_DATA6", \ + "USDHC1_DATA7", \ + "USDHC1_STROBE", \ + "COMP_CTL_GPIO_1V8_3V3_VSEL2", \ + "USDHC2_CLK", \ + "USDHC2_CMD", \ + "USDHC2_DATA0", \ + "USDHC2_DATA1", \ + "USDHC2_DATA2", \ + "USDHC2_DATA3", \ + "COMP_CTL_GPIO_1V8_3V3_VSEL3", \ + "ENET0_RGMII_TXC", \ + "ENET0_RGMII_TX_CTL", \ + "ENET0_RGMII_TXD0", \ + "ENET0_RGMII_TXD1", \ + "ENET0_RGMII_TXD2", \ + "ENET0_RGMII_TXD3", \ + "ENET0_RGMII_RXC", \ + "ENET0_RGMII_RX_CTL", \ + "ENET0_RGMII_RXD0", \ + "ENET0_RGMII_RXD1", \ + "ENET0_RGMII_RXD2", \ + "ENET0_RGMII_RXD3", \ + "COMP_CTL_GPIO_1V8_3V3_ENET_ENETB", \ + "ENET1_RGMII_TXC", \ + "ENET1_RGMII_TX_CTL", \ + "ENET1_RGMII_TXD0", \ + "ENET1_RGMII_TXD1", \ + "ENET1_RGMII_TXD2", \ + "ENET1_RGMII_TXD3", \ + "ENET1_RGMII_RXC", \ + "ENET1_RGMII_RX_CTL", \ + "ENET1_RGMII_RXD0", \ + "ENET1_RGMII_RXD1", \ + "ENET1_RGMII_RXD2", \ + "ENET1_RGMII_RXD3", \ + "COMP_CTL_GPIO_1V8_3V3_ENET_ENETA" +#endif + +#endif /* SC_PAD_DATA_H */ + diff --git a/platform/config/mx8qm/pad_priority.h b/platform/config/mx8qm/pad_priority.h new file mode 100644 index 0000000..cda603f --- /dev/null +++ b/platform/config/mx8qm/pad_priority.h @@ -0,0 +1,187 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to restrict pad mux settings based on resource ownership. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/pad_priority_h.pl */ + +#ifndef SC_PAD_PRIORITY_H +#define SC_PAD_PRIORITY_H + +/* Defines */ + +#define SC_PAD_PRIORITY_INIT \ + PNFO(SIM0_POWER_EN, 0, EMVSIM_0), \ + PNFO(SIM0_GPIO0_00, 0, EMVSIM_0), \ + PNFO(M40_GPIO0_00, 2, UART_4), \ + PNFO(M40_GPIO0_01, 2, UART_4), \ + PNFO(M41_GPIO0_00, 2, UART_3), \ + PNFO(M41_GPIO0_01, 2, UART_3), \ + PNFO(GPT0_CLK, 1, I2C_1), \ + PNFO(GPT0_CAPTURE, 1, I2C_1), \ + PNFO(UART0_RX, 1, SC_UART), \ + PNFO(UART0_TX, 1, SC_UART), \ + PNFO(UART0_RTS_B, 2, UART_2), \ + PNFO(UART0_CTS_B, 2, UART_2), \ + PNFO(UART1_TX, 1, SPI_3), \ + PNFO(UART1_RX, 1, SPI_3), \ + PNFO(UART1_RTS_B, 0, UART_1), \ + PNFO(UART1_RTS_B, 1, SPI_3), \ + PNFO(UART1_RTS_B, 2, UART_1), \ + PNFO(UART1_CTS_B, 0, UART_1), \ + PNFO(UART1_CTS_B, 1, SPI_3), \ + PNFO(UART1_CTS_B, 2, UART_1), \ + PNFO(PMIC_I2C_SDA, 0, SC_I2C), \ + PNFO(PMIC_I2C_SCL, 0, SC_I2C), \ + PNFO(SCU_GPIO0_00, 1, SC_UART), \ + PNFO(SCU_GPIO0_01, 1, SC_UART), \ + PNFO(SCU_BOOT_MODE4, 1, SC_I2C), \ + PNFO(SCU_BOOT_MODE5, 1, SC_I2C), \ + PNFO(LVDS0_I2C1_SCL, 1, UART_2), \ + PNFO(LVDS0_I2C1_SDA, 1, UART_2), \ + PNFO(LVDS1_I2C1_SCL, 1, UART_3), \ + PNFO(LVDS1_I2C1_SDA, 1, UART_3), \ + PNFO(MIPI_CSI0_GPIO0_00, 1, I2C_0), \ + PNFO(MIPI_CSI0_GPIO0_00, 2, CSI_1_I2C_0), \ + PNFO(MIPI_CSI0_GPIO0_01, 1, I2C_0), \ + PNFO(MIPI_CSI0_GPIO0_01, 2, CSI_1_I2C_0), \ + PNFO(MIPI_CSI1_GPIO0_00, 1, UART_4), \ + PNFO(MIPI_CSI1_GPIO0_01, 1, UART_4), \ + PNFO(MIPI_CSI1_I2C0_SCL, 0, CSI_1_I2C_0), \ + PNFO(MIPI_CSI1_I2C0_SDA, 0, CSI_1_I2C_0), \ + PNFO(HDMI_TX0_TS_SCL, 1, I2C_0), \ + PNFO(HDMI_TX0_TS_SDA, 1, I2C_0), \ + PNFO(ESAI1_FST, 1, SPDIF_0), \ + PNFO(ESAI1_SCKT, 2, SPDIF_0), \ + PNFO(ESAI1_TX0, 2, SPDIF_0), \ + PNFO(ESAI1_TX1, 2, SPDIF_0), \ + PNFO(ESAI1_TX2_RX3, 1, SPDIF_0), \ + PNFO(ESAI1_TX3_RX2, 1, SPDIF_0), \ + PNFO(SPDIF0_RX, 0, SPDIF_0), \ + PNFO(SPDIF0_RX, 1, MQS_0), \ + PNFO(SPDIF0_TX, 0, SPDIF_0), \ + PNFO(SPDIF0_TX, 1, MQS_0), \ + PNFO(SPDIF0_EXT_CLK, 0, SPDIF_0), \ + PNFO(SPI3_SCK, 0, SPI_3), \ + PNFO(SPI3_SDO, 0, SPI_3), \ + PNFO(SPI3_SDI, 0, SPI_3), \ + PNFO(SPI3_CS0, 0, SPI_3), \ + PNFO(SPI0_SDO, 1, SAI_0), \ + PNFO(SPI0_SDI, 1, SAI_0), \ + PNFO(SPI0_CS1, 1, SAI_0), \ + PNFO(SPI2_CS1, 1, SAI_0), \ + PNFO(SAI1_RXC, 0, SAI_1), \ + PNFO(SAI1_RXC, 1, SAI_0), \ + PNFO(SAI1_RXD, 1, SAI_0), \ + PNFO(SAI1_RXFS, 0, SAI_1), \ + PNFO(SAI1_RXFS, 1, SAI_0), \ + PNFO(SAI1_TXC, 1, SAI_0), \ + PNFO(SAI1_TXD, 1, SAI_1), \ + PNFO(SAI1_TXFS, 1, SAI_1), \ + PNFO(USB_SS3_TC0, 0, I2C_1), \ + PNFO(USB_SS3_TC0, 1, USB_0), \ + PNFO(USB_SS3_TC1, 0, I2C_1), \ + PNFO(USB_SS3_TC1, 1, USB_2), \ + PNFO(USB_SS3_TC2, 0, I2C_1), \ + PNFO(USB_SS3_TC2, 1, USB_0), \ + PNFO(USB_SS3_TC3, 0, I2C_1), \ + PNFO(USB_SS3_TC3, 1, USB_2), \ + PNFO(USDHC1_RESET_B, 0, SDHC_1), \ + PNFO(USDHC1_VSELECT, 0, SDHC_1), \ + PNFO(ENET0_MDIO, 1, I2C_4), \ + PNFO(ENET0_MDC, 1, I2C_4), \ + PNFO(ENET1_MDIO, 1, I2C_4), \ + PNFO(ENET1_MDC, 1, I2C_4), \ + PNFO(QSPI1A_DATA3, 1, I2C_1), \ + PNFO(QSPI1A_DATA3, 2, USB_0), \ + PNFO(QSPI1A_DATA2, 1, I2C_1), \ + PNFO(QSPI1A_DATA2, 2, USB_2), \ + PNFO(QSPI1A_DATA1, 1, I2C_1), \ + PNFO(QSPI1A_DATA1, 2, USB_2), \ + PNFO(PCIE_CTRL1_CLKREQ_B, 1, I2C_1), \ + PNFO(PCIE_CTRL1_CLKREQ_B, 2, USB_2), \ + PNFO(PCIE_CTRL1_WAKE_B, 1, I2C_1), \ + PNFO(PCIE_CTRL1_WAKE_B, 2, USB_2), \ + PNFO(PCIE_CTRL1_PERST_B, 1, I2C_1), \ + PNFO(PCIE_CTRL1_PERST_B, 2, USB_0), \ + PNFO(USB_HSIC0_DATA, 1, I2C_1), \ + PNFO(USB_HSIC0_STROBE, 1, I2C_1), \ + PNFO(EMMC0_CMD, 2, MQS_0), \ + PNFO(EMMC0_RESET_B, 2, SDHC_1), \ + PNFO(USDHC1_CLK, 1, MQS_0), \ + PNFO(USDHC1_CMD, 1, MQS_0), \ + PNFO(USDHC1_DATA4, 2, MQS_0), \ + PNFO(USDHC1_DATA5, 2, MQS_0), \ + PNFO(USDHC1_STROBE, 2, SDHC_1), \ + PNFO(USDHC2_CLK, 1, MQS_0), \ + PNFO(USDHC2_CMD, 1, MQS_0), \ + PNFO(USDHC2_DATA0, 1, UART_4), \ + PNFO(USDHC2_DATA1, 1, UART_4), \ + PNFO(ENET0_RGMII_TXD2, 1, UART_3), \ + PNFO(ENET0_RGMII_TXD2, 2, VPU_TS_0), \ + PNFO(ENET0_RGMII_TXD3, 1, UART_3), \ + PNFO(ENET0_RGMII_TXD3, 2, VPU_TS_0), \ + PNFO(ENET0_RGMII_RXC, 1, UART_3), \ + PNFO(ENET0_RGMII_RXC, 2, VPU_TS_0), \ + PNFO(ENET0_RGMII_RX_CTL, 1, VPU_TS_0), \ + PNFO(ENET0_RGMII_RXD0, 1, VPU_TS_0), \ + PNFO(ENET0_RGMII_RXD1, 1, VPU_TS_0), \ + PNFO(ENET0_RGMII_RXD2, 2, VPU_TS_0), \ + PNFO(ENET0_RGMII_RXD3, 1, UART_3), \ + PNFO(ENET0_RGMII_RXD3, 2, VPU_TS_0), \ + PNFO(ENET1_RGMII_TXD2, 1, UART_3), \ + PNFO(ENET1_RGMII_TXD2, 2, VPU_TS_0), \ + PNFO(ENET1_RGMII_TXD3, 1, UART_3), \ + PNFO(ENET1_RGMII_TXD3, 2, VPU_TS_0), \ + PNFO(ENET1_RGMII_RXC, 1, UART_3), \ + PNFO(ENET1_RGMII_RXC, 2, VPU_TS_0), \ + PNFO(ENET1_RGMII_RX_CTL, 1, VPU_TS_0), \ + PNFO(ENET1_RGMII_RXD0, 1, VPU_TS_0), \ + PNFO(ENET1_RGMII_RXD1, 1, VPU_TS_0), \ + PNFO(ENET1_RGMII_RXD2, 2, VPU_TS_0), \ + PNFO(ENET1_RGMII_RXD3, 1, UART_3), \ + PNFO(ENET1_RGMII_RXD3, 2, VPU_TS_0), \ + {0, 0, 0} + +#define SC_NUM_PAD_PRIORITY 130 + +#endif /* SC_PAD_PRIORITY_H */ + diff --git a/platform/config/mx8qm/pads.h b/platform/config/mx8qm/pads.h new file mode 100644 index 0000000..ab73e47 --- /dev/null +++ b/platform/config/mx8qm/pads.h @@ -0,0 +1,329 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure SoC pad list. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/pads_h.pl */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/** @{ */ +#define SC_P_SIM0_CLK 0U /*!< DMA.SIM0.CLK, LSIO.GPIO0.IO00 */ +#define SC_P_SIM0_RST 1U /*!< DMA.SIM0.RST, LSIO.GPIO0.IO01 */ +#define SC_P_SIM0_IO 2U /*!< DMA.SIM0.IO, LSIO.GPIO0.IO02 */ +#define SC_P_SIM0_PD 3U /*!< DMA.SIM0.PD, DMA.I2C3.SCL, LSIO.GPIO0.IO03 */ +#define SC_P_SIM0_POWER_EN 4U /*!< DMA.SIM0.POWER_EN, DMA.I2C3.SDA, LSIO.GPIO0.IO04 */ +#define SC_P_SIM0_GPIO0_00 5U /*!< DMA.SIM0.POWER_EN, LSIO.GPIO0.IO05 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 6U /*!< */ +#define SC_P_M40_I2C0_SCL 7U /*!< M40.I2C0.SCL, M40.UART0.RX, M40.GPIO0.IO02, LSIO.GPIO0.IO06 */ +#define SC_P_M40_I2C0_SDA 8U /*!< M40.I2C0.SDA, M40.UART0.TX, M40.GPIO0.IO03, LSIO.GPIO0.IO07 */ +#define SC_P_M40_GPIO0_00 9U /*!< M40.GPIO0.IO00, M40.TPM0.CH0, DMA.UART4.RX, LSIO.GPIO0.IO08 */ +#define SC_P_M40_GPIO0_01 10U /*!< M40.GPIO0.IO01, M40.TPM0.CH1, DMA.UART4.TX, LSIO.GPIO0.IO09 */ +#define SC_P_M41_I2C0_SCL 11U /*!< M41.I2C0.SCL, M41.UART0.RX, M41.GPIO0.IO02, LSIO.GPIO0.IO10 */ +#define SC_P_M41_I2C0_SDA 12U /*!< M41.I2C0.SDA, M41.UART0.TX, M41.GPIO0.IO03, LSIO.GPIO0.IO11 */ +#define SC_P_M41_GPIO0_00 13U /*!< M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ +#define SC_P_M41_GPIO0_01 14U /*!< M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ +#define SC_P_GPT0_CLK 15U /*!< LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ +#define SC_P_GPT0_CAPTURE 16U /*!< LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 */ +#define SC_P_GPT0_COMPARE 17U /*!< LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ +#define SC_P_GPT1_CLK 18U /*!< LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE 19U /*!< LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 */ +#define SC_P_GPT1_COMPARE 20U /*!< LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ +#define SC_P_UART0_RX 21U /*!< DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ +#define SC_P_UART0_TX 22U /*!< DMA.UART0.TX, SCU.UART0.TX, LSIO.GPIO0.IO21 */ +#define SC_P_UART0_RTS_B 23U /*!< DMA.UART0.RTS_B, LSIO.PWM0.OUT, DMA.UART2.RX, LSIO.GPIO0.IO22 */ +#define SC_P_UART0_CTS_B 24U /*!< DMA.UART0.CTS_B, LSIO.PWM1.OUT, DMA.UART2.TX, LSIO.GPIO0.IO23 */ +#define SC_P_UART1_TX 25U /*!< DMA.UART1.TX, DMA.SPI3.SCK, LSIO.GPIO0.IO24 */ +#define SC_P_UART1_RX 26U /*!< DMA.UART1.RX, DMA.SPI3.SDO, LSIO.GPIO0.IO25 */ +#define SC_P_UART1_RTS_B 27U /*!< DMA.UART1.RTS_B, DMA.SPI3.SDI, DMA.UART1.CTS_B, LSIO.GPIO0.IO26 */ +#define SC_P_UART1_CTS_B 28U /*!< DMA.UART1.CTS_B, DMA.SPI3.CS0, DMA.UART1.RTS_B, LSIO.GPIO0.IO27 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29U /*!< */ +#define SC_P_SCU_PMIC_MEMC_ON 30U /*!< SCU.GPIO0.IOXX_PMIC_MEMC_ON */ +#define SC_P_SCU_WDOG_OUT 31U /*!< SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SDA 32U /*!< SCU.PMIC_I2C.SDA */ +#define SC_P_PMIC_I2C_SCL 33U /*!< SCU.PMIC_I2C.SCL */ +#define SC_P_PMIC_EARLY_WARNING 34U /*!< SCU.PMIC_EARLY_WARNING */ +#define SC_P_PMIC_INT_B 35U /*!< SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 36U /*!< SCU.GPIO0.IO00, SCU.UART0.RX, LSIO.GPIO0.IO28 */ +#define SC_P_SCU_GPIO0_01 37U /*!< SCU.GPIO0.IO01, SCU.UART0.TX, LSIO.GPIO0.IO29 */ +#define SC_P_SCU_GPIO0_02 38U /*!< SCU.GPIO0.IO02, SCU.GPIO0.IOXX_PMIC_GPU0_ON, LSIO.GPIO0.IO30 */ +#define SC_P_SCU_GPIO0_03 39U /*!< SCU.GPIO0.IO03, SCU.GPIO0.IOXX_PMIC_GPU1_ON, LSIO.GPIO0.IO31 */ +#define SC_P_SCU_GPIO0_04 40U /*!< SCU.GPIO0.IO04, SCU.GPIO0.IOXX_PMIC_A72_ON, LSIO.GPIO1.IO00 */ +#define SC_P_SCU_GPIO0_05 41U /*!< SCU.GPIO0.IO05, SCU.GPIO0.IOXX_PMIC_A53_ON, LSIO.GPIO1.IO01 */ +#define SC_P_SCU_GPIO0_06 42U /*!< SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ +#define SC_P_SCU_GPIO0_07 43U /*!< SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ +#define SC_P_SCU_BOOT_MODE0 44U /*!< SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45U /*!< SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46U /*!< SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47U /*!< SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48U /*!< SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49U /*!< SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50U /*!< LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51U /*!< LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52U /*!< LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53U /*!< LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54U /*!< LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55U /*!< LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56U /*!< LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57U /*!< LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58U /*!< LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59U /*!< LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60U /*!< LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61U /*!< LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62U /*!< */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63U /*!< MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64U /*!< MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 65U /*!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 */ +#define SC_P_MIPI_DSI0_GPIO0_01 66U /*!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67U /*!< MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68U /*!< MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 69U /*!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 */ +#define SC_P_MIPI_DSI1_GPIO0_01 70U /*!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71U /*!< */ +#define SC_P_MIPI_CSI0_MCLK_OUT 72U /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ +#define SC_P_MIPI_CSI0_I2C0_SCL 73U /*!< MIPI_CSI0.I2C0.SCL, LSIO.GPIO1.IO25 */ +#define SC_P_MIPI_CSI0_I2C0_SDA 74U /*!< MIPI_CSI0.I2C0.SDA, LSIO.GPIO1.IO26 */ +#define SC_P_MIPI_CSI0_GPIO0_00 75U /*!< MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ +#define SC_P_MIPI_CSI0_GPIO0_01 76U /*!< MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77U /*!< MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78U /*!< MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79U /*!< MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80U /*!< MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81U /*!< MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82U /*!< HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83U /*!< HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84U /*!< */ +#define SC_P_ESAI1_FSR 85U /*!< AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86U /*!< AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87U /*!< AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT 88U /*!< AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 */ +#define SC_P_ESAI1_TX0 89U /*!< AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ +#define SC_P_ESAI1_TX1 90U /*!< AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ +#define SC_P_ESAI1_TX2_RX3 91U /*!< AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ +#define SC_P_ESAI1_TX3_RX2 92U /*!< AUD.ESAI1.TX3_RX2, AUD.SPDIF0.TX, LSIO.GPIO2.IO11 */ +#define SC_P_ESAI1_TX4_RX1 93U /*!< AUD.ESAI1.TX4_RX1, LSIO.GPIO2.IO12 */ +#define SC_P_ESAI1_TX5_RX0 94U /*!< AUD.ESAI1.TX5_RX0, LSIO.GPIO2.IO13 */ +#define SC_P_SPDIF0_RX 95U /*!< AUD.SPDIF0.RX, AUD.MQS.R, AUD.ACM.MCLK_IN1, LSIO.GPIO2.IO14 */ +#define SC_P_SPDIF0_TX 96U /*!< AUD.SPDIF0.TX, AUD.MQS.L, AUD.ACM.MCLK_OUT1, LSIO.GPIO2.IO15 */ +#define SC_P_SPDIF0_EXT_CLK 97U /*!< AUD.SPDIF0.EXT_CLK, DMA.DMA0.REQ_IN0, LSIO.GPIO2.IO16 */ +#define SC_P_SPI3_SCK 98U /*!< DMA.SPI3.SCK, LSIO.GPIO2.IO17 */ +#define SC_P_SPI3_SDO 99U /*!< DMA.SPI3.SDO, DMA.FTM.CH0, LSIO.GPIO2.IO18 */ +#define SC_P_SPI3_SDI 100U /*!< DMA.SPI3.SDI, DMA.FTM.CH1, LSIO.GPIO2.IO19 */ +#define SC_P_SPI3_CS0 101U /*!< DMA.SPI3.CS0, DMA.FTM.CH2, LSIO.GPIO2.IO20 */ +#define SC_P_SPI3_CS1 102U /*!< DMA.SPI3.CS1, LSIO.GPIO2.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103U /*!< */ +#define SC_P_ESAI0_FSR 104U /*!< AUD.ESAI0.FSR, LSIO.GPIO2.IO22 */ +#define SC_P_ESAI0_FST 105U /*!< AUD.ESAI0.FST, LSIO.GPIO2.IO23 */ +#define SC_P_ESAI0_SCKR 106U /*!< AUD.ESAI0.SCKR, LSIO.GPIO2.IO24 */ +#define SC_P_ESAI0_SCKT 107U /*!< AUD.ESAI0.SCKT, LSIO.GPIO2.IO25 */ +#define SC_P_ESAI0_TX0 108U /*!< AUD.ESAI0.TX0, LSIO.GPIO2.IO26 */ +#define SC_P_ESAI0_TX1 109U /*!< AUD.ESAI0.TX1, LSIO.GPIO2.IO27 */ +#define SC_P_ESAI0_TX2_RX3 110U /*!< AUD.ESAI0.TX2_RX3, LSIO.GPIO2.IO28 */ +#define SC_P_ESAI0_TX3_RX2 111U /*!< AUD.ESAI0.TX3_RX2, LSIO.GPIO2.IO29 */ +#define SC_P_ESAI0_TX4_RX1 112U /*!< AUD.ESAI0.TX4_RX1, LSIO.GPIO2.IO30 */ +#define SC_P_ESAI0_TX5_RX0 113U /*!< AUD.ESAI0.TX5_RX0, LSIO.GPIO2.IO31 */ +#define SC_P_MCLK_IN0 114U /*!< AUD.ACM.MCLK_IN0, AUD.ESAI0.RX_HF_CLK, AUD.ESAI1.RX_HF_CLK, LSIO.GPIO3.IO00 */ +#define SC_P_MCLK_OUT0 115U /*!< AUD.ACM.MCLK_OUT0, AUD.ESAI0.TX_HF_CLK, AUD.ESAI1.TX_HF_CLK, LSIO.GPIO3.IO01 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116U /*!< */ +#define SC_P_SPI0_SCK 117U /*!< DMA.SPI0.SCK, AUD.SAI0.RXC, LSIO.GPIO3.IO02 */ +#define SC_P_SPI0_SDO 118U /*!< DMA.SPI0.SDO, AUD.SAI0.TXD, LSIO.GPIO3.IO03 */ +#define SC_P_SPI0_SDI 119U /*!< DMA.SPI0.SDI, AUD.SAI0.RXD, LSIO.GPIO3.IO04 */ +#define SC_P_SPI0_CS0 120U /*!< DMA.SPI0.CS0, AUD.SAI0.RXFS, LSIO.GPIO3.IO05 */ +#define SC_P_SPI0_CS1 121U /*!< DMA.SPI0.CS1, AUD.SAI0.TXC, LSIO.GPIO3.IO06 */ +#define SC_P_SPI2_SCK 122U /*!< DMA.SPI2.SCK, LSIO.GPIO3.IO07 */ +#define SC_P_SPI2_SDO 123U /*!< DMA.SPI2.SDO, LSIO.GPIO3.IO08 */ +#define SC_P_SPI2_SDI 124U /*!< DMA.SPI2.SDI, LSIO.GPIO3.IO09 */ +#define SC_P_SPI2_CS0 125U /*!< DMA.SPI2.CS0, LSIO.GPIO3.IO10 */ +#define SC_P_SPI2_CS1 126U /*!< DMA.SPI2.CS1, AUD.SAI0.TXFS, LSIO.GPIO3.IO11 */ +#define SC_P_SAI1_RXC 127U /*!< AUD.SAI1.RXC, AUD.SAI0.TXD, LSIO.GPIO3.IO12 */ +#define SC_P_SAI1_RXD 128U /*!< AUD.SAI1.RXD, AUD.SAI0.TXFS, LSIO.GPIO3.IO13 */ +#define SC_P_SAI1_RXFS 129U /*!< AUD.SAI1.RXFS, AUD.SAI0.RXD, LSIO.GPIO3.IO14 */ +#define SC_P_SAI1_TXC 130U /*!< AUD.SAI1.TXC, AUD.SAI0.TXC, LSIO.GPIO3.IO15 */ +#define SC_P_SAI1_TXD 131U /*!< AUD.SAI1.TXD, AUD.SAI1.RXC, LSIO.GPIO3.IO16 */ +#define SC_P_SAI1_TXFS 132U /*!< AUD.SAI1.TXFS, AUD.SAI1.RXFS, LSIO.GPIO3.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133U /*!< */ +#define SC_P_ADC_IN7 134U /*!< DMA.ADC1.IN3, DMA.SPI1.CS1, LSIO.KPP0.ROW3, LSIO.GPIO3.IO25 */ +#define SC_P_ADC_IN6 135U /*!< DMA.ADC1.IN2, DMA.SPI1.CS0, LSIO.KPP0.ROW2, LSIO.GPIO3.IO24 */ +#define SC_P_ADC_IN5 136U /*!< DMA.ADC1.IN1, DMA.SPI1.SDI, LSIO.KPP0.ROW1, LSIO.GPIO3.IO23 */ +#define SC_P_ADC_IN4 137U /*!< DMA.ADC1.IN0, DMA.SPI1.SDO, LSIO.KPP0.ROW0, LSIO.GPIO3.IO22 */ +#define SC_P_ADC_IN3 138U /*!< DMA.ADC0.IN3, DMA.SPI1.SCK, LSIO.KPP0.COL3, LSIO.GPIO3.IO21 */ +#define SC_P_ADC_IN2 139U /*!< DMA.ADC0.IN2, LSIO.KPP0.COL2, LSIO.GPIO3.IO20 */ +#define SC_P_ADC_IN1 140U /*!< DMA.ADC0.IN1, LSIO.KPP0.COL1, LSIO.GPIO3.IO19 */ +#define SC_P_ADC_IN0 141U /*!< DMA.ADC0.IN0, LSIO.KPP0.COL0, LSIO.GPIO3.IO18 */ +#define SC_P_MLB_SIG 142U /*!< CONN.MLB.SIG, AUD.SAI3.RXC, LSIO.GPIO3.IO26 */ +#define SC_P_MLB_CLK 143U /*!< CONN.MLB.CLK, AUD.SAI3.RXFS, LSIO.GPIO3.IO27 */ +#define SC_P_MLB_DATA 144U /*!< CONN.MLB.DATA, AUD.SAI3.RXD, LSIO.GPIO3.IO28 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145U /*!< */ +#define SC_P_FLEXCAN0_RX 146U /*!< DMA.FLEXCAN0.RX, LSIO.GPIO3.IO29 */ +#define SC_P_FLEXCAN0_TX 147U /*!< DMA.FLEXCAN0.TX, LSIO.GPIO3.IO30 */ +#define SC_P_FLEXCAN1_RX 148U /*!< DMA.FLEXCAN1.RX, LSIO.GPIO3.IO31 */ +#define SC_P_FLEXCAN1_TX 149U /*!< DMA.FLEXCAN1.TX, LSIO.GPIO4.IO00 */ +#define SC_P_FLEXCAN2_RX 150U /*!< DMA.FLEXCAN2.RX, LSIO.GPIO4.IO01 */ +#define SC_P_FLEXCAN2_TX 151U /*!< DMA.FLEXCAN2.TX, LSIO.GPIO4.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152U /*!< */ +#define SC_P_USB_SS3_TC0 153U /*!< DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO4.IO03 */ +#define SC_P_USB_SS3_TC1 154U /*!< DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 155U /*!< DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO05 */ +#define SC_P_USB_SS3_TC3 156U /*!< DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 157U /*!< */ +#define SC_P_USDHC1_RESET_B 158U /*!< CONN.USDHC1.RESET_B, LSIO.GPIO4.IO07 */ +#define SC_P_USDHC1_VSELECT 159U /*!< CONN.USDHC1.VSELECT, LSIO.GPIO4.IO08 */ +#define SC_P_USDHC2_RESET_B 160U /*!< CONN.USDHC2.RESET_B, LSIO.GPIO4.IO09 */ +#define SC_P_USDHC2_VSELECT 161U /*!< CONN.USDHC2.VSELECT, LSIO.GPIO4.IO10 */ +#define SC_P_USDHC2_WP 162U /*!< CONN.USDHC2.WP, LSIO.GPIO4.IO11 */ +#define SC_P_USDHC2_CD_B 163U /*!< CONN.USDHC2.CD_B, LSIO.GPIO4.IO12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164U /*!< */ +#define SC_P_ENET0_MDIO 165U /*!< CONN.ENET0.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO13 */ +#define SC_P_ENET0_MDC 166U /*!< CONN.ENET0.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO14 */ +#define SC_P_ENET0_REFCLK_125M_25M 167U /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, LSIO.GPIO4.IO15 */ +#define SC_P_ENET1_REFCLK_125M_25M 168U /*!< CONN.ENET1.REFCLK_125M_25M, CONN.ENET1.PPS, LSIO.GPIO4.IO16 */ +#define SC_P_ENET1_MDIO 169U /*!< CONN.ENET1.MDIO, DMA.I2C4.SDA, LSIO.GPIO4.IO17 */ +#define SC_P_ENET1_MDC 170U /*!< CONN.ENET1.MDC, DMA.I2C4.SCL, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171U /*!< */ +#define SC_P_QSPI1A_SS0_B 172U /*!< LSIO.QSPI1A.SS0_B, LSIO.GPIO4.IO19 */ +#define SC_P_QSPI1A_SS1_B 173U /*!< LSIO.QSPI1A.SS1_B, LSIO.QSPI1A.SCLK2, LSIO.GPIO4.IO20 */ +#define SC_P_QSPI1A_SCLK 174U /*!< LSIO.QSPI1A.SCLK, LSIO.GPIO4.IO21 */ +#define SC_P_QSPI1A_DQS 175U /*!< LSIO.QSPI1A.DQS, LSIO.GPIO4.IO22 */ +#define SC_P_QSPI1A_DATA3 176U /*!< LSIO.QSPI1A.DATA3, DMA.I2C1.SDA, CONN.USB_OTG1.OC, LSIO.GPIO4.IO23 */ +#define SC_P_QSPI1A_DATA2 177U /*!< LSIO.QSPI1A.DATA2, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO24 */ +#define SC_P_QSPI1A_DATA1 178U /*!< LSIO.QSPI1A.DATA1, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO25 */ +#define SC_P_QSPI1A_DATA0 179U /*!< LSIO.QSPI1A.DATA0, LSIO.GPIO4.IO26 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 180U /*!< */ +#define SC_P_QSPI0A_DATA0 181U /*!< LSIO.QSPI0A.DATA0 */ +#define SC_P_QSPI0A_DATA1 182U /*!< LSIO.QSPI0A.DATA1 */ +#define SC_P_QSPI0A_DATA2 183U /*!< LSIO.QSPI0A.DATA2 */ +#define SC_P_QSPI0A_DATA3 184U /*!< LSIO.QSPI0A.DATA3 */ +#define SC_P_QSPI0A_DQS 185U /*!< LSIO.QSPI0A.DQS */ +#define SC_P_QSPI0A_SS0_B 186U /*!< LSIO.QSPI0A.SS0_B */ +#define SC_P_QSPI0A_SS1_B 187U /*!< LSIO.QSPI0A.SS1_B, LSIO.QSPI0A.SCLK2 */ +#define SC_P_QSPI0A_SCLK 188U /*!< LSIO.QSPI0A.SCLK */ +#define SC_P_QSPI0B_SCLK 189U /*!< LSIO.QSPI0B.SCLK */ +#define SC_P_QSPI0B_DATA0 190U /*!< LSIO.QSPI0B.DATA0 */ +#define SC_P_QSPI0B_DATA1 191U /*!< LSIO.QSPI0B.DATA1 */ +#define SC_P_QSPI0B_DATA2 192U /*!< LSIO.QSPI0B.DATA2 */ +#define SC_P_QSPI0B_DATA3 193U /*!< LSIO.QSPI0B.DATA3 */ +#define SC_P_QSPI0B_DQS 194U /*!< LSIO.QSPI0B.DQS */ +#define SC_P_QSPI0B_SS0_B 195U /*!< LSIO.QSPI0B.SS0_B */ +#define SC_P_QSPI0B_SS1_B 196U /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI0B.SCLK2 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 197U /*!< */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 198U /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO27 */ +#define SC_P_PCIE_CTRL0_WAKE_B 199U /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO28 */ +#define SC_P_PCIE_CTRL0_PERST_B 200U /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO29 */ +#define SC_P_PCIE_CTRL1_CLKREQ_B 201U /*!< HSIO.PCIE1.CLKREQ_B, DMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO30 */ +#define SC_P_PCIE_CTRL1_WAKE_B 202U /*!< HSIO.PCIE1.WAKE_B, DMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO31 */ +#define SC_P_PCIE_CTRL1_PERST_B 203U /*!< HSIO.PCIE1.PERST_B, DMA.I2C1.SCL, CONN.USB_OTG1.PWR, LSIO.GPIO5.IO00 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204U /*!< */ +#define SC_P_USB_HSIC0_DATA 205U /*!< CONN.USB_HSIC0.DATA, DMA.I2C1.SDA, LSIO.GPIO5.IO01 */ +#define SC_P_USB_HSIC0_STROBE 206U /*!< CONN.USB_HSIC0.STROBE, DMA.I2C1.SCL, LSIO.GPIO5.IO02 */ +#define SC_P_CALIBRATION_0_HSIC 207U /*!< */ +#define SC_P_CALIBRATION_1_HSIC 208U /*!< */ +#define SC_P_EMMC0_CLK 209U /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B */ +#define SC_P_EMMC0_CMD 210U /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, AUD.MQS.R, LSIO.GPIO5.IO03 */ +#define SC_P_EMMC0_DATA0 211U /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO5.IO04 */ +#define SC_P_EMMC0_DATA1 212U /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO5.IO05 */ +#define SC_P_EMMC0_DATA2 213U /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO5.IO06 */ +#define SC_P_EMMC0_DATA3 214U /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO5.IO07 */ +#define SC_P_EMMC0_DATA4 215U /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO5.IO08 */ +#define SC_P_EMMC0_DATA5 216U /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO5.IO09 */ +#define SC_P_EMMC0_DATA6 217U /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO5.IO10 */ +#define SC_P_EMMC0_DATA7 218U /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO5.IO11 */ +#define SC_P_EMMC0_STROBE 219U /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO5.IO12 */ +#define SC_P_EMMC0_RESET_B 220U /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, CONN.USDHC1.VSELECT, LSIO.GPIO5.IO13 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221U /*!< */ +#define SC_P_USDHC1_CLK 222U /*!< CONN.USDHC1.CLK, AUD.MQS.R */ +#define SC_P_USDHC1_CMD 223U /*!< CONN.USDHC1.CMD, AUD.MQS.L, LSIO.GPIO5.IO14 */ +#define SC_P_USDHC1_DATA0 224U /*!< CONN.USDHC1.DATA0, CONN.NAND.RE_N, LSIO.GPIO5.IO15 */ +#define SC_P_USDHC1_DATA1 225U /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_P, LSIO.GPIO5.IO16 */ +#define SC_P_CTL_NAND_RE_P_N 226U /*!< */ +#define SC_P_USDHC1_DATA2 227U /*!< CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ +#define SC_P_USDHC1_DATA3 228U /*!< CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ +#define SC_P_CTL_NAND_DQS_P_N 229U /*!< */ +#define SC_P_USDHC1_DATA4 230U /*!< CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 */ +#define SC_P_USDHC1_DATA5 231U /*!< CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA6 232U /*!< CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ +#define SC_P_USDHC1_DATA7 233U /*!< CONN.USDHC1.DATA7, CONN.NAND.ALE, CONN.USDHC1.CD_B, LSIO.GPIO5.IO22 */ +#define SC_P_USDHC1_STROBE 234U /*!< CONN.USDHC1.STROBE, CONN.NAND.CE1_B, CONN.USDHC1.RESET_B, LSIO.GPIO5.IO23 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 235U /*!< */ +#define SC_P_USDHC2_CLK 236U /*!< CONN.USDHC2.CLK, AUD.MQS.R, LSIO.GPIO5.IO24 */ +#define SC_P_USDHC2_CMD 237U /*!< CONN.USDHC2.CMD, AUD.MQS.L, LSIO.GPIO5.IO25 */ +#define SC_P_USDHC2_DATA0 238U /*!< CONN.USDHC2.DATA0, DMA.UART4.RX, LSIO.GPIO5.IO26 */ +#define SC_P_USDHC2_DATA1 239U /*!< CONN.USDHC2.DATA1, DMA.UART4.TX, LSIO.GPIO5.IO27 */ +#define SC_P_USDHC2_DATA2 240U /*!< CONN.USDHC2.DATA2, DMA.UART4.CTS_B, LSIO.GPIO5.IO28 */ +#define SC_P_USDHC2_DATA3 241U /*!< CONN.USDHC2.DATA3, DMA.UART4.RTS_B, LSIO.GPIO5.IO29 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 242U /*!< */ +#define SC_P_ENET0_RGMII_TXC 243U /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, LSIO.GPIO5.IO30 */ +#define SC_P_ENET0_RGMII_TX_CTL 244U /*!< CONN.ENET0.RGMII_TX_CTL, LSIO.GPIO5.IO31 */ +#define SC_P_ENET0_RGMII_TXD0 245U /*!< CONN.ENET0.RGMII_TXD0, LSIO.GPIO6.IO00 */ +#define SC_P_ENET0_RGMII_TXD1 246U /*!< CONN.ENET0.RGMII_TXD1, LSIO.GPIO6.IO01 */ +#define SC_P_ENET0_RGMII_TXD2 247U /*!< CONN.ENET0.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO02 */ +#define SC_P_ENET0_RGMII_TXD3 248U /*!< CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ +#define SC_P_ENET0_RGMII_RXC 249U /*!< CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ +#define SC_P_ENET0_RGMII_RX_CTL 250U /*!< CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 */ +#define SC_P_ENET0_RGMII_RXD0 251U /*!< CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252U /*!< CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RXD2 253U /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ +#define SC_P_ENET0_RGMII_RXD3 254U /*!< CONN.ENET0.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO09 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255U /*!< */ +#define SC_P_ENET1_RGMII_TXC 256U /*!< CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RCLK50M_IN, LSIO.GPIO6.IO10 */ +#define SC_P_ENET1_RGMII_TX_CTL 257U /*!< CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO6.IO11 */ +#define SC_P_ENET1_RGMII_TXD0 258U /*!< CONN.ENET1.RGMII_TXD0, LSIO.GPIO6.IO12 */ +#define SC_P_ENET1_RGMII_TXD1 259U /*!< CONN.ENET1.RGMII_TXD1, LSIO.GPIO6.IO13 */ +#define SC_P_ENET1_RGMII_TXD2 260U /*!< CONN.ENET1.RGMII_TXD2, DMA.UART3.TX, VPU.TSI_S1.VID, LSIO.GPIO6.IO14 */ +#define SC_P_ENET1_RGMII_TXD3 261U /*!< CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ +#define SC_P_ENET1_RGMII_RXC 262U /*!< CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ +#define SC_P_ENET1_RGMII_RX_CTL 263U /*!< CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 */ +#define SC_P_ENET1_RGMII_RXD0 264U /*!< CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265U /*!< CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RXD2 266U /*!< CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ +#define SC_P_ENET1_RGMII_RXD3 267U /*!< CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268U /*!< */ +/** @} */ + +#endif /* SC_PADS_H */ + diff --git a/platform/config/mx8qm/soc.bom b/platform/config/mx8qm/soc.bom new file mode 100755 index 0000000..69a1a64 --- /dev/null +++ b/platform/config/mx8qm/soc.bom @@ -0,0 +1,63 @@ + +SOC = MX8QM + +DRV += \ + analog \ + csr \ + dsc \ + otp \ + pad \ + seco/v2 \ + snvs/v2 \ + sysctr \ + xrdc2 \ + mtr + +DRV2 += \ + rgpio \ + igpio \ + lmem \ + lpi2c \ + lpit \ + lpcg \ + lpuart \ + mu \ + stc \ + systick \ + drc \ + wdog32 + +SS += \ + a53/v1 \ + a72/v1 \ + audio/v1 \ + base/v1 \ + cci/v1 \ + conn/v1 \ + csi/v1 \ + db/v1 \ + dblogic/v1 \ + dc/v1 \ + dma/v1 \ + drc/v1 \ + gpu/v1 \ + hdmi/v1 \ + hdmi_rx/v1 \ + hsio/v1 \ + img/v1 \ + lsio/v2 \ + lvds/v1 \ + m4/v1 \ + mipi/v1 \ + sc/v2 \ + vpu/v3 + +SVC += \ + irq \ + misc \ + pad \ + pm \ + rm \ + seco \ + timer + diff --git a/platform/config/mx8qm/soc.h b/platform/config/mx8qm/soc.h new file mode 100755 index 0000000..ac1de49 --- /dev/null +++ b/platform/config/mx8qm/soc.h @@ -0,0 +1,771 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure SoC specific features of the SCFW. + * Includes info on memory map, DSC mapping, subsystem mapping, etc. + * + */ +/*==========================================================================*/ + +#ifndef SC_SOC_H +#define SC_SOC_H + +/* Includes */ + +#include "main/types.h" +#include "has_ss.h" +#include "fsl_device_registers.h" +#include "ss/drc/v1/dsc.h" + +/* Configure DSCs */ + +/*! Macro to calculate DSC index */ +#define DSC_IDX(X) ((sc_dsc_t) ((((uint32_t) (X)) - ((uint32_t) MSI0_BASE)) / 131072U)) + +/*! Macro to define AI_READ/WRITE */ +#define ANA_READ(BASE_IDX, TOG, ADDRESS, RDATA) DSC_AIRegisterRead(BASE_IDX, TOG, ADDRESS, RDATA) +#define ANA_WRITE(BASE_IDX, TOG, ADDRESS, DATAWORD) DSC_AIRegisterWrite(BASE_IDX, TOG, ADDRESS, DATAWORD) +#define ANA_ENABLE_ANAMIX_AI(BASE_IDX) DSC_EnableAnamixAI(BASE_IDX) +#define ANA_ENABLE_PHYMIX_AI(BASE_IDX) DSC_EnablePhymixAI(BASE_IDX) + +/*! Define for Refgen default trim in case of unfused part */ +#define REFGEN_DEFAULT_TRIM 0x2BU +/*! + * @name Defines for sc_dsc_t + */ +/** @{ */ +#define SC_DSC_SC DSC_IDX(DSC_SC) /* 0x01 */ +#define SC_DSC_MCU_0 DSC_IDX(DSC_MCU_0) /* 0x11 */ +#define SC_DSC_DRC_0 DSC_IDX(DSC_DRC_0) /* 0x12 */ +#define SC_DSC_DC_1 DSC_IDX(DSC_DC_1) /* 0x13 */ +#define SC_DSC_MCU_1 DSC_IDX(DSC_MCU_1) /* 0x14 */ +#define SC_DSC_GPU_1 DSC_IDX(DSC_GPU_1) /* 0x15 */ +#define SC_DSC_CONN DSC_IDX(DSC_CONN) /* 0x16 */ +#define SC_DSC_VPU DSC_IDX(DSC_VPU) /* 0x17 */ +#define SC_DSC_CCI DSC_IDX(DSC_CCI) /* 0x19 */ +#define SC_DSC_AP_1 DSC_IDX(DSC_AP_1) /* 0x21 */ +#define SC_DSC_DB DSC_IDX(DSC_DB) /* 0x22 */ +#define SC_DSC_AP_0 DSC_IDX(DSC_AP_0) /* 0x23 */ +#define SC_DSC_HSIO DSC_IDX(DSC_HSIO) /* 0x24 */ +#define SC_DSC_LSIO DSC_IDX(DSC_LSIO) /* 0x25 */ +#define SC_DSC_GPU_0 DSC_IDX(DSC_GPU_0) /* 0x26 */ +#define SC_DSC_DC_0 DSC_IDX(DSC_DC_0) /* 0x27 */ +#define SC_DSC_DRC_1 DSC_IDX(DSC_DRC_1) /* 0x28 */ +#define SC_DSC_DMA DSC_IDX(DSC_DMA) /* 0x29 */ +#define SC_DSC_DBLOG DSC_IDX(DSC_DBLOG) /* 0x31 */ +#define SC_DSC_IMG DSC_IDX(DSC_IMG) /* 0x32 */ +#define SC_DSC_AUDIO DSC_IDX(DSC_AUDIO) /* 0x33 */ +#define SC_DSC_DI_HDMI DSC_IDX(DSC_HDMI) /* 0x34 */ +#define SC_DSC_RX_HDMI DSC_IDX(DSC_HDMI_RX) /* 0x35 */ +#define SC_DSC_CSI_1 DSC_IDX(DSC_CSI_1) /* 0x36 */ +#define SC_DSC_CSI_0 DSC_IDX(DSC_CSI_0) /* 0x37 */ +#define SC_DSC_DI_MIPI_1 DSC_IDX(DSC_MIPI_1) /* 0x38 */ +#define SC_DSC_DI_MIPI_0 DSC_IDX(DSC_MIPI_0) /* 0x39 */ +#define SC_DSC_DI_LVDS_1 DSC_IDX(DSC_LVDS_1) /* 0x3A */ +#define SC_DSC_DI_LVDS_0 DSC_IDX(DSC_LVDS_0) /* 0x3B */ +#define SC_DSC_LAST 0x3FU +#define SC_DSC_NA SC_DSC_LAST +#define SC_DSC_W 6U +/** @} */ + +/*! + * DSC Type. This type is a used to indicate a Distributed Slave + * Controller (DSC). + */ +typedef uint8_t sc_dsc_t; + +/*! + * @name Defines for sc_ai_t + */ +/** @{ */ +#define SC_AI_HP_PLL 0U +#define SC_AI_DIG_PLL 1U +#define SC_AI_AV_PLL 2U +#define SC_AI_LVDS_TRANS 3U +#define SC_AI_BANDGAP_REF 4U +#define SC_AI_VA_REFGEN 5U +#define SC_AI_NEG_CHARGE_PUMP 6U +#define SC_AI_WELL_LEVEL_SOURCE 7U +#define SC_AI_DIFFCLK_ROOT 8U +#define SC_AI_DIFFCLK_RPTR 9U +#define SC_AI_DIFFCLK_TERM 10U +#define SC_AI_PHY_LDO 11U +#define SC_AI_OSC24M 12U +#define SC_AI_RC200OSC 13U +#define SC_AI_TEMP_SENSE 14U +#define SC_AI_VDROP_PROCMON 15U +#define SC_AI_LAST 16U +/** @} */ + +/*! + * Analog Interface Modules Types. + */ +typedef uint8_t sc_ai_t; + +/* Configure Subsystems */ + +typedef uint8_t sc_ss_inst_t; + +#define SC_SS_INST_W 1U + +/*! + * Subsystem Type. This type is used to indicate a subsystem. + */ +/** @{ */ +#define SC_SUBSYS_SC 0U +#define SC_SUBSYS_MCU_0 1U +#define SC_SUBSYS_MCU_1 2U +#define SC_SUBSYS_CCI 3U +#define SC_SUBSYS_A53 4U +#define SC_SUBSYS_A72 5U +#define SC_SUBSYS_GPU_0 6U +#define SC_SUBSYS_GPU_1 7U +#define SC_SUBSYS_VPU 8U +#define SC_SUBSYS_DC_0 9U +#define SC_SUBSYS_DC_1 10U +#define SC_SUBSYS_IMG 11U +#define SC_SUBSYS_AUDIO 12U +#define SC_SUBSYS_DMA 13U +#define SC_SUBSYS_CONN 14U +#define SC_SUBSYS_DB 15U +#define SC_SUBSYS_DBLOGIC 16U +#define SC_SUBSYS_DRC_0 17U +#define SC_SUBSYS_DRC_1 18U +#define SC_SUBSYS_LSIO 19U +#define SC_SUBSYS_HSIO 20U +#define SC_SUBSYS_LVDS_0 21U +#define SC_SUBSYS_LVDS_1 22U +#define SC_SUBSYS_CSI_0 23U +#define SC_SUBSYS_CSI_1 24U +#define SC_SUBSYS_HDMI_RX 25U +#define SC_SUBSYS_HDMI 26U +#define SC_SUBSYS_MIPI_0 27U +#define SC_SUBSYS_MIPI_1 28U +#define SC_SUBSYS_LAST SC_SUBSYS_MIPI_1 +#define SC_SUBSYS_W 5U +#define SC_SUBSYS_NA 31U +/** @} */ + +/*! + * Subsystem Type. This type is used to indicate a subsystem. + */ +typedef uint8_t sc_sub_t; + +#define SC_PGP_00 0U +#define SC_PGP_01 1U +#define SC_PGP_02 2U +#define SC_PGP_03 3U +#define SC_PGP_10 4U +#define SC_PGP_11 5U +#define SC_PGP_12 6U +#define SC_PGP_13 7U +#define SC_PGP_20 8U +#define SC_PGP_21 9U +#define SC_PGP_22 10U +#define SC_PGP_23 11U +#define SC_PGP_30 12U +#define SC_PGP_31 13U +#define SC_PGP_32 14U +#define SC_PGP_33 15U + +#define SC_PGP_W 5U +#define SC_PGP_NA 16U + +#define MTR_PWR_PLAN_SEL_SCU 0U +#define MTR_PWR_PLAN_SEL_MCU_0 1U +#define MTR_PWR_PLAN_SEL_MCU_1 2U +#define MTR_PWR_PLAN_SEL_GPU3D_1 3U +#define MTR_PWR_PLAN_SEL_LSIO 4U +#define MTR_PWR_PLAN_SEL_GPU3D_0 5U +#define MTR_PWR_PLAN_SEL_CA53 6U +#define MTR_PWR_PLAN_SEL_DBLOG 7U +#define MTR_PWR_PLAN_SEL_CA72 8U +#define MTR_PWR_PLAN_SEL_HSIO 9U +#define MTR_PWR_PLAN_SEL_DRC_0 10U +#define MTR_PWR_PLAN_SEL_DB 11U +#define MTR_PWR_PLAN_SEL_DC_1 12U +#define MTR_PWR_PLAN_SEL_CONNECTIVITY 13U +#define MTR_PWR_PLAN_SEL_DMA 14U +#define MTR_PWR_PLAN_SEL_MIPI_CSI_0 15U +#define MTR_PWR_PLAN_SEL_MIPI_CSI_1 16U +#define MTR_PWR_PLAN_SEL_DRC_1 17U +#define MTR_PWR_PLAN_SEL_DC_0 18U +#define MTR_PWR_PLAN_SEL_RX_HDMI 19U +#define MTR_PWR_PLAN_SEL_IMAGING 20U +#define MTR_PWR_PLAN_SEL_AUDIO 21U +#define MTR_PWR_PLAN_SEL_DI_HDMI 22U +#define MTR_PWR_PLAN_SEL_DI_MIPI_0 23U +#define MTR_PWR_PLAN_SEL_DI_MIPI_1 24U +#define MTR_PWR_PLAN_SEL_VPU 25U + +#define SC_SS_INFO_INIT \ + {HAS_SS_SC, 0, SC_PGP_32, SC_SUBSYS_NA, 0, 0, SC_DSC_SC}, /* SC_SUBSYS_SC */ \ + {HAS_SS_MCU_0, 0, SC_PGP_33, SC_SUBSYS_NA, 0, 0, SC_DSC_MCU_0}, /* SC_SUBSYS_MCU_0 */ \ + {HAS_SS_MCU_1, 1, SC_PGP_03, SC_SUBSYS_NA, 0, 0, SC_DSC_MCU_1}, /* SC_SUBSYS_MCU_1 */ \ + {HAS_SS_CCI, 0, SC_PGP_31, SC_SUBSYS_NA, 0, 0, SC_DSC_CCI}, /* SC_SUBSYS_CCI */ \ + {HAS_SS_AP_0, 0, SC_PGP_31, SC_SUBSYS_NA, 0, 0, SC_DSC_AP_0}, /* SC_SUBSYS_A53 */ \ + {HAS_SS_AP_1, 0, SC_PGP_31, SC_SUBSYS_NA, 0, 0, SC_DSC_AP_1}, /* SC_SUBSYS_A72 */ \ + {HAS_SS_GPU_0, 0, SC_PGP_10, SC_SUBSYS_NA, 0, 0, SC_DSC_GPU_0}, /* SC_SUBSYS_GPU_0 */ \ + {HAS_SS_GPU_1, 1, SC_PGP_00, SC_SUBSYS_NA, 0, 0, SC_DSC_GPU_1}, /* SC_SUBSYS_GPU_1 */ \ + {HAS_SS_VPU, 0, SC_PGP_01, SC_SUBSYS_NA, 0, 0, SC_DSC_VPU}, /* SC_SUBSYS_VPU */ \ + {HAS_SS_DC_0, 0, SC_PGP_20, SC_SUBSYS_IMG, 24, 0, SC_DSC_DC_0}, /* SC_SUBSYS_DC_0 */ \ + {HAS_SS_DC_1, 1, SC_PGP_30, SC_SUBSYS_IMG, 25, 0, SC_DSC_DC_1}, /* SC_SUBSYS_DC_1 */ \ + {HAS_SS_IMG_0, 0, SC_PGP_21, SC_SUBSYS_NA, 0, 0, SC_DSC_IMG}, /* SC_SUBSYS_IMG */ \ + {HAS_SS_AUDIO, 0, SC_PGP_23, SC_SUBSYS_NA, 0, 0, SC_DSC_AUDIO}, /* SC_SUBSYS_AUDIO */ \ + {HAS_SS_DMA, 0, SC_PGP_22, SC_SUBSYS_NA, 0, 0, SC_DSC_DMA}, /* SC_SUBSYS_DMA */ \ + {HAS_SS_CONN, 0, SC_PGP_02, SC_SUBSYS_NA, 0, 0, SC_DSC_CONN}, /* SC_SUBSYS_CONN */ \ + {HAS_SS_DB, 0, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DB}, /* SC_SUBSYS_DB */ \ + {HAS_SS_DBLOGIC, 0, SC_PGP_13, SC_SUBSYS_NA, 0, 0, SC_DSC_DBLOG}, /* SC_SUBSYS_DBLOGIC */ \ + {HAS_SS_DRC_0, 0, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DRC_0}, /* SC_SUBSYS_DRC_0 */ \ + {HAS_SS_DRC_1, 1, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DRC_1}, /* SC_SUBSYS_DRC_1 */ \ + {HAS_SS_LSIO, 0, SC_PGP_12, SC_SUBSYS_NA, 0, 0, SC_DSC_LSIO}, /* SC_SUBSYS_LSIO */ \ + {HAS_SS_HSIO_0, 0, SC_PGP_11, SC_SUBSYS_NA, 0, 0, SC_DSC_HSIO}, /* SC_SUBSYS_HSIO */ \ + {HAS_SS_LVDS_0, 0, SC_PGP_NA, SC_SUBSYS_DC_0, 12, 0, SC_DSC_DI_LVDS_0}, /* SC_SUBSYS_LVDS_0 */ \ + {HAS_SS_LVDS_1, 1, SC_PGP_NA, SC_SUBSYS_DC_1, 12, 0, SC_DSC_DI_LVDS_1}, /* SC_SUBSYS_LVDS_1 */ \ + {HAS_SS_CSI_0, 0, SC_PGP_NA, SC_SUBSYS_IMG, 21, 18, SC_DSC_CSI_0}, /* SC_SUBSYS_CSI_0 */ \ + {HAS_SS_CSI_1, 1, SC_PGP_NA, SC_SUBSYS_IMG, 22, 19, SC_DSC_CSI_1}, /* SC_SUBSYS_CSI_1 */ \ + {HAS_SS_HDMI_RX, 0, SC_PGP_NA, SC_SUBSYS_IMG, 23, 20, SC_DSC_RX_HDMI}, /* SC_SUBSYS_HDMI_RX */ \ + {HAS_SS_HDMI, 0, SC_PGP_NA, SC_SUBSYS_DC_0, 13, 0, SC_DSC_DI_HDMI}, /* SC_SUBSYS_HDMI */ \ + {HAS_SS_MIPI_0, 0, SC_PGP_NA, SC_SUBSYS_DC_0, 11, 0, SC_DSC_DI_MIPI_0}, /* SC_SUBSYS_MIPI_0 */ \ + {HAS_SS_MIPI_1, 1, SC_PGP_NA, SC_SUBSYS_DC_1, 11, 0, SC_DSC_DI_MIPI_1} /* SC_SUBSYS_MIPI_1 */ + +/*! Number of DB */ +#define SC_NUM_DB 1U + +/*! + * DB Connect Type. Stores a subsystem connection mask. + */ +typedef uint32_t sc_db_connect_t; + +/*! DB connect mask */ +#define SC_DB_CONNECT \ + ( BIT(SC_SUBSYS_SC) \ + | BIT(SC_SUBSYS_MCU_0) \ + | BIT(SC_SUBSYS_MCU_1) \ + | BIT(SC_SUBSYS_CCI) \ + | BIT(SC_SUBSYS_GPU_0) \ + | BIT(SC_SUBSYS_GPU_1) \ + | BIT(SC_SUBSYS_VPU) \ + | BIT(SC_SUBSYS_DC_0) \ + | BIT(SC_SUBSYS_DC_1) \ + | BIT(SC_SUBSYS_IMG) \ + | BIT(SC_SUBSYS_AUDIO) \ + | BIT(SC_SUBSYS_DMA) \ + | BIT(SC_SUBSYS_CONN) \ + | BIT(SC_SUBSYS_DBLOGIC) \ + | BIT(SC_SUBSYS_DRC_0) \ + | BIT(SC_SUBSYS_DRC_1) \ + | BIT(SC_SUBSYS_LSIO) \ + | BIT(SC_SUBSYS_HSIO)) + +/*! Init order of DB (SCU outward) */ +#define SC_DB_INIT \ + {SC_R_DB, SC_SUBSYS_DB, SC_DB_CONNECT} + +#define SC_SS_EP_INIT \ + SS_EP_INIT_SC, /* SC_SUBSYS_SC */ \ + SS_EP_INIT_M4, /* SC_SUBSYS_MCU_0 */ \ + SS_EP_INIT_M4, /* SC_SUBSYS_MCU_1 */ \ + SS_EP_INIT_CCI, /* SC_SUBSYS_CCI */ \ + SS_EP_INIT_A53, /* SC_SUBSYS_A53 */ \ + SS_EP_INIT_A72, /* SC_SUBSYS_A72 */ \ + SS_EP_INIT_GPU, /* SC_SUBSYS_GPU_0 */ \ + SS_EP_INIT_GPU, /* SC_SUBSYS_GPU_1 */ \ + SS_EP_INIT_VPU, /* SC_SUBSYS_VPU */ \ + SS_EP_INIT_DC, /* SC_SUBSYS_DC_0 */ \ + SS_EP_INIT_DC, /* SC_SUBSYS_DC_1 */ \ + SS_EP_INIT_IMG, /* SC_SUBSYS_IMG */ \ + SS_EP_INIT_AUDIO, /* SC_SUBSYS_AUDIO */ \ + SS_EP_INIT_DMA, /* SC_SUBSYS_DMA */ \ + SS_EP_INIT_CONN, /* SC_SUBSYS_CONN */ \ + SS_EP_INIT_DB, /* SC_SUBSYS_DB */ \ + SS_EP_INIT_DBLOGIC, /* SC_SUBSYS_DBLOGIC */ \ + SS_EP_INIT_DRC, /* SC_SUBSYS_DRC_0 */ \ + SS_EP_INIT_DRC, /* SC_SUBSYS_DRC_1 */ \ + SS_EP_INIT_LSIO, /* SC_SUBSYS_LSIO */ \ + SS_EP_INIT_HSIO, /* SC_SUBSYS_HSIO */ \ + SS_EP_INIT_LVDS, /* SC_SUBSYS_LVDS_0 */ \ + SS_EP_INIT_LVDS, /* SC_SUBSYS_LVDS_1 */ \ + SS_EP_INIT_CSI, /* SC_SUBSYS_CSI_0 */ \ + SS_EP_INIT_CSI, /* SC_SUBSYS_CSI_1 */ \ + SS_EP_INIT_HDMI_RX, /* SC_SUBSYS_HDMI_RX */ \ + SS_EP_INIT_HDMI, /* SC_SUBSYS_HDMI */ \ + SS_EP_INIT_MIPI, /* SC_SUBSYS_MIPI_0 */ \ + SS_EP_INIT_MIPI /* SC_SUBSYS_MIPI_1 */ + +#define SC_SS_BASE_INFO_INIT \ + &ss_base_info_sc, /* SC_SUBSYS_SC */ \ + &ss_base_info_m4, /* SC_SUBSYS_MCU_0 */ \ + &ss_base_info_m4, /* SC_SUBSYS_MCU_1 */ \ + &ss_base_info_cci, /* SC_SUBSYS_CCI */ \ + &ss_base_info_a53, /* SC_SUBSYS_A53 */ \ + &ss_base_info_a72, /* SC_SUBSYS_A72 */ \ + &ss_base_info_gpu, /* SC_SUBSYS_GPU_0 */ \ + &ss_base_info_gpu, /* SC_SUBSYS_GPU_1 */ \ + &ss_base_info_vpu, /* SC_SUBSYS_VPU */ \ + &ss_base_info_dc, /* SC_SUBSYS_DC_0 */ \ + &ss_base_info_dc, /* SC_SUBSYS_DC_1 */ \ + &ss_base_info_img, /* SC_SUBSYS_IMG */ \ + &ss_base_info_audio, /* SC_SUBSYS_AUDIO */ \ + &ss_base_info_dma, /* SC_SUBSYS_DMA */ \ + &ss_base_info_conn, /* SC_SUBSYS_CONN */ \ + &ss_base_info_db, /* SC_SUBSYS_DB */ \ + &ss_base_info_dblogic, /* SC_SUBSYS_DBLOGIC */ \ + &ss_base_info_drc, /* SC_SUBSYS_DRC_0 */ \ + &ss_base_info_drc, /* SC_SUBSYS_DRC_1 */ \ + &ss_base_info_lsio, /* SC_SUBSYS_LSIO */ \ + &ss_base_info_hsio, /* SC_SUBSYS_HSIO */ \ + &ss_base_info_lvds, /* SC_SUBSYS_LVDS_0 */ \ + &ss_base_info_lvds, /* SC_SUBSYS_LVDS_1 */ \ + &ss_base_info_csi, /* SC_SUBSYS_CSI_0 */ \ + &ss_base_info_csi, /* SC_SUBSYS_CSI_1 */ \ + &ss_base_info_hdmi_rx, /* SC_SUBSYS_HDMI_RX */ \ + &ss_base_info_hdmi, /* SC_SUBSYS_HDMI */ \ + &ss_base_info_mipi, /* SC_SUBSYS_MIPI_0 */ \ + &ss_base_info_mipi /* SC_SUBSYS_MIPI_1 */ + +#ifdef DEBUG + #define SNAME_INIT \ + "SC", \ + "M4_0", \ + "M4_1", \ + "CCI", \ + "A53", \ + "A72", \ + "GPU_0", \ + "GPU_1", \ + "VPU", \ + "DC_0", \ + "DC_1", \ + "IMG", \ + "AUDIO", \ + "DMA", \ + "CONN", \ + "DB", \ + "DBLOGIC", \ + "DRC_0", \ + "DRC_1", \ + "LSIO", \ + "HSIO", \ + "LVDS_0", \ + "LVDS_1", \ + "CSI_0", \ + "CSI_1", \ + "HDMI_RX", \ + "HDMI", \ + "MIPI_0", \ + "MIPI_1" + + #define RNAME_INIT \ + RNAME_INIT_SC_0 \ + RNAME_INIT_M4_0 \ + RNAME_INIT_M4_1 \ + RNAME_INIT_CCI_0 \ + RNAME_INIT_A53_0 \ + RNAME_INIT_A72_0 \ + RNAME_INIT_GPU_0 \ + RNAME_INIT_GPU_1 \ + RNAME_INIT_VPU_0 \ + RNAME_INIT_DC_0 \ + RNAME_INIT_DC_1 \ + RNAME_INIT_IMG_0 \ + RNAME_INIT_AUDIO_0 \ + RNAME_INIT_DMA_0 \ + RNAME_INIT_CONN_0 \ + RNAME_INIT_DB_0 \ + RNAME_INIT_DBLOGIC_0 \ + RNAME_INIT_DRC_0 \ + RNAME_INIT_DRC_1 \ + RNAME_INIT_LSIO_0 \ + RNAME_INIT_HSIO_0 \ + RNAME_INIT_LVDS_0 \ + RNAME_INIT_LVDS_1 \ + RNAME_INIT_CSI_0 \ + RNAME_INIT_CSI_1 \ + RNAME_INIT_HDMI_RX_0 \ + RNAME_INIT_HDMI_0 \ + RNAME_INIT_MIPI_0 \ + RNAME_INIT_MIPI_1 \ + RNAME_INIT_BRD + +#endif + +#define SC_R_DDR SC_R_DRC_0 +#define SC_R_DDR_PLL SC_R_DRC_0_PLL + +/*! Chip versions */ +#define CHIP_VER_B0 0x1U + +/*! Macro to get JTAG ID */ +#ifndef SIMU + #define JTAG_ID (DSC_SC->GPR_STAT[2].RW & 0x1FFU) +#else + #define JTAG_ID ((CHIP_VER_B0 << 5U) | CHIP_ID_QM) +#endif + +/*! Macros to get chip ID and version */ +#define CHIP_ID ((JTAG_ID >> 0U) & 0x1FU) +#define CHIP_VER ((JTAG_ID >> 5U) & 0xFU) + +/* Define IMG DSSCMIX rate */ +#define SC_IMGMIX SC_400MHZ + +/* Configure Top Level Memory Map */ + +#define SC_MEMMAP_INIT \ + { LSIO_SS_BASE1, 0x1C000000U, 1, 1, 30, 1, 0x00, SC_SUBSYS_LSIO}, \ + { SCU_SS_BASE0, 0x4000000U, 0, 1, 26, 0, 0x00, SC_SUBSYS_SC}, \ + { MCU_0_SS_BASE0, 0x4000000U, 1, 1, 26, 0, 0x00, SC_SUBSYS_MCU_0}, \ + { MCU_1_SS_BASE0, 0x4000000U, 1, 1, 26, 0, 0x00, SC_SUBSYS_MCU_1}, \ + {HSIO_0_SS_BASE1, 0x10000000U, 1, 1, 28, 1, 0x00, SC_SUBSYS_HSIO}, \ + {HSIO_0_SS_BASE2, 0x10000000U, 1, 1, 28, 2, 0x00, SC_SUBSYS_HSIO}, \ + { DDR_BASE0, 0x80000000U, 1, 0, 0, 0, 0x00, SC_SUBSYS_DB}, \ + { LSIO_SS_BASE2, 0x40000000U, 1, 1, 30, 2, 0x00, SC_SUBSYS_LSIO}, \ + { DDR_BASE1, 0x780000000ULL, 1, 0, 0, 0, 0x00, SC_SUBSYS_DB}, \ + { SC_NA, SC_NA, 0, 0, 0, 0, 0, 0} + +#define SC_BOOT_ADDR_INIT \ + {OCRAM_ALIAS_BASE, 0x17FFFU, SC_R_OCRAM, SC_SUBSYS_LSIO}, \ + { OCRAM_BASE, 0x3FFFFU, SC_R_OCRAM, SC_SUBSYS_LSIO}, \ + { FSPI0_MEM_BASE, 0x10000000U, SC_R_FSPI_0, SC_SUBSYS_LSIO}, \ + { TCML_MCU_0, 0x4000000U, SC_R_MCU_0_PID0, SC_SUBSYS_MCU_0}, \ + { TCML_MCU_1, 0x4000000U, SC_R_MCU_1_PID0, SC_SUBSYS_MCU_1}, \ + { DDR_BASE0, 0x80000000U, SC_R_DRC_0, SC_SUBSYS_DRC_0}, \ + { FSPI1_MEM_BASE, 0x40000000U, SC_R_FSPI_1, SC_SUBSYS_LSIO}, \ + { HSIO_0_SS_BASE0, 0x1000000U, SC_R_SATA_0, SC_SUBSYS_HSIO}, \ + { DDR_BASE1, 0x780000000ULL, SC_R_DRC_0, SC_SUBSYS_DRC_0}, \ + { SC_NA, SC_NA, 0U, 0U} + +/* Configure Features */ + +/* Configure RM */ +#define SC_RM_NUM_PARTITION 20U //!< Number of resource partitions +#define SC_RM_NUM_MEMREG 64U //!< Number of memory regions +#define SC_RM_NUM_DOMAIN 16U //!< Number of resource domains + +/*! PLL frequencies */ +#define MIN_PLL_RATE 648000000U +#define MAX_PLL_RATE 1344000000U +#define MIN_HP_PLL_RATE 1250000000U +#define MAX_HP_PLL_RATE 2500000000U +#define MIN_HP_PLL_1P5_RATE 833333333U +#define PLL_RATE_DEN 960000U +#define DIV_FACTOR_NUM 2 +#define DIV_FACTOR_DEN 3 + +/*! Define to indicate that AV PLL should be used for DC */ +#define USE_AVPLL_FOR_DC + +/*! Define for DB clock gating issue. */ +#define TKT309042_WORKAROUND + +/*! Has 28FDSOI in SCFW API */ +#define API_HAS_28FDSOI + +#ifdef SIMU +/*! Support partitioning naming for debug */ +#define HAS_PARTITION_NAMES +#endif + +#if defined(LTO) || defined (SIMU) +/*! Enhanced monitor support */ +#define MONITOR_HAS_CMD_OFF +#define MONITOR_HAS_CMD_MSG +#define MONITOR_HAS_CMD_VDETECT +#define MONITOR_HAS_CMD_WDOG +#define MONITOR_HAS_CMD_PANIC +#define MONITOR_HAS_CMD_MRC +#define MONITOR_HAS_CMD_BOOT +#define MONITOR_HAS_CMD_WAKE +#define MONITOR_HAS_CMD_GRANT +#endif + +/*! Define to use SECO FW */ +#define HAS_SECO_FW + +/*! Define for FW version */ +#define SECO_FW_VERSION ((3UL << 16) | (7UL << 4) | 4UL) + +/*! Define to use MIPI DSI/CSI trim */ +#define HAS_DSI_VOH_TRIM + +/*! Define DDR DATX8 Lanes */ +#define DWC_NO_OF_BYTES 4U + +/*! Define to support ROM function calls */ +#define SC_ROM_FUNC_ADDR 0x00000580U +#define SC_ROM_FUNC_TAG 0xEA90U +#define SC_ROM_FUNC_VER 0x0001U + +/*! Defines for AI temp sensor */ +#define AI_TEMP_RATE 1000U +#define AI_TEMP_NP 1915 +#define AI_TEMP_NT 25 +#define AI_TEMP_PANIC 127 + +/*! + * Define operating points for A53, A72 and GPU. + */ +#define NUM_GPU_OPP 3 +#define NUM_A53_OPP 4 +#define NUM_A72_OPP 4 + +/*! Define to indicate timer services required */ +#define HAS_TIMER_SERVICES + +/*! Number of boot images supported by ROM */ +#define SC_BOOT_MAX_LIST 8U + +/* Define boot cpu and address based on whether or + not we're running the DDR stress test */ +#ifdef M4_BOOT + #define BOOT_CPU SC_R_MCU_0_PID0 + #define BOOT_ADDR 0x000000000ULL + #define BOOT_MU SC_R_MCU_0_MU_1A + #define BOOT_CPU_STARTS 1U + #define BOOT_SRC 0x00040000U + #define BOOT_DST 0x34FE0000U + #define BOOT_SIZE 0x20000U + #define BOOT_FLAGS 0x00000000U +#elif defined(TEST_BOOTTIME) + #define BOOT_CPU SC_R_MCU_0_PID0 + #define BOOT_ADDR 0x000000000ULL + #define BOOT_MU SC_R_MCU_0_MU_1A + #define BOOT_CPU_STARTS 1U + #define BOOT_FLAGS 0x00400000U +#else + #define BOOT_CPU SC_R_AP_0_0 + #define BOOT_ADDR 0x080000000UL + #define BOOT_MU SC_R_MU_0A + #define BOOT_CPU_STARTS 1U + #define BOOT_FLAGS 0x00000000U +#endif + +/* Boot data address */ +#define SC_BOOT_DATA_ADDR_PTR 0x000005F0U +#define SC_BOOT_DATA_ADDR 0x2001FC00U +#define SC_BOOT_DATA2_ADDR 0x2001FD00U + +/*! Rom boot device mappings */ +/** @{ */ +#define ROM_SDHC_0 SC_R_SDHC_0 +#define ROM_SDHC_1 SC_R_SDHC_1 +#define ROM_SDHC_2 SC_R_SDHC_2 +#define ROM_FSPI_0 SC_R_FSPI_0 +#define ROM_FSPI_1 SC_R_FSPI_1 +#define ROM_USB_0 SC_R_USB_0 +#define ROM_USB_1 SC_R_USB_0 +#define ROM_USB_2 SC_R_USB_2 +/** @} */ + +/* Config IROB */ +#define SC_IROB_CONFIG SC_IROB_4K + +/* Configure Tests */ +#define TEST_HSIO0_PCIE SC_R_PCIE_A +#define TEST_HSIO0_SERDES SC_R_SERDES_0 +#define TEST_HSIO0_MATCH_0 SC_R_MATCH_0 +#define SC_P_TEST_PAD SC_P_UART1_RX +#define SC_P_TEST_PAD_HSIC SC_P_USB_HSIC0_DATA +#define SC_P_TEST_PAD_COMP SC_P_COMP_CTL_GPIO_3V3_USB3IO +#define SC_P_TEST_PAD_CONFIG SC_P_CALIBRATION_0_HSIC +#define TEST_LSIO HAS_SS_LSIO +#define TEST_DMA HAS_SS_DMA +#define TEST_BOARD_ALT2 SC_FALSE + +/* Max MRC regions */ +#define SC_MAX_NUM_MEMREG \ +( \ + 16U /* DB */ \ + + 32U /* HSIO */ \ + + 48U /* LSIO */ \ + + 4U /* MCU 0 */ \ + + 4U /* MCU 1 */ \ + + 4U /* SC */ \ +) + +/*! Define to indicate number of CAAM job rings */ +#define SC_CAAM_JR 4U + +/*! Define to indicate number of MU */ +#define SC_SECO_MU 4U + +/* Configure Resources */ +#define SC_NO_DTCP + +/* Define CPU topology */ +#define SOC_NUM_CLUSTER 2U +#define SOC_IDX_AP_0 0U +#define SOC_IDX_AP_1 1U +#define SOC_NUM_AP_0 4U +#define SOC_NUM_AP_1 2U +#define SOC_NUM_DIG_AUD_PLL 2U + +/* Define MCU topology */ +#define SOC_NUM_MCU 2U +#define SOC_IDX_MCU_0 0U +#define SOC_IDX_MCU_1 1U + +/* Define HMP topology */ +#define SOC_NUM_HMP_NODES 5U +#define SOC_HMP_IDX_SCU 0U /* SCU must be index 0 */ +#define SOC_HMP_IDX_MCU_0 1U /* MCU order must follow topology above */ +#define SOC_HMP_IDX_MCU_1 2U +#define SOC_HMP_IDX_AP_0 3U /* AP order must follow topology above */ +#define SOC_HMP_IDX_AP_1 4U +#define SOC_HMP_IDX_MCU SOC_HMP_IDX_MCU_0 +#define SOC_HMP_IDX_AP SOC_HMP_IDX_AP_0 + +/* Define system-level interface topology */ +#define SOC_NUM_SYS_IF 4U /* Number of system-level interfaces */ +#define SOC_SYS_IF_MU_RSRC 5U /* Number of AP -> SCU message unit resources */ +#define SOC_SYS_IF_ICN_RSRC 3U /* Number of interconnect resources */ +#define SOC_SYS_IF_OCMEM_RSRC 3U /* Number of on-chip memory resources */ +#define SOC_SYS_IF_DDR_RSRC 2U /* Number of DDR resources */ +#define SOC_SYS_IF_CPU_HPM SC_PM_PW_MODE_LP /* CPU power mode threshold for HPM */ + +/* Define wakeup bindings */ +#define SOC_GIC_DSC SC_DSC_DBLOG /* DSC for GIC wakeups */ +#define SOC_IRQSTEER_DSC SC_DSC_DBLOG /* DSC for IRQSTEER wakeup */ +#define SOC_GIC_WAKEUP00 REGBIT64(1, 0) /* DSC IRQ for GIC wakeups */ +#define SOC_IRQSTEER_AP_WAKEUP REGBIT64(1, 11) /* DSC IRQ for AP IRQSTEER wakeup */ +#define SOC_IRQSTEER_MCU_WAKEUP REGBIT64(1, 9) /* DSC IRQ for MCU IRQSTEER wakeup */ +#define SOC_WAKEUP_PW_MODE SC_PM_PW_MODE_STBY /* CPU power mode limit for GIC wakeup */ +#define SOC_RESUME_PW_MODE SC_PM_PW_MODE_ON /* CPU power mode for resume */ +#define SOC_MCU_STOPM_PDN 3U /* STOPM >= 3 will power down MCU core */ +#define SOC_MCU_STOPM_MEMSR 3U /* STOPM == 3 will retain memories */ + +/* Defines for DDR training */ +#define DQS_TIMER_DURATION_512 1U /* 512 * tCK = 2048 * (1/1600) = 1 us (round up) */ +#define DQS_TIMER_DURATION_1008 1U /* 1008 * tCK = 1008 * (1/1600) = 1 us (round up) */ +#define DQS_TIMER_DURATION_2048 2U /* 2048 * tCK = 2048 * (1/1600) = 2 us (round up) */ +#define DQS_TIMER_DURATION_8192 6U /* 8192 * tCK = 8192 * (1/1600) = 6 us (round up) */ + +/* Include SS configs */ + +#include "all_config.h" +#include "board/config.h" +#include "handlers_MX8QM.h" /* Device specific handlers */ + +/* Configure Resources */ + +#define SC_NUM_RSRC \ + (SS_NUM_RSRC_SC \ + + SS_NUM_RSRC_M4 \ + + SS_NUM_RSRC_M4 \ + + SS_NUM_RSRC_CCI \ + + SS_NUM_RSRC_A53 \ + + SS_NUM_RSRC_A72 \ + + SS_NUM_RSRC_GPU \ + + SS_NUM_RSRC_GPU \ + + SS_NUM_RSRC_VPU \ + + SS_NUM_RSRC_DC \ + + SS_NUM_RSRC_DC \ + + SS_NUM_RSRC_IMG \ + + SS_NUM_RSRC_AUDIO \ + + SS_NUM_RSRC_DMA \ + + SS_NUM_RSRC_CONN \ + + SS_NUM_RSRC_DB \ + + SS_NUM_RSRC_DBLOGIC \ + + SS_NUM_RSRC_DRC \ + + SS_NUM_RSRC_DRC \ + + SS_NUM_RSRC_LSIO \ + + SS_NUM_RSRC_HSIO \ + + SS_NUM_RSRC_LVDS \ + + SS_NUM_RSRC_LVDS \ + + SS_NUM_RSRC_CSI \ + + SS_NUM_RSRC_CSI \ + + SS_NUM_RSRC_HDMI_RX \ + + SS_NUM_RSRC_HDMI \ + + SS_NUM_RSRC_MIPI \ + + SS_NUM_RSRC_MIPI \ + + BRD_NUM_RSRC_BRD) + +#define SC_PAD_INIT_INIT \ + {SC_P_SIM0_POWER_EN, 3, 0}, \ + {SC_P_SIM0_GPIO0_00, 3, 0}, \ + {SC_P_UART1_RTS_B, 3, 0}, \ + {SC_P_UART1_CTS_B, 3, 0}, \ + {SC_P_PMIC_I2C_SDA, 3, 0}, \ + {SC_P_PMIC_I2C_SCL, 3, 0}, \ + {SC_P_SPI3_SCK, 3, 0}, \ + {SC_P_SPI3_SDO, 3, 0}, \ + {SC_P_SPI3_SDI, 3, 0}, \ + {SC_P_SPI3_CS0, 3, 0}, \ + {SC_P_SAI1_RXC, 3, 0}, \ + {SC_P_SAI1_RXFS, 3, 0}, \ + {SC_P_USB_SS3_TC0, 3, 0}, \ + {SC_P_USB_SS3_TC1, 3, 0}, \ + {SC_P_USB_SS3_TC2, 3, 0}, \ + {SC_P_USB_SS3_TC3, 3, 0}, \ + {0, 0, 0} + +#define SC_ROM_SS_INIT \ + 0, /* SC_SUBSYS_SC */ \ + 1, /* SC_SUBSYS_MCU_0 */ \ + 2, /* SC_SUBSYS_MCU_1 */ \ + 3, /* SC_SUBSYS_CCI */ \ + 4, /* SC_SUBSYS_A53 */ \ + 5, /* SC_SUBSYS_A72 */ \ + 6, /* SC_SUBSYS_GPU_0 */ \ + 7, /* SC_SUBSYS_GPU_1 */ \ + 8, /* SC_SUBSYS_VPU */ \ + 10, /* SC_SUBSYS_DC_0 */ \ + 11, /* SC_SUBSYS_DC_1 */ \ + 12, /* SC_SUBSYS_IMG */ \ + 13, /* SC_SUBSYS_AUDIO */ \ + 14, /* SC_SUBSYS_DMA */ \ + 15, /* SC_SUBSYS_CONN */ \ + 16, /* SC_SUBSYS_DB */ \ + 17, /* SC_SUBSYS_DBLOGIC */ \ + 18, /* SC_SUBSYS_DRC_0 */ \ + 19, /* SC_SUBSYS_DRC_1 */ \ + 20, /* SC_SUBSYS_LSIO */ \ + 21, /* SC_SUBSYS_HSIO */ \ + 22, /* SC_SUBSYS_LVDS_0 */ \ + 23, /* SC_SUBSYS_LVDS_1 */ \ + 24, /* SC_SUBSYS_CSI_0 */ \ + 25, /* SC_SUBSYS_CSI_1 */ \ + 26, /* SC_SUBSYS_HDMI_RX */ \ + 27, /* SC_SUBSYS_HDMI */ \ + 28, /* SC_SUBSYS_MIPI_0 */ \ + 29 /* SC_SUBSYS_MIPI_1 */ + +#endif /* SC_SOC_H */ + diff --git a/platform/config/mx8qm/ss_ver.h b/platform/config/mx8qm/ss_ver.h new file mode 100644 index 0000000..675936f --- /dev/null +++ b/platform/config/mx8qm/ss_ver.h @@ -0,0 +1,76 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing subsystem version defines. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/ss_ver_h.pl */ + +#ifndef SC_PLATFORM_CONFIG_MX8QM_SS_VER_H +#define SC_PLATFORM_CONFIG_MX8QM_SS_VER_H + +/* Defines */ + +#define SS_VER_A53 1 +#define SS_VER_A72 1 +#define SS_VER_AUDIO 1 +#define SS_VER_BASE 1 +#define SS_VER_CCI 1 +#define SS_VER_CONN 1 +#define SS_VER_CSI 1 +#define SS_VER_DB 1 +#define SS_VER_DBLOGIC 1 +#define SS_VER_DC 1 +#define SS_VER_DMA 1 +#define SS_VER_DRC 1 +#define SS_VER_GPU 1 +#define SS_VER_HDMI 1 +#define SS_VER_HDMI_RX 1 +#define SS_VER_HSIO 1 +#define SS_VER_IMG 1 +#define SS_VER_LSIO 2 +#define SS_VER_LVDS 1 +#define SS_VER_M4 1 +#define SS_VER_MIPI 1 +#define SS_VER_SC 2 +#define SS_VER_VPU 3 + +#endif /* SC_PLATFORM_CONFIG_MX8QM_SS_VER_H */ + diff --git a/platform/config/mx8qx/ALL/has_ss.h b/platform/config/mx8qx/ALL/has_ss.h new file mode 100755 index 0000000..feb9406 --- /dev/null +++ b/platform/config/mx8qx/ALL/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 0 +#define HAS_SS_CCI 0 +#define HAS_SS_AP_0 0 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 1 +#define HAS_SS_GPU_0 1 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 1 +#define HAS_SS_DC_0 1 +#define HAS_SS_DC_1 0 +#define HAS_SS_IMG_0 1 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 1 +#define HAS_SS_DMA 0 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 0 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 0 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 1 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 0 +#define HAS_SS_LVDS_1 0 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 1 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 1 +#define HAS_SS_CSI_1 0 +#define HAS_SS_HDMI_RX 0 +#define HAS_SS_HDMI 0 +#define HAS_SS_MIPI_0 1 +#define HAS_SS_MIPI_1 1 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qx/CORES/has_ss.h b/platform/config/mx8qx/CORES/has_ss.h new file mode 100755 index 0000000..c035f79 --- /dev/null +++ b/platform/config/mx8qx/CORES/has_ss.h @@ -0,0 +1,90 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure subsystem availability. + * + */ +/*==========================================================================*/ + +#ifndef SC_HAS_SS_H +#define SC_HAS_SS_H + +/* Subsystem Switches */ + +#define HAS_SS_SC 1 +#define HAS_SS_MCU_0 1 +#define HAS_SS_MCU_1 0 +#define HAS_SS_CCI 0 +#define HAS_SS_AP_0 0 +#define HAS_SS_AP_1 0 +#define HAS_SS_AP_2 1 +#define HAS_SS_GPU_0 0 +#define HAS_SS_GPU_1 0 +#define HAS_SS_VPU 0 +#define HAS_SS_DC_0 0 +#define HAS_SS_DC_1 0 +#define HAS_SS_IMG_0 0 +#define HAS_SS_AUDIO 0 +#define HAS_SS_ADMA 1 +#define HAS_SS_DMA 0 +#define HAS_SS_CONN 1 +#define HAS_SS_DB 1 +#define HAS_SS_DBLOGIC 0 +#define HAS_SS_DRC_0 1 +#define HAS_SS_DRC_1 0 +#define HAS_SS_LSIO 1 +#define HAS_SS_HSLSIO 0 +#define HAS_SS_HSIO_0 1 +#define HAS_SS_HSIO_1 0 +#define HAS_SS_LCD_0 0 +#define HAS_SS_LVDS_0 0 +#define HAS_SS_LVDS_1 0 +#define HAS_SS_LVDS_2 0 +#define HAS_SS_PI_0 0 +#define HAS_SS_PI_1 0 +#define HAS_SS_CSI_0 0 +#define HAS_SS_CSI_1 0 +#define HAS_SS_HDMI_RX 0 +#define HAS_SS_HDMI 0 +#define HAS_SS_MIPI_0 0 +#define HAS_SS_MIPI_1 0 +#define HAS_SS_V2X 0 + +#endif /* SC_HAS_SS_H */ + diff --git a/platform/config/mx8qx/iomuxd.h b/platform/config/mx8qx/iomuxd.h new file mode 100755 index 0000000..faaacb2 --- /dev/null +++ b/platform/config/mx8qx/iomuxd.h @@ -0,0 +1,238 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef IOMUXD_H +#define IOMUXD_H + +#ifndef IOMUXD_REG_BASE + #ifdef SCU_RESOURCES + #define IOMUXD_REG_BASE 0x41F80000U + #else + #define IOMUXD_REG_BASE 0x33F80000U + #endif +#endif + + // NUM RING GROUP PAD | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | +#define IOMUXD__PCIE_CTRL0_PERST_B REG32(IOMUXD_REG_BASE+0x00000000U) // 0 0 0 0 | HSIO.PCIE0.PERST_B | | | | LSIO.GPIO4.IO00 | | | | | +#define IOMUXD__PCIE_CTRL0_CLKREQ_B REG32(IOMUXD_REG_BASE+0x00000040U) // 0 0 0 1 | HSIO.PCIE0.CLKREQ_B | | | | LSIO.GPIO4.IO01 | | | | | +#define IOMUXD__PCIE_CTRL0_WAKE_B REG32(IOMUXD_REG_BASE+0x00000080U) // 0 0 0 2 | HSIO.PCIE0.WAKE_B | | | | LSIO.GPIO4.IO02 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP REG32(IOMUXD_REG_BASE+0x000000C0U) // 0 0 0 3 | | | | | | | | | | +#define IOMUXD__USB_SS3_TC0 REG32(IOMUXD_REG_BASE+0x00000100U) // 0 0 0 4 | ADMA.I2C1.SCL | CONN.USB_OTG1.PWR | CONN.USB_OTG2.PWR | | LSIO.GPIO4.IO03 | | | | | +#define IOMUXD__USB_SS3_TC1 REG32(IOMUXD_REG_BASE+0x00000140U) // 0 0 0 5 | ADMA.I2C1.SCL | CONN.USB_OTG2.PWR | | | LSIO.GPIO4.IO04 | | | | | +#define IOMUXD__USB_SS3_TC2 REG32(IOMUXD_REG_BASE+0x00000180U) // 0 0 0 6 | ADMA.I2C1.SDA | CONN.USB_OTG1.OC | CONN.USB_OTG2.OC | | LSIO.GPIO4.IO05 | | | | | +#define IOMUXD__USB_SS3_TC3 REG32(IOMUXD_REG_BASE+0x000001C0U) // 0 0 0 7 | ADMA.I2C1.SDA | CONN.USB_OTG2.OC | | | LSIO.GPIO4.IO06 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_3V3_USB3IO REG32(IOMUXD_REG_BASE+0x00000200U) // 0 0 0 8 | | | | | | | | | | +#define IOMUXD__EMMC0_CLK REG32(IOMUXD_REG_BASE+0x00020000U) // 1 1 0 0 | CONN.EMMC0.CLK | CONN.NAND.READY_B | | | LSIO.GPIO4.IO07 | | | | | +#define IOMUXD__EMMC0_CMD REG32(IOMUXD_REG_BASE+0x00020040U) // 1 1 0 1 | CONN.EMMC0.CMD | CONN.NAND.DQS | | | LSIO.GPIO4.IO08 | | | | | +#define IOMUXD__EMMC0_DATA0 REG32(IOMUXD_REG_BASE+0x00020080U) // 1 1 0 2 | CONN.EMMC0.DATA0 | CONN.NAND.DATA00 | | | LSIO.GPIO4.IO09 | | | | | +#define IOMUXD__EMMC0_DATA1 REG32(IOMUXD_REG_BASE+0x000200C0U) // 1 1 0 3 | CONN.EMMC0.DATA1 | CONN.NAND.DATA01 | | | LSIO.GPIO4.IO10 | | | | | +#define IOMUXD__EMMC0_DATA2 REG32(IOMUXD_REG_BASE+0x00020100U) // 1 1 0 4 | CONN.EMMC0.DATA2 | CONN.NAND.DATA02 | | | LSIO.GPIO4.IO11 | | | | | +#define IOMUXD__EMMC0_DATA3 REG32(IOMUXD_REG_BASE+0x00020140U) // 1 1 0 5 | CONN.EMMC0.DATA3 | CONN.NAND.DATA03 | | | LSIO.GPIO4.IO12 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 REG32(IOMUXD_REG_BASE+0x00020180U) // 1 1 0 6 | | | | | | | | | | +#define IOMUXD__EMMC0_DATA4 REG32(IOMUXD_REG_BASE+0x000201C0U) // 1 1 0 7 | CONN.EMMC0.DATA4 | CONN.NAND.DATA04 | | CONN.EMMC0.WP | LSIO.GPIO4.IO13 | | | | | +#define IOMUXD__EMMC0_DATA5 REG32(IOMUXD_REG_BASE+0x00020200U) // 1 1 0 8 | CONN.EMMC0.DATA5 | CONN.NAND.DATA05 | | CONN.EMMC0.VSELECT | LSIO.GPIO4.IO14 | | | | | +#define IOMUXD__EMMC0_DATA6 REG32(IOMUXD_REG_BASE+0x00020240U) // 1 1 0 9 | CONN.EMMC0.DATA6 | CONN.NAND.DATA06 | | CONN.MLB.CLK | LSIO.GPIO4.IO15 | | | | | +#define IOMUXD__EMMC0_DATA7 REG32(IOMUXD_REG_BASE+0x00020280U) // 1 1 0 10 | CONN.EMMC0.DATA7 | CONN.NAND.DATA07 | | CONN.MLB.SIG | LSIO.GPIO4.IO16 | | | | | +#define IOMUXD__EMMC0_STROBE REG32(IOMUXD_REG_BASE+0x000202C0U) // 1 1 0 11 | CONN.EMMC0.STROBE | CONN.NAND.CLE | | CONN.MLB.DATA | LSIO.GPIO4.IO17 | | | | | +#define IOMUXD__EMMC0_RESET_B REG32(IOMUXD_REG_BASE+0x00020300U) // 1 1 0 12 | CONN.EMMC0.RESET_B | CONN.NAND.WP_B | | | LSIO.GPIO4.IO18 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 REG32(IOMUXD_REG_BASE+0x00020340U) // 1 1 0 13 | | | | | | | | | | +#define IOMUXD__USDHC1_RESET_B REG32(IOMUXD_REG_BASE+0x00020380U) // 1 1 0 14 | CONN.USDHC1.RESET_B | CONN.NAND.RE_N | ADMA.SPI2.SCK | | LSIO.GPIO4.IO19 | | | | | +#define IOMUXD__USDHC1_VSELECT REG32(IOMUXD_REG_BASE+0x00021000U) // 2 1 1 0 | CONN.USDHC1.VSELECT | CONN.NAND.RE_P | ADMA.SPI2.SDO | CONN.NAND.RE_B | LSIO.GPIO4.IO20 | | | | | +#define IOMUXD__IOMUXD_CTL_NAND_RE_P_N REG32(IOMUXD_REG_BASE+0x00021040U) // 2 1 1 1 | | | | | | | | | | +#define IOMUXD__USDHC1_WP REG32(IOMUXD_REG_BASE+0x00021080U) // 2 1 1 2 | CONN.USDHC1.WP | CONN.NAND.DQS_N | ADMA.SPI2.SDI | | LSIO.GPIO4.IO21 | | | | | +#define IOMUXD__USDHC1_CD_B REG32(IOMUXD_REG_BASE+0x000210C0U) // 2 1 1 3 | CONN.USDHC1.CD_B | CONN.NAND.DQS_P | ADMA.SPI2.CS0 | CONN.NAND.DQS | LSIO.GPIO4.IO22 | | | | | +#define IOMUXD__IOMUXD_CTL_NAND_DQS_P_N REG32(IOMUXD_REG_BASE+0x00021100U) // 2 1 1 4 | | | | | | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP REG32(IOMUXD_REG_BASE+0x00021140U) // 2 1 1 5 | | | | | | | | | | +#define IOMUXD__USDHC1_CLK REG32(IOMUXD_REG_BASE+0x00021180U) // 2 1 1 6 | CONN.USDHC1.CLK | | ADMA.UART3.RX | | LSIO.GPIO4.IO23 | | | | | +#define IOMUXD__USDHC1_CMD REG32(IOMUXD_REG_BASE+0x000211C0U) // 2 1 1 7 | CONN.USDHC1.CMD | CONN.NAND.CE0_B | ADMA.MQS.R | | LSIO.GPIO4.IO24 | | | | | +#define IOMUXD__USDHC1_DATA0 REG32(IOMUXD_REG_BASE+0x00021200U) // 2 1 1 8 | CONN.USDHC1.DATA0 | CONN.NAND.CE1_B | ADMA.MQS.L | | LSIO.GPIO4.IO25 | | | | | +#define IOMUXD__USDHC1_DATA1 REG32(IOMUXD_REG_BASE+0x00021240U) // 2 1 1 9 | CONN.USDHC1.DATA1 | CONN.NAND.RE_B | ADMA.UART3.TX | | LSIO.GPIO4.IO26 | | | | | +#define IOMUXD__USDHC1_DATA2 REG32(IOMUXD_REG_BASE+0x00021280U) // 2 1 1 10 | CONN.USDHC1.DATA2 | CONN.NAND.WE_B | ADMA.UART3.CTS_B | | LSIO.GPIO4.IO27 | | | | | +#define IOMUXD__USDHC1_DATA3 REG32(IOMUXD_REG_BASE+0x000212C0U) // 2 1 1 11 | CONN.USDHC1.DATA3 | CONN.NAND.ALE | ADMA.UART3.RTS_B | | LSIO.GPIO4.IO28 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 REG32(IOMUXD_REG_BASE+0x00021300U) // 2 1 1 12 | | | | | | | | | | +#define IOMUXD__ENET0_RGMII_TXC REG32(IOMUXD_REG_BASE+0x00021340U) // 2 1 1 13 | CONN.ENET0.RGMII_TXC | CONN.ENET0.RCLK50M_OUT | CONN.ENET0.RCLK50M_IN | CONN.NAND.CE1_B | LSIO.GPIO4.IO29 | | | | | +#define IOMUXD__ENET0_RGMII_TX_CTL REG32(IOMUXD_REG_BASE+0x00021380U) // 2 1 1 14 | CONN.ENET0.RGMII_TX_CTL | | | CONN.USDHC1.RESET_B | LSIO.GPIO4.IO30 | | | | | +#define IOMUXD__ENET0_RGMII_TXD0 REG32(IOMUXD_REG_BASE+0x00022000U) // 3 1 2 0 | CONN.ENET0.RGMII_TXD0 | | | CONN.USDHC1.VSELECT | LSIO.GPIO4.IO31 | | | | | +#define IOMUXD__ENET0_RGMII_TXD1 REG32(IOMUXD_REG_BASE+0x00022040U) // 3 1 2 1 | CONN.ENET0.RGMII_TXD1 | | | CONN.USDHC1.WP | LSIO.GPIO5.IO00 | | | | | +#define IOMUXD__ENET0_RGMII_TXD2 REG32(IOMUXD_REG_BASE+0x00022080U) // 3 1 2 2 | CONN.ENET0.RGMII_TXD2 | CONN.MLB.CLK | CONN.NAND.CE0_B | CONN.USDHC1.CD_B | LSIO.GPIO5.IO01 | | | | | +#define IOMUXD__ENET0_RGMII_TXD3 REG32(IOMUXD_REG_BASE+0x000220C0U) // 3 1 2 3 | CONN.ENET0.RGMII_TXD3 | CONN.MLB.SIG | CONN.NAND.RE_B | | LSIO.GPIO5.IO02 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 REG32(IOMUXD_REG_BASE+0x00022100U) // 3 1 2 4 | | | | | | | | | | +#define IOMUXD__ENET0_RGMII_RXC REG32(IOMUXD_REG_BASE+0x00022140U) // 3 1 2 5 | CONN.ENET0.RGMII_RXC | CONN.MLB.DATA | CONN.NAND.WE_B | CONN.USDHC1.CLK | LSIO.GPIO5.IO03 | | | | | +#define IOMUXD__ENET0_RGMII_RX_CTL REG32(IOMUXD_REG_BASE+0x00022180U) // 3 1 2 6 | CONN.ENET0.RGMII_RX_CTL | | | CONN.USDHC1.CMD | LSIO.GPIO5.IO04 | | | | | +#define IOMUXD__ENET0_RGMII_RXD0 REG32(IOMUXD_REG_BASE+0x000221C0U) // 3 1 2 7 | CONN.ENET0.RGMII_RXD0 | | | CONN.USDHC1.DATA0 | LSIO.GPIO5.IO05 | | | | | +#define IOMUXD__ENET0_RGMII_RXD1 REG32(IOMUXD_REG_BASE+0x00022200U) // 3 1 2 8 | CONN.ENET0.RGMII_RXD1 | | | CONN.USDHC1.DATA1 | LSIO.GPIO5.IO06 | | | | | +#define IOMUXD__ENET0_RGMII_RXD2 REG32(IOMUXD_REG_BASE+0x00022240U) // 3 1 2 9 | CONN.ENET0.RGMII_RXD2 | CONN.ENET0.RMII_RX_ER | | CONN.USDHC1.DATA2 | LSIO.GPIO5.IO07 | | | | | +#define IOMUXD__ENET0_RGMII_RXD3 REG32(IOMUXD_REG_BASE+0x00022280U) // 3 1 2 10 | CONN.ENET0.RGMII_RXD3 | | CONN.NAND.ALE | CONN.USDHC1.DATA3 | LSIO.GPIO5.IO08 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 REG32(IOMUXD_REG_BASE+0x000222C0U) // 3 1 2 11 | | | | | | | | | | +#define IOMUXD__ENET0_REFCLK_125M_25M REG32(IOMUXD_REG_BASE+0x00022300U) // 3 1 2 12 | CONN.ENET0.REFCLK_125M_25M | CONN.ENET0.PPS | CONN.ENET1.PPS | | LSIO.GPIO5.IO09 | | | | | +#define IOMUXD__ENET0_MDIO REG32(IOMUXD_REG_BASE+0x00023000U) // 4 1 3 0 | CONN.ENET0.MDIO | ADMA.I2C3.SDA | CONN.ENET1.MDIO | | LSIO.GPIO5.IO10 | | | | | +#define IOMUXD__ENET0_MDC REG32(IOMUXD_REG_BASE+0x00023040U) // 4 1 3 1 | CONN.ENET0.MDC | ADMA.I2C3.SCL | CONN.ENET1.MDC | | LSIO.GPIO5.IO11 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT REG32(IOMUXD_REG_BASE+0x00023080U) // 4 1 3 2 | | | | | | | | | | +#define IOMUXD__ESAI0_FSR REG32(IOMUXD_REG_BASE+0x000230C0U) // 4 1 3 3 | ADMA.ESAI0.FSR | CONN.ENET1.RCLK50M_OUT | ADMA.LCDIF.D00 | CONN.ENET1.RGMII_TXC | CONN.ENET1.RCLK50M_IN | | | | | +#define IOMUXD__ESAI0_FST REG32(IOMUXD_REG_BASE+0x00023100U) // 4 1 3 4 | ADMA.ESAI0.FST | CONN.MLB.CLK | ADMA.LCDIF.D01 | CONN.ENET1.RGMII_TXD2 | LSIO.GPIO0.IO01 | | | | | +#define IOMUXD__ESAI0_SCKR REG32(IOMUXD_REG_BASE+0x00023140U) // 4 1 3 5 | ADMA.ESAI0.SCKR | | ADMA.LCDIF.D02 | CONN.ENET1.RGMII_TX_CTL | LSIO.GPIO0.IO02 | | | | | +#define IOMUXD__ESAI0_SCKT REG32(IOMUXD_REG_BASE+0x00023180U) // 4 1 3 6 | ADMA.ESAI0.SCKT | CONN.MLB.SIG | ADMA.LCDIF.D03 | CONN.ENET1.RGMII_TXD3 | LSIO.GPIO0.IO03 | | | | | +#define IOMUXD__ESAI0_TX0 REG32(IOMUXD_REG_BASE+0x000231C0U) // 4 1 3 7 | ADMA.ESAI0.TX0 | CONN.MLB.DATA | ADMA.LCDIF.D04 | CONN.ENET1.RGMII_RXC | LSIO.GPIO0.IO04 | | | | | +#define IOMUXD__ESAI0_TX1 REG32(IOMUXD_REG_BASE+0x00023200U) // 4 1 3 8 | ADMA.ESAI0.TX1 | | ADMA.LCDIF.D05 | CONN.ENET1.RGMII_RXD3 | LSIO.GPIO0.IO05 | | | | | +#define IOMUXD__ESAI0_TX2_RX3 REG32(IOMUXD_REG_BASE+0x00023240U) // 4 1 3 9 | ADMA.ESAI0.TX2_RX3 | CONN.ENET1.RMII_RX_ER | ADMA.LCDIF.D06 | CONN.ENET1.RGMII_RXD2 | LSIO.GPIO0.IO06 | | | | | +#define IOMUXD__ESAI0_TX3_RX2 REG32(IOMUXD_REG_BASE+0x00023280U) // 4 1 3 10 | ADMA.ESAI0.TX3_RX2 | | ADMA.LCDIF.D07 | CONN.ENET1.RGMII_RXD1 | LSIO.GPIO0.IO07 | | | | | +#define IOMUXD__ESAI0_TX4_RX1 REG32(IOMUXD_REG_BASE+0x000232C0U) // 4 1 3 11 | ADMA.ESAI0.TX4_RX1 | | ADMA.LCDIF.D08 | CONN.ENET1.RGMII_TXD0 | LSIO.GPIO0.IO08 | | | | | +#define IOMUXD__ESAI0_TX5_RX0 REG32(IOMUXD_REG_BASE+0x00023300U) // 4 1 3 12 | ADMA.ESAI0.TX5_RX0 | | ADMA.LCDIF.D09 | CONN.ENET1.RGMII_TXD1 | LSIO.GPIO0.IO09 | | | | | +#define IOMUXD__SPDIF0_RX REG32(IOMUXD_REG_BASE+0x00023340U) // 4 1 3 13 | ADMA.SPDIF0.RX | ADMA.MQS.R | ADMA.LCDIF.D10 | CONN.ENET1.RGMII_RXD0 | LSIO.GPIO0.IO10 | | | | | +#define IOMUXD__SPDIF0_TX REG32(IOMUXD_REG_BASE+0x00023380U) // 4 1 3 14 | ADMA.SPDIF0.TX | ADMA.MQS.L | ADMA.LCDIF.D11 | CONN.ENET1.RGMII_RX_CTL | LSIO.GPIO0.IO11 | | | | | +#define IOMUXD__SPDIF0_EXT_CLK REG32(IOMUXD_REG_BASE+0x00024000U) // 5 1 4 0 | ADMA.SPDIF0.EXT_CLK | | ADMA.LCDIF.D12 | CONN.ENET1.REFCLK_125M_25M | LSIO.GPIO0.IO12 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB REG32(IOMUXD_REG_BASE+0x00024040U) // 5 1 4 1 | | | | | | | | | | +#define IOMUXD__SPI3_SCK REG32(IOMUXD_REG_BASE+0x00024080U) // 5 1 4 2 | ADMA.SPI3.SCK | | ADMA.LCDIF.D13 | | LSIO.GPIO0.IO13 | | | | | +#define IOMUXD__SPI3_SDO REG32(IOMUXD_REG_BASE+0x000240C0U) // 5 1 4 3 | ADMA.SPI3.SDO | | ADMA.LCDIF.D14 | | LSIO.GPIO0.IO14 | | | | | +#define IOMUXD__SPI3_SDI REG32(IOMUXD_REG_BASE+0x00024100U) // 5 1 4 4 | ADMA.SPI3.SDI | | ADMA.LCDIF.D15 | | LSIO.GPIO0.IO15 | | | | | +#define IOMUXD__SPI3_CS0 REG32(IOMUXD_REG_BASE+0x00024140U) // 5 1 4 5 | ADMA.SPI3.CS0 | ADMA.ACM.MCLK_OUT1 | ADMA.LCDIF.HSYNC | | LSIO.GPIO0.IO16 | | | | | +#define IOMUXD__SPI3_CS1 REG32(IOMUXD_REG_BASE+0x00024180U) // 5 1 4 6 | ADMA.SPI3.CS1 | ADMA.I2C3.SCL | ADMA.LCDIF.RESET | ADMA.SPI2.CS0 | ADMA.LCDIF.D16 | | | | | +#define IOMUXD__MCLK_IN1 REG32(IOMUXD_REG_BASE+0x000241C0U) // 5 1 4 7 | ADMA.ACM.MCLK_IN1 | ADMA.I2C3.SDA | ADMA.LCDIF.EN | ADMA.SPI2.SCK | ADMA.LCDIF.D17 | | | | | +#define IOMUXD__MCLK_IN0 REG32(IOMUXD_REG_BASE+0x00024200U) // 5 1 4 8 | ADMA.ACM.MCLK_IN0 | ADMA.ESAI0.RX_HF_CLK | ADMA.LCDIF.VSYNC | ADMA.SPI2.SDI | LSIO.GPIO0.IO19 | | | | | +#define IOMUXD__MCLK_OUT0 REG32(IOMUXD_REG_BASE+0x00024240U) // 5 1 4 9 | ADMA.ACM.MCLK_OUT0 | ADMA.ESAI0.TX_HF_CLK | ADMA.LCDIF.CLK | ADMA.SPI2.SDO | LSIO.GPIO0.IO20 | | | | | +#define IOMUXD__UART1_TX REG32(IOMUXD_REG_BASE+0x00024280U) // 5 1 4 10 | ADMA.UART1.TX | LSIO.PWM0.OUT | LSIO.GPT0.CAPTURE | | LSIO.GPIO0.IO21 | | | | | +#define IOMUXD__UART1_RX REG32(IOMUXD_REG_BASE+0x000242C0U) // 5 1 4 11 | ADMA.UART1.RX | LSIO.PWM1.OUT | LSIO.GPT0.COMPARE | LSIO.GPT1.CLK | LSIO.GPIO0.IO22 | | | | | +#define IOMUXD__UART1_RTS_B REG32(IOMUXD_REG_BASE+0x00024300U) // 5 1 4 12 | ADMA.UART1.RTS_B | LSIO.PWM2.OUT | ADMA.LCDIF.D16 | LSIO.GPT1.CAPTURE | LSIO.GPT0.CLK | | | | | +#define IOMUXD__UART1_CTS_B REG32(IOMUXD_REG_BASE+0x00024340U) // 5 1 4 13 | ADMA.UART1.CTS_B | LSIO.PWM3.OUT | ADMA.LCDIF.D17 | LSIO.GPT1.COMPARE | LSIO.GPIO0.IO24 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK REG32(IOMUXD_REG_BASE+0x00024380U) // 5 1 4 14 | | | | | | | | | | +#define IOMUXD__SAI0_TXD REG32(IOMUXD_REG_BASE+0x00040000U) // 6 2 0 0 | ADMA.SAI0.TXD | ADMA.SAI1.RXC | ADMA.SPI1.SDO | ADMA.LCDIF.D18 | LSIO.GPIO0.IO25 | | | | | +#define IOMUXD__SAI0_TXC REG32(IOMUXD_REG_BASE+0x00040040U) // 6 2 0 1 | ADMA.SAI0.TXC | ADMA.SAI1.TXD | ADMA.SPI1.SDI | ADMA.LCDIF.D19 | LSIO.GPIO0.IO26 | | | | | +#define IOMUXD__SAI0_RXD REG32(IOMUXD_REG_BASE+0x00040080U) // 6 2 0 2 | ADMA.SAI0.RXD | ADMA.SAI1.RXFS | ADMA.SPI1.CS0 | ADMA.LCDIF.D20 | LSIO.GPIO0.IO27 | | | | | +#define IOMUXD__SAI0_TXFS REG32(IOMUXD_REG_BASE+0x000400C0U) // 6 2 0 3 | ADMA.SAI0.TXFS | ADMA.SPI2.CS1 | ADMA.SPI1.SCK | | LSIO.GPIO0.IO28 | | | | | +#define IOMUXD__SAI1_RXD REG32(IOMUXD_REG_BASE+0x00040100U) // 6 2 0 4 | ADMA.SAI1.RXD | ADMA.SAI0.RXFS | ADMA.SPI1.CS1 | ADMA.LCDIF.D21 | LSIO.GPIO0.IO29 | | | | | +#define IOMUXD__SAI1_RXC REG32(IOMUXD_REG_BASE+0x00040140U) // 6 2 0 5 | ADMA.SAI1.RXC | ADMA.SAI1.TXC | | ADMA.LCDIF.D22 | LSIO.GPIO0.IO30 | | | | | +#define IOMUXD__SAI1_RXFS REG32(IOMUXD_REG_BASE+0x00040180U) // 6 2 0 6 | ADMA.SAI1.RXFS | ADMA.SAI1.TXFS | | ADMA.LCDIF.D23 | LSIO.GPIO0.IO31 | | | | | +#define IOMUXD__SPI2_CS0 REG32(IOMUXD_REG_BASE+0x000401C0U) // 6 2 0 7 | ADMA.SPI2.CS0 | | | | LSIO.GPIO1.IO00 | | | | | +#define IOMUXD__SPI2_SDO REG32(IOMUXD_REG_BASE+0x00040200U) // 6 2 0 8 | ADMA.SPI2.SDO | | | | LSIO.GPIO1.IO01 | | | | | +#define IOMUXD__SPI2_SDI REG32(IOMUXD_REG_BASE+0x00040240U) // 6 2 0 9 | ADMA.SPI2.SDI | | | | LSIO.GPIO1.IO02 | | | | | +#define IOMUXD__SPI2_SCK REG32(IOMUXD_REG_BASE+0x00040280U) // 6 2 0 10 | ADMA.SPI2.SCK | | | | LSIO.GPIO1.IO03 | | | | | +#define IOMUXD__SPI0_SCK REG32(IOMUXD_REG_BASE+0x000402C0U) // 6 2 0 11 | ADMA.SPI0.SCK | ADMA.SAI0.TXC | M40.I2C0.SCL | M40.GPIO0.IO00 | LSIO.GPIO1.IO04 | | | | | +#define IOMUXD__SPI0_SDI REG32(IOMUXD_REG_BASE+0x00040300U) // 6 2 0 12 | ADMA.SPI0.SDI | ADMA.SAI0.TXD | M40.TPM0.CH0 | M40.GPIO0.IO02 | LSIO.GPIO1.IO05 | | | | | +#define IOMUXD__SPI0_SDO REG32(IOMUXD_REG_BASE+0x00040340U) // 6 2 0 13 | ADMA.SPI0.SDO | ADMA.SAI0.TXFS | M40.I2C0.SDA | M40.GPIO0.IO01 | LSIO.GPIO1.IO06 | | | | | +#define IOMUXD__SPI0_CS1 REG32(IOMUXD_REG_BASE+0x00040380U) // 6 2 0 14 | ADMA.SPI0.CS1 | ADMA.SAI0.RXC | ADMA.SAI1.TXD | ADMA.LCD_PWM0.OUT | LSIO.GPIO1.IO07 | | | | | +#define IOMUXD__SPI0_CS0 REG32(IOMUXD_REG_BASE+0x00041000U) // 7 2 1 0 | ADMA.SPI0.CS0 | ADMA.SAI0.RXD | M40.TPM0.CH1 | M40.GPIO0.IO03 | LSIO.GPIO1.IO08 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT REG32(IOMUXD_REG_BASE+0x00041040U) // 7 2 1 1 | | | | | | | | | | +#define IOMUXD__ADC_IN1 REG32(IOMUXD_REG_BASE+0x00041080U) // 7 2 1 2 | ADMA.ADC.IN1 | M40.I2C0.SDA | M40.GPIO0.IO01 | | LSIO.GPIO1.IO09 | | | | | +#define IOMUXD__ADC_IN0 REG32(IOMUXD_REG_BASE+0x000410C0U) // 7 2 1 3 | ADMA.ADC.IN0 | M40.I2C0.SCL | M40.GPIO0.IO00 | | LSIO.GPIO1.IO10 | | | | | +#define IOMUXD__ADC_IN3 REG32(IOMUXD_REG_BASE+0x00041100U) // 7 2 1 4 | ADMA.ADC.IN3 | M40.UART0.TX | M40.GPIO0.IO03 | ADMA.ACM.MCLK_OUT0 | LSIO.GPIO1.IO11 | | | | | +#define IOMUXD__ADC_IN2 REG32(IOMUXD_REG_BASE+0x00041140U) // 7 2 1 5 | ADMA.ADC.IN2 | M40.UART0.RX | M40.GPIO0.IO02 | ADMA.ACM.MCLK_IN0 | LSIO.GPIO1.IO12 | | | | | +#define IOMUXD__ADC_IN5 REG32(IOMUXD_REG_BASE+0x00041180U) // 7 2 1 6 | ADMA.ADC.IN5 | M40.TPM0.CH1 | M40.GPIO0.IO05 | | LSIO.GPIO1.IO13 | | | | | +#define IOMUXD__ADC_IN4 REG32(IOMUXD_REG_BASE+0x000411C0U) // 7 2 1 7 | ADMA.ADC.IN4 | M40.TPM0.CH0 | M40.GPIO0.IO04 | | LSIO.GPIO1.IO14 | | | | | +#define IOMUXD__FLEXCAN0_RX REG32(IOMUXD_REG_BASE+0x00041200U) // 7 2 1 8 | ADMA.FLEXCAN0.RX | ADMA.SAI2.RXC | ADMA.UART0.RTS_B | ADMA.SAI1.TXC | LSIO.GPIO1.IO15 | | | | | +#define IOMUXD__FLEXCAN0_TX REG32(IOMUXD_REG_BASE+0x00041240U) // 7 2 1 9 | ADMA.FLEXCAN0.TX | ADMA.SAI2.RXD | ADMA.UART0.CTS_B | ADMA.SAI1.TXFS | LSIO.GPIO1.IO16 | | | | | +#define IOMUXD__FLEXCAN1_RX REG32(IOMUXD_REG_BASE+0x00041280U) // 7 2 1 10 | ADMA.FLEXCAN1.RX | ADMA.SAI2.RXFS | ADMA.FTM.CH2 | ADMA.SAI1.TXD | LSIO.GPIO1.IO17 | | | | | +#define IOMUXD__FLEXCAN1_TX REG32(IOMUXD_REG_BASE+0x000412C0U) // 7 2 1 11 | ADMA.FLEXCAN1.TX | ADMA.SAI3.RXC | ADMA.DMA0.REQ_IN0 | ADMA.SAI1.RXD | LSIO.GPIO1.IO18 | | | | | +#define IOMUXD__FLEXCAN2_RX REG32(IOMUXD_REG_BASE+0x00041300U) // 7 2 1 12 | ADMA.FLEXCAN2.RX | ADMA.SAI3.RXD | ADMA.UART3.RX | ADMA.SAI1.RXFS | LSIO.GPIO1.IO19 | | | | | +#define IOMUXD__FLEXCAN2_TX REG32(IOMUXD_REG_BASE+0x00041340U) // 7 2 1 13 | ADMA.FLEXCAN2.TX | ADMA.SAI3.RXFS | ADMA.UART3.TX | ADMA.SAI1.RXC | LSIO.GPIO1.IO20 | | | | | +#define IOMUXD__UART0_RX REG32(IOMUXD_REG_BASE+0x00041380U) // 7 2 1 14 | ADMA.UART0.RX | ADMA.MQS.R | ADMA.FLEXCAN0.RX | SCU.UART0.RX | LSIO.GPIO1.IO21 | | | | | +#define IOMUXD__UART0_TX REG32(IOMUXD_REG_BASE+0x00042000U) // 8 2 2 0 | ADMA.UART0.TX | ADMA.MQS.L | ADMA.FLEXCAN0.TX | SCU.UART0.TX | LSIO.GPIO1.IO22 | | | | | +#define IOMUXD__UART2_TX REG32(IOMUXD_REG_BASE+0x00042040U) // 8 2 2 1 | ADMA.UART2.TX | ADMA.FTM.CH1 | ADMA.FLEXCAN1.TX | | LSIO.GPIO1.IO23 | | | | | +#define IOMUXD__UART2_RX REG32(IOMUXD_REG_BASE+0x00042080U) // 8 2 2 2 | ADMA.UART2.RX | ADMA.FTM.CH0 | ADMA.FLEXCAN1.RX | | LSIO.GPIO1.IO24 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH REG32(IOMUXD_REG_BASE+0x000420C0U) // 8 2 2 3 | | | | | | | | | | +#define IOMUXD__MIPI_DSI0_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00042100U) // 8 2 2 4 | MIPI_DSI0.I2C0.SCL | MIPI_DSI1.GPIO0.IO02 | | | LSIO.GPIO1.IO25 | | | | | +#define IOMUXD__MIPI_DSI0_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00042140U) // 8 2 2 5 | MIPI_DSI0.I2C0.SDA | MIPI_DSI1.GPIO0.IO03 | | | LSIO.GPIO1.IO26 | | | | | +#define IOMUXD__MIPI_DSI0_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00042180U) // 8 2 2 6 | MIPI_DSI0.GPIO0.IO00 | ADMA.I2C1.SCL | MIPI_DSI0.PWM0.OUT | | LSIO.GPIO1.IO27 | | | | | +#define IOMUXD__MIPI_DSI0_GPIO0_01 REG32(IOMUXD_REG_BASE+0x000421C0U) // 8 2 2 7 | MIPI_DSI0.GPIO0.IO01 | ADMA.I2C1.SDA | | | LSIO.GPIO1.IO28 | | | | | +#define IOMUXD__MIPI_DSI1_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00042200U) // 8 2 2 8 | MIPI_DSI1.I2C0.SCL | MIPI_DSI0.GPIO0.IO02 | | | LSIO.GPIO1.IO29 | | | | | +#define IOMUXD__MIPI_DSI1_I2C0_SDA REG32(IOMUXD_REG_BASE+0x00042240U) // 8 2 2 9 | MIPI_DSI1.I2C0.SDA | MIPI_DSI0.GPIO0.IO03 | | | LSIO.GPIO1.IO30 | | | | | +#define IOMUXD__MIPI_DSI1_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00042280U) // 8 2 2 10 | MIPI_DSI1.GPIO0.IO00 | ADMA.I2C2.SCL | MIPI_DSI1.PWM0.OUT | | LSIO.GPIO1.IO31 | | | | | +#define IOMUXD__MIPI_DSI1_GPIO0_01 REG32(IOMUXD_REG_BASE+0x000422C0U) // 8 2 2 11 | MIPI_DSI1.GPIO0.IO01 | ADMA.I2C2.SDA | | | LSIO.GPIO2.IO00 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO REG32(IOMUXD_REG_BASE+0x00042300U) // 8 2 2 12 | | | | | | | | | | +#define IOMUXD__JTAG_TRST_B REG32(IOMUXD_REG_BASE+0x00042340U) // 8 2 2 13 | SCU.JTAG.TRST_B | SCU.WDOG0.WDOG_OUT | | | | | | | | +#define IOMUXD__PMIC_I2C_SCL REG32(IOMUXD_REG_BASE+0x00042380U) // 8 2 2 14 | SCU.PMIC_I2C.SCL | SCU.GPIO0.IOXX_PMIC_A35_ON | | | LSIO.GPIO2.IO01 | | | | | +#define IOMUXD__PMIC_I2C_SDA REG32(IOMUXD_REG_BASE+0x00043000U) // 9 2 3 0 | SCU.PMIC_I2C.SDA | SCU.GPIO0.IOXX_PMIC_GPU_ON | | | LSIO.GPIO2.IO02 | | | | | +#define IOMUXD__PMIC_INT_B REG32(IOMUXD_REG_BASE+0x00043040U) // 9 2 3 1 | SCU.DSC.PMIC_INT_B | | | | | | | | | +#define IOMUXD__SCU_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00043080U) // 9 2 3 2 | SCU.GPIO0.IO00 | SCU.UART0.RX | M40.UART0.RX | ADMA.UART3.RX | LSIO.GPIO2.IO03 | | | | | +#define IOMUXD__SCU_GPIO0_01 REG32(IOMUXD_REG_BASE+0x000430C0U) // 9 2 3 3 | SCU.GPIO0.IO01 | SCU.UART0.TX | M40.UART0.TX | ADMA.UART3.TX | SCU.WDOG0.WDOG_OUT | | | | | +#define IOMUXD__SCU_PMIC_STANDBY REG32(IOMUXD_REG_BASE+0x00043100U) // 9 2 3 4 | SCU.DSC.PMIC_STANDBY | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE0 REG32(IOMUXD_REG_BASE+0x00043140U) // 9 2 3 5 | SCU.DSC.BOOT_MODE0 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE1 REG32(IOMUXD_REG_BASE+0x00043180U) // 9 2 3 6 | SCU.DSC.BOOT_MODE1 | | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE2 REG32(IOMUXD_REG_BASE+0x000431C0U) // 9 2 3 7 | SCU.DSC.BOOT_MODE2 | SCU.PMIC_I2C.SDA | | | | | | | | +#define IOMUXD__SCU_BOOT_MODE3 REG32(IOMUXD_REG_BASE+0x00043200U) // 9 2 3 8 | SCU.DSC.BOOT_MODE3 | SCU.PMIC_I2C.SCL | | SCU.DSC.RTC_CLOCK_OUTPUT_32K | | | | | | +#define IOMUXD__CSI_D00 REG32(IOMUXD_REG_BASE+0x00043240U) // 9 2 3 9 | CI_PI.D02 | | ADMA.SAI0.RXC | | | | | | | +#define IOMUXD__CSI_D01 REG32(IOMUXD_REG_BASE+0x00043280U) // 9 2 3 10 | CI_PI.D03 | | ADMA.SAI0.RXD | | | | | | | +#define IOMUXD__CSI_D02 REG32(IOMUXD_REG_BASE+0x000432C0U) // 9 2 3 11 | CI_PI.D04 | | ADMA.SAI0.RXFS | | | | | | | +#define IOMUXD__CSI_D03 REG32(IOMUXD_REG_BASE+0x00043300U) // 9 2 3 12 | CI_PI.D05 | | ADMA.SAI2.RXC | | | | | | | +#define IOMUXD__CSI_D04 REG32(IOMUXD_REG_BASE+0x00043340U) // 9 2 3 13 | CI_PI.D06 | | ADMA.SAI2.RXD | | | | | | | +#define IOMUXD__CSI_D05 REG32(IOMUXD_REG_BASE+0x00043380U) // 9 2 3 14 | CI_PI.D07 | | ADMA.SAI2.RXFS | | | | | | | +#define IOMUXD__CSI_D06 REG32(IOMUXD_REG_BASE+0x00044000U) // 10 2 4 0 | CI_PI.D08 | | ADMA.SAI3.RXC | | | | | | | +#define IOMUXD__CSI_D07 REG32(IOMUXD_REG_BASE+0x00044040U) // 10 2 4 1 | CI_PI.D09 | | ADMA.SAI3.RXD | | | | | | | +#define IOMUXD__CSI_HSYNC REG32(IOMUXD_REG_BASE+0x00044080U) // 10 2 4 2 | CI_PI.HSYNC | CI_PI.D00 | ADMA.SAI3.RXFS | | | | | | | +#define IOMUXD__CSI_VSYNC REG32(IOMUXD_REG_BASE+0x000440C0U) // 10 2 4 3 | CI_PI.VSYNC | CI_PI.D01 | | | | | | | | +#define IOMUXD__CSI_PCLK REG32(IOMUXD_REG_BASE+0x00044100U) // 10 2 4 4 | CI_PI.PCLK | MIPI_CSI0.I2C0.SCL | | ADMA.SPI1.SCK | LSIO.GPIO3.IO00 | | | | | +#define IOMUXD__CSI_MCLK REG32(IOMUXD_REG_BASE+0x00044140U) // 10 2 4 5 | CI_PI.MCLK | MIPI_CSI0.I2C0.SDA | | ADMA.SPI1.SDO | LSIO.GPIO3.IO01 | | | | | +#define IOMUXD__CSI_EN REG32(IOMUXD_REG_BASE+0x00044180U) // 10 2 4 6 | CI_PI.EN | CI_PI.I2C.SCL | ADMA.I2C3.SCL | ADMA.SPI1.SDI | LSIO.GPIO3.IO02 | | | | | +#define IOMUXD__CSI_RESET REG32(IOMUXD_REG_BASE+0x000441C0U) // 10 2 4 7 | CI_PI.RESET | CI_PI.I2C.SDA | ADMA.I2C3.SDA | ADMA.SPI1.CS0 | LSIO.GPIO3.IO03 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD REG32(IOMUXD_REG_BASE+0x00044200U) // 10 2 4 8 | | | | | | | | | | +#define IOMUXD__MIPI_CSI0_MCLK_OUT REG32(IOMUXD_REG_BASE+0x00044240U) // 10 2 4 9 | MIPI_CSI0.ACM.MCLK_OUT | | | | LSIO.GPIO3.IO04 | | | | | +#define IOMUXD__MIPI_CSI0_I2C0_SCL REG32(IOMUXD_REG_BASE+0x00044280U) // 10 2 4 10 | MIPI_CSI0.I2C0.SCL | MIPI_CSI0.GPIO0.IO02 | | | LSIO.GPIO3.IO05 | | | | | +#define IOMUXD__MIPI_CSI0_I2C0_SDA REG32(IOMUXD_REG_BASE+0x000442C0U) // 10 2 4 11 | MIPI_CSI0.I2C0.SDA | MIPI_CSI0.GPIO0.IO03 | | | LSIO.GPIO3.IO06 | | | | | +#define IOMUXD__MIPI_CSI0_GPIO0_01 REG32(IOMUXD_REG_BASE+0x00044300U) // 10 2 4 12 | MIPI_CSI0.GPIO0.IO01 | ADMA.I2C0.SDA | | | LSIO.GPIO3.IO07 | | | | | +#define IOMUXD__MIPI_CSI0_GPIO0_00 REG32(IOMUXD_REG_BASE+0x00044340U) // 10 2 4 13 | MIPI_CSI0.GPIO0.IO00 | ADMA.I2C0.SCL | | | LSIO.GPIO3.IO08 | | | | | +#define IOMUXD__QSPI0A_DATA0 REG32(IOMUXD_REG_BASE+0x00060000U) // 11 3 0 0 | LSIO.QSPI0A.DATA0 | | | | LSIO.GPIO3.IO09 | | | | | +#define IOMUXD__QSPI0A_DATA1 REG32(IOMUXD_REG_BASE+0x00060040U) // 11 3 0 1 | LSIO.QSPI0A.DATA1 | | | | LSIO.GPIO3.IO10 | | | | | +#define IOMUXD__QSPI0A_DATA2 REG32(IOMUXD_REG_BASE+0x00060080U) // 11 3 0 2 | LSIO.QSPI0A.DATA2 | | | | LSIO.GPIO3.IO11 | | | | | +#define IOMUXD__QSPI0A_DATA3 REG32(IOMUXD_REG_BASE+0x000600C0U) // 11 3 0 3 | LSIO.QSPI0A.DATA3 | | | | LSIO.GPIO3.IO12 | | | | | +#define IOMUXD__QSPI0A_DQS REG32(IOMUXD_REG_BASE+0x00060100U) // 11 3 0 4 | LSIO.QSPI0A.DQS | | | | LSIO.GPIO3.IO13 | | | | | +#define IOMUXD__QSPI0A_SS0_B REG32(IOMUXD_REG_BASE+0x00060140U) // 11 3 0 5 | LSIO.QSPI0A.SS0_B | | | | LSIO.GPIO3.IO14 | | | | | +#define IOMUXD__QSPI0A_SS1_B REG32(IOMUXD_REG_BASE+0x00060180U) // 11 3 0 6 | LSIO.QSPI0A.SS1_B | | | | LSIO.GPIO3.IO15 | | | | | +#define IOMUXD__QSPI0A_SCLK REG32(IOMUXD_REG_BASE+0x000601C0U) // 11 3 0 7 | LSIO.QSPI0A.SCLK | | | | LSIO.GPIO3.IO16 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A REG32(IOMUXD_REG_BASE+0x00060200U) // 11 3 0 8 | | | | | | | | | | +#define IOMUXD__QSPI0B_SCLK REG32(IOMUXD_REG_BASE+0x00060240U) // 11 3 0 9 | LSIO.QSPI0B.SCLK | LSIO.QSPI1A.SCLK | LSIO.KPP0.COL0 | | LSIO.GPIO3.IO17 | | | | | +#define IOMUXD__QSPI0B_DATA0 REG32(IOMUXD_REG_BASE+0x00060280U) // 11 3 0 10 | LSIO.QSPI0B.DATA0 | LSIO.QSPI1A.DATA0 | LSIO.KPP0.COL1 | | LSIO.GPIO3.IO18 | | | | | +#define IOMUXD__QSPI0B_DATA1 REG32(IOMUXD_REG_BASE+0x000602C0U) // 11 3 0 11 | LSIO.QSPI0B.DATA1 | LSIO.QSPI1A.DATA1 | LSIO.KPP0.COL2 | | LSIO.GPIO3.IO19 | | | | | +#define IOMUXD__QSPI0B_DATA2 REG32(IOMUXD_REG_BASE+0x00060300U) // 11 3 0 12 | LSIO.QSPI0B.DATA2 | LSIO.QSPI1A.DATA2 | LSIO.KPP0.COL3 | | LSIO.GPIO3.IO20 | | | | | +#define IOMUXD__QSPI0B_DATA3 REG32(IOMUXD_REG_BASE+0x00060340U) // 11 3 0 13 | LSIO.QSPI0B.DATA3 | LSIO.QSPI1A.DATA3 | LSIO.KPP0.ROW0 | | LSIO.GPIO3.IO21 | | | | | +#define IOMUXD__QSPI0B_DQS REG32(IOMUXD_REG_BASE+0x00060380U) // 11 3 0 14 | LSIO.QSPI0B.DQS | LSIO.QSPI1A.DQS | LSIO.KPP0.ROW1 | | LSIO.GPIO3.IO22 | | | | | +#define IOMUXD__QSPI0B_SS0_B REG32(IOMUXD_REG_BASE+0x00061000U) // 12 3 1 0 | LSIO.QSPI0B.SS0_B | LSIO.QSPI1A.SS0_B | LSIO.KPP0.ROW2 | | LSIO.GPIO3.IO23 | | | | | +#define IOMUXD__QSPI0B_SS1_B REG32(IOMUXD_REG_BASE+0x00061040U) // 12 3 1 1 | LSIO.QSPI0B.SS1_B | LSIO.QSPI1A.SS1_B | LSIO.KPP0.ROW3 | | LSIO.GPIO3.IO24 | | | | | +#define IOMUXD__IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B REG32(IOMUXD_REG_BASE+0x00061080U) // 12 3 1 2 | | | | | | | | | | + +// GROUP REGISTERS FOR WAKEUP CONTROL +#define IOMUXD__GROUP_0_0 REG32(IOMUXD_REG_BASE+0x00000400U) // 0 0 0 0 | +#define IOMUXD__GROUP_1_0 REG32(IOMUXD_REG_BASE+0x00020400U) // 1 1 0 0 | +#define IOMUXD__GROUP_1_1 REG32(IOMUXD_REG_BASE+0x00021400U) // 2 1 1 0 | +#define IOMUXD__GROUP_1_2 REG32(IOMUXD_REG_BASE+0x00022400U) // 3 1 2 0 | +#define IOMUXD__GROUP_1_3 REG32(IOMUXD_REG_BASE+0x00023400U) // 4 1 3 0 | +#define IOMUXD__GROUP_1_4 REG32(IOMUXD_REG_BASE+0x00024400U) // 5 1 4 0 | +#define IOMUXD__GROUP_2_0 REG32(IOMUXD_REG_BASE+0x00040400U) // 6 2 0 0 | +#define IOMUXD__GROUP_2_1 REG32(IOMUXD_REG_BASE+0x00041400U) // 7 2 1 0 | +#define IOMUXD__GROUP_2_2 REG32(IOMUXD_REG_BASE+0x00042400U) // 8 2 2 0 | +#define IOMUXD__GROUP_2_3 REG32(IOMUXD_REG_BASE+0x00043400U) // 9 2 3 0 | +#define IOMUXD__GROUP_2_4 REG32(IOMUXD_REG_BASE+0x00044400U) // 10 2 4 0 | +#define IOMUXD__GROUP_3_0 REG32(IOMUXD_REG_BASE+0x00060400U) // 11 3 0 0 | +#define IOMUXD__GROUP_3_1 REG32(IOMUXD_REG_BASE+0x00061400U) // 12 3 1 0 | + +#endif diff --git a/platform/config/mx8qx/lpcg.h b/platform/config/mx8qx/lpcg.h new file mode 100755 index 0000000..d0e0a18 --- /dev/null +++ b/platform/config/mx8qx/lpcg.h @@ -0,0 +1,148 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef LPCG_H +#define LPCG_H + +// NOTE: Content below comes from cprog file of the SCU design database + +// LPCG______REG +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__REG 0x0000 // IPS_SLOT=CLK_SECO +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__BIT 0 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM0P__CM0P_HCLK__STOP 3 + +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__REG 0x0004 // IPS_SLOT=CLK_SECO +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__BIT 0 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__HWEN 0 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__SWEN 1 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__RSVD 2 +#define LPCG__SS_SCU__CM0P__DEBUG_CLK__STOP 3 + +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__REG 0x0000 // IPS_SLOT=CLK_MMCAU_HCLK +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__BIT 0 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__STOP 3 + +#define LPCG__SS_SCU__CM4__TCMC_HCLK__REG 0x0000 // IPS_SLOT=CLK_TCMC_HCLK +#define LPCG__SS_SCU__CM4__TCMC_HCLK__BIT 0 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__HWEN 0 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__SWEN 1 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__RSVD 2 +#define LPCG__SS_SCU__CM4__TCMC_HCLK__STOP 3 + +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__BIT 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__HWEN 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__SWEN 1 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__RSVD 2 +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__STOP 3 + +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__REG 0x0000 // IPS_SLOT=CLK_LPI2C +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__BIT 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__HWEN 0 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__SWEN 1 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__RSVD 2 +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__STOP 3 + +#define LPCG__SS_SCU__LPIT1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPIT1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__BIT 0 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__HWEN 0 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__SWEN 1 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__RSVD 2 +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__STOP 3 + +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__REG 0x0000 // IPS_SLOT=CLK_LPIT +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__BIT 0 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__HWEN 0 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__SWEN 1 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__RSVD 2 +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__STOP 3 + +#define LPCG__SS_SCU__LPUART1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__LPUART1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__BIT 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__HWEN 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__SWEN 1 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__RSVD 2 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__STOP 3 + +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__REG 0x0000 // IPS_SLOT=CLK_LPUART +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__BIT 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__HWEN 0 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__SWEN 1 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__RSVD 2 +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__STOP 3 + +#define LPCG__SS_SCU__TPM1__IPG_CLK__REG 0x0000 // IPS_SLOT=CLK_TPM +#define LPCG__SS_SCU__TPM1__IPG_CLK__BIT 4 +#define LPCG__SS_SCU__TPM1__IPG_CLK__HWEN 4 +#define LPCG__SS_SCU__TPM1__IPG_CLK__SWEN 5 +#define LPCG__SS_SCU__TPM1__IPG_CLK__RSVD 6 +#define LPCG__SS_SCU__TPM1__IPG_CLK__STOP 7 + +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__REG 0x0000 // IPS_SLOT=CLK_TPM +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__BIT 0 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__HWEN 0 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__SWEN 1 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__RSVD 2 +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__STOP 3 + +#endif + diff --git a/platform/config/mx8qx/soc.bom b/platform/config/mx8qx/soc.bom new file mode 100755 index 0000000..15909a8 --- /dev/null +++ b/platform/config/mx8qx/soc.bom @@ -0,0 +1,57 @@ + +SOC = MX8QX + +DRV += \ + analog \ + csr \ + dsc \ + otp \ + pad \ + seco/v2 \ + snvs/v2 \ + sysctr \ + xrdc2 \ + mtr + +DRV2 += \ + rgpio \ + igpio \ + lmem \ + lpi2c \ + lpit \ + lpcg \ + lpuart \ + mu \ + stc \ + systick \ + drc \ + wdog32 + +SS += \ + a35/v1 \ + adma/v2 \ + base/v1 \ + conn/v1 \ + csi/v1 \ + db/v2 \ + dc/v1 \ + drc/v2 \ + gpu/v2 \ + hsio/v2 \ + img/v1 \ + lsio/v2 \ + m4/v1 \ + mipi/v2 \ + pi/v1 \ + sc/v2 \ + vpu/v4 + +SVC += \ + irq \ + misc \ + pad \ + pm \ + rm \ + seco \ + timer + diff --git a/platform/config/mx8qx/soc.h b/platform/config/mx8qx/soc.h new file mode 100755 index 0000000..5ae660e --- /dev/null +++ b/platform/config/mx8qx/soc.h @@ -0,0 +1,691 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file used to configure SoC specific features of the SCFW. + * Includes info on memory map, DSC mapping, subsystem mapping, etc. + * + */ +/*==========================================================================*/ + +#ifndef SC_SOC_H +#define SC_SOC_H + +/* Includes */ +#include "main/types.h" +#include "has_ss.h" +#include "fsl_device_registers.h" +#include "ss/drc/v2/dsc.h" + +/* Configure DSCs */ + +/*! Macro to calculate DSC index */ +#define DSC_IDX(X) ((sc_dsc_t) ((((uint32_t) (X)) - ((uint32_t) MSI0_BASE)) / 131072U)) + +/*! Macro to define AI_READ/WRITE */ +#define ANA_READ(BASE_IDX, TOG, ADDRESS, RDATA) DSC_AIRegisterRead(BASE_IDX, TOG, ADDRESS, RDATA) +#define ANA_WRITE(BASE_IDX, TOG, ADDRESS, DATAWORD) DSC_AIRegisterWrite(BASE_IDX, TOG, ADDRESS, DATAWORD) +#define ANA_ENABLE_ANAMIX_AI(BASE_IDX) DSC_EnableAnamixAI(BASE_IDX) +#define ANA_ENABLE_PHYMIX_AI(BASE_IDX) DSC_EnablePhymixAI(BASE_IDX) + +/*! Define for Refgen default trim in case of unfused part */ +#define REFGEN_DEFAULT_TRIM 0x2BU + +/*! + * @name Defines for sc_dsc_t + */ +/** @{ */ +#define SC_DSC_SC DSC_IDX(DSC_SC) /* 0x01 */ +#define SC_DSC_ADMA DSC_IDX(DSC_ADMA) /* 0x13 */ +#define SC_DSC_GPU_0 DSC_IDX(DSC_GPU_0) /* 0x16 */ +#define SC_DSC_DB DSC_IDX(DSC_DB) /* 0x19 */ +#define SC_DSC_AP_2 DSC_IDX(DSC_AP_2) /* 0x1A */ +#define SC_DSC_MCU_0 DSC_IDX(DSC_MCU_0) /* 0x1B */ +#define SC_DSC_DRC_0 DSC_IDX(DSC_DRC_0) /* 0x24 */ +#define SC_DSC_DC_0 DSC_IDX(DSC_DC_0) /* 0x25 */ +#define SC_DSC_HSIO DSC_IDX(DSC_HSIO) /* 0x26 */ +#define SC_DSC_CONN DSC_IDX(DSC_CONN) /* 0x27 */ +#define SC_DSC_VPU DSC_IDX(DSC_VPU) /* 0x28 */ +#define SC_DSC_IMG DSC_IDX(DSC_IMG) /* 0x32 */ +#define SC_DSC_LSIO DSC_IDX(DSC_LSIO) /* 0x33 */ +#define SC_DSC_DI_MIPI_1 DSC_IDX(DSC_MIPI_1) /* 0x38 */ +#define SC_DSC_DI_MIPI_0 DSC_IDX(DSC_MIPI_0) /* 0x39 */ +#define SC_DSC_CSI_0 DSC_IDX(DSC_CSI_0) /* 0x3A */ +#define SC_DSC_DI_PI_0 DSC_IDX(DSC_PI_0) /* 0x3B */ +#define SC_DSC_LAST 0x3FU +#define SC_DSC_DRC_1 0x3FU +#define SC_DSC_NA SC_DSC_LAST +#define SC_DSC_W 6U +/** @} */ + +/*! + * DSC Type. This type is a used to indicate a Distributed Slave + * Controller (DSC). + */ +typedef uint8_t sc_dsc_t; + +/*! + * @name Defines for sc_ai_t + */ +/** @{ */ +#define SC_AI_HP_PLL 0U +#define SC_AI_DIG_PLL 1U +#define SC_AI_AV_PLL 2U +#define SC_AI_LVDS_TRANS 3U +#define SC_AI_BANDGAP_REF 4U +#define SC_AI_VA_REFGEN 5U +#define SC_AI_NEG_CHARGE_PUMP 6U +#define SC_AI_WELL_LEVEL_SOURCE 7U +#define SC_AI_DIFFCLK_ROOT 8U +#define SC_AI_DIFFCLK_RPTR 9U +#define SC_AI_DIFFCLK_TERM 10U +#define SC_AI_PHY_LDO 11U +#define SC_AI_OSC24M 12U +#define SC_AI_RC200OSC 13U +#define SC_AI_TEMP_SENSE 14U +#define SC_AI_VDROP_PROCMON 15U +#define SC_AI_LAST 16U +/** @} */ + +/*! + * Analog Interface Modules Types. + */ +typedef uint8_t sc_ai_t; + +/* Configure Subsystems */ + +typedef uint8_t sc_ss_inst_t; + +#define SC_SS_INST_W 1U + +/*! + * @name Defines for sc_sub_t + */ +/** @{ */ +#define SC_SUBSYS_SC 0U +#define SC_SUBSYS_MCU_0 1U +#define SC_SUBSYS_A35 2U +#define SC_SUBSYS_GPU_0 3U +#define SC_SUBSYS_VPU 4U +#define SC_SUBSYS_DC_0 5U +#define SC_SUBSYS_IMG 6U +#define SC_SUBSYS_ADMA 7U +#define SC_SUBSYS_CONN 8U +#define SC_SUBSYS_DB 9U +#define SC_SUBSYS_DRC_0 10U +#define SC_SUBSYS_LSIO 11U +#define SC_SUBSYS_HSIO 12U +#define SC_SUBSYS_MIPI_0 13U +#define SC_SUBSYS_MIPI_1 14U +#define SC_SUBSYS_CSI_0 15U +#define SC_SUBSYS_PI_0 16U +#define SC_SUBSYS_LAST SC_SUBSYS_PI_0 +#define SC_SUBSYS_W 5U +#define SC_SUBSYS_NA 31U +/** @} */ + +/*! + * Subsystem Type. This type is used to indicate a subsystem. + */ +typedef uint8_t sc_sub_t; + +#define SC_PGP_00 0U +#define SC_PGP_01 1U +#define SC_PGP_02 2U +#define SC_PGP_03 3U +#define SC_PGP_10 4U +#define SC_PGP_11 5U +#define SC_PGP_12 6U +#define SC_PGP_13 7U +#define SC_PGP_20 8U +#define SC_PGP_21 9U +#define SC_PGP_22 10U +#define SC_PGP_23 11U + +#define SC_PGP_W 4U +#define SC_PGP_NA 12U + +#define MTR_PWR_PLAN_SEL_SCU0 0U +#define MTR_PWR_PLAN_SEL_DB 1U +#define MTR_PWR_PLAN_SEL_HSIO 2U +#define MTR_PWR_PLAN_SEL_MCU_0 3U +#define MTR_PWR_PLAN_SEL_LSIO 4U +#define MTR_PWR_PLAN_SEL_GPU3D_0 5U +#define MTR_PWR_PLAN_SEL_CA35 6U +#define MTR_PWR_PLAN_SEL_CONNECTIVITY 7U +#define MTR_PWR_PLAN_SEL_VPU 8U +#define MTR_PWR_PLAN_SEL_DRC_0 9U +#define MTR_PWR_PLAN_SEL_DC_0 10U +#define MTR_PWR_PLAN_SEL_MIPI_CSI_0 11U +#define MTR_PWR_PLAN_SEL_IMAGING 12U +#define MTR_PWR_PLAN_SEL_ADMA 13U +#define MTR_PWR_PLAN_SEL_DI_MIPI_DSI_LVDS_0 14U +#define MTR_PWR_PLAN_SEL_DI_MIPI_DSI_LVDS_1 15U + +#define SC_SS_INFO_INIT \ + {HAS_SS_SC, 0, SC_PGP_00, SC_SUBSYS_NA, 0, 0, SC_DSC_SC}, /* SC_SUBSYS_SC */ \ + {HAS_SS_MCU_0, 0, SC_PGP_01, SC_SUBSYS_NA, 0, 0, SC_DSC_MCU_0}, /* SC_SUBSYS_MCU_0 */ \ + {HAS_SS_AP_2, 0, SC_PGP_22, SC_SUBSYS_NA, 0, 0, SC_DSC_AP_2}, /* SC_SUBSYS_A35 */ \ + {HAS_SS_GPU_0, 0, SC_PGP_02, SC_SUBSYS_NA, 0, 0, SC_DSC_GPU_0}, /* SC_SUBSYS_GPU_0 */ \ + {HAS_SS_VPU, 0, SC_PGP_10, SC_SUBSYS_NA, 0, 0, SC_DSC_VPU}, /* SC_SUBSYS_VPU */ \ + {HAS_SS_DC_0, 0, SC_PGP_13, SC_SUBSYS_IMG, 24, 0, SC_DSC_DC_0}, /* SC_SUBSYS_DC_0 */ \ + {HAS_SS_IMG_0, 0, SC_PGP_20, SC_SUBSYS_NA, 0, 0, SC_DSC_IMG}, /* SC_SUBSYS_IMG */ \ + {HAS_SS_ADMA, 0, SC_PGP_03, SC_SUBSYS_IMG, 25, 0, SC_DSC_ADMA}, /* SC_SUBSYS_ADMA */ \ + {HAS_SS_CONN, 0, SC_PGP_11, SC_SUBSYS_NA, 0, 0, SC_DSC_CONN}, /* SC_SUBSYS_CONN */ \ + {HAS_SS_DB, 0, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DB}, /* SC_SUBSYS_DB */ \ + {HAS_SS_DRC_0, 0, SC_PGP_NA, SC_SUBSYS_NA, 0, 0, SC_DSC_DRC_0}, /* SC_SUBSYS_DRC_0 */ \ + {HAS_SS_LSIO, 0, SC_PGP_21, SC_SUBSYS_NA, 0, 0, SC_DSC_LSIO}, /* SC_SUBSYS_LSIO */ \ + {HAS_SS_HSIO_0, 0, SC_PGP_12, SC_SUBSYS_NA, 0, 0, SC_DSC_HSIO}, /* SC_SUBSYS_HSIO */ \ + {HAS_SS_MIPI_0, 0, SC_PGP_NA, SC_SUBSYS_DC_0, 11, 0, SC_DSC_DI_MIPI_0}, /* SC_SUBSYS_MIPI_0 */ \ + {HAS_SS_MIPI_1, 1, SC_PGP_NA, SC_SUBSYS_DC_0, 12, 0, SC_DSC_DI_MIPI_1}, /* SC_SUBSYS_MIPI_1 */ \ + {HAS_SS_CSI_0, 0, SC_PGP_NA, SC_SUBSYS_IMG, 21, 18, SC_DSC_CSI_0}, /* SC_SUBSYS_CSI_0 */ \ + {HAS_SS_PI_0, 0, SC_PGP_NA, SC_SUBSYS_IMG, 23, 20, SC_DSC_DI_PI_0} /* SC_SUBSYS_PI_0 */ + +/*! Number of DB */ +#define SC_NUM_DB 1U + +/*! + * DB Connect Type. Stores a subsystem connection mask. + */ +typedef uint32_t sc_db_connect_t; + +/*! DB connect mask */ +#define SC_DB_CONNECT \ + ( BIT(SC_SUBSYS_SC) \ + | BIT(SC_SUBSYS_MCU_0) \ + | BIT(SC_SUBSYS_A35) \ + | BIT(SC_SUBSYS_GPU_0) \ + | BIT(SC_SUBSYS_VPU) \ + | BIT(SC_SUBSYS_DC_0) \ + | BIT(SC_SUBSYS_IMG) \ + | BIT(SC_SUBSYS_ADMA) \ + | BIT(SC_SUBSYS_CONN) \ + | BIT(SC_SUBSYS_DRC_0) \ + | BIT(SC_SUBSYS_LSIO) \ + | BIT(SC_SUBSYS_HSIO)) + +/*! Init order of DB (SCU outward) */ +#define SC_DB_INIT \ + {SC_R_DB, SC_SUBSYS_DB, SC_DB_CONNECT} + +#define SC_SS_EP_INIT \ + SS_EP_INIT_SC, /* SC_SUBSYS_SC */ \ + SS_EP_INIT_M4, /* SC_SUBSYS_MCU_0 */ \ + SS_EP_INIT_A35, /* SC_SUBSYS_A35 */ \ + SS_EP_INIT_GPU, /* SC_SUBSYS_GPU_0 */ \ + SS_EP_INIT_VPU, /* SC_SUBSYS_VPU */ \ + SS_EP_INIT_DC, /* SC_SUBSYS_DC_0 */ \ + SS_EP_INIT_IMG, /* SC_SUBSYS_IMG */ \ + SS_EP_INIT_ADMA, /* SC_SUBSYS_ADMA */ \ + SS_EP_INIT_CONN, /* SC_SUBSYS_CONN */ \ + SS_EP_INIT_DB, /* SC_SUBSYS_DB */ \ + SS_EP_INIT_DRC, /* SC_SUBSYS_DRC_0 */ \ + SS_EP_INIT_LSIO, /* SC_SUBSYS_LSIO */ \ + SS_EP_INIT_HSIO, /* SC_SUBSYS_HSIO */ \ + SS_EP_INIT_MIPI, /* SC_SUBSYS_MIPI_0 */ \ + SS_EP_INIT_MIPI, /* SC_SUBSYS_MIPI_1 */ \ + SS_EP_INIT_CSI, /* SC_SUBSYS_CSI_0 */ \ + SS_EP_INIT_PI /* SC_SUBSYS_PI_0 */ + +#define SC_SS_BASE_INFO_INIT \ + &ss_base_info_sc, /* SC_SUBSYS_SC */ \ + &ss_base_info_m4, /* SC_SUBSYS_MCU_0 */ \ + &ss_base_info_a35, /* SC_SUBSYS_A35 */ \ + &ss_base_info_gpu, /* SC_SUBSYS_GPU_0 */ \ + &ss_base_info_vpu, /* SC_SUBSYS_VPU */ \ + &ss_base_info_dc, /* SC_SUBSYS_DC_0 */ \ + &ss_base_info_img, /* SC_SUBSYS_IMG */ \ + &ss_base_info_adma, /* SC_SUBSYS_ADMA */ \ + &ss_base_info_conn, /* SC_SUBSYS_CONN */ \ + &ss_base_info_db, /* SC_SUBSYS_DB */ \ + &ss_base_info_drc, /* SC_SUBSYS_DRC_0 */ \ + &ss_base_info_lsio, /* SC_SUBSYS_LSIO */ \ + &ss_base_info_hsio, /* SC_SUBSYS_HSIO */ \ + &ss_base_info_mipi, /* SC_SUBSYS_MIPI_0 */ \ + &ss_base_info_mipi, /* SC_SUBSYS_MIPI_1 */ \ + &ss_base_info_csi, /* SC_SUBSYS_CSI_0 */ \ + &ss_base_info_pi, /* SC_SUBSYS_PI_0 */ + +#ifdef DEBUG + #define SNAME_INIT \ + "SC", \ + "M4_0", \ + "A35", \ + "GPU_0", \ + "VPU", \ + "DC_0", \ + "IMG", \ + "ADMA", \ + "CONN", \ + "DB", \ + "DRC_0", \ + "LSIO", \ + "HSIO", \ + "MIPI_0", \ + "MIPI_1", \ + "CSI_0", \ + "PI_0" + + #define RNAME_INIT \ + RNAME_INIT_SC_0 \ + RNAME_INIT_M4_0 \ + RNAME_INIT_A35_0 \ + RNAME_INIT_GPU_0 \ + RNAME_INIT_VPU_0 \ + RNAME_INIT_DC_0 \ + RNAME_INIT_IMG_0 \ + RNAME_INIT_ADMA_0 \ + RNAME_INIT_CONN_0 \ + RNAME_INIT_DB_0 \ + RNAME_INIT_DRC_0 \ + RNAME_INIT_LSIO_0 \ + RNAME_INIT_HSIO_0 \ + RNAME_INIT_MIPI_0 \ + RNAME_INIT_MIPI_1 \ + RNAME_INIT_CSI_0 \ + RNAME_INIT_PI_0 \ + RNAME_INIT_BRD + +#endif + +#define SC_R_DDR SC_R_DRC_0 +#define SC_R_DDR_PLL SC_R_DRC_0_PLL + +/*! Chip versions */ +#define CHIP_VER_B0 0x1U +#define CHIP_VER_C0 0x2U + +/*! Macro to get JTAG ID */ +#ifndef SIMU + #define JTAG_ID (DSC_SC->GPR_STAT[2].RW & 0x1FFU) +#else + #ifdef SREV_B0 + #define JTAG_ID ((CHIP_VER_B0 << 5U) | CHIP_ID_QX) + #endif + #ifdef SREV_C0 + #define JTAG_ID ((CHIP_VER_C0 << 5U) | CHIP_ID_QX) + #endif +#endif + +/*! Macros to get chip ID and version */ +#define CHIP_ID ((JTAG_ID >> 0U) & 0x1FU) +#define CHIP_VER ((JTAG_ID >> 5U) & 0xFU) + +/* Define IMG DSSCMIX rate */ +#define SC_IMGMIX SC_300MHZ + +/* Configure Top Level Memory Map */ + +#define SC_MEMMAP_INIT \ + { LSIO_SS_BASE1, 0x1C000000U, 1, 1, 30, 1, 0x00, SC_SUBSYS_LSIO}, \ + { SCU_SS_BASE0, 0x4000000U, 0, 1, 26, 0, 0x00, SC_SUBSYS_SC}, \ + { MCU_0_SS_BASE0, 0x4000000U, 1, 1, 26, 0, 0x00, SC_SUBSYS_MCU_0}, \ + {HSIO_0_SS_BASE2, 0x10000000U, 1, 1, 28, 2, 0x00, SC_SUBSYS_HSIO}, \ + { DDR_BASE0, 0x80000000U, 1, 0, 0, 0, 0x00, SC_SUBSYS_DB}, \ + { LSIO_SS_BASE2, 0x40000000U, 1, 1, 30, 2, 0x00, SC_SUBSYS_LSIO}, \ + { DDR_BASE1, 0x780000000ULL, 1, 0, 0, 0, 0x00, SC_SUBSYS_DB}, \ + { SC_NA, SC_NA, 0, 0, 0, 0, 0, 0} + +#define SC_BOOT_ADDR_INIT \ + {OCRAM_ALIAS_BASE, 0x17FFFU, SC_R_OCRAM, SC_SUBSYS_LSIO}, \ + { OCRAM_BASE, 0x3FFFFU, SC_R_OCRAM, SC_SUBSYS_LSIO}, \ + { FSPI0_MEM_BASE, 0x10000000U, SC_R_FSPI_0, SC_SUBSYS_LSIO}, \ + { TCML_MCU_0, 0x4000000U, SC_R_MCU_0_PID0, SC_SUBSYS_MCU_0}, \ + { DDR_BASE0, 0x80000000U, SC_R_DRC_0, SC_SUBSYS_DRC_0}, \ + { FSPI1_MEM_BASE, 0x40000000U, SC_R_FSPI_1, SC_SUBSYS_LSIO}, \ + { DDR_BASE1, 0x780000000ULL, SC_R_DRC_0, SC_SUBSYS_DRC_0}, \ + { SC_NA, SC_NA, 0U, 0U} + +/* Configure Features */ + +/* Configure RM */ +#define SC_RM_NUM_PARTITION 20U //!< Number of resource partitions +#define SC_RM_NUM_MEMREG 64U //!< Number of memory regions +#define SC_RM_NUM_DOMAIN 16U //!< Number of resource domains + +/*! PLL frequencies */ +#define MIN_PLL_RATE 648000000U +#define MAX_PLL_RATE 1344000000U +#define MIN_HP_PLL_RATE 1250000000U +#define MAX_HP_PLL_RATE 2500000000U +#define MIN_HP_PLL_1P5_RATE 833333333U +#define PLL_RATE_DEN 960000U +#define DIV_FACTOR_NUM 2U +#define DIV_FACTOR_DEN 3U + +/*! + * Define operating points for A35. + */ +#define NUM_A35_OPP 2 + +/* Define voltage setpoints for GPU */ +#define NUM_GPU_OPP 2 + +/* No GPU clock table */ +#define NO_GPU_CLKS + +/*! Define to indicate that AV PLL should be used for DC */ +#define USE_AVPLL_FOR_DC + +/*! Define for DB clock gating issue. */ +#define TKT309042_WORKAROUND + +/*! Has 28FDSOI in SCFW API */ +#define API_HAS_28FDSOI + +#ifdef SIMU +/*! Support partitioning naming for debug */ +#define HAS_PARTITION_NAMES +#endif + +#if defined(LTO) || defined (SIMU) +/*! Enhanced monitor support */ +#define MONITOR_HAS_CMD_OFF +#define MONITOR_HAS_CMD_MSG +#define MONITOR_HAS_CMD_VDETECT +#define MONITOR_HAS_CMD_WDOG +#define MONITOR_HAS_CMD_PANIC +#define MONITOR_HAS_CMD_MRC +#define MONITOR_HAS_CMD_BOOT +#define MONITOR_HAS_CMD_WAKE +#define MONITOR_HAS_CMD_GRANT +#endif + +/*! Define to use SECO FW */ +#define HAS_SECO_FW + +/*! Define for FW version */ +#define SECO_FW_VERSION ((3UL << 16) | (7UL << 4) | 4UL) + +/*! Define to use MIPI DSI trim */ +#define HAS_DSI_VOH_TRIM + +/*! Define DDR DATX8 Lanes */ +#define DWC_NO_OF_BYTES 5U + +/*! Defines for AI temp sensor */ +#define FUSE_TEMP_AUTO 0x0 +#define FUSE_TEMP_INDUSL 0x1 +#define FUSE_TEMP_CONS 0x2 +#define FUSE_TEMP_EX_CONS 0x3 +#define AI_TEMP_RATE 1000U +#define AI_TEMP_NP 1915 +#define AI_TEMP_NT 25 +#define AI_TEMP_PANIC 127 +#define AI_TEMP_PANIC_AUTO 127 +#define AI_TEMP_PANIC_INDUS 107 +#define AI_TEMP_PANIC_CONS 97 +#define AI_TEMP_PANIC_EX_CONS 107 + +/*! Define to indicate timer services required */ +#define HAS_TIMER_SERVICES + +/*! Number of boot images supported by ROM */ +#define SC_BOOT_MAX_LIST 8U + +/* Define boot cpu and address based on whether or + not we're running the DDR stress test */ +#ifdef M4_BOOT + #define BOOT_CPU SC_R_MCU_0_PID0 + #define BOOT_ADDR 0x000000000ULL + #define BOOT_MU SC_R_MCU_0_MU_1A + #define BOOT_CPU_STARTS 1U + #define BOOT_SRC 0x00040000U + #define BOOT_DST 0x34FE0000U + #define BOOT_SIZE 0x20000U + #define BOOT_FLAGS 0x00000000U +#elif defined(TEST_BOOTTIME) + #define BOOT_CPU SC_R_MCU_0_PID0 + #define BOOT_ADDR 0x000000000ULL + #define BOOT_MU SC_R_MCU_0_MU_1A + #define BOOT_CPU_STARTS 1U + #define BOOT_FLAGS 0x00400000U +#else + #define BOOT_CPU SC_R_AP_2_0 + #define BOOT_ADDR 0x080000000UL + #define BOOT_MU SC_R_MU_0A + #define BOOT_CPU_STARTS 1U + #define BOOT_FLAGS 0x00000000U +#endif + +/* Boot data address */ +#define SC_BOOT_DATA_ADDR_PTR 0x000005F0U +#define SC_BOOT_DATA_ADDR 0x2001FC00U +#define SC_BOOT_DATA2_ADDR 0x2001FD00U + +/*! Rom boot device mappings */ +/** @{ */ +#define ROM_SDHC_0 SC_R_SDHC_0 +#define ROM_SDHC_1 SC_R_SDHC_1 +#define ROM_SDHC_2 SC_R_SDHC_2 +#define ROM_FSPI_0 SC_R_FSPI_0 +#define ROM_FSPI_1 SC_R_FSPI_1 +#define ROM_USB_0 SC_R_USB_0 +#define ROM_USB_1 SC_R_USB_0 +#define ROM_USB_2 SC_R_USB_2 +/** @} */ + +/* Configure Tests */ +#define TEST_HSIO0_PCIE SC_R_PCIE_B +#define TEST_HSIO0_SERDES SC_R_SERDES_1 +#define TEST_HSIO0_MATCH_0 SC_R_MATCH_0 +#define SC_P_TEST_PAD SC_P_UART1_RX +#define SC_P_TEST_PAD_COMP SC_P_COMP_CTL_GPIO_3V3_USB3IO +#define TEST_LSIO HAS_SS_LSIO +#define TEST_DMA HAS_SS_ADMA +#define TEST_BOARD_ALT2 SC_FALSE + +/* Max MRC regions */ +#define SC_MAX_NUM_MEMREG \ +( \ + 16U /* DB */ \ + + 32U /* HSIO */ \ + + 48U /* LSIO */ \ + + 4U /* MCU */ \ + + 4U /* SC */ \ +) + +/*! Define to indicate number of CAAM job rings */ +#define SC_CAAM_JR 4U + +/*! Define to indicate number of MU */ +#define SC_SECO_MU 4U + +/*! Enable FAKE_TBU use by MCU */ +#define SC_FAKE_TBU + +/* Configure Resources */ +#define SC_NO_DTCP + +/* Define CPU topology */ +#define SOC_NUM_CLUSTER 1U +#define SOC_IDX_AP_2 0U +#define SOC_NUM_AP_2 4U +#define SOC_NUM_DIG_AUD_PLL 2U + +/* Define MCU topology */ +#define SOC_NUM_MCU 1U +#define SOC_IDX_MCU_0 0U + +/* Define HMP topology */ +#define SOC_NUM_HMP_NODES 3U +#define SOC_HMP_IDX_SCU 0U /* SCU must be index 0 */ +#define SOC_HMP_IDX_MCU_0 1U /* MCU order must follow topology above */ +#define SOC_HMP_IDX_AP_2 2U +#define SOC_HMP_IDX_MCU SOC_HMP_IDX_MCU_0 +#define SOC_HMP_IDX_AP SOC_HMP_IDX_AP_2 + +/* Define system-level interface topology */ +#define SOC_NUM_SYS_IF 4U /* Number of system-level interfaces */ +#define SOC_SYS_IF_MU_RSRC 5U /* Number of AP -> SCU message unit resources */ +#define SOC_SYS_IF_ICN_RSRC 1U /* Number of interconnect resources */ +#define SOC_SYS_IF_OCMEM_RSRC 3U /* Number of on-chip memory resources */ +#define SOC_SYS_IF_DDR_RSRC 1U /* Number of DDR resources */ +#define SOC_SYS_IF_CPU_HPM SC_PM_PW_MODE_LP /* CPU power mode threshold for HPM */ + +/* Define wakeup bindings */ +#define SOC_GIC_DSC SC_DSC_ADMA /* DSC for GIC wakeups */ +#define SOC_IRQSTEER_DSC SC_DSC_ADMA /* DSC for IRQSTEER wakeup */ +#define SOC_GIC_WAKEUP00 REGBIT64(1, 0) /* DSC IRQ for GIC wakeups */ +#define SOC_IRQSTEER_AP_WAKEUP REGBIT64(1, 11) /* DSC IRQ for AP IRQSTEER wakeup */ +#define SOC_IRQSTEER_MCU_WAKEUP REGBIT64(1, 9) /* DSC IRQ for MCU IRQSTEER wakeup */ +#define SOC_WAKEUP_PW_MODE SC_PM_PW_MODE_STBY /* CPU power mode limit for GIC wakeup */ +#define SOC_RESUME_PW_MODE SC_PM_PW_MODE_ON /* CPU power mode for resume */ +#define SOC_MCU_STOPM_PDN 3U /* STOPM >= 3 will power down MCU core */ +#define SOC_MCU_STOPM_MEMSR 3U /* STOPM == 3 will retain memories */ +#define SOC_SNVS_PWR_ON_WAKEUP REGBIT64(1, 10) /* DSC IRQ for SNVS_LP set_pwr_on_irq */ + +/* Define ADMA mbist */ +#define SS_ADMA_BIST1 (((uint32_t)DSC_ADMA) + 0x8020U) +#define SS_ADMA_BIST1_START 230U +#define SS_ADMA_BIST1_END 233U + +#define SS_ADMA_BIST3 (((uint32_t)DSC_ADMA) + 0x8040U) +#define SS_ADMA_BIST3_START 234U +#define SS_ADMA_BIST3_END 266U + +/* Defines for DDR training */ +#define DQS_TIMER_DURATION_512 1U /* 512 * tCK = 2048 * (1/1200) = 1 us (round up) */ +#define DQS_TIMER_DURATION_1008 1U /* 1008 * tCK = 1008 * (1/1200) = 1 us (round up) */ +#define DQS_TIMER_DURATION_2048 2U /* 2048 * tCK = 2048 * (1/1200) = 2 us (round up) */ +#define DQS_TIMER_DURATION_8192 7U /* 8192 * tCK = 8192 * (1/1200) = 7 us (round up) */ + +/* Include SS configs */ + +#include "all_config.h" +#include "board/config.h" +#include "handlers_MX8QX.h" /* Device specific handlers */ + +/* Configure Resources */ + +#define SC_NUM_RSRC \ + (SS_NUM_RSRC_SC \ + + SS_NUM_RSRC_M4 \ + + SS_NUM_RSRC_A35 \ + + SS_NUM_RSRC_GPU \ + + SS_NUM_RSRC_VPU \ + + SS_NUM_RSRC_DC \ + + SS_NUM_RSRC_IMG \ + + SS_NUM_RSRC_ADMA \ + + SS_NUM_RSRC_CONN \ + + SS_NUM_RSRC_DB \ + + SS_NUM_RSRC_DRC \ + + SS_NUM_RSRC_LSIO \ + + SS_NUM_RSRC_HSIO \ + + SS_NUM_RSRC_MIPI \ + + SS_NUM_RSRC_MIPI \ + + SS_NUM_RSRC_CSI \ + + SS_NUM_RSRC_PI \ + + BRD_NUM_RSRC_BRD) + +#define SC_PAD_INIT_INIT \ + {SC_P_USB_SS3_TC0, 4, 0}, \ + {SC_P_USB_SS3_TC1, 4, 0}, \ + {SC_P_USB_SS3_TC2, 4, 0}, \ + {SC_P_USB_SS3_TC3, 4, 0}, \ + {SC_P_USDHC1_RESET_B, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_VSELECT, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_WP, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_CD_B, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_CLK, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_CMD, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_DATA0, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_DATA1, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_DATA2, 4, SC_R_SDHC_1}, \ + {SC_P_USDHC1_DATA3, 4, SC_R_SDHC_1}, \ + {SC_P_MCLK_IN0, 4, 0}, \ + {SC_P_MCLK_OUT0, 4, 0}, \ + {SC_P_SAI0_TXD, 4, 0}, \ + {SC_P_SAI0_TXC, 4, 0}, \ + {SC_P_SAI0_RXD, 4, 0}, \ + {SC_P_SAI0_TXFS, 4, 0}, \ + {SC_P_SAI1_RXD, 4, 0}, \ + {SC_P_SAI1_RXC, 4, 0}, \ + {SC_P_SAI1_RXFS, 4, 0}, \ + {SC_P_SPI2_CS0, 4, 0}, \ + {SC_P_SPI2_SDO, 4, 0}, \ + {SC_P_SPI2_SDI, 4, 0}, \ + {SC_P_SPI2_SCK, 4, 0}, \ + {SC_P_FLEXCAN0_RX, 4, SC_R_CAN_0}, \ + {SC_P_FLEXCAN0_TX, 4, SC_R_CAN_0}, \ + {SC_P_FLEXCAN1_RX, 4, SC_R_CAN_1}, \ + {SC_P_FLEXCAN1_TX, 4, SC_R_CAN_1}, \ + {SC_P_PMIC_I2C_SCL, 4, 0}, \ + {SC_P_PMIC_I2C_SDA, 4, 0}, \ + {SC_P_MIPI_CSI0_I2C0_SCL, 4, 0}, \ + {SC_P_MIPI_CSI0_I2C0_SDA, 4, 0}, \ + {0, 0, 0} + +#define SC_ROM_SS_INIT \ + 0, /* SC_SUBSYS_SC */ \ + 1, /* SC_SUBSYS_MCU_0 */ \ + 2, /* SC_SUBSYS_A35 */ \ + 3, /* SC_SUBSYS_GPU_0 */ \ + 4, /* SC_SUBSYS_VPU */ \ + 5, /* SC_SUBSYS_DC_0 */ \ + 6, /* SC_SUBSYS_IMG */ \ + 7, /* SC_SUBSYS_ADMA */ \ + 8, /* SC_SUBSYS_CONN */ \ + 9, /* SC_SUBSYS_DB */ \ + 10, /* SC_SUBSYS_DRC_0 */ \ + 11, /* SC_SUBSYS_LSIO */ \ + 12, /* SC_SUBSYS_HSIO */ \ + 13, /* SC_SUBSYS_MIPI_0 */ \ + 14, /* SC_SUBSYS_MIPI_1 */ \ + 15, /* SC_SUBSYS_CSI_0 */ \ + 16 /* SC_SUBSYS_PI_0 */ + +typedef uint8_t soc_flags_t; + +#define SOC_DYN_PLL_VER +/*! + * @name Defines for soc_flags_t + */ +#define SOC_DC_AXI_DERATE_FLAG (1U << 0U) +#define SOC_DQS2DQ_SYNC_FLAG (1U << 1U) +#define SOC_TEMP_SENSE_FULL_PD (1U << 2U) +#define SOC_RELOCK_ROM_LOCKED_PLL (1U << 3U) +#define SOC_VPU_ENC_MTR (1U << 4U) + +/* External variables */ + +extern uint8_t soc_dpll_ver; +extern soc_flags_t soc_flags; + +#endif /* SC_SOC_H */ + diff --git a/platform/devices/MX8/MX8_adm.h b/platform/devices/MX8/MX8_adm.h new file mode 100755 index 0000000..ee6610b --- /dev/null +++ b/platform/devices/MX8/MX8_adm.h @@ -0,0 +1,672 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8_adm.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for ADM + * + * CMSIS Peripheral Access Layer for ADM + */ + +#ifndef ADM_H +#define ADM_H /**< Symbol preventing repeated inclusion */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADM_Peripheral_Access_Layer ADM Peripheral Access Layer + * @{ + */ + +/** ADM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCU_GPR0[4]; /**< GPR register for SCU Bank 0, array offset: 0x0, array step: 0x4 */ + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< Control register for SCU Bank 0., offset: 0x10 */ + __IO uint32_t SET; /**< Control register for SCU Bank 0., offset: 0x14 */ + __IO uint32_t CLR; /**< Control register for SCU Bank 0., offset: 0x18 */ + __IO uint32_t TOG; /**< Control register for SCU Bank 0., offset: 0x1C */ + } GPR0_CTRL; + __IO uint32_t SCU_GPR1[4]; /**< GPR register for SCU Bank 1, array offset: 0x20, array step: 0x4 */ + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Control register for bank 1., offset: 0x30 */ + __IO uint32_t SET; /**< Control register for bank 1., offset: 0x34 */ + __IO uint32_t CLR; /**< Control register for bank 1., offset: 0x38 */ + __IO uint32_t TOG; /**< Control register for bank 1., offset: 0x3C */ + } GPR1_CTRL; + __IO uint32_t SCU_GPR2[4]; /**< GPR register for SCU Bank 2, array offset: 0x40, array step: 0x4 */ + struct { /* offset: 0x50 */ + __IO uint32_t RW; /**< Control register for Bank 2., offset: 0x50 */ + __IO uint32_t SET; /**< Control register for Bank 2., offset: 0x54 */ + __IO uint32_t CLR; /**< Control register for Bank 2., offset: 0x58 */ + __IO uint32_t TOG; /**< Control register for Bank 2., offset: 0x5C */ + } GPR2_CTRL; + __IO uint32_t SCU_GPR3[4]; /**< GPR register for SCU Bank 3, array offset: 0x60, array step: 0x4 */ + struct { /* offset: 0x70 */ + __IO uint32_t RW; /**< Control register for bank 3., offset: 0x70 */ + __IO uint32_t SET; /**< Control register for bank 3., offset: 0x74 */ + __IO uint32_t CLR; /**< Control register for bank 3., offset: 0x78 */ + __IO uint32_t TOG; /**< Control register for bank 3., offset: 0x7C */ + } GPR3_CTRL; + __IO uint32_t SCU_GPR4[4]; /**< GPR register for SCU Bank 4, array offset: 0x80, array step: 0x4 */ + struct { /* offset: 0x90 */ + __IO uint32_t RW; /**< Control register for bank 4., offset: 0x90 */ + __IO uint32_t SET; /**< Control register for bank 4., offset: 0x94 */ + __IO uint32_t CLR; /**< Control register for bank 4., offset: 0x98 */ + __IO uint32_t TOG; /**< Control register for bank 4., offset: 0x9C */ + } GPR4_CTRL; + __IO uint32_t SCU_GPR5[4]; /**< GPR register for SCU Bank 5, array offset: 0xA0, array step: 0x4 */ + struct { /* offset: 0xB0 */ + __IO uint32_t RW; /**< Control register for bank 5., offset: 0xB0 */ + __IO uint32_t SET; /**< Control register for bank 5., offset: 0xB4 */ + __IO uint32_t CLR; /**< Control register for bank 5., offset: 0xB8 */ + __IO uint32_t TOG; /**< Control register for bank 5., offset: 0xBC */ + } GPR5_CTRL; + struct { /* offset: 0xC0 */ + __IO uint32_t RW; /**< Control register for SCU., offset: 0xC0 */ + __IO uint32_t SET; /**< Control register for SCU., offset: 0xC4 */ + __IO uint32_t CLR; /**< Control register for SCU., offset: 0xC8 */ + __IO uint32_t TOG; /**< Control register for SCU., offset: 0xCC */ + } CTRL0; + struct { /* offset: 0xD0 */ + __IO uint32_t RW; /**< Control register for SCU., offset: 0xD0 */ + __IO uint32_t SET; /**< Control register for SCU., offset: 0xD4 */ + __IO uint32_t CLR; /**< Control register for SCU., offset: 0xD8 */ + __IO uint32_t TOG; /**< Control register for SCU., offset: 0xDC */ + } CTRL1; + __IO uint32_t STATUS0; /**< Status register for SCU., offset: 0xE0 */ + uint8_t RESERVED_0[12]; + __I uint32_t STATUS1; /**< Status register for SCU., offset: 0xF0 */ + uint8_t RESERVED_1[12]; + __I uint32_t GPR0[4]; /**< , array offset: 0x100, array step: 0x4 */ + __I uint32_t GPR1[4]; /**< , array offset: 0x110, array step: 0x4 */ + __I uint32_t GPR2[4]; /**< , array offset: 0x120, array step: 0x4 */ + __I uint32_t GPR3[4]; /**< , array offset: 0x130, array step: 0x4 */ + __I uint32_t GPR4[4]; /**< , array offset: 0x140, array step: 0x4 */ + __I uint32_t GPR5[4]; /**< , array offset: 0x150, array step: 0x4 */ + __I uint32_t SECO_SUPER_ROOT_KEY_HASH[8]; /**< , array offset: 0x160, array step: 0x4 */ + __I uint32_t HDMI_SUPER_ROOT_KEY_HASH[8]; /**< , array offset: 0x180, array step: 0x4 */ + __IO uint32_t CAAM_PWRCTRL_REF; /**< CAAM PWRCTRL reg for reference, offset: 0x1A0 */ + uint8_t RESERVED_2[12]; + __I uint32_t SPARE[4]; /**< , array offset: 0x1B0, array step: 0x4 */ +} ADM_Type; + +/* ---------------------------------------------------------------------------- + -- ADM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADM_Register_Masks ADM Register Masks + * @{ + */ + +/*! @name SCU_GPR0 - GPR register for SCU Bank 0 */ +#define ADM_SCU_GPR0_BANK0_MASK (0xFFFFFFFFU) +#define ADM_SCU_GPR0_BANK0_SHIFT (0U) +#define ADM_SCU_GPR0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << ADM_SCU_GPR0_BANK0_SHIFT)) & ADM_SCU_GPR0_BANK0_MASK) + +/* The count of ADM_SCU_GPR0 */ +#define ADM_SCU_GPR0_COUNT (4U) + +/*! @name GPR0_CTRL - Control register for SCU Bank 0. */ +#define ADM_GPR0_CTRL_CLR_ON_FAIL_MASK (0x1U) +#define ADM_GPR0_CTRL_CLR_ON_FAIL_SHIFT (0U) +#define ADM_GPR0_CTRL_CLR_ON_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_CTRL_CLR_ON_FAIL_SHIFT)) & ADM_GPR0_CTRL_CLR_ON_FAIL_MASK) +#define ADM_GPR0_CTRL_PRIVATE_WR_MASK (0x2U) +#define ADM_GPR0_CTRL_PRIVATE_WR_SHIFT (1U) +#define ADM_GPR0_CTRL_PRIVATE_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_CTRL_PRIVATE_WR_SHIFT)) & ADM_GPR0_CTRL_PRIVATE_WR_MASK) +#define ADM_GPR0_CTRL_PRIVATE_RD_MASK (0x4U) +#define ADM_GPR0_CTRL_PRIVATE_RD_SHIFT (2U) +#define ADM_GPR0_CTRL_PRIVATE_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_CTRL_PRIVATE_RD_SHIFT)) & ADM_GPR0_CTRL_PRIVATE_RD_MASK) +#define ADM_GPR0_CTRL_SHARED_WR_MASK (0x8U) +#define ADM_GPR0_CTRL_SHARED_WR_SHIFT (3U) +#define ADM_GPR0_CTRL_SHARED_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_CTRL_SHARED_WR_SHIFT)) & ADM_GPR0_CTRL_SHARED_WR_MASK) +#define ADM_GPR0_CTRL_SHARED_RD_MASK (0x10U) +#define ADM_GPR0_CTRL_SHARED_RD_SHIFT (4U) +#define ADM_GPR0_CTRL_SHARED_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_CTRL_SHARED_RD_SHIFT)) & ADM_GPR0_CTRL_SHARED_RD_MASK) +#define ADM_GPR0_CTRL_LOCK_MASK (0x20U) +#define ADM_GPR0_CTRL_LOCK_SHIFT (5U) +#define ADM_GPR0_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_CTRL_LOCK_SHIFT)) & ADM_GPR0_CTRL_LOCK_MASK) + +/*! @name SCU_GPR1 - GPR register for SCU Bank 1 */ +#define ADM_SCU_GPR1_BANK1_MASK (0xFFFFFFFFU) +#define ADM_SCU_GPR1_BANK1_SHIFT (0U) +#define ADM_SCU_GPR1_BANK1(x) (((uint32_t)(((uint32_t)(x)) << ADM_SCU_GPR1_BANK1_SHIFT)) & ADM_SCU_GPR1_BANK1_MASK) + +/* The count of ADM_SCU_GPR1 */ +#define ADM_SCU_GPR1_COUNT (4U) + +/*! @name GPR1_CTRL - Control register for bank 1. */ +#define ADM_GPR1_CTRL_CLR_ON_FAIL_MASK (0x1U) +#define ADM_GPR1_CTRL_CLR_ON_FAIL_SHIFT (0U) +#define ADM_GPR1_CTRL_CLR_ON_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_CTRL_CLR_ON_FAIL_SHIFT)) & ADM_GPR1_CTRL_CLR_ON_FAIL_MASK) +#define ADM_GPR1_CTRL_PRIVATE_WR_MASK (0x2U) +#define ADM_GPR1_CTRL_PRIVATE_WR_SHIFT (1U) +#define ADM_GPR1_CTRL_PRIVATE_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_CTRL_PRIVATE_WR_SHIFT)) & ADM_GPR1_CTRL_PRIVATE_WR_MASK) +#define ADM_GPR1_CTRL_PRIVATE_RD_MASK (0x4U) +#define ADM_GPR1_CTRL_PRIVATE_RD_SHIFT (2U) +#define ADM_GPR1_CTRL_PRIVATE_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_CTRL_PRIVATE_RD_SHIFT)) & ADM_GPR1_CTRL_PRIVATE_RD_MASK) +#define ADM_GPR1_CTRL_SHARED_WR_MASK (0x8U) +#define ADM_GPR1_CTRL_SHARED_WR_SHIFT (3U) +#define ADM_GPR1_CTRL_SHARED_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_CTRL_SHARED_WR_SHIFT)) & ADM_GPR1_CTRL_SHARED_WR_MASK) +#define ADM_GPR1_CTRL_SHARED_RD_MASK (0x10U) +#define ADM_GPR1_CTRL_SHARED_RD_SHIFT (4U) +#define ADM_GPR1_CTRL_SHARED_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_CTRL_SHARED_RD_SHIFT)) & ADM_GPR1_CTRL_SHARED_RD_MASK) +#define ADM_GPR1_CTRL_LOCK_MASK (0x20U) +#define ADM_GPR1_CTRL_LOCK_SHIFT (5U) +#define ADM_GPR1_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_CTRL_LOCK_SHIFT)) & ADM_GPR1_CTRL_LOCK_MASK) + +/*! @name SCU_GPR2 - GPR register for SCU Bank 2 */ +#define ADM_SCU_GPR2_BANK2_MASK (0xFFFFFFFFU) +#define ADM_SCU_GPR2_BANK2_SHIFT (0U) +#define ADM_SCU_GPR2_BANK2(x) (((uint32_t)(((uint32_t)(x)) << ADM_SCU_GPR2_BANK2_SHIFT)) & ADM_SCU_GPR2_BANK2_MASK) + +/* The count of ADM_SCU_GPR2 */ +#define ADM_SCU_GPR2_COUNT (4U) + +/*! @name GPR2_CTRL - Control register for Bank 2. */ +#define ADM_GPR2_CTRL_CLR_ON_FAIL_MASK (0x1U) +#define ADM_GPR2_CTRL_CLR_ON_FAIL_SHIFT (0U) +#define ADM_GPR2_CTRL_CLR_ON_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_CTRL_CLR_ON_FAIL_SHIFT)) & ADM_GPR2_CTRL_CLR_ON_FAIL_MASK) +#define ADM_GPR2_CTRL_PRIVATE_WR_MASK (0x2U) +#define ADM_GPR2_CTRL_PRIVATE_WR_SHIFT (1U) +#define ADM_GPR2_CTRL_PRIVATE_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_CTRL_PRIVATE_WR_SHIFT)) & ADM_GPR2_CTRL_PRIVATE_WR_MASK) +#define ADM_GPR2_CTRL_PRIVATE_RD_MASK (0x4U) +#define ADM_GPR2_CTRL_PRIVATE_RD_SHIFT (2U) +#define ADM_GPR2_CTRL_PRIVATE_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_CTRL_PRIVATE_RD_SHIFT)) & ADM_GPR2_CTRL_PRIVATE_RD_MASK) +#define ADM_GPR2_CTRL_SHARED_WR_MASK (0x8U) +#define ADM_GPR2_CTRL_SHARED_WR_SHIFT (3U) +#define ADM_GPR2_CTRL_SHARED_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_CTRL_SHARED_WR_SHIFT)) & ADM_GPR2_CTRL_SHARED_WR_MASK) +#define ADM_GPR2_CTRL_SHARED_RD_MASK (0x10U) +#define ADM_GPR2_CTRL_SHARED_RD_SHIFT (4U) +#define ADM_GPR2_CTRL_SHARED_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_CTRL_SHARED_RD_SHIFT)) & ADM_GPR2_CTRL_SHARED_RD_MASK) +#define ADM_GPR2_CTRL_LOCK_MASK (0x20U) +#define ADM_GPR2_CTRL_LOCK_SHIFT (5U) +#define ADM_GPR2_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_CTRL_LOCK_SHIFT)) & ADM_GPR2_CTRL_LOCK_MASK) + +/*! @name SCU_GPR3 - GPR register for SCU Bank 3 */ +#define ADM_SCU_GPR3_BANK3_MASK (0xFFFFFFFFU) +#define ADM_SCU_GPR3_BANK3_SHIFT (0U) +#define ADM_SCU_GPR3_BANK3(x) (((uint32_t)(((uint32_t)(x)) << ADM_SCU_GPR3_BANK3_SHIFT)) & ADM_SCU_GPR3_BANK3_MASK) + +/* The count of ADM_SCU_GPR3 */ +#define ADM_SCU_GPR3_COUNT (4U) + +/*! @name GPR3_CTRL - Control register for bank 3. */ +#define ADM_GPR3_CTRL_CLR_ON_FAIL_MASK (0x1U) +#define ADM_GPR3_CTRL_CLR_ON_FAIL_SHIFT (0U) +#define ADM_GPR3_CTRL_CLR_ON_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_CTRL_CLR_ON_FAIL_SHIFT)) & ADM_GPR3_CTRL_CLR_ON_FAIL_MASK) +#define ADM_GPR3_CTRL_PRIVATE_WR_MASK (0x2U) +#define ADM_GPR3_CTRL_PRIVATE_WR_SHIFT (1U) +#define ADM_GPR3_CTRL_PRIVATE_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_CTRL_PRIVATE_WR_SHIFT)) & ADM_GPR3_CTRL_PRIVATE_WR_MASK) +#define ADM_GPR3_CTRL_PRIVATE_RD_MASK (0x4U) +#define ADM_GPR3_CTRL_PRIVATE_RD_SHIFT (2U) +#define ADM_GPR3_CTRL_PRIVATE_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_CTRL_PRIVATE_RD_SHIFT)) & ADM_GPR3_CTRL_PRIVATE_RD_MASK) +#define ADM_GPR3_CTRL_SHARED_WR_MASK (0x8U) +#define ADM_GPR3_CTRL_SHARED_WR_SHIFT (3U) +#define ADM_GPR3_CTRL_SHARED_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_CTRL_SHARED_WR_SHIFT)) & ADM_GPR3_CTRL_SHARED_WR_MASK) +#define ADM_GPR3_CTRL_SHARED_RD_MASK (0x10U) +#define ADM_GPR3_CTRL_SHARED_RD_SHIFT (4U) +#define ADM_GPR3_CTRL_SHARED_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_CTRL_SHARED_RD_SHIFT)) & ADM_GPR3_CTRL_SHARED_RD_MASK) +#define ADM_GPR3_CTRL_LOCK_MASK (0x20U) +#define ADM_GPR3_CTRL_LOCK_SHIFT (5U) +#define ADM_GPR3_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_CTRL_LOCK_SHIFT)) & ADM_GPR3_CTRL_LOCK_MASK) + +/*! @name SCU_GPR4 - GPR register for SCU Bank 4 */ +#define ADM_SCU_GPR4_BANK4_MASK (0xFFFFFFFFU) +#define ADM_SCU_GPR4_BANK4_SHIFT (0U) +#define ADM_SCU_GPR4_BANK4(x) (((uint32_t)(((uint32_t)(x)) << ADM_SCU_GPR4_BANK4_SHIFT)) & ADM_SCU_GPR4_BANK4_MASK) + +/* The count of ADM_SCU_GPR4 */ +#define ADM_SCU_GPR4_COUNT (4U) + +/*! @name GPR4_CTRL - Control register for bank 4. */ +#define ADM_GPR4_CTRL_CLR_ON_FAIL_MASK (0x1U) +#define ADM_GPR4_CTRL_CLR_ON_FAIL_SHIFT (0U) +#define ADM_GPR4_CTRL_CLR_ON_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_CTRL_CLR_ON_FAIL_SHIFT)) & ADM_GPR4_CTRL_CLR_ON_FAIL_MASK) +#define ADM_GPR4_CTRL_PRIVATE_WR_MASK (0x2U) +#define ADM_GPR4_CTRL_PRIVATE_WR_SHIFT (1U) +#define ADM_GPR4_CTRL_PRIVATE_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_CTRL_PRIVATE_WR_SHIFT)) & ADM_GPR4_CTRL_PRIVATE_WR_MASK) +#define ADM_GPR4_CTRL_PRIVATE_RD_MASK (0x4U) +#define ADM_GPR4_CTRL_PRIVATE_RD_SHIFT (2U) +#define ADM_GPR4_CTRL_PRIVATE_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_CTRL_PRIVATE_RD_SHIFT)) & ADM_GPR4_CTRL_PRIVATE_RD_MASK) +#define ADM_GPR4_CTRL_SHARED_WR_MASK (0x8U) +#define ADM_GPR4_CTRL_SHARED_WR_SHIFT (3U) +#define ADM_GPR4_CTRL_SHARED_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_CTRL_SHARED_WR_SHIFT)) & ADM_GPR4_CTRL_SHARED_WR_MASK) +#define ADM_GPR4_CTRL_SHARED_RD_MASK (0x10U) +#define ADM_GPR4_CTRL_SHARED_RD_SHIFT (4U) +#define ADM_GPR4_CTRL_SHARED_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_CTRL_SHARED_RD_SHIFT)) & ADM_GPR4_CTRL_SHARED_RD_MASK) +#define ADM_GPR4_CTRL_LOCK_MASK (0x20U) +#define ADM_GPR4_CTRL_LOCK_SHIFT (5U) +#define ADM_GPR4_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_CTRL_LOCK_SHIFT)) & ADM_GPR4_CTRL_LOCK_MASK) + +/*! @name SCU_GPR5 - GPR register for SCU Bank 5 */ +#define ADM_SCU_GPR5_BANK5_MASK (0xFFFFFFFFU) +#define ADM_SCU_GPR5_BANK5_SHIFT (0U) +#define ADM_SCU_GPR5_BANK5(x) (((uint32_t)(((uint32_t)(x)) << ADM_SCU_GPR5_BANK5_SHIFT)) & ADM_SCU_GPR5_BANK5_MASK) + +/* The count of ADM_SCU_GPR5 */ +#define ADM_SCU_GPR5_COUNT (4U) + +/*! @name GPR5_CTRL - Control register for bank 5. */ +#define ADM_GPR5_CTRL_CLR_ON_FAIL_MASK (0x1U) +#define ADM_GPR5_CTRL_CLR_ON_FAIL_SHIFT (0U) +#define ADM_GPR5_CTRL_CLR_ON_FAIL(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_CTRL_CLR_ON_FAIL_SHIFT)) & ADM_GPR5_CTRL_CLR_ON_FAIL_MASK) +#define ADM_GPR5_CTRL_PRIVATE_WR_MASK (0x2U) +#define ADM_GPR5_CTRL_PRIVATE_WR_SHIFT (1U) +#define ADM_GPR5_CTRL_PRIVATE_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_CTRL_PRIVATE_WR_SHIFT)) & ADM_GPR5_CTRL_PRIVATE_WR_MASK) +#define ADM_GPR5_CTRL_PRIVATE_RD_MASK (0x4U) +#define ADM_GPR5_CTRL_PRIVATE_RD_SHIFT (2U) +#define ADM_GPR5_CTRL_PRIVATE_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_CTRL_PRIVATE_RD_SHIFT)) & ADM_GPR5_CTRL_PRIVATE_RD_MASK) +#define ADM_GPR5_CTRL_SHARED_WR_MASK (0x8U) +#define ADM_GPR5_CTRL_SHARED_WR_SHIFT (3U) +#define ADM_GPR5_CTRL_SHARED_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_CTRL_SHARED_WR_SHIFT)) & ADM_GPR5_CTRL_SHARED_WR_MASK) +#define ADM_GPR5_CTRL_SHARED_RD_MASK (0x10U) +#define ADM_GPR5_CTRL_SHARED_RD_SHIFT (4U) +#define ADM_GPR5_CTRL_SHARED_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_CTRL_SHARED_RD_SHIFT)) & ADM_GPR5_CTRL_SHARED_RD_MASK) +#define ADM_GPR5_CTRL_LOCK_MASK (0x20U) +#define ADM_GPR5_CTRL_LOCK_SHIFT (5U) +#define ADM_GPR5_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_CTRL_LOCK_SHIFT)) & ADM_GPR5_CTRL_LOCK_MASK) + +/*! @name CTRL0 - Control register for SCU. */ +#define ADM_CTRL0_ALLOW_SCU_NIDEN_MASK (0x1U) +#define ADM_CTRL0_ALLOW_SCU_NIDEN_SHIFT (0U) +#define ADM_CTRL0_ALLOW_SCU_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_SCU_NIDEN_SHIFT)) & ADM_CTRL0_ALLOW_SCU_NIDEN_MASK) +#define ADM_CTRL0_ALLOW_SCU_DBGEN_MASK (0x2U) +#define ADM_CTRL0_ALLOW_SCU_DBGEN_SHIFT (1U) +#define ADM_CTRL0_ALLOW_SCU_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_SCU_DBGEN_SHIFT)) & ADM_CTRL0_ALLOW_SCU_DBGEN_MASK) +#define ADM_CTRL0_ALLOW_SCU_SPNIDEN_MASK (0x4U) +#define ADM_CTRL0_ALLOW_SCU_SPNIDEN_SHIFT (2U) +#define ADM_CTRL0_ALLOW_SCU_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_SCU_SPNIDEN_SHIFT)) & ADM_CTRL0_ALLOW_SCU_SPNIDEN_MASK) +#define ADM_CTRL0_ALLOW_SCU_SPIDEN_MASK (0x8U) +#define ADM_CTRL0_ALLOW_SCU_SPIDEN_SHIFT (3U) +#define ADM_CTRL0_ALLOW_SCU_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_SCU_SPIDEN_SHIFT)) & ADM_CTRL0_ALLOW_SCU_SPIDEN_MASK) +#define ADM_CTRL0_SCU_ROM_EXIT_MASK (0x10U) +#define ADM_CTRL0_SCU_ROM_EXIT_SHIFT (4U) +#define ADM_CTRL0_SCU_ROM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_SCU_ROM_EXIT_SHIFT)) & ADM_CTRL0_SCU_ROM_EXIT_MASK) +#define ADM_CTRL0_ALLOW_APPS_NIDEN_MASK (0x1E0U) +#define ADM_CTRL0_ALLOW_APPS_NIDEN_SHIFT (5U) +#define ADM_CTRL0_ALLOW_APPS_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_APPS_NIDEN_SHIFT)) & ADM_CTRL0_ALLOW_APPS_NIDEN_MASK) +#define ADM_CTRL0_ALLOW_APPS_DBGEN_MASK (0x1E00U) +#define ADM_CTRL0_ALLOW_APPS_DBGEN_SHIFT (9U) +#define ADM_CTRL0_ALLOW_APPS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_APPS_DBGEN_SHIFT)) & ADM_CTRL0_ALLOW_APPS_DBGEN_MASK) +#define ADM_CTRL0_ALLOW_APPS_SPNIDEN_MASK (0x1E000U) +#define ADM_CTRL0_ALLOW_APPS_SPNIDEN_SHIFT (13U) +#define ADM_CTRL0_ALLOW_APPS_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_APPS_SPNIDEN_SHIFT)) & ADM_CTRL0_ALLOW_APPS_SPNIDEN_MASK) +#define ADM_CTRL0_ALLOW_APPS_SPIDEN_MASK (0x1E0000U) +#define ADM_CTRL0_ALLOW_APPS_SPIDEN_SHIFT (17U) +#define ADM_CTRL0_ALLOW_APPS_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_ALLOW_APPS_SPIDEN_SHIFT)) & ADM_CTRL0_ALLOW_APPS_SPIDEN_MASK) +#define ADM_CTRL0_DISABLE_CAAM_MASK (0x200000U) +#define ADM_CTRL0_DISABLE_CAAM_SHIFT (21U) +#define ADM_CTRL0_DISABLE_CAAM(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_DISABLE_CAAM_SHIFT)) & ADM_CTRL0_DISABLE_CAAM_MASK) +#define ADM_CTRL0_DISABLE_IEE_MASK (0x400000U) +#define ADM_CTRL0_DISABLE_IEE_SHIFT (22U) +#define ADM_CTRL0_DISABLE_IEE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_DISABLE_IEE_SHIFT)) & ADM_CTRL0_DISABLE_IEE_MASK) +#define ADM_CTRL0_DISABLE_HDCP_MASK (0x800000U) +#define ADM_CTRL0_DISABLE_HDCP_SHIFT (23U) +#define ADM_CTRL0_DISABLE_HDCP(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_DISABLE_HDCP_SHIFT)) & ADM_CTRL0_DISABLE_HDCP_MASK) +#define ADM_CTRL0_DISABLE_DTCP_MASK (0x1000000U) +#define ADM_CTRL0_DISABLE_DTCP_SHIFT (24U) +#define ADM_CTRL0_DISABLE_DTCP(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_DISABLE_DTCP_SHIFT)) & ADM_CTRL0_DISABLE_DTCP_MASK) +#define ADM_CTRL0_DISABLE_CAU_MASK (0x2000000U) +#define ADM_CTRL0_DISABLE_CAU_SHIFT (25U) +#define ADM_CTRL0_DISABLE_CAU(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_DISABLE_CAU_SHIFT)) & ADM_CTRL0_DISABLE_CAU_MASK) +#define ADM_CTRL0_EN_GLITCH_DET_MASK (0x4000000U) +#define ADM_CTRL0_EN_GLITCH_DET_SHIFT (26U) +#define ADM_CTRL0_EN_GLITCH_DET(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_EN_GLITCH_DET_SHIFT)) & ADM_CTRL0_EN_GLITCH_DET_MASK) +#define ADM_CTRL0_TCU_SW_RESET_MASK (0x8000000U) +#define ADM_CTRL0_TCU_SW_RESET_SHIFT (27U) +#define ADM_CTRL0_TCU_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_TCU_SW_RESET_SHIFT)) & ADM_CTRL0_TCU_SW_RESET_MASK) +#define ADM_CTRL0_HDMI_RX_APB_MUX_MASK (0x10000000U) +#define ADM_CTRL0_HDMI_RX_APB_MUX_SHIFT (28U) +#define ADM_CTRL0_HDMI_RX_APB_MUX(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_HDMI_RX_APB_MUX_SHIFT)) & ADM_CTRL0_HDMI_RX_APB_MUX_MASK) +#define ADM_CTRL0_HDMI_TX_APB_MUX_MASK (0x20000000U) +#define ADM_CTRL0_HDMI_TX_APB_MUX_SHIFT (29U) +#define ADM_CTRL0_HDMI_TX_APB_MUX(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_HDMI_TX_APB_MUX_SHIFT)) & ADM_CTRL0_HDMI_TX_APB_MUX_MASK) +#define ADM_CTRL0_HDMI_RX_SECURED_MODE_MASK (0x40000000U) +#define ADM_CTRL0_HDMI_RX_SECURED_MODE_SHIFT (30U) +#define ADM_CTRL0_HDMI_RX_SECURED_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_HDMI_RX_SECURED_MODE_SHIFT)) & ADM_CTRL0_HDMI_RX_SECURED_MODE_MASK) +#define ADM_CTRL0_HDMI_TX_SECURED_MODE_MASK (0x80000000U) +#define ADM_CTRL0_HDMI_TX_SECURED_MODE_SHIFT (31U) +#define ADM_CTRL0_HDMI_TX_SECURED_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL0_HDMI_TX_SECURED_MODE_SHIFT)) & ADM_CTRL0_HDMI_TX_SECURED_MODE_MASK) + +/*! @name CTRL1 - Control register for SCU. */ +#define ADM_CTRL1_CAAM_DID_MASK (0x1FU) +#define ADM_CTRL1_CAAM_DID_SHIFT (0U) +#define ADM_CTRL1_CAAM_DID(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_CAAM_DID_SHIFT)) & ADM_CTRL1_CAAM_DID_MASK) +#define ADM_CTRL1_LOCK_CDID_MASK (0x20U) +#define ADM_CTRL1_LOCK_CDID_SHIFT (5U) +#define ADM_CTRL1_LOCK_CDID(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_LOCK_CDID_SHIFT)) & ADM_CTRL1_LOCK_CDID_MASK) +#define ADM_CTRL1_JTAGC_DISABLE_MASK (0x80U) +#define ADM_CTRL1_JTAGC_DISABLE_SHIFT (7U) +#define ADM_CTRL1_JTAGC_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_JTAGC_DISABLE_SHIFT)) & ADM_CTRL1_JTAGC_DISABLE_MASK) +#define ADM_CTRL1_LOCK_JTAGC_DISABLE_MASK (0x100U) +#define ADM_CTRL1_LOCK_JTAGC_DISABLE_SHIFT (8U) +#define ADM_CTRL1_LOCK_JTAGC_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_LOCK_JTAGC_DISABLE_SHIFT)) & ADM_CTRL1_LOCK_JTAGC_DISABLE_MASK) +#define ADM_CTRL1_PAR_FR_ALLOWED_MASK (0x200U) +#define ADM_CTRL1_PAR_FR_ALLOWED_SHIFT (9U) +#define ADM_CTRL1_PAR_FR_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_PAR_FR_ALLOWED_SHIFT)) & ADM_CTRL1_PAR_FR_ALLOWED_MASK) +#define ADM_CTRL1_FR_ALLOWED_MASK (0x400U) +#define ADM_CTRL1_FR_ALLOWED_SHIFT (10U) +#define ADM_CTRL1_FR_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_FR_ALLOWED_SHIFT)) & ADM_CTRL1_FR_ALLOWED_MASK) +#define ADM_CTRL1_NO_RETURN_ALLOWED_MASK (0x800U) +#define ADM_CTRL1_NO_RETURN_ALLOWED_SHIFT (11U) +#define ADM_CTRL1_NO_RETURN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_NO_RETURN_ALLOWED_SHIFT)) & ADM_CTRL1_NO_RETURN_ALLOWED_MASK) +#define ADM_CTRL1_CNR_ALLOWED_MASK (0x1000U) +#define ADM_CTRL1_CNR_ALLOWED_SHIFT (12U) +#define ADM_CTRL1_CNR_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_CNR_ALLOWED_SHIFT)) & ADM_CTRL1_CNR_ALLOWED_MASK) +#define ADM_CTRL1_LOCKUP_SV_MASK (0x2000U) +#define ADM_CTRL1_LOCKUP_SV_SHIFT (13U) +#define ADM_CTRL1_LOCKUP_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_LOCKUP_SV_SHIFT)) & ADM_CTRL1_LOCKUP_SV_MASK) +#define ADM_CTRL1_UERR_SV_MASK (0x4000U) +#define ADM_CTRL1_UERR_SV_SHIFT (14U) +#define ADM_CTRL1_UERR_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_UERR_SV_SHIFT)) & ADM_CTRL1_UERR_SV_MASK) +#define ADM_CTRL1_TAMPER_SV_MASK (0x8000U) +#define ADM_CTRL1_TAMPER_SV_SHIFT (15U) +#define ADM_CTRL1_TAMPER_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_TAMPER_SV_SHIFT)) & ADM_CTRL1_TAMPER_SV_MASK) +#define ADM_CTRL1_GLITCH_SV_MASK (0x10000U) +#define ADM_CTRL1_GLITCH_SV_SHIFT (16U) +#define ADM_CTRL1_GLITCH_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_GLITCH_SV_SHIFT)) & ADM_CTRL1_GLITCH_SV_MASK) +#define ADM_CTRL1_WDOG_SV_MASK (0x20000U) +#define ADM_CTRL1_WDOG_SV_SHIFT (17U) +#define ADM_CTRL1_WDOG_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_WDOG_SV_SHIFT)) & ADM_CTRL1_WDOG_SV_MASK) +#define ADM_CTRL1_CAAM_SV_MASK (0x40000U) +#define ADM_CTRL1_CAAM_SV_SHIFT (18U) +#define ADM_CTRL1_CAAM_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_CAAM_SV_SHIFT)) & ADM_CTRL1_CAAM_SV_MASK) +#define ADM_CTRL1_OBSERVE_VALUE_MASK (0x380000U) +#define ADM_CTRL1_OBSERVE_VALUE_SHIFT (19U) +#define ADM_CTRL1_OBSERVE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CTRL1_OBSERVE_VALUE_SHIFT)) & ADM_CTRL1_OBSERVE_VALUE_MASK) + +/*! @name STATUS0 - Status register for SCU. */ +#define ADM_STATUS0_SCU_NIDEN_ALLOWED_MASK (0x1U) +#define ADM_STATUS0_SCU_NIDEN_ALLOWED_SHIFT (0U) +#define ADM_STATUS0_SCU_NIDEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SCU_NIDEN_ALLOWED_SHIFT)) & ADM_STATUS0_SCU_NIDEN_ALLOWED_MASK) +#define ADM_STATUS0_SCU_DBGEN_ALLOWED_MASK (0x2U) +#define ADM_STATUS0_SCU_DBGEN_ALLOWED_SHIFT (1U) +#define ADM_STATUS0_SCU_DBGEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SCU_DBGEN_ALLOWED_SHIFT)) & ADM_STATUS0_SCU_DBGEN_ALLOWED_MASK) +#define ADM_STATUS0_SCU_SPNIDEN_ALLOWED_MASK (0x4U) +#define ADM_STATUS0_SCU_SPNIDEN_ALLOWED_SHIFT (2U) +#define ADM_STATUS0_SCU_SPNIDEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SCU_SPNIDEN_ALLOWED_SHIFT)) & ADM_STATUS0_SCU_SPNIDEN_ALLOWED_MASK) +#define ADM_STATUS0_SCU_SPIDEN_ALLOWED_MASK (0x8U) +#define ADM_STATUS0_SCU_SPIDEN_ALLOWED_SHIFT (3U) +#define ADM_STATUS0_SCU_SPIDEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SCU_SPIDEN_ALLOWED_SHIFT)) & ADM_STATUS0_SCU_SPIDEN_ALLOWED_MASK) +#define ADM_STATUS0_SECO_DBGEN_ALLOWED_MASK (0x10U) +#define ADM_STATUS0_SECO_DBGEN_ALLOWED_SHIFT (4U) +#define ADM_STATUS0_SECO_DBGEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SECO_DBGEN_ALLOWED_SHIFT)) & ADM_STATUS0_SECO_DBGEN_ALLOWED_MASK) +#define ADM_STATUS0_APPS_NIDEN_ALLOWED_MASK (0x1E0U) +#define ADM_STATUS0_APPS_NIDEN_ALLOWED_SHIFT (5U) +#define ADM_STATUS0_APPS_NIDEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APPS_NIDEN_ALLOWED_SHIFT)) & ADM_STATUS0_APPS_NIDEN_ALLOWED_MASK) +#define ADM_STATUS0_APPS_DBGEN_ALLOWED_MASK (0x1E00U) +#define ADM_STATUS0_APPS_DBGEN_ALLOWED_SHIFT (9U) +#define ADM_STATUS0_APPS_DBGEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APPS_DBGEN_ALLOWED_SHIFT)) & ADM_STATUS0_APPS_DBGEN_ALLOWED_MASK) +#define ADM_STATUS0_APPS_SPNIDEN_ALLOWED_MASK (0x1E000U) +#define ADM_STATUS0_APPS_SPNIDEN_ALLOWED_SHIFT (13U) +#define ADM_STATUS0_APPS_SPNIDEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APPS_SPNIDEN_ALLOWED_SHIFT)) & ADM_STATUS0_APPS_SPNIDEN_ALLOWED_MASK) +#define ADM_STATUS0_APPS_SPIDEN_ALLOWED_MASK (0x1E0000U) +#define ADM_STATUS0_APPS_SPIDEN_ALLOWED_SHIFT (17U) +#define ADM_STATUS0_APPS_SPIDEN_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APPS_SPIDEN_ALLOWED_SHIFT)) & ADM_STATUS0_APPS_SPIDEN_ALLOWED_MASK) +#define ADM_STATUS0_EARLY_FUSES_VALID_MASK (0x200000U) +#define ADM_STATUS0_EARLY_FUSES_VALID_SHIFT (21U) +#define ADM_STATUS0_EARLY_FUSES_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_EARLY_FUSES_VALID_SHIFT)) & ADM_STATUS0_EARLY_FUSES_VALID_MASK) +#define ADM_STATUS0_SCU_FUSES_VALID_MASK (0x400000U) +#define ADM_STATUS0_SCU_FUSES_VALID_SHIFT (22U) +#define ADM_STATUS0_SCU_FUSES_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SCU_FUSES_VALID_SHIFT)) & ADM_STATUS0_SCU_FUSES_VALID_MASK) +#define ADM_STATUS0_ALL_FUSES_VALID_MASK (0x800000U) +#define ADM_STATUS0_ALL_FUSES_VALID_SHIFT (23U) +#define ADM_STATUS0_ALL_FUSES_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_ALL_FUSES_VALID_SHIFT)) & ADM_STATUS0_ALL_FUSES_VALID_MASK) +#define ADM_STATUS0_HAB_ONLY_CRYPTO_MASK (0x1000000U) +#define ADM_STATUS0_HAB_ONLY_CRYPTO_SHIFT (24U) +#define ADM_STATUS0_HAB_ONLY_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_HAB_ONLY_CRYPTO_SHIFT)) & ADM_STATUS0_HAB_ONLY_CRYPTO_MASK) +#define ADM_STATUS0_APB_GPR_ILLEGAL_RD_MASK (0x2000000U) +#define ADM_STATUS0_APB_GPR_ILLEGAL_RD_SHIFT (25U) +#define ADM_STATUS0_APB_GPR_ILLEGAL_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APB_GPR_ILLEGAL_RD_SHIFT)) & ADM_STATUS0_APB_GPR_ILLEGAL_RD_MASK) +#define ADM_STATUS0_APB_GPR_ILLEGAL_WR_MASK (0x4000000U) +#define ADM_STATUS0_APB_GPR_ILLEGAL_WR_SHIFT (26U) +#define ADM_STATUS0_APB_GPR_ILLEGAL_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APB_GPR_ILLEGAL_WR_SHIFT)) & ADM_STATUS0_APB_GPR_ILLEGAL_WR_MASK) +#define ADM_STATUS0_APB_SCU_GPR_ILLEGAL_RD_MASK (0x8000000U) +#define ADM_STATUS0_APB_SCU_GPR_ILLEGAL_RD_SHIFT (27U) +#define ADM_STATUS0_APB_SCU_GPR_ILLEGAL_RD(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APB_SCU_GPR_ILLEGAL_RD_SHIFT)) & ADM_STATUS0_APB_SCU_GPR_ILLEGAL_RD_MASK) +#define ADM_STATUS0_APB_SCU_GPR_ILLEGAL_WR_MASK (0x10000000U) +#define ADM_STATUS0_APB_SCU_GPR_ILLEGAL_WR_SHIFT (28U) +#define ADM_STATUS0_APB_SCU_GPR_ILLEGAL_WR(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_APB_SCU_GPR_ILLEGAL_WR_SHIFT)) & ADM_STATUS0_APB_SCU_GPR_ILLEGAL_WR_MASK) +#define ADM_STATUS0_SDP_DISABLE_MASK (0x20000000U) +#define ADM_STATUS0_SDP_DISABLE_SHIFT (29U) +#define ADM_STATUS0_SDP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SDP_DISABLE_SHIFT)) & ADM_STATUS0_SDP_DISABLE_MASK) +#define ADM_STATUS0_SDP_WO_MASK (0x40000000U) +#define ADM_STATUS0_SDP_WO_SHIFT (30U) +#define ADM_STATUS0_SDP_WO(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SDP_WO_SHIFT)) & ADM_STATUS0_SDP_WO_MASK) +#define ADM_STATUS0_SECO_FW_MASK (0x80000000U) +#define ADM_STATUS0_SECO_FW_SHIFT (31U) +#define ADM_STATUS0_SECO_FW(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS0_SECO_FW_SHIFT)) & ADM_STATUS0_SECO_FW_MASK) + +/*! @name STATUS1 - Status register for SCU. */ +#define ADM_STATUS1_CL_SV_MASK (0x1U) +#define ADM_STATUS1_CL_SV_SHIFT (0U) +#define ADM_STATUS1_CL_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_CL_SV_SHIFT)) & ADM_STATUS1_CL_SV_MASK) +#define ADM_STATUS1_UERR_SV_MASK (0x2U) +#define ADM_STATUS1_UERR_SV_SHIFT (1U) +#define ADM_STATUS1_UERR_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_UERR_SV_SHIFT)) & ADM_STATUS1_UERR_SV_MASK) +#define ADM_STATUS1_TAMPER_SV_MASK (0x4U) +#define ADM_STATUS1_TAMPER_SV_SHIFT (2U) +#define ADM_STATUS1_TAMPER_SV(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_TAMPER_SV_SHIFT)) & ADM_STATUS1_TAMPER_SV_MASK) +#define ADM_STATUS1_LIFE_CYCLE_MASK (0x3FF8U) +#define ADM_STATUS1_LIFE_CYCLE_SHIFT (3U) +#define ADM_STATUS1_LIFE_CYCLE(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_LIFE_CYCLE_SHIFT)) & ADM_STATUS1_LIFE_CYCLE_MASK) +#define ADM_STATUS1_HDCP_ENCRYPTED_MASK (0x4000U) +#define ADM_STATUS1_HDCP_ENCRYPTED_SHIFT (14U) +#define ADM_STATUS1_HDCP_ENCRYPTED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_HDCP_ENCRYPTED_SHIFT)) & ADM_STATUS1_HDCP_ENCRYPTED_MASK) +#define ADM_STATUS1_NXP_SECRETS_PRESENT_MASK (0x8000U) +#define ADM_STATUS1_NXP_SECRETS_PRESENT_SHIFT (15U) +#define ADM_STATUS1_NXP_SECRETS_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_NXP_SECRETS_PRESENT_SHIFT)) & ADM_STATUS1_NXP_SECRETS_PRESENT_MASK) +#define ADM_STATUS1_SECO_HOLD_MASK (0x10000U) +#define ADM_STATUS1_SECO_HOLD_SHIFT (16U) +#define ADM_STATUS1_SECO_HOLD(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_SECO_HOLD_SHIFT)) & ADM_STATUS1_SECO_HOLD_MASK) +#define ADM_STATUS1_SCU_HOLD_MASK (0x20000U) +#define ADM_STATUS1_SCU_HOLD_SHIFT (17U) +#define ADM_STATUS1_SCU_HOLD(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_SCU_HOLD_SHIFT)) & ADM_STATUS1_SCU_HOLD_MASK) +#define ADM_STATUS1_SNVS_HOLD_MASK (0x40000U) +#define ADM_STATUS1_SNVS_HOLD_SHIFT (18U) +#define ADM_STATUS1_SNVS_HOLD(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_SNVS_HOLD_SHIFT)) & ADM_STATUS1_SNVS_HOLD_MASK) +#define ADM_STATUS1_FIELD_IS_PROGRAMMED_MASK (0x80000U) +#define ADM_STATUS1_FIELD_IS_PROGRAMMED_SHIFT (19U) +#define ADM_STATUS1_FIELD_IS_PROGRAMMED(x) (((uint32_t)(((uint32_t)(x)) << ADM_STATUS1_FIELD_IS_PROGRAMMED_SHIFT)) & ADM_STATUS1_FIELD_IS_PROGRAMMED_MASK) + +/*! @name GPR0 - */ +#define ADM_GPR0_BANK0_MASK (0xFFFFFFFFU) +#define ADM_GPR0_BANK0_SHIFT (0U) +#define ADM_GPR0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR0_BANK0_SHIFT)) & ADM_GPR0_BANK0_MASK) + +/* The count of ADM_GPR0 */ +#define ADM_GPR0_COUNT (4U) + +/*! @name GPR1 - */ +#define ADM_GPR1_BANK1_MASK (0xFFFFFFFFU) +#define ADM_GPR1_BANK1_SHIFT (0U) +#define ADM_GPR1_BANK1(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR1_BANK1_SHIFT)) & ADM_GPR1_BANK1_MASK) + +/* The count of ADM_GPR1 */ +#define ADM_GPR1_COUNT (4U) + +/*! @name GPR2 - */ +#define ADM_GPR2_BANK2_MASK (0xFFFFFFFFU) +#define ADM_GPR2_BANK2_SHIFT (0U) +#define ADM_GPR2_BANK2(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR2_BANK2_SHIFT)) & ADM_GPR2_BANK2_MASK) + +/* The count of ADM_GPR2 */ +#define ADM_GPR2_COUNT (4U) + +/*! @name GPR3 - */ +#define ADM_GPR3_BANK3_MASK (0xFFFFFFFFU) +#define ADM_GPR3_BANK3_SHIFT (0U) +#define ADM_GPR3_BANK3(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR3_BANK3_SHIFT)) & ADM_GPR3_BANK3_MASK) + +/* The count of ADM_GPR3 */ +#define ADM_GPR3_COUNT (4U) + +/*! @name GPR4 - */ +#define ADM_GPR4_BANK4_MASK (0xFFFFFFFFU) +#define ADM_GPR4_BANK4_SHIFT (0U) +#define ADM_GPR4_BANK4(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR4_BANK4_SHIFT)) & ADM_GPR4_BANK4_MASK) + +/* The count of ADM_GPR4 */ +#define ADM_GPR4_COUNT (4U) + +/*! @name GPR5 - */ +#define ADM_GPR5_BANK5_MASK (0xFFFFFFFFU) +#define ADM_GPR5_BANK5_SHIFT (0U) +#define ADM_GPR5_BANK5(x) (((uint32_t)(((uint32_t)(x)) << ADM_GPR5_BANK5_SHIFT)) & ADM_GPR5_BANK5_MASK) + +/* The count of ADM_GPR5 */ +#define ADM_GPR5_COUNT (4U) + +/*! @name SECO_SUPER_ROOT_KEY_HASH - */ +#define ADM_SECO_SUPER_ROOT_KEY_HASH_VALUE_MASK (0xFFFFFFFFU) +#define ADM_SECO_SUPER_ROOT_KEY_HASH_VALUE_SHIFT (0U) +#define ADM_SECO_SUPER_ROOT_KEY_HASH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ADM_SECO_SUPER_ROOT_KEY_HASH_VALUE_SHIFT)) & ADM_SECO_SUPER_ROOT_KEY_HASH_VALUE_MASK) + +/* The count of ADM_SECO_SUPER_ROOT_KEY_HASH */ +#define ADM_SECO_SUPER_ROOT_KEY_HASH_COUNT (8U) + +/*! @name HDMI_SUPER_ROOT_KEY_HASH - */ +#define ADM_HDMI_SUPER_ROOT_KEY_HASH_VALUE_MASK (0xFFFFFFFFU) +#define ADM_HDMI_SUPER_ROOT_KEY_HASH_VALUE_SHIFT (0U) +#define ADM_HDMI_SUPER_ROOT_KEY_HASH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ADM_HDMI_SUPER_ROOT_KEY_HASH_VALUE_SHIFT)) & ADM_HDMI_SUPER_ROOT_KEY_HASH_VALUE_MASK) + +/* The count of ADM_HDMI_SUPER_ROOT_KEY_HASH */ +#define ADM_HDMI_SUPER_ROOT_KEY_HASH_COUNT (8U) + +/*! @name CAAM_PWRCTRL_REF - CAAM PWRCTRL reg for reference */ +#define ADM_CAAM_PWRCTRL_REF_VALUE_MASK (0xFFFFFFU) +#define ADM_CAAM_PWRCTRL_REF_VALUE_SHIFT (0U) +#define ADM_CAAM_PWRCTRL_REF_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ADM_CAAM_PWRCTRL_REF_VALUE_SHIFT)) & ADM_CAAM_PWRCTRL_REF_VALUE_MASK) +#define ADM_CAAM_PWRCTRL_REF_LOCK_PWR_REF_MASK (0x80000000U) +#define ADM_CAAM_PWRCTRL_REF_LOCK_PWR_REF_SHIFT (31U) +#define ADM_CAAM_PWRCTRL_REF_LOCK_PWR_REF(x) (((uint32_t)(((uint32_t)(x)) << ADM_CAAM_PWRCTRL_REF_LOCK_PWR_REF_SHIFT)) & ADM_CAAM_PWRCTRL_REF_LOCK_PWR_REF_MASK) + +/*! @name SPARE - */ +#define ADM_SPARE_VALUE_MASK (0xFFFFFFFFU) +#define ADM_SPARE_VALUE_SHIFT (0U) +#define ADM_SPARE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ADM_SPARE_VALUE_SHIFT)) & ADM_SPARE_VALUE_MASK) + +/* The count of ADM_SPARE */ +#define ADM_SPARE_COUNT (4U) + + +/*! + * @} + */ /* end of group ADM_Register_Masks */ + + +/* ADM - Peripheral instance base addresses */ +/** Peripheral ADM base pointer */ +#define ADM ((ADM_Type *)ADM_BASE) +/** Array initializer of ADM peripheral base addresses */ +#define ADM_BASE_ADDRS { ADM_BASE } +/** Array initializer of ADM peripheral base pointers */ +#define ADM_BASE_PTRS { ADM } + +/*! + * @} + */ /* end of group ADM_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* ADM_H */ + diff --git a/platform/devices/MX8/MX8_asmc.h b/platform/devices/MX8/MX8_asmc.h new file mode 100755 index 0000000..3a64970 --- /dev/null +++ b/platform/devices/MX8/MX8_asmc.h @@ -0,0 +1,171 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_ASMC_REGISTERS_H +#define HW_ASMC_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- ASMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer + * @{ + */ + +/** ASMC - Register Layout Typedef */ +typedef struct { + __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */ + __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */ + __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */ + __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */ +} ASMC_Type; + +/* ---------------------------------------------------------------------------- + -- ASMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASMC_Register_Masks ASMC Register Masks + * @{ + */ + +/*! @name SRS - System Reset Status Register */ +#define ASMC_SRS_WAKEUP_MASK (0x1U) +#define ASMC_SRS_WAKEUP_SHIFT (0U) +#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK) +#define ASMC_SRS_WDOG1_MASK (0x20U) +#define ASMC_SRS_WDOG1_SHIFT (5U) +#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK) +#define ASMC_SRS_RES_MASK (0x40U) +#define ASMC_SRS_RES_SHIFT (6U) +#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK) +#define ASMC_SRS_POR_MASK (0x80U) +#define ASMC_SRS_POR_SHIFT (7U) +#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK) +#define ASMC_SRS_LOCKUP_MASK (0x200U) +#define ASMC_SRS_LOCKUP_SHIFT (9U) +#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK) +#define ASMC_SRS_SW_MASK (0x400U) +#define ASMC_SRS_SW_SHIFT (10U) +#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK) +#define ASMC_SRS_UECC_MASK (0x1000U) +#define ASMC_SRS_UECC_SHIFT (12U) +#define ASMC_SRS_UECC(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_UECC_SHIFT)) & ASMC_SRS_UECC_MASK) + +#define ASMC_SRSH_MSI_MASK (0x10000U) +#define ASMC_SRSH_MSI_SHIFT (16U) +#define ASMC_SRSH_MSI(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRSH_MSI_SHIFT)) & ASMC_SRSH_MSI_MASK) +#define ASMC_SRSH_SNVS_MASK (0x20000U) +#define ASMC_SRSH_SNVS_SHIFT (17U) +#define ASMC_SRSH_PANIC(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRSH_PANIC_SHIFT)) & ASMC_SRSH_PANIC_MASK) +#define ASMC_SRSH_PANIC_MASK (0x40000U) +#define ASMC_SRSH_PANIC_SHIFT (18U) +#define ASMC_SRSH_PANIC(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRSH_PANIC_SHIFT)) & ASMC_SRSH_PANIC_MASK) +#define ASMC_SRSH_JTAG_MASK (0x80000U) +#define ASMC_SRSH_JTAG_SHIFT (19U) +#define ASMC_SRSH_JTAG(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRSH_JTAG_SHIFT)) & ASMC_SRSH_JTAG_MASK) +#define ASMC_SRSH_WDOG_MASK (0x100000U) +#define ASMC_SRSH_WDOG_SHIFT (20U) +#define ASMC_SRSH_WDOG(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRSH_WDOG_SHIFT)) & ASMC_SRSH_WDOG_MASK) +#define ASMC_SRSH_SW_MASK (0x200000U) +#define ASMC_SRSH_SW_SHIFT (21U) +#define ASMC_SRSH_SRS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRSH_SW_SHIFT)) & ASMC_SRSH_SW_MASK) + +/*! @name PMPROT - Power Mode Protection register */ +#define ASMC_PMPROT_AVLLS_MASK (0x2U) +#define ASMC_PMPROT_AVLLS_SHIFT (1U) +#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK) +#define ASMC_PMPROT_ALLS_MASK (0x8U) +#define ASMC_PMPROT_ALLS_SHIFT (3U) +#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK) +#define ASMC_PMPROT_AVLP_MASK (0x20U) +#define ASMC_PMPROT_AVLP_SHIFT (5U) +#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK) +#define ASMC_PMPROT_AHSRUN_MASK (0x80U) +#define ASMC_PMPROT_AHSRUN_SHIFT (7U) +#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK) + +/*! @name PMCTRL - Power Mode Control register */ +#define ASMC_PMCTRL_STOPM_MASK (0x7U) +#define ASMC_PMCTRL_STOPM_SHIFT (0U) +#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK) +#define ASMC_PMCTRL_RUNM_MASK (0x60U) +#define ASMC_PMCTRL_RUNM_SHIFT (5U) +#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK) + +/*! @name STOPCTRL - Stop Control Register */ +#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U) +#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U) +#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK) + +/*! @name PMSTAT - Power Mode Status register */ +#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) +#define ASMC_PMSTAT_PMSTAT_SHIFT (0U) +#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) + + +/*! + * @} + */ /* end of group ASMC_Register_Masks */ + + +/** Peripheral ASMC base pointer */ +#define ASMC ((ASMC_Type *)ASMC_BASE) +/** Array initializer of ASMC peripheral base addresses */ +#define ASMC_BASE_ADDRS { ASMC_BASE } +/** Array initializer of ASMC peripheral base pointers */ +#define ASMC_BASE_PTRS { ASMC } + +/*! + * @} + */ /* end of group ASMC_Peripheral_Access_Layer */ + +#endif /* HW_ASMC_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_csr.h b/platform/devices/MX8/MX8_csr.h new file mode 100755 index 0000000..684a10b --- /dev/null +++ b/platform/devices/MX8/MX8_csr.h @@ -0,0 +1,150 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file MX8_csr.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for CSR + * + * CMSIS Peripheral Access Layer for CSR + */ + +#ifndef CSR_H +#define CSR_H /**< Symbol preventing repeated inclusion */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- CSR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSR_Peripheral_Access_Layer CSR Peripheral Access Layer + * @{ + */ + +/** CSR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR_LP_PG[16]; /**< Control and Status Registers, LP_PG0-LP_PG3 offset 0x9000 */ + __IO uint32_t CSR_PORT_CONFIG; /**< Control and Status Registers, PORT_CONFIG offset 0x9040 */ + uint8_t RESERVED_18[188]; + __IO uint32_t GPR_CSR_CTRL[196]; /**< Control and Status Registers, offset 0x9100 */ +} CSR_Type; + +/** CSR2 - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR_CSR_CTRL[256]; /**< Control and Status Registers, offset 0x9100 */ +} CSR2_Type; + +/* CSR - Peripheral instance base addresses */ +/** Peripheral CSR base address */ +#define CSR_BASE (0u) +/** Peripheral CSR base pointer */ +#define CSR ((CSR_Type *)CSR_BASE) +/** Array initializer of CSR peripheral base addresses */ +#define CSR_BASE_ADDRS { CSR_BASE } +/** Array initializer of CSR peripheral base pointers */ +#define CSR_BASE_PTRS { CSR } + +/*! + * @} + */ /* end of group CSR_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* CSR_H */ + diff --git a/platform/devices/MX8/MX8_ddr_phy.h b/platform/devices/MX8/MX8_ddr_phy.h new file mode 100755 index 0000000..afbb594 --- /dev/null +++ b/platform/devices/MX8/MX8_ddr_phy.h @@ -0,0 +1,1925 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** ################################################################### +*/ + +#ifndef HW_DDR_PHY_REGISTERS_H +#define HW_DDR_PHY_REGISTERS_H + +//JDG change base addr for DDR_PHY +#define DDR_PHY_BASE_ADDR(X) (0x5c000000UL + ((U32(X) * 0x100000UL) + 0x10000UL)) + +// Following defines registers offset of the Synopsys DesignWare Cores LPDDR4 multiPHY Utility Block (PUB) +#define DDR_PHY_RIDR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x000U)) +#define DDR_PHY_RIDR_0 0x5c010000 +#define DDR_PHY_RIDR_1 0x5c110000 +#define DDR_PHY_PIR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x001U)) +#define DDR_PHY_PIR_0 0x5c010004 +#define DDR_PHY_PIR_1 0x5c110004 +#define DDR_PHY_PGCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x004U)) +#define DDR_PHY_PGCR0_0 0x5c010010 +#define DDR_PHY_PGCR0_1 0x5c110010 +#define DDR_PHY_PGCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x005U)) +#define DDR_PHY_PGCR1_0 0x5c010014 +#define DDR_PHY_PGCR1_1 0x5c110014 +#define DDR_PHY_PGCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x006U)) +#define DDR_PHY_PGCR2_0 0x5c010018 +#define DDR_PHY_PGCR2_1 0x5c110018 +#define DDR_PHY_PGCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x007U)) +#define DDR_PHY_PGCR3_0 0x5c01001c +#define DDR_PHY_PGCR3_1 0x5c11001c +#define DDR_PHY_PGCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x008U)) +#define DDR_PHY_PGCR4_0 0x5c010020 +#define DDR_PHY_PGCR4_1 0x5c110020 +#define DDR_PHY_PGCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x009U)) +#define DDR_PHY_PGCR5_0 0x5c010024 +#define DDR_PHY_PGCR5_1 0x5c110024 +#define DDR_PHY_PGCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x00AU)) +#define DDR_PHY_PGCR6_0 0x5c010028 +#define DDR_PHY_PGCR6_1 0x5c110028 +#define DDR_PHY_PGCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x00BU)) +#define DDR_PHY_PGCR7_0 0x5c01002c +#define DDR_PHY_PGCR7_1 0x5c11002c +#define DDR_PHY_PGSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x00CU)) +#define DDR_PHY_PGSR0_0 0x5c010030 +#define DDR_PHY_PGSR0_1 0x5c110030 +#define DDR_PHY_PGSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x00DU)) +#define DDR_PHY_PGSR1_0 0x5c010034 +#define DDR_PHY_PGSR1_1 0x5c110034 +#define DDR_PHY_PGSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x00EU)) +#define DDR_PHY_PGSR2_0 0x5c010038 +#define DDR_PHY_PGSR2_1 0x5c110038 +#define DDR_PHY_PTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x010U)) +#define DDR_PHY_PTR0_0 0x5c010040 +#define DDR_PHY_PTR0_1 0x5c110040 +#define DDR_PHY_PTR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x011U)) +#define DDR_PHY_PTR1_0 0x5c010044 +#define DDR_PHY_PTR1_1 0x5c110044 +#define DDR_PHY_PTR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x012U)) +#define DDR_PHY_PTR2_0 0x5c010048 +#define DDR_PHY_PTR2_1 0x5c110048 +#define DDR_PHY_PTR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x013U)) +#define DDR_PHY_PTR3_0 0x5c01004c +#define DDR_PHY_PTR3_1 0x5c11004c +#define DDR_PHY_PTR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x014U)) +#define DDR_PHY_PTR4_0 0x5c010050 +#define DDR_PHY_PTR4_1 0x5c110050 +#define DDR_PHY_PTR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x015U)) +#define DDR_PHY_PTR5_0 0x5c010054 +#define DDR_PHY_PTR5_1 0x5c110054 +#define DDR_PHY_PTR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x016U)) +#define DDR_PHY_PTR6_0 0x5c010058 +#define DDR_PHY_PTR6_1 0x5c110058 +#define DDR_PHY_PLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x01AU)) +#define DDR_PHY_PLLCR0_0 0x5c010068 +#define DDR_PHY_PLLCR0_1 0x5c110068 +#define DDR_PHY_PLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x01BU)) +#define DDR_PHY_PLLCR1_0 0x5c01006c +#define DDR_PHY_PLLCR1_1 0x5c11006c +#define DDR_PHY_PLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x01CU)) +#define DDR_PHY_PLLCR2_0 0x5c010070 +#define DDR_PHY_PLLCR2_1 0x5c110070 +#define DDR_PHY_PLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x01DU)) +#define DDR_PHY_PLLCR3_0 0x5c010074 +#define DDR_PHY_PLLCR3_1 0x5c110074 +#define DDR_PHY_PLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x01EU)) +#define DDR_PHY_PLLCR4_0 0x5c010078 +#define DDR_PHY_PLLCR4_1 0x5c110078 +#define DDR_PHY_PLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x01FU)) +#define DDR_PHY_PLLCR5_0 0x5c01007c +#define DDR_PHY_PLLCR5_1 0x5c11007c +#define DDR_PHY_DXCCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x022U)) +#define DDR_PHY_DXCCR_0 0x5c010088 +#define DDR_PHY_DXCCR_1 0x5c110088 +#define DDR_PHY_DSGCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x024U)) +#define DDR_PHY_DSGCR_0 0x5c010090 +#define DDR_PHY_DSGCR_1 0x5c110090 +#define DDR_PHY_ODTCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x026U)) +#define DDR_PHY_ODTCR_0 0x5c010098 +#define DDR_PHY_ODTCR_1 0x5c110098 +#define DDR_PHY_AACR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x028U)) +#define DDR_PHY_AACR_0 0x5c0100a0 +#define DDR_PHY_AACR_1 0x5c1100a0 +#define DDR_PHY_GPR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x030U)) +#define DDR_PHY_GPR0_0 0x5c0100c0 +#define DDR_PHY_GPR0_1 0x5c1100c0 +#define DDR_PHY_GPR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x031U)) +#define DDR_PHY_GPR1_0 0x5c0100c4 +#define DDR_PHY_GPR1_1 0x5c1100c4 +#define DDR_PHY_DCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x040U)) +#define DDR_PHY_DCR_0 0x5c010100 +#define DDR_PHY_DCR_1 0x5c110100 +#define DDR_PHY_DTPR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x044U)) +#define DDR_PHY_DTPR0_0 0x5c010110 +#define DDR_PHY_DTPR0_1 0x5c110110 +#define DDR_PHY_DTPR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x045U)) +#define DDR_PHY_DTPR1_0 0x5c010114 +#define DDR_PHY_DTPR1_1 0x5c110114 +#define DDR_PHY_DTPR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x046U)) +#define DDR_PHY_DTPR2_0 0x5c010118 +#define DDR_PHY_DTPR2_1 0x5c110118 +#define DDR_PHY_DTPR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x047U)) +#define DDR_PHY_DTPR3_0 0x5c01011c +#define DDR_PHY_DTPR3_1 0x5c11011c +#define DDR_PHY_DTPR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x048U)) +#define DDR_PHY_DTPR4_0 0x5c010120 +#define DDR_PHY_DTPR4_1 0x5c110120 +#define DDR_PHY_DTPR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x049U)) +#define DDR_PHY_DTPR5_0 0x5c010124 +#define DDR_PHY_DTPR5_1 0x5c110124 +#define DDR_PHY_RDIMMGCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x050U)) +#define DDR_PHY_RDIMMGCR0_0 0x5c010140 +#define DDR_PHY_RDIMMGCR0_1 0x5c110140 +#define DDR_PHY_RDIMMGCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x051U)) +#define DDR_PHY_RDIMMGCR1_0 0x5c010144 +#define DDR_PHY_RDIMMGCR1_1 0x5c110144 +#define DDR_PHY_RDIMMGCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x052U) +#define DDR_PHY_RDIMMGCR2_0 0x5c010148 +#define DDR_PHY_RDIMMGCR2_1 0x5c110148 +#define DDR_PHY_RDIMMCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x054U)) +#define DDR_PHY_RDIMMCR0_0 0x5c010150 +#define DDR_PHY_RDIMMCR0_1 0x5c110150 +#define DDR_PHY_RDIMMCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x055U)) +#define DDR_PHY_RDIMMCR1_0 0x5c010154 +#define DDR_PHY_RDIMMCR1_1 0x5c110154 +#define DDR_PHY_RDIMMCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x056U)) +#define DDR_PHY_RDIMMCR2_0 0x5c010158 +#define DDR_PHY_RDIMMCR2_1 0x5c110158 +#define DDR_PHY_RDIMMCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x057U)) +#define DDR_PHY_RDIMMCR3_0 0x5c01015c +#define DDR_PHY_RDIMMCR3_1 0x5c11015c +#define DDR_PHY_RDIMMCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x058U)) +#define DDR_PHY_RDIMMCR4_0 0x5c010160 +#define DDR_PHY_RDIMMCR4_1 0x5c110160 +#define DDR_PHY_SCHCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x05AU)) +#define DDR_PHY_SCHCR0_0 0x5c010168 +#define DDR_PHY_SCHCR0_1 0x5c110168 +#define DDR_PHY_SCHCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x05BU)) +#define DDR_PHY_SCHCR1_0 0x5c01016c +#define DDR_PHY_SCHCR1_1 0x5c11016c +#define DDR_PHY_MR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x060U)) +#define DDR_PHY_MR0_0 0x5c010180 +#define DDR_PHY_MR0_1 0x5c110180 +#define DDR_PHY_MR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x061U)) +#define DDR_PHY_MR1_0 0x5c010184 +#define DDR_PHY_MR1_1 0x5c110184 +#define DDR_PHY_MR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x062U)) +#define DDR_PHY_MR2_0 0x5c010188 +#define DDR_PHY_MR2_1 0x5c110188 +#define DDR_PHY_MR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x063U)) +#define DDR_PHY_MR3_0 0x5c01018c +#define DDR_PHY_MR3_1 0x5c11018c +#define DDR_PHY_MR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x064U)) +#define DDR_PHY_MR4_0 0x5c010190 +#define DDR_PHY_MR4_1 0x5c110190 +#define DDR_PHY_MR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x065U)) +#define DDR_PHY_MR5_0 0x5c010194 +#define DDR_PHY_MR5_1 0x5c110194 +#define DDR_PHY_MR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x066U)) +#define DDR_PHY_MR6_0 0x5c010198 +#define DDR_PHY_MR6_1 0x5c110198 +#define DDR_PHY_MR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x067U)) +#define DDR_PHY_MR7_0 0x5c01019c +#define DDR_PHY_MR7_1 0x5c11019c +#define DDR_PHY_MR11(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x06BU)) +#define DDR_PHY_MR11_0 0x5c0101ac +#define DDR_PHY_MR11_1 0x5c1101ac +#define DDR_PHY_MR12(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x06CU)) +#define DDR_PHY_MR12_0 0x5c0101b0 +#define DDR_PHY_MR12_1 0x5c1101b0 +#define DDR_PHY_MR13(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x06DU)) +#define DDR_PHY_MR13_0 0x5c0101b4 +#define DDR_PHY_MR13_1 0x5c1101b4 +#define DDR_PHY_MR14(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x06EU)) +#define DDR_PHY_MR14_0 0x5c0101b8 +#define DDR_PHY_MR14_1 0x5c1101b8 +#define DDR_PHY_MR22(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x076U)) +#define DDR_PHY_MR22_0 0x5c0101d8 +#define DDR_PHY_MR22_1 0x5c1101d8 +#define DDR_PHY_DTCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x080U)) +#define DDR_PHY_DTCR0_0 0x5c010200 +#define DDR_PHY_DTCR0_1 0x5c110200 +#define DDR_PHY_DTCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x081U)) +#define DDR_PHY_DTCR1_0 0x5c010204 +#define DDR_PHY_DTCR1_1 0x5c110204 +#define DDR_PHY_DTAR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x082U)) +#define DDR_PHY_DTAR0_0 0x5c010208 +#define DDR_PHY_DTAR0_1 0x5c110208 +#define DDR_PHY_DTAR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x083U)) +#define DDR_PHY_DTAR1_0 0x5c01020c +#define DDR_PHY_DTAR1_1 0x5c11020c +#define DDR_PHY_DTAR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x084U)) +#define DDR_PHY_DTAR2_0 0x5c010210 +#define DDR_PHY_DTAR2_1 0x5c110210 +#define DDR_PHY_DTDR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x086U)) +#define DDR_PHY_DTDR0_0 0x5c010218 +#define DDR_PHY_DTDR0_1 0x5c110218 +#define DDR_PHY_DTDR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x087U)) +#define DDR_PHY_DTDR1_0 0x5c01021c +#define DDR_PHY_DTDR1_1 0x5c11021c +#define DDR_PHY_DTEDR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x08CU)) +#define DDR_PHY_DTEDR0_0 0x5c010230 +#define DDR_PHY_DTEDR0_1 0x5c110230 +#define DDR_PHY_DTEDR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x08CU)) +#define DDR_PHY_DTEDR1_0 0x5c010230 +#define DDR_PHY_DTEDR1_1 0x5c110230 +#define DDR_PHY_DTEDR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x08CU)) +#define DDR_PHY_DTEDR2_0 0x5c010230 +#define DDR_PHY_DTEDR2_1 0x5c110230 +#define DDR_PHY_VTDR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x08FU)) +#define DDR_PHY_VTDR_0 0x5c01023c +#define DDR_PHY_VTDR_1 0x5c11023c +#define DDR_PHY_CATR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x090U)) +#define DDR_PHY_CATR0_0 0x5c010240 +#define DDR_PHY_CATR0_1 0x5c110240 +#define DDR_PHY_CATR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x091U)) +#define DDR_PHY_CATR1_0 0x5c010244 +#define DDR_PHY_CATR1_1 0x5c110244 +#define DDR_PHY_PGCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x092U)) +#define DDR_PHY_PGCR8_0 0x5c010248 +#define DDR_PHY_PGCR8_1 0x5c110248 +#define DDR_PHY_DQSDR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x094U)) +#define DDR_PHY_DQSDR0_0 0x5c010250 +#define DDR_PHY_DQSDR0_1 0x5c110250 +#define DDR_PHY_DQSDR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x095U)) +#define DDR_PHY_DQSDR1_0 0x5c010254 +#define DDR_PHY_DQSDR1_1 0x5c110254 +#define DDR_PHY_DQSDR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x096U)) +#define DDR_PHY_DQSDR2_0 0x5c010258 +#define DDR_PHY_DQSDR2_1 0x5c110258 +#define DDR_PHY_DCUAR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C0U)) +#define DDR_PHY_DCUAR_0 0x5c010300 +#define DDR_PHY_DCUAR_1 0x5c110300 +#define DDR_PHY_DCUDR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C1U)) +#define DDR_PHY_DCUDR_0 0x5c010304 +#define DDR_PHY_DCUDR_1 0x5c110304 +#define DDR_PHY_DCURR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C2U)) +#define DDR_PHY_DCURR_0 0x5c010308 +#define DDR_PHY_DCURR_1 0x5c110308 +#define DDR_PHY_DCULR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C3U)) +#define DDR_PHY_DCULR_0 0x5c01030c +#define DDR_PHY_DCULR_1 0x5c11030c +#define DDR_PHY_DCUGCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C4U)) +#define DDR_PHY_DCUGCR_0 0x5c010310 +#define DDR_PHY_DCUGCR_1 0x5c110310 +#define DDR_PHY_DCUTPR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C5U)) +#define DDR_PHY_DCUTPR_0 0x5c010314 +#define DDR_PHY_DCUTPR_1 0x5c110314 +#define DDR_PHY_DCUSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C6U)) +#define DDR_PHY_DCUSR0_0 0x5c010318 +#define DDR_PHY_DCUSR0_1 0x5c110318 +#define DDR_PHY_DCUSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x0C7U)) +#define DDR_PHY_DCUSR1_0 0x5c01031c +#define DDR_PHY_DCUSR1_1 0x5c11031c +#define DDR_PHY_BISTRR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x100U)) +#define DDR_PHY_BISTRR_0 0x5c010400 +#define DDR_PHY_BISTRR_1 0x5c110400 +#define DDR_PHY_BISTWCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x101U)) +#define DDR_PHY_BISTWCR_0 0x5c010404 +#define DDR_PHY_BISTWCR_1 0x5c110404 +#define DDR_PHY_BISTMSKR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x102U)) +#define DDR_PHY_BISTMSKR0_0 0x5c010408 +#define DDR_PHY_BISTMSKR0_1 0x5c110408 +#define DDR_PHY_BISTMSKR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x103U)) +#define DDR_PHY_BISTMSKR1_0 0x5c01040c +#define DDR_PHY_BISTMSKR1_1 0x5c11040c +#define DDR_PHY_BISTMSKR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x104U)) +#define DDR_PHY_BISTMSKR2_0 0x5c010410 +#define DDR_PHY_BISTMSKR2_1 0x5c110410 +#define DDR_PHY_BISTLSR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x105U)) +#define DDR_PHY_BISTLSR_0 0x5c010414 +#define DDR_PHY_BISTLSR_1 0x5c110414 +#define DDR_PHY_BISTAR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x106U)) +#define DDR_PHY_BISTAR0_0 0x5c010418 +#define DDR_PHY_BISTAR0_1 0x5c110418 +#define DDR_PHY_BISTAR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x107U)) +#define DDR_PHY_BISTAR1_0 0x5c01041c +#define DDR_PHY_BISTAR1_1 0x5c11041c +#define DDR_PHY_BISTAR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x108U)) +#define DDR_PHY_BISTAR2_0 0x5c010420 +#define DDR_PHY_BISTAR2_1 0x5c110420 +#define DDR_PHY_BISTAR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x109U)) +#define DDR_PHY_BISTAR3_0 0x5c010424 +#define DDR_PHY_BISTAR3_1 0x5c110424 +#define DDR_PHY_BISTAR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x10AU)) +#define DDR_PHY_BISTAR4_0 0x5c010428 +#define DDR_PHY_BISTAR4_1 0x5c110428 +#define DDR_PHY_BISTUDPR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x10BU)) +#define DDR_PHY_BISTUDPR_0 0x5c01042c +#define DDR_PHY_BISTUDPR_1 0x5c11042c +#define DDR_PHY_BISTGSR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x10CU)) +#define DDR_PHY_BISTGSR_0 0x5c010430 +#define DDR_PHY_BISTGSR_1 0x5c110430 +#define DDR_PHY_BISTWER0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x10DU)) +#define DDR_PHY_BISTWER0_0 0x5c010434 +#define DDR_PHY_BISTWER0_1 0x5c110434 +#define DDR_PHY_BISTWER1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x10EU)) +#define DDR_PHY_BISTWER1_0 0x5c010438 +#define DDR_PHY_BISTWER1_1 0x5c110438 +#define DDR_PHY_BISTBER0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x10FU)) +#define DDR_PHY_BISTBER0_0 0x5c01043c +#define DDR_PHY_BISTBER0_1 0x5c11043c +#define DDR_PHY_BISTBER1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x110U)) +#define DDR_PHY_BISTBER1_0 0x5c010440 +#define DDR_PHY_BISTBER1_1 0x5c110440 +#define DDR_PHY_BISTBER2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x111U)) +#define DDR_PHY_BISTBER2_0 0x5c010444 +#define DDR_PHY_BISTBER2_1 0x5c110444 +#define DDR_PHY_BISTBER3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x112U)) +#define DDR_PHY_BISTBER3_0 0x5c010448 +#define DDR_PHY_BISTBER3_1 0x5c110448 +#define DDR_PHY_BISTBER4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x113U)) +#define DDR_PHY_BISTBER4_0 0x5c01044c +#define DDR_PHY_BISTBER4_1 0x5c11044c +#define DDR_PHY_BISTWCSR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x114U)) +#define DDR_PHY_BISTWCSR_0 0x5c010450 +#define DDR_PHY_BISTWCSR_1 0x5c110450 +#define DDR_PHY_BISTFWR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x115U)) +#define DDR_PHY_BISTFWR0_0 0x5c010454 +#define DDR_PHY_BISTFWR0_1 0x5c110454 +#define DDR_PHY_BISTFWR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x116U)) +#define DDR_PHY_BISTFWR1_0 0x5c010458 +#define DDR_PHY_BISTFWR1_1 0x5c110458 +#define DDR_PHY_BISTFWR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x117U)) +#define DDR_PHY_BISTFWR2_0 0x5c01045c +#define DDR_PHY_BISTFWR2_1 0x5c11045c +#define DDR_PHY_BISTBER5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x118U)) +#define DDR_PHY_BISTBER5_0 0x5c010460 +#define DDR_PHY_BISTBER5_1 0x5c110460 +#define DDR_PHY_RANKIDR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x137U)) +#define DDR_PHY_RANKIDR_0 0x5c0104dc +#define DDR_PHY_RANKIDR_1 0x5c1104dc +#define DDR_PHY_RIOCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x138U)) +#define DDR_PHY_RIOCR0_0 0x5c0104e0 +#define DDR_PHY_RIOCR0_1 0x5c1104e0 +#define DDR_PHY_RIOCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x139U)) +#define DDR_PHY_RIOCR1_0 0x5c0104e4 +#define DDR_PHY_RIOCR1_1 0x5c1104e4 +#define DDR_PHY_RIOCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x13AU)) +#define DDR_PHY_RIOCR2_0 0x5c0104e8 +#define DDR_PHY_RIOCR2_1 0x5c1104e8 +#define DDR_PHY_RIOCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x13BU)) +#define DDR_PHY_RIOCR3_0 0x5c0104ec +#define DDR_PHY_RIOCR3_1 0x5c1104ec +#define DDR_PHY_RIOCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x13CU)) +#define DDR_PHY_RIOCR4_0 0x5c0104f0 +#define DDR_PHY_RIOCR4_1 0x5c1104f0 +#define DDR_PHY_RIOCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x13DU)) +#define DDR_PHY_RIOCR5_0 0x5c0104f4 +#define DDR_PHY_RIOCR5_1 0x5c1104f4 +#define DDR_PHY_ACIOCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x140U)) +#define DDR_PHY_ACIOCR0_0 0x5c010500 +#define DDR_PHY_ACIOCR0_1 0x5c110500 +#define DDR_PHY_ACIOCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x141U)) +#define DDR_PHY_ACIOCR1_0 0x5c010504 +#define DDR_PHY_ACIOCR1_1 0x5c110504 +#define DDR_PHY_ACIOCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x142U)) +#define DDR_PHY_ACIOCR2_0 0x5c010508 +#define DDR_PHY_ACIOCR2_1 0x5c110508 +#define DDR_PHY_ACIOCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x143U)) +#define DDR_PHY_ACIOCR3_0 0x5c01050c +#define DDR_PHY_ACIOCR3_1 0x5c11050c +#define DDR_PHY_ACIOCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x144U)) +#define DDR_PHY_ACIOCR4_0 0x5c010510 +#define DDR_PHY_ACIOCR4_1 0x5c110510 +#define DDR_PHY_ACIOCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x145U)) +#define DDR_PHY_ACIOCR5_0 0x5c010514 +#define DDR_PHY_ACIOCR5_1 0x5c110514 +#define DDR_PHY_IOVCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x148U)) +#define DDR_PHY_IOVCR0_0 0x5c010520 +#define DDR_PHY_IOVCR0_1 0x5c110520 +#define DDR_PHY_IOVCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x149U)) +#define DDR_PHY_IOVCR1_0 0x5c010524 +#define DDR_PHY_IOVCR1_1 0x5c110524 +#define DDR_PHY_VTCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x14AU)) +#define DDR_PHY_VTCR0_0 0x5c010528 +#define DDR_PHY_VTCR0_1 0x5c110528 +#define DDR_PHY_VTCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x14BU)) +#define DDR_PHY_VTCR1_0 0x5c01052c +#define DDR_PHY_VTCR1_1 0x5c11052c +#define DDR_PHY_ACBDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x150U)) +#define DDR_PHY_ACBDLR0_0 0x5c010540 +#define DDR_PHY_ACBDLR0_1 0x5c110540 +#define DDR_PHY_ACBDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x151U)) +#define DDR_PHY_ACBDLR1_0 0x5c010544 +#define DDR_PHY_ACBDLR1_1 0x5c110544 +#define DDR_PHY_ACBDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x152U)) +#define DDR_PHY_ACBDLR2_0 0x5c010548 +#define DDR_PHY_ACBDLR2_1 0x5c110548 +#define DDR_PHY_ACBDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x153U)) +#define DDR_PHY_ACBDLR3_0 0x5c01054c +#define DDR_PHY_ACBDLR3_1 0x5c11054c +#define DDR_PHY_ACBDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x154U)) +#define DDR_PHY_ACBDLR4_0 0x5c010550 +#define DDR_PHY_ACBDLR4_1 0x5c110550 +#define DDR_PHY_ACBDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x155U)) +#define DDR_PHY_ACBDLR5_0 0x5c010554 +#define DDR_PHY_ACBDLR5_1 0x5c110554 +#define DDR_PHY_ACBDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x156U)) +#define DDR_PHY_ACBDLR6_0 0x5c010558 +#define DDR_PHY_ACBDLR6_1 0x5c110558 +#define DDR_PHY_ACBDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x157U)) +#define DDR_PHY_ACBDLR7_0 0x5c01055c +#define DDR_PHY_ACBDLR7_1 0x5c11055c +#define DDR_PHY_ACBDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x158U)) +#define DDR_PHY_ACBDLR8_0 0x5c010560 +#define DDR_PHY_ACBDLR8_1 0x5c110560 +#define DDR_PHY_ACBDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x159U)) +#define DDR_PHY_ACBDLR9_0 0x5c010564 +#define DDR_PHY_ACBDLR9_1 0x5c110564 +#define DDR_PHY_ACBDLR10(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x15AU)) +#define DDR_PHY_ACBDLR10_0 0x5c010568 +#define DDR_PHY_ACBDLR10_1 0x5c110568 +#define DDR_PHY_ACBDLR11(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x15BU)) +#define DDR_PHY_ACBDLR11_0 0x5c01056c +#define DDR_PHY_ACBDLR11_1 0x5c11056c +#define DDR_PHY_ACBDLR12(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x15CU)) +#define DDR_PHY_ACBDLR12_0 0x5c010570 +#define DDR_PHY_ACBDLR12_1 0x5c110570 +#define DDR_PHY_ACBDLR13(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x15DU)) +#define DDR_PHY_ACBDLR13_0 0x5c010574 +#define DDR_PHY_ACBDLR13_1 0x5c110574 +#define DDR_PHY_ACBDLR14(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x15EU)) +#define DDR_PHY_ACBDLR14_0 0x5c010578 +#define DDR_PHY_ACBDLR14_1 0x5c110578 +#define DDR_PHY_ACBDLR15(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x15FU)) +#define DDR_PHY_ACBDLR15_0 0x5c01057c +#define DDR_PHY_ACBDLR15_1 0x5c11057c +#define DDR_PHY_ACBDLR16(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x160U)) +#define DDR_PHY_ACBDLR16_0 0x5c010580 +#define DDR_PHY_ACBDLR16_1 0x5c110580 +#define DDR_PHY_ACLCDLR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x161U)) +#define DDR_PHY_ACLCDLR_0 0x5c010584 +#define DDR_PHY_ACLCDLR_1 0x5c110584 +#define DDR_PHY_ACMDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x168U)) +#define DDR_PHY_ACMDLR0_0 0x5c0105a0 +#define DDR_PHY_ACMDLR0_1 0x5c1105a0 +#define DDR_PHY_ACMDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x169U)) +#define DDR_PHY_ACMDLR1_0 0x5c0105a4 +#define DDR_PHY_ACMDLR1_1 0x5c1105a4 +#define DDR_PHY_ZQCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A0U)) +#define DDR_PHY_ZQCR_0 0x5c010680 +#define DDR_PHY_ZQCR_1 0x5c110680 +#define DDR_PHY_ZQ0PR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A1U)) +#define DDR_PHY_ZQ0PR0_0 0x5c010684 +#define DDR_PHY_ZQ0PR0_1 0x5c110684 +#define DDR_PHY_ZQ0PR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A2U)) +#define DDR_PHY_ZQ0PR1_0 0x5c010688 +#define DDR_PHY_ZQ0PR1_1 0x5c110688 +#define DDR_PHY_ZQ0DR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A3U)) +#define DDR_PHY_ZQ0DR0_0 0x5c01068c +#define DDR_PHY_ZQ0DR0_1 0x5c11068c +#define DDR_PHY_ZQ0DR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A4U)) +#define DDR_PHY_ZQ0DR1_0 0x5c010690 +#define DDR_PHY_ZQ0DR1_1 0x5c110690 +#define DDR_PHY_ZQ0OR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A5U)) +#define DDR_PHY_ZQ0OR0_0 0x5c010694 +#define DDR_PHY_ZQ0OR0_1 0x5c110694 +#define DDR_PHY_ZQ0OR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A6U)) +#define DDR_PHY_ZQ0OR1_0 0x5c010698 +#define DDR_PHY_ZQ0OR1_1 0x5c110698 +#define DDR_PHY_ZQ0SR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A7U)) +#define DDR_PHY_ZQ0SR_0 0x5c01069c +#define DDR_PHY_ZQ0SR_1 0x5c11069c +#define DDR_PHY_ZQ1PR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1A9U)) +#define DDR_PHY_ZQ1PR0_0 0x5c0106a4 +#define DDR_PHY_ZQ1PR0_1 0x5c1106a4 +#define DDR_PHY_ZQ1PR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1AAU)) +#define DDR_PHY_ZQ1PR1_0 0x5c0106a8 +#define DDR_PHY_ZQ1PR1_1 0x5c1106a8 +#define DDR_PHY_ZQ1DR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1ABU)) +#define DDR_PHY_ZQ1DR0_0 0x5c0106ac +#define DDR_PHY_ZQ1DR0_1 0x5c1106ac +#define DDR_PHY_ZQ1DR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1ACU)) +#define DDR_PHY_ZQ1DR1_0 0x5c0106b0 +#define DDR_PHY_ZQ1DR1_1 0x5c1106b0 +#define DDR_PHY_ZQ1OR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1ADU)) +#define DDR_PHY_ZQ1OR0_0 0x5c0106b4 +#define DDR_PHY_ZQ1OR0_1 0x5c1106b4 +#define DDR_PHY_ZQ1OR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1AEU)) +#define DDR_PHY_ZQ1OR1_0 0x5c0106b8 +#define DDR_PHY_ZQ1OR1_1 0x5c1106b8 +#define DDR_PHY_ZQ1SR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1AFU)) +#define DDR_PHY_ZQ1SR_0 0x5c0106bc +#define DDR_PHY_ZQ1SR_1 0x5c1106bc +#define DDR_PHY_ZQ2PR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B1U)) +#define DDR_PHY_ZQ2PR0_0 0x5c0106c4 +#define DDR_PHY_ZQ2PR0_1 0x5c1106c4 +#define DDR_PHY_ZQ2PR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B2U)) +#define DDR_PHY_ZQ2PR1_0 0x5c0106c8 +#define DDR_PHY_ZQ2PR1_1 0x5c1106c8 +#define DDR_PHY_ZQ2DR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B3U)) +#define DDR_PHY_ZQ2DR0_0 0x5c0106cc +#define DDR_PHY_ZQ2DR0_1 0x5c1106cc +#define DDR_PHY_ZQ2DR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B4U)) +#define DDR_PHY_ZQ2DR1_0 0x5c0106d0 +#define DDR_PHY_ZQ2DR1_1 0x5c1106d0 +#define DDR_PHY_ZQ2OR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B5U)) +#define DDR_PHY_ZQ2OR0_0 0x5c0106d4 +#define DDR_PHY_ZQ2OR0_1 0x5c1106d4 +#define DDR_PHY_ZQ2OR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B6U)) +#define DDR_PHY_ZQ2OR1_0 0x5c0106d8 +#define DDR_PHY_ZQ2OR1_1 0x5c1106d8 +#define DDR_PHY_ZQ2SR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B7U)) +#define DDR_PHY_ZQ2SR_0 0x5c0106dc +#define DDR_PHY_ZQ2SR_1 0x5c1106dc +#define DDR_PHY_ZQ3PR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1B9U)) +#define DDR_PHY_ZQ3PR0_0 0x5c0106e4 +#define DDR_PHY_ZQ3PR0_1 0x5c1106e4 +#define DDR_PHY_ZQ3PR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1BAU)) +#define DDR_PHY_ZQ3PR1_0 0x5c0106e8 +#define DDR_PHY_ZQ3PR1_1 0x5c1106e8 +#define DDR_PHY_ZQ3DR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1BBU)) +#define DDR_PHY_ZQ3DR0_0 0x5c0106ec +#define DDR_PHY_ZQ3DR0_1 0x5c1106ec +#define DDR_PHY_ZQ3DR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1BCU)) +#define DDR_PHY_ZQ3DR1_0 0x5c0106f0 +#define DDR_PHY_ZQ3DR1_1 0x5c1106f0 +#define DDR_PHY_ZQ3OR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1BDU)) +#define DDR_PHY_ZQ3OR0_0 0x5c0106f4 +#define DDR_PHY_ZQ3OR0_1 0x5c1106f4 +#define DDR_PHY_ZQ3OR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1BEU)) +#define DDR_PHY_ZQ3OR1_0 0x5c0106f8 +#define DDR_PHY_ZQ3OR1_1 0x5c1106f8 +#define DDR_PHY_ZQ3SR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1BFU)) +#define DDR_PHY_ZQ3SR_0 0x5c0106fc +#define DDR_PHY_ZQ3SR_1 0x5c1106fc +#define DDR_PHY_DX0GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C0U)) +#define DDR_PHY_DX0GCR0_0 0x5c010700 +#define DDR_PHY_DX0GCR0_1 0x5c110700 +#define DDR_PHY_DX0GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C1U)) +#define DDR_PHY_DX0GCR1_0 0x5c010704 +#define DDR_PHY_DX0GCR1_1 0x5c110704 +#define DDR_PHY_DX0GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C2U)) +#define DDR_PHY_DX0GCR2_0 0x5c010708 +#define DDR_PHY_DX0GCR2_1 0x5c110708 +#define DDR_PHY_DX0GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C3U)) +#define DDR_PHY_DX0GCR3_0 0x5c01070c +#define DDR_PHY_DX0GCR3_1 0x5c11070c +#define DDR_PHY_DX0GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C4U)) +#define DDR_PHY_DX0GCR4_0 0x5c010710 +#define DDR_PHY_DX0GCR4_1 0x5c110710 +#define DDR_PHY_DX0GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C5U)) +#define DDR_PHY_DX0GCR5_0 0x5c010714 +#define DDR_PHY_DX0GCR5_1 0x5c110714 +#define DDR_PHY_DX0GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C6U)) +#define DDR_PHY_DX0GCR6_0 0x5c010718 +#define DDR_PHY_DX0GCR6_1 0x5c110718 +#define DDR_PHY_DX0GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C7U)) +#define DDR_PHY_DX0GCR7_0 0x5c01071c +#define DDR_PHY_DX0GCR7_1 0x5c11071c +#define DDR_PHY_DX0GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C8U)) +#define DDR_PHY_DX0GCR8_0 0x5c010720 +#define DDR_PHY_DX0GCR8_1 0x5c110720 +#define DDR_PHY_DX0GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1C9U)) +#define DDR_PHY_DX0GCR9_0 0x5c010724 +#define DDR_PHY_DX0GCR9_1 0x5c110724 +#define DDR_PHY_DX0DQMAP0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1CAU)) +#define DDR_PHY_DX0DQMAP0_0 0x5c010728 +#define DDR_PHY_DX0DQMAP0_1 0x5c110728 +#define DDR_PHY_DX0DQMAP1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1CBU)) +#define DDR_PHY_DX0DQMAP1_0 0x5c01072c +#define DDR_PHY_DX0DQMAP1_1 0x5c11072c +#define DDR_PHY_DX0BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D0U)) +#define DDR_PHY_DX0BDLR0_0 0x5c010740 +#define DDR_PHY_DX0BDLR0_1 0x5c110740 +#define DDR_PHY_DX0BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D1U)) +#define DDR_PHY_DX0BDLR1_0 0x5c010744 +#define DDR_PHY_DX0BDLR1_1 0x5c110744 +#define DDR_PHY_DX0BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D2U)) +#define DDR_PHY_DX0BDLR2_0 0x5c010748 +#define DDR_PHY_DX0BDLR2_1 0x5c110748 +#define DDR_PHY_DX0BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D4U)) +#define DDR_PHY_DX0BDLR3_0 0x5c010750 +#define DDR_PHY_DX0BDLR3_1 0x5c110750 +#define DDR_PHY_DX0BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D5U)) +#define DDR_PHY_DX0BDLR4_0 0x5c010754 +#define DDR_PHY_DX0BDLR4_1 0x5c110754 +#define DDR_PHY_DX0BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D6U)) +#define DDR_PHY_DX0BDLR5_0 0x5c010758 +#define DDR_PHY_DX0BDLR5_1 0x5c110758 +#define DDR_PHY_DX0BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D8U)) +#define DDR_PHY_DX0BDLR6_0 0x5c010760 +#define DDR_PHY_DX0BDLR6_1 0x5c110760 +#define DDR_PHY_DX0BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1D9U)) +#define DDR_PHY_DX0BDLR7_0 0x5c010764 +#define DDR_PHY_DX0BDLR7_1 0x5c110764 +#define DDR_PHY_DX0BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1DAU)) +#define DDR_PHY_DX0BDLR8_0 0x5c010768 +#define DDR_PHY_DX0BDLR8_1 0x5c110768 +#define DDR_PHY_DX0BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1DBU)) +#define DDR_PHY_DX0BDLR9_0 0x5c01076c +#define DDR_PHY_DX0BDLR9_1 0x5c11076c +#define DDR_PHY_DX0LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E0U)) +#define DDR_PHY_DX0LCDLR0_0 0x5c010780 +#define DDR_PHY_DX0LCDLR0_1 0x5c110780 +#define DDR_PHY_DX0LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E1U)) +#define DDR_PHY_DX0LCDLR1_0 0x5c010784 +#define DDR_PHY_DX0LCDLR1_1 0x5c110784 +#define DDR_PHY_DX0LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E2U)) +#define DDR_PHY_DX0LCDLR2_0 0x5c010788 +#define DDR_PHY_DX0LCDLR2_1 0x5c110788 +#define DDR_PHY_DX0LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E3U)) +#define DDR_PHY_DX0LCDLR3_0 0x5c01078c +#define DDR_PHY_DX0LCDLR3_1 0x5c11078c +#define DDR_PHY_DX0LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E4U)) +#define DDR_PHY_DX0LCDLR4_0 0x5c010790 +#define DDR_PHY_DX0LCDLR4_1 0x5c110790 +#define DDR_PHY_DX0LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E5U)) +#define DDR_PHY_DX0LCDLR5_0 0x5c010794 +#define DDR_PHY_DX0LCDLR5_1 0x5c110794 +#define DDR_PHY_DX0MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E8U)) +#define DDR_PHY_DX0MDLR0_0 0x5c0107a0 +#define DDR_PHY_DX0MDLR0_1 0x5c1107a0 +#define DDR_PHY_DX0MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1E9U)) +#define DDR_PHY_DX0MDLR1_0 0x5c0107a4 +#define DDR_PHY_DX0MDLR1_1 0x5c1107a4 +#define DDR_PHY_DX0GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F0U)) +#define DDR_PHY_DX0GTR0_0 0x5c0107c0 +#define DDR_PHY_DX0GTR0_1 0x5c1107c0 +#define DDR_PHY_DX0RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F4U)) +#define DDR_PHY_DX0RSR0_0 0x5c0107d0 +#define DDR_PHY_DX0RSR0_1 0x5c1107d0 +#define DDR_PHY_DX0RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F5U)) +#define DDR_PHY_DX0RSR1_0 0x5c0107d4 +#define DDR_PHY_DX0RSR1_1 0x5c1107d4 +#define DDR_PHY_DX0RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F6U)) +#define DDR_PHY_DX0RSR2_0 0x5c0107d8 +#define DDR_PHY_DX0RSR2_1 0x5c1107d8 +#define DDR_PHY_DX0RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F7U)) +#define DDR_PHY_DX0RSR3_0 0x5c0107dc +#define DDR_PHY_DX0RSR3_1 0x5c1107dc +#define DDR_PHY_DX0GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F8U)) +#define DDR_PHY_DX0GSR0_0 0x5c0107e0 +#define DDR_PHY_DX0GSR0_1 0x5c1107e0 +#define DDR_PHY_DX0GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1F9U)) +#define DDR_PHY_DX0GSR1_0 0x5c0107e4 +#define DDR_PHY_DX0GSR1_1 0x5c1107e4 +#define DDR_PHY_DX0GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1FAU)) +#define DDR_PHY_DX0GSR2_0 0x5c0107e8 +#define DDR_PHY_DX0GSR2_1 0x5c1107e8 +#define DDR_PHY_DX0GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1FBU)) +#define DDR_PHY_DX0GSR3_0 0x5c0107ec +#define DDR_PHY_DX0GSR3_1 0x5c1107ec +#define DDR_PHY_DX0GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1FCU)) +#define DDR_PHY_DX0GSR4_0 0x5c0107f0 +#define DDR_PHY_DX0GSR4_1 0x5c1107f0 +#define DDR_PHY_DX0GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1FDU)) +#define DDR_PHY_DX0GSR5_0 0x5c0107f4 +#define DDR_PHY_DX0GSR5_1 0x5c1107f4 +#define DDR_PHY_DX0GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x1FEU)) +#define DDR_PHY_DX0GSR6_0 0x5c0107f8 +#define DDR_PHY_DX0GSR6_1 0x5c1107f8 +#define DDR_PHY_DX1GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x200U)) +#define DDR_PHY_DX1GCR0_0 0x5c010800 +#define DDR_PHY_DX1GCR0_1 0x5c110800 +#define DDR_PHY_DX1GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x201U)) +#define DDR_PHY_DX1GCR1_0 0x5c010804 +#define DDR_PHY_DX1GCR1_1 0x5c110804 +#define DDR_PHY_DX1GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x202U)) +#define DDR_PHY_DX1GCR2_0 0x5c010808 +#define DDR_PHY_DX1GCR2_1 0x5c110808 +#define DDR_PHY_DX1GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x203U)) +#define DDR_PHY_DX1GCR3_0 0x5c01080c +#define DDR_PHY_DX1GCR3_1 0x5c11080c +#define DDR_PHY_DX1GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x204U)) +#define DDR_PHY_DX1GCR4_0 0x5c010810 +#define DDR_PHY_DX1GCR4_1 0x5c110810 +#define DDR_PHY_DX1GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x205U)) +#define DDR_PHY_DX1GCR5_0 0x5c010814 +#define DDR_PHY_DX1GCR5_1 0x5c110814 +#define DDR_PHY_DX1GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x206U)) +#define DDR_PHY_DX1GCR6_0 0x5c010818 +#define DDR_PHY_DX1GCR6_1 0x5c110818 +#define DDR_PHY_DX1GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x207U)) +#define DDR_PHY_DX1GCR7_0 0x5c01081c +#define DDR_PHY_DX1GCR7_1 0x5c11081c +#define DDR_PHY_DX1GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x208U)) +#define DDR_PHY_DX1GCR8_0 0x5c010820 +#define DDR_PHY_DX1GCR8_1 0x5c110820 +#define DDR_PHY_DX1GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x209U)) +#define DDR_PHY_DX1GCR9_0 0x5c010824 +#define DDR_PHY_DX1GCR9_1 0x5c110824 +#define DDR_PHY_DX1DQMAP0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x20AU)) +#define DDR_PHY_DX1DQMAP0_0 0x5c010828 +#define DDR_PHY_DX1DQMAP0_1 0x5c110828 +#define DDR_PHY_DX1DQMAP1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x20BU)) +#define DDR_PHY_DX1DQMAP1_0 0x5c01082c +#define DDR_PHY_DX1DQMAP1_1 0x5c11082c +#define DDR_PHY_DX1BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x210U)) +#define DDR_PHY_DX1BDLR0_0 0x5c010840 +#define DDR_PHY_DX1BDLR0_1 0x5c110840 +#define DDR_PHY_DX1BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x211U)) +#define DDR_PHY_DX1BDLR1_0 0x5c010844 +#define DDR_PHY_DX1BDLR1_1 0x5c110844 +#define DDR_PHY_DX1BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x212U)) +#define DDR_PHY_DX1BDLR2_0 0x5c010848 +#define DDR_PHY_DX1BDLR2_1 0x5c110848 +#define DDR_PHY_DX1BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x214U)) +#define DDR_PHY_DX1BDLR3_0 0x5c010850 +#define DDR_PHY_DX1BDLR3_1 0x5c110850 +#define DDR_PHY_DX1BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x215U)) +#define DDR_PHY_DX1BDLR4_0 0x5c010854 +#define DDR_PHY_DX1BDLR4_1 0x5c110854 +#define DDR_PHY_DX1BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x216U)) +#define DDR_PHY_DX1BDLR5_0 0x5c010858 +#define DDR_PHY_DX1BDLR5_1 0x5c110858 +#define DDR_PHY_DX1BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x218U)) +#define DDR_PHY_DX1BDLR6_0 0x5c010860 +#define DDR_PHY_DX1BDLR6_1 0x5c110860 +#define DDR_PHY_DX1BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x219U)) +#define DDR_PHY_DX1BDLR7_0 0x5c010864 +#define DDR_PHY_DX1BDLR7_1 0x5c110864 +#define DDR_PHY_DX1BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x21AU)) +#define DDR_PHY_DX1BDLR8_0 0x5c010868 +#define DDR_PHY_DX1BDLR8_1 0x5c110868 +#define DDR_PHY_DX1BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x21BU)) +#define DDR_PHY_DX1BDLR9_0 0x5c01086c +#define DDR_PHY_DX1BDLR9_1 0x5c11086c +#define DDR_PHY_DX1LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x220U)) +#define DDR_PHY_DX1LCDLR0_0 0x5c010880 +#define DDR_PHY_DX1LCDLR0_1 0x5c110880 +#define DDR_PHY_DX1LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x221U)) +#define DDR_PHY_DX1LCDLR1_0 0x5c010884 +#define DDR_PHY_DX1LCDLR1_1 0x5c110884 +#define DDR_PHY_DX1LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x222U)) +#define DDR_PHY_DX1LCDLR2_0 0x5c010888 +#define DDR_PHY_DX1LCDLR2_1 0x5c110888 +#define DDR_PHY_DX1LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x223U)) +#define DDR_PHY_DX1LCDLR3_0 0x5c01088c +#define DDR_PHY_DX1LCDLR3_1 0x5c11088c +#define DDR_PHY_DX1LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x224U)) +#define DDR_PHY_DX1LCDLR4_0 0x5c010890 +#define DDR_PHY_DX1LCDLR4_1 0x5c110890 +#define DDR_PHY_DX1LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x225U)) +#define DDR_PHY_DX1LCDLR5_0 0x5c010894 +#define DDR_PHY_DX1LCDLR5_1 0x5c110894 +#define DDR_PHY_DX1MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x228U)) +#define DDR_PHY_DX1MDLR0_0 0x5c0108a0 +#define DDR_PHY_DX1MDLR0_1 0x5c1108a0 +#define DDR_PHY_DX1MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x229U)) +#define DDR_PHY_DX1MDLR1_0 0x5c0108a4 +#define DDR_PHY_DX1MDLR1_1 0x5c1108a4 +#define DDR_PHY_DX1GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x230U)) +#define DDR_PHY_DX1GTR0_0 0x5c0108c0 +#define DDR_PHY_DX1GTR0_1 0x5c1108c0 +#define DDR_PHY_DX1RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x234U)) +#define DDR_PHY_DX1RSR0_0 0x5c0108d0 +#define DDR_PHY_DX1RSR0_1 0x5c1108d0 +#define DDR_PHY_DX1RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x235U)) +#define DDR_PHY_DX1RSR1_0 0x5c0108d4 +#define DDR_PHY_DX1RSR1_1 0x5c1108d4 +#define DDR_PHY_DX1RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x236U)) +#define DDR_PHY_DX1RSR2_0 0x5c0108d8 +#define DDR_PHY_DX1RSR2_1 0x5c1108d8 +#define DDR_PHY_DX1RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x237U)) +#define DDR_PHY_DX1RSR3_0 0x5c0108dc +#define DDR_PHY_DX1RSR3_1 0x5c1108dc +#define DDR_PHY_DX1GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x238U)) +#define DDR_PHY_DX1GSR0_0 0x5c0108e0 +#define DDR_PHY_DX1GSR0_1 0x5c1108e0 +#define DDR_PHY_DX1GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x239U)) +#define DDR_PHY_DX1GSR1_0 0x5c0108e4 +#define DDR_PHY_DX1GSR1_1 0x5c1108e4 +#define DDR_PHY_DX1GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x23AU)) +#define DDR_PHY_DX1GSR2_0 0x5c0108e8 +#define DDR_PHY_DX1GSR2_1 0x5c1108e8 +#define DDR_PHY_DX1GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x23BU)) +#define DDR_PHY_DX1GSR3_0 0x5c0108ec +#define DDR_PHY_DX1GSR3_1 0x5c1108ec +#define DDR_PHY_DX1GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x23CU)) +#define DDR_PHY_DX1GSR4_0 0x5c0108f0 +#define DDR_PHY_DX1GSR4_1 0x5c1108f0 +#define DDR_PHY_DX1GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x23DU)) +#define DDR_PHY_DX1GSR5_0 0x5c0108f4 +#define DDR_PHY_DX1GSR5_1 0x5c1108f4 +#define DDR_PHY_DX1GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x23EU)) +#define DDR_PHY_DX1GSR6_0 0x5c0108f8 +#define DDR_PHY_DX1GSR6_1 0x5c1108f8 +#define DDR_PHY_DX2GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x240U)) +#define DDR_PHY_DX2GCR0_0 0x5c010900 +#define DDR_PHY_DX2GCR0_1 0x5c110900 +#define DDR_PHY_DX2GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x241U)) +#define DDR_PHY_DX2GCR1_0 0x5c010904 +#define DDR_PHY_DX2GCR1_1 0x5c110904 +#define DDR_PHY_DX2GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x242U)) +#define DDR_PHY_DX2GCR2_0 0x5c010908 +#define DDR_PHY_DX2GCR2_1 0x5c110908 +#define DDR_PHY_DX2GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x243U)) +#define DDR_PHY_DX2GCR3_0 0x5c01090c +#define DDR_PHY_DX2GCR3_1 0x5c11090c +#define DDR_PHY_DX2GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x244U)) +#define DDR_PHY_DX2GCR4_0 0x5c010910 +#define DDR_PHY_DX2GCR4_1 0x5c110910 +#define DDR_PHY_DX2GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x245U)) +#define DDR_PHY_DX2GCR5_0 0x5c010914 +#define DDR_PHY_DX2GCR5_1 0x5c110914 +#define DDR_PHY_DX2GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x246U)) +#define DDR_PHY_DX2GCR6_0 0x5c010918 +#define DDR_PHY_DX2GCR6_1 0x5c110918 +#define DDR_PHY_DX2GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x247U)) +#define DDR_PHY_DX2GCR7_0 0x5c01091c +#define DDR_PHY_DX2GCR7_1 0x5c11091c +#define DDR_PHY_DX2GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x248U)) +#define DDR_PHY_DX2GCR8_0 0x5c010920 +#define DDR_PHY_DX2GCR8_1 0x5c110920 +#define DDR_PHY_DX2GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x249U)) +#define DDR_PHY_DX2GCR9_0 0x5c010924 +#define DDR_PHY_DX2GCR9_1 0x5c110924 +#define DDR_PHY_DX2DQMAP0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x24AU)) +#define DDR_PHY_DX2DQMAP0_0 0x5c010928 +#define DDR_PHY_DX2DQMAP0_1 0x5c110928 +#define DDR_PHY_DX2DQMAP1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x24BU)) +#define DDR_PHY_DX2DQMAP1_0 0x5c01092c +#define DDR_PHY_DX2DQMAP1_1 0x5c11092c +#define DDR_PHY_DX2BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x250U)) +#define DDR_PHY_DX2BDLR0_0 0x5c010940 +#define DDR_PHY_DX2BDLR0_1 0x5c110940 +#define DDR_PHY_DX2BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x251U)) +#define DDR_PHY_DX2BDLR1_0 0x5c010944 +#define DDR_PHY_DX2BDLR1_1 0x5c110944 +#define DDR_PHY_DX2BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x252U)) +#define DDR_PHY_DX2BDLR2_0 0x5c010948 +#define DDR_PHY_DX2BDLR2_1 0x5c110948 +#define DDR_PHY_DX2BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x254U)) +#define DDR_PHY_DX2BDLR3_0 0x5c010950 +#define DDR_PHY_DX2BDLR3_1 0x5c110950 +#define DDR_PHY_DX2BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x255U)) +#define DDR_PHY_DX2BDLR4_0 0x5c010954 +#define DDR_PHY_DX2BDLR4_1 0x5c110954 +#define DDR_PHY_DX2BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x256U)) +#define DDR_PHY_DX2BDLR5_0 0x5c010958 +#define DDR_PHY_DX2BDLR5_1 0x5c110958 +#define DDR_PHY_DX2BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x258U)) +#define DDR_PHY_DX2BDLR6_0 0x5c010960 +#define DDR_PHY_DX2BDLR6_1 0x5c110960 +#define DDR_PHY_DX2BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x259U)) +#define DDR_PHY_DX2BDLR7_0 0x5c010964 +#define DDR_PHY_DX2BDLR7_1 0x5c110964 +#define DDR_PHY_DX2BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x25AU)) +#define DDR_PHY_DX2BDLR8_0 0x5c010968 +#define DDR_PHY_DX2BDLR8_1 0x5c110968 +#define DDR_PHY_DX2BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x25BU)) +#define DDR_PHY_DX2BDLR9_0 0x5c01096c +#define DDR_PHY_DX2BDLR9_1 0x5c11096c +#define DDR_PHY_DX2LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x260U)) +#define DDR_PHY_DX2LCDLR0_0 0x5c010980 +#define DDR_PHY_DX2LCDLR0_1 0x5c110980 +#define DDR_PHY_DX2LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x261U)) +#define DDR_PHY_DX2LCDLR1_0 0x5c010984 +#define DDR_PHY_DX2LCDLR1_1 0x5c110984 +#define DDR_PHY_DX2LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x262U)) +#define DDR_PHY_DX2LCDLR2_0 0x5c010988 +#define DDR_PHY_DX2LCDLR2_1 0x5c110988 +#define DDR_PHY_DX2LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x263U)) +#define DDR_PHY_DX2LCDLR3_0 0x5c01098c +#define DDR_PHY_DX2LCDLR3_1 0x5c11098c +#define DDR_PHY_DX2LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x264U)) +#define DDR_PHY_DX2LCDLR4_0 0x5c010990 +#define DDR_PHY_DX2LCDLR4_1 0x5c110990 +#define DDR_PHY_DX2LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x265U)) +#define DDR_PHY_DX2LCDLR5_0 0x5c010994 +#define DDR_PHY_DX2LCDLR5_1 0x5c110994 +#define DDR_PHY_DX2MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x268U)) +#define DDR_PHY_DX2MDLR0_0 0x5c0109a0 +#define DDR_PHY_DX2MDLR0_1 0x5c1109a0 +#define DDR_PHY_DX2MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x269U)) +#define DDR_PHY_DX2MDLR1_0 0x5c0109a4 +#define DDR_PHY_DX2MDLR1_1 0x5c1109a4 +#define DDR_PHY_DX2GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x270U)) +#define DDR_PHY_DX2GTR0_0 0x5c0109c0 +#define DDR_PHY_DX2GTR0_1 0x5c1109c0 +#define DDR_PHY_DX2RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x274U)) +#define DDR_PHY_DX2RSR0_0 0x5c0109d0 +#define DDR_PHY_DX2RSR0_1 0x5c1109d0 +#define DDR_PHY_DX2RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x275U)) +#define DDR_PHY_DX2RSR1_0 0x5c0109d4 +#define DDR_PHY_DX2RSR1_1 0x5c1109d4 +#define DDR_PHY_DX2RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x276U)) +#define DDR_PHY_DX2RSR2_0 0x5c0109d8 +#define DDR_PHY_DX2RSR2_1 0x5c1109d8 +#define DDR_PHY_DX2RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x277U)) +#define DDR_PHY_DX2RSR3_0 0x5c0109dc +#define DDR_PHY_DX2RSR3_1 0x5c1109dc +#define DDR_PHY_DX2GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x278U)) +#define DDR_PHY_DX2GSR0_0 0x5c0109e0 +#define DDR_PHY_DX2GSR0_1 0x5c1109e0 +#define DDR_PHY_DX2GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x279U)) +#define DDR_PHY_DX2GSR1_0 0x5c0109e4 +#define DDR_PHY_DX2GSR1_1 0x5c1109e4 +#define DDR_PHY_DX2GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x27AU)) +#define DDR_PHY_DX2GSR2_0 0x5c0109e8 +#define DDR_PHY_DX2GSR2_1 0x5c1109e8 +#define DDR_PHY_DX2GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x27BU)) +#define DDR_PHY_DX2GSR3_0 0x5c0109ec +#define DDR_PHY_DX2GSR3_1 0x5c1109ec +#define DDR_PHY_DX2GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x27CU)) +#define DDR_PHY_DX2GSR4_0 0x5c0109f0 +#define DDR_PHY_DX2GSR4_1 0x5c1109f0 +#define DDR_PHY_DX2GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x27DU)) +#define DDR_PHY_DX2GSR5_0 0x5c0109f4 +#define DDR_PHY_DX2GSR5_1 0x5c1109f4 +#define DDR_PHY_DX2GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x27EU)) +#define DDR_PHY_DX2GSR6_0 0x5c0109f8 +#define DDR_PHY_DX2GSR6_1 0x5c1109f8 +#define DDR_PHY_DX3GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x280U)) +#define DDR_PHY_DX3GCR0_0 0x5c010a00 +#define DDR_PHY_DX3GCR0_1 0x5c110a00 +#define DDR_PHY_DX3GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x281U)) +#define DDR_PHY_DX3GCR1_0 0x5c010a04 +#define DDR_PHY_DX3GCR1_1 0x5c110a04 +#define DDR_PHY_DX3GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x282U)) +#define DDR_PHY_DX3GCR2_0 0x5c010a08 +#define DDR_PHY_DX3GCR2_1 0x5c110a08 +#define DDR_PHY_DX3GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x283U)) +#define DDR_PHY_DX3GCR3_0 0x5c010a0c +#define DDR_PHY_DX3GCR3_1 0x5c110a0c +#define DDR_PHY_DX3GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x284U)) +#define DDR_PHY_DX3GCR4_0 0x5c010a10 +#define DDR_PHY_DX3GCR4_1 0x5c110a10 +#define DDR_PHY_DX3GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x285U)) +#define DDR_PHY_DX3GCR5_0 0x5c010a14 +#define DDR_PHY_DX3GCR5_1 0x5c110a14 +#define DDR_PHY_DX3GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x286U)) +#define DDR_PHY_DX3GCR6_0 0x5c010a18 +#define DDR_PHY_DX3GCR6_1 0x5c110a18 +#define DDR_PHY_DX3GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x287U)) +#define DDR_PHY_DX3GCR7_0 0x5c010a1c +#define DDR_PHY_DX3GCR7_1 0x5c110a1c +#define DDR_PHY_DX3GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x288U)) +#define DDR_PHY_DX3GCR8_0 0x5c010a20 +#define DDR_PHY_DX3GCR8_1 0x5c110a20 +#define DDR_PHY_DX3GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x289U)) +#define DDR_PHY_DX3GCR9_0 0x5c010a24 +#define DDR_PHY_DX3GCR9_1 0x5c110a24 +#define DDR_PHY_DX3DQMAP0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x28AU)) +#define DDR_PHY_DX3DQMAP0_0 0x5c010a28 +#define DDR_PHY_DX3DQMAP0_1 0x5c110a28 +#define DDR_PHY_DX3DQMAP1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x28BU)) +#define DDR_PHY_DX3DQMAP1_0 0x5c010a2c +#define DDR_PHY_DX3DQMAP1_1 0x5c110a2c +#define DDR_PHY_DX3BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x290U)) +#define DDR_PHY_DX3BDLR0_0 0x5c010a40 +#define DDR_PHY_DX3BDLR0_1 0x5c110a40 +#define DDR_PHY_DX3BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x291U)) +#define DDR_PHY_DX3BDLR1_0 0x5c010a44 +#define DDR_PHY_DX3BDLR1_1 0x5c110a44 +#define DDR_PHY_DX3BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x292U)) +#define DDR_PHY_DX3BDLR2_0 0x5c010a48 +#define DDR_PHY_DX3BDLR2_1 0x5c110a48 +#define DDR_PHY_DX3BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x294U)) +#define DDR_PHY_DX3BDLR3_0 0x5c010a50 +#define DDR_PHY_DX3BDLR3_1 0x5c110a50 +#define DDR_PHY_DX3BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x295U)) +#define DDR_PHY_DX3BDLR4_0 0x5c010a54 +#define DDR_PHY_DX3BDLR4_1 0x5c110a54 +#define DDR_PHY_DX3BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x296U)) +#define DDR_PHY_DX3BDLR5_0 0x5c010a58 +#define DDR_PHY_DX3BDLR5_1 0x5c110a58 +#define DDR_PHY_DX3BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x298U)) +#define DDR_PHY_DX3BDLR6_0 0x5c010a60 +#define DDR_PHY_DX3BDLR6_1 0x5c110a60 +#define DDR_PHY_DX3BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x299U)) +#define DDR_PHY_DX3BDLR7_0 0x5c010a64 +#define DDR_PHY_DX3BDLR7_1 0x5c110a64 +#define DDR_PHY_DX3BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x29AU)) +#define DDR_PHY_DX3BDLR8_0 0x5c010a68 +#define DDR_PHY_DX3BDLR8_1 0x5c110a68 +#define DDR_PHY_DX3BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x29BU)) +#define DDR_PHY_DX3BDLR9_0 0x5c010a6c +#define DDR_PHY_DX3BDLR9_1 0x5c110a6c +#define DDR_PHY_DX3LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A0U)) +#define DDR_PHY_DX3LCDLR0_0 0x5c010a80 +#define DDR_PHY_DX3LCDLR0_1 0x5c110a80 +#define DDR_PHY_DX3LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A1U)) +#define DDR_PHY_DX3LCDLR1_0 0x5c010a84 +#define DDR_PHY_DX3LCDLR1_1 0x5c110a84 +#define DDR_PHY_DX3LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A2U)) +#define DDR_PHY_DX3LCDLR2_0 0x5c010a88 +#define DDR_PHY_DX3LCDLR2_1 0x5c110a88 +#define DDR_PHY_DX3LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A3U)) +#define DDR_PHY_DX3LCDLR3_0 0x5c010a8c +#define DDR_PHY_DX3LCDLR3_1 0x5c110a8c +#define DDR_PHY_DX3LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A4U)) +#define DDR_PHY_DX3LCDLR4_0 0x5c010a90 +#define DDR_PHY_DX3LCDLR4_1 0x5c110a90 +#define DDR_PHY_DX3LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A5U)) +#define DDR_PHY_DX3LCDLR5_0 0x5c010a94 +#define DDR_PHY_DX3LCDLR5_1 0x5c110a94 +#define DDR_PHY_DX3MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A8U)) +#define DDR_PHY_DX3MDLR0_0 0x5c010aa0 +#define DDR_PHY_DX3MDLR0_1 0x5c110aa0 +#define DDR_PHY_DX3MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2A9U)) +#define DDR_PHY_DX3MDLR1_0 0x5c010aa4 +#define DDR_PHY_DX3MDLR1_1 0x5c110aa4 +#define DDR_PHY_DX3GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B0U)) +#define DDR_PHY_DX3GTR0_0 0x5c010ac0 +#define DDR_PHY_DX3GTR0_1 0x5c110ac0 +#define DDR_PHY_DX3RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B4U)) +#define DDR_PHY_DX3RSR0_0 0x5c010ad0 +#define DDR_PHY_DX3RSR0_1 0x5c110ad0 +#define DDR_PHY_DX3RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B5U)) +#define DDR_PHY_DX3RSR1_0 0x5c010ad4 +#define DDR_PHY_DX3RSR1_1 0x5c110ad4 +#define DDR_PHY_DX3RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B6U)) +#define DDR_PHY_DX3RSR2_0 0x5c010ad8 +#define DDR_PHY_DX3RSR2_1 0x5c110ad8 +#define DDR_PHY_DX3RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B7U)) +#define DDR_PHY_DX3RSR3_0 0x5c010adc +#define DDR_PHY_DX3RSR3_1 0x5c110adc +#define DDR_PHY_DX3GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B8U)) +#define DDR_PHY_DX3GSR0_0 0x5c010ae0 +#define DDR_PHY_DX3GSR0_1 0x5c110ae0 +#define DDR_PHY_DX3GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2B9U)) +#define DDR_PHY_DX3GSR1_0 0x5c010ae4 +#define DDR_PHY_DX3GSR1_1 0x5c110ae4 +#define DDR_PHY_DX3GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2BAU)) +#define DDR_PHY_DX3GSR2_0 0x5c010ae8 +#define DDR_PHY_DX3GSR2_1 0x5c110ae8 +#define DDR_PHY_DX3GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2BBU)) +#define DDR_PHY_DX3GSR3_0 0x5c010aec +#define DDR_PHY_DX3GSR3_1 0x5c110aec +#define DDR_PHY_DX3GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2BCU)) +#define DDR_PHY_DX3GSR4_0 0x5c010af0 +#define DDR_PHY_DX3GSR4_1 0x5c110af0 +#define DDR_PHY_DX3GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2BDU)) +#define DDR_PHY_DX3GSR5_0 0x5c010af4 +#define DDR_PHY_DX3GSR5_1 0x5c110af4 +#define DDR_PHY_DX3GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2BEU)) +#define DDR_PHY_DX3GSR6_0 0x5c010af8 +#define DDR_PHY_DX3GSR6_1 0x5c110af8 +#define DDR_PHY_DX4GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C0U)) +#define DDR_PHY_DX4GCR0_0 0x5c010b00 +#define DDR_PHY_DX4GCR0_1 0x5c110b00 +#define DDR_PHY_DX4GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C1U)) +#define DDR_PHY_DX4GCR1_0 0x5c010b04 +#define DDR_PHY_DX4GCR1_1 0x5c110b04 +#define DDR_PHY_DX4GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C2U)) +#define DDR_PHY_DX4GCR2_0 0x5c010b08 +#define DDR_PHY_DX4GCR2_1 0x5c110b08 +#define DDR_PHY_DX4GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C3U)) +#define DDR_PHY_DX4GCR3_0 0x5c010b0c +#define DDR_PHY_DX4GCR3_1 0x5c110b0c +#define DDR_PHY_DX4GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C4U)) +#define DDR_PHY_DX4GCR4_0 0x5c010b10 +#define DDR_PHY_DX4GCR4_1 0x5c110b10 +#define DDR_PHY_DX4GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C5U)) +#define DDR_PHY_DX4GCR5_0 0x5c010b14 +#define DDR_PHY_DX4GCR5_1 0x5c110b14 +#define DDR_PHY_DX4GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C6U)) +#define DDR_PHY_DX4GCR6_0 0x5c010b18 +#define DDR_PHY_DX4GCR6_1 0x5c110b18 +#define DDR_PHY_DX4GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C7U)) +#define DDR_PHY_DX4GCR7_0 0x5c010b1c +#define DDR_PHY_DX4GCR7_1 0x5c110b1c +#define DDR_PHY_DX4GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C8U)) +#define DDR_PHY_DX4GCR8_0 0x5c010b20 +#define DDR_PHY_DX4GCR8_1 0x5c110b20 +#define DDR_PHY_DX4GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2C9U)) +#define DDR_PHY_DX4GCR9_0 0x5c010b24 +#define DDR_PHY_DX4GCR9_1 0x5c110b24 +#define DDR_PHY_DX4DQMAP0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2CAU)) +#define DDR_PHY_DX4DQMAP0_0 0x5c010b28 +#define DDR_PHY_DX4DQMAP0_1 0x5c110b28 +#define DDR_PHY_DX4DQMAP1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2CBU)) +#define DDR_PHY_DX4DQMAP1_0 0x5c010b2c +#define DDR_PHY_DX4DQMAP1_1 0x5c110b2c +#define DDR_PHY_DX4BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D0U)) +#define DDR_PHY_DX4BDLR0_0 0x5c010b40 +#define DDR_PHY_DX4BDLR0_1 0x5c110b40 +#define DDR_PHY_DX4BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D1U)) +#define DDR_PHY_DX4BDLR1_0 0x5c010b44 +#define DDR_PHY_DX4BDLR1_1 0x5c110b44 +#define DDR_PHY_DX4BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D2U)) +#define DDR_PHY_DX4BDLR2_0 0x5c010b48 +#define DDR_PHY_DX4BDLR2_1 0x5c110b48 +#define DDR_PHY_DX4BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D4U)) +#define DDR_PHY_DX4BDLR3_0 0x5c010b50 +#define DDR_PHY_DX4BDLR3_1 0x5c110b50 +#define DDR_PHY_DX4BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D5U)) +#define DDR_PHY_DX4BDLR4_0 0x5c010b54 +#define DDR_PHY_DX4BDLR4_1 0x5c110b54 +#define DDR_PHY_DX4BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D6U)) +#define DDR_PHY_DX4BDLR5_0 0x5c010b58 +#define DDR_PHY_DX4BDLR5_1 0x5c110b58 +#define DDR_PHY_DX4BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D8U)) +#define DDR_PHY_DX4BDLR6_0 0x5c010b60 +#define DDR_PHY_DX4BDLR6_1 0x5c110b60 +#define DDR_PHY_DX4BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2D9U)) +#define DDR_PHY_DX4BDLR7_0 0x5c010b64 +#define DDR_PHY_DX4BDLR7_1 0x5c110b64 +#define DDR_PHY_DX4BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2DAU)) +#define DDR_PHY_DX4BDLR8_0 0x5c010b68 +#define DDR_PHY_DX4BDLR8_1 0x5c110b68 +#define DDR_PHY_DX4BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2DBU)) +#define DDR_PHY_DX4BDLR9_0 0x5c010b6c +#define DDR_PHY_DX4BDLR9_1 0x5c110b6c +#define DDR_PHY_DX4LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E0U)) +#define DDR_PHY_DX4LCDLR0_0 0x5c010b80 +#define DDR_PHY_DX4LCDLR0_1 0x5c110b80 +#define DDR_PHY_DX4LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E1U)) +#define DDR_PHY_DX4LCDLR1_0 0x5c010b84 +#define DDR_PHY_DX4LCDLR1_1 0x5c110b84 +#define DDR_PHY_DX4LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E2U)) +#define DDR_PHY_DX4LCDLR2_0 0x5c010b88 +#define DDR_PHY_DX4LCDLR2_1 0x5c110b88 +#define DDR_PHY_DX4LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E3U)) +#define DDR_PHY_DX4LCDLR3_0 0x5c010b8c +#define DDR_PHY_DX4LCDLR3_1 0x5c110b8c +#define DDR_PHY_DX4LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E4U)) +#define DDR_PHY_DX4LCDLR4_0 0x5c010b90 +#define DDR_PHY_DX4LCDLR4_1 0x5c110b90 +#define DDR_PHY_DX4LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E5U)) +#define DDR_PHY_DX4LCDLR5_0 0x5c010b94 +#define DDR_PHY_DX4LCDLR5_1 0x5c110b94 +#define DDR_PHY_DX4MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E8U)) +#define DDR_PHY_DX4MDLR0_0 0x5c010ba0 +#define DDR_PHY_DX4MDLR0_1 0x5c110ba0 +#define DDR_PHY_DX4MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2E9U)) +#define DDR_PHY_DX4MDLR1_0 0x5c010ba4 +#define DDR_PHY_DX4MDLR1_1 0x5c110ba4 +#define DDR_PHY_DX4GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F0U)) +#define DDR_PHY_DX4GTR0_0 0x5c010bc0 +#define DDR_PHY_DX4GTR0_1 0x5c110bc0 +#define DDR_PHY_DX4RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F4U)) +#define DDR_PHY_DX4RSR0_0 0x5c010bd0 +#define DDR_PHY_DX4RSR0_1 0x5c110bd0 +#define DDR_PHY_DX4RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F5U)) +#define DDR_PHY_DX4RSR1_0 0x5c010bd4 +#define DDR_PHY_DX4RSR1_1 0x5c110bd4 +#define DDR_PHY_DX4RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F6U)) +#define DDR_PHY_DX4RSR2_0 0x5c010bd8 +#define DDR_PHY_DX4RSR2_1 0x5c110bd8 +#define DDR_PHY_DX4RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F7U)) +#define DDR_PHY_DX4RSR3_0 0x5c010bdc +#define DDR_PHY_DX4RSR3_1 0x5c110bdc +#define DDR_PHY_DX4GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F8U)) +#define DDR_PHY_DX4GSR0_0 0x5c010be0 +#define DDR_PHY_DX4GSR0_1 0x5c110be0 +#define DDR_PHY_DX4GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2F9U)) +#define DDR_PHY_DX4GSR1_0 0x5c010be4 +#define DDR_PHY_DX4GSR1_1 0x5c110be4 +#define DDR_PHY_DX4GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2FAU)) +#define DDR_PHY_DX4GSR2_0 0x5c010be8 +#define DDR_PHY_DX4GSR2_1 0x5c110be8 +#define DDR_PHY_DX4GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2FBU)) +#define DDR_PHY_DX4GSR3_0 0x5c010bec +#define DDR_PHY_DX4GSR3_1 0x5c110bec +#define DDR_PHY_DX4GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2FCU)) +#define DDR_PHY_DX4GSR4_0 0x5c010bf0 +#define DDR_PHY_DX4GSR4_1 0x5c110bf0 +#define DDR_PHY_DX4GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2FDU)) +#define DDR_PHY_DX4GSR5_0 0x5c010bf4 +#define DDR_PHY_DX4GSR5_1 0x5c110bf4 +#define DDR_PHY_DX4GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x2FEU)) +#define DDR_PHY_DX4GSR6_0 0x5c010bf8 +#define DDR_PHY_DX4GSR6_1 0x5c110bf8 +#define DDR_PHY_DX5GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x300U)) +#define DDR_PHY_DX5GCR0_0 0x5c010c00 +#define DDR_PHY_DX5GCR0_1 0x5c110c00 +#define DDR_PHY_DX5GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x301U)) +#define DDR_PHY_DX5GCR1_0 0x5c010c04 +#define DDR_PHY_DX5GCR1_1 0x5c110c04 +#define DDR_PHY_DX5GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x302U)) +#define DDR_PHY_DX5GCR2_0 0x5c010c08 +#define DDR_PHY_DX5GCR2_1 0x5c110c08 +#define DDR_PHY_DX5GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x303U)) +#define DDR_PHY_DX5GCR3_0 0x5c010c0c +#define DDR_PHY_DX5GCR3_1 0x5c110c0c +#define DDR_PHY_DX5GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x304U)) +#define DDR_PHY_DX5GCR4_0 0x5c010c10 +#define DDR_PHY_DX5GCR4_1 0x5c110c10 +#define DDR_PHY_DX5GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x305U)) +#define DDR_PHY_DX5GCR5_0 0x5c010c14 +#define DDR_PHY_DX5GCR5_1 0x5c110c14 +#define DDR_PHY_DX5GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x306U)) +#define DDR_PHY_DX5GCR6_0 0x5c010c18 +#define DDR_PHY_DX5GCR6_1 0x5c110c18 +#define DDR_PHY_DX5GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x307U)) +#define DDR_PHY_DX5GCR7_0 0x5c010c1c +#define DDR_PHY_DX5GCR7_1 0x5c110c1c +#define DDR_PHY_DX5GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x308U)) +#define DDR_PHY_DX5GCR8_0 0x5c010c20 +#define DDR_PHY_DX5GCR8_1 0x5c110c20 +#define DDR_PHY_DX5GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x309U)) +#define DDR_PHY_DX5GCR9_0 0x5c010c24 +#define DDR_PHY_DX5GCR9_1 0x5c110c24 +#define DDR_PHY_DX5BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x310U)) +#define DDR_PHY_DX5BDLR0_0 0x5c010c40 +#define DDR_PHY_DX5BDLR0_1 0x5c110c40 +#define DDR_PHY_DX5BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x311U)) +#define DDR_PHY_DX5BDLR1_0 0x5c010c44 +#define DDR_PHY_DX5BDLR1_1 0x5c110c44 +#define DDR_PHY_DX5BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x312U)) +#define DDR_PHY_DX5BDLR2_0 0x5c010c48 +#define DDR_PHY_DX5BDLR2_1 0x5c110c48 +#define DDR_PHY_DX5BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x314U)) +#define DDR_PHY_DX5BDLR3_0 0x5c010c50 +#define DDR_PHY_DX5BDLR3_1 0x5c110c50 +#define DDR_PHY_DX5BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x315U)) +#define DDR_PHY_DX5BDLR4_0 0x5c010c54 +#define DDR_PHY_DX5BDLR4_1 0x5c110c54 +#define DDR_PHY_DX5BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x316U)) +#define DDR_PHY_DX5BDLR5_0 0x5c010c58 +#define DDR_PHY_DX5BDLR5_1 0x5c110c58 +#define DDR_PHY_DX5BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x318U)) +#define DDR_PHY_DX5BDLR6_0 0x5c010c60 +#define DDR_PHY_DX5BDLR6_1 0x5c110c60 +#define DDR_PHY_DX5BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x319U)) +#define DDR_PHY_DX5BDLR7_0 0x5c010c64 +#define DDR_PHY_DX5BDLR7_1 0x5c110c64 +#define DDR_PHY_DX5BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x31AU)) +#define DDR_PHY_DX5BDLR8_0 0x5c010c68 +#define DDR_PHY_DX5BDLR8_1 0x5c110c68 +#define DDR_PHY_DX5BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x31BU)) +#define DDR_PHY_DX5BDLR9_0 0x5c010c6c +#define DDR_PHY_DX5BDLR9_1 0x5c110c6c +#define DDR_PHY_DX5LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x320U)) +#define DDR_PHY_DX5LCDLR0_0 0x5c010c80 +#define DDR_PHY_DX5LCDLR0_1 0x5c110c80 +#define DDR_PHY_DX5LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x321U)) +#define DDR_PHY_DX5LCDLR1_0 0x5c010c84 +#define DDR_PHY_DX5LCDLR1_1 0x5c110c84 +#define DDR_PHY_DX5LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x322U)) +#define DDR_PHY_DX5LCDLR2_0 0x5c010c88 +#define DDR_PHY_DX5LCDLR2_1 0x5c110c88 +#define DDR_PHY_DX5LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x323U)) +#define DDR_PHY_DX5LCDLR3_0 0x5c010c8c +#define DDR_PHY_DX5LCDLR3_1 0x5c110c8c +#define DDR_PHY_DX5LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x324U)) +#define DDR_PHY_DX5LCDLR4_0 0x5c010c90 +#define DDR_PHY_DX5LCDLR4_1 0x5c110c90 +#define DDR_PHY_DX5LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x325U)) +#define DDR_PHY_DX5LCDLR5_0 0x5c010c94 +#define DDR_PHY_DX5LCDLR5_1 0x5c110c94 +#define DDR_PHY_DX5MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x328U)) +#define DDR_PHY_DX5MDLR0_0 0x5c010ca0 +#define DDR_PHY_DX5MDLR0_1 0x5c110ca0 +#define DDR_PHY_DX5MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x329U)) +#define DDR_PHY_DX5MDLR1_0 0x5c010ca4 +#define DDR_PHY_DX5MDLR1_1 0x5c110ca4 +#define DDR_PHY_DX5GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x330U)) +#define DDR_PHY_DX5GTR0_0 0x5c010cc0 +#define DDR_PHY_DX5GTR0_1 0x5c110cc0 +#define DDR_PHY_DX5RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x334U)) +#define DDR_PHY_DX5RSR0_0 0x5c010cd0 +#define DDR_PHY_DX5RSR0_1 0x5c110cd0 +#define DDR_PHY_DX5RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x335U)) +#define DDR_PHY_DX5RSR1_0 0x5c010cd4 +#define DDR_PHY_DX5RSR1_1 0x5c110cd4 +#define DDR_PHY_DX5RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x336U)) +#define DDR_PHY_DX5RSR2_0 0x5c010cd8 +#define DDR_PHY_DX5RSR2_1 0x5c110cd8 +#define DDR_PHY_DX5RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x337U)) +#define DDR_PHY_DX5RSR3_0 0x5c010cdc +#define DDR_PHY_DX5RSR3_1 0x5c110cdc +#define DDR_PHY_DX5GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x338U)) +#define DDR_PHY_DX5GSR0_0 0x5c010ce0 +#define DDR_PHY_DX5GSR0_1 0x5c110ce0 +#define DDR_PHY_DX5GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x339U)) +#define DDR_PHY_DX5GSR1_0 0x5c010ce4 +#define DDR_PHY_DX5GSR1_1 0x5c110ce4 +#define DDR_PHY_DX5GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x33AU)) +#define DDR_PHY_DX5GSR2_0 0x5c010ce8 +#define DDR_PHY_DX5GSR2_1 0x5c110ce8 +#define DDR_PHY_DX5GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x33BU)) +#define DDR_PHY_DX5GSR3_0 0x5c010cec +#define DDR_PHY_DX5GSR3_1 0x5c110cec +#define DDR_PHY_DX5GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x33CU)) +#define DDR_PHY_DX5GSR4_0 0x5c010cf0 +#define DDR_PHY_DX5GSR4_1 0x5c110cf0 +#define DDR_PHY_DX5GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x33DU)) +#define DDR_PHY_DX5GSR5_0 0x5c010cf4 +#define DDR_PHY_DX5GSR5_1 0x5c110cf4 +#define DDR_PHY_DX5GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x33EU)) +#define DDR_PHY_DX5GSR6_0 0x5c010cf8 +#define DDR_PHY_DX5GSR6_1 0x5c110cf8 +#define DDR_PHY_DX6GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x340U)) +#define DDR_PHY_DX6GCR0_0 0x5c010d00 +#define DDR_PHY_DX6GCR0_1 0x5c110d00 +#define DDR_PHY_DX6GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x341U)) +#define DDR_PHY_DX6GCR1_0 0x5c010d04 +#define DDR_PHY_DX6GCR1_1 0x5c110d04 +#define DDR_PHY_DX6GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x342U)) +#define DDR_PHY_DX6GCR2_0 0x5c010d08 +#define DDR_PHY_DX6GCR2_1 0x5c110d08 +#define DDR_PHY_DX6GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x343U)) +#define DDR_PHY_DX6GCR3_0 0x5c010d0c +#define DDR_PHY_DX6GCR3_1 0x5c110d0c +#define DDR_PHY_DX6GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x344U)) +#define DDR_PHY_DX6GCR4_0 0x5c010d10 +#define DDR_PHY_DX6GCR4_1 0x5c110d10 +#define DDR_PHY_DX6GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x345U)) +#define DDR_PHY_DX6GCR5_0 0x5c010d14 +#define DDR_PHY_DX6GCR5_1 0x5c110d14 +#define DDR_PHY_DX6GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x346U)) +#define DDR_PHY_DX6GCR6_0 0x5c010d18 +#define DDR_PHY_DX6GCR6_1 0x5c110d18 +#define DDR_PHY_DX6GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x347U)) +#define DDR_PHY_DX6GCR7_0 0x5c010d1c +#define DDR_PHY_DX6GCR7_1 0x5c110d1c +#define DDR_PHY_DX6GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x348U)) +#define DDR_PHY_DX6GCR8_0 0x5c010d20 +#define DDR_PHY_DX6GCR8_1 0x5c110d20 +#define DDR_PHY_DX6GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x349U)) +#define DDR_PHY_DX6GCR9_0 0x5c010d24 +#define DDR_PHY_DX6GCR9_1 0x5c110d24 +#define DDR_PHY_DX6BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x350U)) +#define DDR_PHY_DX6BDLR0_0 0x5c010d40 +#define DDR_PHY_DX6BDLR0_1 0x5c110d40 +#define DDR_PHY_DX6BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x351U)) +#define DDR_PHY_DX6BDLR1_0 0x5c010d44 +#define DDR_PHY_DX6BDLR1_1 0x5c110d44 +#define DDR_PHY_DX6BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x352U)) +#define DDR_PHY_DX6BDLR2_0 0x5c010d48 +#define DDR_PHY_DX6BDLR2_1 0x5c110d48 +#define DDR_PHY_DX6BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x354U)) +#define DDR_PHY_DX6BDLR3_0 0x5c010d50 +#define DDR_PHY_DX6BDLR3_1 0x5c110d50 +#define DDR_PHY_DX6BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x355U)) +#define DDR_PHY_DX6BDLR4_0 0x5c010d54 +#define DDR_PHY_DX6BDLR4_1 0x5c110d54 +#define DDR_PHY_DX6BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x356U)) +#define DDR_PHY_DX6BDLR5_0 0x5c010d58 +#define DDR_PHY_DX6BDLR5_1 0x5c110d58 +#define DDR_PHY_DX6BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x358U)) +#define DDR_PHY_DX6BDLR6_0 0x5c010d60 +#define DDR_PHY_DX6BDLR6_1 0x5c110d60 +#define DDR_PHY_DX6BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x359U)) +#define DDR_PHY_DX6BDLR7_0 0x5c010d64 +#define DDR_PHY_DX6BDLR7_1 0x5c110d64 +#define DDR_PHY_DX6BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x35AU)) +#define DDR_PHY_DX6BDLR8_0 0x5c010d68 +#define DDR_PHY_DX6BDLR8_1 0x5c110d68 +#define DDR_PHY_DX6BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x35BU)) +#define DDR_PHY_DX6BDLR9_0 0x5c010d6c +#define DDR_PHY_DX6BDLR9_1 0x5c110d6c +#define DDR_PHY_DX6LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x360U)) +#define DDR_PHY_DX6LCDLR0_0 0x5c010d80 +#define DDR_PHY_DX6LCDLR0_1 0x5c110d80 +#define DDR_PHY_DX6LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x361U)) +#define DDR_PHY_DX6LCDLR1_0 0x5c010d84 +#define DDR_PHY_DX6LCDLR1_1 0x5c110d84 +#define DDR_PHY_DX6LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x362U)) +#define DDR_PHY_DX6LCDLR2_0 0x5c010d88 +#define DDR_PHY_DX6LCDLR2_1 0x5c110d88 +#define DDR_PHY_DX6LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x363U)) +#define DDR_PHY_DX6LCDLR3_0 0x5c010d8c +#define DDR_PHY_DX6LCDLR3_1 0x5c110d8c +#define DDR_PHY_DX6LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x364U)) +#define DDR_PHY_DX6LCDLR4_0 0x5c010d90 +#define DDR_PHY_DX6LCDLR4_1 0x5c110d90 +#define DDR_PHY_DX6LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x365U)) +#define DDR_PHY_DX6LCDLR5_0 0x5c010d94 +#define DDR_PHY_DX6LCDLR5_1 0x5c110d94 +#define DDR_PHY_DX6MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x368U)) +#define DDR_PHY_DX6MDLR0_0 0x5c010da0 +#define DDR_PHY_DX6MDLR0_1 0x5c110da0 +#define DDR_PHY_DX6MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x369U)) +#define DDR_PHY_DX6MDLR1_0 0x5c010da4 +#define DDR_PHY_DX6MDLR1_1 0x5c110da4 +#define DDR_PHY_DX6GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x370U)) +#define DDR_PHY_DX6GTR0_0 0x5c010dc0 +#define DDR_PHY_DX6GTR0_1 0x5c110dc0 +#define DDR_PHY_DX6RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x374U)) +#define DDR_PHY_DX6RSR0_0 0x5c010dd0 +#define DDR_PHY_DX6RSR0_1 0x5c110dd0 +#define DDR_PHY_DX6RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x375U)) +#define DDR_PHY_DX6RSR1_0 0x5c010dd4 +#define DDR_PHY_DX6RSR1_1 0x5c110dd4 +#define DDR_PHY_DX6RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x376U)) +#define DDR_PHY_DX6RSR2_0 0x5c010dd8 +#define DDR_PHY_DX6RSR2_1 0x5c110dd8 +#define DDR_PHY_DX6RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x377U)) +#define DDR_PHY_DX6RSR3_0 0x5c010ddc +#define DDR_PHY_DX6RSR3_1 0x5c110ddc +#define DDR_PHY_DX6GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x378U)) +#define DDR_PHY_DX6GSR0_0 0x5c010de0 +#define DDR_PHY_DX6GSR0_1 0x5c110de0 +#define DDR_PHY_DX6GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x379U)) +#define DDR_PHY_DX6GSR1_0 0x5c010de4 +#define DDR_PHY_DX6GSR1_1 0x5c110de4 +#define DDR_PHY_DX6GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x37AU)) +#define DDR_PHY_DX6GSR2_0 0x5c010de8 +#define DDR_PHY_DX6GSR2_1 0x5c110de8 +#define DDR_PHY_DX6GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x37BU)) +#define DDR_PHY_DX6GSR3_0 0x5c010dec +#define DDR_PHY_DX6GSR3_1 0x5c110dec +#define DDR_PHY_DX6GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x37CU)) +#define DDR_PHY_DX6GSR4_0 0x5c010df0 +#define DDR_PHY_DX6GSR4_1 0x5c110df0 +#define DDR_PHY_DX6GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x37DU)) +#define DDR_PHY_DX6GSR5_0 0x5c010df4 +#define DDR_PHY_DX6GSR5_1 0x5c110df4 +#define DDR_PHY_DX6GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x37EU)) +#define DDR_PHY_DX6GSR6_0 0x5c010df8 +#define DDR_PHY_DX6GSR6_1 0x5c110df8 +#define DDR_PHY_DX7GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x380U)) +#define DDR_PHY_DX7GCR0_0 0x5c010e00 +#define DDR_PHY_DX7GCR0_1 0x5c110e00 +#define DDR_PHY_DX7GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x381U)) +#define DDR_PHY_DX7GCR1_0 0x5c010e04 +#define DDR_PHY_DX7GCR1_1 0x5c110e04 +#define DDR_PHY_DX7GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x382U)) +#define DDR_PHY_DX7GCR2_0 0x5c010e08 +#define DDR_PHY_DX7GCR2_1 0x5c110e08 +#define DDR_PHY_DX7GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x383U)) +#define DDR_PHY_DX7GCR3_0 0x5c010e0c +#define DDR_PHY_DX7GCR3_1 0x5c110e0c +#define DDR_PHY_DX7GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x384U)) +#define DDR_PHY_DX7GCR4_0 0x5c010e10 +#define DDR_PHY_DX7GCR4_1 0x5c110e10 +#define DDR_PHY_DX7GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x385U)) +#define DDR_PHY_DX7GCR5_0 0x5c010e14 +#define DDR_PHY_DX7GCR5_1 0x5c110e14 +#define DDR_PHY_DX7GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x386U)) +#define DDR_PHY_DX7GCR6_0 0x5c010e18 +#define DDR_PHY_DX7GCR6_1 0x5c110e18 +#define DDR_PHY_DX7GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x387U)) +#define DDR_PHY_DX7GCR7_0 0x5c010e1c +#define DDR_PHY_DX7GCR7_1 0x5c110e1c +#define DDR_PHY_DX7GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x388U)) +#define DDR_PHY_DX7GCR8_0 0x5c010e20 +#define DDR_PHY_DX7GCR8_1 0x5c110e20 +#define DDR_PHY_DX7GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x389U)) +#define DDR_PHY_DX7GCR9_0 0x5c010e24 +#define DDR_PHY_DX7GCR9_1 0x5c110e24 +#define DDR_PHY_DX7BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x390U)) +#define DDR_PHY_DX7BDLR0_0 0x5c010e40 +#define DDR_PHY_DX7BDLR0_1 0x5c110e40 +#define DDR_PHY_DX7BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x391U)) +#define DDR_PHY_DX7BDLR1_0 0x5c010e44 +#define DDR_PHY_DX7BDLR1_1 0x5c110e44 +#define DDR_PHY_DX7BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x392U)) +#define DDR_PHY_DX7BDLR2_0 0x5c010e48 +#define DDR_PHY_DX7BDLR2_1 0x5c110e48 +#define DDR_PHY_DX7BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x394U)) +#define DDR_PHY_DX7BDLR3_0 0x5c010e50 +#define DDR_PHY_DX7BDLR3_1 0x5c110e50 +#define DDR_PHY_DX7BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x395U)) +#define DDR_PHY_DX7BDLR4_0 0x5c010e54 +#define DDR_PHY_DX7BDLR4_1 0x5c110e54 +#define DDR_PHY_DX7BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x396U)) +#define DDR_PHY_DX7BDLR5_0 0x5c010e58 +#define DDR_PHY_DX7BDLR5_1 0x5c110e58 +#define DDR_PHY_DX7BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x398U)) +#define DDR_PHY_DX7BDLR6_0 0x5c010e60 +#define DDR_PHY_DX7BDLR6_1 0x5c110e60 +#define DDR_PHY_DX7BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x399U)) +#define DDR_PHY_DX7BDLR7_0 0x5c010e64 +#define DDR_PHY_DX7BDLR7_1 0x5c110e64 +#define DDR_PHY_DX7BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x39AU)) +#define DDR_PHY_DX7BDLR8_0 0x5c010e68 +#define DDR_PHY_DX7BDLR8_1 0x5c110e68 +#define DDR_PHY_DX7BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x39BU)) +#define DDR_PHY_DX7BDLR9_0 0x5c010e6c +#define DDR_PHY_DX7BDLR9_1 0x5c110e6c +#define DDR_PHY_DX7LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A0U)) +#define DDR_PHY_DX7LCDLR0_0 0x5c010e80 +#define DDR_PHY_DX7LCDLR0_1 0x5c110e80 +#define DDR_PHY_DX7LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A1U)) +#define DDR_PHY_DX7LCDLR1_0 0x5c010e84 +#define DDR_PHY_DX7LCDLR1_1 0x5c110e84 +#define DDR_PHY_DX7LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A2U)) +#define DDR_PHY_DX7LCDLR2_0 0x5c010e88 +#define DDR_PHY_DX7LCDLR2_1 0x5c110e88 +#define DDR_PHY_DX7LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A3U)) +#define DDR_PHY_DX7LCDLR3_0 0x5c010e8c +#define DDR_PHY_DX7LCDLR3_1 0x5c110e8c +#define DDR_PHY_DX7LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A4U)) +#define DDR_PHY_DX7LCDLR4_0 0x5c010e90 +#define DDR_PHY_DX7LCDLR4_1 0x5c110e90 +#define DDR_PHY_DX7LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A5U)) +#define DDR_PHY_DX7LCDLR5_0 0x5c010e94 +#define DDR_PHY_DX7LCDLR5_1 0x5c110e94 +#define DDR_PHY_DX7MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A8U)) +#define DDR_PHY_DX7MDLR0_0 0x5c010ea0 +#define DDR_PHY_DX7MDLR0_1 0x5c110ea0 +#define DDR_PHY_DX7MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3A9U)) +#define DDR_PHY_DX7MDLR1_0 0x5c010ea4 +#define DDR_PHY_DX7MDLR1_1 0x5c110ea4 +#define DDR_PHY_DX7GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B0U)) +#define DDR_PHY_DX7GTR0_0 0x5c010ec0 +#define DDR_PHY_DX7GTR0_1 0x5c110ec0 +#define DDR_PHY_DX7RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B4U)) +#define DDR_PHY_DX7RSR0_0 0x5c010ed0 +#define DDR_PHY_DX7RSR0_1 0x5c110ed0 +#define DDR_PHY_DX7RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B5U)) +#define DDR_PHY_DX7RSR1_0 0x5c010ed4 +#define DDR_PHY_DX7RSR1_1 0x5c110ed4 +#define DDR_PHY_DX7RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B6U)) +#define DDR_PHY_DX7RSR2_0 0x5c010ed8 +#define DDR_PHY_DX7RSR2_1 0x5c110ed8 +#define DDR_PHY_DX7RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B7U)) +#define DDR_PHY_DX7RSR3_0 0x5c010edc +#define DDR_PHY_DX7RSR3_1 0x5c110edc +#define DDR_PHY_DX7GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B8U)) +#define DDR_PHY_DX7GSR0_0 0x5c010ee0 +#define DDR_PHY_DX7GSR0_1 0x5c110ee0 +#define DDR_PHY_DX7GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3B9U)) +#define DDR_PHY_DX7GSR1_0 0x5c010ee4 +#define DDR_PHY_DX7GSR1_1 0x5c110ee4 +#define DDR_PHY_DX7GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3BAU)) +#define DDR_PHY_DX7GSR2_0 0x5c010ee8 +#define DDR_PHY_DX7GSR2_1 0x5c110ee8 +#define DDR_PHY_DX7GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3BBU)) +#define DDR_PHY_DX7GSR3_0 0x5c010eec +#define DDR_PHY_DX7GSR3_1 0x5c110eec +#define DDR_PHY_DX7GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3BCU)) +#define DDR_PHY_DX7GSR4_0 0x5c010ef0 +#define DDR_PHY_DX7GSR4_1 0x5c110ef0 +#define DDR_PHY_DX7GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3BDU)) +#define DDR_PHY_DX7GSR5_0 0x5c010ef4 +#define DDR_PHY_DX7GSR5_1 0x5c110ef4 +#define DDR_PHY_DX7GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3BEU)) +#define DDR_PHY_DX7GSR6_0 0x5c010ef8 +#define DDR_PHY_DX7GSR6_1 0x5c110ef8 +#define DDR_PHY_DX8GCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C0U)) +#define DDR_PHY_DX8GCR0_0 0x5c010f00 +#define DDR_PHY_DX8GCR0_1 0x5c110f00 +#define DDR_PHY_DX8GCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C1U)) +#define DDR_PHY_DX8GCR1_0 0x5c010f04 +#define DDR_PHY_DX8GCR1_1 0x5c110f04 +#define DDR_PHY_DX8GCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C2U)) +#define DDR_PHY_DX8GCR2_0 0x5c010f08 +#define DDR_PHY_DX8GCR2_1 0x5c110f08 +#define DDR_PHY_DX8GCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C3U)) +#define DDR_PHY_DX8GCR3_0 0x5c010f0c +#define DDR_PHY_DX8GCR3_1 0x5c110f0c +#define DDR_PHY_DX8GCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C4U)) +#define DDR_PHY_DX8GCR4_0 0x5c010f10 +#define DDR_PHY_DX8GCR4_1 0x5c110f10 +#define DDR_PHY_DX8GCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C5U)) +#define DDR_PHY_DX8GCR5_0 0x5c010f14 +#define DDR_PHY_DX8GCR5_1 0x5c110f14 +#define DDR_PHY_DX8GCR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C6U)) +#define DDR_PHY_DX8GCR6_0 0x5c010f18 +#define DDR_PHY_DX8GCR6_1 0x5c110f18 +#define DDR_PHY_DX8GCR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C7U)) +#define DDR_PHY_DX8GCR7_0 0x5c010f1c +#define DDR_PHY_DX8GCR7_1 0x5c110f1c +#define DDR_PHY_DX8GCR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C8U)) +#define DDR_PHY_DX8GCR8_0 0x5c010f20 +#define DDR_PHY_DX8GCR8_1 0x5c110f20 +#define DDR_PHY_DX8GCR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3C9U)) +#define DDR_PHY_DX8GCR9_0 0x5c010f24 +#define DDR_PHY_DX8GCR9_1 0x5c110f24 +#define DDR_PHY_DX8BDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D0U)) +#define DDR_PHY_DX8BDLR0_0 0x5c010f40 +#define DDR_PHY_DX8BDLR0_1 0x5c110f40 +#define DDR_PHY_DX8BDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D1U)) +#define DDR_PHY_DX8BDLR1_0 0x5c010f44 +#define DDR_PHY_DX8BDLR1_1 0x5c110f44 +#define DDR_PHY_DX8BDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D2U)) +#define DDR_PHY_DX8BDLR2_0 0x5c010f48 +#define DDR_PHY_DX8BDLR2_1 0x5c110f48 +#define DDR_PHY_DX8BDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D4U)) +#define DDR_PHY_DX8BDLR3_0 0x5c010f50 +#define DDR_PHY_DX8BDLR3_1 0x5c110f50 +#define DDR_PHY_DX8BDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D5U)) +#define DDR_PHY_DX8BDLR4_0 0x5c010f54 +#define DDR_PHY_DX8BDLR4_1 0x5c110f54 +#define DDR_PHY_DX8BDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D6U)) +#define DDR_PHY_DX8BDLR5_0 0x5c010f58 +#define DDR_PHY_DX8BDLR5_1 0x5c110f58 +#define DDR_PHY_DX8BDLR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D8U)) +#define DDR_PHY_DX8BDLR6_0 0x5c010f60 +#define DDR_PHY_DX8BDLR6_1 0x5c110f60 +#define DDR_PHY_DX8BDLR7(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3D9U)) +#define DDR_PHY_DX8BDLR7_0 0x5c010f64 +#define DDR_PHY_DX8BDLR7_1 0x5c110f64 +#define DDR_PHY_DX8BDLR8(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3DAU)) +#define DDR_PHY_DX8BDLR8_0 0x5c010f68 +#define DDR_PHY_DX8BDLR8_1 0x5c110f68 +#define DDR_PHY_DX8BDLR9(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3DBU)) +#define DDR_PHY_DX8BDLR9_0 0x5c010f6c +#define DDR_PHY_DX8BDLR9_1 0x5c110f6c +#define DDR_PHY_DX8LCDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E0U)) +#define DDR_PHY_DX8LCDLR0_0 0x5c010f80 +#define DDR_PHY_DX8LCDLR0_1 0x5c110f80 +#define DDR_PHY_DX8LCDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E1U)) +#define DDR_PHY_DX8LCDLR1_0 0x5c010f84 +#define DDR_PHY_DX8LCDLR1_1 0x5c110f84 +#define DDR_PHY_DX8LCDLR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E2U)) +#define DDR_PHY_DX8LCDLR2_0 0x5c010f88 +#define DDR_PHY_DX8LCDLR2_1 0x5c110f88 +#define DDR_PHY_DX8LCDLR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E3U)) +#define DDR_PHY_DX8LCDLR3_0 0x5c010f8c +#define DDR_PHY_DX8LCDLR3_1 0x5c110f8c +#define DDR_PHY_DX8LCDLR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E4U)) +#define DDR_PHY_DX8LCDLR4_0 0x5c010f90 +#define DDR_PHY_DX8LCDLR4_1 0x5c110f90 +#define DDR_PHY_DX8LCDLR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E5U)) +#define DDR_PHY_DX8LCDLR5_0 0x5c010f94 +#define DDR_PHY_DX8LCDLR5_1 0x5c110f94 +#define DDR_PHY_DX8MDLR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E8U)) +#define DDR_PHY_DX8MDLR0_0 0x5c010fa0 +#define DDR_PHY_DX8MDLR0_1 0x5c110fa0 +#define DDR_PHY_DX8MDLR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3E9U)) +#define DDR_PHY_DX8MDLR1_0 0x5c010fa4 +#define DDR_PHY_DX8MDLR1_1 0x5c110fa4 +#define DDR_PHY_DX8GTR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F0U)) +#define DDR_PHY_DX8GTR0_0 0x5c010fc0 +#define DDR_PHY_DX8GTR0_1 0x5c110fc0 +#define DDR_PHY_DX8RSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F4U)) +#define DDR_PHY_DX8RSR0_0 0x5c010fd0 +#define DDR_PHY_DX8RSR0_1 0x5c110fd0 +#define DDR_PHY_DX8RSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F5U)) +#define DDR_PHY_DX8RSR1_0 0x5c010fd4 +#define DDR_PHY_DX8RSR1_1 0x5c110fd4 +#define DDR_PHY_DX8RSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F6U)) +#define DDR_PHY_DX8RSR2_0 0x5c010fd8 +#define DDR_PHY_DX8RSR2_1 0x5c110fd8 +#define DDR_PHY_DX8RSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F7U)) +#define DDR_PHY_DX8RSR3_0 0x5c010fdc +#define DDR_PHY_DX8RSR3_1 0x5c110fdc +#define DDR_PHY_DX8GSR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F8U)) +#define DDR_PHY_DX8GSR0_0 0x5c010fe0 +#define DDR_PHY_DX8GSR0_1 0x5c110fe0 +#define DDR_PHY_DX8GSR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3F9U)) +#define DDR_PHY_DX8GSR1_0 0x5c010fe4 +#define DDR_PHY_DX8GSR1_1 0x5c110fe4 +#define DDR_PHY_DX8GSR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3FAU)) +#define DDR_PHY_DX8GSR2_0 0x5c010fe8 +#define DDR_PHY_DX8GSR2_1 0x5c110fe8 +#define DDR_PHY_DX8GSR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3FBU)) +#define DDR_PHY_DX8GSR3_0 0x5c010fec +#define DDR_PHY_DX8GSR3_1 0x5c110fec +#define DDR_PHY_DX8GSR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3FCU)) +#define DDR_PHY_DX8GSR4_0 0x5c010ff0 +#define DDR_PHY_DX8GSR4_1 0x5c110ff0 +#define DDR_PHY_DX8GSR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3FDU)) +#define DDR_PHY_DX8GSR5_0 0x5c010ff4 +#define DDR_PHY_DX8GSR5_1 0x5c110ff4 +#define DDR_PHY_DX8GSR6(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x3FEU)) +#define DDR_PHY_DX8GSR6_0 0x5c010ff8 +#define DDR_PHY_DX8GSR6_1 0x5c110ff8 +#define DDR_PHY_DX8SL0OSC(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x500U)) +#define DDR_PHY_DX8SL0OSC_0 0x5c011400 +#define DDR_PHY_DX8SL0OSC_1 0x5c111400 +#define DDR_PHY_DX8SL0PLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x501U)) +#define DDR_PHY_DX8SL0PLLCR0_0 0x5c011404 +#define DDR_PHY_DX8SL0PLLCR0_1 0x5c111404 +#define DDR_PHY_DX8SL0PLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x502U)) +#define DDR_PHY_DX8SL0PLLCR1_0 0x5c011408 +#define DDR_PHY_DX8SL0PLLCR1_1 0x5c111408 +#define DDR_PHY_DX8SL0PLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x503U)) +#define DDR_PHY_DX8SL0PLLCR2_0 0x5c01140c +#define DDR_PHY_DX8SL0PLLCR2_1 0x5c11140c +#define DDR_PHY_DX8SL0PLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x504U)) +#define DDR_PHY_DX8SL0PLLCR3_0 0x5c011410 +#define DDR_PHY_DX8SL0PLLCR3_1 0x5c111410 +#define DDR_PHY_DX8SL0PLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x505U)) +#define DDR_PHY_DX8SL0PLLCR4_0 0x5c011414 +#define DDR_PHY_DX8SL0PLLCR4_1 0x5c111414 +#define DDR_PHY_DX8SL0PLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x506U)) +#define DDR_PHY_DX8SL0PLLCR5_0 0x5c011418 +#define DDR_PHY_DX8SL0PLLCR5_1 0x5c111418 +#define DDR_PHY_DX8SL0DQSCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x507U)) +#define DDR_PHY_DX8SL0DQSCTL_0 0x5c01141c +#define DDR_PHY_DX8SL0DQSCTL_1 0x5c11141c +#define DDR_PHY_DX8SL0TRNCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x508U)) +#define DDR_PHY_DX8SL0TRNCTL_0 0x5c011420 +#define DDR_PHY_DX8SL0TRNCTL_1 0x5c111420 +#define DDR_PHY_DX8SL0DDLCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x509U)) +#define DDR_PHY_DX8SL0DDLCTL_0 0x5c011424 +#define DDR_PHY_DX8SL0DDLCTL_1 0x5c111424 +#define DDR_PHY_DX8SL0DXCTL1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x50AU)) +#define DDR_PHY_DX8SL0DXCTL1_0 0x5c011428 +#define DDR_PHY_DX8SL0DXCTL1_1 0x5c111428 +#define DDR_PHY_DX8SL0DXCTL2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x50BU)) +#define DDR_PHY_DX8SL0DXCTL2_0 0x5c01142c +#define DDR_PHY_DX8SL0DXCTL2_1 0x5c11142c +#define DDR_PHY_DX8SL0IOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x50CU)) +#define DDR_PHY_DX8SL0IOCR_0 0x5c011430 +#define DDR_PHY_DX8SL0IOCR_1 0x5c111430 +#define DDR_PHY_DX8SL1OSC(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x510U)) +#define DDR_PHY_DX8SL1OSC_0 0x5c011440 +#define DDR_PHY_DX8SL1OSC_1 0x5c111440 +#define DDR_PHY_DX8SL1PLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x511U)) +#define DDR_PHY_DX8SL1PLLCR0_0 0x5c011444 +#define DDR_PHY_DX8SL1PLLCR0_1 0x5c111444 +#define DDR_PHY_DX8SL1PLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x512U)) +#define DDR_PHY_DX8SL1PLLCR1_0 0x5c011448 +#define DDR_PHY_DX8SL1PLLCR1_1 0x5c111448 +#define DDR_PHY_DX8SL1PLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x513U)) +#define DDR_PHY_DX8SL1PLLCR2_0 0x5c01144c +#define DDR_PHY_DX8SL1PLLCR2_1 0x5c11144c +#define DDR_PHY_DX8SL1PLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x514U)) +#define DDR_PHY_DX8SL1PLLCR3_0 0x5c011450 +#define DDR_PHY_DX8SL1PLLCR3_1 0x5c111450 +#define DDR_PHY_DX8SL1PLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x515U)) +#define DDR_PHY_DX8SL1PLLCR4_0 0x5c011454 +#define DDR_PHY_DX8SL1PLLCR4_1 0x5c111454 +#define DDR_PHY_DX8SL1PLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x516U)) +#define DDR_PHY_DX8SL1PLLCR5_0 0x5c011458 +#define DDR_PHY_DX8SL1PLLCR5_1 0x5c111458 +#define DDR_PHY_DX8SL1DQSCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x517U)) +#define DDR_PHY_DX8SL1DQSCTL_0 0x5c01145c +#define DDR_PHY_DX8SL1DQSCTL_1 0x5c11145c +#define DDR_PHY_DX8SL1TRNCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x518U)) +#define DDR_PHY_DX8SL1TRNCTL_0 0x5c011460 +#define DDR_PHY_DX8SL1TRNCTL_1 0x5c111460 +#define DDR_PHY_DX8SL1DDLCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x519U)) +#define DDR_PHY_DX8SL1DDLCTL_0 0x5c011464 +#define DDR_PHY_DX8SL1DDLCTL_1 0x5c111464 +#define DDR_PHY_DX8SL1DXCTL1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x51AU)) +#define DDR_PHY_DX8SL1DXCTL1_0 0x5c011468 +#define DDR_PHY_DX8SL1DXCTL1_1 0x5c111468 +#define DDR_PHY_DX8SL1DXCTL2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x51BU)) +#define DDR_PHY_DX8SL1DXCTL2_0 0x5c01146c +#define DDR_PHY_DX8SL1DXCTL2_1 0x5c11146c +#define DDR_PHY_DX8SL1IOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x51CU)) +#define DDR_PHY_DX8SL1IOCR_0 0x5c011470 +#define DDR_PHY_DX8SL1IOCR_1 0x5c111470 +#define DDR_PHY_DX8SL2OSC(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x520U)) +#define DDR_PHY_DX8SL2OSC_0 0x5c011480 +#define DDR_PHY_DX8SL2OSC_1 0x5c111480 +#define DDR_PHY_DX8SL2PLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x521U)) +#define DDR_PHY_DX8SL2PLLCR0_0 0x5c011484 +#define DDR_PHY_DX8SL2PLLCR0_1 0x5c111484 +#define DDR_PHY_DX8SL2PLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x522U)) +#define DDR_PHY_DX8SL2PLLCR1_0 0x5c011488 +#define DDR_PHY_DX8SL2PLLCR1_1 0x5c111488 +#define DDR_PHY_DX8SL2PLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x523U)) +#define DDR_PHY_DX8SL2PLLCR2_0 0x5c01148c +#define DDR_PHY_DX8SL2PLLCR2_1 0x5c11148c +#define DDR_PHY_DX8SL2PLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x524U)) +#define DDR_PHY_DX8SL2PLLCR3_0 0x5c011490 +#define DDR_PHY_DX8SL2PLLCR3_1 0x5c111490 +#define DDR_PHY_DX8SL2PLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x525U)) +#define DDR_PHY_DX8SL2PLLCR4_0 0x5c011494 +#define DDR_PHY_DX8SL2PLLCR4_1 0x5c111494 +#define DDR_PHY_DX8SL2PLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x526U)) +#define DDR_PHY_DX8SL2PLLCR5_0 0x5c011498 +#define DDR_PHY_DX8SL2PLLCR5_1 0x5c111498 +#define DDR_PHY_DX8SL2DQSCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x527U)) +#define DDR_PHY_DX8SL2DQSCTL_0 0x5c01149c +#define DDR_PHY_DX8SL2DQSCTL_1 0x5c11149c +#define DDR_PHY_DX8SL2TRNCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x528U)) +#define DDR_PHY_DX8SL2TRNCTL_0 0x5c0114a0 +#define DDR_PHY_DX8SL2TRNCTL_1 0x5c1114a0 +#define DDR_PHY_DX8SL2DDLCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x529U)) +#define DDR_PHY_DX8SL2DDLCTL_0 0x5c0114a4 +#define DDR_PHY_DX8SL2DDLCTL_1 0x5c1114a4 +#define DDR_PHY_DX8SL2DXCTL1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x52AU)) +#define DDR_PHY_DX8SL2DXCTL1_0 0x5c0114a8 +#define DDR_PHY_DX8SL2DXCTL1_1 0x5c1114a8 +#define DDR_PHY_DX8SL2DXCTL2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x52BU)) +#define DDR_PHY_DX8SL2DXCTL2_0 0x5c0114ac +#define DDR_PHY_DX8SL2DXCTL2_1 0x5c1114ac +#define DDR_PHY_DX8SL2IOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x52CU)) +#define DDR_PHY_DX8SL2IOCR_0 0x5c0114b0 +#define DDR_PHY_DX8SL2IOCR_1 0x5c1114b0 +#define DDR_PHY_DX8SL3OSC(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x530U)) +#define DDR_PHY_DX8SL3OSC_0 0x5c0114c0 +#define DDR_PHY_DX8SL3OSC_1 0x5c1114c0 +#define DDR_PHY_DX8SL3PLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x531U)) +#define DDR_PHY_DX8SL3PLLCR0_0 0x5c0114c4 +#define DDR_PHY_DX8SL3PLLCR0_1 0x5c1114c4 +#define DDR_PHY_DX8SL3PLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x532U)) +#define DDR_PHY_DX8SL3PLLCR1_0 0x5c0114c8 +#define DDR_PHY_DX8SL3PLLCR1_1 0x5c1114c8 +#define DDR_PHY_DX8SL3PLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x533U)) +#define DDR_PHY_DX8SL3PLLCR2_0 0x5c0114cc +#define DDR_PHY_DX8SL3PLLCR2_1 0x5c1114cc +#define DDR_PHY_DX8SL3PLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x534U)) +#define DDR_PHY_DX8SL3PLLCR3_0 0x5c0114d0 +#define DDR_PHY_DX8SL3PLLCR3_1 0x5c1114d0 +#define DDR_PHY_DX8SL3PLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x535U)) +#define DDR_PHY_DX8SL3PLLCR4_0 0x5c0114d4 +#define DDR_PHY_DX8SL3PLLCR4_1 0x5c1114d4 +#define DDR_PHY_DX8SL3PLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x536U)) +#define DDR_PHY_DX8SL3PLLCR5_0 0x5c0114d8 +#define DDR_PHY_DX8SL3PLLCR5_1 0x5c1114d8 +#define DDR_PHY_DX8SL3DQSCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x537U)) +#define DDR_PHY_DX8SL3DQSCTL_0 0x5c0114dc +#define DDR_PHY_DX8SL3DQSCTL_1 0x5c1114dc +#define DDR_PHY_DX8SL3TRNCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x538U)) +#define DDR_PHY_DX8SL3TRNCTL_0 0x5c0114e0 +#define DDR_PHY_DX8SL3TRNCTL_1 0x5c1114e0 +#define DDR_PHY_DX8SL3DDLCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x539U)) +#define DDR_PHY_DX8SL3DDLCTL_0 0x5c0114e4 +#define DDR_PHY_DX8SL3DDLCTL_1 0x5c1114e4 +#define DDR_PHY_DX8SL3DXCTL1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x53AU)) +#define DDR_PHY_DX8SL3DXCTL1_0 0x5c0114e8 +#define DDR_PHY_DX8SL3DXCTL1_1 0x5c1114e8 +#define DDR_PHY_DX8SL3DXCTL2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x53BU)) +#define DDR_PHY_DX8SL3DXCTL2_0 0x5c0114ec +#define DDR_PHY_DX8SL3DXCTL2_1 0x5c1114ec +#define DDR_PHY_DX8SL3IOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x53CU)) +#define DDR_PHY_DX8SL3IOCR_0 0x5c0114f0 +#define DDR_PHY_DX8SL3IOCR_1 0x5c1114f0 +#define DDR_PHY_DX8SL4OSC(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x540U)) +#define DDR_PHY_DX8SL4OSC_0 0x5c011500 +#define DDR_PHY_DX8SL4OSC_1 0x5c111500 +#define DDR_PHY_DX8SL4PLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x541U)) +#define DDR_PHY_DX8SL4PLLCR0_0 0x5c011504 +#define DDR_PHY_DX8SL4PLLCR0_1 0x5c111504 +#define DDR_PHY_DX8SL4PLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x542U)) +#define DDR_PHY_DX8SL4PLLCR1_0 0x5c011508 +#define DDR_PHY_DX8SL4PLLCR1_1 0x5c111508 +#define DDR_PHY_DX8SL4PLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x543U)) +#define DDR_PHY_DX8SL4PLLCR2_0 0x5c01150c +#define DDR_PHY_DX8SL4PLLCR2_1 0x5c11150c +#define DDR_PHY_DX8SL4PLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x544U)) +#define DDR_PHY_DX8SL4PLLCR3_0 0x5c011510 +#define DDR_PHY_DX8SL4PLLCR3_1 0x5c111510 +#define DDR_PHY_DX8SL4PLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x545U)) +#define DDR_PHY_DX8SL4PLLCR4_0 0x5c011514 +#define DDR_PHY_DX8SL4PLLCR4_1 0x5c111514 +#define DDR_PHY_DX8SL4PLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x546U)) +#define DDR_PHY_DX8SL4PLLCR5_0 0x5c011518 +#define DDR_PHY_DX8SL4PLLCR5_1 0x5c111518 +#define DDR_PHY_DX8SL4DQSCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x547U)) +#define DDR_PHY_DX8SL4DQSCTL_0 0x5c01151c +#define DDR_PHY_DX8SL4DQSCTL_1 0x5c11151c +#define DDR_PHY_DX8SL4TRNCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x548U)) +#define DDR_PHY_DX8SL4TRNCTL_0 0x5c011520 +#define DDR_PHY_DX8SL4TRNCTL_1 0x5c111520 +#define DDR_PHY_DX8SL4DDLCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x549U)) +#define DDR_PHY_DX8SL4DDLCTL_0 0x5c011524 +#define DDR_PHY_DX8SL4DDLCTL_1 0x5c111524 +#define DDR_PHY_DX8SL4DXCTL1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x54AU)) +#define DDR_PHY_DX8SL4DXCTL1_0 0x5c011528 +#define DDR_PHY_DX8SL4DXCTL1_1 0x5c111528 +#define DDR_PHY_DX8SL4DXCTL2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x54BU)) +#define DDR_PHY_DX8SL4DXCTL2_0 0x5c01152c +#define DDR_PHY_DX8SL4DXCTL2_1 0x5c11152c +#define DDR_PHY_DX8SL4IOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x54CU)) +#define DDR_PHY_DX8SL4IOCR_0 0x5c011530 +#define DDR_PHY_DX8SL4IOCR_1 0x5c111530 +#define DDR_PHY_DX8SLbOSC(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F0U)) +#define DDR_PHY_DX8SLbOSC_0 0x5c0117c0 +#define DDR_PHY_DX8SLbOSC_1 0x5c1117c0 +#define DDR_PHY_DX8SLbPLLCR0(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F1U)) +#define DDR_PHY_DX8SLbPLLCR0_0 0x5c0117c4 +#define DDR_PHY_DX8SLbPLLCR0_1 0x5c1117c4 +#define DDR_PHY_DX8SLbPLLCR1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F2U)) +#define DDR_PHY_DX8SLbPLLCR1_0 0x5c0117c8 +#define DDR_PHY_DX8SLbPLLCR1_1 0x5c1117c8 +#define DDR_PHY_DX8SLbPLLCR2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F3U)) +#define DDR_PHY_DX8SLbPLLCR2_0 0x5c0117cc +#define DDR_PHY_DX8SLbPLLCR2_1 0x5c1117cc +#define DDR_PHY_DX8SLbPLLCR3(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F4U)) +#define DDR_PHY_DX8SLbPLLCR3_0 0x5c0117d0 +#define DDR_PHY_DX8SLbPLLCR3_1 0x5c1117d0 +#define DDR_PHY_DX8SLbPLLCR4(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F5U)) +#define DDR_PHY_DX8SLbPLLCR4_0 0x5c0117d4 +#define DDR_PHY_DX8SLbPLLCR4_1 0x5c1117d4 +#define DDR_PHY_DX8SLbPLLCR5(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F6U)) +#define DDR_PHY_DX8SLbPLLCR5_0 0x5c0117d8 +#define DDR_PHY_DX8SLbPLLCR5_1 0x5c1117d8 +#define DDR_PHY_DX8SLbDQSCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F7U)) +#define DDR_PHY_DX8SLbDQSCTL_0 0x5c0117dc +#define DDR_PHY_DX8SLbDQSCTL_1 0x5c1117dc +#define DDR_PHY_DX8SLbTRNCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F8U)) +#define DDR_PHY_DX8SLbTRNCTL_0 0x5c0117e0 +#define DDR_PHY_DX8SLbTRNCTL_1 0x5c1117e0 +#define DDR_PHY_DX8SLbDDLCTL(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5F9U)) +#define DDR_PHY_DX8SLbDDLCTL_0 0x5c0117e4 +#define DDR_PHY_DX8SLbDDLCTL_1 0x5c1117e4 +#define DDR_PHY_DX8SLbDXCTL1(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5FAU)) +#define DDR_PHY_DX8SLbDXCTL1_0 0x5c0117e8 +#define DDR_PHY_DX8SLbDXCTL1_1 0x5c1117e8 +#define DDR_PHY_DX8SLbDXCTL2(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5FBU)) +#define DDR_PHY_DX8SLbDXCTL2_0 0x5c0117ec +#define DDR_PHY_DX8SLbDXCTL2_1 0x5c1117ec +#define DDR_PHY_DX8SLbIOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5FCU)) +#define DDR_PHY_DX8SLbIOCR_0 0x5c0117f0 +#define DDR_PHY_DX8SLbIOCR_1 0x5c1117f0 +#define DDR_PHY_DX4SLbIOCR(X) REG32(DDR_PHY_BASE_ADDR(X) + (4U*0x5FDU)) +#define DDR_PHY_DX4SLbIOCR_0 0x5c0117f4 +#define DDR_PHY_DX4SLbIOCR_1 0x5c1117f4 + +#endif + diff --git a/platform/devices/MX8/MX8_ddrc.h b/platform/devices/MX8/MX8_ddrc.h new file mode 100755 index 0000000..80dbb54 --- /dev/null +++ b/platform/devices/MX8/MX8_ddrc.h @@ -0,0 +1,662 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** ################################################################### +*/ + +#ifndef HW_DDRC_REGISTERS_H +#define HW_DDRC_REGISTERS_H + +//JDG change base addr for DDRC +#define DDRC_BASE_ADDR(X) (0x5c000000UL + ((U32(X) * 0x100000UL))) + +#define DDRC_MSTR(X) REG32(DDRC_BASE_ADDR(X) + 0x00U) +#define DDRC_MSTR_0 0x5c000000 +#define DDRC_MSTR_1 0x5c100000 +#define DDRC_STAT(X) REG32(DDRC_BASE_ADDR(X) + 0x04U) +#define DDRC_STAT_0 0x5c000004 +#define DDRC_STAT_1 0x5c100004 +#define DDRC_MRCTRL0(X) REG32(DDRC_BASE_ADDR(X) + 0x10U) +#define DDRC_MRCTRL0_0 0x5c000010 +#define DDRC_MRCTRL0_1 0x5c100010 +#define DDRC_MRCTRL1(X) REG32(DDRC_BASE_ADDR(X) + 0x14U) +#define DDRC_MRCTRL1_0 0x5c000014 +#define DDRC_MRCTRL1_1 0x5c100014 +#define DDRC_MRSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x18U) +#define DDRC_MRSTAT_0 0x5c000018 +#define DDRC_MRSTAT_1 0x5c100018 +#define DDRC_MRCTRL2(X) REG32(DDRC_BASE_ADDR(X) + 0x1cU) +#define DDRC_MRCTRL2_0 0x5c00001c +#define DDRC_MRCTRL2_1 0x5c10001c +#define DDRC_DERATEEN(X) REG32(DDRC_BASE_ADDR(X) + 0x20U) +#define DDRC_DERATEEN_0 0x5c000020 +#define DDRC_DERATEEN_1 0x5c100020 +#define DDRC_DERATEINT(X) REG32(DDRC_BASE_ADDR(X) + 0x24U) +#define DDRC_DERATEINT_0 0x5c000024 +#define DDRC_DERATEINT_1 0x5c100024 +#define DDRC_PWRCTL(X) REG32(DDRC_BASE_ADDR(X) + 0x30U) +#define DDRC_PWRCTL_0 0x5c000030 +#define DDRC_PWRCTL_1 0x5c100030 +#define DDRC_PWRTMG(X) REG32(DDRC_BASE_ADDR(X) + 0x34U) +#define DDRC_PWRTMG_0 0x5c000034 +#define DDRC_PWRTMG_1 0x5c100034 +#define DDRC_HWLPCTL(X) REG32(DDRC_BASE_ADDR(X) + 0x38U) +#define DDRC_HWLPCTL_0 0x5c000038 +#define DDRC_HWLPCTL_1 0x5c100038 +#define DDRC_RFSHCTL0(X) REG32(DDRC_BASE_ADDR(X) + 0x50U) +#define DDRC_RFSHCTL0_0 0x5c000050 +#define DDRC_RFSHCTL0_1 0x5c100050 +#define DDRC_RFSHCTL1(X) REG32(DDRC_BASE_ADDR(X) + 0x54U) +#define DDRC_RFSHCTL1_0 0x5c000054 +#define DDRC_RFSHCTL1_1 0x5c100054 +#define DDRC_RFSHCTL2(X) REG32(DDRC_BASE_ADDR(X) + 0x58U) +#define DDRC_RFSHCTL2_0 0x5c000058 +#define DDRC_RFSHCTL2_1 0x5c100058 +#define DDRC_RFSHCTL3(X) REG32(DDRC_BASE_ADDR(X) + 0x60U) +#define DDRC_RFSHCTL3_0 0x5c000060 +#define DDRC_RFSHCTL3_1 0x5c100060 +#define DDRC_RFSHTMG(X) REG32(DDRC_BASE_ADDR(X) + 0x64U) +#define DDRC_RFSHTMG_0 0x5c000064 +#define DDRC_RFSHTMG_1 0x5c100064 +#define DDRC_ECCCFG0(X) REG32(DDRC_BASE_ADDR(X) + 0x70U) +#define DDRC_ECCCFG0_0 0x5c000070 +#define DDRC_ECCCFG0_1 0x5c100070 +#define DDRC_ECCCFG1(X) REG32(DDRC_BASE_ADDR(X) + 0x74U) +#define DDRC_ECCCFG1_0 0x5c000074 +#define DDRC_ECCCFG1_1 0x5c100074 +#define DDRC_ECCSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x78U) +#define DDRC_ECCSTAT_0 0x5c000078 +#define DDRC_ECCSTAT_1 0x5c100078 +#define DDRC_ECCCLR(X) REG32(DDRC_BASE_ADDR(X) + 0x7cU) +#define DDRC_ECCCLR_0 0x5c00007c +#define DDRC_ECCCLR_1 0x5c10007c +#define DDRC_ECCERRCNT(X) REG32(DDRC_BASE_ADDR(X) + 0x80U) +#define DDRC_ECCERRCNT_0 0x5c000080 +#define DDRC_ECCERRCNT_1 0x5c100080 +#define DDRC_ECCCADDR0(X) REG32(DDRC_BASE_ADDR(X) + 0x84U) +#define DDRC_ECCCADDR0_0 0x5c000084 +#define DDRC_ECCCADDR0_1 0x5c100084 +#define DDRC_ECCCADDR1(X) REG32(DDRC_BASE_ADDR(X) + 0x88U) +#define DDRC_ECCCADDR1_0 0x5c000088 +#define DDRC_ECCCADDR1_1 0x5c100088 +#define DDRC_ECCCSYN0(X) REG32(DDRC_BASE_ADDR(X) + 0x8cU) +#define DDRC_ECCCSYN0_0 0x5c00008c +#define DDRC_ECCCSYN0_1 0x5c10008c +#define DDRC_ECCCSYN1(X) REG32(DDRC_BASE_ADDR(X) + 0x90U) +#define DDRC_ECCCSYN1_0 0x5c000090 +#define DDRC_ECCCSYN1_1 0x5c100090 +#define DDRC_ECCCSYN2(X) REG32(DDRC_BASE_ADDR(X) + 0x94U) +#define DDRC_ECCCSYN2_0 0x5c000094 +#define DDRC_ECCCSYN2_1 0x5c100094 +#define DDRC_ECCBITMASK0(X) REG32(DDRC_BASE_ADDR(X) + 0x98U) +#define DDRC_ECCBITMASK0_0 0x5c000098 +#define DDRC_ECCBITMASK0_1 0x5c100098 +#define DDRC_ECCBITMASK1(X) REG32(DDRC_BASE_ADDR(X) + 0x9cU) +#define DDRC_ECCBITMASK1_0 0x5c00009c +#define DDRC_ECCBITMASK1_1 0x5c10009c +#define DDRC_ECCBITMASK2(X) REG32(DDRC_BASE_ADDR(X) + 0xa0U) +#define DDRC_ECCBITMASK2_0 0x5c0000a0 +#define DDRC_ECCBITMASK2_1 0x5c1000a0 +#define DDRC_ECCUADDR0(X) REG32(DDRC_BASE_ADDR(X) + 0xa4U) +#define DDRC_ECCUADDR0_0 0x5c0000a4 +#define DDRC_ECCUADDR0_1 0x5c1000a4 +#define DDRC_ECCUADDR1(X) REG32(DDRC_BASE_ADDR(X) + 0xa8U) +#define DDRC_ECCUADDR1_0 0x5c0000a8 +#define DDRC_ECCUADDR1_1 0x5c1000a8 +#define DDRC_ECCUSYN0(X) REG32(DDRC_BASE_ADDR(X) + 0xacU) +#define DDRC_ECCUSYN0_0 0x5c0000ac +#define DDRC_ECCUSYN0_1 0x5c1000ac +#define DDRC_ECCUSYN1(X) REG32(DDRC_BASE_ADDR(X) + 0xb0U) +#define DDRC_ECCUSYN1_0 0x5c0000b0 +#define DDRC_ECCUSYN1_1 0x5c1000b0 +#define DDRC_ECCUSYN2(X) REG32(DDRC_BASE_ADDR(X) + 0xb4U) +#define DDRC_ECCUSYN2_0 0x5c0000b4 +#define DDRC_ECCUSYN2_1 0x5c1000b4 +#define DDRC_ECCPOISONADDR0(X) REG32(DDRC_BASE_ADDR(X) + 0xb8U) +#define DDRC_ECCPOISONADDR0_0 0x5c0000b8 +#define DDRC_ECCPOISONADDR0_1 0x5c1000b8 +#define DDRC_ECCPOISONADDR1(X) REG32(DDRC_BASE_ADDR(X) + 0xbcU) +#define DDRC_ECCPOISONADDR1_0 0x5c0000bc +#define DDRC_ECCPOISONADDR1_1 0x5c1000bc +#define DDRC_CRCPARCTL0(X) REG32(DDRC_BASE_ADDR(X) + 0xc0U) +#define DDRC_CRCPARCTL0_0 0x5c0000c0 +#define DDRC_CRCPARCTL0_1 0x5c1000c0 +#define DDRC_CRCPARCTL1(X) REG32(DDRC_BASE_ADDR(X) + 0xc4U) +#define DDRC_CRCPARCTL1_0 0x5c0000c4 +#define DDRC_CRCPARCTL1_1 0x5c1000c4 +#define DDRC_CRCPARCTL2(X) REG32(DDRC_BASE_ADDR(X) + 0xc8U) +#define DDRC_CRCPARCTL2_0 0x5c0000c8 +#define DDRC_CRCPARCTL2_1 0x5c1000c8 +#define DDRC_CRCPARSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0xccU) +#define DDRC_CRCPARSTAT_0 0x5c0000cc +#define DDRC_CRCPARSTAT_1 0x5c1000cc +#define DDRC_INIT0(X) REG32(DDRC_BASE_ADDR(X) + 0xd0U) +#define DDRC_INIT0_0 0x5c0000d0 +#define DDRC_INIT0_1 0x5c1000d0 +#define DDRC_INIT1(X) REG32(DDRC_BASE_ADDR(X) + 0xd4U) +#define DDRC_INIT1_0 0x5c0000d4 +#define DDRC_INIT1_1 0x5c1000d4 +#define DDRC_INIT2(X) REG32(DDRC_BASE_ADDR(X) + 0xd8U) +#define DDRC_INIT2_0 0x5c0000d8 +#define DDRC_INIT2_1 0x5c1000d8 +#define DDRC_INIT3(X) REG32(DDRC_BASE_ADDR(X) + 0xdcU) +#define DDRC_INIT3_0 0x5c0000dc +#define DDRC_INIT3_1 0x5c1000dc +#define DDRC_INIT4(X) REG32(DDRC_BASE_ADDR(X) + 0xe0U) +#define DDRC_INIT4_0 0x5c0000e0 +#define DDRC_INIT4_1 0x5c1000e0 +#define DDRC_INIT5(X) REG32(DDRC_BASE_ADDR(X) + 0xe4U) +#define DDRC_INIT5_0 0x5c0000e4 +#define DDRC_INIT5_1 0x5c1000e4 +#define DDRC_INIT6(X) REG32(DDRC_BASE_ADDR(X) + 0xe8U) +#define DDRC_INIT6_0 0x5c0000e8 +#define DDRC_INIT6_1 0x5c1000e8 +#define DDRC_INIT7(X) REG32(DDRC_BASE_ADDR(X) + 0xecU) +#define DDRC_INIT7_0 0x5c0000ec +#define DDRC_INIT7_1 0x5c1000ec +#define DDRC_DIMMCTL(X) REG32(DDRC_BASE_ADDR(X) + 0xf0U) +#define DDRC_DIMMCTL_0 0x5c0000f0 +#define DDRC_DIMMCTL_1 0x5c1000f0 +#define DDRC_RANKCTL(X) REG32(DDRC_BASE_ADDR(X) + 0xf4U) +#define DDRC_RANKCTL_0 0x5c0000f4 +#define DDRC_RANKCTL_1 0x5c1000f4 +#define DDRC_DRAMTMG0(X) REG32(DDRC_BASE_ADDR(X) + 0x100U) +#define DDRC_DRAMTMG0_0 0x5c000100 +#define DDRC_DRAMTMG0_1 0x5c100100 +#define DDRC_DRAMTMG1(X) REG32(DDRC_BASE_ADDR(X) + 0x104U) +#define DDRC_DRAMTMG1_0 0x5c000104 +#define DDRC_DRAMTMG1_1 0x5c100104 +#define DDRC_DRAMTMG2(X) REG32(DDRC_BASE_ADDR(X) + 0x108U) +#define DDRC_DRAMTMG2_0 0x5c000108 +#define DDRC_DRAMTMG2_1 0x5c100108 +#define DDRC_DRAMTMG3(X) REG32(DDRC_BASE_ADDR(X) + 0x10cU) +#define DDRC_DRAMTMG3_0 0x5c00010c +#define DDRC_DRAMTMG3_1 0x5c10010c +#define DDRC_DRAMTMG4(X) REG32(DDRC_BASE_ADDR(X) + 0x110U) +#define DDRC_DRAMTMG4_0 0x5c000110 +#define DDRC_DRAMTMG4_1 0x5c100110 +#define DDRC_DRAMTMG5(X) REG32(DDRC_BASE_ADDR(X) + 0x114U) +#define DDRC_DRAMTMG5_0 0x5c000114 +#define DDRC_DRAMTMG5_1 0x5c100114 +#define DDRC_DRAMTMG6(X) REG32(DDRC_BASE_ADDR(X) + 0x118U) +#define DDRC_DRAMTMG6_0 0x5c000118 +#define DDRC_DRAMTMG6_1 0x5c100118 +#define DDRC_DRAMTMG7(X) REG32(DDRC_BASE_ADDR(X) + 0x11cU) +#define DDRC_DRAMTMG7_0 0x5c00011c +#define DDRC_DRAMTMG7_1 0x5c10011c +#define DDRC_DRAMTMG8(X) REG32(DDRC_BASE_ADDR(X) + 0x120U) +#define DDRC_DRAMTMG8_0 0x5c000120 +#define DDRC_DRAMTMG8_1 0x5c100120 +#define DDRC_DRAMTMG9(X) REG32(DDRC_BASE_ADDR(X) + 0x124U) +#define DDRC_DRAMTMG9_0 0x5c000124 +#define DDRC_DRAMTMG9_1 0x5c100124 +#define DDRC_DRAMTMG10(X) REG32(DDRC_BASE_ADDR(X) + 0x128U) +#define DDRC_DRAMTMG10_0 0x5c000128 +#define DDRC_DRAMTMG10_1 0x5c100128 +#define DDRC_DRAMTMG11(X) REG32(DDRC_BASE_ADDR(X) + 0x12cU) +#define DDRC_DRAMTMG11_0 0x5c00012c +#define DDRC_DRAMTMG11_1 0x5c10012c +#define DDRC_DRAMTMG12(X) REG32(DDRC_BASE_ADDR(X) + 0x130U) +#define DDRC_DRAMTMG12_0 0x5c000130 +#define DDRC_DRAMTMG12_1 0x5c100130 +#define DDRC_DRAMTMG13(X) REG32(DDRC_BASE_ADDR(X) + 0x134U) +#define DDRC_DRAMTMG13_0 0x5c000134 +#define DDRC_DRAMTMG13_1 0x5c100134 +#define DDRC_DRAMTMG14(X) REG32(DDRC_BASE_ADDR(X) + 0x138U) +#define DDRC_DRAMTMG14_0 0x5c000138 +#define DDRC_DRAMTMG14_1 0x5c100138 +#define DDRC_DRAMTMG15(X) REG32(DDRC_BASE_ADDR(X) + 0x13CU) +#define DDRC_DRAMTMG15_0 0x5c00013c +#define DDRC_DRAMTMG15_1 0x5c10013c +#define DDRC_DRAMTMG16(X) REG32(DDRC_BASE_ADDR(X) + 0x140U) +#define DDRC_DRAMTMG16_0 0x5c000140 +#define DDRC_DRAMTMG16_1 0x5c100140 +// +#define DDRC_ZQCTL0(X) REG32(DDRC_BASE_ADDR(X) + 0x180U) +#define DDRC_ZQCTL0_0 0x5c000180 +#define DDRC_ZQCTL0_1 0x5c100180 +#define DDRC_ZQCTL1(X) REG32(DDRC_BASE_ADDR(X) + 0x184U) +#define DDRC_ZQCTL1_0 0x5c000184 +#define DDRC_ZQCTL1_1 0x5c100184 +#define DDRC_ZQCTL2(X) REG32(DDRC_BASE_ADDR(X) + 0x188U) +#define DDRC_ZQCTL2_0 0x5c000188 +#define DDRC_ZQCTL2_1 0x5c100188 +#define DDRC_ZQSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x18cU) +#define DDRC_ZQSTAT_0 0x5c00018c +#define DDRC_ZQSTAT_1 0x5c10018c +#define DDRC_DFITMG0(X) REG32(DDRC_BASE_ADDR(X) + 0x190U) +#define DDRC_DFITMG0_0 0x5c000190 +#define DDRC_DFITMG0_1 0x5c100190 +#define DDRC_DFITMG1(X) REG32(DDRC_BASE_ADDR(X) + 0x194U) +#define DDRC_DFITMG1_0 0x5c000194 +#define DDRC_DFITMG1_1 0x5c100194 +#define DDRC_DFILPCFG0(X) REG32(DDRC_BASE_ADDR(X) + 0x198U) +#define DDRC_DFILPCFG0_0 0x5c000198 +#define DDRC_DFILPCFG0_1 0x5c100198 +#define DDRC_DFILPCFG1(X) REG32(DDRC_BASE_ADDR(X) + 0x19cU) +#define DDRC_DFILPCFG1_0 0x5c00019c +#define DDRC_DFILPCFG1_1 0x5c10019c +#define DDRC_DFIUPD0(X) REG32(DDRC_BASE_ADDR(X) + 0x1a0U) +#define DDRC_DFIUPD0_0 0x5c0001a0 +#define DDRC_DFIUPD0_1 0x5c1001a0 +#define DDRC_DFIUPD1(X) REG32(DDRC_BASE_ADDR(X) + 0x1a4U) +#define DDRC_DFIUPD1_0 0x5c0001a4 +#define DDRC_DFIUPD1_1 0x5c1001a4 +#define DDRC_DFIUPD2(X) REG32(DDRC_BASE_ADDR(X) + 0x1a8U) +#define DDRC_DFIUPD2_0 0x5c0001a8 +#define DDRC_DFIUPD2_1 0x5c1001a8 +#define DDRC_DFIUPD3(X) REG32(DDRC_BASE_ADDR(X) + 0x1acU) // iMX8 hasn't it +#define DDRC_DFIMISC(X) REG32(DDRC_BASE_ADDR(X) + 0x1b0U) +#define DDRC_DFIMISC_0 0x5c0001b0 +#define DDRC_DFIMISC_1 0x5c1001b0 +#define DDRC_DFITMG2(X) REG32(DDRC_BASE_ADDR(X) + 0x1b4U) +#define DDRC_DFITMG2_0 0x5c0001b4 +#define DDRC_DFITMG2_1 0x5c1001b4 +#define DDRC_DFITMG3(X) REG32(DDRC_BASE_ADDR(X) + 0x1b8U) +#define DDRC_DFITMG3_0 0x5c0001b8 +#define DDRC_DFITMG3_1 0x5c1001b8 +// +#define DDRC_DBICTL(X) REG32(DDRC_BASE_ADDR(X) + 0x1c0U) +#define DDRC_DBICTL_0 0x5c0001c0 +#define DDRC_DBICTL_1 0x5c1001c0 +#define DDRC_TRAINCTL0(X) REG32(DDRC_BASE_ADDR(X) + 0x1d0U) +#define DDRC_TRAINCTL0_0 0x5c0001d0 +#define DDRC_TRAINCTL0_1 0x5c1001d0 +#define DDRC_TRAINCTL1(X) REG32(DDRC_BASE_ADDR(X) + 0x1d4U) +#define DDRC_TRAINCTL1_0 0x5c0001d4 +#define DDRC_TRAINCTL1_1 0x5c1001d4 +#define DDRC_TRAINCTL2(X) REG32(DDRC_BASE_ADDR(X) + 0x1d8U) +#define DDRC_TRAINCTL2_0 0x5c0001d8 +#define DDRC_TRAINCTL2_1 0x5c1001d8 +#define DDRC_TRAINSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x1dcU) +#define DDRC_TRAINSTAT_0 0x5c0001dc +#define DDRC_TRAINSTAT_1 0x5c1001dc +#define DDRC_ADDRMAP0(X) REG32(DDRC_BASE_ADDR(X) + 0x200U) +#define DDRC_ADDRMAP0_0 0x5c000200 +#define DDRC_ADDRMAP0_1 0x5c100200 +#define DDRC_ADDRMAP1(X) REG32(DDRC_BASE_ADDR(X) + 0x204U) +#define DDRC_ADDRMAP1_0 0x5c000204 +#define DDRC_ADDRMAP1_1 0x5c100204 +#define DDRC_ADDRMAP2(X) REG32(DDRC_BASE_ADDR(X) + 0x208U) +#define DDRC_ADDRMAP2_0 0x5c000208 +#define DDRC_ADDRMAP2_1 0x5c100208 +#define DDRC_ADDRMAP3(X) REG32(DDRC_BASE_ADDR(X) + 0x20cU) +#define DDRC_ADDRMAP3_0 0x5c00020c +#define DDRC_ADDRMAP3_1 0x5c10020c +#define DDRC_ADDRMAP4(X) REG32(DDRC_BASE_ADDR(X) + 0x210U) +#define DDRC_ADDRMAP4_0 0x5c000210 +#define DDRC_ADDRMAP4_1 0x5c100210 +#define DDRC_ADDRMAP5(X) REG32(DDRC_BASE_ADDR(X) + 0x214U) +#define DDRC_ADDRMAP5_0 0x5c000214 +#define DDRC_ADDRMAP5_1 0x5c100214 +#define DDRC_ADDRMAP6(X) REG32(DDRC_BASE_ADDR(X) + 0x218U) +#define DDRC_ADDRMAP6_0 0x5c000218 +#define DDRC_ADDRMAP6_1 0x5c100218 +#define DDRC_ADDRMAP7(X) REG32(DDRC_BASE_ADDR(X) + 0x21cU) +#define DDRC_ADDRMAP7_0 0x5c00021c +#define DDRC_ADDRMAP7_1 0x5c10021c +#define DDRC_ADDRMAP8(X) REG32(DDRC_BASE_ADDR(X) + 0x220U) +#define DDRC_ADDRMAP8_0 0x5c000220 +#define DDRC_ADDRMAP8_1 0x5c100220 +#define DDRC_ADDRMAP9(X) REG32(DDRC_BASE_ADDR(X) + 0x224U) +#define DDRC_ADDRMAP9_0 0x5c000224 +#define DDRC_ADDRMAP9_1 0x5c100224 +#define DDRC_ADDRMAP10(X) REG32(DDRC_BASE_ADDR(X) + 0x228U) +#define DDRC_ADDRMAP10_0 0x5c000228 +#define DDRC_ADDRMAP10_1 0x5c100228 +#define DDRC_ADDRMAP11(X) REG32(DDRC_BASE_ADDR(X) + 0x22cU) +#define DDRC_ADDRMAP11_0 0x5c00022c +#define DDRC_ADDRMAP11_1 0x5c10022c +// +#define DDRC_ODTCFG(X) REG32(DDRC_BASE_ADDR(X) + 0x240U) +#define DDRC_ODTCFG_0 0x5c000240 +#define DDRC_ODTCFG_1 0x5c100240 +#define DDRC_ODTMAP(X) REG32(DDRC_BASE_ADDR(X) + 0x244U) +#define DDRC_ODTMAP_0 0x5c000244 +#define DDRC_ODTMAP_1 0x5c100244 +#define DDRC_SCHED(X) REG32(DDRC_BASE_ADDR(X) + 0x250U) +#define DDRC_SCHED_0 0x5c000250 +#define DDRC_SCHED_1 0x5c100250 +#define DDRC_SCHED1(X) REG32(DDRC_BASE_ADDR(X) + 0x254U) +#define DDRC_SCHED1_0 0x5c000254 +#define DDRC_SCHED1_1 0x5c100254 +#define DDRC_PERFHPR1(X) REG32(DDRC_BASE_ADDR(X) + 0x25cU) +#define DDRC_PERFHPR1_0 0x5c00025c +#define DDRC_PERFHPR1_1 0x5c10025c +#define DDRC_PERFLPR1(X) REG32(DDRC_BASE_ADDR(X) + 0x264U) +#define DDRC_PERFLPR1_0 0x5c000264 +#define DDRC_PERFLPR1_1 0x5c100264 +#define DDRC_PERFWR1(X) REG32(DDRC_BASE_ADDR(X) + 0x26cU) +#define DDRC_PERFWR1_0 0x5c00026c +#define DDRC_PERFWR1_1 0x5c10026c +#define DDRC_PERFVPR1(X) REG32(DDRC_BASE_ADDR(X) + 0x274U) +#define DDRC_PERFVPR1_0 0x5c000274 +#define DDRC_PERFVPR1_1 0x5c100274 +// +#define DDRC_PERFVPW1(X) REG32(DDRC_BASE_ADDR(X) + 0x278U) +#define DDRC_PERFVPW1_0 0x5c000278 +#define DDRC_PERFVPW1_1 0x5c100278 +// +#define DDRC_DQMAP0(X) REG32(DDRC_BASE_ADDR(X) + 0x280U) +#define DDRC_DQMAP0_0 0x5c000280 +#define DDRC_DQMAP0_1 0x5c100280 +#define DDRC_DQMAP1(X) REG32(DDRC_BASE_ADDR(X) + 0x284U) +#define DDRC_DQMAP1_0 0x5c000284 +#define DDRC_DQMAP1_1 0x5c100284 +#define DDRC_DQMAP2(X) REG32(DDRC_BASE_ADDR(X) + 0x288U) +#define DDRC_DQMAP2_0 0x5c000288 +#define DDRC_DQMAP2_1 0x5c100288 +#define DDRC_DQMAP3(X) REG32(DDRC_BASE_ADDR(X) + 0x28cU) +#define DDRC_DQMAP3_0 0x5c00028c +#define DDRC_DQMAP3_1 0x5c10028c +#define DDRC_DQMAP4(X) REG32(DDRC_BASE_ADDR(X) + 0x290U) +#define DDRC_DQMAP4_0 0x5c000290 +#define DDRC_DQMAP4_1 0x5c100290 +#define DDRC_DQMAP5(X) REG32(DDRC_BASE_ADDR(X) + 0x294U) +#define DDRC_DQMAP5_0 0x5c000294 +#define DDRC_DQMAP5_1 0x5c100294 +#define DDRC_DBG0(X) REG32(DDRC_BASE_ADDR(X) + 0x300U) +#define DDRC_DBG0_0 0x5c000300 +#define DDRC_DBG0_1 0x5c100300 +#define DDRC_DBG1(X) REG32(DDRC_BASE_ADDR(X) + 0x304U) +#define DDRC_DBG1_0 0x5c000304 +#define DDRC_DBG1_1 0x5c100304 +#define DDRC_DBGCAM(X) REG32(DDRC_BASE_ADDR(X) + 0x308U) +#define DDRC_DBGCAM_0 0x5c000308 +#define DDRC_DBGCAM_1 0x5c100308 +#define DDRC_DBGCMD(X) REG32(DDRC_BASE_ADDR(X) + 0x30cU) +#define DDRC_DBGCMD_0 0x5c00030c +#define DDRC_DBGCMD_1 0x5c10030c +#define DDRC_DBGSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x310U) +#define DDRC_DBGSTAT_0 0x5c000310 +#define DDRC_DBGSTAT_1 0x5c100310 +// +#define DDRC_SWCTL(X) REG32(DDRC_BASE_ADDR(X) + 0x320U) +#define DDRC_SWCTL_0 0x5c000320 +#define DDRC_SWCTL_1 0x5c100320 +#define DDRC_SWSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x324U) +#define DDRC_SWSTAT_0 0x5c000324 +#define DDRC_SWSTAT_1 0x5c100324 +#define DDRC_OCPARCFG0(X) REG32(DDRC_BASE_ADDR(X) + 0x330U) +#define DDRC_OCPARCFG0_0 0x5c000330 +#define DDRC_OCPARCFG0_1 0x5c100330 +#define DDRC_OCPARCFG1(X) REG32(DDRC_BASE_ADDR(X) + 0x334U) +#define DDRC_OCPARCFG1_0 0x5c000334 +#define DDRC_OCPARCFG1_1 0x5c100334 +#define DDRC_OCPARCFG2(X) REG32(DDRC_BASE_ADDR(X) + 0x338U) +#define DDRC_OCPARCFG2_0 0x5c000338 +#define DDRC_OCPARCFG2_1 0x5c100338 +#define DDRC_OCPARCFG3(X) REG32(DDRC_BASE_ADDR(X) + 0x33cU) +#define DDRC_OCPARCFG3_0 0x5c00033c +#define DDRC_OCPARCFG3_1 0x5c10033c +#define DDRC_OCPARSTAT0(X) REG32(DDRC_BASE_ADDR(X) + 0x340U) +#define DDRC_OCPARSTAT0_0 0x5c000340 +#define DDRC_OCPARSTAT0_1 0x5c100340 +#define DDRC_OCPARSTAT1(X) REG32(DDRC_BASE_ADDR(X) + 0x344U) +#define DDRC_OCPARSTAT1_0 0x5c000344 +#define DDRC_OCPARSTAT1_1 0x5c100344 +#define DDRC_OCPARWLOG0(X) REG32(DDRC_BASE_ADDR(X) + 0x348U) +#define DDRC_OCPARWLOG0_0 0x5c000348 +#define DDRC_OCPARWLOG0_1 0x5c100348 +#define DDRC_OCPARWLOG1(X) REG32(DDRC_BASE_ADDR(X) + 0x34cU) +#define DDRC_OCPARWLOG1_0 0x5c00034c +#define DDRC_OCPARWLOG1_1 0x5c10034c +#define DDRC_OCPARWLOG2(X) REG32(DDRC_BASE_ADDR(X) + 0x350U) +#define DDRC_OCPARWLOG2_0 0x5c000350 +#define DDRC_OCPARWLOG2_1 0x5c100350 +#define DDRC_OCPARAWLOG0(X) REG32(DDRC_BASE_ADDR(X) + 0x354U) +#define DDRC_OCPARAWLOG0_0 0x5c000354 +#define DDRC_OCPARAWLOG0_1 0x5c100354 +#define DDRC_OCPARAWLOG1(X) REG32(DDRC_BASE_ADDR(X) + 0x358U) +#define DDRC_OCPARAWLOG1_0 0x5c000358 +#define DDRC_OCPARAWLOG1_1 0x5c100358 +#define DDRC_OCPARRLOG0(X) REG32(DDRC_BASE_ADDR(X) + 0x35cU) +#define DDRC_OCPARRLOG0_0 0x5c00035c +#define DDRC_OCPARRLOG0_1 0x5c10035c +#define DDRC_OCPARRLOG1(X) REG32(DDRC_BASE_ADDR(X) + 0x360U) +#define DDRC_OCPARRLOG1_0 0x5c000360 +#define DDRC_OCPARRLOG1_1 0x5c100360 +#define DDRC_OCPARARLOG0(X) REG32(DDRC_BASE_ADDR(X) + 0x364U) +#define DDRC_OCPARARLOG0_0 0x5c000364 +#define DDRC_OCPARARLOG0_1 0x5c100364 +#define DDRC_OCPARARLOG1(X) REG32(DDRC_BASE_ADDR(X) + 0x368U) +#define DDRC_OCPARARLOG1_0 0x5c000368 +#define DDRC_OCPARARLOG1_1 0x5c100368 + +#define DDRC_ECCAPSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x388U) +#define DDRC_ECCAPSTAT_0 0x5c000388 +#define DDRC_ECCAPSTAT_1 0x5c100388 +#define DDRC_PSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0x3fcU) +#define DDRC_PSTAT_0 0x5c0003fc +#define DDRC_PSTAT_1 0x5c1003fc +#define DDRC_PCCFG(X) REG32(DDRC_BASE_ADDR(X) + 0x400U) +#define DDRC_PCCFG_0 0x5c000400 +#define DDRC_PCCFG_1 0x5c100400 +#define DDRC_PCFGR_0(X) REG32(DDRC_BASE_ADDR(X) + 0x404U) +#define DDRC_PCFGR_0_0 0x5c000404 +#define DDRC_PCFGR_0_1 0x5c100404 +#define DDRC_PCFGR_1(X) REG32(DDRC_BASE_ADDR(X) + (1U*0xb0U)+0x404U) +#define DDRC_PCFGR_1_0 0x5c0004b4 +#define DDRC_PCFGR_1_1 0x5c1004b4 +#define DDRC_PCFGR_2(X) REG32(DDRC_BASE_ADDR(X) + (2U*0xb0U)+0x404U) +#define DDRC_PCFGR_2_0 0x5c000564 +#define DDRC_PCFGR_2_1 0x5c100564 +#define DDRC_PCFGR_3(X) REG32(DDRC_BASE_ADDR(X) + (3U*0xb0U)+0x404U) +#define DDRC_PCFGR_3_0 0x5c000614 +#define DDRC_PCFGR_3_1 0x5c100614 +#define DDRC_PCFGW_0(X) REG32(DDRC_BASE_ADDR(X) + 0x408U) +#define DDRC_PCFGW_0_0 0x5c000408 +#define DDRC_PCFGW_0_1 0x5c100408 +#define DDRC_PCFGW_1(X) REG32(DDRC_BASE_ADDR(X) + (1U*0xb0U)+0x408U) +#define DDRC_PCFGW_1_0 0x5c0004b8 +#define DDRC_PCFGW_1_1 0x5c1004b8 +#define DDRC_PCFGW_2(X) REG32(DDRC_BASE_ADDR(X) + (2U*0xb0U)+0x408U) +#define DDRC_PCFGW_2_0 0x5c000568 +#define DDRC_PCFGW_2_1 0x5c100568 +#define DDRC_PCFGW_3(X) REG32(DDRC_BASE_ADDR(X) + (3U*0xb0U)+0x408U) +#define DDRC_PCFGW_3_0 0x5c000618 +#define DDRC_PCFGW_3_1 0x5c100618 +#define DDRC_PCFGC_0(X) REG32(DDRC_BASE_ADDR(X) + 0x40cU) +#define DDRC_PCFGC_0_0 0x5c00040c +#define DDRC_PCFGC_0_1 0x5c10040c +#define DDRC_PCFGIDMASKCH(X) REG32(DDRC_BASE_ADDR(X) + 0x410U) +#define DDRC_PCFGIDMASKCH_0 0x5c000410 +#define DDRC_PCFGIDMASKCH_1 0x5c100410 +#define DDRC_PCFGIDVALUECH(X) REG32(DDRC_BASE_ADDR(X) + 0x414U) +#define DDRC_PCFGIDVALUECH_0 0x5c000414 +#define DDRC_PCFGIDVALUECH_1 0x5c100414 +#define DDRC_PCTRL_0(X) REG32(DDRC_BASE_ADDR(X) + 0x490U) +#define DDRC_PCTRL_0_0 0x5c000490 +#define DDRC_PCTRL_0_1 0x5c100490 +#define DDRC_PCTRL_1(X) REG32(DDRC_BASE_ADDR(X) + 0x490U + (1U*0xb0U)) +#define DDRC_PCTRL_1_0 0x5c000540 +#define DDRC_PCTRL_1_1 0x5c100540 +#define DDRC_PCTRL_2(X) REG32(DDRC_BASE_ADDR(X) + 0x490U + (2U*0xb0U)) +#define DDRC_PCTRL_2_0 0x5c0005f0 +#define DDRC_PCTRL_2_1 0x5c1005f0 +#define DDRC_PCTRL_3(X) REG32(DDRC_BASE_ADDR(X) + 0x490U + (3U*0xb0U)) +#define DDRC_PCTRL_3_0 0x5c0006a0 +#define DDRC_PCTRL_3_1 0x5c1006a0 +#define DDRC_PCFGQOS0_0(X) REG32(DDRC_BASE_ADDR(X) + 0x494U) +#define DDRC_PCFGQOS0_0_0 0x5c000494 +#define DDRC_PCFGQOS0_0_1 0x5c100494 +#define DDRC_PCFGQOS1_0(X) REG32(DDRC_BASE_ADDR(X) + 0x498U) +#define DDRC_PCFGQOS1_0_0 0x5c000498 +#define DDRC_PCFGQOS1_0_1 0x5c100498 +#define DDRC_PCFGWQOS0_0(X) REG32(DDRC_BASE_ADDR(X) + 0x49cU) +#define DDRC_PCFGWQOS0_0_0 0x5c00049c +#define DDRC_PCFGWQOS0_0_1 0x5c10049c +#define DDRC_PCFGWQOS1_0(X) REG32(DDRC_BASE_ADDR(X) + 0x4a0U) +#define DDRC_PCFGWQOS1_0_0 0x5c0004a0 +#define DDRC_PCFGWQOS1_0_1 0x5c1004a0 +#define DDRC_SARBASE0(X) REG32(DDRC_BASE_ADDR(X) + 0xf04U) +#define DDRC_SARBASE0_0 0x5c000f04 +#define DDRC_SARBASE0_1 0x5c100f04 +#define DDRC_SARSIZE0(X) REG32(DDRC_BASE_ADDR(X) + 0xf08U) +#define DDRC_SARSIZE0_0 0x5c000f08 +#define DDRC_SARSIZE0_1 0x5c100f08 +#define DDRC_SBRCTL(X) REG32(DDRC_BASE_ADDR(X) + 0xf24U) +#define DDRC_SBRCTL_0 0x5c000f24 +#define DDRC_SBRCTL_1 0x5c100f24 +#define DDRC_SBRSTAT(X) REG32(DDRC_BASE_ADDR(X) + 0xf28U) +#define DDRC_SBRSTAT_0 0x5c000f28 +#define DDRC_SBRSTAT_1 0x5c100f28 +#define DDRC_SBRWDATA0(X) REG32(DDRC_BASE_ADDR(X) + 0xf2cU) +#define DDRC_SBRWDATA0_0 0x5c000f2c +#define DDRC_SBRWDATA0_1 0x5c100f2c +#define DDRC_SBRWDATA1(X) REG32(DDRC_BASE_ADDR(X) + 0xf30U) +#define DDRC_SBRWDATA1_0 0x5c000f30 +#define DDRC_SBRWDATA1_1 0x5c100f30 +#define DDRC_PDCH(X) REG32(DDRC_BASE_ADDR(X) + 0xf34U) +#define DDRC_PDCH_0 0x5c000f34 +#define DDRC_PDCH_1 0x5c100f34 +#define DDRC_SBRSTART0(X) REG32(DDRC_BASE_ADDR(X) + 0xf38U) +#define DDRC_SBRSTART0_0 0x5c000f38 +#define DDRC_SBRSTART0_1 0x5c100f38 +#define DDRC_SBRSTART1(X) REG32(DDRC_BASE_ADDR(X) + 0xf3cU) +#define DDRC_SBRSTART1_0 0x5c000f3c +#define DDRC_SBRSTART1_1 0x5c100f3c +#define DDRC_SBRRANGE0(X) REG32(DDRC_BASE_ADDR(X) + 0xf40U) +#define DDRC_SBRRANGE0_0 0x5c000f40 +#define DDRC_SBRRANGE0_1 0x5c100f40 +#define DDRC_SBRRANGE1(X) REG32(DDRC_BASE_ADDR(X) + 0xf44U) +#define DDRC_SBRRANGE1_0 0x5c000f44 +#define DDRC_SBRRANGE1_1 0x5c100f44 + +#define DDRC_PCFGW_0_0_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(0))) +#define DDRC_PCFGW_0_1_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(1))) +#define DDRC_PCFGW_0_2_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(2))) +#define DDRC_PCFGW_0_3_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(3))) + +#define DDRC_MRCTRL1_0_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(0))) +#define DDRC_MRCTRL1_1_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(1))) +#define DDRC_MRCTRL1_2_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(2))) +#define DDRC_MRCTRL1_3_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(3))) + + +// SHADOW registers + +#define DDRC_DERATEEN_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2020U) +#define DDRC_DERATEEN_SHADOW_0 0x5c002020 +#define DDRC_DERATEEN_SHADOW_1 0x5c102020 +#define DDRC_DERATEINT_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2024U) +#define DDRC_DERATEINT_SHADOW_0 0x5c002024 +#define DDRC_DERATEINT_SHADOW_1 0x5c102024 +#define DDRC_RFSHCTL0_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2050U) +#define DDRC_RFSHCTL0_SHADOW_0 0x5c002050 +#define DDRC_RFSHCTL0_SHADOW_1 0x5c102050 +#define DDRC_RFSHTMG_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2064U) +#define DDRC_RFSHTMG_SHADOW_0 0x5c002064 +#define DDRC_RFSHTMG_SHADOW_1 0x5c102064 +#define DDRC_INIT3_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x20dcU) +#define DDRC_INIT3_SHADOW_0 0x5c0020dc +#define DDRC_INIT3_SHADOW_1 0x5c1020dc +#define DDRC_INIT4_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x20e0U) +#define DDRC_INIT4_SHADOW_0 0x5c0020e0 +#define DDRC_INIT4_SHADOW_1 0x5c1020e0 +#define DDRC_INIT6_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x20e8U) +#define DDRC_INIT6_SHADOW_0 0x5c0020e8 +#define DDRC_INIT6_SHADOW_1 0x5c1020e8 +#define DDRC_INIT7_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x20ecU) +#define DDRC_INIT7_SHADOW_0 0x5c0020ec +#define DDRC_INIT7_SHADOW_1 0x5c1020ec +#define DDRC_DRAMTMG0_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2100U) +#define DDRC_DRAMTMG0_SHADOW_0 0x5c002100 +#define DDRC_DRAMTMG0_SHADOW_1 0x5c102100 +#define DDRC_DRAMTMG1_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2104U) +#define DDRC_DRAMTMG1_SHADOW_0 0x5c002104 +#define DDRC_DRAMTMG1_SHADOW_1 0x5c102104 +#define DDRC_DRAMTMG2_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2108U) +#define DDRC_DRAMTMG2_SHADOW_0 0x5c002108 +#define DDRC_DRAMTMG2_SHADOW_1 0x5c102108 +#define DDRC_DRAMTMG3_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x210cU) +#define DDRC_DRAMTMG3_SHADOW_0 0x5c00210c +#define DDRC_DRAMTMG3_SHADOW_1 0x5c10210c +#define DDRC_DRAMTMG4_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2110U) +#define DDRC_DRAMTMG4_SHADOW_0 0x5c002110 +#define DDRC_DRAMTMG4_SHADOW_1 0x5c102110 +#define DDRC_DRAMTMG5_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2114U) +#define DDRC_DRAMTMG5_SHADOW_0 0x5c002114 +#define DDRC_DRAMTMG5_SHADOW_1 0x5c102114 +#define DDRC_DRAMTMG6_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2118U) +#define DDRC_DRAMTMG6_SHADOW_0 0x5c002118 +#define DDRC_DRAMTMG6_SHADOW_1 0x5c102118 +#define DDRC_DRAMTMG7_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x211cU) +#define DDRC_DRAMTMG7_SHADOW_0 0x5c00211c +#define DDRC_DRAMTMG7_SHADOW_1 0x5c10211c +#define DDRC_DRAMTMG8_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2120U) +#define DDRC_DRAMTMG8_SHADOW_0 0x5c002120 +#define DDRC_DRAMTMG8_SHADOW_1 0x5c102120 +#define DDRC_DRAMTMG9_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2124U) +#define DDRC_DRAMTMG9_SHADOW_0 0x5c002124 +#define DDRC_DRAMTMG9_SHADOW_1 0x5c102124 +#define DDRC_DRAMTMG10_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2128U) +#define DDRC_DRAMTMG10_SHADOW_0 0x5c002128 +#define DDRC_DRAMTMG10_SHADOW_1 0x5c102128 +#define DDRC_DRAMTMG11_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x212cU) +#define DDRC_DRAMTMG11_SHADOW_0 0x5c00212c +#define DDRC_DRAMTMG11_SHADOW_1 0x5c10212c +#define DDRC_DRAMTMG12_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2130U) +#define DDRC_DRAMTMG12_SHADOW_0 0x5c002130 +#define DDRC_DRAMTMG12_SHADOW_1 0x5c102130 +#define DDRC_DRAMTMG13_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2134U) +#define DDRC_DRAMTMG13_SHADOW_0 0x5c002134 +#define DDRC_DRAMTMG13_SHADOW_1 0x5c102134 +#define DDRC_DRAMTMG14_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2138U) +#define DDRC_DRAMTMG14_SHADOW_0 0x5c002138 +#define DDRC_DRAMTMG14_SHADOW_1 0x5c102138 +#define DDRC_DRAMTMG15_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x213CU) +#define DDRC_DRAMTMG15_SHADOW_0 0x5c00213c +#define DDRC_DRAMTMG15_SHADOW_1 0x5c10213c +#define DDRC_DRAMTMG16_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2140U) +#define DDRC_DRAMTMG16_SHADOW_0 0x5c002140 +#define DDRC_DRAMTMG16_SHADOW_1 0x5c102140 +#define DDRC_ZQCTL0_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2180U) +#define DDRC_ZQCTL0_SHADOW_0 0x5c002180 +#define DDRC_ZQCTL0_SHADOW_1 0x5c102180 +#define DDRC_DFITMG0_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2190U) +#define DDRC_DFITMG0_SHADOW_0 0x5c002190 +#define DDRC_DFITMG0_SHADOW_1 0x5c102190 +#define DDRC_DFITMG1_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2194U) +#define DDRC_DFITMG1_SHADOW_0 0x5c002194 +#define DDRC_DFITMG1_SHADOW_1 0x5c102194 +#define DDRC_DFITMG2_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x21b4U) +#define DDRC_DFITMG2_SHADOW_0 0x5c0021b4 +#define DDRC_DFITMG2_SHADOW_1 0x5c1021b4 +#define DDRC_DFITMG3_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x21b8U) +#define DDRC_DFITMG3_SHADOW_0 0x5c0021b8 +#define DDRC_DFITMG3_SHADOW_1 0x5c1021b8 +#define DDRC_ODTCFG_SHADOW(X) REG32(DDRC_BASE_ADDR(X) + 0x2240U) +#define DDRC_ODTCFG_SHADOW_0 0x5c002240 +#define DDRC_ODTCFG_SHADOW_1 0x5c102240 + +#endif + diff --git a/platform/devices/MX8/MX8_dma3.h b/platform/devices/MX8/MX8_dma3.h new file mode 100755 index 0000000..8a88bb9 --- /dev/null +++ b/platform/devices/MX8/MX8_dma3.h @@ -0,0 +1,180 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_DMA_REGISTERS_H +#define HW_DMA_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< offset: 0x0 */ + __I uint32_t MP_ES; /**< offset: 0x4 */ + uint8_t RESERVED_0[4]; + __I uint32_t MP_HRS; /**< offset: 0xC */ + uint8_t RESERVED_1[240]; + __IO uint32_t CH_GRPRI[32]; /**< offset: 0x100 */ + uint8_t RESERVED_2[65152]; + struct { /**< offset: 0x10000 */ + __IO uint32_t CH_CSR; /**< offset: 0x0 */ + __IO uint32_t CH_ES; /**< offset: 0x4 */ + __IO uint32_t CH_INT; /**< offset: 0x8 */ + __IO uint32_t CH_SBR; /**< offset: 0xC */ + __IO uint32_t CH_PRI; /**< offset: 0x10 */ + uint8_t RESERVED_3[12]; + __IO uint32_t TCD_SADDR; /**< offset: 0x20 */ + __IO uint16_t TCD_SOFF; /**< offset: 0x24 */ + __IO uint16_t TCD_ATTR; /**< offset: 0x26 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< offset: 0x28 */ + __IO uint32_t TCD_SLAST_SDA; /**< offset: 0x2C */ + __IO uint32_t TCD_DADDR; /**< offset: 0x30 */ + __IO uint16_t TCD_DOFF; /**< offset: 0x34 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< offset: 0x36 */ + __IO uint32_t TCD_DLAST_SGA; /**< offset: 0x38 */ + __IO uint16_t TCD_CSR; /**< offset: 0x3C */ + __IO uint16_t TCD_BITER_ELINKNO; /**< offset: 0x3E */ + uint8_t RESERVED_4[65472]; + } CH[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control Register */ +#define DMA_MP_CSR_EBW_MASK (0x00000001U) +#define DMA_MP_CSR_EBW_SHIFT (0U) +#define DMA_MP_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EBW_SHIFT)) & DMA_MP_CSR_EBW_MASK) +#define DMA_MP_CSR_EDBG_MASK (0x00000002U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) +#define DMA_MP_CSR_ERCA_MASK (0x00000004U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) +#define DMA_MP_CSR_HAE_MASK (0x00000010U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) +#define DMA_MP_CSR_HALT_MASK (0x00000020U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) +#define DMA_MP_CSR_ECL_MASK (0x00000040U) +#define DMA_MP_CSR_ECL_SHIFT (6U) +#define DMA_MP_CSR_ECL(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECL_SHIFT)) & DMA_MP_CSR_ECL_MASK) +#define DMA_MP_CSR_EMI_MASK (0x00000080U) +#define DMA_MP_CSR_EMI_SHIFT (7U) +#define DMA_MP_CSR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EMI_SHIFT)) & DMA_MP_CSR_EMI_MASK) +#define DMA_MP_CSR_ECX_MASK (0x00000100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) +#define DMA_MP_CSR_CX_MASK (0x00000200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) +#define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) + +/*! @name GRPRI - Channel Arbitration Group */ +#define DMA_CH_GRPRI_GRPRI_MASK (0x0000001FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_GRPRI_GRPRI_SHIFT)) & DMA_GRPRI_GRPRI_MASK) + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Peripheral DMA1 base pointer */ +#define DMA1 ((DMA_Type *)DMA1_BASE) +/** Peripheral DMA2 base pointer */ +#define DMA2 ((DMA_Type *)DMA2_BASE) +/** Peripheral DMA3 base pointer */ +#define DMA3 ((DMA_Type *)DMA3_BASE) +/** Peripheral DMA4 base pointer */ +#define DMA4 ((DMA_Type *)DMA4_BASE) +/** Peripheral DMA5 base pointer */ +#define DMA5 ((DMA_Type *)DMA5_BASE) +/** Peripheral DMA6 base pointer */ +#define DMA6 ((DMA_Type *)DMA6_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE, \ + DMA1_BASE, \ + DMA2_BASE, \ + DMA3_BASE, \ + DMA4_BASE, \ + DMA5_BASE, \ + DMA6_BASE} +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0, \ + DMA1, \ + DMA2, \ + DMA3, \ + DMA4, \ + DMA5, \ + DMA6} + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + +#endif /* HW_DMA_REGISTERS_H */ diff --git a/platform/devices/MX8/MX8_drc.h b/platform/devices/MX8/MX8_drc.h new file mode 100755 index 0000000..04d2db6 --- /dev/null +++ b/platform/devices/MX8/MX8_drc.h @@ -0,0 +1,242 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2018 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_DRC_REGISTERS_H +#define HW_DRC_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- DRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DRC_Peripheral_Access_Layer DRC Peripheral Access Layer + * @{ + */ +typedef struct { + uint32_t mstr; + uint32_t derateen; + uint32_t derateint; + uint32_t rfshctl0; + uint32_t rfshtmg; + uint32_t init0; + uint32_t init1; + uint32_t init3; + uint32_t init4; + uint32_t init5; + uint32_t init6; + uint32_t init7; + uint32_t rankctl; + uint32_t dramtmg0; + uint32_t dramtmg1; + uint32_t dramtmg2; + uint32_t dramtmg3; + uint32_t dramtmg4; + uint32_t dramtmg5; + uint32_t dramtmg6; + uint32_t dramtmg7; + uint32_t dramtmg8; + uint32_t dramtmg9; + uint32_t dramtmg11; + uint32_t dramtmg12; + uint32_t dramtmg13; + uint32_t dramtmg14; + uint32_t zqctl0; + uint32_t zqctl1; + uint32_t dfitmg0; + uint32_t dfitmg1; + uint32_t dfitmg2; + uint32_t dfitmg3; + uint32_t dfimisc; + uint32_t dfiupd0; + uint32_t dfiupd1; + uint32_t dfiupd2; + uint32_t addrmap0; + uint32_t addrmap1; + uint32_t addrmap2; + uint32_t addrmap3; + uint32_t addrmap4; + uint32_t addrmap5; + uint32_t addrmap6; + uint32_t addrmap7; + uint32_t addrmap8; + uint32_t ecccfg0; + uint32_t dbictl; + uint32_t odtcfg; + uint32_t odtmap; + uint32_t sched; + uint32_t pctrl_0; + uint32_t hwlpctl; + uint32_t dfilpcfg0; + uint32_t dfitmg0_shadow; + uint32_t pwrctl; + uint32_t pwrtmg; + uint32_t gpr_qchan; +} ddrc; + +typedef struct{ + uint32_t dx0gcr0; + uint32_t dx1gcr0; + uint32_t dx2gcr0; + uint32_t dx3gcr0; + uint32_t dx4gcr0; + uint32_t dx0gcr1; + uint32_t dx1gcr1; + uint32_t dx2gcr1; + uint32_t dx3gcr1; + uint32_t dx4gcr1; + uint32_t dx2gcr2; + uint32_t dx3gcr2; + uint32_t dx4gcr2; + uint32_t dx2gcr3; + uint32_t dx3gcr3; + uint32_t dx4gcr3; + uint32_t dcr; + uint32_t pgcr8; + uint32_t dx0dqmap0; + uint32_t dx0dqmap1; + uint32_t dx1dqmap0; + uint32_t dx1dqmap1; + uint32_t dx2dqmap0; + uint32_t dx2dqmap1; + uint32_t dx3dqmap0; + uint32_t dx3dqmap1; + uint32_t dx4dqmap0; + uint32_t dx4dqmap1; + uint32_t catr0; + uint32_t catr1; + uint32_t pgcr0; + uint32_t pgcr1; + uint32_t pgcr2; + uint32_t pgcr3; + uint32_t pgcr4; + uint32_t pgcr5; + uint32_t pgcr6; + uint32_t ptr0; + uint32_t ptr1; + uint32_t pllcr0; + uint32_t dxccr; + uint32_t dx8sl0pllcr0; + uint32_t dx8sl1pllcr0; + uint32_t dx8sl2pllcr0; + uint32_t zqcr; + uint32_t zq0pr0; + uint32_t zq1pr0; + uint32_t zq0dr0; + uint32_t zq0dr1; + uint32_t zq1dr0; + uint32_t zq1dr1; + uint32_t mr0; + uint32_t mr1; + uint32_t mr2; + uint32_t mr3; + uint32_t mr4; + uint32_t mr5; + uint32_t mr6; + uint32_t mr11; + uint32_t mr13; + uint32_t mr22; + uint32_t mr12; + uint32_t mr14; + uint32_t dtpr0; + uint32_t dtpr1; + uint32_t dtpr2; + uint32_t dtpr3; + uint32_t dtpr4; + uint32_t dtpr5; + uint32_t ptr2; + uint32_t ptr3; + uint32_t ptr4; + uint32_t ptr5; + uint32_t ptr6; + uint32_t rankidr; + uint32_t odtcr; + uint32_t aciocr0; + uint32_t aciocr1; + uint32_t aciocr2; + uint32_t aciocr3; + uint32_t aciocr5; + uint32_t riocr2; + uint32_t riocr5; + uint32_t iovcr0; + uint32_t vtcr0; + uint32_t vtcr1; + uint32_t dx0gcr5; + uint32_t dx1gcr5; + uint32_t dx2gcr5; + uint32_t dx3gcr5; + uint32_t dx4gcr5; + uint32_t dx0gcr4; + uint32_t dx1gcr4; + uint32_t dx2gcr4; + uint32_t dx3gcr4; + uint32_t dx4gcr4; + uint32_t dqsdr0; + uint32_t dqsdr1; + uint32_t dqsdr2; + uint32_t bistar1; + uint32_t bistar2; + uint32_t bistar4; + uint32_t dtcr0; + uint32_t dtcr1; + uint32_t dx8slbdxctl2; + uint32_t dx8slbiocr; + uint32_t aclcdlr; + uint32_t acbdlr3; + uint32_t acbdlr6; + uint32_t acbdlr7; + uint32_t acbdlr8; + uint32_t acbdlr9; +} ddr_phy; + +#define MR11_ADDR 0xB + +/*! + * @} + */ /* end of group DRC_Peripheral_Access_Layer */ + +#endif /* HW_DRC_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_drc_perf.h b/platform/devices/MX8/MX8_drc_perf.h new file mode 100755 index 0000000..6a3d908 --- /dev/null +++ b/platform/devices/MX8/MX8_drc_perf.h @@ -0,0 +1,65 @@ +/* +** ################################################################### +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** ################################################################### +*/ + +#ifndef HW_DRC_PERF_REGISTERS_H +#define HW_DRC_PERF_REGISTERS_H + +#define DRC_PERF_COUNTER_BASE_ADDR(X) (0x5c000000U + (((X) * 0x100000U) + 0x20000U)) + +#define DRC_PERF_COUNTER_0_CR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x00U) +#define DRC_PERF_COUNTER_1_CR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x04U) +#define DRC_PERF_COUNTER_2_CR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x08U) +#define DRC_PERF_COUNTER_3_CR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x0cU) +#define DRC_PERF_COUNTER_0_DR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x20U) +#define DRC_PERF_COUNTER_1_DR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x24U) +#define DRC_PERF_COUNTER_2_DR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x28U) +#define DRC_PERF_COUNTER_3_DR(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x2cU) +#define DRC_PERF_COUNTER_MRR_0_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x40U) +#define DRC_PERF_COUNTER_MRR_1_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x44U) +#define DRC_PERF_COUNTER_MRR_2_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x48U) +#define DRC_PERF_COUNTER_MRR_3_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x4cU) +#define DRC_PERF_COUNTER_MRR_4_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x50U) +#define DRC_PERF_COUNTER_MRR_5_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x54U) +#define DRC_PERF_COUNTER_MRR_6_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x58U) +#define DRC_PERF_COUNTER_MRR_7_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x5cU) +#define DRC_PERF_COUNTER_MRR_8_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x60U) +#define DRC_PERF_COUNTER_MRR_9_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x64U) +#define DRC_PERF_COUNTER_MRR_10_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x68U) +#define DRC_PERF_COUNTER_MRR_11_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x6cU) +#define DRC_PERF_COUNTER_MRR_12_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x70U) +#define DRC_PERF_COUNTER_MRR_13_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x74U) +#define DRC_PERF_COUNTER_MRR_14_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x78U) +#define DRC_PERF_COUNTER_MRR_15_DATA(X) REG32(DRC_PERF_COUNTER_BASE_ADDR(X) + 0x7cU) + +#endif + diff --git a/platform/devices/MX8/MX8_dsc.h b/platform/devices/MX8/MX8_dsc.h new file mode 100755 index 0000000..3894616 --- /dev/null +++ b/platform/devices/MX8/MX8_dsc.h @@ -0,0 +1,1083 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for the DSC +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file MX8_dsc.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for the DSC + * + * CMSIS Peripheral Access Layer for the DSC + */ + +#ifndef HW_DSC_REGISTERS_H +#define HW_DSC_REGISTERS_H /**< Symbol preventing repeated inclusion */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +#define DSC_MAX_PD 8 //!< Max number of power domains + +/* ---------------------------------------------------------------------------- + -- DSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSC_Peripheral_Access_Layer DSC Peripheral Access Layer + * @{ + */ + +/** DSC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0 */ + __IO uint32_t RW; /**< Reset Control: MSlice and CSlice resetn bits, offset: 0x0 */ + __IO uint32_t SET; /**< Reset Control: MSlice and CSlice resetn bits, offset: 0x4 */ + __IO uint32_t CLR; /**< Reset Control: MSlice and CSlice resetn bits, offset: 0x8 */ + __IO uint32_t TOG; /**< Reset Control: MSlice and CSlice resetn bits, offset: 0xC */ + } RST_CTRL_SLICE_RSTN[3]; + struct { /* offset: 0x30 */ + __IO uint32_t RW; /**< Reset Control: Clock Root reset bits., offset: 0x30 */ + __IO uint32_t SET; /**< Reset Control: Clock Root reset bits., offset: 0x34 */ + __IO uint32_t CLR; /**< Reset Control: Clock Root reset bits., offset: 0x38 */ + __IO uint32_t TOG; /**< Reset Control: Clock Root reset bits., offset: 0x3C */ + } RST_CTRL_CR_RSTN; + struct { /* offset: 0x40 */ + __IO uint32_t RW; /**< Reset Control: Subsystem resets, offset: 0x40 */ + __IO uint32_t SET; /**< Reset Control: Subsystem resets, offset: 0x44 */ + __IO uint32_t CLR; /**< Reset Control: Subsystem resets, offset: 0x48 */ + __IO uint32_t TOG; /**< Reset Control: Subsystem resets, offset: 0x4C */ + } RST_CTRL_SS_RSTN; + uint8_t RESERVED_0[176]; + struct { /* offset: 0x100 */ + __IO uint32_t RW; /**< Reset Control: MSlice and CSlice select functional clock mux bits., offset: 0x100 */ + __IO uint32_t SET; /**< Reset Control: MSlice and CSlice select functional clock mux bits., offset: 0x104 */ + __IO uint32_t CLR; /**< Reset Control: MSlice and CSlice select functional clock mux bits., offset: 0x108 */ + __IO uint32_t TOG; /**< Reset Control: MSlice and CSlice select functional clock mux bits., offset: 0x10C */ + } RST_CTRL_SLICE_SFCM[3]; + struct { /* offset: 0x130 */ + __IO uint32_t RW; /**< Reset Control: Select Functional Clock mux for root clocks., offset: 0x130 */ + __IO uint32_t SET; /**< Reset Control: Select Functional Clock mux for root clocks., offset: 0x134 */ + __IO uint32_t CLR; /**< Reset Control: Select Functional Clock mux for root clocks., offset: 0x138 */ + __IO uint32_t TOG; /**< Reset Control: Select Functional Clock mux for root clocks., offset: 0x13C */ + } RST_CTRL_CR_SFCM; + uint8_t RESERVED_1[192]; + struct { /* offset: 0x200 */ + __IO uint32_t RW; /**< Reset Control: Mslice and Cslice Start Functional Clock bits, offset: 0x200 */ + __IO uint32_t SET; /**< Reset Control: Mslice and Cslice Start Functional Clock bits, offset: 0x204 */ + __IO uint32_t CLR; /**< Reset Control: Mslice and Cslice Start Functional Clock bits, offset: 0x208 */ + __IO uint32_t TOG; /**< Reset Control: Mslice and Cslice Start Functional Clock bits, offset: 0x20C */ + } RST_CTRL_SLICE_SFC[3]; + struct { /* offset: 0x230 */ + __IO uint32_t RW; /**< Reset Control: Start Functional Clock bits for root clocks., offset: 0x230 */ + __IO uint32_t SET; /**< Reset Control: Start Functional Clock bits for root clocks., offset: 0x234 */ + __IO uint32_t CLR; /**< Reset Control: Start Functional Clock bits for root clocks., offset: 0x238 */ + __IO uint32_t TOG; /**< Reset Control: Start Functional Clock bits for root clocks., offset: 0x23C */ + } RST_CTRL_CR_SFC; + uint8_t RESERVED_2[192]; + struct { /* offset: 0x300 */ + __IO uint32_t RW; /**< Reset Control: Enable for the reset clock., offset: 0x300 */ + __IO uint32_t SET; /**< Reset Control: Enable for the reset clock., offset: 0x304 */ + __IO uint32_t CLR; /**< Reset Control: Enable for the reset clock., offset: 0x308 */ + __IO uint32_t TOG; /**< Reset Control: Enable for the reset clock., offset: 0x30C */ + } RST_CTRL_RESET_CLK_EN; + uint8_t RESERVED_3[240]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t RW; /**< Power domain controls, array offset: 0x400, array step: 0x10 */ + __IO uint32_t SET; /**< Power domain controls, array offset: 0x404, array step: 0x10 */ + __IO uint32_t CLR; /**< Power domain controls, array offset: 0x408, array step: 0x10 */ + __IO uint32_t TOG; /**< Power domain controls, array offset: 0x40C, array step: 0x10 */ + } POWER_CTRL[6]; + uint8_t RESERVED_4[160]; + struct { /* offset: 0x500, array step: 0x10 */ + __IO uint32_t RW; /**< General purpose control register bits., array offset: 0x500, array step: 0x10 */ + __IO uint32_t SET; /**< General purpose control register bits., array offset: 0x504, array step: 0x10 */ + __IO uint32_t CLR; /**< General purpose control register bits., array offset: 0x508, array step: 0x10 */ + __IO uint32_t TOG; /**< General purpose control register bits., array offset: 0x50C, array step: 0x10 */ + } GPR_CTRL[FSL_FEATURE_DSC_GPR_CTRL_CNT]; + uint32_t RESERVED_5[64 - (4 * FSL_FEATURE_DSC_GPR_CTRL_CNT)]; + struct { /* offset: 0x600, array step: 0x10 */ + __I uint32_t RW; /**< General purpose status bits., array offset: 0x600, array step: 0x10 */ + __I uint32_t SET; /**< General purpose status bits., array offset: 0x604, array step: 0x10 */ + __I uint32_t CLR; /**< General purpose status bits., array offset: 0x608, array step: 0x10 */ + __I uint32_t TOG; /**< General purpose status bits., array offset: 0x60C, array step: 0x10 */ + } GPR_STAT[3]; + uint8_t RESERVED_6[208]; + struct { /* offset: 0x700 */ + __IO uint32_t RW; /**< IRQ mask register for DSC interrupts., offset: 0x700 */ + __IO uint32_t SET; /**< IRQ mask register for DSC interrupts., offset: 0x704 */ + __IO uint32_t CLR; /**< IRQ mask register for DSC interrupts., offset: 0x708 */ + __IO uint32_t TOG; /**< IRQ mask register for DSC interrupts., offset: 0x70C */ + } IRQ_MASK_DSC; + struct { /* offset: 0x710 */ + __IO uint32_t RW; /**< IRQ mask register for Subsystem interrupts., offset: 0x710 */ + __IO uint32_t SET; /**< IRQ mask register for Subsystem interrupts., offset: 0x714 */ + __IO uint32_t CLR; /**< IRQ mask register for Subsystem interrupts., offset: 0x718 */ + __IO uint32_t TOG; /**< IRQ mask register for Subsystem interrupts., offset: 0x71C */ + } IRQ_MASK_SUBSYS; + uint8_t RESERVED_7[224]; + struct { /* offset: 0x800 */ + __I uint32_t RW; /**< IRQ masked status register for DSC interrupts., offset: 0x800 */ + __I uint32_t SET; /**< IRQ masked status register for DSC interrupts., offset: 0x804 */ + __I uint32_t CLR; /**< IRQ masked status register for DSC interrupts., offset: 0x808 */ + __I uint32_t TOG; /**< IRQ masked status register for DSC interrupts., offset: 0x80C */ + } IRQ_MASK_STATUS_DSC; + struct { /* offset: 0x810 */ + __I uint32_t RW; /**< IRQ masked status register for Subsystem interrupts., offset: 0x810 */ + __I uint32_t SET; /**< IRQ masked status register for Subsystem interrupts., offset: 0x814 */ + __I uint32_t CLR; /**< IRQ masked status register for Subsystem interrupts., offset: 0x818 */ + __I uint32_t TOG; /**< IRQ masked status register for Subsystem interrupts., offset: 0x81C */ + } IRQ_MASK_STATUS_SUBSYS; + uint8_t RESERVED_8[224]; + struct { /* offset: 0x900 */ + __IO uint32_t RW; /**< IRQ non-masked status register for DSC interrupts., offset: 0x900 */ + __IO uint32_t SET; /**< IRQ non-masked status register for DSC interrupts., offset: 0x904 */ + __IO uint32_t CLR; /**< IRQ non-masked status register for DSC interrupts., offset: 0x908 */ + __IO uint32_t TOG; /**< IRQ non-masked status register for DSC interrupts., offset: 0x90C */ + } IRQ_NONMASK_STATUS_DSC; + struct { /* offset: 0x910 */ + __I uint32_t RW; /**< IRQ non-masked status register for Subsystem interrupts., offset: 0x910 */ + __I uint32_t SET; /**< IRQ non-masked status register for Subsystem interrupts., offset: 0x914 */ + __I uint32_t CLR; /**< IRQ non-masked status register for Subsystem interrupts., offset: 0x918 */ + __I uint32_t TOG; /**< IRQ non-masked status register for Subsystem interrupts., offset: 0x91C */ + } IRQ_NONMASK_STATUS_SUBSYS; + uint8_t RESERVED_9[224]; + struct { /* offset: 0xA00 */ + __IO uint32_t RW; /**< Analog Interface Control Registers, offset: 0xA00 */ + __IO uint32_t SET; /**< Analog Interface Control Registers, offset: 0xA04 */ + __IO uint32_t CLR; /**< Analog Interface Control Registers, offset: 0xA08 */ + __IO uint32_t TOG; /**< Analog Interface Control Registers, offset: 0xA0C */ + } AI_CTRL; + struct { /* offset: 0xA10 */ + __IO uint32_t RW; /**< Analog Interface Registers, offset: 0xA10 */ + __IO uint32_t SET; /**< Analog Interface Registers, offset: 0xA14 */ + __IO uint32_t CLR; /**< Analog Interface Registers, offset: 0xA18 */ + __IO uint32_t TOG; /**< Analog Interface Registers, offset: 0xA1C */ + } AI_WR_DATA; + struct { /* offset: 0xA20 */ + __IO uint32_t RW; /**< Analog Interface Registers, offset: 0xA20 */ + __IO uint32_t SET; /**< Analog Interface Registers, offset: 0xA24 */ + __IO uint32_t CLR; /**< Analog Interface Registers, offset: 0xA28 */ + __IO uint32_t TOG; /**< Analog Interface Registers, offset: 0xA2C */ + } AI_TOGGLE0; + struct { /* offset: 0xA30 */ + __IO uint32_t RW; /**< Analog Interface Registers, offset: 0xA30 */ + __IO uint32_t SET; /**< Analog Interface Registers, offset: 0xA34 */ + __IO uint32_t CLR; /**< Analog Interface Registers, offset: 0xA38 */ + __IO uint32_t TOG; /**< Analog Interface Registers, offset: 0xA3C */ + } AI_TOGGLE1; + struct { /* offset: 0xA40 - NOT SCT Type*/ + __I uint32_t RW; /**< Analog Interface Registers, offset: 0xA40 */ + __I uint32_t SET; /**< Analog Interface Registers, offset: 0xA44 */ + __I uint32_t CLR; /**< Analog Interface Registers, offset: 0xA48 */ + __I uint32_t TOG; /**< Analog Interface Registers, offset: 0xA4C */ + } AI_DONE_TOGGLE0; + struct { /* offset: 0xA50 - NOT SCT Type*/ + __I uint32_t RW; /**< Analog Interface Registers, offset: 0xA50 */ + __I uint32_t SET; /**< Analog Interface Registers, offset: 0xA54 */ + __I uint32_t CLR; /**< Analog Interface Registers, offset: 0xA58 */ + __I uint32_t TOG; /**< Analog Interface Registers, offset: 0xA5C */ + } AI_DONE_TOGGLE1; + struct { /* offset: 0xA60 - NOT SCT Type*/ + __I uint32_t RW; /**< Analog Interface Registers, offset: 0xA60 */ + __I uint32_t SET; /**< Analog Interface Registers, offset: 0xA64 */ + __I uint32_t CLR; /**< Analog Interface Registers, offset: 0xA68 */ + __I uint32_t TOG; /**< Analog Interface Registers, offset: 0xA6C */ + } AI_RD_DATA; + struct { /* offset: 0xA70 - NOT SCT type*/ + __I uint32_t RW; /**< Analog Interface Registers, offset: 0xA70 */ + __I uint32_t SET; /**< Analog Interface Registers, offset: 0xA74 */ + __I uint32_t CLR; /**< Analog Interface Registers, offset: 0xA78 */ + __I uint32_t TOG; /**< Analog Interface Registers, offset: 0xA7C */ + } AI_BUSY0; + struct { /* offset: 0xA80 - NOT SCT type*/ + __I uint32_t RW; /**< Analog Interface Registers, offset: 0xA80 */ + __I uint32_t SET; /**< Analog Interface Registers, offset: 0xA84 */ + __I uint32_t CLR; /**< Analog Interface Registers, offset: 0xA88 */ + __I uint32_t TOG; /**< Analog Interface Registers, offset: 0xA8C */ + } AI_BUSY1; + + uint8_t RESERVED_10[112]; + struct { /* offset: 0xB00 */ + __IO uint32_t RW; /**< LOCKOUT Register, offset: 0xB00 */ + __IO uint32_t SET; /**< LOCKOUT Register, offset: 0xB04 */ + __IO uint32_t CLR; /**< LOCKOUT Register, offset: 0xB08 */ + __IO uint32_t TOG; /**< LOCKOUT Register, offset: 0xB0C */ + } LOCKOUT; + uint8_t RESERVED_11[8432]; + /**< Single small clock root divider slices (divide by 31)., array offset: 0x2C00, array step: 0x4 */ + __IO uint32_t SSSLICE_CTRL[FSL_FEATURE_DSC_SSSLICE_CNT]; + uint32_t RESERVED_12[256 - FSL_FEATURE_DSC_SSSLICE_CNT]; + /**< Single large clock root divider slices (divide by 255)., array offset: 0x3000, array step: 0x4 */ + __IO uint32_t SLSLICE_CTRL[FSL_FEATURE_DSC_SLSLICE_CNT]; + uint32_t RESERVED_13[256 - FSL_FEATURE_DSC_SLSLICE_CNT]; + struct { /* offset: 0x3400, array step: 0x8 */ + __IO uint32_t MSLICE_CTRL__0; /**< Muliple synchronous clock root divider slices register., array offset: 0x3400, array step: 0x8 */ + __IO uint32_t MSLICE_CTRL__1; /**< Muliple synchronous clock root divider slices register., array offset: 0x3404, array step: 0x8 */ + } MSLICE_CTRL[1]; + uint8_t RESERVED_14[1016]; + /**< CPU clock root divider slices., array offset: 0x3800, array step: 0x4 */ + __IO uint32_t CSLICE_CTRL[FSL_FEATURE_DSC_CSLICE_CNT]; + uint32_t RESERVED_15[256 - FSL_FEATURE_DSC_CSLICE_CNT]; + __IO uint32_t XTAL_CTRL; /**< Xtal control register., offset: 0x3C00 */ + uint8_t RESERVED_16[1020]; + __IO uint32_t ROSC_CTRL; /**< Ring oscillator control register., offset: 0x4000 */ + uint8_t RESERVED_17[14332]; + __I uint32_t STATUS_0; /**< STATUS_0, offset: 0x7800 */ + uint8_t RESERVED_18[1020]; + __IO uint32_t DFT_CTRL; /**< DFT Control, offset: 0x7C00 */ +} DSC_Type; + +/* ---------------------------------------------------------------------------- + -- DSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSC_Register_Masks DSC Register Masks + * @{ + */ + +/*! @name RST_CTRL_SLICE_RSTN - Reset Control: MSlice and CSlice resetn bits */ +#define DSC_RST_CTRL_SLICE_RSTN_CSLICE_RSTN_MASK (0x1U) +#define DSC_RST_CTRL_SLICE_RSTN_CSLICE_RSTN_SHIFT (0U) +#define DSC_RST_CTRL_SLICE_RSTN_CSLICE_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLICE_RSTN_CSLICE_RSTN_SHIFT)) & DSC_RST_CTRL_SLICE_RSTN_CSLICE_RSTN_MASK) +#define DSC_RST_CTRL_SLICE_RSTN_MSLICE_RSTN_MASK (0x10000U) +#define DSC_RST_CTRL_SLICE_RSTN_MSLICE_RSTN_SHIFT (16U) +#define DSC_RST_CTRL_SLICE_RSTN_MSLICE_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLICE_RSTN_MSLICE_RSTN_SHIFT)) & DSC_RST_CTRL_SLICE_RSTN_MSLICE_RSTN_MASK) + +/*! @name RST_CTRL_SLSLICE_RSTN - Reset Control: SLSlice resetn bits */ +#define DSC_RST_CTRL_SLSLICE_RSTN_SLSLICE_RSTN_MASK (0x1FFFFU) +#define DSC_RST_CTRL_SLSLICE_RSTN_SLSLICE_RSTN_SHIFT (0U) +#define DSC_RST_CTRL_SLSLICE_RSTN_SLSLICE_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLSLICE_RSTN_SLSLICE_RSTN_SHIFT)) & DSC_RST_CTRL_SLSLICE_RSTN_SLSLICE_RSTN_MASK) + +/*! @name RST_CTRL_SSSLICE_RSTN - Reset Control: SSSlice resetn bits */ +#define DSC_RST_CTRL_SSSLICE_RSTN_SSSLICE_RSTN_MASK (0xFFU) +#define DSC_RST_CTRL_SSSLICE_RSTN_SSSLICE_RSTN_SHIFT (0U) +#define DSC_RST_CTRL_SSSLICE_RSTN_SSSLICE_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SSSLICE_RSTN_SSSLICE_RSTN_SHIFT)) & DSC_RST_CTRL_SSSLICE_RSTN_SSSLICE_RSTN_MASK) + +/*! @name RST_CTRL_CR_RSTN - Reset Control: Clock Root reset bits. */ +#define DSC_RST_CTRL_CR_RSTN_XTAL32K_SS_RSTN_MASK (0x1U) +#define DSC_RST_CTRL_CR_RSTN_XTAL32K_SS_RSTN_SHIFT (0U) +#define DSC_RST_CTRL_CR_RSTN_XTAL32K_SS_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_RSTN_XTAL32K_SS_RSTN_SHIFT)) & DSC_RST_CTRL_CR_RSTN_XTAL32K_SS_RSTN_MASK) +#define DSC_RST_CTRL_CR_RSTN_XTAL24M_SS_RSTN_MASK (0x4U) +#define DSC_RST_CTRL_CR_RSTN_XTAL24M_SS_RSTN_SHIFT (2U) +#define DSC_RST_CTRL_CR_RSTN_XTAL24M_SS_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_RSTN_XTAL24M_SS_RSTN_SHIFT)) & DSC_RST_CTRL_CR_RSTN_XTAL24M_SS_RSTN_MASK) +#define DSC_RST_CTRL_CR_RSTN_XTAL24M_ANA_RSTN_MASK (0x8U) +#define DSC_RST_CTRL_CR_RSTN_XTAL24M_ANA_RSTN_SHIFT (3U) +#define DSC_RST_CTRL_CR_RSTN_XTAL24M_ANA_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_RSTN_XTAL24M_ANA_RSTN_SHIFT)) & DSC_RST_CTRL_CR_RSTN_XTAL24M_ANA_RSTN_MASK) +#define DSC_RST_CTRL_CR_RSTN_AI_RSTN_MASK (0xFF0U) +#define DSC_RST_CTRL_CR_RSTN_AI_RSTN_SHIFT (4U) +#define DSC_RST_CTRL_CR_RSTN_AI_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_RSTN_AI_RSTN_SHIFT)) & DSC_RST_CTRL_CR_RSTN_AI_RSTN_MASK) + +/*! @name RST_CTRL_SS_RSTN - Reset Control: Subsystem resets */ +#define DSC_RST_CTRL_SS_RSTN_SUBSYS_RSTN_MASK (0x3FFU) +#define DSC_RST_CTRL_SS_RSTN_SUBSYS_RSTN_SHIFT (0U) +#define DSC_RST_CTRL_SS_RSTN_SUBSYS_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SS_RSTN_SUBSYS_RSTN_SHIFT)) & DSC_RST_CTRL_SS_RSTN_SUBSYS_RSTN_MASK) + +/*! @name RST_CTRL_SLICE_SFCM - Reset Control: MSlice and CSlice select functional clock mux bits. */ +#define DSC_RST_CTRL_SLICE_SFCM_CSLICE_SFCM_MASK (0x1U) +#define DSC_RST_CTRL_SLICE_SFCM_CSLICE_SFCM_SHIFT (0U) +#define DSC_RST_CTRL_SLICE_SFCM_CSLICE_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLICE_SFCM_CSLICE_SFCM_SHIFT)) & DSC_RST_CTRL_SLICE_SFCM_CSLICE_SFCM_MASK) +#define DSC_RST_CTRL_SLICE_SFCM_MSLICE_SFCM_MASK (0x10000U) +#define DSC_RST_CTRL_SLICE_SFCM_MSLICE_SFCM_SHIFT (16U) +#define DSC_RST_CTRL_SLICE_SFCM_MSLICE_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLICE_SFCM_MSLICE_SFCM_SHIFT)) & DSC_RST_CTRL_SLICE_SFCM_MSLICE_SFCM_MASK) + +/*! @name RST_CTRL_SLSLICE_SFCM - Reset Control: SLSlice select functional clock mux bits. */ +#define DSC_RST_CTRL_SLSLICE_SFCM_SLSLICE_SFCM_MASK (0x1FFFFU) +#define DSC_RST_CTRL_SLSLICE_SFCM_SLSLICE_SFCM_SHIFT (0U) +#define DSC_RST_CTRL_SLSLICE_SFCM_SLSLICE_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLSLICE_SFCM_SLSLICE_SFCM_SHIFT)) & DSC_RST_CTRL_SLSLICE_SFCM_SLSLICE_SFCM_MASK) + +/*! @name RST_CTRL_SSSLICE_SFCM - Reset Control: SSSlice select functional clock mux bits. */ +#define DSC_RST_CTRL_SSSLICE_SFCM_SSSLICE_SFCM_MASK (0xFFU) +#define DSC_RST_CTRL_SSSLICE_SFCM_SSSLICE_SFCM_SHIFT (0U) +#define DSC_RST_CTRL_SSSLICE_SFCM_SSSLICE_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SSSLICE_SFCM_SSSLICE_SFCM_SHIFT)) & DSC_RST_CTRL_SSSLICE_SFCM_SSSLICE_SFCM_MASK) + +/*! @name RST_CTRL_CR_SFCM - Reset Control: Select Functional Clock mux for root clocks. */ +#define DSC_RST_CTRL_CR_SFCM_XTAL32K_SS_SFCM_MASK (0x1U) +#define DSC_RST_CTRL_CR_SFCM_XTAL32K_SS_SFCM_SHIFT (0U) +#define DSC_RST_CTRL_CR_SFCM_XTAL32K_SS_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_SFCM_XTAL32K_SS_SFCM_SHIFT)) & DSC_RST_CTRL_CR_SFCM_XTAL32K_SS_SFCM_MASK) +#define DSC_RST_CTRL_CR_SFCM_XTAL24M_SS_SFCM_MASK (0x4U) +#define DSC_RST_CTRL_CR_SFCM_XTAL24M_SS_SFCM_SHIFT (2U) +#define DSC_RST_CTRL_CR_SFCM_XTAL24M_SS_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_SFCM_XTAL24M_SS_SFCM_SHIFT)) & DSC_RST_CTRL_CR_SFCM_XTAL24M_SS_SFCM_MASK) +#define DSC_RST_CTRL_CR_SFCM_XTAL24M_ANA_SFCM_MASK (0x8U) +#define DSC_RST_CTRL_CR_SFCM_XTAL24M_ANA_SFCM_SHIFT (3U) +#define DSC_RST_CTRL_CR_SFCM_XTAL24M_ANA_SFCM(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_SFCM_XTAL24M_ANA_SFCM_SHIFT)) & DSC_RST_CTRL_CR_SFCM_XTAL24M_ANA_SFCM_MASK) + +/*! @name RST_CTRL_SLICE_SFC - Reset Control: Mslice and Cslice Start Functional Clock bits */ +#define DSC_RST_CTRL_SLICE_SFC_CSLICE_SFC_MASK (0x1U) +#define DSC_RST_CTRL_SLICE_SFC_CSLICE_SFC_SHIFT (0U) +#define DSC_RST_CTRL_SLICE_SFC_CSLICE_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLICE_SFC_CSLICE_SFC_SHIFT)) & DSC_RST_CTRL_SLICE_SFC_CSLICE_SFC_MASK) +#define DSC_RST_CTRL_SLICE_SFC_MSLICE_SFC_MASK (0x10000U) +#define DSC_RST_CTRL_SLICE_SFC_MSLICE_SFC_SHIFT (16U) +#define DSC_RST_CTRL_SLICE_SFC_MSLICE_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLICE_SFC_MSLICE_SFC_SHIFT)) & DSC_RST_CTRL_SLICE_SFC_MSLICE_SFC_MASK) + +/*! @name RST_CTRL_SLSLICE_SFC - Reset Control: SSSlice Start Functional Clocks */ +#define DSC_RST_CTRL_SLSLICE_SFC_SLSLICE_SFC_MASK (0x1FFFFU) +#define DSC_RST_CTRL_SLSLICE_SFC_SLSLICE_SFC_SHIFT (0U) +#define DSC_RST_CTRL_SLSLICE_SFC_SLSLICE_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SLSLICE_SFC_SLSLICE_SFC_SHIFT)) & DSC_RST_CTRL_SLSLICE_SFC_SLSLICE_SFC_MASK) + +/*! @name RST_CTRL_SSSLICE_SFC - Reset Control: SSSlice start functional clocks */ +#define DSC_RST_CTRL_SSSLICE_SFC_SSSLICE_SFC_MASK (0xFFU) +#define DSC_RST_CTRL_SSSLICE_SFC_SSSLICE_SFC_SHIFT (0U) +#define DSC_RST_CTRL_SSSLICE_SFC_SSSLICE_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_SSSLICE_SFC_SSSLICE_SFC_SHIFT)) & DSC_RST_CTRL_SSSLICE_SFC_SSSLICE_SFC_MASK) + +/*! @name RST_CTRL_CR_SFC - Reset Control: Start Functional Clock bits for root clocks. */ +#define DSC_RST_CTRL_CR_SFC_XTAL32K_SS_SFC_MASK (0x1U) +#define DSC_RST_CTRL_CR_SFC_XTAL32K_SS_SFC_SHIFT (0U) +#define DSC_RST_CTRL_CR_SFC_XTAL32K_SS_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_SFC_XTAL32K_SS_SFC_SHIFT)) & DSC_RST_CTRL_CR_SFC_XTAL32K_SS_SFC_MASK) +#define DSC_RST_CTRL_CR_SFC_XTAL24M_SS_SFC_MASK (0x4U) +#define DSC_RST_CTRL_CR_SFC_XTAL24M_SS_SFC_SHIFT (2U) +#define DSC_RST_CTRL_CR_SFC_XTAL24M_SS_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_SFC_XTAL24M_SS_SFC_SHIFT)) & DSC_RST_CTRL_CR_SFC_XTAL24M_SS_SFC_MASK) +#define DSC_RST_CTRL_CR_SFC_XTAL24M_ANA_SFC_MASK (0x8U) +#define DSC_RST_CTRL_CR_SFC_XTAL24M_ANA_SFC_SHIFT (3U) +#define DSC_RST_CTRL_CR_SFC_XTAL24M_ANA_SFC(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_CR_SFC_XTAL24M_ANA_SFC_SHIFT)) & DSC_RST_CTRL_CR_SFC_XTAL24M_ANA_SFC_MASK) + +/*! @name RST_CTRL_RESET_CLK_EN - Reset Control: Enable for the reset clock. */ +#define DSC_RST_CTRL_RESET_CLK_EN_RESET_CLK_EN_MASK (0x1U) +#define DSC_RST_CTRL_RESET_CLK_EN_RESET_CLK_EN_SHIFT (0U) +#define DSC_RST_CTRL_RESET_CLK_EN_RESET_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_RST_CTRL_RESET_CLK_EN_RESET_CLK_EN_SHIFT)) & DSC_RST_CTRL_RESET_CLK_EN_RESET_CLK_EN_MASK) + +/*! @name POWER_CTRL - Power domain controls */ +#define DSC_POWER_CTRL_PFET_LF_EN_MASK (0x1U) +#define DSC_POWER_CTRL_PFET_LF_EN_SHIFT (0U) +#define DSC_POWER_CTRL_PFET_LF_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_PFET_LF_EN_SHIFT)) & DSC_POWER_CTRL_PFET_LF_EN_MASK) +#define DSC_POWER_CTRL_PFET_HF_EN_MASK (0x2U) +#define DSC_POWER_CTRL_PFET_HF_EN_SHIFT (1U) +#define DSC_POWER_CTRL_PFET_HF_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_PFET_HF_EN_SHIFT)) & DSC_POWER_CTRL_PFET_HF_EN_MASK) +#define DSC_POWER_CTRL_INPUT_ISO_EN_MASK (0x4U) +#define DSC_POWER_CTRL_INPUT_ISO_EN_SHIFT (2U) +#define DSC_POWER_CTRL_INPUT_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_INPUT_ISO_EN_SHIFT)) & DSC_POWER_CTRL_INPUT_ISO_EN_MASK) +#define DSC_POWER_CTRL_OUTPUT_ISO_EN_MASK (0x8U) +#define DSC_POWER_CTRL_OUTPUT_ISO_EN_SHIFT (3U) +#define DSC_POWER_CTRL_OUTPUT_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_OUTPUT_ISO_EN_SHIFT)) & DSC_POWER_CTRL_OUTPUT_ISO_EN_MASK) +#define DSC_POWER_CTRL_MISC_MASK (0xFFFF00U) +#define DSC_POWER_CTRL_MISC_SHIFT (8U) +#define DSC_POWER_CTRL_MISC(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_MISC_SHIFT)) & DSC_POWER_CTRL_MISC_MASK) +#define DSC_POWER_CTRL_PFET_LF_ACK_MASK (0x40000000U) +#define DSC_POWER_CTRL_PFET_LF_ACK_SHIFT (30U) +#define DSC_POWER_CTRL_PFET_LF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_PFET_LF_ACK_SHIFT)) & DSC_POWER_CTRL_PFET_LF_ACK_MASK) +#define DSC_POWER_CTRL_PFET_HF_ACK_MASK (0x80000000U) +#define DSC_POWER_CTRL_PFET_HF_ACK_SHIFT (31U) +#define DSC_POWER_CTRL_PFET_HF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_POWER_CTRL_PFET_HF_ACK_SHIFT)) & DSC_POWER_CTRL_PFET_HF_ACK_MASK) + +#define DSC_PWRCTRL_MEM_HS_MASK 0x00000800U +#define DSC_PWRCTRL_MEM_LS_MASK 0x00000400U + +#define DSC_PWRCTRL_MAIN_RFF_MASK 0x00001000U +#define DSC_PWRCTRL_MAIN_SLEEP_MASK 0x00002000U +#define DSC_PWRCTRL_MAIN_STDBY_MASK 0x00004000U +#define DSC_PWRCTRL_MAIN_INPUT_GATE_MASK 0x00008000U + +#define DSC_PWRCTRL_PSW_SMALL_MA_MASK 0x00010000U +#define DSC_PWRCTRL_PSW_LARGE_MA_MASK 0x00020000U +#define DSC_PWRCTRL_PSW_SMALL_MP_MASK 0x00040000U +#define DSC_PWRCTRL_PSW_LARGE_MP_MASK 0x00080000U +#define DSC_PWRCTRL_PSW_SMALL_MA_2_MASK 0x00040000U +#define DSC_PWRCTRL_PSW_LARGE_MA_2_MASK 0x00080000U +#define DSC_PWRCTRL_PSW_SMALL_MASK 0x00100000U +#define DSC_PWRCTRL_PSW_LARGE_MASK 0x00200000U + +#define DSC_PWRCTRL_PSW_SMALL_MA_3_MASK 0x00400000U +#define DSC_PWRCTRL_PSW_LARGE_MA_3_MASK 0x00800000U + +#define DSC_PWRCTRL_MEM_DEEP_SLEEP 0x00400000U +#define DSC_PWRCTRL_MEM_STANDBY 0x00800000U + + +/* The count of DSC_POWER_CTRL */ +#define DSC_POWER_CTRL_COUNT (6U) + +/* The count of DSC_POWER_CTRL_SET */ +#define DSC_POWER_CTRL_SET_COUNT (6U) + +/* The count of DSC_POWER_CTRL_CLR */ +#define DSC_POWER_CTRL_CLR_COUNT (6U) + +/* The count of DSC_POWER_CTRL_TOG */ +#define DSC_POWER_CTRL_TOG_COUNT (6U) + +/*! @name GPR_CTRL - General purpose control register bits. */ +#define DSC_GPR_CTRL_CTRL_MASK (0xFFFFFFFFU) +#define DSC_GPR_CTRL_CTRL_SHIFT (0U) +#define DSC_GPR_CTRL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DSC_GPR_CTRL_CTRL_SHIFT)) & DSC_GPR_CTRL_CTRL_MASK) + +/* The count of DSC_GPR_CTRL_SET */ +#define DSC_GPR_CTRL_SET_COUNT (3U) + +/* The count of DSC_GPR_CTRL_CLR */ +#define DSC_GPR_CTRL_CLR_COUNT (3U) + +/* The count of DSC_GPR_CTRL_TOG */ +#define DSC_GPR_CTRL_TOG_COUNT (3U) + +/*! @name GPR_STAT - General purpose status bits. */ +#define DSC_GPR_STAT_STATUS_MASK (0xFFFFFFFFU) +#define DSC_GPR_STAT_STATUS_SHIFT (0U) +#define DSC_GPR_STAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSC_GPR_STAT_STATUS_SHIFT)) & DSC_GPR_STAT_STATUS_MASK) + +/* The count of DSC_GPR_STAT */ +#define DSC_GPR_STAT_COUNT (3U) + +/* The count of DSC_GPR_STAT_SET */ +#define DSC_GPR_STAT_SET_COUNT (3U) + +/* The count of DSC_GPR_STAT_CLR */ +#define DSC_GPR_STAT_CLR_COUNT (3U) + +/* The count of DSC_GPR_STAT_TOG */ +#define DSC_GPR_STAT_TOG_COUNT (3U) + +/*! @name IRQ_MASK_DSC - IRQ mask register for DSC interrupts. */ +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_PANIC_MASK (0x1U) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_PANIC_SHIFT (0U) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_PANIC(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_TEMPSENSOR_PANIC_SHIFT)) & DSC_IRQ_MASK_DSC_TEMPSENSOR_PANIC_MASK) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_LOW_MASK (0x2U) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_LOW_SHIFT (1U) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_TEMPSENSOR_LOW_SHIFT)) & DSC_IRQ_MASK_DSC_TEMPSENSOR_LOW_MASK) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_HIGH_MASK (0x4U) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_HIGH_SHIFT (2U) +#define DSC_IRQ_MASK_DSC_TEMPSENSOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_TEMPSENSOR_HIGH_SHIFT)) & DSC_IRQ_MASK_DSC_TEMPSENSOR_HIGH_MASK) +#define DSC_IRQ_MASK_DSC_MSI_SLV_ERROR_IRQ_MASK (0x8U) +#define DSC_IRQ_MASK_DSC_MSI_SLV_ERROR_IRQ_SHIFT (3U) +#define DSC_IRQ_MASK_DSC_MSI_SLV_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_MSI_SLV_ERROR_IRQ_SHIFT)) & DSC_IRQ_MASK_DSC_MSI_SLV_ERROR_IRQ_MASK) +#define DSC_IRQ_MASK_DSC_MSI_SLV_WR_OVFL_IRQ_MASK (0x10U) +#define DSC_IRQ_MASK_DSC_MSI_SLV_WR_OVFL_IRQ_SHIFT (4U) +#define DSC_IRQ_MASK_DSC_MSI_SLV_WR_OVFL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_MSI_SLV_WR_OVFL_IRQ_SHIFT)) & DSC_IRQ_MASK_DSC_MSI_SLV_WR_OVFL_IRQ_MASK) +#define DSC_IRQ_MASK_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_MASK (0x20U) +#define DSC_IRQ_MASK_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_SHIFT (5U) +#define DSC_IRQ_MASK_DSC_MSI_SLV_AHB_WR_OVFL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_SHIFT)) & DSC_IRQ_MASK_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_MASK) +#define DSC_IRQ_MASK_DSC_BIST_IRQ_MASK (0x40U) +#define DSC_IRQ_MASK_DSC_BIST_IRQ_SHIFT (6U) +#define DSC_IRQ_MASK_DSC_BIST_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_BIST_IRQ_SHIFT)) & DSC_IRQ_MASK_DSC_BIST_IRQ_MASK) +#define DSC_IRQ_MASK_DSC_PWRCTRL_PFET_LF_ACK_MASK (0x3F0000U) +#define DSC_IRQ_MASK_DSC_PWRCTRL_PFET_LF_ACK_SHIFT (16U) +#define DSC_IRQ_MASK_DSC_PWRCTRL_PFET_LF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_PWRCTRL_PFET_LF_ACK_SHIFT)) & DSC_IRQ_MASK_DSC_PWRCTRL_PFET_LF_ACK_MASK) +#define DSC_IRQ_MASK_DSC_PWRCTRL_PFET_HF_ACK_MASK (0x3F000000U) +#define DSC_IRQ_MASK_DSC_PWRCTRL_PFET_HF_ACK_SHIFT (24U) +#define DSC_IRQ_MASK_DSC_PWRCTRL_PFET_HF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_DSC_PWRCTRL_PFET_HF_ACK_SHIFT)) & DSC_IRQ_MASK_DSC_PWRCTRL_PFET_HF_ACK_MASK) + +/*! @name IRQ_MASK_SUBSYS - IRQ mask register for Subsystem interrupts. */ +#define DSC_IRQ_MASK_SUBSYS_SUBSYS_MASK (0xFFFFFFFU) +#define DSC_IRQ_MASK_SUBSYS_SUBSYS_SHIFT (0U) +#define DSC_IRQ_MASK_SUBSYS_SUBSYS(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_SUBSYS_SUBSYS_SHIFT)) & DSC_IRQ_MASK_SUBSYS_SUBSYS_MASK) + +/*! @name IRQ_MASK_STATUS_DSC - IRQ masked status register for DSC interrupts. */ +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_PANIC_MASK (0x1U) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_PANIC_SHIFT (0U) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_PANIC(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_PANIC_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_PANIC_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_LOW_MASK (0x2U) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_LOW_SHIFT (1U) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_LOW_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_LOW_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_HIGH_MASK (0x4U) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_HIGH_SHIFT (2U) +#define DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_HIGH_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_TEMPSENSOR_HIGH_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_MASK (0x8U) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_SHIFT (3U) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_MASK (0x10U) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_SHIFT (4U) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_MASK (0x20U) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_SHIFT (5U) +#define DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_BIST_IRQ_MASK (0x40U) +#define DSC_IRQ_MASK_STATUS_DSC_BIST_IRQ_SHIFT (6U) +#define DSC_IRQ_MASK_STATUS_DSC_BIST_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_BIST_IRQ_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_BIST_IRQ_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_MASK (0x3F0000U) +#define DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_SHIFT (16U) +#define DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_MASK) +#define DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_MASK (0x3F000000U) +#define DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_SHIFT (24U) +#define DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_SHIFT)) & DSC_IRQ_MASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_MASK) + +/*! @name IRQ_MASK_STATUS_SUBSYS - IRQ masked status register for Subsystem interrupts. */ +#define DSC_IRQ_MASK_STATUS_SUBSYS_SUBSYS_MASK (0xFFFFFFFU) +#define DSC_IRQ_MASK_STATUS_SUBSYS_SUBSYS_SHIFT (0U) +#define DSC_IRQ_MASK_STATUS_SUBSYS_SUBSYS(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_MASK_STATUS_SUBSYS_SUBSYS_SHIFT)) & DSC_IRQ_MASK_STATUS_SUBSYS_SUBSYS_MASK) + +/*! @name IRQ_NONMASK_STATUS_DSC - IRQ non-masked status register for DSC interrupts. */ +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_PANIC_MASK (0x1U) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_PANIC_SHIFT (0U) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_PANIC(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_PANIC_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_PANIC_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_LOW_MASK (0x2U) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_LOW_SHIFT (1U) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_LOW_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_LOW_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_HIGH_MASK (0x4U) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_HIGH_SHIFT (2U) +#define DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_HIGH_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_TEMPSENSOR_HIGH_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_MASK (0x8U) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_SHIFT (3U) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_ERROR_IRQ_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_MASK (0x10U) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_SHIFT (4U) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_WR_OVFL_IRQ_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_MASK (0x20U) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_SHIFT (5U) +#define DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_MSI_SLV_AHB_WR_OVFL_IRQ_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_BIST_IRQ_MASK (0x40U) +#define DSC_IRQ_NONMASK_STATUS_DSC_BIST_IRQ_SHIFT (6U) +#define DSC_IRQ_NONMASK_STATUS_DSC_BIST_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_BIST_IRQ_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_BIST_IRQ_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_MASK (0x3F0000U) +#define DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_SHIFT (16U) +#define DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_LF_ACK_MASK) +#define DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_MASK (0x3F000000U) +#define DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_SHIFT (24U) +#define DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_SHIFT)) & DSC_IRQ_NONMASK_STATUS_DSC_PWRCTRL_PFET_HF_ACK_MASK) + +/*! @name IRQ_NONMASK_STATUS_SUBSYS - IRQ non-masked status register for Subsystem interrupts. */ +#define DSC_IRQ_NONMASK_STATUS_SUBSYS_SUBSYS_MASK (0xFFFFFFFU) +#define DSC_IRQ_NONMASK_STATUS_SUBSYS_SUBSYS_SHIFT (0U) +#define DSC_IRQ_NONMASK_STATUS_SUBSYS_SUBSYS(x) (((uint32_t)(((uint32_t)(x)) << DSC_IRQ_NONMASK_STATUS_SUBSYS_SUBSYS_SHIFT)) & DSC_IRQ_NONMASK_STATUS_SUBSYS_SUBSYS_MASK) + +/*! @name AI_CTRL - Analog Interface Control Registers */ +#define DSC_AI_CTRL_ADDR_MASK (0xFFFFU) +#define DSC_AI_CTRL_ADDR_SHIFT (0U) +#define DSC_AI_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_CTRL_ADDR_SHIFT)) & DSC_AI_CTRL_ADDR_MASK) +#define DSC_AI_CTRL_SRC_SEL_MASK (0x1F0000U) +#define DSC_AI_CTRL_SRC_SEL_SHIFT (16U) +#define DSC_AI_CTRL_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_CTRL_SRC_SEL_SHIFT)) & DSC_AI_CTRL_SRC_SEL_MASK) +#define DSC_AI_CTRL_RWB_MASK (0x80000000U) +#define DSC_AI_CTRL_RWB_SHIFT (31U) +#define DSC_AI_CTRL_RWB(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_CTRL_RWB_SHIFT)) & DSC_AI_CTRL_RWB_MASK) + +/*! @name AI_WR_DATA - Analog Interface Registers */ +#define DSC_AI_WR_DATA_WR_DATA_MASK (0xFFFFFFFFU) +#define DSC_AI_WR_DATA_WR_DATA_SHIFT (0U) +#define DSC_AI_WR_DATA_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_WR_DATA_WR_DATA_SHIFT)) & DSC_AI_WR_DATA_WR_DATA_MASK) + +/*! @name AI_TOGGLE - Analog Interface Registers */ +#define DSC_AI_TOGGLE_TOGGLE_MASK (0xFFFFFFFFU) +#define DSC_AI_TOGGLE_TOGGLE_SHIFT (0U) +#define DSC_AI_TOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_TOGGLE_TOGGLE_SHIFT)) & DSC_AI_TOGGLE_TOGGLE_MASK) + +/*! @name AI_DONE_TOGGLE - Analog Interface Registers */ +#define DSC_AI_DONE_TOGGLE_DONE_TOGGLE_MASK (0xFFFFFFFFU) +#define DSC_AI_DONE_TOGGLE_DONE_TOGGLE_SHIFT (0U) +#define DSC_AI_DONE_TOGGLE_DONE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_DONE_TOGGLE_DONE_TOGGLE_SHIFT)) & DSC_AI_DONE_TOGGLE_DONE_TOGGLE_MASK) + +/*! @name AI_RD_DATA - Analog Interface Registers */ +#define DSC_AI_RD_DATA_RD_DATA_MASK (0xFFFFFFFFU) +#define DSC_AI_RD_DATA_RD_DATA_SHIFT (0U) +#define DSC_AI_RD_DATA_RD_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_RD_DATA_RD_DATA_SHIFT)) & DSC_AI_RD_DATA_RD_DATA_MASK) + +/*! @name AI_BUSY - Analog Interface Registers */ +#define DSC_AI_BUSY_BUSY_MASK (0xFFFFFFFFU) +#define DSC_AI_BUSY_BUSY_SHIFT (0U) +#define DSC_AI_BUSY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << DSC_AI_BUSY_BUSY_SHIFT)) & DSC_AI_BUSY_BUSY_MASK) + +/*! @name LOCKOUT - LOCKOUT Register */ +#define DSC_LOCKOUT_LOCKOUT_MASK (0xFFU) +#define DSC_LOCKOUT_LOCKOUT_SHIFT (0U) +#define DSC_LOCKOUT_LOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << DSC_LOCKOUT_LOCKOUT_SHIFT)) & DSC_LOCKOUT_LOCKOUT_MASK) +#define DSC_LOCKOUT_LOCKOUT_EN_MASK (0x80000000U) +#define DSC_LOCKOUT_LOCKOUT_EN_SHIFT (31U) +#define DSC_LOCKOUT_LOCKOUT_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_LOCKOUT_LOCKOUT_EN_SHIFT)) & DSC_LOCKOUT_LOCKOUT_EN_MASK) + +/*! @name SSSLICE_CTRL - Single small clock root divider slices (divide by 31). */ +#define DSC_SSSLICE_CTRL_SSDIV_MASK (0x1FU) +#define DSC_SSSLICE_CTRL_SSDIV_SHIFT (0U) +#define DSC_SSSLICE_CTRL_SSDIV(x) (((uint32_t)(((uint32_t)(x)) << DSC_SSSLICE_CTRL_SSDIV_SHIFT)) & DSC_SSSLICE_CTRL_SSDIV_MASK) +#define DSC_SSSLICE_CTRL_SRC_SEL_MASK (0x1C000000U) +#define DSC_SSSLICE_CTRL_SRC_SEL_SHIFT (26U) +#define DSC_SSSLICE_CTRL_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_SSSLICE_CTRL_SRC_SEL_SHIFT)) & DSC_SSSLICE_CTRL_SRC_SEL_MASK) +#define DSC_SSSLICE_CTRL_HW_SEL_MASK (0x20000000U) +#define DSC_SSSLICE_CTRL_HW_SEL_SHIFT (29U) +#define DSC_SSSLICE_CTRL_HW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_SSSLICE_CTRL_HW_SEL_SHIFT)) & DSC_SSSLICE_CTRL_HW_SEL_MASK) +#define DSC_SSSLICE_CTRL_FW_SEL_MASK (0xC0000000U) +#define DSC_SSSLICE_CTRL_FW_SEL_SHIFT (30U) +#define DSC_SSSLICE_CTRL_FW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_SSSLICE_CTRL_FW_SEL_SHIFT)) & DSC_SSSLICE_CTRL_FW_SEL_MASK) + +/* The count of DSC_SSSLICE_CTRL */ +#define DSC_SSSLICE_CTRL_COUNT (8U) + +/*! @name SLSLICE_CTRL - Single large clock root divider slices (divide by 255). */ +#define DSC_SLSLICE_CTRL_SLDIV_MASK (0xFFU) +#define DSC_SLSLICE_CTRL_SLDIV_SHIFT (0U) +#define DSC_SLSLICE_CTRL_SLDIV(x) (((uint32_t)(((uint32_t)(x)) << DSC_SLSLICE_CTRL_SLDIV_SHIFT)) & DSC_SLSLICE_CTRL_SLDIV_MASK) +#define DSC_SLSLICE_CTRL_SRC_SEL_MASK (0x1C000000U) +#define DSC_SLSLICE_CTRL_SRC_SEL_SHIFT (26U) +#define DSC_SLSLICE_CTRL_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_SLSLICE_CTRL_SRC_SEL_SHIFT)) & DSC_SLSLICE_CTRL_SRC_SEL_MASK) +#define DSC_SLSLICE_CTRL_HW_SEL_MASK (0x20000000U) +#define DSC_SLSLICE_CTRL_HW_SEL_SHIFT (29U) +#define DSC_SLSLICE_CTRL_HW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_SLSLICE_CTRL_HW_SEL_SHIFT)) & DSC_SLSLICE_CTRL_HW_SEL_MASK) +#define DSC_SLSLICE_CTRL_FW_SEL_MASK (0xC0000000U) +#define DSC_SLSLICE_CTRL_FW_SEL_SHIFT (30U) +#define DSC_SLSLICE_CTRL_FW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_SLSLICE_CTRL_FW_SEL_SHIFT)) & DSC_SLSLICE_CTRL_FW_SEL_MASK) + +/* The count of DSC_SLSLICE_CTRL */ +#define DSC_SLSLICE_CTRL_COUNT (17U) + +/*! @name MSLICE_CTRL__0 - Muliple synchronous clock root divider slices register. */ +#define DSC_MSLICE_CTRL__0_DIV_ROOT0_MASK (0x1FU) +#define DSC_MSLICE_CTRL__0_DIV_ROOT0_SHIFT (0U) +#define DSC_MSLICE_CTRL__0_DIV_ROOT0(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__0_DIV_ROOT0_SHIFT)) & DSC_MSLICE_CTRL__0_DIV_ROOT0_MASK) +#define DSC_MSLICE_CTRL__0_DIV_ROOT1_MASK (0x3E0U) +#define DSC_MSLICE_CTRL__0_DIV_ROOT1_SHIFT (5U) +#define DSC_MSLICE_CTRL__0_DIV_ROOT1(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__0_DIV_ROOT1_SHIFT)) & DSC_MSLICE_CTRL__0_DIV_ROOT1_MASK) + +/* The count of DSC_MSLICE_CTRL__0 */ +#define DSC_MSLICE_CTRL__0_COUNT (1U) + +/*! @name MSLICE_CTRL__1 - Muliple synchronous clock root divider slices register. */ +#define DSC_MSLICE_CTRL__1_DIV_ROOT2_MASK (0x1FU) +#define DSC_MSLICE_CTRL__1_DIV_ROOT2_SHIFT (0U) +#define DSC_MSLICE_CTRL__1_DIV_ROOT2(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__1_DIV_ROOT2_SHIFT)) & DSC_MSLICE_CTRL__1_DIV_ROOT2_MASK) +#define DSC_MSLICE_CTRL__1_DIV_ROOT3_MASK (0x3E0U) +#define DSC_MSLICE_CTRL__1_DIV_ROOT3_SHIFT (5U) +#define DSC_MSLICE_CTRL__1_DIV_ROOT3(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__1_DIV_ROOT3_SHIFT)) & DSC_MSLICE_CTRL__1_DIV_ROOT3_MASK) +#define DSC_MSLICE_CTRL__1_SYS_CTR_CLK_SEL_MASK (0x2000000U) +#define DSC_MSLICE_CTRL__1_SYS_CTR_CLK_SEL_SHIFT (25U) +#define DSC_MSLICE_CTRL__1_SYS_CTR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__1_SYS_CTR_CLK_SEL_SHIFT)) & DSC_MSLICE_CTRL__1_SYS_CTR_CLK_SEL_MASK) +#define DSC_MSLICE_CTRL__1_SRC_SEL_MASK (0x1C000000U) +#define DSC_MSLICE_CTRL__1_SRC_SEL_SHIFT (26U) +#define DSC_MSLICE_CTRL__1_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__1_SRC_SEL_SHIFT)) & DSC_MSLICE_CTRL__1_SRC_SEL_MASK) +#define DSC_MSLICE_CTRL__1_HW_SEL_MASK (0x20000000U) +#define DSC_MSLICE_CTRL__1_HW_SEL_SHIFT (29U) +#define DSC_MSLICE_CTRL__1_HW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__1_HW_SEL_SHIFT)) & DSC_MSLICE_CTRL__1_HW_SEL_MASK) +#define DSC_MSLICE_CTRL__1_FW_SEL_MASK (0xC0000000U) +#define DSC_MSLICE_CTRL__1_FW_SEL_SHIFT (30U) +#define DSC_MSLICE_CTRL__1_FW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_MSLICE_CTRL__1_FW_SEL_SHIFT)) & DSC_MSLICE_CTRL__1_FW_SEL_MASK) + +/* The count of DSC_MSLICE_CTRL__1 */ +#define DSC_MSLICE_CTRL__1_COUNT (1U) + +/*! @name CSLICE_CTRL - CPU clock root divider slices. */ +#define DSC_CSLICE_CTRL_SRC_SEL_MASK (0x1C000000U) +#define DSC_CSLICE_CTRL_SRC_SEL_SHIFT (26U) +#define DSC_CSLICE_CTRL_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_CSLICE_CTRL_SRC_SEL_SHIFT)) & DSC_CSLICE_CTRL_SRC_SEL_MASK) +#define DSC_CSLICE_CTRL_HW_SEL_MASK (0x20000000U) +#define DSC_CSLICE_CTRL_HW_SEL_SHIFT (29U) +#define DSC_CSLICE_CTRL_HW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_CSLICE_CTRL_HW_SEL_SHIFT)) & DSC_CSLICE_CTRL_HW_SEL_MASK) +#define DSC_CSLICE_CTRL_FW_SEL_MASK (0xC0000000U) +#define DSC_CSLICE_CTRL_FW_SEL_SHIFT (30U) +#define DSC_CSLICE_CTRL_FW_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_CSLICE_CTRL_FW_SEL_SHIFT)) & DSC_CSLICE_CTRL_FW_SEL_MASK) + +/* The count of DSC_CSLICE_CTRL */ +#define DSC_CSLICE_CTRL_COUNT (1U) + +/*! @name XTAL_CTRL - Xtal control register. */ +#define DSC_XTAL_CTRL_GLBL_ANA_XTAL24M_EN_MASK (0x1U) +#define DSC_XTAL_CTRL_GLBL_ANA_XTAL24M_EN_SHIFT (0U) +#define DSC_XTAL_CTRL_GLBL_ANA_XTAL24M_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_GLBL_ANA_XTAL24M_EN_SHIFT)) & DSC_XTAL_CTRL_GLBL_ANA_XTAL24M_EN_MASK) +#define DSC_XTAL_CTRL_DSC_AON_XTAL24M_EN_MASK (0x2U) +#define DSC_XTAL_CTRL_DSC_AON_XTAL24M_EN_SHIFT (1U) +#define DSC_XTAL_CTRL_DSC_AON_XTAL24M_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_DSC_AON_XTAL24M_EN_SHIFT)) & DSC_XTAL_CTRL_DSC_AON_XTAL24M_EN_MASK) +#define DSC_XTAL_CTRL_DSC_PG_XTAL24M_EN_MASK (0x4U) +#define DSC_XTAL_CTRL_DSC_PG_XTAL24M_EN_SHIFT (2U) +#define DSC_XTAL_CTRL_DSC_PG_XTAL24M_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_DSC_PG_XTAL24M_EN_SHIFT)) & DSC_XTAL_CTRL_DSC_PG_XTAL24M_EN_MASK) +#define DSC_XTAL_CTRL_ANALOG_XTAL24M_EN_MASK (0x8U) +#define DSC_XTAL_CTRL_ANALOG_XTAL24M_EN_SHIFT (3U) +#define DSC_XTAL_CTRL_ANALOG_XTAL24M_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_ANALOG_XTAL24M_EN_SHIFT)) & DSC_XTAL_CTRL_ANALOG_XTAL24M_EN_MASK) +#define DSC_XTAL_CTRL_OSC_XTAL24M_EN_MASK (0x100U) +#define DSC_XTAL_CTRL_OSC_XTAL24M_EN_SHIFT (8U) +#define DSC_XTAL_CTRL_OSC_XTAL24M_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_OSC_XTAL24M_EN_SHIFT)) & DSC_XTAL_CTRL_OSC_XTAL24M_EN_MASK) +#define DSC_XTAL_CTRL_OSC_XTAL32K_SFC_SEL_MASK (0x10000U) +#define DSC_XTAL_CTRL_OSC_XTAL32K_SFC_SEL_SHIFT (16U) +#define DSC_XTAL_CTRL_OSC_XTAL32K_SFC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_OSC_XTAL32K_SFC_SEL_SHIFT)) & DSC_XTAL_CTRL_OSC_XTAL32K_SFC_SEL_MASK) +#define DSC_XTAL_CTRL_XTAL32K_SYNC_SEL_MASK (0x80000000U) +#define DSC_XTAL_CTRL_XTAL32K_SYNC_SEL_SHIFT (31U) +#define DSC_XTAL_CTRL_XTAL32K_SYNC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DSC_XTAL_CTRL_XTAL32K_SYNC_SEL_SHIFT)) & DSC_XTAL_CTRL_XTAL32K_SYNC_SEL_MASK) + +/*! @name ROSC_CTRL - Ring oscillator control register. */ +#define DSC_ROSC_CTRL_ROSC_START_EN_MASK (0x1U) +#define DSC_ROSC_CTRL_ROSC_START_EN_SHIFT (0U) +#define DSC_ROSC_CTRL_ROSC_START_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_ROSC_CTRL_ROSC_START_EN_SHIFT)) & DSC_ROSC_CTRL_ROSC_START_EN_MASK) +#define DSC_ROSC_CTRL_ROSC_STOP_EN_MASK (0x2U) +#define DSC_ROSC_CTRL_ROSC_STOP_EN_SHIFT (1U) +#define DSC_ROSC_CTRL_ROSC_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_ROSC_CTRL_ROSC_STOP_EN_SHIFT)) & DSC_ROSC_CTRL_ROSC_STOP_EN_MASK) + +/*! @name STATUS_0 - STATUS_0 */ +#define DSC_STATUS_0_DSC_HM_TYPE_MASK (0xFU) +#define DSC_STATUS_0_DSC_HM_TYPE_SHIFT (0U) +#define DSC_STATUS_0_DSC_HM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DSC_STATUS_0_DSC_HM_TYPE_SHIFT)) & DSC_STATUS_0_DSC_HM_TYPE_MASK) + +/*! @name DFT_CTRL - DFT Control */ +#define DSC_DFT_CTRL_TCU_RSTN_MASK (0x1U) +#define DSC_DFT_CTRL_TCU_RSTN_SHIFT (0U) +#define DSC_DFT_CTRL_TCU_RSTN(x) (((uint32_t)(((uint32_t)(x)) << DSC_DFT_CTRL_TCU_RSTN_SHIFT)) & DSC_DFT_CTRL_TCU_RSTN_MASK) +#define DSC_DFT_CTRL_BI_BIST_MODE_MASK (0x2U) +#define DSC_DFT_CTRL_BI_BIST_MODE_SHIFT (1U) +#define DSC_DFT_CTRL_BI_BIST_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSC_DFT_CTRL_BI_BIST_MODE_SHIFT)) & DSC_DFT_CTRL_BI_BIST_MODE_MASK) +#define DSC_DFT_CTRL_BI_DC_SCAN_MODE_MASK (0x4U) +#define DSC_DFT_CTRL_BI_DC_SCAN_MODE_SHIFT (2U) +#define DSC_DFT_CTRL_BI_DC_SCAN_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSC_DFT_CTRL_BI_DC_SCAN_MODE_SHIFT)) & DSC_DFT_CTRL_BI_DC_SCAN_MODE_MASK) +#define DSC_DFT_CTRL_BI_IO_EN_MASK (0x8U) +#define DSC_DFT_CTRL_BI_IO_EN_SHIFT (3U) +#define DSC_DFT_CTRL_BI_IO_EN(x) (((uint32_t)(((uint32_t)(x)) << DSC_DFT_CTRL_BI_IO_EN_SHIFT)) & DSC_DFT_CTRL_BI_IO_EN_MASK) + +/*! + * @} + */ /* end of group DSC_Register_Masks */ + +/* DSC - Peripheral instance base addresses */ +/** Peripheral dsc base pointer */ +#define DSC1 ((DSC_Type *)DSC1_BASE) +/** Peripheral dsc base pointer */ +#define DSC2 ((DSC_Type *)DSC2_BASE) +/** Peripheral dsc base pointer */ +#define DSC3 ((DSC_Type *)DSC3_BASE) +/** Peripheral dsc base pointer */ +#define DSC4 ((DSC_Type *)DSC4_BASE) +/** Peripheral dsc base pointer */ +#define DSC5 ((DSC_Type *)DSC5_BASE) +/** Peripheral dsc base pointer */ +#define DSC6 ((DSC_Type *)DSC6_BASE) +/** Peripheral dsc base pointer */ +#define DSC7 ((DSC_Type *)DSC7_BASE) +/** Peripheral dsc base pointer */ +#define DSC8 ((DSC_Type *)DSC8_BASE) +/** Peripheral dsc base pointer */ +#define DSC9 ((DSC_Type *)DSC9_BASE) +/** Peripheral dsc base pointer */ +#define DSC10 ((DSC_Type *)DSC10_BASE) +/** Peripheral dsc base pointer */ +#define DSC11 ((DSC_Type *)DSC11_BASE) +/** Peripheral dsc base pointer */ +#define DSC12 ((DSC_Type *)DSC12_BASE) +/** Peripheral dsc base pointer */ +#define DSC13 ((DSC_Type *)DSC13_BASE) +/** Peripheral dsc base pointer */ +#define DSC14 ((DSC_Type *)DSC14_BASE) +/** Peripheral dsc base pointer */ +#define DSC15 ((DSC_Type *)DSC15_BASE) +/** Peripheral dsc base pointer */ +#define DSC17 ((DSC_Type *)DSC17_BASE) +/** Peripheral dsc base pointer */ +#define DSC18 ((DSC_Type *)DSC18_BASE) +/** Peripheral dsc base pointer */ +#define DSC19 ((DSC_Type *)DSC19_BASE) +/** Peripheral dsc base pointer */ +#define DSC20 ((DSC_Type *)DSC20_BASE) +/** Peripheral dsc base pointer */ +#define DSC21 ((DSC_Type *)DSC21_BASE) +/** Peripheral dsc base pointer */ +#define DSC22 ((DSC_Type *)DSC22_BASE) +/** Peripheral dsc base pointer */ +#define DSC23 ((DSC_Type *)DSC23_BASE) +/** Peripheral dsc base pointer */ +#define DSC24 ((DSC_Type *)DSC24_BASE) +/** Peripheral dsc base pointer */ +#define DSC25 ((DSC_Type *)DSC25_BASE) +/** Peripheral dsc base pointer */ +#define DSC26 ((DSC_Type *)DSC26_BASE) +/** Peripheral dsc base pointer */ +#define DSC27 ((DSC_Type *)DSC27_BASE) +/** Peripheral dsc base pointer */ +#define DSC28 ((DSC_Type *)DSC28_BASE) +/** Peripheral dsc base pointer */ +#define DSC29 ((DSC_Type *)DSC29_BASE) +/** Peripheral dsc base pointer */ +#define DSC30 ((DSC_Type *)DSC30_BASE) +/** Peripheral dsc base pointer */ +#define DSC31 ((DSC_Type *)DSC31_BASE) +/** Peripheral dsc base pointer */ +#define DSC33 ((DSC_Type *)DSC33_BASE) +/** Peripheral dsc base pointer */ +#define DSC34 ((DSC_Type *)DSC34_BASE) +/** Peripheral dsc base pointer */ +#define DSC35 ((DSC_Type *)DSC35_BASE) +/** Peripheral dsc base pointer */ +#define DSC36 ((DSC_Type *)DSC36_BASE) +/** Peripheral dsc base pointer */ +#define DSC37 ((DSC_Type *)DSC37_BASE) +/** Peripheral dsc base pointer */ +#define DSC38 ((DSC_Type *)DSC38_BASE) +/** Peripheral dsc base pointer */ +#define DSC39 ((DSC_Type *)DSC39_BASE) +/** Peripheral dsc base pointer */ +#define DSC40 ((DSC_Type *)DSC40_BASE) +/** Peripheral dsc base pointer */ +#define DSC41 ((DSC_Type *)DSC41_BASE) +/** Peripheral dsc base pointer */ +#define DSC42 ((DSC_Type *)DSC42_BASE) +/** Peripheral dsc base pointer */ +#define DSC43 ((DSC_Type *)DSC43_BASE) +/** Peripheral dsc base pointer */ +#define DSC44 ((DSC_Type *)DSC44_BASE) +/** Peripheral dsc base pointer */ +#define DSC45 ((DSC_Type *)DSC45_BASE) +/** Peripheral dsc base pointer */ +#define DSC46 ((DSC_Type *)DSC46_BASE) +/** Peripheral dsc base pointer */ +#define DSC47 ((DSC_Type *)DSC47_BASE) +/** Peripheral dsc base pointer */ +#define DSC49 ((DSC_Type *)DSC49_BASE) +/** Peripheral dsc base pointer */ +#define DSC50 ((DSC_Type *)DSC50_BASE) +/** Peripheral dsc base pointer */ +#define DSC51 ((DSC_Type *)DSC51_BASE) +/** Peripheral dsc base pointer */ +#define DSC52 ((DSC_Type *)DSC52_BASE) +/** Peripheral dsc base pointer */ +#define DSC53 ((DSC_Type *)DSC53_BASE) +/** Peripheral dsc base pointer */ +#define DSC54 ((DSC_Type *)DSC54_BASE) +/** Peripheral dsc base pointer */ +#define DSC55 ((DSC_Type *)DSC55_BASE) +/** Peripheral dsc base pointer */ +#define DSC56 ((DSC_Type *)DSC56_BASE) +/** Peripheral dsc base pointer */ +#define DSC57 ((DSC_Type *)DSC57_BASE) +/** Peripheral dsc base pointer */ +#define DSC58 ((DSC_Type *)DSC58_BASE) +/** Peripheral dsc base pointer */ +#define DSC59 ((DSC_Type *)DSC59_BASE) +/** Peripheral dsc base pointer */ +#define DSC60 ((DSC_Type *)DSC60_BASE) +/** Peripheral dsc base pointer */ +#define DSC61 ((DSC_Type *)DSC61_BASE) +/** Peripheral dsc base pointer */ +#define DSC62 ((DSC_Type *)DSC62_BASE) +/** Peripheral dsc base pointer */ +#define DSC63 ((DSC_Type *)DSC63_BASE) +/** Array initializer of DSC peripheral base addresses */ +#define DSC_BASE_ADDRS { DSC1_BASE, DSC2_BASE, DSC3_BASE, DSC4_BASE, DSC5_BASE, DSC6_BASE, DSC7_BASE, DSC8_BASE, DSC9_BASE, DSC10_BASE, DSC11_BASE, DSC12_BASE, DSC13_BASE, DSC14_BASE, DSC15_BASE, DSC17_BASE, DSC18_BASE, DSC19_BASE, DSC20_BASE, DSC21_BASE, DSC22_BASE, DSC23_BASE, DSC24_BASE, DSC25_BASE, DSC26_BASE, DSC27_BASE, DSC28_BASE, DSC29_BASE, DSC30_BASE, DSC31_BASE, DSC33_BASE, DSC34_BASE, DSC35_BASE, DSC36_BASE, DSC37_BASE, DSC38_BASE, DSC39_BASE, DSC40_BASE, DSC41_BASE, DSC42_BASE, DSC43_BASE, DSC44_BASE, DSC45_BASE, DSC46_BASE, DSC47_BASE, DSC49_BASE, DSC50_BASE, DSC51_BASE, DSC52_BASE, DSC53_BASE, DSC54_BASE, DSC55_BASE, DSC56_BASE, DSC57_BASE, DSC58_BASE, DSC59_BASE, DSC60_BASE, DSC61_BASE, DSC62_BASE, DSC63_BASE } +/** Array initializer of DSC peripheral base pointers */ +#define DSC_BASE_PTRS { DSC1, DSC2, DSC3, DSC4, DSC5, DSC6, DSC7, DSC8, DSC9, DSC10, DSC11, DSC12, DSC13, DSC14, DSC15, DSC17, DSC18, DSC19, DSC20, DSC21, DSC22, DSC23, DSC24, DSC25, DSC26, DSC27, DSC28, DSC29, DSC30, DSC31, DSC33, DSC34, DSC35, DSC36, DSC37, DSC38, DSC39, DSC40, DSC41, DSC42, DSC43, DSC44, DSC45, DSC46, DSC47, DSC49, DSC50, DSC51, DSC52, DSC53, DSC54, DSC55, DSC56, DSC57, DSC58, DSC59, DSC60, DSC61, DSC62, DSC63 } + +/*! + * @} + */ /* end of group DSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MSI_MSTR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MSI_MSTR_Peripheral_Access_Layer MSI_MSTR Peripheral Access Layer + * @{ + */ + +/** MSI_MSTR - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEBUG0; /**< AHB address of last transaction from AHB error response, offset: 0x0 */ + __IO uint32_t DEBUG1; /**< AHB command of last transaction from AHB error response, offset: 0x4 */ + __IO uint32_t CTRL0; /**< MSI Master Control, offset: 0x8 */ + __IO uint32_t CTRL1; /**< MSI Master Control, offset: 0xC */ + struct { /* offset: 0x10 */ + __IO uint32_t RW; /**< MSI IRQ Mask, offset: 0x10 */ + __IO uint32_t SET; /**< MSI IRQ Mask, offset: 0x14 */ + __IO uint32_t CLR; /**< MSI IRQ Mask, offset: 0x18 */ + __IO uint32_t TOG; /**< MSI IRQ Mask, offset: 0x1C */ + } IRQ_MASK; + struct { /* offset: 0x20 */ + __IO uint32_t RW; /**< MSI IRQ, offset: 0x20 */ + __IO uint32_t SET; /**< MSI IRQ, offset: 0x24 */ + __IO uint32_t CLR; /**< MSI IRQ, offset: 0x28 */ + __IO uint32_t TOG; /**< MSI IRQ, offset: 0x2C */ + } IRQ; + struct { /* offset: 0x30 */ + __I uint32_t RW; /**< MSI IRQ Masked Status, offset: 0x30 */ + __I uint32_t SET; /**< MSI IRQ Masked Status, offset: 0x34 */ + __I uint32_t CLR; /**< MSI IRQ Masked Status, offset: 0x38 */ + __I uint32_t TOG; /**< MSI IRQ Masked Status, offset: 0x3C */ + } IRQ_MASK_STATUS; + __I uint32_t STATUS; /**< MSI Master Control STATUS, offset: 0x40 */ +} MSI_MSTR_Type; + +/* ---------------------------------------------------------------------------- + -- MSI_MSTR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MSI_MSTR_Register_Masks MSI_MSTR Register Masks + * @{ + */ + +/*! @name DEBUG0 - AHB address of last transaction from AHB error response */ +#define MSI_MSTR_DEBUG0_HADDR_MASK (0xFFFFFFFFU) +#define MSI_MSTR_DEBUG0_HADDR_SHIFT (0U) +#define MSI_MSTR_DEBUG0_HADDR(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_DEBUG0_HADDR_SHIFT)) & MSI_MSTR_DEBUG0_HADDR_MASK) + +/*! @name DEBUG1 - AHB command of last transaction from AHB error response */ +#define MSI_MSTR_DEBUG1_HBURST_MASK (0x7U) +#define MSI_MSTR_DEBUG1_HBURST_SHIFT (0U) +#define MSI_MSTR_DEBUG1_HBURST(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_DEBUG1_HBURST_SHIFT)) & MSI_MSTR_DEBUG1_HBURST_MASK) +#define MSI_MSTR_DEBUG1_HSIZE_MASK (0x38U) +#define MSI_MSTR_DEBUG1_HSIZE_SHIFT (3U) +#define MSI_MSTR_DEBUG1_HSIZE(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_DEBUG1_HSIZE_SHIFT)) & MSI_MSTR_DEBUG1_HSIZE_MASK) +#define MSI_MSTR_DEBUG1_HWRITE_MASK (0x40U) +#define MSI_MSTR_DEBUG1_HWRITE_SHIFT (6U) +#define MSI_MSTR_DEBUG1_HWRITE(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_DEBUG1_HWRITE_SHIFT)) & MSI_MSTR_DEBUG1_HWRITE_MASK) + +/*! @name CTRL0 - MSI Master Control */ +#define MSI_MSTR_CTRL0_RESET_KICK_MASK (0x1U) +#define MSI_MSTR_CTRL0_RESET_KICK_SHIFT (0U) +#define MSI_MSTR_CTRL0_RESET_KICK(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_CTRL0_RESET_KICK_SHIFT)) & MSI_MSTR_CTRL0_RESET_KICK_MASK) +#define MSI_MSTR_CTRL0_WR_BURST_CONVERT_MASK (0x2U) +#define MSI_MSTR_CTRL0_WR_BURST_CONVERT_SHIFT (1U) +#define MSI_MSTR_CTRL0_WR_BURST_CONVERT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_CTRL0_WR_BURST_CONVERT_SHIFT)) & MSI_MSTR_CTRL0_WR_BURST_CONVERT_MASK) +#define MSI_MSTR_CTRL0_RD_BURST_CONVERT_MASK (0x4U) +#define MSI_MSTR_CTRL0_RD_BURST_CONVERT_SHIFT (2U) +#define MSI_MSTR_CTRL0_RD_BURST_CONVERT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_CTRL0_RD_BURST_CONVERT_SHIFT)) & MSI_MSTR_CTRL0_RD_BURST_CONVERT_MASK) +#define MSI_MSTR_CTRL0_POST_WR_LIMIT_MASK (0x1FF8U) +#define MSI_MSTR_CTRL0_POST_WR_LIMIT_SHIFT (3U) +#define MSI_MSTR_CTRL0_POST_WR_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_CTRL0_POST_WR_LIMIT_SHIFT)) & MSI_MSTR_CTRL0_POST_WR_LIMIT_MASK) + +/*! @name CTRL1 - MSI Master Control */ +#define MSI_MSTR_CTRL1_TIMEOUT_COUNT_MASK (0xFFFFFU) +#define MSI_MSTR_CTRL1_TIMEOUT_COUNT_SHIFT (0U) +#define MSI_MSTR_CTRL1_TIMEOUT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_CTRL1_TIMEOUT_COUNT_SHIFT)) & MSI_MSTR_CTRL1_TIMEOUT_COUNT_MASK) + +/*! @name IRQ_MASK - MSI IRQ Mask */ +#define MSI_MSTR_IRQ_MASK_MSI_MSTR_ERROR_MASK (0x1U) +#define MSI_MSTR_IRQ_MASK_MSI_MSTR_ERROR_SHIFT (0U) +#define MSI_MSTR_IRQ_MASK_MSI_MSTR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_IRQ_MASK_MSI_MSTR_ERROR_SHIFT)) & MSI_MSTR_IRQ_MASK_MSI_MSTR_ERROR_MASK) +#define MSI_MSTR_IRQ_MASK_AHB_TIMEOUT_MASK (0x2U) +#define MSI_MSTR_IRQ_MASK_AHB_TIMEOUT_SHIFT (1U) +#define MSI_MSTR_IRQ_MASK_AHB_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_IRQ_MASK_AHB_TIMEOUT_SHIFT)) & MSI_MSTR_IRQ_MASK_AHB_TIMEOUT_MASK) + +/*! @name IRQ - MSI IRQ */ +#define MSI_MSTR_IRQ_MSI_MSTR_ERROR_MASK (0x1U) +#define MSI_MSTR_IRQ_MSI_MSTR_ERROR_SHIFT (0U) +#define MSI_MSTR_IRQ_MSI_MSTR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_IRQ_MSI_MSTR_ERROR_SHIFT)) & MSI_MSTR_IRQ_MSI_MSTR_ERROR_MASK) +#define MSI_MSTR_IRQ_AHB_TIMEOUT_MASK (0x2U) +#define MSI_MSTR_IRQ_AHB_TIMEOUT_SHIFT (1U) +#define MSI_MSTR_IRQ_AHB_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_IRQ_AHB_TIMEOUT_SHIFT)) & MSI_MSTR_IRQ_AHB_TIMEOUT_MASK) + +/*! @name IRQ_MASK_STATUS - MSI IRQ Masked Status */ +#define MSI_MSTR_IRQ_MASK_STATUS_MSI_MSTR_ERROR_MASK (0x1U) +#define MSI_MSTR_IRQ_MASK_STATUS_MSI_MSTR_ERROR_SHIFT (0U) +#define MSI_MSTR_IRQ_MASK_STATUS_MSI_MSTR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_IRQ_MASK_STATUS_MSI_MSTR_ERROR_SHIFT)) & MSI_MSTR_IRQ_MASK_STATUS_MSI_MSTR_ERROR_MASK) +#define MSI_MSTR_IRQ_MASK_STATUS_AHB_TIMEOUT_MASK (0x2U) +#define MSI_MSTR_IRQ_MASK_STATUS_AHB_TIMEOUT_SHIFT (1U) +#define MSI_MSTR_IRQ_MASK_STATUS_AHB_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_IRQ_MASK_STATUS_AHB_TIMEOUT_SHIFT)) & MSI_MSTR_IRQ_MASK_STATUS_AHB_TIMEOUT_MASK) + +/*! @name STATUS - MSI Master Control STATUS */ +#define MSI_MSTR_STATUS_OTC_CNT_GT0_MASK (0x1U) +#define MSI_MSTR_STATUS_OTC_CNT_GT0_SHIFT (0U) +#define MSI_MSTR_STATUS_OTC_CNT_GT0(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_STATUS_OTC_CNT_GT0_SHIFT)) & MSI_MSTR_STATUS_OTC_CNT_GT0_MASK) +#define MSI_MSTR_STATUS_AHB_WR_OTC_CNT_MASK (0xFFEU) +#define MSI_MSTR_STATUS_AHB_WR_OTC_CNT_SHIFT (1U) +#define MSI_MSTR_STATUS_AHB_WR_OTC_CNT(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_STATUS_AHB_WR_OTC_CNT_SHIFT)) & MSI_MSTR_STATUS_AHB_WR_OTC_CNT_MASK) +#define MSI_MSTR_STATUS_POST_WR_TIMEOUT_ERROR_MASK (0x1000U) +#define MSI_MSTR_STATUS_POST_WR_TIMEOUT_ERROR_SHIFT (12U) +#define MSI_MSTR_STATUS_POST_WR_TIMEOUT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << MSI_MSTR_STATUS_POST_WR_TIMEOUT_ERROR_SHIFT)) & MSI_MSTR_STATUS_POST_WR_TIMEOUT_ERROR_MASK) + + +/*! + * @} + */ /* end of group MSI_MSTR_Register_Masks */ + + +/* MSI_MSTR - Peripheral instance base addresses */ +/** Peripheral msi_mstr base pointer */ +#define MSI0 ((MSI_MSTR_Type *)MSI0_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI1 ((MSI_MSTR_Type *)MSI1_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI2 ((MSI_MSTR_Type *)MSI2_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI3 ((MSI_MSTR_Type *)MSI3_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI4 ((MSI_MSTR_Type *)MSI4_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI5 ((MSI_MSTR_Type *)MSI5_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI6 ((MSI_MSTR_Type *)MSI6_BASE) +/** Peripheral msi_mstr base pointer */ +#define MSI7 ((MSI_MSTR_Type *)MSI7_BASE) +/** Array initializer of MSI_MSTR peripheral base addresses */ +#define MSI_MSTR_BASE_ADDRS { MSI0_BASE, MSI1_BASE, MSI2_BASE, MSI3_BASE, MSI4_BASE, MSI5_BASE, MSI6_BASE, MSI7_BASE } +/** Array initializer of MSI_MSTR peripheral base pointers */ +#define MSI_MSTR_BASE_PTRS { MSI0, MSI1, MSI2, MSI3, MSI4, MSI5, MSI6, MSI7 } + +/*! + * @} + */ /* end of group MSI_MSTR_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* HW_DSC_REGISTERS_H */ + diff --git a/platform/devices/MX8/MX8_dsc_ai.h b/platform/devices/MX8/MX8_dsc_ai.h new file mode 100755 index 0000000..ae9fe5a --- /dev/null +++ b/platform/devices/MX8/MX8_dsc_ai.h @@ -0,0 +1,1211 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file MX8_dsc_ai.h.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for teh DSC AI + * + * CMSIS Peripheral Access Layer for the DSC AI + */ + +#ifndef HW_DSC_AI_REGISTERS_H +#define HW_DSC_AI_REGISTERS_H /**< Symbol preventing repeated inclusion */ + +// AI - Fractional PLL Local Control Register Memory Map +#define AI_FRAC_PLL_LOCAL_CTRL 0x00U +#define AI_FRAC_PLL_LOCAL_SPECTRUM 0x10U +#define AI_FRAC_PLL_LOCAL_NUMERATOR 0x20U +#define AI_FRAC_PLL_LOCAL_DENOMINATOR 0x30U + + +// AI Toggle Map + +#define AI_PLL0_TOGGLE (0U) +#define AI_PLL1_TOGGLE (1U) +#define AI_PLL2_TOGGLE (2U) +#define AI_OSC24M_TOGGLE (3U) +#define AI_RC200OSC_TOGGLE (4U) +#define AI_VDROP_PROCMON_TOGGLE (5U) +#define AI_TEMP_SENSE_TOGGLE (6U) +#define AI_LVDS_TRANS_TOGGLE (7U) +#define AI_NEG_CHARGE_PUMP_TOGGLE (8U) +#define AI_WELL_LEVEL_SOURCE_TOGGLE (9U) +#define AI_BANDGAP_REF_TOGGLE (10U) +#define AI_VA_REFGEN_TOGGLE (11U) +#define AI_DIFFCLK_RPTR_TOGGLE (12U) +#define AI_DIFFCLK_ROOT_TOGGLE (13U) +#define AI_DIFFCLK_TERM_TOGGLE (14U) +#define AI_DIFFCLK_RPTR1_TOGGLE (15U) +#define AI_PHY_PLL0_TOGGLE (16U) +#define AI_PHY_PLL1_TOGGLE (17U) +#define AI_PHY_LDO0_TOGGLE (18U) +#define AI_PHY_LDO1_TOGGLE (19U) +#define AI_PHY_LVDS_TRANS_TOGGLE (20U) +#define AI_PHY_BANDGAP_REF_TOGGLE (21U) +#define AI_PHY_VA_REFGEN_TOGGLE (22U) +#define AI_PHY_DIFFCLK_RPTR_TOGGLE (23U) +#define AI_PHY_DIFFCLK_ROOT0_TOGGLE (24U) +#define AI_PHY_DIFFCLK_ROOT1_TOGGLE (25U) +#define AI_PHY_DIFFCLK_ROOT2_TOGGLE (26U) +#define AI_PHY_DIFFCLK_TERM0_TOGGLE (27U) +#define AI_PHY_DIFFCLK_TERM1_TOGGLE (28U) +#define AI_PHY_DIFFCLK_TERM2_TOGGLE (29U) +#define AI_PHY_DIFFCLK_TERM3_TOGGLE (30U) +#define AI_PHY_LDO2_TOGGLE (31U) + + +// Generic AI + +#define AI_GENERIC_CTRL0_ADDR (0x0000U) +#define AI_GENERIC_CTRL0_SET_ADDR (0x0004U) +#define AI_GENERIC_CTRL0_CLEAR_ADDR (0x0008U) +#define AI_GENERIC_CTRL0_TOGGLE_ADDR (0x000cU) +#define AI_GENERIC_CTRL1_ADDR (0x0010U) +#define AI_GENERIC_CTRL1_SET_ADDR (0x0014U) +#define AI_GENERIC_CTRL1_CLEAR_ADDR (0x0018U) +#define AI_GENERIC_CTRL1_TOGGLE_ADDR (0x001cU) +#define AI_GENERIC_CTRL2_ADDR (0x0020U) +#define AI_GENERIC_CTRL2_SET_ADDR (0x0024U) +#define AI_GENERIC_CTRL2_CLEAR_ADDR (0x0028U) +#define AI_GENERIC_CTRL2_TOGGLE_ADDR (0x002cU) +#define AI_GENERIC_CTRL3_ADDR (0x0030U) +#define AI_GENERIC_CTRL3_SET_ADDR (0x0034U) +#define AI_GENERIC_CTRL3_CLEAR_ADDR (0x0038U) +#define AI_GENERIC_CTRL3_TOGGLE_ADDR (0x003cU) +#define AI_GENERIC_CTRL4_ADDR (0x0040U) +#define AI_GENERIC_CTRL4_SET_ADDR (0x0044U) +#define AI_GENERIC_CTRL4_CLEAR_ADDR (0x0048U) +#define AI_GENERIC_CTRL4_TOGGLE_ADDR (0x004cU) +#define AI_GENERIC_STAT0_ADDR (0x0050U) +#define AI_GENERIC_STAT1_ADDR (0x0060U) +#define AI_GENERIC_STAT2_ADDR (0x0070U) + +#define AI_HP_PLL_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_HP_PLL_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_HP_PLL_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_HP_PLL_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_HP_PLL_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_OSC24M_CTRLOSC_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_OSC24M_CTRLOSC_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_OSC24M_CTRLOSC_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_OSC24M_CTRLOSC_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_OSC24M_STATOSC_ADDR (AI_GENERIC_STAT0_ADDR) +#define AI_OSC24M_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_RC200OSC_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_RC200OSC_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_RC200OSC_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_RC200OSC_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_RC200OSC_CTRL1_ADDR (AI_GENERIC_CTRL1_ADDR) +#define AI_RC200OSC_CTRL1_SET_ADDR (AI_GENERIC_CTRL1_SET_ADDR) +#define AI_RC200OSC_CTRL1_CLEAR_ADDR (AI_GENERIC_CTRL1_CLEAR_ADDR) +#define AI_RC200OSC_CTRL1_TOGGLE_ADDR (AI_GENERIC_CTRL1_TOGGLE_ADDR) +#define AI_RC200OSC_CTRL2_ADDR (AI_GENERIC_CTRL2_ADDR) +#define AI_RC200OSC_CTRL2_SET_ADDR (AI_GENERIC_CTRL2_SET_ADDR) +#define AI_RC200OSC_CTRL2_CLEAR_ADDR (AI_GENERIC_CTRL2_CLEAR_ADDR) +#define AI_RC200OSC_CTRL2_TOGGLE_ADDR (AI_GENERIC_CTRL2_TOGGLE_ADDR) +#define AI_RC200OSC_CTRL3_ADDR (AI_GENERIC_CTRL3_ADDR) +#define AI_RC200OSC_CTRL3_SET_ADDR (AI_GENERIC_CTRL3_SET_ADDR) +#define AI_RC200OSC_CTRL3_CLEAR_ADDR (AI_GENERIC_CTRL3_CLEAR_ADDR) +#define AI_RC200OSC_CTRL3_TOGGLE_ADDR (AI_GENERIC_CTRL3_TOGGLE_ADDR) +#define AI_RC200OSC_CTRL4_ADDR (AI_GENERIC_CTRL4_ADDR) +#define AI_RC200OSC_CTRL4_SET_ADDR (AI_GENERIC_CTRL4_SET_ADDR) +#define AI_RC200OSC_CTRL4_CLEAR_ADDR (AI_GENERIC_CTRL4_CLEAR_ADDR) +#define AI_RC200OSC_CTRL4_TOGGLE_ADDR (AI_GENERIC_CTRL4_TOGGLE_ADDR) +#define AI_RC200OSC_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) +#define AI_RC200OSC_STAT1_ADDR (AI_GENERIC_STAT1_ADDR) +#define AI_RC200OSC_STAT2_ADDR (AI_GENERIC_STAT2_ADDR) + +#define AI_LVDS_TRANS_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_LVDS_TRANS_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_LVDS_TRANS_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_LVDS_TRANS_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_LVDS_TRANS_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_NEG_CHARGE_PUMP_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_NEG_CHARGE_PUMP_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_NEG_CHARGE_PUMP_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_NEG_CHARGE_PUMP_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_NEG_CHARGE_PUMP_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_WELL_LEVEL_SOURCE_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_WELL_LEVEL_SOURCE_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_WELL_LEVEL_SOURCE_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_WELL_LEVEL_SOURCE_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_BANDGAP_REF_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_BANDGAP_REF_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_BANDGAP_REF_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_BANDGAP_REF_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_BANDGAP_REF_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_VA_REFGEN_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_VA_REFGEN_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_VA_REFGEN_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_VA_REFGEN_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_VA_REFGEN_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_DIFFCLK_RPTR_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_DIFFCLK_RPTR_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_DIFFCLK_RPTR_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_DIFFCLK_RPTR_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_DIFFCLK_RPTR_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_DIFFCLK_ROOT_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_DIFFCLK_ROOT_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_DIFFCLK_ROOT_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_DIFFCLK_ROOT_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_DIFFCLK_ROOT_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_DIFFCLK_TERM_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_DIFFCLK_TERM_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_DIFFCLK_TERM_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_DIFFCLK_TERM_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_DIFFCLK_TERM_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_AV_PLL_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_AV_PLL_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_AV_PLL_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_AV_PLL_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_AV_PLL_SPREAD_SPECTRUM_ADDR (AI_GENERIC_CTRL1_ADDR) +#define AI_AV_PLL_SPREAD_SPECTRUM_SET_ADDR (AI_GENERIC_CTRL1_SET_ADDR) +#define AI_AV_PLL_SPREAD_SPECTRUM_CLEAR_ADDR (AI_GENERIC_CTRL1_CLEAR_ADDR) +#define AI_AV_PLL_SPREAD_SPECTRUM_TOGGLE_ADDR (AI_GENERIC_CTRL1_TOGGLE_ADDR) +#define AI_AV_PLL_NUMERATOR_ADDR (AI_GENERIC_CTRL2_ADDR) +#define AI_AV_PLL_NUMERATOR_SET_ADDR (AI_GENERIC_CTRL2_SET_ADDR) +#define AI_AV_PLL_NUMERATOR_CLEAR_ADDR (AI_GENERIC_CTRL2_CLEAR_ADDR) +#define AI_AV_PLL_NUMERATOR_TOGGLE_ADDR (AI_GENERIC_CTRL2_TOGGLE_ADDR) +#define AI_AV_PLL_DENOMINATOR_ADDR (AI_GENERIC_CTRL3_ADDR) +#define AI_AV_PLL_DENOMINATOR_SET_ADDR (AI_GENERIC_CTRL3_SET_ADDR) +#define AI_AV_PLL_DENOMINATOR_CLEAR_ADDR (AI_GENERIC_CTRL3_CLEAR_ADDR) +#define AI_AV_PLL_DENOMINATOR_TOGGLE_ADDR (AI_GENERIC_CTRL3_TOGGLE_ADDR) +#define AI_AV_PLL_CTRL4_ADDR (AI_GENERIC_CTRL4_ADDR) +#define AI_AV_PLL_CTRL4_SET_ADDR (AI_GENERIC_CTRL4_SET_ADDR) +#define AI_AV_PLL_CTRL4_CLEAR_ADDR (AI_GENERIC_CTRL4_CLEAR_ADDR) +#define AI_AV_PLL_CTRL4_TOGGLE_ADDR (AI_GENERIC_CTRL4_TOGGLE_ADDR) +#define AI_AV_PLL_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) +#define AI_AV_PLL_STAT1_ADDR (AI_GENERIC_STAT1_ADDR) +#define AI_AV_PLL_STAT2_ADDR (AI_GENERIC_STAT2_ADDR) + +#define AI_MLB_PLL_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_MLB_PLL_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_MLB_PLL_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_MLB_PLL_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_MLB_PLL_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + +#define AI_PHY_LDO_CTRL0_ADDR (AI_GENERIC_CTRL0_ADDR) +#define AI_PHY_LDO_CTRL0_SET_ADDR (AI_GENERIC_CTRL0_SET_ADDR) +#define AI_PHY_LDO_CTRL0_CLEAR_ADDR (AI_GENERIC_CTRL0_CLEAR_ADDR) +#define AI_PHY_LDO_CTRL0_TOGGLE_ADDR (AI_GENERIC_CTRL0_TOGGLE_ADDR) +#define AI_PHY_LDO_STAT0_ADDR (AI_GENERIC_STAT0_ADDR) + + +// Custom AI + +#define AI_DIG_PLL_DIV_CTRL_ADDR (0x0000U) +#define AI_DIG_PLL_MFN_ADDR (0x0004U) +#define AI_DIG_PLL_MFD_ADDR (0x0008U) +#define AI_DIG_PLL_SSC_ADDR (0x000cU) +#define AI_DIG_PLL_LPF_CTRL_ADDR (0x0010U) +#define AI_DIG_PLL_LPF_CTRL_SET_ADDR (0x0014U) +#define AI_DIG_PLL_LPF_CTRL_CLR_ADDR (0x0018U) +#define AI_DIG_PLL_LPF_CTRL_TOG_ADDR (0x001cU) +#define AI_DIG_PLL_DCO_CTRL_ADDR (0x0020U) +#define AI_DIG_PLL_DCO_CTRL_SET_ADDR (0x0024U) +#define AI_DIG_PLL_DCO_CTRL_CLR_ADDR (0x0028U) +#define AI_DIG_PLL_DCO_CTRL_TOG_ADDR (0x002cU) +#define AI_DIG_PLL_CTRL_ADDR (0x0030U) +#define AI_DIG_PLL_CTRL_SET_ADDR (0x0034U) +#define AI_DIG_PLL_CTRL_CLR_ADDR (0x0038U) +#define AI_DIG_PLL_CTRL_TOG_ADDR (0x003cU) +#define AI_DIG_PLL_CTRL2_ADDR (0x0040U) +#define AI_DIG_PLL_CTRL2_SET_ADDR (0x0044U) +#define AI_DIG_PLL_CTRL2_CLR_ADDR (0x0048U) +#define AI_DIG_PLL_CTRL2_TOG_ADDR (0x004cU) +#define AI_DIG_PLL_CTRL3_ADDR (0x0050U) +#define AI_DIG_PLL_CTRL3_SET_ADDR (0x0054U) +#define AI_DIG_PLL_CTRL3_CLR_ADDR (0x0058U) +#define AI_DIG_PLL_CTRL3_TOG_ADDR (0x005cU) +#define AI_DIG_PLL_STATUS_ADDR (0x0060U) +#define AI_DIG_PLL_SPARE_ADDR (0x0070U) + +#define AI_DIG_PLL_DIV_CTRL_RESET (0x00000028U) +#define AI_DIG_PLL_MFN_RESET (0x00000000U) +#define AI_DIG_PLL_MFD_RESET (0x0000ffffU) +#define AI_DIG_PLL_SSC_RESET (0x00000000U) +#define AI_DIG_PLL_LPF_CTRL_RESET (0x10005026U) +#define AI_DIG_PLL_DCO_CTRL_RESET (0x0400c040U) +#define AI_DIG_PLL_CTRL_RESET (0x0f040000U) +#define AI_DIG_PLL_CTRL2_RESET (0x00030400U) +#define AI_DIG_PLL_CTRL3_RESET (0x01000100U) +#define AI_DIG_PLL_STATUS_RESET (0x00000000U) + +#define AI_DIG_PLL_DIV_CTRL_MASK (0x0000007fU) +#define AI_DIG_PLL_MFN_MASK (0x3fffffffU) +#define AI_DIG_PLL_MFD_MASK (0x3fffffffU) +#define AI_DIG_PLL_SSC_MASK (0x00ffffffU) +#define AI_DIG_PLL_LPF_CTRL_MASK (0xfffff777U) +#define AI_DIG_PLL_DCO_CTRL_MASK (0xff01ff7fU) +#define AI_DIG_PLL_CTRL_MASK (0xffffffffU) +#define AI_DIG_PLL_CTRL2_MASK (0x7ff7ffffU) +#define AI_DIG_PLL_CTRL3_MASK (0xf9c0ffffU) +#define AI_DIG_PLL_STATUS_MASK (0x01ff7f0fU) + +#define AI_VDROP_PROCMON_CTRL0_ADDR (0x0000U) +#define AI_VDROP_PROCMON_CTRL0_SET_ADDR (0x0004U) +#define AI_VDROP_PROCMON_CTRL0_CLEAR_ADDR (0x0008U) +#define AI_VDROP_PROCMON_CTRL0_TOGGLE_ADDR (0x000cU) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_ADDR (0x0010U) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_SET_ADDR (0x0014U) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_CLEAR_ADDR (0x0018U) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_TOGGLE_ADDR (0x001cU) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADDR (0x0020U) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_SET_ADDR (0x0024U) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_CLEAR_ADDR (0x0028U) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_TOGGLE_ADDR (0x002cU) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_ADDR (0x0030U) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_SET_ADDR (0x0034U) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_CLEAR_ADDR (0x0038U) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_TOGGLE_ADDR (0x003cU) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_ADDR (0x0040U) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_SET_ADDR (0x0044U) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_CLEAR_ADDR (0x0048U) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_TOGGLE_ADDR (0x004cU) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_ADDR (0x0050U) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_SET_ADDR (0x0054U) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_CLEAR_ADDR (0x0058U) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_TOGGLE_ADDR (0x005cU) +#define AI_VDROP_PROCMON_DEBUG_STATUS_ADDR (0x0060U) + +#define AI_TEMP_SENSE_CTRL0_ADDR (0x0000U) +#define AI_TEMP_SENSE_CTRL0_SET_ADDR (0x0004U) +#define AI_TEMP_SENSE_CTRL0_CLEAR_ADDR (0x0008U) +#define AI_TEMP_SENSE_CTRL0_TOGGLE_ADDR (0x000cU) +#define AI_TEMP_SENSE_CTRL1_ADDR (0x0010U) +#define AI_TEMP_SENSE_CTRL1_SET_ADDR (0x0014U) +#define AI_TEMP_SENSE_CTRL1_CLEAR_ADDR (0x0018U) +#define AI_TEMP_SENSE_CTRL1_TOGGLE_ADDR (0x001cU) +#define AI_TEMP_SENSE_RANGE0_ADDR (0x0020U) +#define AI_TEMP_SENSE_RANGE0_SET_ADDR (0x0024U) +#define AI_TEMP_SENSE_RANGE0_CLEAR_ADDR (0x0028U) +#define AI_TEMP_SENSE_RANGE0_TOGGLE_ADDR (0x002cU) +#define AI_TEMP_SENSE_RANGE1_ADDR (0x0030U) +#define AI_TEMP_SENSE_RANGE1_SET_ADDR (0x0034U) +#define AI_TEMP_SENSE_RANGE1_CLEAR_ADDR (0x0038U) +#define AI_TEMP_SENSE_RANGE1_TOGGLE_ADDR (0x003cU) +#define AI_TEMP_SENSE_OFFSET_COMP_ADDR (0x0040U) +#define AI_TEMP_SENSE_OFFSET_COMP_SET_ADDR (0x0044U) +#define AI_TEMP_SENSE_OFFSET_COMP_CLEAR_ADDR (0x0048U) +#define AI_TEMP_SENSE_OFFSET_COMP_TOGGLE_ADDR (0x004cU) +#define AI_TEMP_SENSE_STATUS0_ADDR (0x0050U) +#define AI_TEMP_SENSE_STATUS0_SET_ADDR (0x0054U) +#define AI_TEMP_SENSE_STATUS0_CLEAR_ADDR (0x0058U) +#define AI_TEMP_SENSE_STATUS0_TOGGLE_ADDR (0x005cU) + +// AI Registers + +#define AI_DIG_PLL_DIV_CTRL_MFI_MASK (0x7FU) +#define AI_DIG_PLL_DIV_CTRL_MFI_SHIFT (0U) +#define AI_DIG_PLL_DIV_CTRL_MFI(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_DIV_CTRL_MFI_SHIFT)) & AI_DIG_PLL_DIV_CTRL_MFI_MASK) +#define AI_DIG_PLL_MFN_VALUE_MASK (0x3FFFFFFFU) +#define AI_DIG_PLL_MFN_VALUE_SHIFT (0U) +#define AI_DIG_PLL_MFN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_MFN_VALUE_SHIFT)) & AI_DIG_PLL_MFN_VALUE_MASK) +#define AI_DIG_PLL_MFD_VALUE_MASK (0x3FFFFFFFU) +#define AI_DIG_PLL_MFD_VALUE_SHIFT (0U) +#define AI_DIG_PLL_MFD_VALUE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_MFD_VALUE_SHIFT)) & AI_DIG_PLL_MFD_VALUE_MASK) +#define AI_DIG_PLL_SSC_STEP_MASK (0xFFFU) +#define AI_DIG_PLL_SSC_STEP_SHIFT (0U) +#define AI_DIG_PLL_SSC_STEP(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_SSC_STEP_SHIFT)) & AI_DIG_PLL_SSC_STEP_MASK) +#define AI_DIG_PLL_SSC_STOP_MASK (0xFFF000U) +#define AI_DIG_PLL_SSC_STOP_SHIFT (12U) +#define AI_DIG_PLL_SSC_STOP(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_SSC_STOP_SHIFT)) & AI_DIG_PLL_SSC_STOP_MASK) +#define AI_DIG_PLL_LPF_CTRL_KP_MASK (0x7U) +#define AI_DIG_PLL_LPF_CTRL_KP_SHIFT (0U) +#define AI_DIG_PLL_LPF_CTRL_KP(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_KP_SHIFT)) & AI_DIG_PLL_LPF_CTRL_KP_MASK) +#define AI_DIG_PLL_LPF_CTRL_KI_MASK (0x70U) +#define AI_DIG_PLL_LPF_CTRL_KI_SHIFT (4U) +#define AI_DIG_PLL_LPF_CTRL_KI(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_KI_SHIFT)) & AI_DIG_PLL_LPF_CTRL_KI_MASK) +#define AI_DIG_PLL_LPF_CTRL_KD_MASK (0x700U) +#define AI_DIG_PLL_LPF_CTRL_KD_SHIFT (8U) +#define AI_DIG_PLL_LPF_CTRL_KD(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_KD_SHIFT)) & AI_DIG_PLL_LPF_CTRL_KD_MASK) +#define AI_DIG_PLL_LPF_CTRL_KN_MASK (0xf000U) +#define AI_DIG_PLL_LPF_CTRL_KN_SHIFT (12U) +#define AI_DIG_PLL_LPF_CTRL_KN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_KN_SHIFT)) & AI_DIG_PLL_LPF_CTRL_KN_MASK) +#define AI_DIG_PLL_LPF_CTRL_FLOCK_BYP_MASK (0x10000U) +#define AI_DIG_PLL_LPF_CTRL_FLOCK_BYP_SHIFT (16U) +#define AI_DIG_PLL_LPF_CTRL_FLOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_FLOCK_BYP_SHIFT)) & AI_DIG_PLL_LPF_CTRL_FLOCK_BYP_MASK) +#define AI_DIG_PLL_LPF_CTRL_KE_MASK (0x60000U) +#define AI_DIG_PLL_LPF_CTRL_KE_SHIFT (17U) +#define AI_DIG_PLL_LPF_CTRL_KE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_KE_SHIFT)) & AI_DIG_PLL_LPF_CTRL_KE_MASK) +#define AI_DIG_PLL_LPF_CTRL_KC_MASK (0x7FF80000U) +#define AI_DIG_PLL_LPF_CTRL_KC_SHIFT (19U) +#define AI_DIG_PLL_LPF_CTRL_KC(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_KC_SHIFT)) & AI_DIG_PLL_LPF_CTRL_KC_MASK) +#define AI_DIG_PLL_LPF_CTRL_FINE_PLOCK_MASK (0x80000000U) +#define AI_DIG_PLL_LPF_CTRL_FINE_PLOCK_SHIFT (31U) +#define AI_DIG_PLL_LPF_CTRL_FINE_PLOCK(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_LPF_CTRL_FINE_PLOCK_SHIFT)) & AI_DIG_PLL_LPF_CTRL_FINE_PLOCK_MASK) +#define AI_DIG_PLL_DCO_CTRL_FC_DS_MASK (0x7FU) +#define AI_DIG_PLL_DCO_CTRL_FC_DS_SHIFT (0U) +#define AI_DIG_PLL_DCO_CTRL_FC_DS(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_DCO_CTRL_FC_DS_SHIFT)) & AI_DIG_PLL_DCO_CTRL_FC_DS_MASK) +#define AI_DIG_PLL_DCO_CTRL_FC_UFINE_MASK (0x1FF00U) +#define AI_DIG_PLL_DCO_CTRL_FC_UFINE_SHIFT (8U) +#define AI_DIG_PLL_DCO_CTRL_FC_UFINE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_DCO_CTRL_FC_UFINE_SHIFT)) & AI_DIG_PLL_DCO_CTRL_FC_UFINE_MASK) +#define AI_DIG_PLL_DCO_CTRL_DCO_PC_MASK (0x7F000000U) +#define AI_DIG_PLL_DCO_CTRL_DCO_PC_SHIFT (24U) +#define AI_DIG_PLL_DCO_CTRL_DCO_PC(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_DCO_CTRL_DCO_PC_SHIFT)) & AI_DIG_PLL_DCO_CTRL_DCO_PC_MASK) +#define AI_DIG_PLL_DCO_CTRL_OVERRIDE_MASK (0x80000000U) +#define AI_DIG_PLL_DCO_CTRL_OVERRIDE_SHIFT (31U) +#define AI_DIG_PLL_DCO_CTRL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_DCO_CTRL_OVERRIDE_SHIFT)) & AI_DIG_PLL_DCO_CTRL_OVERRIDE_MASK) +#define AI_DIG_PLL_CTRL_DPLL_CLK_EN_MASK (0x1U) +#define AI_DIG_PLL_CTRL_DPLL_CLK_EN_SHIFT (0U) +#define AI_DIG_PLL_CTRL_DPLL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_DPLL_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_DPLL_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_DPLL_DIV_2_CLK_EN_MASK (0x2U) +#define AI_DIG_PLL_CTRL_DPLL_DIV_2_CLK_EN_SHIFT (1U) +#define AI_DIG_PLL_CTRL_DPLL_DIV_2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_DPLL_DIV_2_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_DPLL_DIV_2_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_DPLL_DIV_4_CLK_EN_MASK (0x4U) +#define AI_DIG_PLL_CTRL_DPLL_DIV_4_CLK_EN_SHIFT (2U) +#define AI_DIG_PLL_CTRL_DPLL_DIV_4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_DPLL_DIV_4_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_DPLL_DIV_4_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_DCO_CLK_EN_MASK (0x8U) +#define AI_DIG_PLL_CTRL_DCO_CLK_EN_SHIFT (3U) +#define AI_DIG_PLL_CTRL_DCO_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_DCO_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_DCO_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_PLL_TEST_MASK (0xFF0U) +#define AI_DIG_PLL_CTRL_PLL_TEST_SHIFT (4U) +#define AI_DIG_PLL_CTRL_PLL_TEST(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_PLL_TEST_SHIFT)) & AI_DIG_PLL_CTRL_PLL_TEST_MASK) +#define AI_DIG_PLL_CTRL_DCO_VCHP_DLY_MASK (0xF000U) +#define AI_DIG_PLL_CTRL_DCO_VCHP_DLY_SHIFT (12U) +#define AI_DIG_PLL_CTRL_DCO_VCHP_DLY(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_DCO_VCHP_DLY_SHIFT)) & AI_DIG_PLL_CTRL_DCO_VCHP_DLY_MASK) +#define AI_DIG_PLL_CTRL_REF_CLK_CNTR_MASK (0xF0000U) +#define AI_DIG_PLL_CTRL_REF_CLK_CNTR_SHIFT (16U) +#define AI_DIG_PLL_CTRL_REF_CLK_CNTR(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_REF_CLK_CNTR_SHIFT)) & AI_DIG_PLL_CTRL_REF_CLK_CNTR_MASK) +#define AI_DIG_PLL_CTRL_COARSE_BIT_DLY_MASK (0x3FF00000U) +#define AI_DIG_PLL_CTRL_COARSE_BIT_DLY_SHIFT (20U) +#define AI_DIG_PLL_CTRL_COARSE_BIT_DLY(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_COARSE_BIT_DLY_SHIFT)) & AI_DIG_PLL_CTRL_COARSE_BIT_DLY_MASK) +#define AI_DIG_PLL_CTRL_ENABLE_MASK (0x40000000U) +#define AI_DIG_PLL_CTRL_ENABLE_SHIFT (30U) +#define AI_DIG_PLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_ENABLE_SHIFT)) & AI_DIG_PLL_CTRL_ENABLE_MASK) +#define AI_DIG_PLL_CTRL_START_MASK (0x80000000U) +#define AI_DIG_PLL_CTRL_START_SHIFT (31U) +#define AI_DIG_PLL_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_START_SHIFT)) & AI_DIG_PLL_CTRL_START_MASK) + +#define AI_DIG_PLL_CTRL_SET_DPLL_CLK_EN_MASK (0x1U) +#define AI_DIG_PLL_CTRL_SET_DPLL_CLK_EN_SHIFT (0U) +#define AI_DIG_PLL_CTRL_SET_DPLL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_SET_DPLL_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_SET_DPLL_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_SET_DPLL_DIV_2_CLK_EN_MASK (0x2U) +#define AI_DIG_PLL_CTRL_SET_DPLL_DIV_2_CLK_EN_SHIFT (1U) +#define AI_DIG_PLL_CTRL_SET_DPLL_DIV_2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_SET_DPLL_DIV_2_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_SET_DPLL_DIV_2_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_SET_DPLL_DIV_4_CLK_EN_MASK (0x4U) +#define AI_DIG_PLL_CTRL_SET_DPLL_DIV_4_CLK_EN_SHIFT (2U) +#define AI_DIG_PLL_CTRL_SET_DPLL_DIV_4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_SET_DPLL_DIV_4_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_SET_DPLL_DIV_4_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_SET_DCO_CLK_EN_MASK (0x8U) +#define AI_DIG_PLL_CTRL_SET_DCO_CLK_EN_SHIFT (3U) +#define AI_DIG_PLL_CTRL_SET_DCO_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_SET_DCO_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_SET_DCO_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_SET_ENABLE_MASK (0x40000000U) +#define AI_DIG_PLL_CTRL_SET_ENABLE_SHIFT (30U) +#define AI_DIG_PLL_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_SET_ENABLE_SHIFT)) & AI_DIG_PLL_CTRL_SET_ENABLE_MASK) +#define AI_DIG_PLL_CTRL_SET_START_MASK (0x80000000U) +#define AI_DIG_PLL_CTRL_SET_START_SHIFT (31U) +#define AI_DIG_PLL_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_SET_START_SHIFT)) & AI_DIG_PLL_CTRL_SET_START_MASK) + +#define AI_DIG_PLL_CTRL_CLR_DPLL_CLK_EN_MASK (0x1U) +#define AI_DIG_PLL_CTRL_CLR_DPLL_CLK_EN_SHIFT (0U) +#define AI_DIG_PLL_CTRL_CLR_DPLL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_CLR_DPLL_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_CLR_DPLL_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_CLR_DPLL_DIV_2_CLK_EN_MASK (0x2U) +#define AI_DIG_PLL_CTRL_CLR_DPLL_DIV_2_CLK_EN_SHIFT (1U) +#define AI_DIG_PLL_CTRL_CLR_DPLL_DIV_2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_CLR_DPLL_DIV_2_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_CLR_DPLL_DIV_2_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_CLR_DPLL_DIV_4_CLK_EN_MASK (0x4U) +#define AI_DIG_PLL_CTRL_CLR_DPLL_DIV_4_CLK_EN_SHIFT (2U) +#define AI_DIG_PLL_CTRL_CLR_DPLL_DIV_4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_CLR_DPLL_DIV_4_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_CLR_DPLL_DIV_4_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_CLR_DCO_CLK_EN_MASK (0x8U) +#define AI_DIG_PLL_CTRL_CLR_DCO_CLK_EN_SHIFT (3U) +#define AI_DIG_PLL_CTRL_CLR_DCO_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_CLR_DCO_CLK_EN_SHIFT)) & AI_DIG_PLL_CTRL_CLR_DCO_CLK_EN_MASK) +#define AI_DIG_PLL_CTRL_CLR_ENABLE_MASK (0x40000000U) +#define AI_DIG_PLL_CTRL_CLR_ENABLE_SHIFT (30U) +#define AI_DIG_PLL_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_CLR_ENABLE_SHIFT)) & AI_DIG_PLL_CTRL_CLR_ENABLE_MASK) +#define AI_DIG_PLL_CTRL_CLR_START_MASK (0x80000000U) +#define AI_DIG_PLL_CTRL_CLR_START_SHIFT (31U) +#define AI_DIG_PLL_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL_CLR_START_SHIFT)) & AI_DIG_PLL_CTRL_CLR_START_MASK) + + + +#define AI_DIG_PLL_CTRL2_EN_TRACKING_MASK (0x1U) +#define AI_DIG_PLL_CTRL2_EN_TRACKING_SHIFT (0U) +#define AI_DIG_PLL_CTRL2_EN_TRACKING(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_EN_TRACKING_SHIFT)) & AI_DIG_PLL_CTRL2_EN_TRACKING_MASK) +#define AI_DIG_PLL_CTRL2_FC_CNT_MASK (0x7FEU) +#define AI_DIG_PLL_CTRL2_FC_CNT_SHIFT (1U) +#define AI_DIG_PLL_CTRL2_FC_CNT(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_FC_CNT_SHIFT)) & AI_DIG_PLL_CTRL2_FC_CNT_MASK) +#define AI_DIG_PLL_CTRL2_FC_THRESH_MASK (0x7F800U) +#define AI_DIG_PLL_CTRL2_FC_THRESH_SHIFT (11U) +#define AI_DIG_PLL_CTRL2_FC_THRESH(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_FC_THRESH_SHIFT)) & AI_DIG_PLL_CTRL2_FC_THRESH_MASK) +#define AI_DIG_PLL_CTRL2_KE1_MASK (0x700000U) +#define AI_DIG_PLL_CTRL2_KE1_SHIFT (20U) +#define AI_DIG_PLL_CTRL2_KE1(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_KE1_SHIFT)) & AI_DIG_PLL_CTRL2_KE1_MASK) +#define AI_DIG_PLL_CTRL2_KE2_MASK (0x3800000U) +#define AI_DIG_PLL_CTRL2_KE2_SHIFT (23U) +#define AI_DIG_PLL_CTRL2_KE2(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_KE2_SHIFT)) & AI_DIG_PLL_CTRL2_KE2_MASK) +#define AI_DIG_PLL_CTRL2_KE3_MASK (0x1C000000U) +#define AI_DIG_PLL_CTRL2_KE3_SHIFT (26U) +#define AI_DIG_PLL_CTRL2_KE3(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_KE3_SHIFT)) & AI_DIG_PLL_CTRL2_KE3_MASK) +#define AI_DIG_PLL_CTRL2_DITHER_EN_MASK (0x20000000U) +#define AI_DIG_PLL_CTRL2_DITHER_EN_SHIFT (29U) +#define AI_DIG_PLL_CTRL2_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_DITHER_EN_SHIFT)) & AI_DIG_PLL_CTRL2_DITHER_EN_MASK) +#define AI_DIG_PLL_CTRL2_SSC_EN_MASK (0x40000000U) +#define AI_DIG_PLL_CTRL2_SSC_EN_SHIFT (30U) +#define AI_DIG_PLL_CTRL2_SSC_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL2_SSC_EN_SHIFT)) & AI_DIG_PLL_CTRL2_SSC_EN_MASK) + +#define AI_DIG_PLL_CTRL3_COARSE_CNT_MASK (0xFFFFU) +#define AI_DIG_PLL_CTRL3_COARSE_CNT_SHIFT (0U) +#define AI_DIG_PLL_CTRL3_COARSE_CNT(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL3_COARSE_CNT_SHIFT)) & AI_DIG_PLL_CTRL3_COARSE_CNT_MASK) +#define AI_DIG_PLL_CTRL3_COARSE_ADJ_STEP_MASK (0x1C00000U) +#define AI_DIG_PLL_CTRL3_COARSE_ADJ_STEP_SHIFT (22U) +#define AI_DIG_PLL_CTRL3_COARSE_ADJ_STEP(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL3_COARSE_ADJ_STEP_SHIFT)) & AI_DIG_PLL_CTRL3_COARSE_ADJ_STEP_MASK) +#define AI_DIG_PLL_CTRL3_TEST_MASK (0xF8000000U) +#define AI_DIG_PLL_CTRL3_TEST_SHIFT (27U) +#define AI_DIG_PLL_CTRL3_TEST(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL3_TEST_SHIFT)) & AI_DIG_PLL_CTRL3_TEST_MASK) + +#define AI_DIG_PLL_CTRL3_TEST_BIT0_MASK (0x08000000U) +#define AI_DIG_PLL_CTRL3_TEST_BIT0_SHIFT (27U) +#define AI_DIG_PLL_CTRL3_TEST_BIT0(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL3_TEST_BIT0_SHIFT)) & AI_DIG_PLL_CTRL3_TEST_BIT0_MASK) +#define AI_DIG_PLL_CTRL3_TEST_BIT1_MASK (0x10000000U) +#define AI_DIG_PLL_CTRL3_TEST_BIT1_SHIFT (28U) +#define AI_DIG_PLL_CTRL3_TEST_BIT1(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL3_TEST_BIT1_SHIFT)) & AI_DIG_PLL_CTRL3_TEST_BIT1_MASK) +#define AI_DIG_PLL_CTRL3_TEST_BIT2_MASK (0x20000000U) +#define AI_DIG_PLL_CTRL3_TEST_BIT2_SHIFT (29U) +#define AI_DIG_PLL_CTRL3_TEST_BIT2(x) (((uint32_t)(((uint32_t)(x)) << AI_DIG_PLL_CTRL3_TEST_BIT2_SHIFT)) & AI_DIG_PLL_CTRL3_TEST_BIT2_MASK) + +#define AI_DIG_PLL_STATUS_FLOCK_MASK (0x1U) +#define AI_DIG_PLL_STATUS_FLOCK_SHIFT (0U) +#define AI_DIG_PLL_STATUS_FLOCK(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_FLOCK_MASK) >> AI_DIG_PLL_STATUS_FLOCK_SHIFT)) +#define AI_DIG_PLL_STATUS_PLOCK_MASK (0x2U) +#define AI_DIG_PLL_STATUS_PLOCK_SHIFT (1U) +#define AI_DIG_PLL_STATUS_PLOCK(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_PLOCK_MASK) >> AI_DIG_PLL_STATUS_PLOCK_SHIFT)) +#define AI_DIG_PLL_STATUS_S1_OVERFLOW_FLAG_MASK (0x4U) +#define AI_DIG_PLL_STATUS_S1_OVERFLOW_FLAG_SHIFT (2U) +#define AI_DIG_PLL_STATUS_S1_OVERFLOW_FLAG_FLAG(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_S1_OVERFLOW_FLAG_MASK) >> AI_DIG_PLL_STATUS_S1_OVERFLOW_FLAG_SHIFT)) +#define AI_DIG_PLL_STATUS_S1_UNDERFLOW_FLAG_MASK (0x8U) +#define AI_DIG_PLL_STATUS_S1_UNDERFLOW_FLAG_SHIFT (3U) +#define AI_DIG_PLL_STATUS_S1_UNDERFLOW_FLAG(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_S1_UNDERFLOW_FLAG_MASK) >> AI_DIG_PLL_STATUS_S1_UNDERFLOW_FLAG_SHIFT)) + +#define AI_DIG_PLL_STATUS_COUNT_SUM_LSB_MASK (0x70U) +#define AI_DIG_PLL_STATUS_COUNT_SUM_LSB_SHIFT (4U) +#define AI_DIG_PLL_STATUS_COUNT_SUM_LSB(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_COUNT_SUM_LSB_MASK) >> AI_DIG_PLL_STATUS_COUNT_SUM_LSB_SHIFT)) +#define AI_DIG_PLL_STATUS_FC_DS_MASK (0x7F00U) +#define AI_DIG_PLL_STATUS_FC_DS_SHIFT (8U) +#define AI_DIG_PLL_STATUS_FC_DS(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_FC_DS_MASK) >> AI_DIG_PLL_STATUS_FC_DS_SHIFT)) +#define AI_DIG_PLL_STATUS_FC_UFINE_MASK (0x1FF0000U) +#define AI_DIG_PLL_STATUS_FC_UFINE_SHIFT (16U) +#define AI_DIG_PLL_STATUS_FC_UFINE(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_FC_UFINE_MASK) >> AI_DIG_PLL_STATUS_FC_UFINE_SHIFT)) +#define AI_DIG_PLL_STATUS_COUNT_SUM_MSB_MASK (0xFE000000U) +#define AI_DIG_PLL_STATUS_COUNT_SUM_MSB_SHIFT (25U) +#define AI_DIG_PLL_STATUS_COUNT_SUM_MSB(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_STATUS_COUNT_SUM_MSB_MASK) >> AI_DIG_PLL_STATUS_COUNT_SUM_MSB_SHIFT)) +#define AI_DIG_PLL_SPARE_SPARE_FIELD_MASK (0xFFFFFFFFU) +#define AI_DIG_PLL_SPARE_SPARE_FIELD_SHIFT (0U) +#define AI_DIG_PLL_SPARE_SPARE_FIELD(x) ((uint32_t)((((uint32_t)(x)) & AI_DIG_PLL_SPARE_SPARE_FIELD_MASK) >> AI_DIG_PLL_SPARE_SPARE_FIELD_SHIFT)) + +#define AI_HP_PLL_CTRL0_DIV_SELECT_MASK (0xFFU) +#define AI_HP_PLL_CTRL0_DIV_SELECT_SHIFT (0U) +#define AI_HP_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_DIV_SELECT_SHIFT)) & AI_HP_PLL_CTRL0_DIV_SELECT_MASK) +#define AI_HP_PLL_CTRL0_HALF_LF_R_MASK (0x100U) +#define AI_HP_PLL_CTRL0_HALF_LF_R_SHIFT (8U) +#define AI_HP_PLL_CTRL0_HALF_LF_R(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_HALF_LF_R_SHIFT)) & AI_HP_PLL_CTRL0_HALF_LF_R_MASK) +#define AI_HP_PLL_CTRL0_DOUBLE_LF_R_MASK (0x200U) +#define AI_HP_PLL_CTRL0_DOUBLE_LF_R_SHIFT (9U) +#define AI_HP_PLL_CTRL0_DOUBLE_LF_R(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_DOUBLE_LF_R_SHIFT)) & AI_HP_PLL_CTRL0_DOUBLE_LF_R_MASK) +#define AI_HP_PLL_CTRL0_HALF_CP_MASK (0x400U) +#define AI_HP_PLL_CTRL0_HALF_CP_SHIFT (10U) +#define AI_HP_PLL_CTRL0_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_HALF_CP_SHIFT)) & AI_HP_PLL_CTRL0_HALF_CP_MASK) +#define AI_HP_PLL_CTRL0_DOUBLE_CP_MASK (0x800U) +#define AI_HP_PLL_CTRL0_DOUBLE_CP_SHIFT (11U) +#define AI_HP_PLL_CTRL0_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_DOUBLE_CP_SHIFT)) & AI_HP_PLL_CTRL0_DOUBLE_CP_MASK) +#define AI_HP_PLL_CTRL0_HOLD_RING_OFF_MASK (0x1000U) +#define AI_HP_PLL_CTRL0_HOLD_RING_OFF_SHIFT (12U) +#define AI_HP_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_HP_PLL_CTRL0_HOLD_RING_OFF_MASK) +#define AI_HP_PLL_CTRL0_PLL_POWERUP_MASK (0x2000U) +#define AI_HP_PLL_CTRL0_PLL_POWERUP_SHIFT (13U) +#define AI_HP_PLL_CTRL0_PLL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_PLL_POWERUP_SHIFT)) & AI_HP_PLL_CTRL0_PLL_POWERUP_MASK) +#define AI_HP_PLL_CTRL0_REF_PCIE_CLK_EN_MASK (0x4000U) +#define AI_HP_PLL_CTRL0_REF_PCIE_CLK_EN_SHIFT (14U) +#define AI_HP_PLL_CTRL0_REF_PCIE_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_REF_PCIE_CLK_EN_SHIFT)) & AI_HP_PLL_CTRL0_REF_PCIE_CLK_EN_MASK) +#define AI_HP_PLL_CTRL0_CLK_BYPASS_MASK (0x8000U) +#define AI_HP_PLL_CTRL0_CLK_BYPASS_SHIFT (15U) +#define AI_HP_PLL_CTRL0_CLK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_BYPASS_SHIFT)) & AI_HP_PLL_CTRL0_CLK_BYPASS_MASK) +#define AI_HP_PLL_CTRL0_BIAS_PWRUP_MASK (0x10000U) +#define AI_HP_PLL_CTRL0_BIAS_PWRUP_SHIFT (16U) +#define AI_HP_PLL_CTRL0_BIAS_PWRUP(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_BIAS_PWRUP_SHIFT)) & AI_HP_PLL_CTRL0_BIAS_PWRUP_MASK) +#define AI_HP_PLL_CTRL0_CLK_DCK_DIV4_EN_MASK (0x20000U) +#define AI_HP_PLL_CTRL0_CLK_DCK_DIV4_EN_SHIFT (17U) +#define AI_HP_PLL_CTRL0_CLK_DCK_DIV4_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_DCK_DIV4_EN_SHIFT)) & AI_HP_PLL_CTRL0_CLK_DCK_DIV4_EN_MASK) +#define AI_HP_PLL_CTRL0_CLK_DCK_DIV2_EN_MASK (0x40000U) +#define AI_HP_PLL_CTRL0_CLK_DCK_DIV2_EN_SHIFT (18U) +#define AI_HP_PLL_CTRL0_CLK_DCK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_DCK_DIV2_EN_SHIFT)) & AI_HP_PLL_CTRL0_CLK_DCK_DIV2_EN_MASK) +#define AI_HP_PLL_CTRL0_CLK_DCK_EN_MASK (0x80000U) +#define AI_HP_PLL_CTRL0_CLK_DCK_EN_SHIFT (19U) +#define AI_HP_PLL_CTRL0_CLK_DCK_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_DCK_EN_SHIFT)) & AI_HP_PLL_CTRL0_CLK_DCK_EN_MASK) +#define AI_HP_PLL_CTRL0_REGULATOR_LP_EN_MASK (0x100000U) +#define AI_HP_PLL_CTRL0_REGULATOR_LP_EN_SHIFT (20U) +#define AI_HP_PLL_CTRL0_REGULATOR_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_REGULATOR_LP_EN_SHIFT)) & AI_HP_PLL_CTRL0_REGULATOR_LP_EN_MASK) +#define AI_HP_PLL_CTRL0_REGULATOR_EN_MASK (0x200000U) +#define AI_HP_PLL_CTRL0_REGULATOR_EN_SHIFT (21U) +#define AI_HP_PLL_CTRL0_REGULATOR_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_REGULATOR_EN_SHIFT)) & AI_HP_PLL_CTRL0_REGULATOR_EN_MASK) +#define AI_HP_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK (0xC00000U) +#define AI_HP_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT (22U) +#define AI_HP_PLL_CTRL0_REGULATOR_VOLT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT)) & AI_HP_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK) +#define AI_HP_PLL_CTRL0_REGULATOR_TST_EN_MASK (0x1000000U) +#define AI_HP_PLL_CTRL0_REGULATOR_TST_EN_SHIFT (24U) +#define AI_HP_PLL_CTRL0_REGULATOR_TST_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_REGULATOR_TST_EN_SHIFT)) & AI_HP_PLL_CTRL0_REGULATOR_TST_EN_MASK) +#define AI_HP_PLL_CTRL0_SEL_LVDS_DIV_MASK (0x2000000U) +#define AI_HP_PLL_CTRL0_SEL_LVDS_DIV_SHIFT (25U) +#define AI_HP_PLL_CTRL0_SEL_LVDS_DIV(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_SEL_LVDS_DIV_SHIFT)) & AI_HP_PLL_CTRL0_SEL_LVDS_DIV_MASK) +#define AI_HP_PLL_CTRL0_TESTMODE_MASK (0x4000000U) +#define AI_HP_PLL_CTRL0_TESTMODE_SHIFT (26U) +#define AI_HP_PLL_CTRL0_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_TESTMODE_SHIFT)) & AI_HP_PLL_CTRL0_TESTMODE_MASK) +#define AI_HP_PLL_CTRL0_SEL_CLK_DIV_1P5_MASK (0x8000000U) +#define AI_HP_PLL_CTRL0_SEL_CLK_DIV_1P5_SHIFT (27U) +#define AI_HP_PLL_CTRL0_SEL_CLK_DIV_1P5(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_SEL_CLK_DIV_1P5_SHIFT)) & AI_HP_PLL_CTRL0_SEL_CLK_DIV_1P5_MASK) +#define AI_HP_PLL_CTRL0_CLK_DIV_1P5_EN_MASK (0x10000000U) +#define AI_HP_PLL_CTRL0_CLK_DIV_1P5_EN_SHIFT (28U) +#define AI_HP_PLL_CTRL0_CLK_DIV_1P5_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_DIV_1P5_EN_SHIFT)) & AI_HP_PLL_CTRL0_CLK_DIV_1P5_EN_MASK) +#define AI_HP_PLL_CTRL0_CLK_LVDS_EN_MASK (0x20000000U) +#define AI_HP_PLL_CTRL0_CLK_LVDS_EN_SHIFT (29U) +#define AI_HP_PLL_CTRL0_CLK_LVDS_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_LVDS_EN_SHIFT)) & AI_HP_PLL_CTRL0_CLK_LVDS_EN_MASK) +#define AI_HP_PLL_CTRL0_CLK_ISOLATION_B_MASK (0x40000000U) +#define AI_HP_PLL_CTRL0_CLK_ISOLATION_B_SHIFT (30U) +#define AI_HP_PLL_CTRL0_CLK_ISOLATION_B(x) (((uint32_t)(((uint32_t)(x)) << AI_HP_PLL_CTRL0_CLK_ISOLATION_B_SHIFT)) & AI_HP_PLL_CTRL0_CLK_ISOLATION_B_MASK) + +#define AI_OSC24M_CTRLOSC_EN_OSC_LV_MASK (0x1U) +#define AI_OSC24M_CTRLOSC_EN_OSC_LV_SHIFT (0U) +#define AI_OSC24M_CTRLOSC_EN_OSC_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_EN_OSC_LV_SHIFT)) & AI_OSC24M_CTRLOSC_EN_OSC_LV_MASK) +#define AI_OSC24M_CTRLOSC_BYPASS_REGH_LV_MASK (0x2U) +#define AI_OSC24M_CTRLOSC_BYPASS_REGH_LV_SHIFT (1U) +#define AI_OSC24M_CTRLOSC_BYPASS_REGH_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_BYPASS_REGH_LV_SHIFT)) & AI_OSC24M_CTRLOSC_BYPASS_REGH_LV_MASK) +#define AI_OSC24M_CTRLOSC_BYPASS_REGL_LV_MASK (0x4U) +#define AI_OSC24M_CTRLOSC_BYPASS_REGL_LV_SHIFT (2U) +#define AI_OSC24M_CTRLOSC_BYPASS_REGL_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_BYPASS_REGL_LV_SHIFT)) & AI_OSC24M_CTRLOSC_BYPASS_REGL_LV_MASK) +#define AI_OSC24M_CTRLOSC_EN_CLK_EXT_LV_MASK (0x8U) +#define AI_OSC24M_CTRLOSC_EN_CLK_EXT_LV_SHIFT (3U) +#define AI_OSC24M_CTRLOSC_EN_CLK_EXT_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_EN_CLK_EXT_LV_SHIFT)) & AI_OSC24M_CTRLOSC_EN_CLK_EXT_LV_MASK) +#define AI_OSC24M_CTRLOSC_TUNE_REGH_LV_MASK (0x70U) +#define AI_OSC24M_CTRLOSC_TUNE_REGH_LV_SHIFT (4U) +#define AI_OSC24M_CTRLOSC_TUNE_REGH_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_TUNE_REGH_LV_SHIFT)) & AI_OSC24M_CTRLOSC_TUNE_REGH_LV_MASK) +#define AI_OSC24M_CTRLOSC_TUNE_REGL_LV_MASK (0x380U) +#define AI_OSC24M_CTRLOSC_TUNE_REGL_LV_SHIFT (7U) +#define AI_OSC24M_CTRLOSC_TUNE_REGL_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_TUNE_REGL_LV_SHIFT)) & AI_OSC24M_CTRLOSC_TUNE_REGL_LV_MASK) +#define AI_OSC24M_CTRLOSC_IREF_TUNE_LV_MASK (0xC00U) +#define AI_OSC24M_CTRLOSC_IREF_TUNE_LV_SHIFT (10U) +#define AI_OSC24M_CTRLOSC_IREF_TUNE_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_IREF_TUNE_LV_SHIFT)) & AI_OSC24M_CTRLOSC_IREF_TUNE_LV_MASK) +#define AI_OSC24M_CTRLOSC_CL_TUNE_LV_MASK (0xF000U) +#define AI_OSC24M_CTRLOSC_CL_TUNE_LV_SHIFT (12U) +#define AI_OSC24M_CTRLOSC_CL_TUNE_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_CL_TUNE_LV_SHIFT)) & AI_OSC24M_CTRLOSC_CL_TUNE_LV_MASK) +#define AI_OSC24M_CTRLOSC_ITAIL_PKDET_LV_MASK (0x30000U) +#define AI_OSC24M_CTRLOSC_ITAIL_PKDET_LV_SHIFT (16U) +#define AI_OSC24M_CTRLOSC_ITAIL_PKDET_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_ITAIL_PKDET_LV_SHIFT)) & AI_OSC24M_CTRLOSC_ITAIL_PKDET_LV_MASK) +#define AI_OSC24M_CTRLOSC_VTEST_SEL_LV_MASK (0x1C0000U) +#define AI_OSC24M_CTRLOSC_VTEST_SEL_LV_SHIFT (18U) +#define AI_OSC24M_CTRLOSC_VTEST_SEL_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_VTEST_SEL_LV_SHIFT)) & AI_OSC24M_CTRLOSC_VTEST_SEL_LV_MASK) +#define AI_OSC24M_CTRLOSC_TEST_ENABLE_LV_MASK (0x200000U) +#define AI_OSC24M_CTRLOSC_TEST_ENABLE_LV_SHIFT (21U) +#define AI_OSC24M_CTRLOSC_TEST_ENABLE_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_TEST_ENABLE_LV_SHIFT)) & AI_OSC24M_CTRLOSC_TEST_ENABLE_LV_MASK) +#define AI_OSC24M_CTRLOSC_REGL_STANDALONE_LV_MASK (0x400000U) +#define AI_OSC24M_CTRLOSC_REGL_STANDALONE_LV_SHIFT (22U) +#define AI_OSC24M_CTRLOSC_REGL_STANDALONE_LV(x) (((uint32_t)(((uint32_t)(x)) << AI_OSC24M_CTRLOSC_REGL_STANDALONE_LV_SHIFT)) & AI_OSC24M_CTRLOSC_REGL_STANDALONE_LV_MASK) +#define AI_OSC24M_STATOSC_CLK_OKAY_LV_MASK (0x1U) +#define AI_OSC24M_STATOSC_CLK_OKAY_LV_SHIFT (0U) +#define AI_OSC24M_STATOSC_CLK_OKAY_LV(x) ((uint32_t)((((uint32_t)(x)) & AI_OSC24M_STATOSC_CLK_OKAY_LV_MASK) >> AI_OSC24M_STATOSC_CLK_OKAY_LV_SHIFT)) +#define AI_RC200OSC_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) +#define AI_RC200OSC_CTRL0_REF_CLK_DIV_SHIFT (24U) +#define AI_RC200OSC_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RC200OSC_CTRL0_REF_CLK_DIV_MASK) +#define AI_RC200OSC_CTRL1_HYST_MINUS_MASK (0xFU) +#define AI_RC200OSC_CTRL1_HYST_MINUS_SHIFT (0U) +#define AI_RC200OSC_CTRL1_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL1_HYST_MINUS_SHIFT)) & AI_RC200OSC_CTRL1_HYST_MINUS_MASK) +#define AI_RC200OSC_CTRL1_HYST_PLUS_MASK (0xF00U) +#define AI_RC200OSC_CTRL1_HYST_PLUS_SHIFT (8U) +#define AI_RC200OSC_CTRL1_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL1_HYST_PLUS_SHIFT)) & AI_RC200OSC_CTRL1_HYST_PLUS_MASK) +#define AI_RC200OSC_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) +#define AI_RC200OSC_CTRL1_TARGET_COUNT_SHIFT (16U) +#define AI_RC200OSC_CTRL1_TARGET_COUNT(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL1_TARGET_COUNT_SHIFT)) & AI_RC200OSC_CTRL1_TARGET_COUNT_MASK) +#define AI_RC200OSC_CTRL2_TUNE_INV_MASK (0x100U) +#define AI_RC200OSC_CTRL2_TUNE_INV_SHIFT (8U) +#define AI_RC200OSC_CTRL2_TUNE_INV(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL2_TUNE_INV_SHIFT)) & AI_RC200OSC_CTRL2_TUNE_INV_MASK) +#define AI_RC200OSC_CTRL2_TUNE_BYP_MASK (0x400U) +#define AI_RC200OSC_CTRL2_TUNE_BYP_SHIFT (10U) +#define AI_RC200OSC_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL2_TUNE_BYP_SHIFT)) & AI_RC200OSC_CTRL2_TUNE_BYP_MASK) +#define AI_RC200OSC_CTRL2_TUNE_EN_MASK (0x1000U) +#define AI_RC200OSC_CTRL2_TUNE_EN_SHIFT (12U) +#define AI_RC200OSC_CTRL2_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL2_TUNE_EN_SHIFT)) & AI_RC200OSC_CTRL2_TUNE_EN_MASK) +#define AI_RC200OSC_CTRL2_TUNE_START_MASK (0x4000U) +#define AI_RC200OSC_CTRL2_TUNE_START_SHIFT (14U) +#define AI_RC200OSC_CTRL2_TUNE_START(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL2_TUNE_START_SHIFT)) & AI_RC200OSC_CTRL2_TUNE_START_MASK) +#define AI_RC200OSC_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) +#define AI_RC200OSC_CTRL2_OSC_TUNE_VAL_SHIFT (24U) +#define AI_RC200OSC_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RC200OSC_CTRL2_OSC_TUNE_VAL_MASK) +#define AI_RC200OSC_CTRL3_CLR_ERR_MASK (0x1U) +#define AI_RC200OSC_CTRL3_CLR_ERR_SHIFT (0U) +#define AI_RC200OSC_CTRL3_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL3_CLR_ERR_SHIFT)) & AI_RC200OSC_CTRL3_CLR_ERR_MASK) +#define AI_RC200OSC_CTRL3_EN_1M_CLK_MASK (0x100U) +#define AI_RC200OSC_CTRL3_EN_1M_CLK_SHIFT (8U) +#define AI_RC200OSC_CTRL3_EN_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL3_EN_1M_CLK_SHIFT)) & AI_RC200OSC_CTRL3_EN_1M_CLK_MASK) +#define AI_RC200OSC_CTRL3_MUX_1M_CLK_MASK (0x400U) +#define AI_RC200OSC_CTRL3_MUX_1M_CLK_SHIFT (10U) +#define AI_RC200OSC_CTRL3_MUX_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RC200OSC_CTRL3_MUX_1M_CLK_MASK) +#define AI_RC200OSC_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U) +#define AI_RC200OSC_CTRL3_COUNT_1M_CLK_SHIFT (16U) +#define AI_RC200OSC_CTRL3_COUNT_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RC200OSC_CTRL3_COUNT_1M_CLK_MASK) +#define AI_RC200OSC_CTRL4_REF_MUX_CTRL_MASK (0x30000U) +#define AI_RC200OSC_CTRL4_REF_MUX_CTRL_SHIFT (16U) +#define AI_RC200OSC_CTRL4_REF_MUX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL4_REF_MUX_CTRL_SHIFT)) & AI_RC200OSC_CTRL4_REF_MUX_CTRL_MASK) +#define AI_RC200OSC_CTRL4_LVDS_MUX_CTRL_MASK (0x300000U) +#define AI_RC200OSC_CTRL4_LVDS_MUX_CTRL_SHIFT (20U) +#define AI_RC200OSC_CTRL4_LVDS_MUX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL4_LVDS_MUX_CTRL_SHIFT)) & AI_RC200OSC_CTRL4_LVDS_MUX_CTRL_MASK) +#define AI_RC200OSC_CTRL4_LVDS_OUT_EN_MASK (0x1000000U) +#define AI_RC200OSC_CTRL4_LVDS_OUT_EN_SHIFT (24U) +#define AI_RC200OSC_CTRL4_LVDS_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL4_LVDS_OUT_EN_SHIFT)) & AI_RC200OSC_CTRL4_LVDS_OUT_EN_MASK) +#define AI_RC200OSC_CTRL4_PWD_MASK (0x20000000U) +#define AI_RC200OSC_CTRL4_PWD_SHIFT (29U) +#define AI_RC200OSC_CTRL4_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL4_PWD_SHIFT)) & AI_RC200OSC_CTRL4_PWD_MASK) +#define AI_RC200OSC_CTRL4_OSC_EN_MASK (0x80000000U) +#define AI_RC200OSC_CTRL4_OSC_EN_SHIFT (31U) +#define AI_RC200OSC_CTRL4_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_RC200OSC_CTRL4_OSC_EN_SHIFT)) & AI_RC200OSC_CTRL4_OSC_EN_MASK) +#define AI_RC200OSC_STAT0_CLK1M_ERR_MASK (0x1U) +#define AI_RC200OSC_STAT0_CLK1M_ERR_SHIFT (0U) +#define AI_RC200OSC_STAT0_CLK1M_ERR(x) ((uint32_t)((((uint32_t)(x)) & AI_RC200OSC_STAT0_CLK1M_ERR_MASK) >> AI_RC200OSC_STAT0_CLK1M_ERR_SHIFT)) +#define AI_RC200OSC_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U) +#define AI_RC200OSC_STAT1_CURR_COUNT_VAL_SHIFT (16U) +#define AI_RC200OSC_STAT1_CURR_COUNT_VAL(x) ((uint32_t)((((uint32_t)(x)) & AI_RC200OSC_STAT1_CURR_COUNT_VAL_MASK) >> AI_RC200OSC_STAT1_CURR_COUNT_VAL_SHIFT)) +#define AI_RC200OSC_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) +#define AI_RC200OSC_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) +#define AI_RC200OSC_STAT2_CURR_OSC_TUNE_VAL(x) ((uint32_t)((((uint32_t)(x)) & AI_RC200OSC_STAT2_CURR_OSC_TUNE_VAL_MASK) >> AI_RC200OSC_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) + +#define AI_VDROP_PROCMON_CTRL0_DLY_RUN_MASK (0x1U) +#define AI_VDROP_PROCMON_CTRL0_DLY_RUN_SHIFT (0U) +#define AI_VDROP_PROCMON_CTRL0_DLY_RUN(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_DLY_RUN_SHIFT)) & AI_VDROP_PROCMON_CTRL0_DLY_RUN_MASK) +#define AI_VDROP_PROCMON_CTRL0_DLY_RELOCK_MASK (0x2U) +#define AI_VDROP_PROCMON_CTRL0_DLY_RELOCK_SHIFT (1U) +#define AI_VDROP_PROCMON_CTRL0_DLY_RELOCK(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_DLY_RELOCK_SHIFT)) & AI_VDROP_PROCMON_CTRL0_DLY_RELOCK_MASK) +#define AI_VDROP_PROCMON_CTRL0_DLY_1P_EN_MASK (0x4U) +#define AI_VDROP_PROCMON_CTRL0_DLY_1P_EN_SHIFT (2U) +#define AI_VDROP_PROCMON_CTRL0_DLY_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_DLY_1P_EN_SHIFT)) & AI_VDROP_PROCMON_CTRL0_DLY_1P_EN_MASK) +#define AI_VDROP_PROCMON_CTRL0_PLL_CNT_EN_MASK (0x8U) +#define AI_VDROP_PROCMON_CTRL0_PLL_CNT_EN_SHIFT (3U) +#define AI_VDROP_PROCMON_CTRL0_PLL_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_PLL_CNT_EN_SHIFT)) & AI_VDROP_PROCMON_CTRL0_PLL_CNT_EN_MASK) +#define AI_VDROP_PROCMON_CTRL0_CLKGATE_CTRL_MASK (0x30U) +#define AI_VDROP_PROCMON_CTRL0_CLKGATE_CTRL_SHIFT (4U) +#define AI_VDROP_PROCMON_CTRL0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_CLKGATE_CTRL_SHIFT)) & AI_VDROP_PROCMON_CTRL0_CLKGATE_CTRL_MASK) +#define AI_VDROP_PROCMON_CTRL0_ADLY_SETTLE_CNT_MASK (0x3C0U) +#define AI_VDROP_PROCMON_CTRL0_ADLY_SETTLE_CNT_SHIFT (6U) +#define AI_VDROP_PROCMON_CTRL0_ADLY_SETTLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_ADLY_SETTLE_CNT_SHIFT)) & AI_VDROP_PROCMON_CTRL0_ADLY_SETTLE_CNT_MASK) +#define AI_VDROP_PROCMON_CTRL0_TST_CLKGATE_CTRL_MASK (0x400U) +#define AI_VDROP_PROCMON_CTRL0_TST_CLKGATE_CTRL_SHIFT (10U) +#define AI_VDROP_PROCMON_CTRL0_TST_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_TST_CLKGATE_CTRL_SHIFT)) & AI_VDROP_PROCMON_CTRL0_TST_CLKGATE_CTRL_MASK) +#define AI_VDROP_PROCMON_CTRL0_STATUS_SEL_MASK (0xF0000U) +#define AI_VDROP_PROCMON_CTRL0_STATUS_SEL_SHIFT (16U) +#define AI_VDROP_PROCMON_CTRL0_STATUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_CTRL0_STATUS_SEL_SHIFT)) & AI_VDROP_PROCMON_CTRL0_STATUS_SEL_MASK) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_XCK_NXT_UPD_SVAL_MASK (0xFFU) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_XCK_NXT_UPD_SVAL_SHIFT (0U) +#define AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_XCK_NXT_UPD_SVAL(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_XCK_NXT_UPD_SVAL_SHIFT)) & AI_VDROP_PROCMON_XTAL24M_TIMER_CTRL_XCK_NXT_UPD_SVAL_MASK) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_TAP_MASK (0x3FU) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_TAP_SHIFT (0U) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_TAP(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_TAP_SHIFT)) & AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_TAP_MASK) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_OVRD_EN_MASK (0x80000000U) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_OVRD_EN_SHIFT (31U) +#define AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_OVRD_EN_SHIFT)) & AI_VDROP_PROCMON_ADLY_CHAIN_CTRL_ADLY_ENC_OVRD_EN_MASK) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_FDLY_UPDC_ADLY_INC_WTMK_MASK (0x7FFFU) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_FDLY_UPDC_ADLY_INC_WTMK_SHIFT (0U) +#define AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_FDLY_UPDC_ADLY_INC_WTMK(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_FDLY_UPDC_ADLY_INC_WTMK_SHIFT)) & AI_VDROP_PROCMON_UPDATE_INC_WATERMARK_FDLY_UPDC_ADLY_INC_WTMK_MASK) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_FDLY_UPDC_ADLY_DEC_WTMK_MASK (0x7FFFU) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_FDLY_UPDC_ADLY_DEC_WTMK_SHIFT (0U) +#define AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_FDLY_UPDC_ADLY_DEC_WTMK(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_FDLY_UPDC_ADLY_DEC_WTMK_SHIFT)) & AI_VDROP_PROCMON_UPDATE_DEC_WATERMARK_FDLY_UPDC_ADLY_DEC_WTMK_MASK) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_WTMK_MASK (0x1FU) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_WTMK_SHIFT (0U) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_WTMK(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_WTMK_SHIFT)) & AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_WTMK_MASK) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_LOCK_BIT_MASK (0x1F0000U) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_LOCK_BIT_SHIFT (16U) +#define AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_LOCK_BIT(x) (((uint32_t)(((uint32_t)(x)) << AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_LOCK_BIT_SHIFT)) & AI_VDROP_PROCMON_FDLY_TAP_CTRL_FDLY_TAP_LOCK_BIT_MASK) +#define AI_VDROP_PROCMON_DEBUG_STATUS_DEBUG_STATUS_MASK (0xFFFFFFFFU) +#define AI_VDROP_PROCMON_DEBUG_STATUS_DEBUG_STATUS_SHIFT (0U) +#define AI_VDROP_PROCMON_DEBUG_STATUS_DEBUG_STATUS(x) ((uint32_t)((((uint32_t)(x)) & AI_VDROP_PROCMON_DEBUG_STATUS_DEBUG_STATUS_MASK) >> AI_VDROP_PROCMON_DEBUG_STATUS_DEBUG_STATUS_SHIFT)) + +#define AI_TEMP_SENSE_CTRL0_SLOPE_CAL_MASK (0x3FU) +#define AI_TEMP_SENSE_CTRL0_SLOPE_CAL_SHIFT (0U) +#define AI_TEMP_SENSE_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL0_SLOPE_CAL_SHIFT)) & AI_TEMP_SENSE_CTRL0_SLOPE_CAL_MASK) +#define AI_TEMP_SENSE_CTRL0_V_SEL_MASK (0x300U) +#define AI_TEMP_SENSE_CTRL0_V_SEL_SHIFT (8U) +#define AI_TEMP_SENSE_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL0_V_SEL_SHIFT)) & AI_TEMP_SENSE_CTRL0_V_SEL_MASK) +#define AI_TEMP_SENSE_CTRL0_IBIAS_TRIM_MASK (0xF000U) +#define AI_TEMP_SENSE_CTRL0_IBIAS_TRIM_SHIFT (12U) +#define AI_TEMP_SENSE_CTRL0_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL0_IBIAS_TRIM_SHIFT)) & AI_TEMP_SENSE_CTRL0_IBIAS_TRIM_MASK) +#define AI_TEMP_SENSE_CTRL1_FREQ_MASK (0xFFFFU) +#define AI_TEMP_SENSE_CTRL1_FREQ_SHIFT (0U) +#define AI_TEMP_SENSE_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_FREQ_SHIFT)) & AI_TEMP_SENSE_CTRL1_FREQ_MASK) +#define AI_TEMP_SENSE_CTRL1_FINISH_IE_MASK (0x10000U) +#define AI_TEMP_SENSE_CTRL1_FINISH_IE_SHIFT (16U) +#define AI_TEMP_SENSE_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_FINISH_IE_SHIFT)) & AI_TEMP_SENSE_CTRL1_FINISH_IE_MASK) +#define AI_TEMP_SENSE_CTRL1_LOW_TEMP_IE_MASK (0x20000U) +#define AI_TEMP_SENSE_CTRL1_LOW_TEMP_IE_SHIFT (17U) +#define AI_TEMP_SENSE_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_LOW_TEMP_IE_SHIFT)) & AI_TEMP_SENSE_CTRL1_LOW_TEMP_IE_MASK) +#define AI_TEMP_SENSE_CTRL1_HIGH_TEMP_IE_MASK (0x40000U) +#define AI_TEMP_SENSE_CTRL1_HIGH_TEMP_IE_SHIFT (18U) +#define AI_TEMP_SENSE_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_HIGH_TEMP_IE_SHIFT)) & AI_TEMP_SENSE_CTRL1_HIGH_TEMP_IE_MASK) +#define AI_TEMP_SENSE_CTRL1_PANIC_TEMP_IE_MASK (0x80000U) +#define AI_TEMP_SENSE_CTRL1_PANIC_TEMP_IE_SHIFT (19U) +#define AI_TEMP_SENSE_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_PANIC_TEMP_IE_SHIFT)) & AI_TEMP_SENSE_CTRL1_PANIC_TEMP_IE_MASK) +#define AI_TEMP_SENSE_CTRL1_START_MASK (0x400000U) +#define AI_TEMP_SENSE_CTRL1_START_SHIFT (22U) +#define AI_TEMP_SENSE_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_START_SHIFT)) & AI_TEMP_SENSE_CTRL1_START_MASK) +#define AI_TEMP_SENSE_CTRL1_PWD_MASK (0x800000U) +#define AI_TEMP_SENSE_CTRL1_PWD_SHIFT (23U) +#define AI_TEMP_SENSE_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_PWD_SHIFT)) & AI_TEMP_SENSE_CTRL1_PWD_MASK) +#define AI_TEMP_SENSE_CTRL1_FULL_PWD_MASK (0x80000000U) +#define AI_TEMP_SENSE_CTRL1_FULL_PWD_SHIFT (31U) +#define AI_TEMP_SENSE_CTRL1_FULL_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_CTRL1_FULL_PWD_SHIFT)) & AI_TEMP_SENSE_CTRL1_FULL_PWD_MASK) +#define AI_TEMP_SENSE_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU) +#define AI_TEMP_SENSE_RANGE0_LOW_TEMP_VAL_SHIFT (0U) +#define AI_TEMP_SENSE_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_RANGE0_LOW_TEMP_VAL_SHIFT)) & AI_TEMP_SENSE_RANGE0_LOW_TEMP_VAL_MASK) +#define AI_TEMP_SENSE_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U) +#define AI_TEMP_SENSE_RANGE0_HIGH_TEMP_VAL_SHIFT (16U) +#define AI_TEMP_SENSE_RANGE0_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_RANGE0_HIGH_TEMP_VAL_SHIFT)) & AI_TEMP_SENSE_RANGE0_HIGH_TEMP_VAL_MASK) +#define AI_TEMP_SENSE_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU) +#define AI_TEMP_SENSE_RANGE1_PANIC_TEMP_VAL_SHIFT (0U) +#define AI_TEMP_SENSE_RANGE1_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_RANGE1_PANIC_TEMP_VAL_SHIFT)) & AI_TEMP_SENSE_RANGE1_PANIC_TEMP_VAL_MASK) +#define AI_TEMP_SENSE_STATUS0_TEMP_VAL_MASK (0xFFFU) +#define AI_TEMP_SENSE_STATUS0_TEMP_VAL_SHIFT (0U) +#define AI_TEMP_SENSE_STATUS0_TEMP_VAL(x) ((uint32_t)((((uint32_t)(x)) & AI_TEMP_SENSE_STATUS0_TEMP_VAL_MASK) >> AI_TEMP_SENSE_STATUS0_TEMP_VAL_SHIFT)) +#define AI_TEMP_SENSE_STATUS0_TEMP_VAL_W1C(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_STATUS0_TEMP_VAL_SHIFT)) & AI_TEMP_SENSE_STATUS0_TEMP_VAL_MASK) +#define AI_TEMP_SENSE_STATUS0_FINISH_MASK (0x10000U) +#define AI_TEMP_SENSE_STATUS0_FINISH_SHIFT (16U) +#define AI_TEMP_SENSE_STATUS0_FINISH(x) ((uint32_t)((((uint32_t)(x)) & AI_TEMP_SENSE_STATUS0_FINISH_MASK) >> AI_TEMP_SENSE_STATUS0_FINISH_SHIFT)) +#define AI_TEMP_SENSE_STATUS0_FINISH_W1C(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_STATUS0_FINISH_SHIFT)) & AI_TEMP_SENSE_STATUS0_FINISH_MASK) +#define AI_TEMP_SENSE_STATUS0_LOW_TEMP_MASK (0x20000U) +#define AI_TEMP_SENSE_STATUS0_LOW_TEMP_SHIFT (17U) +#define AI_TEMP_SENSE_STATUS0_LOW_TEMP(x) ((uint32_t)((((uint32_t)(x)) & AI_TEMP_SENSE_STATUS0_LOW_TEMP_MASK) >> AI_TEMP_SENSE_STATUS0_LOW_TEMP_SHIFT)) +#define AI_TEMP_SENSE_STATUS0_LOW_TEMP_W1C(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_STATUS0_LOW_TEMP_SHIFT)) & AI_TEMP_SENSE_STATUS0_LOW_TEMP_MASK) +#define AI_TEMP_SENSE_STATUS0_HIGH_TEMP_MASK (0x40000U) +#define AI_TEMP_SENSE_STATUS0_HIGH_TEMP_SHIFT (18U) +#define AI_TEMP_SENSE_STATUS0_HIGH_TEMP(x) ((uint32_t)((((uint32_t)(x)) & AI_TEMP_SENSE_STATUS0_HIGH_TEMP_MASK) >> AI_TEMP_SENSE_STATUS0_HIGH_TEMP_SHIFT)) +#define AI_TEMP_SENSE_STATUS0_HIGH_TEMP_W1C(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_STATUS0_HIGH_TEMP_SHIFT)) & AI_TEMP_SENSE_STATUS0_HIGH_TEMP_MASK) +#define AI_TEMP_SENSE_STATUS0_PANIC_TEMP_MASK (0x80000U) +#define AI_TEMP_SENSE_STATUS0_PANIC_TEMP_SHIFT (19U) +#define AI_TEMP_SENSE_STATUS0_PANIC_TEMP(x) ((uint32_t)((((uint32_t)(x)) & AI_TEMP_SENSE_STATUS0_PANIC_TEMP_MASK) >> AI_TEMP_SENSE_STATUS0_PANIC_TEMP_SHIFT)) +#define AI_TEMP_SENSE_STATUS0_PANIC_TEMP_W1C(x) (((uint32_t)(((uint32_t)(x)) << AI_TEMP_SENSE_STATUS0_PANIC_TEMP_SHIFT)) & AI_TEMP_SENSE_STATUS0_PANIC_TEMP_MASK) + +#define AI_LVDS_TRANS_CTRL0_IPP_OBE_MASK (0x1U) +#define AI_LVDS_TRANS_CTRL0_IPP_OBE_SHIFT (0U) +#define AI_LVDS_TRANS_CTRL0_IPP_OBE(x) (((uint32_t)(((uint32_t)(x)) << AI_LVDS_TRANS_CTRL0_IPP_OBE_SHIFT)) & AI_LVDS_TRANS_CTRL0_IPP_OBE_MASK) +#define AI_LVDS_TRANS_CTRL0_IPP_IBE_MASK (0x2U) +#define AI_LVDS_TRANS_CTRL0_IPP_IBE_SHIFT (1U) +#define AI_LVDS_TRANS_CTRL0_IPP_IBE(x) (((uint32_t)(((uint32_t)(x)) << AI_LVDS_TRANS_CTRL0_IPP_IBE_SHIFT)) & AI_LVDS_TRANS_CTRL0_IPP_IBE_MASK) +#define AI_LVDS_TRANS_CTRL0_I_TRIM_MASK (0xCU) +#define AI_LVDS_TRANS_CTRL0_I_TRIM_SHIFT (2U) +#define AI_LVDS_TRANS_CTRL0_I_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_LVDS_TRANS_CTRL0_I_TRIM_SHIFT)) & AI_LVDS_TRANS_CTRL0_I_TRIM_MASK) +#define AI_LVDS_TRANS_CTRL0_INPUT_SOURCE_MASK (0x30U) +#define AI_LVDS_TRANS_CTRL0_INPUT_SOURCE_SHIFT (4U) +#define AI_LVDS_TRANS_CTRL0_INPUT_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << AI_LVDS_TRANS_CTRL0_INPUT_SOURCE_SHIFT)) & AI_LVDS_TRANS_CTRL0_INPUT_SOURCE_MASK) +#define AI_LVDS_TRANS_CTRL0_ANA_TEST_EN_MASK (0x40U) +#define AI_LVDS_TRANS_CTRL0_ANA_TEST_EN_SHIFT (6U) +#define AI_LVDS_TRANS_CTRL0_ANA_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_LVDS_TRANS_CTRL0_ANA_TEST_EN_SHIFT)) & AI_LVDS_TRANS_CTRL0_ANA_TEST_EN_MASK) +#define AI_LVDS_TRANS_CTRL0_DIV4_EN_MASK (0x80U) +#define AI_LVDS_TRANS_CTRL0_DIV4_EN_SHIFT (7U) +#define AI_LVDS_TRANS_CTRL0_DIV4_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_LVDS_TRANS_CTRL0_DIV4_EN_SHIFT)) & AI_LVDS_TRANS_CTRL0_DIV4_EN_MASK) + +#define AI_NEG_CHARGE_PUMP_CTRL0_EN_NCP_MASK (0x1U) +#define AI_NEG_CHARGE_PUMP_CTRL0_EN_NCP_SHIFT (0U) +#define AI_NEG_CHARGE_PUMP_CTRL0_EN_NCP(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_EN_NCP_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_EN_NCP_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_TRIM_VNEG_MASK (0x3EU) +#define AI_NEG_CHARGE_PUMP_CTRL0_TRIM_VNEG_SHIFT (1U) +#define AI_NEG_CHARGE_PUMP_CTRL0_TRIM_VNEG(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_TRIM_VNEG_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_TRIM_VNEG_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_CLK_DIV_MASK (0x40U) +#define AI_NEG_CHARGE_PUMP_CTRL0_CLK_DIV_SHIFT (6U) +#define AI_NEG_CHARGE_PUMP_CTRL0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_CLK_DIV_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_CLK_DIV_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_DIS_CP_MASK (0x380U) +#define AI_NEG_CHARGE_PUMP_CTRL0_DIS_CP_SHIFT (7U) +#define AI_NEG_CHARGE_PUMP_CTRL0_DIS_CP(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_DIS_CP_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_DIS_CP_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_MASK (0x400U) +#define AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SHIFT (10U) +#define AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SEL_MASK (0x800U) +#define AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SEL_SHIFT (11U) +#define AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SEL_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_OPEN_SW_SEL_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_B_MASK (0x1000U) +#define AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_B_SHIFT (12U) +#define AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_B(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_B_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_B_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_SEL_MASK (0x2000U) +#define AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_SEL_SHIFT (13U) +#define AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_SEL_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_RST_VNEG_OK_SEL_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_SKIP_MODE_MASK (0x4000U) +#define AI_NEG_CHARGE_PUMP_CTRL0_SKIP_MODE_SHIFT (14U) +#define AI_NEG_CHARGE_PUMP_CTRL0_SKIP_MODE(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_SKIP_MODE_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_SKIP_MODE_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_TEST_MODE_MASK (0x38000U) +#define AI_NEG_CHARGE_PUMP_CTRL0_TEST_MODE_SHIFT (15U) +#define AI_NEG_CHARGE_PUMP_CTRL0_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_TEST_MODE_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_TEST_MODE_MASK) +#define AI_NEG_CHARGE_PUMP_CTRL0_EXTRA_MASK (0x1C0000U) +#define AI_NEG_CHARGE_PUMP_CTRL0_EXTRA_SHIFT (18U) +#define AI_NEG_CHARGE_PUMP_CTRL0_EXTRA(x) (((uint32_t)(((uint32_t)(x)) << AI_NEG_CHARGE_PUMP_CTRL0_EXTRA_SHIFT)) & AI_NEG_CHARGE_PUMP_CTRL0_EXTRA_MASK) +#define AI_NEG_CHARGE_PUMP_STAT0_VNEG_OK_MASK (0x1U) +#define AI_NEG_CHARGE_PUMP_STAT0_VNEG_OK_SHIFT (0U) +#define AI_NEG_CHARGE_PUMP_STAT0_VNEG_OK(x) ((uint32_t)((((uint32_t)(x)) & AI_NEG_CHARGE_PUMP_STAT0_VNEG_OK_MASK) >> AI_NEG_CHARGE_PUMP_STAT0_VNEG_OK_SHIFT)) +#define AI_NEG_CHARGE_PUMP_STAT0_SKIP_MASK (0x2U) +#define AI_NEG_CHARGE_PUMP_STAT0_SKIP_SHIFT (1U) +#define AI_NEG_CHARGE_PUMP_STAT0_SKIP(x) ((uint32_t)((((uint32_t)(x)) & AI_NEG_CHARGE_PUMP_STAT0_SKIP_MASK) >> AI_NEG_CHARGE_PUMP_STAT0_SKIP_SHIFT)) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_CLOSED_MASK (0x4U) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_CLOSED_SHIFT (2U) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_CLOSED(x) ((uint32_t)((((uint32_t)(x)) & AI_NEG_CHARGE_PUMP_STAT0_SW_CLOSED_MASK) >> AI_NEG_CHARGE_PUMP_STAT0_SW_CLOSED_SHIFT)) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_DISCHARGE_MASK (0x8U) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_DISCHARGE_SHIFT (3U) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_DISCHARGE(x) ((uint32_t)((((uint32_t)(x)) & AI_NEG_CHARGE_PUMP_STAT0_SW_DISCHARGE_MASK) >> AI_NEG_CHARGE_PUMP_STAT0_SW_DISCHARGE_SHIFT)) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_OPEN_MASK (0x10U) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_OPEN_SHIFT (4U) +#define AI_NEG_CHARGE_PUMP_STAT0_SW_OPEN(x) ((uint32_t)((((uint32_t)(x)) & AI_NEG_CHARGE_PUMP_STAT0_SW_OPEN_MASK) >> AI_NEG_CHARGE_PUMP_STAT0_SW_OPEN_SHIFT)) + +#define AI_WELL_LEVEL_SOURCE_CTRL0_REF_V_CTRL_MASK (0xFFU) +#define AI_WELL_LEVEL_SOURCE_CTRL0_REF_V_CTRL_SHIFT (0U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_REF_V_CTRL(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_REF_V_CTRL_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_REF_V_CTRL_MASK) +#define AI_WELL_LEVEL_SOURCE_CTRL0_V_FB_MASK (0x700U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_V_FB_SHIFT (8U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_V_FB(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_V_FB_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_V_FB_MASK) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_SEL_MASK (0xF800U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_SEL_SHIFT (11U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_SEL_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_SEL_MASK) +#define AI_WELL_LEVEL_SOURCE_CTRL0_EN_REG_LINES_MASK (0x1F0000U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_EN_REG_LINES_SHIFT (16U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_EN_REG_LINES(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_EN_REG_LINES_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_EN_REG_LINES_MASK) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_BLK_SEL_MASK (0xE00000U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_BLK_SEL_SHIFT (21U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_BLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_BLK_SEL_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_TEST_MODE_BLK_SEL_MASK) +#define AI_WELL_LEVEL_SOURCE_CTRL0_EN_DLYD_REG_LINES_MASK (0x1F000000U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_EN_DLYD_REG_LINES_SHIFT (24U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_EN_DLYD_REG_LINES(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_EN_DLYD_REG_LINES_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_EN_DLYD_REG_LINES_MASK) +#define AI_WELL_LEVEL_SOURCE_CTRL0_ASYM_BIAS_MASK (0xC0000000U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_ASYM_BIAS_SHIFT (30U) +#define AI_WELL_LEVEL_SOURCE_CTRL0_ASYM_BIAS(x) (((uint32_t)(((uint32_t)(x)) << AI_WELL_LEVEL_SOURCE_CTRL0_ASYM_BIAS_SHIFT)) & AI_WELL_LEVEL_SOURCE_CTRL0_ASYM_BIAS_MASK) + +#define AI_BANDGAP_REF_CTRL0_REFTOP_PWD_MASK (0x1U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_PWD_SHIFT (0U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_PWD_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_LINREGREF_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_LINREGREF_PWD_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_PWDVBGUP_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_LOWPOWER_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_SELFBIASOFF_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_VBGADJ_MASK (0xE0U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_VBGADJ_SHIFT (5U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_VBGADJ_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_BIAS_TST_MASK (0x300U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_BIAS_TST_SHIFT (8U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_BIAS_TST_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_BIAS_TST_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_IBZTCADJ_MASK) +#define AI_BANDGAP_REF_CTRL0_REFTOP_ANATEST_MASK (0x1E000U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_ANATEST_SHIFT (13U) +#define AI_BANDGAP_REF_CTRL0_REFTOP_ANATEST(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_REF_CTRL0_REFTOP_ANATEST_SHIFT)) & AI_BANDGAP_REF_CTRL0_REFTOP_ANATEST_MASK) +#define AI_BANDGAP_REF_STAT0_REFTOP_VBGUP_MASK (0x1U) +#define AI_BANDGAP_REF_STAT0_REFTOP_VBGUP_SHIFT (0U) +#define AI_BANDGAP_REF_STAT0_REFTOP_VBGUP(x) ((uint32_t)((((uint32_t)(x)) & AI_BANDGAP_REF_STAT0_REFTOP_VBGUP_MASK) >> AI_BANDGAP_REF_STAT0_REFTOP_VBGUP_SHIFT)) +#define AI_BANDGAP_REF_STAT0_VDD1_PORB_MASK (0x2U) +#define AI_BANDGAP_REF_STAT0_VDD1_PORB_SHIFT (1U) +#define AI_BANDGAP_REF_STAT0_VDD1_PORB(x) ((uint32_t)((((uint32_t)(x)) & AI_BANDGAP_REF_STAT0_VDD1_PORB_MASK) >> AI_BANDGAP_REF_STAT0_VDD1_PORB_SHIFT)) +#define AI_BANDGAP_REF_STAT0_VDD2_PORB_MASK (0x4U) +#define AI_BANDGAP_REF_STAT0_VDD2_PORB_SHIFT (2U) +#define AI_BANDGAP_REF_STAT0_VDD2_PORB(x) ((uint32_t)((((uint32_t)(x)) & AI_BANDGAP_REF_STAT0_VDD2_PORB_MASK) >> AI_BANDGAP_REF_STAT0_VDD2_PORB_SHIFT)) +#define AI_BANDGAP_REF_STAT0_VDD3_PORB_MASK (0x8U) +#define AI_BANDGAP_REF_STAT0_VDD3_PORB_SHIFT (3U) +#define AI_BANDGAP_REF_STAT0_VDD3_PORB(x) ((uint32_t)((((uint32_t)(x)) & AI_BANDGAP_REF_STAT0_VDD3_PORB_MASK) >> AI_BANDGAP_REF_STAT0_VDD3_PORB_SHIFT)) + +#define AI_VA_REFGEN_CTRL0_REFGEN_TRIM_MASK (0xFFU) +#define AI_VA_REFGEN_CTRL0_REFGEN_TRIM_SHIFT (0U) +#define AI_VA_REFGEN_CTRL0_REFGEN_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_VA_REFGEN_CTRL0_REFGEN_TRIM_SHIFT)) & AI_VA_REFGEN_CTRL0_REFGEN_TRIM_MASK) +#define AI_VA_REFGEN_CTRL0_REFGEN_ANATEST_MASK (0x700U) +#define AI_VA_REFGEN_CTRL0_REFGEN_ANATEST_SHIFT (8U) +#define AI_VA_REFGEN_CTRL0_REFGEN_ANATEST(x) (((uint32_t)(((uint32_t)(x)) << AI_VA_REFGEN_CTRL0_REFGEN_ANATEST_SHIFT)) & AI_VA_REFGEN_CTRL0_REFGEN_ANATEST_MASK) +#define AI_VA_REFGEN_CTRL0_REFGEN_EN_MASK (0x800U) +#define AI_VA_REFGEN_CTRL0_REFGEN_EN_SHIFT (11U) +#define AI_VA_REFGEN_CTRL0_REFGEN_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_VA_REFGEN_CTRL0_REFGEN_EN_SHIFT)) & AI_VA_REFGEN_CTRL0_REFGEN_EN_MASK) +#define AI_VA_REFGEN_STAT0_REFGEN_SZ_MASK (0x1U) +#define AI_VA_REFGEN_STAT0_REFGEN_SZ_SHIFT (0U) +#define AI_VA_REFGEN_STAT0_REFGEN_SZ(x) ((uint32_t)((((uint32_t)(x)) & AI_VA_REFGEN_STAT0_REFGEN_SZ_MASK) >> AI_VA_REFGEN_STAT0_REFGEN_SZ_SHIFT)) + +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_MASK (0x1U) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_SHIFT (0U) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_PWDB_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_PWDB_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_CLKPATH_MASK (0x2U) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_CLKPATH_SHIFT (1U) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_CLKPATH(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_PWDB_CLKPATH_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_PWDB_CLKPATH_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_REG1P0A_MASK (0x4U) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_REG1P0A_SHIFT (2U) +#define AI_DIFFCLK_RPTR_CTRL0_PWDB_REG1P0A(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_PWDB_REG1P0A_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_PWDB_REG1P0A_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_CLKOUT_SEL_MASK (0x10U) +#define AI_DIFFCLK_RPTR_CTRL0_CLKOUT_SEL_SHIFT (4U) +#define AI_DIFFCLK_RPTR_CTRL0_CLKOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_CLKOUT_SEL_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_CLKOUT_SEL_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_REG1P0A_ADJ_MASK (0xE0U) +#define AI_DIFFCLK_RPTR_CTRL0_REG1P0A_ADJ_SHIFT (5U) +#define AI_DIFFCLK_RPTR_CTRL0_REG1P0A_ADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_REG1P0A_ADJ_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_REG1P0A_ADJ_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR0_MASK (0x300U) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR0_SHIFT (8U) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR0(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_DRV_CUR0_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_DRV_CUR0_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR1_MASK (0xC00U) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR1_SHIFT (10U) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR1(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_DRV_CUR1_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_DRV_CUR1_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_TERM_RES_MASK (0x3000U) +#define AI_DIFFCLK_RPTR_CTRL0_TERM_RES_SHIFT (12U) +#define AI_DIFFCLK_RPTR_CTRL0_TERM_RES(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_TERM_RES_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_TERM_RES_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR_IN_MASK (0xC000U) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR_IN_SHIFT (14U) +#define AI_DIFFCLK_RPTR_CTRL0_DRV_CUR_IN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_DRV_CUR_IN_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_DRV_CUR_IN_MASK) +#define AI_DIFFCLK_RPTR_CTRL0_EN_VDDA1P0_TEST_MASK (0x80000000U) +#define AI_DIFFCLK_RPTR_CTRL0_EN_VDDA1P0_TEST_SHIFT (31U) +#define AI_DIFFCLK_RPTR_CTRL0_EN_VDDA1P0_TEST(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_RPTR_CTRL0_EN_VDDA1P0_TEST_SHIFT)) & AI_DIFFCLK_RPTR_CTRL0_EN_VDDA1P0_TEST_MASK) + +#define AI_DIFFCLK_ROOT_CTRL0_PWDB_MASK (0x1U) +#define AI_DIFFCLK_ROOT_CTRL0_PWDB_SHIFT (0U) +#define AI_DIFFCLK_ROOT_CTRL0_PWDB(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_PWDB_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_PWDB_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_PWDB_CLKPATH_MASK (0x2U) +#define AI_DIFFCLK_ROOT_CTRL0_PWDB_CLKPATH_SHIFT (1U) +#define AI_DIFFCLK_ROOT_CTRL0_PWDB_CLKPATH(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_PWDB_CLKPATH_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_PWDB_CLKPATH_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_MASK (0x4U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_SHIFT (2U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_DIFF_MASK (0x8U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_DIFF_SHIFT (3U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_DIFF(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_DIFF_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_CLKMUX_ENABLE_DIFF_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_DIFF_MASK (0x10U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_DIFF_SHIFT (4U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_DIFF_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_DIFF_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_SE_MASK (0x20U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_SE_SHIFT (5U) +#define AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_SE(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_SE_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_CLKIN_SEL_SE_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_XTALIN_ISO_B_MASK (0x40U) +#define AI_DIFFCLK_ROOT_CTRL0_XTALIN_ISO_B_SHIFT (6U) +#define AI_DIFFCLK_ROOT_CTRL0_XTALIN_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_XTALIN_ISO_B_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_XTALIN_ISO_B_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_DRV_CUR0_MASK (0x300U) +#define AI_DIFFCLK_ROOT_CTRL0_DRV_CUR0_SHIFT (8U) +#define AI_DIFFCLK_ROOT_CTRL0_DRV_CUR0(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_DRV_CUR0_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_DRV_CUR0_MASK) +#define AI_DIFFCLK_ROOT_CTRL0_DRV_CUR1_MASK (0xC00U) +#define AI_DIFFCLK_ROOT_CTRL0_DRV_CUR1_SHIFT (10U) +#define AI_DIFFCLK_ROOT_CTRL0_DRV_CUR1(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_ROOT_CTRL0_DRV_CUR1_SHIFT)) & AI_DIFFCLK_ROOT_CTRL0_DRV_CUR1_MASK) + +#define AI_DIFFCLK_TERM_CTRL0_PWDB_MASK (0x1U) +#define AI_DIFFCLK_TERM_CTRL0_PWDB_SHIFT (0U) +#define AI_DIFFCLK_TERM_CTRL0_PWDB(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_TERM_CTRL0_PWDB_SHIFT)) & AI_DIFFCLK_TERM_CTRL0_PWDB_MASK) +#define AI_DIFFCLK_TERM_CTRL0_PWDB_CLKPATH_MASK (0x2U) +#define AI_DIFFCLK_TERM_CTRL0_PWDB_CLKPATH_SHIFT (1U) +#define AI_DIFFCLK_TERM_CTRL0_PWDB_CLKPATH(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_TERM_CTRL0_PWDB_CLKPATH_SHIFT)) & AI_DIFFCLK_TERM_CTRL0_PWDB_CLKPATH_MASK) +#define AI_DIFFCLK_TERM_CTRL0_CLKOUT_SEL_MASK (0x10U) +#define AI_DIFFCLK_TERM_CTRL0_CLKOUT_SEL_SHIFT (4U) +#define AI_DIFFCLK_TERM_CTRL0_CLKOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_TERM_CTRL0_CLKOUT_SEL_SHIFT)) & AI_DIFFCLK_TERM_CTRL0_CLKOUT_SEL_MASK) +#define AI_DIFFCLK_TERM_CTRL0_TERM_RES_MASK (0x300U) +#define AI_DIFFCLK_TERM_CTRL0_TERM_RES_SHIFT (8U) +#define AI_DIFFCLK_TERM_CTRL0_TERM_RES(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_TERM_CTRL0_TERM_RES_SHIFT)) & AI_DIFFCLK_TERM_CTRL0_TERM_RES_MASK) +#define AI_DIFFCLK_TERM_CTRL0_SQRUP_CUR_MASK (0xC00U) +#define AI_DIFFCLK_TERM_CTRL0_SQRUP_CUR_SHIFT (10U) +#define AI_DIFFCLK_TERM_CTRL0_SQRUP_CUR(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_TERM_CTRL0_SQRUP_CUR_SHIFT)) & AI_DIFFCLK_TERM_CTRL0_SQRUP_CUR_MASK) +#define AI_DIFFCLK_TERM_CTRL0_DRV_CUR_IN_MASK (0x3000U) +#define AI_DIFFCLK_TERM_CTRL0_DRV_CUR_IN_SHIFT (12U) +#define AI_DIFFCLK_TERM_CTRL0_DRV_CUR_IN(x) (((uint32_t)(((uint32_t)(x)) << AI_DIFFCLK_TERM_CTRL0_DRV_CUR_IN_SHIFT)) & AI_DIFFCLK_TERM_CTRL0_DRV_CUR_IN_MASK) + +#define AI_AV_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) +#define AI_AV_PLL_CTRL0_DIV_SELECT_SHIFT (0U) +#define AI_AV_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_DIV_SELECT_SHIFT)) & AI_AV_PLL_CTRL0_DIV_SELECT_MASK) +#define AI_AV_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) +#define AI_AV_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) +#define AI_AV_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AI_AV_PLL_CTRL0_ENABLE_ALT_MASK) +#define AI_AV_PLL_CTRL0_HALF_LF_MASK (0x200U) +#define AI_AV_PLL_CTRL0_HALF_LF_SHIFT (9U) +#define AI_AV_PLL_CTRL0_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_HALF_LF_SHIFT)) & AI_AV_PLL_CTRL0_HALF_LF_MASK) +#define AI_AV_PLL_CTRL0_DOUBLE_LF_MASK (0x400U) +#define AI_AV_PLL_CTRL0_DOUBLE_LF_SHIFT (10U) +#define AI_AV_PLL_CTRL0_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_DOUBLE_LF_SHIFT)) & AI_AV_PLL_CTRL0_DOUBLE_LF_MASK) +#define AI_AV_PLL_CTRL0_HALF_CP_MASK (0x800U) +#define AI_AV_PLL_CTRL0_HALF_CP_SHIFT (11U) +#define AI_AV_PLL_CTRL0_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_HALF_CP_SHIFT)) & AI_AV_PLL_CTRL0_HALF_CP_MASK) +#define AI_AV_PLL_CTRL0_DOUBLE_CP_MASK (0x1000U) +#define AI_AV_PLL_CTRL0_DOUBLE_CP_SHIFT (12U) +#define AI_AV_PLL_CTRL0_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_DOUBLE_CP_SHIFT)) & AI_AV_PLL_CTRL0_DOUBLE_CP_MASK) +#define AI_AV_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) +#define AI_AV_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) +#define AI_AV_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_AV_PLL_CTRL0_HOLD_RING_OFF_MASK) +#define AI_AV_PLL_CTRL0_POWERUP_MASK (0x4000U) +#define AI_AV_PLL_CTRL0_POWERUP_SHIFT (14U) +#define AI_AV_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_POWERUP_SHIFT)) & AI_AV_PLL_CTRL0_POWERUP_MASK) +#define AI_AV_PLL_CTRL0_ENABLE_MASK (0x8000U) +#define AI_AV_PLL_CTRL0_ENABLE_SHIFT (15U) +#define AI_AV_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_ENABLE_SHIFT)) & AI_AV_PLL_CTRL0_ENABLE_MASK) +#define AI_AV_PLL_CTRL0_BYPASS_MASK (0x10000U) +#define AI_AV_PLL_CTRL0_BYPASS_SHIFT (16U) +#define AI_AV_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_BYPASS_SHIFT)) & AI_AV_PLL_CTRL0_BYPASS_MASK) +#define AI_AV_PLL_CTRL0_DITHER_EN_MASK (0x20000U) +#define AI_AV_PLL_CTRL0_DITHER_EN_SHIFT (17U) +#define AI_AV_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_DITHER_EN_SHIFT)) & AI_AV_PLL_CTRL0_DITHER_EN_MASK) +#define AI_AV_PLL_CTRL0_PFD_OFFSET_EN_MASK (0x40000U) +#define AI_AV_PLL_CTRL0_PFD_OFFSET_EN_SHIFT (18U) +#define AI_AV_PLL_CTRL0_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_PFD_OFFSET_EN_SHIFT)) & AI_AV_PLL_CTRL0_PFD_OFFSET_EN_MASK) +#define AI_AV_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) +#define AI_AV_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) +#define AI_AV_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AI_AV_PLL_CTRL0_BIAS_TRIM_MASK) +#define AI_AV_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) +#define AI_AV_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) +#define AI_AV_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AI_AV_PLL_CTRL0_PLL_REG_EN_MASK) +#define AI_AV_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK (0x1800000U) +#define AI_AV_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT (23U) +#define AI_AV_PLL_CTRL0_REGULATOR_VOLT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT)) & AI_AV_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK) +#define AI_AV_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) +#define AI_AV_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) +#define AI_AV_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AI_AV_PLL_CTRL0_POST_DIV_SEL_MASK) +#define AI_AV_PLL_CTRL0_TEST_MODE_MASK (0x40000000U) +#define AI_AV_PLL_CTRL0_TEST_MODE_SHIFT (30U) +#define AI_AV_PLL_CTRL0_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_TEST_MODE_SHIFT)) & AI_AV_PLL_CTRL0_TEST_MODE_MASK) +#define AI_AV_PLL_CTRL0_TEST_MUX_ENABLE_MASK (0x80000000U) +#define AI_AV_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT (31U) +#define AI_AV_PLL_CTRL0_TEST_MUX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT)) & AI_AV_PLL_CTRL0_TEST_MUX_ENABLE_MASK) +#define AI_AV_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) +#define AI_AV_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) +#define AI_AV_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AI_AV_PLL_SPREAD_SPECTRUM_STEP_MASK) +#define AI_AV_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) +#define AI_AV_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) +#define AI_AV_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AI_AV_PLL_SPREAD_SPECTRUM_ENABLE_MASK) +#define AI_AV_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) +#define AI_AV_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) +#define AI_AV_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AI_AV_PLL_SPREAD_SPECTRUM_STOP_MASK) +#define AI_AV_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) +#define AI_AV_PLL_NUMERATOR_NUM_SHIFT (0U) +#define AI_AV_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_NUMERATOR_NUM_SHIFT)) & AI_AV_PLL_NUMERATOR_NUM_MASK) +#define AI_AV_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) +#define AI_AV_PLL_DENOMINATOR_DENOM_SHIFT (0U) +#define AI_AV_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_DENOMINATOR_DENOM_SHIFT)) & AI_AV_PLL_DENOMINATOR_DENOM_MASK) + +#define AI_AV_PLL_STAT0_REG_MASK (0xFFFFFFFFU) +#define AI_AV_PLL_STAT0_REG_SHIFT (0U) +#define AI_AV_PLL_STAT0_REG(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_STAT0_REG_SHIFT)) & AI_AV_PLL_STAT0_REG_MASK) + +#define AI_AV_PLL_STAT1_REG_MASK (0xFFFFFFFFU) +#define AI_AV_PLL_STAT1_REG_SHIFT (0U) +#define AI_AV_PLL_STAT1_REG(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_STAT1_REG_SHIFT)) & AI_AV_PLL_STAT1_REG_MASK) +#define AI_AV_PLL_STAT2_REG_MASK (0xFFFFFFFFU) +#define AI_AV_PLL_STAT2_REG_SHIFT (0U) +#define AI_AV_PLL_STAT2_REG(x) (((uint32_t)(((uint32_t)(x)) << AI_AV_PLL_STAT1_REG_SHIFT)) & AI_AV_PLL_STAT1_REG_MASK) + +#define AI_MLB_PLL_CTRL0_PLL_REG_ENABLE_MASK (0x1U) +#define AI_MLB_PLL_CTRL0_PLL_REG_ENABLE_SHIFT (0U) +#define AI_MLB_PLL_CTRL0_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_PLL_REG_ENABLE_SHIFT)) & AI_MLB_PLL_CTRL0_PLL_REG_ENABLE_MASK) +#define AI_MLB_PLL_CTRL0_POWERUP_MASK (0x2U) +#define AI_MLB_PLL_CTRL0_POWERUP_SHIFT (1U) +#define AI_MLB_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_POWERUP_SHIFT)) & AI_MLB_PLL_CTRL0_POWERUP_MASK) +#define AI_MLB_PLL_CTRL0_MLBPLL_ENABLE_MASK (0x4U) +#define AI_MLB_PLL_CTRL0_MLBPLL_ENABLE_SHIFT (2U) +#define AI_MLB_PLL_CTRL0_MLBPLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLBPLL_ENABLE_SHIFT)) & AI_MLB_PLL_CTRL0_MLBPLL_ENABLE_MASK) +#define AI_MLB_PLL_CTRL0_MLBPLL_BYPASS_MASK (0x8U) +#define AI_MLB_PLL_CTRL0_MLBPLL_BYPASS_SHIFT (3U) +#define AI_MLB_PLL_CTRL0_MLBPLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLBPLL_BYPASS_SHIFT)) & AI_MLB_PLL_CTRL0_MLBPLL_BYPASS_MASK) +#define AI_MLB_PLL_CTRL0_LVDS_SRC_CLK_EN_MLB_PLL_MASK (0x10U) +#define AI_MLB_PLL_CTRL0_LVDS_SRC_CLK_EN_MLB_PLL_SHIFT (4U) +#define AI_MLB_PLL_CTRL0_LVDS_SRC_CLK_EN_MLB_PLL(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_LVDS_SRC_CLK_EN_MLB_PLL_SHIFT)) & AI_MLB_PLL_CTRL0_LVDS_SRC_CLK_EN_MLB_PLL_MASK) +#define AI_MLB_PLL_CTRL0_DOUBLE_CP_CURRENT_MASK (0x20U) +#define AI_MLB_PLL_CTRL0_DOUBLE_CP_CURRENT_SHIFT (5U) +#define AI_MLB_PLL_CTRL0_DOUBLE_CP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_DOUBLE_CP_CURRENT_SHIFT)) & AI_MLB_PLL_CTRL0_DOUBLE_CP_CURRENT_MASK) +#define AI_MLB_PLL_CTRL0_HALF_CP_CURRENT_MASK (0x40U) +#define AI_MLB_PLL_CTRL0_HALF_CP_CURRENT_SHIFT (6U) +#define AI_MLB_PLL_CTRL0_HALF_CP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_HALF_CP_CURRENT_SHIFT)) & AI_MLB_PLL_CTRL0_HALF_CP_CURRENT_MASK) +#define AI_MLB_PLL_CTRL0_HOLD_RING_OFF_MASK (0x80U) +#define AI_MLB_PLL_CTRL0_HOLD_RING_OFF_SHIFT (7U) +#define AI_MLB_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_MLB_PLL_CTRL0_HOLD_RING_OFF_MASK) +#define AI_MLB_PLL_CTRL0_MLB_PLL_DIV_CFG_MASK (0x300U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_DIV_CFG_SHIFT (8U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_DIV_CFG(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLB_PLL_DIV_CFG_SHIFT)) & AI_MLB_PLL_CTRL0_MLB_PLL_DIV_CFG_MASK) +#define AI_MLB_PLL_CTRL0_MLB_PLL_PHASE_SEL_MASK (0xC00U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_PHASE_SEL_SHIFT (10U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_PHASE_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLB_PLL_PHASE_SEL_SHIFT)) & AI_MLB_PLL_CTRL0_MLB_PLL_PHASE_SEL_MASK) +#define AI_MLB_PLL_CTRL0_MLB_PLL_RXCLK_DEL_CFG_MASK (0x7000U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_RXCLK_DEL_CFG_SHIFT (12U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_RXCLK_DEL_CFG(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLB_PLL_RXCLK_DEL_CFG_SHIFT)) & AI_MLB_PLL_CTRL0_MLB_PLL_RXCLK_DEL_CFG_MASK) +#define AI_MLB_PLL_CTRL0_MLB_PLL_VDDD_DELAY_CFG_MASK (0x70000U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_VDDD_DELAY_CFG_SHIFT (16U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_VDDD_DELAY_CFG(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLB_PLL_VDDD_DELAY_CFG_SHIFT)) & AI_MLB_PLL_CTRL0_MLB_PLL_VDDD_DELAY_CFG_MASK) +#define AI_MLB_PLL_CTRL0_MLB_PLL_FLT_RES_SEL_MASK (0x700000U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_FLT_RES_SEL_SHIFT (20U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_FLT_RES_SEL(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLB_PLL_FLT_RES_SEL_SHIFT)) & AI_MLB_PLL_CTRL0_MLB_PLL_FLT_RES_SEL_MASK) +#define AI_MLB_PLL_CTRL0_MLB_PLL_VDDA_DELAY_CFG_MASK (0x7000000U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_VDDA_DELAY_CFG_SHIFT (24U) +#define AI_MLB_PLL_CTRL0_MLB_PLL_VDDA_DELAY_CFG(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_MLB_PLL_VDDA_DELAY_CFG_SHIFT)) & AI_MLB_PLL_CTRL0_MLB_PLL_VDDA_DELAY_CFG_MASK) +#define AI_MLB_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK (0x18000000U) +#define AI_MLB_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT (27U) +#define AI_MLB_PLL_CTRL0_REGULATOR_VOLT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT)) & AI_MLB_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK) +#define AI_MLB_PLL_CTRL0_TEST_MUX_ENABLE_MASK (0x20000000U) +#define AI_MLB_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT (29U) +#define AI_MLB_PLL_CTRL0_TEST_MUX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT)) & AI_MLB_PLL_CTRL0_TEST_MUX_ENABLE_MASK) +#define AI_MLB_PLL_CTRL0_TSTI_POWERUP_MASK (0x40000000U) +#define AI_MLB_PLL_CTRL0_TSTI_POWERUP_SHIFT (30U) +#define AI_MLB_PLL_CTRL0_TSTI_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_TSTI_POWERUP_SHIFT)) & AI_MLB_PLL_CTRL0_TSTI_POWERUP_MASK) +#define AI_MLB_PLL_CTRL0_TESTMODE_MASK (0x80000000U) +#define AI_MLB_PLL_CTRL0_TESTMODE_SHIFT (31U) +#define AI_MLB_PLL_CTRL0_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << AI_MLB_PLL_CTRL0_TESTMODE_SHIFT)) & AI_MLB_PLL_CTRL0_TESTMODE_MASK) + +#define AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) +#define AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) +#define AI_PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK (0x2U) +#define AI_PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U) +#define AI_PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK (0x4U) +#define AI_PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT (2U) +#define AI_PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK (0x1F0U) +#define AI_PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT (4U) +#define AI_PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_ANATEST_MASK (0x7000U) +#define AI_PHY_LDO_CTRL0_LINREG_ANATEST_SHIFT (12U) +#define AI_PHY_LDO_CTRL0_LINREG_ANATEST(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_ANATEST_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_ANATEST_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK (0x8000U) +#define AI_PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT (15U) +#define AI_PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK) +#define AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU) +#define AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U) +#define AI_PHY_LDO_STAT0_LINREG_STAT(x) ((uint32_t)((((uint32_t)(x)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK) >> AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) + +#endif diff --git a/platform/devices/MX8/MX8_ecsr_reset.h b/platform/devices/MX8/MX8_ecsr_reset.h new file mode 100755 index 0000000..f299839 --- /dev/null +++ b/platform/devices/MX8/MX8_ecsr_reset.h @@ -0,0 +1,147 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file MX8_ecsr_reset.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for ESCR Peripheral Reset + * + * CMSIS Peripheral Access Layer for ECSR Reset + */ + +#ifndef ECSR_RESET_H +#define ECSR_RESET_H /**< Symbol preventing repeated inclusion */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ECSR Reset Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSR_Reset_Peripheral_Access_Layer ECSR Reset Peripheral Access Layer + * @{ + */ + +/** ECSR Reset - Register Layout Typedef */ +typedef struct { + __IO uint32_t ECSR_PER_RESET_REQ[4]; /**< offset: 0x00 */ + __I uint32_t ECSR_PER_RESET_ACK[4]; /**< offset: 0x10 */ + __IO uint32_t ECSR_PER_CLK_STOP_REQ[4]; /**< offset: 0x20 */ + __I uint32_t ECSR_PER_CLK_STOP_ACK[4]; /**< offset: 0x30 */ + __IO uint32_t ECSR_PER_BUS_IDLE_REQ[4]; /**< offset: 0x40 */ + __I uint32_t ECSR_PER_BUS_IDLE_ACK[4]; /**< offset: 0x50 */ + __IO uint32_t ECSR_PER_BUS_BLACK_HOLE[4]; /**< offset: 0x60 */ +} ECSR_Reset_Type; + +/* ECSR Reset - Peripheral instance base addresses */ +/** Peripheral ECSR Reset base address */ +#define ECSR_RESET_BASE (0u) +/** Peripheral ECSR Reset base pointer */ +#define ECSR_RESET ((ECSR_Reset_Type *)ECSR_RESET_BASE) +/** Array initializer of ECSR Reset peripheral base addresses */ +#define ECSR_RESET_BASE_ADDRS { ECSR_RESET_BASE } +/** Array initializer of ECSR Reset peripheral base pointers */ +#define ECSR_RESET_BASE_PTRS { ECSR_RESET } + +/*! + * @} + */ /* end of group CSR_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* ECSR_RESET_H */ + diff --git a/platform/devices/MX8/MX8_flexspi.h b/platform/devices/MX8/MX8_flexspi.h new file mode 100755 index 0000000..e6cfe1a --- /dev/null +++ b/platform/devices/MX8/MX8_flexspi.h @@ -0,0 +1,690 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_FLEXSPI_REGISTERS_H +#define HW_FLEXSPI_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */ + __O uint32_t AHBRXBUFCR1[8]; /**< AHB RX Buffer 0 Control Register 1..AHB RX Buffer 7 Control Register 1, array offset: 0x40, array step: 0x4 */ + __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ + __IO uint32_t FLSHCR3; /**< Flash Control Register 3, offset: 0x90 */ + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + __O uint32_t FLSHCR5; /**< Flash Control Register 5, offset: 0x98 */ + __O uint32_t FLSHCR6; /**< Flash Control Register 6, offset: 0x9C */ + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + __O uint32_t IPCR2; /**< IP Control Register 2, offset: 0xA8 */ + __O uint32_t IPCR3; /**< IP Control Register 3, offset: 0xAC */ + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */ + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + __IO uint32_t MISCCR2; /**< Misc Control Register 2, offset: 0xC8 */ + __O uint32_t MISCCR3; /**< Misc Control Register 3, offset: 0xCC */ + __O uint32_t MISCCR4; /**< Misc Control Register 4, offset: 0xD0 */ + __O uint32_t MISCCR5; /**< Misc Control Register 5, offset: 0xD4 */ + __O uint32_t MISCCR6; /**< Misc Control Register 6, offset: 0xD8 */ + __O uint32_t MISCCR7; /**< Misc Control Register 7, offset: 0xDC */ + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_0[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_ENDCFG_MASK (0xCU) +#define FLEXSPI_MCR0_ENDCFG_SHIFT (2U) +#define FLEXSPI_MCR0_ENDCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ENDCFG_SHIFT)) & FLEXSPI_MCR0_ENDCFG_MASK) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) +#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) +#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U) +#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U) +#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) + +/*! @name MCR1 - Module Control Register 1 */ +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) + +/*! @name MCR2 - Module Control Register 2 */ +#define FLEXSPI_MCR2_ABORTONCMDEN_MASK (0x1U) +#define FLEXSPI_MCR2_ABORTONCMDEN_SHIFT (0U) +#define FLEXSPI_MCR2_ABORTONCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONCMDEN_SHIFT)) & FLEXSPI_MCR2_ABORTONCMDEN_MASK) +#define FLEXSPI_MCR2_ABORTONRADDREN_MASK (0x2U) +#define FLEXSPI_MCR2_ABORTONRADDREN_SHIFT (1U) +#define FLEXSPI_MCR2_ABORTONRADDREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONRADDREN_SHIFT)) & FLEXSPI_MCR2_ABORTONRADDREN_MASK) +#define FLEXSPI_MCR2_ABORTONCADDREN_MASK (0x4U) +#define FLEXSPI_MCR2_ABORTONCADDREN_SHIFT (2U) +#define FLEXSPI_MCR2_ABORTONCADDREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONCADDREN_SHIFT)) & FLEXSPI_MCR2_ABORTONCADDREN_MASK) +#define FLEXSPI_MCR2_ABORTONMODEEN_MASK (0x8U) +#define FLEXSPI_MCR2_ABORTONMODEEN_SHIFT (3U) +#define FLEXSPI_MCR2_ABORTONMODEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONMODEEN_SHIFT)) & FLEXSPI_MCR2_ABORTONMODEEN_MASK) +#define FLEXSPI_MCR2_ABORTONDUMMYEN_MASK (0x10U) +#define FLEXSPI_MCR2_ABORTONDUMMYEN_SHIFT (4U) +#define FLEXSPI_MCR2_ABORTONDUMMYEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONDUMMYEN_SHIFT)) & FLEXSPI_MCR2_ABORTONDUMMYEN_MASK) +#define FLEXSPI_MCR2_ABORTONWRITEEN_MASK (0x20U) +#define FLEXSPI_MCR2_ABORTONWRITEEN_SHIFT (5U) +#define FLEXSPI_MCR2_ABORTONWRITEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONWRITEEN_SHIFT)) & FLEXSPI_MCR2_ABORTONWRITEEN_MASK) +#define FLEXSPI_MCR2_ABORTONREADEN_MASK (0x40U) +#define FLEXSPI_MCR2_ABORTONREADEN_SHIFT (6U) +#define FLEXSPI_MCR2_ABORTONREADEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONREADEN_SHIFT)) & FLEXSPI_MCR2_ABORTONREADEN_MASK) +#define FLEXSPI_MCR2_ABORTONLEARNEN_MASK (0x80U) +#define FLEXSPI_MCR2_ABORTONLEARNEN_SHIFT (7U) +#define FLEXSPI_MCR2_ABORTONLEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONLEARNEN_SHIFT)) & FLEXSPI_MCR2_ABORTONLEARNEN_MASK) +#define FLEXSPI_MCR2_ABORTONDATSZEN_MASK (0x100U) +#define FLEXSPI_MCR2_ABORTONDATSZEN_SHIFT (8U) +#define FLEXSPI_MCR2_ABORTONDATSZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_ABORTONDATSZEN_SHIFT)) & FLEXSPI_MCR2_ABORTONDATSZEN_MASK) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_SCK2OPT_MASK (0x1000U) +#define FLEXSPI_MCR2_SCK2OPT_SHIFT (12U) +#define FLEXSPI_MCR2_SCK2OPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCK2OPT_SHIFT)) & FLEXSPI_MCR2_SCK2OPT_MASK) +#define FLEXSPI_MCR2_TSTMD_MASK (0x2000U) +#define FLEXSPI_MCR2_TSTMD_SHIFT (13U) +#define FLEXSPI_MCR2_TSTMD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_TSTMD_SHIFT)) & FLEXSPI_MCR2_TSTMD_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_FLASHDQSOPT_MASK (0x10000U) +#define FLEXSPI_MCR2_FLASHDQSOPT_SHIFT (16U) +#define FLEXSPI_MCR2_FLASHDQSOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_FLASHDQSOPT_SHIFT)) & FLEXSPI_MCR2_FLASHDQSOPT_MASK) +#define FLEXSPI_MCR2_RXDELAYOPT_MASK (0x60000U) +#define FLEXSPI_MCR2_RXDELAYOPT_SHIFT (17U) +#define FLEXSPI_MCR2_RXDELAYOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RXDELAYOPT_SHIFT)) & FLEXSPI_MCR2_RXDELAYOPT_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_CLKPHASERST_MASK (0x100000U) +#define FLEXSPI_MCR2_CLKPHASERST_SHIFT (20U) +#define FLEXSPI_MCR2_CLKPHASERST(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLKPHASERST_SHIFT)) & FLEXSPI_MCR2_CLKPHASERST_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) + +/*! @name AHBCR - AHB Bus Control Register */ +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) +#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) +#define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) +#define FLEXSPI_AHBCR_CLRAHBTXBUF_MASK (0x4U) +#define FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT (2U) +#define FLEXSPI_AHBCR_CLRAHBTXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBTXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBTXBUF_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +#define FLEXSPI_AHBCR_AFLASHBASE_MASK (0xF0000000U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ +#define FLEXSPI_AHBCR_AFLASHBASE_SHIFT (28U) +#define FLEXSPI_AHBCR_AFLASHBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_AFLASHBASE_SHIFT)) & FLEXSPI_AHBCR_AFLASHBASE_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ + +/*! @name INTEN - Interrupt Enable Register */ +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U) +#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U) +#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) + +/*! @name INTR - Interrupt Register */ +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U) +#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U) +#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) + +/*! @name LUTKEY - LUT Key Register */ +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) + +/*! @name LUTCR - LUT Control Register */ +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (8U) + +/* The count of FLEXSPI_AHBRXBUFCR1 */ +#define FLEXSPI_AHBRXBUFCR1_COUNT (8U) + +/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR3 - Flash Control Register 3 */ +#define FLEXSPI_FLSHCR3_SIODOIDLE_MASK (0xFFU) +#define FLEXSPI_FLSHCR3_SIODOIDLE_SHIFT (0U) +#define FLEXSPI_FLSHCR3_SIODOIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIODOIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIODOIDLE_MASK) +#define FLEXSPI_FLSHCR3_SIODONONIDLE_MASK (0xFF00U) +#define FLEXSPI_FLSHCR3_SIODONONIDLE_SHIFT (8U) +#define FLEXSPI_FLSHCR3_SIODONONIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIODONONIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIODONONIDLE_MASK) +#define FLEXSPI_FLSHCR3_SIOOEIDLE_MASK (0xFF0000U) +#define FLEXSPI_FLSHCR3_SIOOEIDLE_SHIFT (16U) +#define FLEXSPI_FLSHCR3_SIOOEIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIOOEIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIOOEIDLE_MASK) +#define FLEXSPI_FLSHCR3_SIOOENONIDLE_MASK (0xFF000000U) +#define FLEXSPI_FLSHCR3_SIOOENONIDLE_SHIFT (24U) +#define FLEXSPI_FLSHCR3_SIOOENONIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR3_SIOOENONIDLE_SHIFT)) & FLEXSPI_FLSHCR3_SIOOENONIDLE_MASK) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) + +/*! @name IPCR0 - IP Control Register 0 */ +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) + +/*! @name IPCR1 - IP Control Register 1 */ +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) + +/*! @name IPCMD - IP Command Register */ +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) + +/*! @name DLPR - Data Learn Pattern Register */ +#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU) +#define FLEXSPI_DLPR_DLP_SHIFT (0U) +#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK) + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) + +/*! @name DLLCR - DLL Control Register 0 */ +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_FORCEUPDATE_MASK (0x4U) +#define FLEXSPI_DLLCR_FORCEUPDATE_SHIFT (2U) +#define FLEXSPI_DLLCR_FORCEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_FORCEUPDATE_SHIFT)) & FLEXSPI_DLLCR_FORCEUPDATE_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_GATEUPDATE_MASK (0x80U) +#define FLEXSPI_DLLCR_GATEUPDATE_SHIFT (7U) +#define FLEXSPI_DLLCR_GATEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_GATEUPDATE_SHIFT)) & FLEXSPI_DLLCR_GATEUPDATE_MASK) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +#define FLEXSPI_DLLCR_REFPHASEGAP_MASK (0x18000U) +#define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT (15U) +#define FLEXSPI_DLLCR_REFPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK) +#define FLEXSPI_DLLCR_REFPHASESTART_MASK (0xE0000U) +#define FLEXSPI_DLLCR_REFPHASESTART_SHIFT (17U) +#define FLEXSPI_DLLCR_REFPHASESTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASESTART_SHIFT)) & FLEXSPI_DLLCR_REFPHASESTART_MASK) +#define FLEXSPI_DLLCR_SLVUPDATEINT_MASK (0xFF00000U) +#define FLEXSPI_DLLCR_SLVUPDATEINT_SHIFT (20U) +#define FLEXSPI_DLLCR_SLVUPDATEINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVUPDATEINT_SHIFT)) & FLEXSPI_DLLCR_SLVUPDATEINT_MASK) +#define FLEXSPI_DLLCR_REFUPDATEINT_MASK (0xF0000000U) +#define FLEXSPI_DLLCR_REFUPDATEINT_SHIFT (28U) +#define FLEXSPI_DLLCR_REFUPDATEINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFUPDATEINT_SHIFT)) & FLEXSPI_DLLCR_REFUPDATEINT_MASK) + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name MISCCR2 - Misc Control Register 2 */ +#define FLEXSPI_MISCCR2_LEARNPHASEGAP_MASK (0x3U) +#define FLEXSPI_MISCCR2_LEARNPHASEGAP_SHIFT (0U) +#define FLEXSPI_MISCCR2_LEARNPHASEGAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_LEARNPHASEGAP_SHIFT)) & FLEXSPI_MISCCR2_LEARNPHASEGAP_MASK) +#define FLEXSPI_MISCCR2_PHASERSTOPT_MASK (0xCU) +#define FLEXSPI_MISCCR2_PHASERSTOPT_SHIFT (2U) +#define FLEXSPI_MISCCR2_PHASERSTOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_PHASERSTOPT_SHIFT)) & FLEXSPI_MISCCR2_PHASERSTOPT_MASK) +#define FLEXSPI_MISCCR2_DOEOPT_MASK (0x10U) +#define FLEXSPI_MISCCR2_DOEOPT_SHIFT (4U) +#define FLEXSPI_MISCCR2_DOEOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_DOEOPT_SHIFT)) & FLEXSPI_MISCCR2_DOEOPT_MASK) +#define FLEXSPI_MISCCR2_RWDSOEOPT_MASK (0x20U) +#define FLEXSPI_MISCCR2_RWDSOEOPT_SHIFT (5U) +#define FLEXSPI_MISCCR2_RWDSOEOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR2_RWDSOEOPT_SHIFT)) & FLEXSPI_MISCCR2_RWDSOEOPT_MASK) + +/*! @name STS0 - Status Register 0 */ +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U) +#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U) +#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK) +#define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U) +#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U) +#define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK) + +/*! @name STS1 - Status Register 1 */ +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) + +/*! @name STS2 - Status Register 2 */ +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 127 */ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (128U) + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FSPI0 base pointer */ +#define FSPI0 ((FLEXSPI_Type *)FSPI0_BASE) +/** Peripheral FSPI1 base pointer */ +#define FSPI1 ((FLEXSPI_Type *)FSPI1_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FSPI_BASE_ADDRS { FSPI0_BASE, FSPI1_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FSPI_BASE_PTRS { FSPI0, FSPI1 } +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { NotAvail_IRQn } + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + +#endif /* HW_FLEXSPI_REGISTERS_H */ diff --git a/platform/devices/MX8/MX8_gpio.h b/platform/devices/MX8/MX8_gpio.h new file mode 100755 index 0000000..dd89cc4 --- /dev/null +++ b/platform/devices/MX8/MX8_gpio.h @@ -0,0 +1,207 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_GPIO_REGISTERS_H +#define HW_GPIO_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- FGPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer + * @{ + */ + +/** FGPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} FGPIO_Type; + +/* ---------------------------------------------------------------------------- + -- FGPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FGPIO_Register_Masks FGPIO Register Masks + * @{ + */ + +/*! @name PDOR - Port Data Output Register */ +#define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) +#define FGPIO_PDOR_PDO_SHIFT (0U) +#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) + +/*! @name PSOR - Port Set Output Register */ +#define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define FGPIO_PSOR_PTSO_SHIFT (0U) +#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) + +/*! @name PCOR - Port Clear Output Register */ +#define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define FGPIO_PCOR_PTCO_SHIFT (0U) +#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) + +/*! @name PTOR - Port Toggle Output Register */ +#define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define FGPIO_PTOR_PTTO_SHIFT (0U) +#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) + +/*! @name PDIR - Port Data Input Register */ +#define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define FGPIO_PDIR_PDI_SHIFT (0U) +#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) + +/*! @name PDDR - Port Data Direction Register */ +#define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define FGPIO_PDDR_PDD_SHIFT (0U) +#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) + + +/*! + * @} + */ /* end of group FGPIO_Register_Masks */ + + +/* FGPIO - Peripheral instance base addresses */ +/** Peripheral FGPIOA base address */ +#define FGPIOA_BASE (0xF8000000u) +/** Peripheral FGPIOA base pointer */ +#define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) +/** Array initializer of FGPIO peripheral base addresses */ +#define FGPIO_BASE_ADDRS { FGPIOA_BASE } +/** Array initializer of FGPIO peripheral base pointers */ +#define FGPIO_BASE_PTRS { FGPIOA } + +/*! + * @} + */ /* end of group FGPIO_Peripheral_Access_Layer */ + +/* ---------------------------------------------------------------------------- + -- RGPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RGPIO_Peripheral_Access_Layer RGPIO Peripheral Access Layer + * @{ + */ + +/** RGPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} RGPIO_Type; + +/* ---------------------------------------------------------------------------- + -- RGPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RGPIO_Register_Masks RGPIO Register Masks + * @{ + */ + +/*! @name PDOR - Port Data Output Register */ +#define RGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) +#define RGPIO_PDOR_PDO_SHIFT (0U) +#define RGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDOR_PDO_SHIFT)) & RGPIO_PDOR_PDO_MASK) + +/*! @name PSOR - Port Set Output Register */ +#define RGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define RGPIO_PSOR_PTSO_SHIFT (0U) +#define RGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PSOR_PTSO_SHIFT)) & RGPIO_PSOR_PTSO_MASK) + +/*! @name PCOR - Port Clear Output Register */ +#define RGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define RGPIO_PCOR_PTCO_SHIFT (0U) +#define RGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PCOR_PTCO_SHIFT)) & RGPIO_PCOR_PTCO_MASK) + +/*! @name PTOR - Port Toggle Output Register */ +#define RGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define RGPIO_PTOR_PTTO_SHIFT (0U) +#define RGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PTOR_PTTO_SHIFT)) & RGPIO_PTOR_PTTO_MASK) + +/*! @name PDIR - Port Data Input Register */ +#define RGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define RGPIO_PDIR_PDI_SHIFT (0U) +#define RGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDIR_PDI_SHIFT)) & RGPIO_PDIR_PDI_MASK) + +/*! @name PDDR - Port Data Direction Register */ +#define RGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define RGPIO_PDDR_PDD_SHIFT (0U) +#define RGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << RGPIO_PDDR_PDD_SHIFT)) & RGPIO_PDDR_PDD_MASK) + + +/*! + * @} + */ /* end of group RGPIO_Register_Masks */ + + +/* RGPIO - Peripheral instance base addresses */ +/** Peripheral RGPIOA base pointer */ +#define RGPIOA ((RGPIO_Type *)RGPIOA_BASE) +/** Peripheral RGPIOB base pointer */ +#define RGPIOB ((RGPIO_Type *)RGPIOB_BASE) +/** Peripheral RGPIOC base pointer */ +#define RGPIOC ((RGPIO_Type *)RGPIOC_BASE) +/** Array initializer of RGPIO peripheral base addresses */ +#define RGPIO_BASE_ADDRS { RGPIOA_BASE, RGPIOB_BASE, RGPIOC_BASE } +/** Array initializer of RGPIO peripheral base pointers */ +#define RGPIO_BASE_PTRS { RGPIOA, RGPIOB, RGPIOC } + +/*! + * @} + */ /* end of group RGPIO_Peripheral_Access_Layer */ + +#endif /* HW_GPIO_REGISTERS_H */ diff --git a/platform/devices/MX8/MX8_igpio.h b/platform/devices/MX8/MX8_igpio.h new file mode 100755 index 0000000..cbd7eb8 --- /dev/null +++ b/platform/devices/MX8/MX8_igpio.h @@ -0,0 +1,464 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_IGPIO_REGISTERS_H +#define HW_IGPIO_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +/*! GDIR + * 0b00000000000000000000000000000000..GPIO is configured as input. + * 0b00000000000000000000000000000001..GPIO is configured as output. + */ +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +/*! IMR + * 0b00000000000000000000000000000000..Interrupt n is disabled. + * 0b00000000000000000000000000000001..Interrupt n is enabled. + */ +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Peripheral GPIO5 base pointer */ +#define GPIO6 ((GPIO_Type *)GPIO6_BASE) +/** Peripheral GPIO5 base pointer */ +#define GPIO7 ((GPIO_Type *)GPIO7_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, \ + GPIO2_BASE, GPIO3_BASE, \ + GPIO4_BASE, GPIO5_BASE, \ + GPIO6_BASE, GPIO7_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, \ + GPIO3, GPIO4, GPIO5, \ + GPIO6, GPIO7 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + +#endif /* HW_IGPIO_REGISTERS_H */ diff --git a/platform/devices/MX8/MX8_isi.h b/platform/devices/MX8/MX8_isi.h new file mode 100755 index 0000000..78e9b8d --- /dev/null +++ b/platform/devices/MX8/MX8_isi.h @@ -0,0 +1,831 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8_isi.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for ISI + * + * CMSIS Peripheral Access Layer for ISI + */ + +#ifndef ISI_H +#define ISI_H /**< Symbol preventing repeated inclusion */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ISI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer + * @{ + */ + +/** ISI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHNL_CTRL; /**< Channel Control Register, offset: 0x0 */ + __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control Register, offset: 0x4 */ + __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control Register, offset: 0x8 */ + __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */ + __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t CHNL_STS; /**< Channel Status Register, offset: 0x14 */ + __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor Register, offset: 0x18 */ + __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset Register, offset: 0x1C */ + __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */ + __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */ + __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */ + __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */ + __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */ + __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */ + __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */ + __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */ + __IO uint32_t CHNL_ROI_0_ALPHA; /**< Channel Alpha Value Register for Region of Interest 0, offset: 0x40 */ + __IO uint32_t CHNL_ROI_0_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 0, offset: 0x44 */ + __IO uint32_t CHNL_ROI_0_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 0, offset: 0x48 */ + __IO uint32_t CHNL_ROI_1_ALPHA; /**< Channel Alpha Value Register for Region of Interest 1, offset: 0x4C */ + __IO uint32_t CHNL_ROI_1_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 1, offset: 0x50 */ + __IO uint32_t CHNL_ROI_1_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 1, offset: 0x54 */ + __IO uint32_t CHNL_ROI_2_ALPHA; /**< Channel Alpha Value Register for Region of Interest 2, offset: 0x58 */ + __IO uint32_t CHNL_ROI_2_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 2, offset: 0x5C */ + __IO uint32_t CHNL_ROI_2_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 2, offset: 0x60 */ + __IO uint32_t CHNL_ROI_3_ALPHA; /**< Channel Alpha Value Register for Region of Interest 3, offset: 0x64 */ + __IO uint32_t CHNL_ROI_3_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 3, offset: 0x68 */ + __IO uint32_t CHNL_ROI_3_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 3, offset: 0x6C */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */ + __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */ + __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */ + __IO uint32_t CHNL_IN_BUF_ADDR; /**< Channel Input Buffer Address, offset: 0x80 */ + __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */ + __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */ + __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */ + __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */ +} ISI_Type; + +/* ---------------------------------------------------------------------------- + -- ISI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ISI_Register_Masks ISI Register Masks + * @{ + */ + +/*! @name CHNL_CTRL - Channel Control Register */ +#define ISI_CHNL_CTRL_SRC_MASK (0x7U) +#define ISI_CHNL_CTRL_SRC_SHIFT (0U) +#define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK) +#define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U) +#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U) +#define ISI_CHNL_CTRL_SRC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK) +#define ISI_CHNL_CTRL_MIPI_VC_ID_MASK (0xC0U) +#define ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT (6U) +#define ISI_CHNL_CTRL_MIPI_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_MIPI_VC_ID_SHIFT)) & ISI_CHNL_CTRL_MIPI_VC_ID_MASK) +#define ISI_CHNL_CTRL_SEC_LB_SRC_MASK (0x700U) +#define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT (8U) +#define ISI_CHNL_CTRL_SEC_LB_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK) +#define ISI_CHNL_CTRL_BLANK_PXL_MASK (0xFF0000U) +#define ISI_CHNL_CTRL_BLANK_PXL_SHIFT (16U) +#define ISI_CHNL_CTRL_BLANK_PXL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_BLANK_PXL_SHIFT)) & ISI_CHNL_CTRL_BLANK_PXL_MASK) +#define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U) +#define ISI_CHNL_CTRL_SW_RST_SHIFT (24U) +#define ISI_CHNL_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK) +#define ISI_CHNL_CTRL_CHAIN_BUF_MASK (0x6000000U) +#define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT (25U) +#define ISI_CHNL_CTRL_CHAIN_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK) +#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U) +#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U) +#define ISI_CHNL_CTRL_CHNL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK) +#define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U) +#define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U) +#define ISI_CHNL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK) +#define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U) +#define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U) +#define ISI_CHNL_CTRL_CHNL_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK) + +/*! @name CHNL_IMG_CTRL - Channel Image Control Register */ +#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U) +#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U) +#define ISI_CHNL_IMG_CTRL_CSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK) +#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U) +#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U) +#define ISI_CHNL_IMG_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK) +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U) +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U) +#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK) +#define ISI_CHNL_IMG_CTRL_RSVD2_MASK (0x10U) +#define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT (4U) +#define ISI_CHNL_IMG_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK) +#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U) +#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U) +#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK) +#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U) +#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U) +#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK) +#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U) +#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U) +#define ISI_CHNL_IMG_CTRL_CROP_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK) +#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U) +#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U) +#define ISI_CHNL_IMG_CTRL_DEC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK) +#define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U) +#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U) +#define ISI_CHNL_IMG_CTRL_DEC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK) +#define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U) +#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U) +#define ISI_CHNL_IMG_CTRL_DEINT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U) +#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK) +#define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x3F000000U) +#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U) +#define ISI_CHNL_IMG_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK) +#define ISI_CHNL_IMG_CTRL_RSVD0_MASK (0xC0000000U) +#define ISI_CHNL_IMG_CTRL_RSVD0_SHIFT (30U) +#define ISI_CHNL_IMG_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD0_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD0_MASK) + +/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */ +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK (0x3U) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT (0U) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK (0x18U) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT (3U) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK (0xC0U) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT (6U) +#define ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U) +#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK) + +/*! @name CHNL_IMG_CFG - Channel Image Configuration */ +#define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU) +#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U) +#define ISI_CHNL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK) +#define ISI_CHNL_IMG_CFG_RSVD0_MASK (0xE000U) +#define ISI_CHNL_IMG_CFG_RSVD0_SHIFT (13U) +#define ISI_CHNL_IMG_CFG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK) +#define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) +#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U) +#define ISI_CHNL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK) +#define ISI_CHNL_IMG_CFG_RSVD1_MASK (0xE0000000U) +#define ISI_CHNL_IMG_CFG_RSVD1_SHIFT (29U) +#define ISI_CHNL_IMG_CFG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK) + +/*! @name CHNL_IER - Channel Interrupt Enable Register */ +#define ISI_CHNL_IER_RSVD0_MASK (0x3FFFU) +#define ISI_CHNL_IER_RSVD0_SHIFT (0U) +#define ISI_CHNL_IER_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK) +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x4000U) +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (14U) +#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK) +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x8000U) +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (15U) +#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK) +#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x10000U) +#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (16U) +#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK) +#define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK (0x20000U) +#define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT (17U) +#define ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_Y_BUF_EN_MASK) +#define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK (0x40000U) +#define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT (18U) +#define ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_Y_BUF_EN_MASK) +#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x80000U) +#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (19U) +#define ISI_CHNL_IER_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK) +#define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK (0x100000U) +#define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT (20U) +#define ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_U_BUF_EN_MASK) +#define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK (0x200000U) +#define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT (21U) +#define ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_U_BUF_EN_MASK) +#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x400000U) +#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (22U) +#define ISI_CHNL_IER_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK) +#define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK (0x800000U) +#define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT (23U) +#define ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_EXCS_OFLW_V_BUF_EN_MASK) +#define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK (0x1000000U) +#define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT (24U) +#define ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_PANIC_V_BUF_EN_MASK) +#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U) +#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U) +#define ISI_CHNL_IER_AXI_RD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK) +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U) +#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK) +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U) +#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK) +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U) +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U) +#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK) +#define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U) +#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U) +#define ISI_CHNL_IER_FRM_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK) +#define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U) +#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U) +#define ISI_CHNL_IER_LINE_RCVD_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK) +#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U) +#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U) +#define ISI_CHNL_IER_MEM_RD_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK) + +/*! @name CHNL_STS - Channel Status Register */ +#define ISI_CHNL_STS_OFLW_BYTES_MASK (0xFFU) +#define ISI_CHNL_STS_OFLW_BYTES_SHIFT (0U) +#define ISI_CHNL_STS_OFLW_BYTES(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_BYTES_SHIFT)) & ISI_CHNL_STS_OFLW_BYTES_MASK) +#define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U) +#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U) +#define ISI_CHNL_STS_BUF1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK) +#define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U) +#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U) +#define ISI_CHNL_STS_BUF2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK) +#define ISI_CHNL_STS_RSVD1_MASK (0x3C00U) +#define ISI_CHNL_STS_RSVD1_SHIFT (10U) +#define ISI_CHNL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK) +#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x4000U) +#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (14U) +#define ISI_CHNL_STS_LATE_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK) +#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x8000U) +#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (15U) +#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK) +#define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x10000U) +#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (16U) +#define ISI_CHNL_STS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK) +#define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK (0x20000U) +#define ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT (17U) +#define ISI_CHNL_STS_EXCS_OFLW_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_Y_BUF_MASK) +#define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK (0x40000U) +#define ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT (18U) +#define ISI_CHNL_STS_OFLW_PANIC_Y_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_Y_BUF_MASK) +#define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x80000U) +#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (19U) +#define ISI_CHNL_STS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK) +#define ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK (0x100000U) +#define ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT (20U) +#define ISI_CHNL_STS_EXCS_OFLW_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_U_BUF_MASK) +#define ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK (0x200000U) +#define ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT (21U) +#define ISI_CHNL_STS_OFLW_PANIC_U_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_U_BUF_MASK) +#define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U) +#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U) +#define ISI_CHNL_STS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK) +#define ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK (0x800000U) +#define ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT (23U) +#define ISI_CHNL_STS_EXCS_OFLW_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EXCS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_EXCS_OFLW_V_BUF_MASK) +#define ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK (0x1000000U) +#define ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT (24U) +#define ISI_CHNL_STS_OFLW_PANIC_V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_PANIC_V_BUF_MASK) +#define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U) +#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U) +#define ISI_CHNL_STS_AXI_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK) +#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U) +#define ISI_CHNL_STS_AXI_WR_ERR_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK) +#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U) +#define ISI_CHNL_STS_AXI_WR_ERR_U(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK) +#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U) +#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U) +#define ISI_CHNL_STS_AXI_WR_ERR_V(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK) +#define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U) +#define ISI_CHNL_STS_FRM_STRD_SHIFT (29U) +#define ISI_CHNL_STS_FRM_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK) +#define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U) +#define ISI_CHNL_STS_LINE_STRD_SHIFT (30U) +#define ISI_CHNL_STS_LINE_STRD(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK) +#define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U) +#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U) +#define ISI_CHNL_STS_MEM_RD_DONE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK) + +/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */ +#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU) +#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U) +#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK) +#define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK (0xC000U) +#define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT (14U) +#define ISI_CHNL_SCALE_FACTOR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK) +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U) +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U) +#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK) +#define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK (0xC0000000U) +#define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT (30U) +#define ISI_CHNL_SCALE_FACTOR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK) + +/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */ +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU) +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U) +#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK) +#define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK (0xF000U) +#define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT (12U) +#define ISI_CHNL_SCALE_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK) +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U) +#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK) +#define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT (28U) +#define ISI_CHNL_SCALE_OFFSET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK) + +/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */ +#define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_CROP_ULC_Y_SHIFT (0U) +#define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK) +#define ISI_CHNL_CROP_ULC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_CROP_ULC_RSVD1_SHIFT (12U) +#define ISI_CHNL_CROP_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK) +#define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_CROP_ULC_X_SHIFT (16U) +#define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK) +#define ISI_CHNL_CROP_ULC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_CROP_ULC_RSVD0_SHIFT (28U) +#define ISI_CHNL_CROP_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK) + +/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */ +#define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_CROP_LRC_Y_SHIFT (0U) +#define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK) +#define ISI_CHNL_CROP_LRC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_CROP_LRC_RSVD1_SHIFT (12U) +#define ISI_CHNL_CROP_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK) +#define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_CROP_LRC_X_SHIFT (16U) +#define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK) +#define ISI_CHNL_CROP_LRC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_CROP_LRC_RSVD0_SHIFT (28U) +#define ISI_CHNL_CROP_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK) + +/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */ +#define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U) +#define ISI_CHNL_CSC_COEFF0_A1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK) +#define ISI_CHNL_CSC_COEFF0_RSVD1_MASK (0xF800U) +#define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT (11U) +#define ISI_CHNL_CSC_COEFF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK) +#define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U) +#define ISI_CHNL_CSC_COEFF0_A2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK) +#define ISI_CHNL_CSC_COEFF0_RSVD0_MASK (0xF8000000U) +#define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT (27U) +#define ISI_CHNL_CSC_COEFF0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK) + +/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */ +#define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U) +#define ISI_CHNL_CSC_COEFF1_A3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK) +#define ISI_CHNL_CSC_COEFF1_RSVD1_MASK (0xF800U) +#define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT (11U) +#define ISI_CHNL_CSC_COEFF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK) +#define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U) +#define ISI_CHNL_CSC_COEFF1_B1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK) +#define ISI_CHNL_CSC_COEFF1_RSVD0_MASK (0xF8000000U) +#define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT (27U) +#define ISI_CHNL_CSC_COEFF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK) + +/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */ +#define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U) +#define ISI_CHNL_CSC_COEFF2_B2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK) +#define ISI_CHNL_CSC_COEFF2_RSVD1_MASK (0xF800U) +#define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT (11U) +#define ISI_CHNL_CSC_COEFF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK) +#define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U) +#define ISI_CHNL_CSC_COEFF2_B3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK) +#define ISI_CHNL_CSC_COEFF2_RSVD0_MASK (0xF8000000U) +#define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT (27U) +#define ISI_CHNL_CSC_COEFF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK) + +/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */ +#define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U) +#define ISI_CHNL_CSC_COEFF3_C1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK) +#define ISI_CHNL_CSC_COEFF3_RSVD1_MASK (0xF800U) +#define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT (11U) +#define ISI_CHNL_CSC_COEFF3_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK) +#define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U) +#define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U) +#define ISI_CHNL_CSC_COEFF3_C2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK) +#define ISI_CHNL_CSC_COEFF3_RSVD0_MASK (0xF8000000U) +#define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT (27U) +#define ISI_CHNL_CSC_COEFF3_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK) + +/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */ +#define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU) +#define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U) +#define ISI_CHNL_CSC_COEFF4_C3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK) +#define ISI_CHNL_CSC_COEFF4_RSVD1_MASK (0xF800U) +#define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT (11U) +#define ISI_CHNL_CSC_COEFF4_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK) +#define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U) +#define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U) +#define ISI_CHNL_CSC_COEFF4_D1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK) +#define ISI_CHNL_CSC_COEFF4_RSVD0_MASK (0xFE000000U) +#define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT (25U) +#define ISI_CHNL_CSC_COEFF4_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK) + +/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */ +#define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU) +#define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U) +#define ISI_CHNL_CSC_COEFF5_D2(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK) +#define ISI_CHNL_CSC_COEFF5_RSVD1_MASK (0xFE00U) +#define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT (9U) +#define ISI_CHNL_CSC_COEFF5_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK) +#define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U) +#define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U) +#define ISI_CHNL_CSC_COEFF5_D3(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK) +#define ISI_CHNL_CSC_COEFF5_RSVD0_MASK (0xFE000000U) +#define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT (25U) +#define ISI_CHNL_CSC_COEFF5_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK) + +/*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value Register for Region of Interest 0 */ +#define ISI_CHNL_ROI_0_ALPHA_RSVD1_MASK (0xFFFFU) +#define ISI_CHNL_ROI_0_ALPHA_RSVD1_SHIFT (0U) +#define ISI_CHNL_ROI_0_ALPHA_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_RSVD1_MASK) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT (16U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK) +#define ISI_CHNL_ROI_0_ALPHA_RSVD0_MASK (0xFE0000U) +#define ISI_CHNL_ROI_0_ALPHA_RSVD0_SHIFT (17U) +#define ISI_CHNL_ROI_0_ALPHA_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_RSVD0_MASK) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT (24U) +#define ISI_CHNL_ROI_0_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK) + +/*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate Register for Region of Interest 0 */ +#define ISI_CHNL_ROI_0_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_0_ULC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_0_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK) +#define ISI_CHNL_ROI_0_ULC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_0_ULC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_0_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_ULC_RSVD1_MASK) +#define ISI_CHNL_ROI_0_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_0_ULC_X_SHIFT (16U) +#define ISI_CHNL_ROI_0_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK) +#define ISI_CHNL_ROI_0_ULC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_0_ULC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_0_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_ULC_RSVD0_MASK) + +/*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate Register for Region of Interest 0 */ +#define ISI_CHNL_ROI_0_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_0_LRC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_0_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK) +#define ISI_CHNL_ROI_0_LRC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_0_LRC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_0_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_LRC_RSVD1_MASK) +#define ISI_CHNL_ROI_0_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_0_LRC_X_SHIFT (16U) +#define ISI_CHNL_ROI_0_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK) +#define ISI_CHNL_ROI_0_LRC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_0_LRC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_0_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_LRC_RSVD0_MASK) + +/*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value Register for Region of Interest 1 */ +#define ISI_CHNL_ROI_1_ALPHA_RSVD1_MASK (0xFFFFU) +#define ISI_CHNL_ROI_1_ALPHA_RSVD1_SHIFT (0U) +#define ISI_CHNL_ROI_1_ALPHA_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_RSVD1_MASK) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT (16U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK) +#define ISI_CHNL_ROI_1_ALPHA_RSVD0_MASK (0xFE0000U) +#define ISI_CHNL_ROI_1_ALPHA_RSVD0_SHIFT (17U) +#define ISI_CHNL_ROI_1_ALPHA_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_RSVD0_MASK) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT (24U) +#define ISI_CHNL_ROI_1_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK) + +/*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate Register for Region of Interest 1 */ +#define ISI_CHNL_ROI_1_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_1_ULC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_1_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK) +#define ISI_CHNL_ROI_1_ULC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_1_ULC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_1_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_ULC_RSVD1_MASK) +#define ISI_CHNL_ROI_1_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_1_ULC_X_SHIFT (16U) +#define ISI_CHNL_ROI_1_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK) +#define ISI_CHNL_ROI_1_ULC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_1_ULC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_1_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_ULC_RSVD0_MASK) + +/*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate Register for Region of Interest 1 */ +#define ISI_CHNL_ROI_1_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_1_LRC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_1_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK) +#define ISI_CHNL_ROI_1_LRC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_1_LRC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_1_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_LRC_RSVD1_MASK) +#define ISI_CHNL_ROI_1_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_1_LRC_X_SHIFT (16U) +#define ISI_CHNL_ROI_1_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK) +#define ISI_CHNL_ROI_1_LRC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_1_LRC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_1_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_LRC_RSVD0_MASK) + +/*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value Register for Region of Interest 2 */ +#define ISI_CHNL_ROI_2_ALPHA_RSVD1_MASK (0xFFFFU) +#define ISI_CHNL_ROI_2_ALPHA_RSVD1_SHIFT (0U) +#define ISI_CHNL_ROI_2_ALPHA_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_RSVD1_MASK) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT (16U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK) +#define ISI_CHNL_ROI_2_ALPHA_RSVD0_MASK (0xFE0000U) +#define ISI_CHNL_ROI_2_ALPHA_RSVD0_SHIFT (17U) +#define ISI_CHNL_ROI_2_ALPHA_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_RSVD0_MASK) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT (24U) +#define ISI_CHNL_ROI_2_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK) + +/*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate Register for Region of Interest 2 */ +#define ISI_CHNL_ROI_2_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_2_ULC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_2_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK) +#define ISI_CHNL_ROI_2_ULC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_2_ULC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_2_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_ULC_RSVD1_MASK) +#define ISI_CHNL_ROI_2_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_2_ULC_X_SHIFT (16U) +#define ISI_CHNL_ROI_2_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK) +#define ISI_CHNL_ROI_2_ULC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_2_ULC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_2_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_ULC_RSVD0_MASK) + +/*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate Register for Region of Interest 2 */ +#define ISI_CHNL_ROI_2_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_2_LRC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_2_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK) +#define ISI_CHNL_ROI_2_LRC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_2_LRC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_2_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_LRC_RSVD1_MASK) +#define ISI_CHNL_ROI_2_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_2_LRC_X_SHIFT (16U) +#define ISI_CHNL_ROI_2_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK) +#define ISI_CHNL_ROI_2_LRC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_2_LRC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_2_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_LRC_RSVD0_MASK) + +/*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value Register for Region of Interest 3 */ +#define ISI_CHNL_ROI_3_ALPHA_RSVD1_MASK (0xFFFFU) +#define ISI_CHNL_ROI_3_ALPHA_RSVD1_SHIFT (0U) +#define ISI_CHNL_ROI_3_ALPHA_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_RSVD1_MASK) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK (0x10000U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT (16U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK) +#define ISI_CHNL_ROI_3_ALPHA_RSVD0_MASK (0xFE0000U) +#define ISI_CHNL_ROI_3_ALPHA_RSVD0_SHIFT (17U) +#define ISI_CHNL_ROI_3_ALPHA_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_RSVD0_MASK) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK (0xFF000000U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT (24U) +#define ISI_CHNL_ROI_3_ALPHA_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK) + +/*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate Register for Region of Interest 3 */ +#define ISI_CHNL_ROI_3_ULC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_3_ULC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_3_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK) +#define ISI_CHNL_ROI_3_ULC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_3_ULC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_3_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_ULC_RSVD1_MASK) +#define ISI_CHNL_ROI_3_ULC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_3_ULC_X_SHIFT (16U) +#define ISI_CHNL_ROI_3_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK) +#define ISI_CHNL_ROI_3_ULC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_3_ULC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_3_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_ULC_RSVD0_MASK) + +/*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate Register for Region of Interest 3 */ +#define ISI_CHNL_ROI_3_LRC_Y_MASK (0xFFFU) +#define ISI_CHNL_ROI_3_LRC_Y_SHIFT (0U) +#define ISI_CHNL_ROI_3_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK) +#define ISI_CHNL_ROI_3_LRC_RSVD1_MASK (0xF000U) +#define ISI_CHNL_ROI_3_LRC_RSVD1_SHIFT (12U) +#define ISI_CHNL_ROI_3_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_LRC_RSVD1_MASK) +#define ISI_CHNL_ROI_3_LRC_X_MASK (0xFFF0000U) +#define ISI_CHNL_ROI_3_LRC_X_SHIFT (16U) +#define ISI_CHNL_ROI_3_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK) +#define ISI_CHNL_ROI_3_LRC_RSVD0_MASK (0xF0000000U) +#define ISI_CHNL_ROI_3_LRC_RSVD0_SHIFT (28U) +#define ISI_CHNL_ROI_3_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_LRC_RSVD0_MASK) + +/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */ +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U) +#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK) + +/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U) +#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK) + +/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */ +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U) +#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK) + +/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */ +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U) +#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK) + +/*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */ +#define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT (0U) +#define ISI_CHNL_IN_BUF_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK) + +/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */ +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU) +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U) +#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK) +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U) +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U) +#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK) + +/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */ +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U) +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U) +#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK) +#define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK (0xFFFFFFEU) +#define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT (1U) +#define ISI_CHNL_MEM_RD_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK) +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U) +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U) +#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK) + +/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */ +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U) +#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK) + +/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U) +#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK) + +/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */ +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU) +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U) +#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK) + +/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */ +#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU) +#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U) +#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK) +#define ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK (0xE000U) +#define ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT (13U) +#define ISI_CHNL_SCL_IMG_CFG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK) +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U) +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U) +#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK) +#define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK (0xE0000000U) +#define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT (29U) +#define ISI_CHNL_SCL_IMG_CFG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK) + + +/*! + * @} + */ /* end of group ISI_Register_Masks */ + + +/** Peripheral ISI base pointers */ +#define ISI0 ((ISI_Type *)ISI0_BASE) +#define ISI1 ((ISI_Type *)ISI1_BASE) +#define ISI2 ((ISI_Type *)ISI2_BASE) +#define ISI3 ((ISI_Type *)ISI3_BASE) +#define ISI4 ((ISI_Type *)ISI4_BASE) +#define ISI5 ((ISI_Type *)ISI5_BASE) +#define ISI6 ((ISI_Type *)ISI6_BASE) +#define ISI7 ((ISI_Type *)ISI7_BASE) +#define ISI8 ((ISI_Type *)ISI8_BASE) +#define ISI9 ((ISI_Type *)ISI9_BASE) +#define ISI10 ((ISI_Type *)ISI10_BASE) +#define ISI11 ((ISI_Type *)ISI11_BASE) +#define ISI12 ((ISI_Type *)ISI12_BASE) +#define ISI13 ((ISI_Type *)ISI13_BASE) +#define ISI14 ((ISI_Type *)ISI14_BASE) +#define ISI15 ((ISI_Type *)ISI15_BASE) +#define ISI16 ((ISI_Type *)ISI16_BASE) +#define ISI17 ((ISI_Type *)ISI17_BASE) +#define ISI18 ((ISI_Type *)ISI18_BASE) +#define ISI19 ((ISI_Type *)ISI19_BASE) +#define ISI20 ((ISI_Type *)ISI20_BASE) +#define ISI21 ((ISI_Type *)ISI21_BASE) +#define ISI22 ((ISI_Type *)ISI22_BASE) +#define ISI23 ((ISI_Type *)ISI23_BASE) + +/** Array initializer of ISI peripheral base addresses */ +#define ISI_BASE_ADDRS { ISI0_BASE, ISI1_BASE, \ + ISI2_BASE, ISI3_BASE, \ + ISI4_BASE, ISI5_BASE, \ + ISI6_BASE, ISI7_BASE, \ + ISI8_BASE, ISI9_BASE, \ + ISI10_BASE, ISI11_BASE, \ + ISI12_BASE, ISI13_BASE, \ + ISI14_BASE, ISI15_BASE, \ + ISI16_BASE, ISI17_BASE, \ + ISI18_BASE, ISI19_BASE, \ + ISI20_BASE, ISI21_BASE, \ + ISI22_BASE, ISI23_BASE } + + +/** Array initializer of ISI peripheral base pointers */ +#define ISI_BASE_PTRS { ISI0, ISI1, ISI2, ISI3, \ + ISI4, ISI5, ISI6, ISI7, \ + ISI8, ISI9, ISI10, ISI11, \ + ISI12, ISI13, ISI14, ISI15, \ + ISI16, ISI17, ISI18, ISI19, \ + ISI20, ISI21, ISI22, ISI23 } + +/*! + * @} + */ /* end of group ISI_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* ISI_H */ + diff --git a/platform/devices/MX8/MX8_jpgdec.h b/platform/devices/MX8/MX8_jpgdec.h new file mode 100755 index 0000000..c32a8c8 --- /dev/null +++ b/platform/devices/MX8/MX8_jpgdec.h @@ -0,0 +1,323 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8_jpegdec.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer JPGDEC + * + * CMSIS Peripheral Access Layer for JPGDEC + */ + +#ifndef JPGDEC_H +#define JPGDEC_H /**< Symbol preventing repeated inclusion */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- JPGDEC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup JPGDEC_Peripheral_Access_Layer JPGDEC Peripheral Access Layer + * @{ + */ + +/** JPGDEC - Register Layout Typedef */ +typedef struct { + __IO uint32_t GLB_CTRL; /**< Global Control, offset: 0x0 */ + __I uint32_t COM_STATUS; /**< Common Status, offset: 0x4 */ + __I uint32_t RSVD_COM_IRQ_EN; /**< RSVD, offset: 0x8 */ + __I uint32_t RSVD_CUR_DESCPT_PTR; /**< RSVD, offset: 0xC */ + __I uint32_t RSVD_NXT_DESCPT_PTR; /**< RSVD, offset: 0x10 */ + __IO uint32_t OUT_BUF_BASE0; /**< Output Image Frame Buffer0 Base Address, offset: 0x14 */ + __IO uint32_t OUT_BUF_BASE1; /**< Output Image Frame Buffer1 Base Address, offset: 0x18 */ + __IO uint32_t OUT_PITCH; /**< Image Output Buffer Pitch, offset: 0x1C */ + __IO uint32_t STM_BUFBASE; /**< Input JPEG Stream Buffer Base Address, offset: 0x20 */ + __IO uint32_t STM_BUFSIZE; /**< Input JPEG Stream Buffer Size, offset: 0x24 */ + __IO uint32_t IMGSIZE; /**< Image Resolution, offset: 0x28 */ + __IO uint32_t STM_CTRL; /**< Bit Stream and Switching Control, offset: 0x2C */ + uint8_t RESERVED_0[65488]; + struct { /* offset: 0x10000, array step: 0x10000 */ + __IO uint32_t SLOT_STATUS; /**< Bitstream Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t SLOT_IRQ_EN; /**< Bitstream Interrupt Eanble, array offset: 0x10004, array step: 0x10000 */ + __I uint32_t SLOT_BUF_PTR; /**< Bitstream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */ + __I uint32_t SLOT_CUR_DESCPT_PTR; /**< Current Descriptors, array offset: 0x1000C, array step: 0x10000 */ + __IO uint32_t SLOT_NXT_DESCPT_PTR; /**< Next Descriptors, array offset: 0x10010, array step: 0x10000 */ + uint8_t RESERVED_0[65516]; + } BITSTRM_SLOT_REGS[4]; +} JPGDEC_Type; + +/* ---------------------------------------------------------------------------- + -- JPGDEC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup JPGDEC_Register_Masks JPGDEC Register Masks + * @{ + */ + +/*! @name GLB_CTRL - Global Control */ +#define JPGDEC_GLB_CTRL_JPG_DEC_EN_MASK (0x1U) +#define JPGDEC_GLB_CTRL_JPG_DEC_EN_SHIFT (0U) +#define JPGDEC_GLB_CTRL_JPG_DEC_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_GLB_CTRL_JPG_DEC_EN_SHIFT)) & JPGDEC_GLB_CTRL_JPG_DEC_EN_MASK) +#define JPGDEC_GLB_CTRL_SFTRST_MASK (0x2U) +#define JPGDEC_GLB_CTRL_SFTRST_SHIFT (1U) +#define JPGDEC_GLB_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_GLB_CTRL_SFTRST_SHIFT)) & JPGDEC_GLB_CTRL_SFTRST_MASK) +#define JPGDEC_GLB_CTRL_DEC_GO_MASK (0x4U) +#define JPGDEC_GLB_CTRL_DEC_GO_SHIFT (2U) +#define JPGDEC_GLB_CTRL_DEC_GO(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_GLB_CTRL_DEC_GO_SHIFT)) & JPGDEC_GLB_CTRL_DEC_GO_MASK) +#define JPGDEC_GLB_CTRL_L_ENDIAN_MASK (0x8U) +#define JPGDEC_GLB_CTRL_L_ENDIAN_SHIFT (3U) +#define JPGDEC_GLB_CTRL_L_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_GLB_CTRL_L_ENDIAN_SHIFT)) & JPGDEC_GLB_CTRL_L_ENDIAN_MASK) +#define JPGDEC_GLB_CTRL_SLOT_EN_MASK (0xF0U) +#define JPGDEC_GLB_CTRL_SLOT_EN_SHIFT (4U) +#define JPGDEC_GLB_CTRL_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_GLB_CTRL_SLOT_EN_SHIFT)) & JPGDEC_GLB_CTRL_SLOT_EN_MASK) + +/*! @name COM_STATUS - Common Status */ +#define JPGDEC_COM_STATUS_CUR_SLOT_MASK (0x60000000U) +#define JPGDEC_COM_STATUS_CUR_SLOT_SHIFT (29U) +#define JPGDEC_COM_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_COM_STATUS_CUR_SLOT_SHIFT)) & JPGDEC_COM_STATUS_CUR_SLOT_MASK) +#define JPGDEC_COM_STATUS_DEC_ONGOING_MASK (0x80000000U) +#define JPGDEC_COM_STATUS_DEC_ONGOING_SHIFT (31U) +#define JPGDEC_COM_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_COM_STATUS_DEC_ONGOING_SHIFT)) & JPGDEC_COM_STATUS_DEC_ONGOING_MASK) + +/*! @name OUT_BUF_BASE0 - Output Image Frame Buffer0 Base Address */ +#define JPGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK (0xFFFFFFF0U) +#define JPGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT (4U) +#define JPGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_SHIFT)) & JPGDEC_OUT_BUF_BASE0_OUT_BUF_BASE0_MASK) + +/*! @name OUT_BUF_BASE1 - Output Image Frame Buffer1 Base Address */ +#define JPGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK (0xFFFFFFF0U) +#define JPGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT (4U) +#define JPGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_SHIFT)) & JPGDEC_OUT_BUF_BASE1_OUT_BUF_BASE1_MASK) + +/*! @name OUT_PITCH - Image Output Buffer Pitch */ +#define JPGDEC_OUT_PITCH_OUT_PITCH_MASK (0xFFFFU) +#define JPGDEC_OUT_PITCH_OUT_PITCH_SHIFT (0U) +#define JPGDEC_OUT_PITCH_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_OUT_PITCH_OUT_PITCH_SHIFT)) & JPGDEC_OUT_PITCH_OUT_PITCH_MASK) + +/*! @name STM_BUFBASE - Input JPEG Stream Buffer Base Address */ +#define JPGDEC_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U) +#define JPGDEC_STM_BUFBASE_STM_BUFBASE_SHIFT (4U) +#define JPGDEC_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPGDEC_STM_BUFBASE_STM_BUFBASE_MASK) + +/*! @name STM_BUFSIZE - Input JPEG Stream Buffer Size */ +#define JPGDEC_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U) +#define JPGDEC_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U) +#define JPGDEC_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPGDEC_STM_BUFSIZE_STM_BUFSIZE_MASK) + +/*! @name IMGSIZE - Image Resolution */ +#define JPGDEC_IMGSIZE_IMG_HEIGHT_MASK (0x3FFFU) +#define JPGDEC_IMGSIZE_IMG_HEIGHT_SHIFT (0U) +#define JPGDEC_IMGSIZE_IMG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPGDEC_IMGSIZE_IMG_HEIGHT_MASK) +#define JPGDEC_IMGSIZE_IMG_WIDTH_MASK (0x3FFF0000U) +#define JPGDEC_IMGSIZE_IMG_WIDTH_SHIFT (16U) +#define JPGDEC_IMGSIZE_IMG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_IMGSIZE_IMG_WIDTH_SHIFT)) & JPGDEC_IMGSIZE_IMG_WIDTH_MASK) + +/*! @name STM_CTRL - Bit Stream and Switching Control */ +#define JPGDEC_STM_CTRL_PIXEL_PRECISION_MASK (0x4U) +#define JPGDEC_STM_CTRL_PIXEL_PRECISION_SHIFT (2U) +#define JPGDEC_STM_CTRL_PIXEL_PRECISION(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPGDEC_STM_CTRL_PIXEL_PRECISION_MASK) +#define JPGDEC_STM_CTRL_IMAGE_FORMAT_MASK (0x78U) +#define JPGDEC_STM_CTRL_IMAGE_FORMAT_SHIFT (3U) +#define JPGDEC_STM_CTRL_IMAGE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPGDEC_STM_CTRL_IMAGE_FORMAT_MASK) +#define JPGDEC_STM_CTRL_BITBUF_PTR_CLR_MASK (0x80U) +#define JPGDEC_STM_CTRL_BITBUF_PTR_CLR_SHIFT (7U) +#define JPGDEC_STM_CTRL_BITBUF_PTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPGDEC_STM_CTRL_BITBUF_PTR_CLR_MASK) +#define JPGDEC_STM_CTRL_AUTO_START_MASK (0x100U) +#define JPGDEC_STM_CTRL_AUTO_START_SHIFT (8U) +#define JPGDEC_STM_CTRL_AUTO_START(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_STM_CTRL_AUTO_START_SHIFT)) & JPGDEC_STM_CTRL_AUTO_START_MASK) + +/*! @name SLOT_STATUS - Bitstream Status */ +#define JPGDEC_SLOT_STATUS_STMBUF_HALF_MASK (0x1U) +#define JPGDEC_SLOT_STATUS_STMBUF_HALF_SHIFT (0U) +#define JPGDEC_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPGDEC_SLOT_STATUS_STMBUF_HALF_MASK) +#define JPGDEC_SLOT_STATUS_STMBUF_RTND_MASK (0x2U) +#define JPGDEC_SLOT_STATUS_STMBUF_RTND_SHIFT (1U) +#define JPGDEC_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPGDEC_SLOT_STATUS_STMBUF_RTND_MASK) +#define JPGDEC_SLOT_STATUS_SWITCHED_IN_MASK (0x4U) +#define JPGDEC_SLOT_STATUS_SWITCHED_IN_SHIFT (2U) +#define JPGDEC_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPGDEC_SLOT_STATUS_SWITCHED_IN_MASK) +#define JPGDEC_SLOT_STATUS_FRMDONE_MASK (0x8U) +#define JPGDEC_SLOT_STATUS_FRMDONE_SHIFT (3U) +#define JPGDEC_SLOT_STATUS_FRMDONE(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_FRMDONE_SHIFT)) & JPGDEC_SLOT_STATUS_FRMDONE_MASK) +#define JPGDEC_SLOT_STATUS_DECERR_MASK (0x100U) +#define JPGDEC_SLOT_STATUS_DECERR_SHIFT (8U) +#define JPGDEC_SLOT_STATUS_DECERR(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_DECERR_SHIFT)) & JPGDEC_SLOT_STATUS_DECERR_MASK) +#define JPGDEC_SLOT_STATUS_DES_RD_ERR_MASK (0x200U) +#define JPGDEC_SLOT_STATUS_DES_RD_ERR_SHIFT (9U) +#define JPGDEC_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPGDEC_SLOT_STATUS_DES_RD_ERR_MASK) +#define JPGDEC_SLOT_STATUS_BIT_RD_ERR_MASK (0x400U) +#define JPGDEC_SLOT_STATUS_BIT_RD_ERR_SHIFT (10U) +#define JPGDEC_SLOT_STATUS_BIT_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_BIT_RD_ERR_SHIFT)) & JPGDEC_SLOT_STATUS_BIT_RD_ERR_MASK) +#define JPGDEC_SLOT_STATUS_PIXEL_WT_ERR_MASK (0x800U) +#define JPGDEC_SLOT_STATUS_PIXEL_WT_ERR_SHIFT (11U) +#define JPGDEC_SLOT_STATUS_PIXEL_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_PIXEL_WT_ERR_SHIFT)) & JPGDEC_SLOT_STATUS_PIXEL_WT_ERR_MASK) +#define JPGDEC_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U) +#define JPGDEC_SLOT_STATUS_CUR_SLOT_SHIFT (29U) +#define JPGDEC_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPGDEC_SLOT_STATUS_CUR_SLOT_MASK) +#define JPGDEC_SLOT_STATUS_DEC_ONGOING_MASK (0x80000000U) +#define JPGDEC_SLOT_STATUS_DEC_ONGOING_SHIFT (31U) +#define JPGDEC_SLOT_STATUS_DEC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_STATUS_DEC_ONGOING_SHIFT)) & JPGDEC_SLOT_STATUS_DEC_ONGOING_MASK) + +/* The count of JPGDEC_SLOT_STATUS */ +#define JPGDEC_SLOT_STATUS_COUNT (4U) + +/*! @name SLOT_IRQ_EN - Bitstream Interrupt Eanble */ +#define JPGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U) +#define JPGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U) +#define JPGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U) +#define JPGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U) +#define JPGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK (0x4U) +#define JPGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT (2U) +#define JPGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_SWITCHED_IN_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U) +#define JPGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U) +#define JPGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_DECERR_IRQ_EN_MASK (0x100U) +#define JPGDEC_SLOT_IRQ_EN_DECERR_IRQ_EN_SHIFT (8U) +#define JPGDEC_SLOT_IRQ_EN_DECERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_DECERR_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_DECERR_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK (0x200U) +#define JPGDEC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT (9U) +#define JPGDEC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_MASK (0x400U) +#define JPGDEC_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_SHIFT (10U) +#define JPGDEC_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_BIT_RD_ERR_IRQ_EN_MASK) +#define JPGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_MASK (0x800U) +#define JPGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_SHIFT (11U) +#define JPGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_SHIFT)) & JPGDEC_SLOT_IRQ_EN_PIXEL_WT_ERR_IRQ_EN_MASK) + +/* The count of JPGDEC_SLOT_IRQ_EN */ +#define JPGDEC_SLOT_IRQ_EN_COUNT (4U) + +/*! @name SLOT_BUF_PTR - Bitstream Buffer Pointer */ +#define JPGDEC_SLOT_BUF_PTR_STMBUF_PTR_MASK (0xFFFFFFFFU) +#define JPGDEC_SLOT_BUF_PTR_STMBUF_PTR_SHIFT (0U) +#define JPGDEC_SLOT_BUF_PTR_STMBUF_PTR(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_BUF_PTR_STMBUF_PTR_SHIFT)) & JPGDEC_SLOT_BUF_PTR_STMBUF_PTR_MASK) + +/* The count of JPGDEC_SLOT_BUF_PTR */ +#define JPGDEC_SLOT_BUF_PTR_COUNT (4U) + +/*! @name SLOT_CUR_DESCPT_PTR - Current Descriptors */ +#define JPGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU) +#define JPGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U) +#define JPGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPGDEC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK) + +/* The count of JPGDEC_SLOT_CUR_DESCPT_PTR */ +#define JPGDEC_SLOT_CUR_DESCPT_PTR_COUNT (4U) + +/*! @name SLOT_NXT_DESCPT_PTR - Next Descriptors */ +#define JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK (0x1U) +#define JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT (0U) +#define JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_SHIFT)) & JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_EN_MASK) +#define JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU) +#define JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U) +#define JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPGDEC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK) + +/* The count of JPGDEC_SLOT_NXT_DESCPT_PTR */ +#define JPGDEC_SLOT_NXT_DESCPT_PTR_COUNT (4U) + + +/*! + * @} + */ /* end of group JPGDEC_Register_Masks */ + + +/* JPGDEC - Peripheral instance base addresses */ +/** Peripheral JPEG_DEC base address */ +#define JPEGDEC_BASE (0u) +/** Peripheral JPEG_DEC base pointer */ +#define JPEGDEC ((JPGDEC_Type *)JPEGDEC_BASE) +/** Array initializer of JPGDEC peripheral base addresses */ +#define JPGDEC_BASE_ADDRS { JPEGDEC_BASE } +/** Array initializer of JPGDEC peripheral base pointers */ +#define JPGDEC_BASE_PTRS { JPEGDEC } + +/*! + * @} + */ /* end of group JPGDEC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* JPGDEC_H */ + diff --git a/platform/devices/MX8/MX8_jpgenc.h b/platform/devices/MX8/MX8_jpgenc.h new file mode 100755 index 0000000..ce34bb5 --- /dev/null +++ b/platform/devices/MX8/MX8_jpgenc.h @@ -0,0 +1,325 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8_jpegenc.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for JPGENC + * + * CMSIS Peripheral Access Layer for JPGENC + */ + +#ifndef JPGENC_H +#define JPGENC_H /**< Symbol preventing repeated inclusion */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- JPGENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup JPGENC_Peripheral_Access_Layer JPGENC Peripheral Access Layer + * @{ + */ + +/** JPGENC - Register Layout Typedef */ +typedef struct { + __IO uint32_t GLB_CTRL; /**< Global Control, offset: 0x0 */ + __I uint32_t COM_STATUS; /**< Common Status, offset: 0x4 */ + __I uint32_t RSVD_COM_IRQ_EN; /**< RSVD, offset: 0x8 */ + __I uint32_t RSVD_CUR_DESCPT_PTR; /**< RSVD, offset: 0xC */ + __I uint32_t RSVD_NXT_DESCPT_PTR; /**< RSVD, offset: 0x10 */ + __IO uint32_t IN_BUF_BASE0; /**< Input Image Frame Buffer0 Base Address, offset: 0x14 */ + __IO uint32_t IN_BUF_BASE1; /**< Input Image Frame Buffer1 Base Address, offset: 0x18 */ + __IO uint32_t IN_LINE_PITCH; /**< Image Input Buffer Line Pitch, offset: 0x1C */ + __IO uint32_t STM_BUFBASE; /**< Output JPEG Stream Buffer Base Address, offset: 0x20 */ + __IO uint32_t STM_BUFSIZE; /**< Output JPEG Stream Buffer Size, offset: 0x24 */ + __IO uint32_t IMGSIZE; /**< Image Resolution, offset: 0x28 */ + __IO uint32_t STM_CTRL; /**< Bit Stream Switch and Control, offset: 0x2C */ + uint8_t RESERVED_0[65488]; + struct { /* offset: 0x10000, array step: 0x10000 */ + __IO uint32_t SLOT_STATUS; /**< Bit Stream SLOT Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t SLOT_IRQ_EN; /**< Bit Stream Interrupt Enable Register, array offset: 0x10004, array step: 0x10000 */ + __I uint32_t SLOT_BUF_PTR; /**< Bit Stream Buffer Pointer, array offset: 0x10008, array step: 0x10000 */ + __I uint32_t SLOT_CUR_DESCPT_PTR; /**< Current Encoding Descriptor Pointer, array offset: 0x1000C, array step: 0x10000 */ + __IO uint32_t SLOT_NXT_DESCPT_PTR; /**< Next Encoding Descriptor Pointer, array offset: 0x10010, array step: 0x10000 */ + uint8_t RESERVED_0[65516]; + } BITSTRM_SLOT_REGS[4]; +} JPGENC_Type; + +/* ---------------------------------------------------------------------------- + -- JPGENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup JPGENC_Register_Masks JPGENC Register Masks + * @{ + */ + +/*! @name GLB_CTRL - Global Control */ +#define JPGENC_GLB_CTRL_JPG_ENC_EN_MASK (0x1U) +#define JPGENC_GLB_CTRL_JPG_ENC_EN_SHIFT (0U) +#define JPGENC_GLB_CTRL_JPG_ENC_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_GLB_CTRL_JPG_ENC_EN_SHIFT)) & JPGENC_GLB_CTRL_JPG_ENC_EN_MASK) +#define JPGENC_GLB_CTRL_SFTRST_MASK (0x2U) +#define JPGENC_GLB_CTRL_SFTRST_SHIFT (1U) +#define JPGENC_GLB_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_GLB_CTRL_SFTRST_SHIFT)) & JPGENC_GLB_CTRL_SFTRST_MASK) +#define JPGENC_GLB_CTRL_ENC_GO_MASK (0x4U) +#define JPGENC_GLB_CTRL_ENC_GO_SHIFT (2U) +#define JPGENC_GLB_CTRL_ENC_GO(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_GLB_CTRL_ENC_GO_SHIFT)) & JPGENC_GLB_CTRL_ENC_GO_MASK) +#define JPGENC_GLB_CTRL_L_ENDIAN_MASK (0x8U) +#define JPGENC_GLB_CTRL_L_ENDIAN_SHIFT (3U) +#define JPGENC_GLB_CTRL_L_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_GLB_CTRL_L_ENDIAN_SHIFT)) & JPGENC_GLB_CTRL_L_ENDIAN_MASK) +#define JPGENC_GLB_CTRL_SLOT_EN_MASK (0xF0U) +#define JPGENC_GLB_CTRL_SLOT_EN_SHIFT (4U) +#define JPGENC_GLB_CTRL_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_GLB_CTRL_SLOT_EN_SHIFT)) & JPGENC_GLB_CTRL_SLOT_EN_MASK) + +/*! @name COM_STATUS - Common Status */ +#define JPGENC_COM_STATUS_CUR_SLOT_MASK (0x60000000U) +#define JPGENC_COM_STATUS_CUR_SLOT_SHIFT (29U) +#define JPGENC_COM_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_COM_STATUS_CUR_SLOT_SHIFT)) & JPGENC_COM_STATUS_CUR_SLOT_MASK) +#define JPGENC_COM_STATUS_ENC_ONGOING_MASK (0x80000000U) +#define JPGENC_COM_STATUS_ENC_ONGOING_SHIFT (31U) +#define JPGENC_COM_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_COM_STATUS_ENC_ONGOING_SHIFT)) & JPGENC_COM_STATUS_ENC_ONGOING_MASK) + +/*! @name IN_BUF_BASE0 - Input Image Frame Buffer0 Base Address */ +#define JPGENC_IN_BUF_BASE0_IN_BUF_BASE0_MASK (0xFFFFFFF0U) +#define JPGENC_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT (4U) +#define JPGENC_IN_BUF_BASE0_IN_BUF_BASE0(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_IN_BUF_BASE0_IN_BUF_BASE0_SHIFT)) & JPGENC_IN_BUF_BASE0_IN_BUF_BASE0_MASK) + +/*! @name IN_BUF_BASE1 - Input Image Frame Buffer1 Base Address */ +#define JPGENC_IN_BUF_BASE1_IN_BUF_BASE1_MASK (0xFFFFFFF0U) +#define JPGENC_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT (4U) +#define JPGENC_IN_BUF_BASE1_IN_BUF_BASE1(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_IN_BUF_BASE1_IN_BUF_BASE1_SHIFT)) & JPGENC_IN_BUF_BASE1_IN_BUF_BASE1_MASK) + +/*! @name IN_LINE_PITCH - Image Input Buffer Line Pitch */ +#define JPGENC_IN_LINE_PITCH_IN_LINE_PITCH_MASK (0xFFFFU) +#define JPGENC_IN_LINE_PITCH_IN_LINE_PITCH_SHIFT (0U) +#define JPGENC_IN_LINE_PITCH_IN_LINE_PITCH(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_IN_LINE_PITCH_IN_LINE_PITCH_SHIFT)) & JPGENC_IN_LINE_PITCH_IN_LINE_PITCH_MASK) + +/*! @name STM_BUFBASE - Output JPEG Stream Buffer Base Address */ +#define JPGENC_STM_BUFBASE_STM_BUFBASE_MASK (0xFFFFFFF0U) +#define JPGENC_STM_BUFBASE_STM_BUFBASE_SHIFT (4U) +#define JPGENC_STM_BUFBASE_STM_BUFBASE(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_BUFBASE_STM_BUFBASE_SHIFT)) & JPGENC_STM_BUFBASE_STM_BUFBASE_MASK) + +/*! @name STM_BUFSIZE - Output JPEG Stream Buffer Size */ +#define JPGENC_STM_BUFSIZE_STM_BUFSIZE_MASK (0xFFFFFC00U) +#define JPGENC_STM_BUFSIZE_STM_BUFSIZE_SHIFT (10U) +#define JPGENC_STM_BUFSIZE_STM_BUFSIZE(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_BUFSIZE_STM_BUFSIZE_SHIFT)) & JPGENC_STM_BUFSIZE_STM_BUFSIZE_MASK) + +/*! @name IMGSIZE - Image Resolution */ +#define JPGENC_IMGSIZE_IMG_HEIGHT_MASK (0x3FFFU) +#define JPGENC_IMGSIZE_IMG_HEIGHT_SHIFT (0U) +#define JPGENC_IMGSIZE_IMG_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_IMGSIZE_IMG_HEIGHT_SHIFT)) & JPGENC_IMGSIZE_IMG_HEIGHT_MASK) +#define JPGENC_IMGSIZE_IMG_WIDTH_MASK (0x3FFF0000U) +#define JPGENC_IMGSIZE_IMG_WIDTH_SHIFT (16U) +#define JPGENC_IMGSIZE_IMG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_IMGSIZE_IMG_WIDTH_SHIFT)) & JPGENC_IMGSIZE_IMG_WIDTH_MASK) + +/*! @name STM_CTRL - Bit Stream Switch and Control */ +#define JPGENC_STM_CTRL_PIXEL_PRECISION_MASK (0x4U) +#define JPGENC_STM_CTRL_PIXEL_PRECISION_SHIFT (2U) +#define JPGENC_STM_CTRL_PIXEL_PRECISION(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_CTRL_PIXEL_PRECISION_SHIFT)) & JPGENC_STM_CTRL_PIXEL_PRECISION_MASK) +#define JPGENC_STM_CTRL_IMAGE_FORMAT_MASK (0x78U) +#define JPGENC_STM_CTRL_IMAGE_FORMAT_SHIFT (3U) +#define JPGENC_STM_CTRL_IMAGE_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_CTRL_IMAGE_FORMAT_SHIFT)) & JPGENC_STM_CTRL_IMAGE_FORMAT_MASK) +#define JPGENC_STM_CTRL_BITBUF_PTR_CLR_MASK (0x80U) +#define JPGENC_STM_CTRL_BITBUF_PTR_CLR_SHIFT (7U) +#define JPGENC_STM_CTRL_BITBUF_PTR_CLR(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_CTRL_BITBUF_PTR_CLR_SHIFT)) & JPGENC_STM_CTRL_BITBUF_PTR_CLR_MASK) +#define JPGENC_STM_CTRL_AUTO_START_MASK (0x100U) +#define JPGENC_STM_CTRL_AUTO_START_SHIFT (8U) +#define JPGENC_STM_CTRL_AUTO_START(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_CTRL_AUTO_START_SHIFT)) & JPGENC_STM_CTRL_AUTO_START_MASK) +#define JPGENC_STM_CTRL_CONFIG_MOD_MASK (0x200U) +#define JPGENC_STM_CTRL_CONFIG_MOD_SHIFT (9U) +#define JPGENC_STM_CTRL_CONFIG_MOD(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_STM_CTRL_CONFIG_MOD_SHIFT)) & JPGENC_STM_CTRL_CONFIG_MOD_MASK) + +/*! @name SLOT_STATUS - Bit Stream SLOT Status */ +#define JPGENC_SLOT_STATUS_STMBUF_HALF_MASK (0x1U) +#define JPGENC_SLOT_STATUS_STMBUF_HALF_SHIFT (0U) +#define JPGENC_SLOT_STATUS_STMBUF_HALF(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_STMBUF_HALF_SHIFT)) & JPGENC_SLOT_STATUS_STMBUF_HALF_MASK) +#define JPGENC_SLOT_STATUS_STMBUF_RTND_MASK (0x2U) +#define JPGENC_SLOT_STATUS_STMBUF_RTND_SHIFT (1U) +#define JPGENC_SLOT_STATUS_STMBUF_RTND(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_STMBUF_RTND_SHIFT)) & JPGENC_SLOT_STATUS_STMBUF_RTND_MASK) +#define JPGENC_SLOT_STATUS_SWITCHED_IN_MASK (0x4U) +#define JPGENC_SLOT_STATUS_SWITCHED_IN_SHIFT (2U) +#define JPGENC_SLOT_STATUS_SWITCHED_IN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_SWITCHED_IN_SHIFT)) & JPGENC_SLOT_STATUS_SWITCHED_IN_MASK) +#define JPGENC_SLOT_STATUS_FRMDONE_MASK (0x8U) +#define JPGENC_SLOT_STATUS_FRMDONE_SHIFT (3U) +#define JPGENC_SLOT_STATUS_FRMDONE(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_FRMDONE_SHIFT)) & JPGENC_SLOT_STATUS_FRMDONE_MASK) +#define JPGENC_SLOT_STATUS_ENC_CONFG_ERR_MASK (0x100U) +#define JPGENC_SLOT_STATUS_ENC_CONFG_ERR_SHIFT (8U) +#define JPGENC_SLOT_STATUS_ENC_CONFG_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_ENC_CONFG_ERR_SHIFT)) & JPGENC_SLOT_STATUS_ENC_CONFG_ERR_MASK) +#define JPGENC_SLOT_STATUS_DES_RD_ERR_MASK (0x200U) +#define JPGENC_SLOT_STATUS_DES_RD_ERR_SHIFT (9U) +#define JPGENC_SLOT_STATUS_DES_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_DES_RD_ERR_SHIFT)) & JPGENC_SLOT_STATUS_DES_RD_ERR_MASK) +#define JPGENC_SLOT_STATUS_BIT_WT_ERR_MASK (0x400U) +#define JPGENC_SLOT_STATUS_BIT_WT_ERR_SHIFT (10U) +#define JPGENC_SLOT_STATUS_BIT_WT_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_BIT_WT_ERR_SHIFT)) & JPGENC_SLOT_STATUS_BIT_WT_ERR_MASK) +#define JPGENC_SLOT_STATUS_IMG_RD_ERR_MASK (0x800U) +#define JPGENC_SLOT_STATUS_IMG_RD_ERR_SHIFT (11U) +#define JPGENC_SLOT_STATUS_IMG_RD_ERR(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_IMG_RD_ERR_SHIFT)) & JPGENC_SLOT_STATUS_IMG_RD_ERR_MASK) +#define JPGENC_SLOT_STATUS_CUR_SLOT_MASK (0x60000000U) +#define JPGENC_SLOT_STATUS_CUR_SLOT_SHIFT (29U) +#define JPGENC_SLOT_STATUS_CUR_SLOT(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_CUR_SLOT_SHIFT)) & JPGENC_SLOT_STATUS_CUR_SLOT_MASK) +#define JPGENC_SLOT_STATUS_ENC_ONGOING_MASK (0x80000000U) +#define JPGENC_SLOT_STATUS_ENC_ONGOING_SHIFT (31U) +#define JPGENC_SLOT_STATUS_ENC_ONGOING(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_STATUS_ENC_ONGOING_SHIFT)) & JPGENC_SLOT_STATUS_ENC_ONGOING_MASK) + +/* The count of JPGENC_SLOT_STATUS */ +#define JPGENC_SLOT_STATUS_COUNT (4U) + +/*! @name SLOT_IRQ_EN - Bit Stream Interrupt Enable Register */ +#define JPGENC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK (0x1U) +#define JPGENC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT (0U) +#define JPGENC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_STMBUF_HALF_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK (0x2U) +#define JPGENC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT (1U) +#define JPGENC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_STMBUF_RTND_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_SWITHCED_IN_IRQ_EN_MASK (0x4U) +#define JPGENC_SLOT_IRQ_EN_SWITHCED_IN_IRQ_EN_SHIFT (2U) +#define JPGENC_SLOT_IRQ_EN_SWITHCED_IN_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_SWITHCED_IN_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_SWITHCED_IN_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK (0x8U) +#define JPGENC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT (3U) +#define JPGENC_SLOT_IRQ_EN_FRMDONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_FRMDONE_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_MASK (0x100U) +#define JPGENC_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_SHIFT (8U) +#define JPGENC_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_ENC_CONFG_ERR_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK (0x200U) +#define JPGENC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT (9U) +#define JPGENC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_DES_RD_ERR_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_MASK (0x400U) +#define JPGENC_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_SHIFT (10U) +#define JPGENC_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_BIT_WT_ERR_IRQ_EN_MASK) +#define JPGENC_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_MASK (0x800U) +#define JPGENC_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_SHIFT (11U) +#define JPGENC_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_SHIFT)) & JPGENC_SLOT_IRQ_EN_IMG_RD_ERR_IRQ_EN_MASK) + +/* The count of JPGENC_SLOT_IRQ_EN */ +#define JPGENC_SLOT_IRQ_EN_COUNT (4U) + +/*! @name SLOT_BUF_PTR - Bit Stream Buffer Pointer */ +#define JPGENC_SLOT_BUF_PTR_STMBUF_PTR_MASK (0xFFFFFFFFU) +#define JPGENC_SLOT_BUF_PTR_STMBUF_PTR_SHIFT (0U) +#define JPGENC_SLOT_BUF_PTR_STMBUF_PTR(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_BUF_PTR_STMBUF_PTR_SHIFT)) & JPGENC_SLOT_BUF_PTR_STMBUF_PTR_MASK) + +/* The count of JPGENC_SLOT_BUF_PTR */ +#define JPGENC_SLOT_BUF_PTR_COUNT (4U) + +/*! @name SLOT_CUR_DESCPT_PTR - Current Encoding Descriptor Pointer */ +#define JPGENC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK (0xFFFFFFFCU) +#define JPGENC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT (2U) +#define JPGENC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_SHIFT)) & JPGENC_SLOT_CUR_DESCPT_PTR_CUR_DESCPT_PRT_MASK) + +/* The count of JPGENC_SLOT_CUR_DESCPT_PTR */ +#define JPGENC_SLOT_CUR_DESCPT_PTR_COUNT (4U) + +/*! @name SLOT_NXT_DESCPT_PTR - Next Encoding Descriptor Pointer */ +#define JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK (0x1U) +#define JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT (0U) +#define JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_SHIFT)) & JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PTR_EN_MASK) +#define JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK (0xFFFFFFFCU) +#define JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT (2U) +#define JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT(x) (((uint32_t)(((uint32_t)(x)) << JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_SHIFT)) & JPGENC_SLOT_NXT_DESCPT_PTR_NXT_DESCPT_PRT_MASK) + +/* The count of JPGENC_SLOT_NXT_DESCPT_PTR */ +#define JPGENC_SLOT_NXT_DESCPT_PTR_COUNT (4U) + + +/*! + * @} + */ /* end of group JPGENC_Register_Masks */ + + +/* JPGENC - Peripheral instance base addresses */ +/** Peripheral JPGENCWRP base address */ +#define JPGENC_BASE (0u) +/** Peripheral JPGENCWRP base pointer */ +#define JPGENC ((JPGENC_Type *)JPGENC_BASE) +/** Array initializer of JPGENC peripheral base addresses */ +#define JPGENC_BASE_ADDRS { JPGENC_BASE } +/** Array initializer of JPGENC peripheral base pointers */ +#define JPGENC_BASE_PTRS { JPGENC } + +/*! + * @} + */ /* end of group JPGENC_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* JPGENC_H */ + diff --git a/platform/devices/MX8/MX8_lmem_cache.h b/platform/devices/MX8/MX8_lmem_cache.h new file mode 100755 index 0000000..820b0ee --- /dev/null +++ b/platform/devices/MX8/MX8_lmem_cache.h @@ -0,0 +1,342 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_LMEM_CACHE_REGISTERS_H +#define HW_LMEM_CACHE_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- LMEM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer + * @{ + */ + +/** LMEM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */ + __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */ + __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */ + __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */ + uint8_t RESERVED_0[16]; + __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */ + uint8_t RESERVED_1[2012]; + __IO uint32_t PSCCR; /**< Cache control register, offset: 0x800 */ + __IO uint32_t PSCLCR; /**< Cache line control register, offset: 0x804 */ + __IO uint32_t PSCSAR; /**< Cache search address register, offset: 0x808 */ + __IO uint32_t PSCCVR; /**< Cache read/write value register, offset: 0x80C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PSCRMR; /**< Cache regions mode register, offset: 0x820 */ +} LMEM_Type; + +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/*! @name PCCCR - Cache control register */ +#define LMEM_PCCCR_ENCACHE_MASK (0x1U) +#define LMEM_PCCCR_ENCACHE_SHIFT (0U) +#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK) +#define LMEM_PCCCR_ENWRBUF_MASK (0x2U) +#define LMEM_PCCCR_ENWRBUF_SHIFT (1U) +#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK) +#define LMEM_PCCCR_INVW0_MASK (0x1000000U) +#define LMEM_PCCCR_INVW0_SHIFT (24U) +#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK) +#define LMEM_PCCCR_PUSHW0_MASK (0x2000000U) +#define LMEM_PCCCR_PUSHW0_SHIFT (25U) +#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK) +#define LMEM_PCCCR_INVW1_MASK (0x4000000U) +#define LMEM_PCCCR_INVW1_SHIFT (26U) +#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK) +#define LMEM_PCCCR_PUSHW1_MASK (0x8000000U) +#define LMEM_PCCCR_PUSHW1_SHIFT (27U) +#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK) +#define LMEM_PCCCR_GO_MASK (0x80000000U) +#define LMEM_PCCCR_GO_SHIFT (31U) +#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK) + +/*! @name PCCLCR - Cache line control register */ +#define LMEM_PCCLCR_LGO_MASK (0x1U) +#define LMEM_PCCLCR_LGO_SHIFT (0U) +#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK) +#define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU) +#define LMEM_PCCLCR_CACHEADDR_SHIFT (2U) +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK) +#define LMEM_PCCLCR_WSEL_MASK (0x4000U) +#define LMEM_PCCLCR_WSEL_SHIFT (14U) +#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK) +#define LMEM_PCCLCR_TDSEL_MASK (0x10000U) +#define LMEM_PCCLCR_TDSEL_SHIFT (16U) +#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK) +#define LMEM_PCCLCR_LCIVB_MASK (0x100000U) +#define LMEM_PCCLCR_LCIVB_SHIFT (20U) +#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK) +#define LMEM_PCCLCR_LCIMB_MASK (0x200000U) +#define LMEM_PCCLCR_LCIMB_SHIFT (21U) +#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK) +#define LMEM_PCCLCR_LCWAY_MASK (0x400000U) +#define LMEM_PCCLCR_LCWAY_SHIFT (22U) +#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK) +#define LMEM_PCCLCR_LCMD_MASK (0x3000000U) +#define LMEM_PCCLCR_LCMD_SHIFT (24U) +#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK) +#define LMEM_PCCLCR_LADSEL_MASK (0x4000000U) +#define LMEM_PCCLCR_LADSEL_SHIFT (26U) +#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK) +#define LMEM_PCCLCR_LACC_MASK (0x8000000U) +#define LMEM_PCCLCR_LACC_SHIFT (27U) +#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK) + +/*! @name PCCSAR - Cache search address register */ +#define LMEM_PCCSAR_LGO_MASK (0x1U) +#define LMEM_PCCSAR_LGO_SHIFT (0U) +#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK) +#define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) +#define LMEM_PCCSAR_PHYADDR_SHIFT (2U) +#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK) + +/*! @name PCCCVR - Cache read/write value register */ +#define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU) +#define LMEM_PCCCVR_DATA_SHIFT (0U) +#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK) + +/*! @name PCCRMR - Cache regions mode register */ +#define LMEM_PCCRMR_R15_MASK (0x3U) +#define LMEM_PCCRMR_R15_SHIFT (0U) +#define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK) +#define LMEM_PCCRMR_R14_MASK (0xCU) +#define LMEM_PCCRMR_R14_SHIFT (2U) +#define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK) +#define LMEM_PCCRMR_R13_MASK (0x30U) +#define LMEM_PCCRMR_R13_SHIFT (4U) +#define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK) +#define LMEM_PCCRMR_R12_MASK (0xC0U) +#define LMEM_PCCRMR_R12_SHIFT (6U) +#define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK) +#define LMEM_PCCRMR_R11_MASK (0x300U) +#define LMEM_PCCRMR_R11_SHIFT (8U) +#define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK) +#define LMEM_PCCRMR_R10_MASK (0xC00U) +#define LMEM_PCCRMR_R10_SHIFT (10U) +#define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK) +#define LMEM_PCCRMR_R9_MASK (0x3000U) +#define LMEM_PCCRMR_R9_SHIFT (12U) +#define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK) +#define LMEM_PCCRMR_R8_MASK (0xC000U) +#define LMEM_PCCRMR_R8_SHIFT (14U) +#define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK) +#define LMEM_PCCRMR_R7_MASK (0x30000U) +#define LMEM_PCCRMR_R7_SHIFT (16U) +#define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK) +#define LMEM_PCCRMR_R6_MASK (0xC0000U) +#define LMEM_PCCRMR_R6_SHIFT (18U) +#define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK) +#define LMEM_PCCRMR_R5_MASK (0x300000U) +#define LMEM_PCCRMR_R5_SHIFT (20U) +#define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK) +#define LMEM_PCCRMR_R4_MASK (0xC00000U) +#define LMEM_PCCRMR_R4_SHIFT (22U) +#define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK) +#define LMEM_PCCRMR_R3_MASK (0x3000000U) +#define LMEM_PCCRMR_R3_SHIFT (24U) +#define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK) +#define LMEM_PCCRMR_R2_MASK (0xC000000U) +#define LMEM_PCCRMR_R2_SHIFT (26U) +#define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK) +#define LMEM_PCCRMR_R1_MASK (0x30000000U) +#define LMEM_PCCRMR_R1_SHIFT (28U) +#define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK) +#define LMEM_PCCRMR_R0_MASK (0xC0000000U) +#define LMEM_PCCRMR_R0_SHIFT (30U) +#define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK) + +/*! @name PSCCR - Cache control register */ +#define LMEM_PSCCR_ENCACHE_MASK (0x1U) +#define LMEM_PSCCR_ENCACHE_SHIFT (0U) +#define LMEM_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENCACHE_SHIFT)) & LMEM_PSCCR_ENCACHE_MASK) +#define LMEM_PSCCR_ENWRBUF_MASK (0x2U) +#define LMEM_PSCCR_ENWRBUF_SHIFT (1U) +#define LMEM_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_ENWRBUF_SHIFT)) & LMEM_PSCCR_ENWRBUF_MASK) +#define LMEM_PSCCR_INVW0_MASK (0x1000000U) +#define LMEM_PSCCR_INVW0_SHIFT (24U) +#define LMEM_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW0_SHIFT)) & LMEM_PSCCR_INVW0_MASK) +#define LMEM_PSCCR_PUSHW0_MASK (0x2000000U) +#define LMEM_PSCCR_PUSHW0_SHIFT (25U) +#define LMEM_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW0_SHIFT)) & LMEM_PSCCR_PUSHW0_MASK) +#define LMEM_PSCCR_INVW1_MASK (0x4000000U) +#define LMEM_PSCCR_INVW1_SHIFT (26U) +#define LMEM_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_INVW1_SHIFT)) & LMEM_PSCCR_INVW1_MASK) +#define LMEM_PSCCR_PUSHW1_MASK (0x8000000U) +#define LMEM_PSCCR_PUSHW1_SHIFT (27U) +#define LMEM_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_PUSHW1_SHIFT)) & LMEM_PSCCR_PUSHW1_MASK) +#define LMEM_PSCCR_GO_MASK (0x80000000U) +#define LMEM_PSCCR_GO_SHIFT (31U) +#define LMEM_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCR_GO_SHIFT)) & LMEM_PSCCR_GO_MASK) + +/*! @name PSCLCR - Cache line control register */ +#define LMEM_PSCLCR_LGO_MASK (0x1U) +#define LMEM_PSCLCR_LGO_SHIFT (0U) +#define LMEM_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LGO_SHIFT)) & LMEM_PSCLCR_LGO_MASK) +#define LMEM_PSCLCR_CACHEADDR_MASK (0xFFCU) +#define LMEM_PSCLCR_CACHEADDR_SHIFT (2U) +#define LMEM_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_CACHEADDR_SHIFT)) & LMEM_PSCLCR_CACHEADDR_MASK) +#define LMEM_PSCLCR_WSEL_MASK (0x4000U) +#define LMEM_PSCLCR_WSEL_SHIFT (14U) +#define LMEM_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_WSEL_SHIFT)) & LMEM_PSCLCR_WSEL_MASK) +#define LMEM_PSCLCR_TDSEL_MASK (0x10000U) +#define LMEM_PSCLCR_TDSEL_SHIFT (16U) +#define LMEM_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_TDSEL_SHIFT)) & LMEM_PSCLCR_TDSEL_MASK) +#define LMEM_PSCLCR_LCIVB_MASK (0x100000U) +#define LMEM_PSCLCR_LCIVB_SHIFT (20U) +#define LMEM_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIVB_SHIFT)) & LMEM_PSCLCR_LCIVB_MASK) +#define LMEM_PSCLCR_LCIMB_MASK (0x200000U) +#define LMEM_PSCLCR_LCIMB_SHIFT (21U) +#define LMEM_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCIMB_SHIFT)) & LMEM_PSCLCR_LCIMB_MASK) +#define LMEM_PSCLCR_LCWAY_MASK (0x400000U) +#define LMEM_PSCLCR_LCWAY_SHIFT (22U) +#define LMEM_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCWAY_SHIFT)) & LMEM_PSCLCR_LCWAY_MASK) +#define LMEM_PSCLCR_LCMD_MASK (0x3000000U) +#define LMEM_PSCLCR_LCMD_SHIFT (24U) +#define LMEM_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LCMD_SHIFT)) & LMEM_PSCLCR_LCMD_MASK) +#define LMEM_PSCLCR_LADSEL_MASK (0x4000000U) +#define LMEM_PSCLCR_LADSEL_SHIFT (26U) +#define LMEM_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LADSEL_SHIFT)) & LMEM_PSCLCR_LADSEL_MASK) +#define LMEM_PSCLCR_LACC_MASK (0x8000000U) +#define LMEM_PSCLCR_LACC_SHIFT (27U) +#define LMEM_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCLCR_LACC_SHIFT)) & LMEM_PSCLCR_LACC_MASK) + +/*! @name PSCSAR - Cache search address register */ +#define LMEM_PSCSAR_LGO_MASK (0x1U) +#define LMEM_PSCSAR_LGO_SHIFT (0U) +#define LMEM_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_LGO_SHIFT)) & LMEM_PSCSAR_LGO_MASK) +#define LMEM_PSCSAR_PHYADDR_MASK (0xFFFFFFFCU) +#define LMEM_PSCSAR_PHYADDR_SHIFT (2U) +#define LMEM_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCSAR_PHYADDR_SHIFT)) & LMEM_PSCSAR_PHYADDR_MASK) + +/*! @name PSCCVR - Cache read/write value register */ +#define LMEM_PSCCVR_DATA_MASK (0xFFFFFFFFU) +#define LMEM_PSCCVR_DATA_SHIFT (0U) +#define LMEM_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCCVR_DATA_SHIFT)) & LMEM_PSCCVR_DATA_MASK) + +/*! @name PSCRMR - Cache regions mode register */ +#define LMEM_PSCRMR_R15_MASK (0x3U) +#define LMEM_PSCRMR_R15_SHIFT (0U) +#define LMEM_PSCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R15_SHIFT)) & LMEM_PSCRMR_R15_MASK) +#define LMEM_PSCRMR_R14_MASK (0xCU) +#define LMEM_PSCRMR_R14_SHIFT (2U) +#define LMEM_PSCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R14_SHIFT)) & LMEM_PSCRMR_R14_MASK) +#define LMEM_PSCRMR_R13_MASK (0x30U) +#define LMEM_PSCRMR_R13_SHIFT (4U) +#define LMEM_PSCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R13_SHIFT)) & LMEM_PSCRMR_R13_MASK) +#define LMEM_PSCRMR_R12_MASK (0xC0U) +#define LMEM_PSCRMR_R12_SHIFT (6U) +#define LMEM_PSCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R12_SHIFT)) & LMEM_PSCRMR_R12_MASK) +#define LMEM_PSCRMR_R11_MASK (0x300U) +#define LMEM_PSCRMR_R11_SHIFT (8U) +#define LMEM_PSCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R11_SHIFT)) & LMEM_PSCRMR_R11_MASK) +#define LMEM_PSCRMR_R10_MASK (0xC00U) +#define LMEM_PSCRMR_R10_SHIFT (10U) +#define LMEM_PSCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R10_SHIFT)) & LMEM_PSCRMR_R10_MASK) +#define LMEM_PSCRMR_R9_MASK (0x3000U) +#define LMEM_PSCRMR_R9_SHIFT (12U) +#define LMEM_PSCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R9_SHIFT)) & LMEM_PSCRMR_R9_MASK) +#define LMEM_PSCRMR_R8_MASK (0xC000U) +#define LMEM_PSCRMR_R8_SHIFT (14U) +#define LMEM_PSCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R8_SHIFT)) & LMEM_PSCRMR_R8_MASK) +#define LMEM_PSCRMR_R7_MASK (0x30000U) +#define LMEM_PSCRMR_R7_SHIFT (16U) +#define LMEM_PSCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R7_SHIFT)) & LMEM_PSCRMR_R7_MASK) +#define LMEM_PSCRMR_R6_MASK (0xC0000U) +#define LMEM_PSCRMR_R6_SHIFT (18U) +#define LMEM_PSCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R6_SHIFT)) & LMEM_PSCRMR_R6_MASK) +#define LMEM_PSCRMR_R5_MASK (0x300000U) +#define LMEM_PSCRMR_R5_SHIFT (20U) +#define LMEM_PSCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R5_SHIFT)) & LMEM_PSCRMR_R5_MASK) +#define LMEM_PSCRMR_R4_MASK (0xC00000U) +#define LMEM_PSCRMR_R4_SHIFT (22U) +#define LMEM_PSCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R4_SHIFT)) & LMEM_PSCRMR_R4_MASK) +#define LMEM_PSCRMR_R3_MASK (0x3000000U) +#define LMEM_PSCRMR_R3_SHIFT (24U) +#define LMEM_PSCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R3_SHIFT)) & LMEM_PSCRMR_R3_MASK) +#define LMEM_PSCRMR_R2_MASK (0xC000000U) +#define LMEM_PSCRMR_R2_SHIFT (26U) +#define LMEM_PSCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R2_SHIFT)) & LMEM_PSCRMR_R2_MASK) +#define LMEM_PSCRMR_R1_MASK (0x30000000U) +#define LMEM_PSCRMR_R1_SHIFT (28U) +#define LMEM_PSCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R1_SHIFT)) & LMEM_PSCRMR_R1_MASK) +#define LMEM_PSCRMR_R0_MASK (0xC0000000U) +#define LMEM_PSCRMR_R0_SHIFT (30U) +#define LMEM_PSCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PSCRMR_R0_SHIFT)) & LMEM_PSCRMR_R0_MASK) + + +/*! + * @} + */ /* end of group LMEM_Register_Masks */ + + +/* LMEM - Peripheral instance base addresses */ +/** Peripheral LMEM base pointer */ +#define LMEM ((LMEM_Type *)LMEM_BASE) +/** Array initializer of LMEM peripheral base addresses */ +#define LMEM_BASE_ADDRS { LMEM_BASE } +/** Array initializer of LMEM peripheral base pointers */ +#define LMEM_BASE_PTRS { LMEM } + +/*! + * @} + */ /* end of group LMEM_Peripheral_Access_Layer */ + +#endif /* HW_LMEM_CACHE_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_lpc.h b/platform/devices/MX8/MX8_lpc.h new file mode 100755 index 0000000..2735a56 --- /dev/null +++ b/platform/devices/MX8/MX8_lpc.h @@ -0,0 +1,181 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_LPC_REGISTERS_H +#define HW_LPC_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- LPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +#define LPC_NUM_STAGES 7 + +/*! + * @addtogroup LPC_Peripheral_Access_Layer LPC Peripheral Access Layer + * @{ + */ + +/** LPC_CTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t LPC_PC[LPC_NUM_STAGES]; /**< Power Control Register N, offset: 0x0 */ + __IO uint32_t LPC_CR; /**< Configuration Register, offset: 0x1C */ + __IO uint32_t LPC_ED[LPC_NUM_STAGES]; /**< Entry Delay Register N, offset: 0x20 */ + uint32_t RESERVED_0[1]; + __IO uint32_t LPC_XD[LPC_NUM_STAGES]; /**< Exit Delay Register N, offset: 0x40 */ +} LPC_Type, *LPC_MemMapPtr; + + +/* ---------------------------------------------------------------------------- + -- LPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPC_Register_Masks LPC Register Masks + * @{ + */ + +/* LPC_PC Bit Fields */ +/* LPC_CR Bit Fields */ +/* LPC_ED Bit Fields */ +/* LPC_XD Bit Fields */ + +#define LPC_LOW_FANOUT_BIT 0U +#define LPC_HIGH_FANOUT_BIT 1U +#define LPC_INPUT_ISO_BIT 2U +#define LPC_OUTPUT_ISO_BIT 3U +#define LPC_SW_RESETN_BIT 4U +#define LPC_PD_CONTROL_BIT 8U +#define LPC_MEM_LS_CONTROL_BIT 10U +#define LPC_MEM_HS_CONTROL_BIT 11U +#define LPC_RFF_BIT 12U +#define LPC_MEM_SLEEP_BIT 13U +#define LPC_MEM_STDBY_BIT 14U +#define LPC_MEM_IG_BIT 15U +#define LPC_TCM_SMALL_MA_BIT 16U +#define LPC_TCM_LARGE_MA_BIT 17U +#define LPC_CM4_SMALL_MA_BIT 18U +#define LPC_CM4_LARGE_MA_BIT 19U +#define LPC_NSR_SMALL_MA_BIT 20U +#define LPC_NSR_LARGE_MA_BIT 21U +#define LPC_CM0_RAM_SMALL_MA_BIT 22U +#define LPC_CM0_RAM_LARGE_MA_BIT 23U + +#define LPC_LOW_FANOUT BIT(LPC_LOW_FANOUT_BIT) +#define LPC_HIGH_FANOUT BIT(LPC_HIGH_FANOUT_BIT) +#define LPC_INPUT_ISO BIT(LPC_INPUT_ISO_BIT) +#define LPC_OUTPUT_ISO BIT(LPC_OUTPUT_ISO_BIT) +#define LPC_SW_RESETN BIT(LPC_SW_RESETN_BIT) +#define LPC_PD_CONTROL BIT(LPC_PD_CONTROL_BIT) +#define LPC_MEM_LS_CONTROL BIT(LPC_MEM_LS_CONTROL_BIT) +#define LPC_MEM_HS_CONTROL BIT(LPC_MEM_HS_CONTROL_BIT) +#define LPC_RFF BIT(LPC_RFF_BIT) +#define LPC_MEM_SLEEP BIT(LPC_MEM_SLEEP_BIT) +#define LPC_MEM_STDBY BIT(LPC_MEM_STDBY_BIT) +#define LPC_MEM_IG BIT(LPC_MEM_IG_BIT) +#define LPC_TCM_SMALL_MA BIT(LPC_TCM_SMALL_MA_BIT) +#define LPC_TCM_LARGE_MA BIT(LPC_TCM_LARGE_MA_BIT) +#define LPC_CM4_SMALL_MA BIT(LPC_CM4_SMALL_MA_BIT) +#define LPC_CM4_LARGE_MA BIT(LPC_CM4_LARGE_MA_BIT) +#define LPC_NSR_SMALL_MA BIT(LPC_NSR_SMALL_MA_BIT) +#define LPC_NSR_LARGE_MA BIT(LPC_NSR_LARGE_MA_BIT) +#define LPC_CM0_RAM_SMALL_MA BIT(LPC_CM0_RAM_SMALL_MA_BIT) +#define LPC_CM0_RAM_LARGE_MA BIT(LPC_CM0_RAM_LARGE_MA_BIT) + +#define LPC_CR__ROSC_DISABLE 0U +#define LPC_CR__PMIC_STBY 1U +#define LPC_CR__PWRCTRL_MUXSEL 2U +#define LPC_CR__LPC_CLOCK_SEL 4U +#define LPC_CR__LPC_CLOCK_STOP 6U +#define LPC_CR__LPC_CLOCK_GATE 7U + +#define LPC_CLK_25M 0U +#define LPC_CLK_1M 1U +#define LPC_CLK_32K 2U + +typedef uint8_t clk_sel_t; + +#define DSC_PWR_SEL 0U +#define LPC_PWR_SEL 1U + +typedef uint8_t pwr_ctrl_mux_sel_t; + +#define ROSC_EN 0U +#define ROSC_DIS 1U + +typedef uint8_t rosc_dis_t; + +#define PMIC_STDBY_NAST 0U +#define PMIC_STDBY_AST 1U + +typedef uint8_t pmic_stdby_t; + +/*! + * @} + */ /* end of group LPC_Register_Masks */ + + +/** Peripheral LPC base pointer */ +#define LPC ((LPC_Type *)LPC_BASE) + +/* ---------------------------------------------------------------------------- + -- LPC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPC_Register_Accessor_Macros LPC - Register accessor macros + * @{ + */ + + + + +/*! + * @} + */ /* end of group LPC_Peripheral_Access_Layer */ + +#endif /* HW_LPC_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_lpcg.h b/platform/devices/MX8/MX8_lpcg.h new file mode 100755 index 0000000..b6f0c19 --- /dev/null +++ b/platform/devices/MX8/MX8_lpcg.h @@ -0,0 +1,96 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_LPCG_REGISTERS_H +#define HW_LPCG_REGISTERS_H + +#include "lpcg.h" + +/* + * LPCG access macros + */ +#define HW_LPCG_ADDR(lpcg) ((lpcg##__BASE) + (lpcg##__REG)) +#define HW_LPCG_RD(lpcg) (*(volatile uint32_t *)(HW_LPCG_ADDR(lpcg))) +#define HW_LPCG_WR(lpcg, val) (*(volatile uint32_t *)(HW_LPCG_ADDR(lpcg)) = (val)) +#define HW_LPCG_BMSK(lpcg, bit) (1U << (lpcg##__##bit)) +#define HW_LPCG_BSET(lpcg, bit) (HW_LPCG_WR(lpcg, HW_LPCG_RD(lpcg) | HW_LPCG_BMSK(lpcg, bit))) +#define HW_LPCG_BCLR(lpcg, bit) (HW_LPCG_WR(lpcg, HW_LPCG_RD(lpcg) & (~(HW_LPCG_BMSK(lpcg, bit))))) + +/* + * LPCG base addresses + */ +#define LPCG__SS_SCU__CM4__TCMC_HCLK__BASE 0x415E0000U + +#define LPCG__SS_SCU__CM4__MMCAU_HCLK__BASE 0x415F0000U + +#define LPCG__SS_SCU__TPM1__IPG_CLK__BASE 0x41600000U +#define LPCG__SS_SCU__TPM1__LPTPM_CLK__BASE 0x41600000U + +#define LPCG__SS_SCU__LPIT1__IPG_CLK__BASE 0x41610000U +#define LPCG__SS_SCU__LPIT1__IPG_PER_CLK__BASE 0x41610000U +#define LPCG__SS_SCU__LPIT1__IPG_UNGATED_PER_CLK__BASE 0x41610000U + +#define LPCG__SS_SCU__LPUART1__IPG_CLK__BASE 0x41620000U +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_CLK__BASE 0x41620000U +#define LPCG__SS_SCU__LPUART1__LPUART_BAUD_GATED_CLK__BASE 0x41620000U + +#define LPCG__SS_SCU__LPI2C1__IPG_CLK__BASE 0x41630000U +#define LPCG__SS_SCU__LPI2C1__LPI2C_CLK__BASE 0x41630000U +#define LPCG__SS_SCU__LPI2C1__LPI2C_DIV_CLK__BASE 0x41630000U + +/* + * LPCG common bit definitions + */ +#define LPCG__SS_SCU__PER_CLK__HWEN 0U +#define LPCG__SS_SCU__PER_CLK__SWEN 1U +#define LPCG__SS_SCU__PER_CLK__STOP 3U + +#define LPCG__SS_SCU__IPG_CLK__HWEN 4U +#define LPCG__SS_SCU__IPG_CLK__SWEN 5U +#define LPCG__SS_SCU__IPG_CLK__STOP 7U + + +#endif /* HW_LPCG_REGISTERS_H */ + diff --git a/platform/devices/MX8/MX8_lpi2c.h b/platform/devices/MX8/MX8_lpi2c.h new file mode 100755 index 0000000..9b4b822 --- /dev/null +++ b/platform/devices/MX8/MX8_lpi2c.h @@ -0,0 +1,640 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_LPI2C_REGISTERS_H +#define HW_LPI2C_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + uint8_t RESERVED_6[156]; + __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + uint8_t RESERVED_7[4]; + __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) + +/*! @name PARAM - Parameter Register */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) + +/*! @name MCR - Master Control Register */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) + +/*! @name MSR - Master Status Register */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) + +/*! @name MIER - Master Interrupt Enable Register */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +/*! @name MDER - Master DMA Enable Register */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) + +/*! @name MCFGR0 - Master Configuration Register 0 */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +/*! @name MCFGR1 - Master Configuration Register 1 */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) + +/*! @name MCFGR2 - Master Configuration Register 2 */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) + +/*! @name MCFGR3 - Master Configuration Register 3 */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) + +/*! @name MDMR - Master Data Match Register */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) + +/*! @name MFCR - Master FIFO Control Register */ +#define LPI2C_MFCR_TXWATER_MASK (0xFFU) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0xFF0000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) + +/*! @name MFSR - Master FIFO Status Register */ +#define LPI2C_MFSR_TXCOUNT_MASK (0xFFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) + +/*! @name MTDR - Master Transmit Data Register */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) + +/*! @name MRDR - Master Receive Data Register */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) + +/*! @name SCR - Slave Control Register */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) + +/*! @name SSR - Slave Status Register */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) + +/*! @name SIER - Slave Interrupt Enable Register */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) + +/*! @name SDER - Slave DMA Enable Register */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) + +/*! @name SAMR - Slave Address Match Register */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) + +/*! @name SASR - Slave Address Status Register */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) + +/*! @name STAR - Slave Transmit ACK Register */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) + +/*! @name STDR - Slave Transmit Data Register */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) + +/*! @name SRDR - Slave Receive Data Register */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Peripheral LPI2C5 base pointer */ +#define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) +/** Peripheral LPI2C6 base pointer */ +#define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) +/** Peripheral LPI2C7 base pointer */ +#define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) +/** Peripheral LPI2C8 base pointer */ +#define LPI2C8 ((LPI2C_Type *)LPI2C8_BASE) +/** Peripheral LPI2C9 base pointer */ +#define LPI2C9 ((LPI2C_Type *)LPI2C9_BASE) +/** Peripheral LPI2C10 base pointer */ +#define LPI2C10 ((LPI2C_Type *)LPI2C10_BASE) +/** Peripheral LPI2C11 base pointer */ +#define LPI2C11 ((LPI2C_Type *)LPI2C11_BASE) +/** Peripheral LPI2C12 base pointer */ +#define LPI2C12 ((LPI2C_Type *)LPI2C12_BASE) +/** Peripheral LPI2C13 base pointer */ +#define LPI2C13 ((LPI2C_Type *)LPI2C13_BASE) +/** Peripheral LPI2C14 base pointer */ +#define LPI2C14 ((LPI2C_Type *)LPI2C14_BASE) +/** Peripheral LPI2C15 base pointer */ +#define LPI2C15 ((LPI2C_Type *)LPI2C15_BASE) +/** Peripheral LPI2C16 base pointer */ +#define LPI2C16 ((LPI2C_Type *)LPI2C16_BASE) +/** Peripheral LPI2C17 base pointer */ +#define LPI2C17 ((LPI2C_Type *)LPI2C17_BASE) +/** Peripheral LPI2C18 base pointer */ +#define LPI2C18 ((LPI2C_Type *)LPI2C18_BASE) +/** Peripheral LPI2C19 base pointer */ +#define LPI2C19 ((LPI2C_Type *)LPI2C19_BASE) +/** Peripheral LPI2C20 base pointer */ +#define LPI2C20 ((LPI2C_Type *)LPI2C20_BASE) +/** Peripheral LPI2C21 base pointer */ +#define LPI2C21 ((LPI2C_Type *)LPI2C21_BASE) +/** Peripheral LPI2C22 base pointer */ +#define LPI2C22 ((LPI2C_Type *)LPI2C22_BASE) +/** Peripheral LPI2C23 base pointer */ +#define LPI2C23 ((LPI2C_Type *)LPI2C23_BASE) +/** Peripheral LPI2C24 base pointer */ +#define LPI2C24 ((LPI2C_Type *)LPI2C24_BASE) +/** Peripheral LPI2C25 base pointer */ +#define LPI2C25 ((LPI2C_Type *)LPI2C25_BASE) + +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, \ + LPI2C2_BASE, LPI2C3_BASE, \ + LPI2C4_BASE, LPI2C5_BASE, \ + LPI2C6_BASE, LPI2C7_BASE, \ + LPI2C8_BASE, LPI2C9_BASE, \ + LPI2C10_BASE, LPI2C11_BASE, \ + LPI2C12_BASE, LPI2C13_BASE, \ + LPI2C14_BASE, LPI2C15_BASE, \ + LPI2C16_BASE, LPI2C17_BASE, \ + LPI2C18_BASE, LPI2C19_BASE, \ + LPI2C20_BASE, LPI2C21_BASE, \ + LPI2C22_BASE, LPI2C23_BASE, \ + LPI2C24_BASE, LPI2C25_BASE} +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, \ + LPI2C2, LPI2C3, \ + LPI2C4, LPI2C5, \ + LPI2C6, LPI2C7, \ + LPI2C8, LPI2C9, \ + LPI2C10, LPI2C11, \ + LPI2C12, LPI2C13, \ + LPI2C14, LPI2C15, \ + LPI2C16, LPI2C17, \ + LPI2C18, LPI2C19, \ + LPI2C20, LPI2C21, \ + LPI2C22, LPI2C23, \ + LPI2C24, LPI2C25} +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + +#endif /* HW_LPI2C_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_lpit.h b/platform/devices/MX8/MX8_lpit.h new file mode 100755 index 0000000..063110e --- /dev/null +++ b/platform/devices/MX8/MX8_lpit.h @@ -0,0 +1,244 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_LPIT_REGISTERS_H +#define HW_LPIT_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- LPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPIT_Peripheral_Access_Layer LPIT Peripheral Access Layer + * @{ + */ + +/** LPIT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t MCR; /**< Module Control Register, offset: 0x8 */ + __IO uint32_t MSR; /**< Module Status Register, offset: 0xC */ + __IO uint32_t MIER; /**< Module Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t SETTEN; /**< Set Timer Enable Register, offset: 0x14 */ + __IO uint32_t CLRTEN; /**< Clear Timer Enable Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + struct { /* offset: 0x20, array step: 0x10 */ + __IO uint32_t TVAL; /**< Timer Value Register, array offset: 0x20, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value, array offset: 0x24, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[4]; +} LPIT_Type; + +/* ---------------------------------------------------------------------------- + -- LPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPIT_Register_Masks LPIT Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +#define LPIT_VERID_FEATURE_MASK (0xFFFFU) +#define LPIT_VERID_FEATURE_SHIFT (0U) +#define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_FEATURE_SHIFT)) & LPIT_VERID_FEATURE_MASK) +#define LPIT_VERID_MINOR_MASK (0xFF0000U) +#define LPIT_VERID_MINOR_SHIFT (16U) +#define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MINOR_SHIFT)) & LPIT_VERID_MINOR_MASK) +#define LPIT_VERID_MAJOR_MASK (0xFF000000U) +#define LPIT_VERID_MAJOR_SHIFT (24U) +#define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPIT_VERID_MAJOR_SHIFT)) & LPIT_VERID_MAJOR_MASK) + +/*! @name PARAM - Parameter Register */ +#define LPIT_PARAM_CHANNEL_MASK (0xFFU) +#define LPIT_PARAM_CHANNEL_SHIFT (0U) +#define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_CHANNEL_SHIFT)) & LPIT_PARAM_CHANNEL_MASK) +#define LPIT_PARAM_EXT_TRIG_MASK (0xFF00U) +#define LPIT_PARAM_EXT_TRIG_SHIFT (8U) +#define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << LPIT_PARAM_EXT_TRIG_SHIFT)) & LPIT_PARAM_EXT_TRIG_MASK) + +/*! @name MCR - Module Control Register */ +#define LPIT_MCR_M_CEN_MASK (0x1U) +#define LPIT_MCR_M_CEN_SHIFT (0U) +#define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_M_CEN_SHIFT)) & LPIT_MCR_M_CEN_MASK) +#define LPIT_MCR_SW_RST_MASK (0x2U) +#define LPIT_MCR_SW_RST_SHIFT (1U) +#define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK) +#define LPIT_MCR_DOZE_EN_MASK (0x4U) +#define LPIT_MCR_DOZE_EN_SHIFT (2U) +#define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DOZE_EN_SHIFT)) & LPIT_MCR_DOZE_EN_MASK) +#define LPIT_MCR_DBG_EN_MASK (0x8U) +#define LPIT_MCR_DBG_EN_SHIFT (3U) +#define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_DBG_EN_SHIFT)) & LPIT_MCR_DBG_EN_MASK) + +/*! @name MSR - Module Status Register */ +#define LPIT_MSR_TIF0_MASK (0x1U) +#define LPIT_MSR_TIF0_SHIFT (0U) +#define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF0_SHIFT)) & LPIT_MSR_TIF0_MASK) +#define LPIT_MSR_TIF1_MASK (0x2U) +#define LPIT_MSR_TIF1_SHIFT (1U) +#define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF1_SHIFT)) & LPIT_MSR_TIF1_MASK) +#define LPIT_MSR_TIF2_MASK (0x4U) +#define LPIT_MSR_TIF2_SHIFT (2U) +#define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF2_SHIFT)) & LPIT_MSR_TIF2_MASK) +#define LPIT_MSR_TIF3_MASK (0x8U) +#define LPIT_MSR_TIF3_SHIFT (3U) +#define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MSR_TIF3_SHIFT)) & LPIT_MSR_TIF3_MASK) + +/*! @name MIER - Module Interrupt Enable Register */ +#define LPIT_MIER_TIE0_MASK (0x1U) +#define LPIT_MIER_TIE0_SHIFT (0U) +#define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE0_SHIFT)) & LPIT_MIER_TIE0_MASK) +#define LPIT_MIER_TIE1_MASK (0x2U) +#define LPIT_MIER_TIE1_SHIFT (1U) +#define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE1_SHIFT)) & LPIT_MIER_TIE1_MASK) +#define LPIT_MIER_TIE2_MASK (0x4U) +#define LPIT_MIER_TIE2_SHIFT (2U) +#define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE2_SHIFT)) & LPIT_MIER_TIE2_MASK) +#define LPIT_MIER_TIE3_MASK (0x8U) +#define LPIT_MIER_TIE3_SHIFT (3U) +#define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_MIER_TIE3_SHIFT)) & LPIT_MIER_TIE3_MASK) + +/*! @name SETTEN - Set Timer Enable Register */ +#define LPIT_SETTEN_SET_T_EN_0_MASK (0x1U) +#define LPIT_SETTEN_SET_T_EN_0_SHIFT (0U) +#define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_0_SHIFT)) & LPIT_SETTEN_SET_T_EN_0_MASK) +#define LPIT_SETTEN_SET_T_EN_1_MASK (0x2U) +#define LPIT_SETTEN_SET_T_EN_1_SHIFT (1U) +#define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_1_SHIFT)) & LPIT_SETTEN_SET_T_EN_1_MASK) +#define LPIT_SETTEN_SET_T_EN_2_MASK (0x4U) +#define LPIT_SETTEN_SET_T_EN_2_SHIFT (2U) +#define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_2_SHIFT)) & LPIT_SETTEN_SET_T_EN_2_MASK) +#define LPIT_SETTEN_SET_T_EN_3_MASK (0x8U) +#define LPIT_SETTEN_SET_T_EN_3_SHIFT (3U) +#define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_SETTEN_SET_T_EN_3_SHIFT)) & LPIT_SETTEN_SET_T_EN_3_MASK) + +/*! @name CLRTEN - Clear Timer Enable Register */ +#define LPIT_CLRTEN_CLR_T_EN_0_MASK (0x1U) +#define LPIT_CLRTEN_CLR_T_EN_0_SHIFT (0U) +#define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_0_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_0_MASK) +#define LPIT_CLRTEN_CLR_T_EN_1_MASK (0x2U) +#define LPIT_CLRTEN_CLR_T_EN_1_SHIFT (1U) +#define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_1_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_1_MASK) +#define LPIT_CLRTEN_CLR_T_EN_2_MASK (0x4U) +#define LPIT_CLRTEN_CLR_T_EN_2_SHIFT (2U) +#define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_2_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_2_MASK) +#define LPIT_CLRTEN_CLR_T_EN_3_MASK (0x8U) +#define LPIT_CLRTEN_CLR_T_EN_3_SHIFT (3U) +#define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CLRTEN_CLR_T_EN_3_SHIFT)) & LPIT_CLRTEN_CLR_T_EN_3_MASK) + +/*! @name TVAL - Timer Value Register */ +#define LPIT_TVAL_TMR_VAL_MASK (0xFFFFFFFFU) +#define LPIT_TVAL_TMR_VAL_SHIFT (0U) +#define LPIT_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TVAL_TMR_VAL_SHIFT)) & LPIT_TVAL_TMR_VAL_MASK) + +/* The count of LPIT_TVAL */ +#define LPIT_TVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value */ +#define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) +#define LPIT_CVAL_TMR_CUR_VAL_SHIFT (0U) +#define LPIT_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK) + +/* The count of LPIT_CVAL */ +#define LPIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +#define LPIT_TCTRL_T_EN_MASK (0x1U) +#define LPIT_TCTRL_T_EN_SHIFT (0U) +#define LPIT_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_T_EN_SHIFT)) & LPIT_TCTRL_T_EN_MASK) +#define LPIT_TCTRL_CHAIN_MASK (0x2U) +#define LPIT_TCTRL_CHAIN_SHIFT (1U) +#define LPIT_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_CHAIN_SHIFT)) & LPIT_TCTRL_CHAIN_MASK) +#define LPIT_TCTRL_MODE_MASK (0xCU) +#define LPIT_TCTRL_MODE_SHIFT (2U) +#define LPIT_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_MODE_SHIFT)) & LPIT_TCTRL_MODE_MASK) +#define LPIT_TCTRL_TSOT_MASK (0x10000U) +#define LPIT_TCTRL_TSOT_SHIFT (16U) +#define LPIT_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOT_SHIFT)) & LPIT_TCTRL_TSOT_MASK) +#define LPIT_TCTRL_TSOI_MASK (0x20000U) +#define LPIT_TCTRL_TSOI_SHIFT (17U) +#define LPIT_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TSOI_SHIFT)) & LPIT_TCTRL_TSOI_MASK) +#define LPIT_TCTRL_TROT_MASK (0x40000U) +#define LPIT_TCTRL_TROT_SHIFT (18U) +#define LPIT_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TROT_SHIFT)) & LPIT_TCTRL_TROT_MASK) +#define LPIT_TCTRL_TRG_SRC_MASK (0x800000U) +#define LPIT_TCTRL_TRG_SRC_SHIFT (23U) +#define LPIT_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SRC_SHIFT)) & LPIT_TCTRL_TRG_SRC_MASK) +#define LPIT_TCTRL_TRG_SEL_MASK (0xF000000U) +#define LPIT_TCTRL_TRG_SEL_SHIFT (24U) +#define LPIT_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPIT_TCTRL_TRG_SEL_SHIFT)) & LPIT_TCTRL_TRG_SEL_MASK) + +/* The count of LPIT_TCTRL */ +#define LPIT_TCTRL_COUNT (4U) + + +/*! + * @} + */ /* end of group LPIT_Register_Masks */ + + +/* LPIT - Peripheral instance base addresses */ +/** Peripheral LPIT0 base pointer */ +#define LPIT0 ((LPIT_Type *)LPIT0_BASE) +/** Array initializer of LPIT peripheral base addresses */ +#define LPIT_BASE_ADDRS { LPIT0_BASE } +/** Array initializer of LPIT peripheral base pointers */ +#define LPIT_BASE_PTRS { LPIT0 } +/** Interrupt vectors for the LPIT peripheral type */ +#define LPIT_IRQS { LPIT0_IRQn } +/** Clocks for the LPIT peripheral type */ +#define LPIT_CLOCKS { kCLOCK_LPIT_SC } + +/*! + * @} + */ /* end of group LPIT_Peripheral_Access_Layer */ + +#endif /* HW_LPIT_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_lpuart.h b/platform/devices/MX8/MX8_lpuart.h new file mode 100755 index 0000000..b4f7737 --- /dev/null +++ b/platform/devices/MX8/MX8_lpuart.h @@ -0,0 +1,479 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_LPUART_REGISTERS_H +#define HW_LPUART_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ + __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ + __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ + __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) + +/*! @name PARAM - Parameter Register */ +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) + +/*! @name GLOBAL - LPUART Global Register */ +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) + +/*! @name PINCFG - LPUART Pin Configuration Register */ +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) + +/*! @name BAUD - LPUART Baud Rate Register */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) + +/*! @name STAT - LPUART Status Register */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) + +/*! @name CTRL - LPUART Control Register */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) + +/*! @name DATA - LPUART Data Register */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) + +/*! @name MATCH - LPUART Match Address Register */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) + +/*! @name MODIR - LPUART Modem IrDA Register */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_RTSWATER_MASK (0xFF00U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) + +/*! @name FIFO - LPUART FIFO Register */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) + +/*! @name WATER - LPUART Watermark Register */ +#define LPUART_WATER_TXWATER_MASK (0xFFU) +#define LPUART_WATER_TXWATER_SHIFT (0U) +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) +#define LPUART_WATER_TXCOUNT_MASK (0xFF00U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) +#define LPUART_WATER_RXWATER_MASK (0xFF0000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) +#define LPUART_WATER_RXCOUNT_MASK (0xFF000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Peripheral LPUART6 base pointer */ +#define LPUART6 ((LPUART_Type *)LPUART6_BASE) +/** Peripheral LPUART7 base pointer */ +#define LPUART7 ((LPUART_Type *)LPUART7_BASE) +/** Peripheral LPUART8 base pointer */ +#define LPUART8 ((LPUART_Type *)LPUART8_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, \ + LPUART2_BASE, LPUART3_BASE, \ + LPUART4_BASE, LPUART5_BASE, \ + LPUART6_BASE, LPUART7_BASE, \ + LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, \ + LPUART2, LPUART3, \ + LPUART4, LPUART5, \ + LPUART6, LPUART7, \ + LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + +#endif /* HW_LPUART_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_mbist.h b/platform/devices/MX8/MX8_mbist.h new file mode 100755 index 0000000..4e33254 --- /dev/null +++ b/platform/devices/MX8/MX8_mbist.h @@ -0,0 +1,2086 @@ +/* +** ################################################################### +** Processor: mbist +** Compiler: Keil ARM C/C++ Compiler +** Build: b181128 +** +** Abstract: +** CMSIS Peripheral Access Layer for mbist +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file MX8_mbist.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for MX8_mbist + * + * CMSIS Peripheral Access Layer for MX8_mbist + */ + +#ifndef MX8_MBIST_H +#define MX8_MBIST_H /**< Symbol preventing repeated inclusion */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- MBIST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MBIST_Peripheral_Access_Layer MBIST Peripheral Access Layer + * @{ + */ + +/** MBIST - Register Layout Typedef */ +typedef struct { + __IO uint32_t IOR; /**< Internal Offset Register, offset: 0x0 */ + __IO uint32_t IAR; /**< Indirect Access Register, offset: 0x4 */ + __O uint32_t DBA; /**< Direct BIST Access Register (Write), offset: 0x8 */ + __IO uint16_t GCR; /**< General Configuration, offset: 0xC */ + uint8_t RESERVED_0[2]; + __IO uint8_t ACSTA; /**< Address Configuration Start, offset: 0x10 */ + uint8_t RESERVED_1[3]; + __IO uint8_t ACEND; /**< Address Configuration End, offset: 0x14 */ + uint8_t RESERVED_2[3]; + __IO uint16_t ALG1; /**< Algorithm Reg1, offset: 0x18 */ + uint8_t RESERVED_3[2]; + __IO uint32_t ALG2; /**< Algorithm Reg2, offset: 0x1C */ + __IO uint32_t ALG3; /**< Algorithm Reg3, offset: 0x20 */ + __IO uint32_t ALG4; /**< Algorithm Reg4, offset: 0x24 */ + __IO uint32_t ALG5; /**< Algorithm Reg5, offset: 0x28 */ + uint8_t RESERVED_4[16]; + __IO uint8_t BGCR; /**< Background Configuration, offset: 0x3C */ + uint8_t RESERVED_5[3]; + __IO uint8_t MSEL; /**< Memory Selection 1, offset: 0x40 */ + uint8_t RESERVED_6[31]; + __IO uint16_t UDPR; /**< User Defined Port Control, offset: 0x60 */ + uint8_t RESERVED_7[66]; + __IO uint8_t BSTART; /**< BIST Start, offset: 0xA4 */ + uint8_t RESERVED_8[3]; +} MBIST_Type; + +/* ---------------------------------------------------------------------------- + -- MBIST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MBIST_Register_Masks MBIST Register Masks + * @{ + */ + +/*! @name IOR - Internal Offset Register */ +/*! @{ */ +#define MBIST_IOR_OFFSET_MASK (0xFFFFFFFFU) +#define MBIST_IOR_OFFSET_SHIFT (0U) +#define MBIST_IOR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MBIST_IOR_OFFSET_SHIFT)) & MBIST_IOR_OFFSET_MASK) +/*! @} */ + +/*! @name IAR - Indirect Access Register */ +/*! @{ */ +#define MBIST_IAR_VALUE_MASK (0xFFFFFFFFU) +#define MBIST_IAR_VALUE_SHIFT (0U) +#define MBIST_IAR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MBIST_IAR_VALUE_SHIFT)) & MBIST_IAR_VALUE_MASK) +/*! @} */ + +/*! @name DBA - Direct BIST Access Register (Write) */ +/*! @{ */ +#define MBIST_DBA_BSTART_MASK (0x3U) +#define MBIST_DBA_BSTART_SHIFT (0U) +#define MBIST_DBA_BSTART(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_BSTART_SHIFT)) & MBIST_DBA_BSTART_MASK) +#define MBIST_DBA_BRST_MASK (0x4U) +#define MBIST_DBA_BRST_SHIFT (2U) +/*! BRST - Bist Reset + * 0b1..FSLBIST3/ARMport general soft reset. + */ +#define MBIST_DBA_BRST(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_BRST_SHIFT)) & MBIST_DBA_BRST_MASK) +#define MBIST_DBA_SRST_MASK (0x8U) +#define MBIST_DBA_SRST_SHIFT (3U) +/*! SRST - Status Reset + * 0b1..FSLBIST3/ARMport Status reset. This resets: DSMs; BSMs; ipt_bist_status. + */ +#define MBIST_DBA_SRST(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_SRST_SHIFT)) & MBIST_DBA_SRST_MASK) +#define MBIST_DBA_ALGOSEL_MASK (0x1F0U) +#define MBIST_DBA_ALGOSEL_SHIFT (4U) +#define MBIST_DBA_ALGOSEL(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_ALGOSEL_SHIFT)) & MBIST_DBA_ALGOSEL_MASK) +#define MBIST_DBA_DB0_MASK (0x200U) +#define MBIST_DBA_DB0_SHIFT (9U) +#define MBIST_DBA_DB0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_DB0_SHIFT)) & MBIST_DBA_DB0_MASK) +#define MBIST_DBA_DB1_MASK (0x400U) +#define MBIST_DBA_DB1_SHIFT (10U) +#define MBIST_DBA_DB1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_DB1_SHIFT)) & MBIST_DBA_DB1_MASK) +#define MBIST_DBA_DB2_MASK (0x800U) +#define MBIST_DBA_DB2_SHIFT (11U) +#define MBIST_DBA_DB2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_DB2_SHIFT)) & MBIST_DBA_DB2_MASK) +#define MBIST_DBA_BISRLAT_MASK (0x8000U) +#define MBIST_DBA_BISRLAT_SHIFT (15U) +#define MBIST_DBA_BISRLAT(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_BISRLAT_SHIFT)) & MBIST_DBA_BISRLAT_MASK) +#define MBIST_DBA_UDPR_MASK (0xFFFF0000U) +#define MBIST_DBA_UDPR_SHIFT (16U) +#define MBIST_DBA_UDPR(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBA_UDPR_SHIFT)) & MBIST_DBA_UDPR_MASK) +/*! @} */ + +/*! @name GCR - General Configuration */ +/*! @{ */ +#define MBIST_GCR_OPM_MASK (0x7U) +#define MBIST_GCR_OPM_SHIFT (0U) +/*! OPM - Operation Mode + * 0b000..Normal Sticky Mode - Test runs from start to end and then stops (The fail signal will be asserted as soon as an error is detected and stays asserted until reset at the end of the test). + * 0b001..RESERVED + * 0b010..Run-Forever Sticky Mode - Test repeats forever. The fail bit will be asserted as soon as an error is detected and it stays asserted. + * 0b011..RESERVED + * 0b100..Stop-On-Fail Mode - Test stops when a fail is detected and can then be resumed under user command (manual fail data upload). + * 0b101..RESERVED + * 0b110..Stop-On-Read Mode (just for ROM test) - Test stops on each read and can then be resumed (manual fail data uploaded) + * 0b111..RESERVED + */ +#define MBIST_GCR_OPM(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_OPM_SHIFT)) & MBIST_GCR_OPM_MASK) +#define MBIST_GCR_AMODE_MASK (0x38U) +#define MBIST_GCR_AMODE_SHIFT (3U) +/*! AMODE - Address Mode + * 0b000..Natural (or Normal) Addressing - Addresses are incremented from first memory position to up. + * 0b001..Block fast - Block address are incremented first, the other addresses are incremented as address bits were rotated making the block-bits the LSBs. + * 0b010..Column Fast - Column address are incremented first, the other addresses are incremented as the address bits were rotated making the column-bits the LSBs. + * 0b011..Row Fast - Row addresses are incremented first, then column; the other addresses are incremented as the address bits were rotated making the row-bits the LSBs. + * 0b100..Gang Fast - The gang addresses are incremented first, the other addresses are incremented as the address bits were rotated making the gang-bits the LSBs. + * 0b101..Reserved (if selected it falls back to default -Natural Addressing) + * 0b110..Reserved (if selected it falls back to default -Natural Addressing) + * 0b111..Anybit Fast - In this mode, the test will be run multiple times one for each address bit being the fast bit of the run. Attention! Running this mode takes a long time. + */ +#define MBIST_GCR_AMODE(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_AMODE_SHIFT)) & MBIST_GCR_AMODE_MASK) +#define MBIST_GCR_MAM_MASK (0x1C0U) +#define MBIST_GCR_MAM_SHIFT (6U) +/*! MAM - Dual Port Test Configuration + * 0b000..Disable both Automatic (A/B) and Dual Port stress Tests + * 0b001..Automatic A/B Test with same address + * 0b010..Automatic A/B Test but disable Dual Port stress Test + * 0b011..Automatic A/B Test with adjacent address + * 0b100..Regular Test with same address and port A as primary + * 0b101..Regular Test with same address and port B as primary + * 0b110..Regular Test with adjacent address and port A as primary + * 0b111..Regular Test with adjacent address and port B as primary + */ +#define MBIST_GCR_MAM(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_MAM_SHIFT)) & MBIST_GCR_MAM_MASK) +#define MBIST_GCR_CEN_MASK (0x200U) +#define MBIST_GCR_CEN_SHIFT (9U) +/*! CEN - Continuous Enabled + * 0b0..Continuous Enable mode de-active. + * 0b1..Continuous Enable mode active. + */ +#define MBIST_GCR_CEN(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_CEN_SHIFT)) & MBIST_GCR_CEN_MASK) +#define MBIST_GCR_NOCOMP_MASK (0x400U) +#define MBIST_GCR_NOCOMP_SHIFT (10U) +/*! NOCOMP - No Compare + * 0b0..Normal compare is performed in RAM tests. + * 0b1..No compare is performed in RAM tests. + */ +#define MBIST_GCR_NOCOMP(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_NOCOMP_SHIFT)) & MBIST_GCR_NOCOMP_MASK) +#define MBIST_GCR_IWEN_MASK (0x800U) +#define MBIST_GCR_IWEN_SHIFT (11U) +/*! IWEN - Bit Write Enable Test Mode + * 0b0..Disable bit/word write enable test mode. + * 0b1..Enable bit/word write enable test mode. + */ +#define MBIST_GCR_IWEN(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_IWEN_SHIFT)) & MBIST_GCR_IWEN_MASK) +#define MBIST_GCR_MC_RST_MASK (0x1000U) +#define MBIST_GCR_MC_RST_SHIFT (12U) +/*! MC_RST - Memory Configuration Reset + * 0b1..Reset memory configuration. + */ +#define MBIST_GCR_MC_RST(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_MC_RST_SHIFT)) & MBIST_GCR_MC_RST_MASK) +#define MBIST_GCR_RDHLD_MASK (0x4000U) +#define MBIST_GCR_RDHLD_SHIFT (14U) +#define MBIST_GCR_RDHLD(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_RDHLD_SHIFT)) & MBIST_GCR_RDHLD_MASK) +#define MBIST_GCR_BURNIN_MASK (0x8000U) +#define MBIST_GCR_BURNIN_SHIFT (15U) +#define MBIST_GCR_BURNIN(x) (((uint16_t)(((uint16_t)(x)) << MBIST_GCR_BURNIN_SHIFT)) & MBIST_GCR_BURNIN_MASK) +/*! @} */ + +/*! @name ACSTA - Address Configuration Start */ +/*! @{ */ +#define MBIST_ACSTA_STARTA_MASK (0x7FFU) +#define MBIST_ACSTA_STARTA_SHIFT (0U) +#define MBIST_ACSTA_STARTA(x) (((uint8_t)(((uint8_t)(x)) << MBIST_ACSTA_STARTA_SHIFT)) & MBIST_ACSTA_STARTA_MASK) +/*! @} */ + +/*! @name ACEND - Address Configuration End */ +/*! @{ */ +#define MBIST_ACEND_ENDA_MASK (0x7FFU) +#define MBIST_ACEND_ENDA_SHIFT (0U) +#define MBIST_ACEND_ENDA(x) (((uint8_t)(((uint8_t)(x)) << MBIST_ACEND_ENDA_SHIFT)) & MBIST_ACEND_ENDA_MASK) +/*! @} */ + +/*! @name ALG1 - Algorithm Reg1 */ +/*! @{ */ +#define MBIST_ALG1_VME_MASK (0x7U) +#define MBIST_ALG1_VME_SHIFT (0U) +/*! VME - Valid March Elements + * 0b000..ME0 + * 0b001..ME0 Through ME1 + * 0b010..ME0 Through ME2 + * 0b011..ME0 Through ME3 + * 0b100..ME0 Through ME4 + * 0b101..ME0 Through ME5 + * 0b110..ME0 Through ME6 + * 0b111..ME0 Through ME7 + */ +#define MBIST_ALG1_VME(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_VME_SHIFT)) & MBIST_ALG1_VME_MASK) +#define MBIST_ALG1_PAUSE_0_MASK (0x8U) +#define MBIST_ALG1_PAUSE_0_SHIFT (3U) +#define MBIST_ALG1_PAUSE_0(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_0_SHIFT)) & MBIST_ALG1_PAUSE_0_MASK) +#define MBIST_ALG1_PAUSE_1_MASK (0x10U) +#define MBIST_ALG1_PAUSE_1_SHIFT (4U) +#define MBIST_ALG1_PAUSE_1(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_1_SHIFT)) & MBIST_ALG1_PAUSE_1_MASK) +#define MBIST_ALG1_PAUSE_2_MASK (0x20U) +#define MBIST_ALG1_PAUSE_2_SHIFT (5U) +#define MBIST_ALG1_PAUSE_2(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_2_SHIFT)) & MBIST_ALG1_PAUSE_2_MASK) +#define MBIST_ALG1_PAUSE_3_MASK (0x40U) +#define MBIST_ALG1_PAUSE_3_SHIFT (6U) +#define MBIST_ALG1_PAUSE_3(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_3_SHIFT)) & MBIST_ALG1_PAUSE_3_MASK) +#define MBIST_ALG1_PAUSE_4_MASK (0x80U) +#define MBIST_ALG1_PAUSE_4_SHIFT (7U) +#define MBIST_ALG1_PAUSE_4(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_4_SHIFT)) & MBIST_ALG1_PAUSE_4_MASK) +#define MBIST_ALG1_PAUSE_5_MASK (0x100U) +#define MBIST_ALG1_PAUSE_5_SHIFT (8U) +#define MBIST_ALG1_PAUSE_5(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_5_SHIFT)) & MBIST_ALG1_PAUSE_5_MASK) +#define MBIST_ALG1_PAUSE_6_MASK (0x200U) +#define MBIST_ALG1_PAUSE_6_SHIFT (9U) +#define MBIST_ALG1_PAUSE_6(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_6_SHIFT)) & MBIST_ALG1_PAUSE_6_MASK) +#define MBIST_ALG1_PAUSE_7_MASK (0x400U) +#define MBIST_ALG1_PAUSE_7_SHIFT (10U) +#define MBIST_ALG1_PAUSE_7(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_PAUSE_7_SHIFT)) & MBIST_ALG1_PAUSE_7_MASK) +#define MBIST_ALG1_MP_REP_MASK (0xF800U) +#define MBIST_ALG1_MP_REP_SHIFT (11U) +#define MBIST_ALG1_MP_REP(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_MP_REP_SHIFT)) & MBIST_ALG1_MP_REP_MASK) +#define MBIST_ALG1_ALGSEL_MASK (0x1F0000U) +#define MBIST_ALG1_ALGSEL_SHIFT (16U) +#define MBIST_ALG1_ALGSEL(x) (((uint16_t)(((uint16_t)(x)) << MBIST_ALG1_ALGSEL_SHIFT)) & MBIST_ALG1_ALGSEL_MASK) +/*! @} */ + +/*! @name ALG2 - Algorithm Reg2 */ +/*! @{ */ +#define MBIST_ALG2_ME0_D_MASK (0x1U) +#define MBIST_ALG2_ME0_D_SHIFT (0U) +/*! ME0_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG2_ME0_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_D_SHIFT)) & MBIST_ALG2_ME0_D_MASK) +#define MBIST_ALG2_ME0_VMP_MASK (0xEU) +#define MBIST_ALG2_ME0_VMP_SHIFT (1U) +/*! ME0_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG2_ME0_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_VMP_SHIFT)) & MBIST_ALG2_ME0_VMP_MASK) +#define MBIST_ALG2_ME0_MP0_MASK (0x30U) +#define MBIST_ALG2_ME0_MP0_SHIFT (4U) +/*! ME0_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME0_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_MP0_SHIFT)) & MBIST_ALG2_ME0_MP0_MASK) +#define MBIST_ALG2_ME0_MP1_MASK (0xC0U) +#define MBIST_ALG2_ME0_MP1_SHIFT (6U) +/*! ME0_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME0_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_MP1_SHIFT)) & MBIST_ALG2_ME0_MP1_MASK) +#define MBIST_ALG2_ME0_MP2_MASK (0x300U) +#define MBIST_ALG2_ME0_MP2_SHIFT (8U) +/*! ME0_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME0_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_MP2_SHIFT)) & MBIST_ALG2_ME0_MP2_MASK) +#define MBIST_ALG2_ME0_MP3_MASK (0xC00U) +#define MBIST_ALG2_ME0_MP3_SHIFT (10U) +/*! ME0_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME0_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_MP3_SHIFT)) & MBIST_ALG2_ME0_MP3_MASK) +#define MBIST_ALG2_ME0_MP4_MASK (0x3000U) +#define MBIST_ALG2_ME0_MP4_SHIFT (12U) +/*! ME0_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME0_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_MP4_SHIFT)) & MBIST_ALG2_ME0_MP4_MASK) +#define MBIST_ALG2_ME0_MP5_MASK (0xC000U) +#define MBIST_ALG2_ME0_MP5_SHIFT (14U) +/*! ME0_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME0_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME0_MP5_SHIFT)) & MBIST_ALG2_ME0_MP5_MASK) +#define MBIST_ALG2_ME1_D_MASK (0x10000U) +#define MBIST_ALG2_ME1_D_SHIFT (16U) +/*! ME1_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG2_ME1_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_D_SHIFT)) & MBIST_ALG2_ME1_D_MASK) +#define MBIST_ALG2_ME1_VMP_MASK (0xE0000U) +#define MBIST_ALG2_ME1_VMP_SHIFT (17U) +/*! ME1_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG2_ME1_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_VMP_SHIFT)) & MBIST_ALG2_ME1_VMP_MASK) +#define MBIST_ALG2_ME1_MP0_MASK (0x300000U) +#define MBIST_ALG2_ME1_MP0_SHIFT (20U) +/*! ME1_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME1_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_MP0_SHIFT)) & MBIST_ALG2_ME1_MP0_MASK) +#define MBIST_ALG2_ME1_MP1_MASK (0xC00000U) +#define MBIST_ALG2_ME1_MP1_SHIFT (22U) +/*! ME1_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME1_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_MP1_SHIFT)) & MBIST_ALG2_ME1_MP1_MASK) +#define MBIST_ALG2_ME1_MP2_MASK (0x3000000U) +#define MBIST_ALG2_ME1_MP2_SHIFT (24U) +/*! ME1_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME1_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_MP2_SHIFT)) & MBIST_ALG2_ME1_MP2_MASK) +#define MBIST_ALG2_ME1_MP3_MASK (0xC000000U) +#define MBIST_ALG2_ME1_MP3_SHIFT (26U) +/*! ME1_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME1_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_MP3_SHIFT)) & MBIST_ALG2_ME1_MP3_MASK) +#define MBIST_ALG2_ME1_MP4_MASK (0x30000000U) +#define MBIST_ALG2_ME1_MP4_SHIFT (28U) +/*! ME1_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME1_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_MP4_SHIFT)) & MBIST_ALG2_ME1_MP4_MASK) +#define MBIST_ALG2_ME1_MP5_MASK (0xC0000000U) +#define MBIST_ALG2_ME1_MP5_SHIFT (30U) +/*! ME1_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG2_ME1_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG2_ME1_MP5_SHIFT)) & MBIST_ALG2_ME1_MP5_MASK) +/*! @} */ + +/*! @name ALG3 - Algorithm Reg3 */ +/*! @{ */ +#define MBIST_ALG3_ME2_D_MASK (0x1U) +#define MBIST_ALG3_ME2_D_SHIFT (0U) +/*! ME2_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG3_ME2_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_D_SHIFT)) & MBIST_ALG3_ME2_D_MASK) +#define MBIST_ALG3_ME2_VMP_MASK (0xEU) +#define MBIST_ALG3_ME2_VMP_SHIFT (1U) +/*! ME2_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG3_ME2_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_VMP_SHIFT)) & MBIST_ALG3_ME2_VMP_MASK) +#define MBIST_ALG3_ME2_MP0_MASK (0x30U) +#define MBIST_ALG3_ME2_MP0_SHIFT (4U) +/*! ME2_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME2_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_MP0_SHIFT)) & MBIST_ALG3_ME2_MP0_MASK) +#define MBIST_ALG3_ME2_MP1_MASK (0xC0U) +#define MBIST_ALG3_ME2_MP1_SHIFT (6U) +/*! ME2_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME2_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_MP1_SHIFT)) & MBIST_ALG3_ME2_MP1_MASK) +#define MBIST_ALG3_ME2_MP2_MASK (0x300U) +#define MBIST_ALG3_ME2_MP2_SHIFT (8U) +/*! ME2_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME2_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_MP2_SHIFT)) & MBIST_ALG3_ME2_MP2_MASK) +#define MBIST_ALG3_ME2_MP3_MASK (0xC00U) +#define MBIST_ALG3_ME2_MP3_SHIFT (10U) +/*! ME2_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME2_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_MP3_SHIFT)) & MBIST_ALG3_ME2_MP3_MASK) +#define MBIST_ALG3_ME2_MP4_MASK (0x3000U) +#define MBIST_ALG3_ME2_MP4_SHIFT (12U) +/*! ME2_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME2_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_MP4_SHIFT)) & MBIST_ALG3_ME2_MP4_MASK) +#define MBIST_ALG3_ME2_MP5_MASK (0xC000U) +#define MBIST_ALG3_ME2_MP5_SHIFT (14U) +/*! ME2_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME2_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME2_MP5_SHIFT)) & MBIST_ALG3_ME2_MP5_MASK) +#define MBIST_ALG3_ME3_D_MASK (0x10000U) +#define MBIST_ALG3_ME3_D_SHIFT (16U) +/*! ME3_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG3_ME3_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_D_SHIFT)) & MBIST_ALG3_ME3_D_MASK) +#define MBIST_ALG3_ME3_VMP_MASK (0xE0000U) +#define MBIST_ALG3_ME3_VMP_SHIFT (17U) +/*! ME3_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG3_ME3_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_VMP_SHIFT)) & MBIST_ALG3_ME3_VMP_MASK) +#define MBIST_ALG3_ME3_MP0_MASK (0x300000U) +#define MBIST_ALG3_ME3_MP0_SHIFT (20U) +/*! ME3_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME3_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_MP0_SHIFT)) & MBIST_ALG3_ME3_MP0_MASK) +#define MBIST_ALG3_ME3_MP1_MASK (0xC00000U) +#define MBIST_ALG3_ME3_MP1_SHIFT (22U) +/*! ME3_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME3_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_MP1_SHIFT)) & MBIST_ALG3_ME3_MP1_MASK) +#define MBIST_ALG3_ME3_MP2_MASK (0x3000000U) +#define MBIST_ALG3_ME3_MP2_SHIFT (24U) +/*! ME3_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME3_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_MP2_SHIFT)) & MBIST_ALG3_ME3_MP2_MASK) +#define MBIST_ALG3_ME3_MP3_MASK (0xC000000U) +#define MBIST_ALG3_ME3_MP3_SHIFT (26U) +/*! ME3_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME3_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_MP3_SHIFT)) & MBIST_ALG3_ME3_MP3_MASK) +#define MBIST_ALG3_ME3_MP4_MASK (0x30000000U) +#define MBIST_ALG3_ME3_MP4_SHIFT (28U) +/*! ME3_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME3_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_MP4_SHIFT)) & MBIST_ALG3_ME3_MP4_MASK) +#define MBIST_ALG3_ME3_MP5_MASK (0xC0000000U) +#define MBIST_ALG3_ME3_MP5_SHIFT (30U) +/*! ME3_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG3_ME3_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG3_ME3_MP5_SHIFT)) & MBIST_ALG3_ME3_MP5_MASK) +/*! @} */ + +/*! @name ALG4 - Algorithm Reg4 */ +/*! @{ */ +#define MBIST_ALG4_ME4_D_MASK (0x1U) +#define MBIST_ALG4_ME4_D_SHIFT (0U) +/*! ME4_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG4_ME4_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_D_SHIFT)) & MBIST_ALG4_ME4_D_MASK) +#define MBIST_ALG4_ME4_VMP_MASK (0xEU) +#define MBIST_ALG4_ME4_VMP_SHIFT (1U) +/*! ME4_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG4_ME4_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_VMP_SHIFT)) & MBIST_ALG4_ME4_VMP_MASK) +#define MBIST_ALG4_ME4_MP0_MASK (0x30U) +#define MBIST_ALG4_ME4_MP0_SHIFT (4U) +/*! ME4_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME4_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_MP0_SHIFT)) & MBIST_ALG4_ME4_MP0_MASK) +#define MBIST_ALG4_ME4_MP1_MASK (0xC0U) +#define MBIST_ALG4_ME4_MP1_SHIFT (6U) +/*! ME4_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME4_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_MP1_SHIFT)) & MBIST_ALG4_ME4_MP1_MASK) +#define MBIST_ALG4_ME4_MP2_MASK (0x300U) +#define MBIST_ALG4_ME4_MP2_SHIFT (8U) +/*! ME4_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME4_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_MP2_SHIFT)) & MBIST_ALG4_ME4_MP2_MASK) +#define MBIST_ALG4_ME4_MP3_MASK (0xC00U) +#define MBIST_ALG4_ME4_MP3_SHIFT (10U) +/*! ME4_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME4_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_MP3_SHIFT)) & MBIST_ALG4_ME4_MP3_MASK) +#define MBIST_ALG4_ME4_MP4_MASK (0x3000U) +#define MBIST_ALG4_ME4_MP4_SHIFT (12U) +/*! ME4_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME4_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_MP4_SHIFT)) & MBIST_ALG4_ME4_MP4_MASK) +#define MBIST_ALG4_ME4_MP5_MASK (0xC000U) +#define MBIST_ALG4_ME4_MP5_SHIFT (14U) +/*! ME4_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME4_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME4_MP5_SHIFT)) & MBIST_ALG4_ME4_MP5_MASK) +#define MBIST_ALG4_ME5_D_MASK (0x10000U) +#define MBIST_ALG4_ME5_D_SHIFT (16U) +/*! ME5_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG4_ME5_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_D_SHIFT)) & MBIST_ALG4_ME5_D_MASK) +#define MBIST_ALG4_ME5_VMP_MASK (0xE0000U) +#define MBIST_ALG4_ME5_VMP_SHIFT (17U) +/*! ME5_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG4_ME5_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_VMP_SHIFT)) & MBIST_ALG4_ME5_VMP_MASK) +#define MBIST_ALG4_ME5_MP0_MASK (0x300000U) +#define MBIST_ALG4_ME5_MP0_SHIFT (20U) +/*! ME5_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME5_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_MP0_SHIFT)) & MBIST_ALG4_ME5_MP0_MASK) +#define MBIST_ALG4_ME5_MP1_MASK (0xC00000U) +#define MBIST_ALG4_ME5_MP1_SHIFT (22U) +/*! ME5_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME5_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_MP1_SHIFT)) & MBIST_ALG4_ME5_MP1_MASK) +#define MBIST_ALG4_ME5_MP2_MASK (0x3000000U) +#define MBIST_ALG4_ME5_MP2_SHIFT (24U) +/*! ME5_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME5_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_MP2_SHIFT)) & MBIST_ALG4_ME5_MP2_MASK) +#define MBIST_ALG4_ME5_MP3_MASK (0xC000000U) +#define MBIST_ALG4_ME5_MP3_SHIFT (26U) +/*! ME5_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME5_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_MP3_SHIFT)) & MBIST_ALG4_ME5_MP3_MASK) +#define MBIST_ALG4_ME5_MP4_MASK (0x30000000U) +#define MBIST_ALG4_ME5_MP4_SHIFT (28U) +/*! ME5_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME5_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_MP4_SHIFT)) & MBIST_ALG4_ME5_MP4_MASK) +#define MBIST_ALG4_ME5_MP5_MASK (0xC0000000U) +#define MBIST_ALG4_ME5_MP5_SHIFT (30U) +/*! ME5_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG4_ME5_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG4_ME5_MP5_SHIFT)) & MBIST_ALG4_ME5_MP5_MASK) +/*! @} */ + +/*! @name ALG5 - Algorithm Reg5 */ +/*! @{ */ +#define MBIST_ALG5_ME6_D_MASK (0x1U) +#define MBIST_ALG5_ME6_D_SHIFT (0U) +/*! ME6_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG5_ME6_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_D_SHIFT)) & MBIST_ALG5_ME6_D_MASK) +#define MBIST_ALG5_ME6_VMP_MASK (0xEU) +#define MBIST_ALG5_ME6_VMP_SHIFT (1U) +/*! ME6_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG5_ME6_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_VMP_SHIFT)) & MBIST_ALG5_ME6_VMP_MASK) +#define MBIST_ALG5_ME6_MP0_MASK (0x30U) +#define MBIST_ALG5_ME6_MP0_SHIFT (4U) +/*! ME6_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME6_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_MP0_SHIFT)) & MBIST_ALG5_ME6_MP0_MASK) +#define MBIST_ALG5_ME6_MP1_MASK (0xC0U) +#define MBIST_ALG5_ME6_MP1_SHIFT (6U) +/*! ME6_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME6_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_MP1_SHIFT)) & MBIST_ALG5_ME6_MP1_MASK) +#define MBIST_ALG5_ME6_MP2_MASK (0x300U) +#define MBIST_ALG5_ME6_MP2_SHIFT (8U) +/*! ME6_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME6_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_MP2_SHIFT)) & MBIST_ALG5_ME6_MP2_MASK) +#define MBIST_ALG5_ME6_MP3_MASK (0xC00U) +#define MBIST_ALG5_ME6_MP3_SHIFT (10U) +/*! ME6_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME6_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_MP3_SHIFT)) & MBIST_ALG5_ME6_MP3_MASK) +#define MBIST_ALG5_ME6_MP4_MASK (0x3000U) +#define MBIST_ALG5_ME6_MP4_SHIFT (12U) +/*! ME6_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME6_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_MP4_SHIFT)) & MBIST_ALG5_ME6_MP4_MASK) +#define MBIST_ALG5_ME6_MP5_MASK (0xC000U) +#define MBIST_ALG5_ME6_MP5_SHIFT (14U) +/*! ME6_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME6_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME6_MP5_SHIFT)) & MBIST_ALG5_ME6_MP5_MASK) +#define MBIST_ALG5_ME7_D_MASK (0x10000U) +#define MBIST_ALG5_ME7_D_SHIFT (16U) +/*! ME7_D - Address Direction + * 0b0..Address generator is decremented from ENDA to STARTA. + * 0b1..Address generator is incremented from STARTA to ENDA. + */ +#define MBIST_ALG5_ME7_D(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_D_SHIFT)) & MBIST_ALG5_ME7_D_MASK) +#define MBIST_ALG5_ME7_VMP_MASK (0xE0000U) +#define MBIST_ALG5_ME7_VMP_SHIFT (17U) +/*! ME7_VMP - Valid March Phases + * 0b000..MP0 + * 0b001..MP0 through MP1 + * 0b010..MP0 through MP2 + * 0b011..MP0 through MP3 + * 0b100..MP0 through MP4 + * 0b101..MP0 through MP5 + * 0b110..Illegal value + * 0b111..March Phase Replication + */ +#define MBIST_ALG5_ME7_VMP(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_VMP_SHIFT)) & MBIST_ALG5_ME7_VMP_MASK) +#define MBIST_ALG5_ME7_MP0_MASK (0x300000U) +#define MBIST_ALG5_ME7_MP0_SHIFT (20U) +/*! ME7_MP0 - March Phase 0 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME7_MP0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_MP0_SHIFT)) & MBIST_ALG5_ME7_MP0_MASK) +#define MBIST_ALG5_ME7_MP1_MASK (0xC00000U) +#define MBIST_ALG5_ME7_MP1_SHIFT (22U) +/*! ME7_MP1 - March Phase 1 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME7_MP1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_MP1_SHIFT)) & MBIST_ALG5_ME7_MP1_MASK) +#define MBIST_ALG5_ME7_MP2_MASK (0x3000000U) +#define MBIST_ALG5_ME7_MP2_SHIFT (24U) +/*! ME7_MP2 - March Phase 2 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME7_MP2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_MP2_SHIFT)) & MBIST_ALG5_ME7_MP2_MASK) +#define MBIST_ALG5_ME7_MP3_MASK (0xC000000U) +#define MBIST_ALG5_ME7_MP3_SHIFT (26U) +/*! ME7_MP3 - March Phase 3 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME7_MP3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_MP3_SHIFT)) & MBIST_ALG5_ME7_MP3_MASK) +#define MBIST_ALG5_ME7_MP4_MASK (0x30000000U) +#define MBIST_ALG5_ME7_MP4_SHIFT (28U) +/*! ME7_MP4 - March Phase 4 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME7_MP4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_MP4_SHIFT)) & MBIST_ALG5_ME7_MP4_MASK) +#define MBIST_ALG5_ME7_MP5_MASK (0xC0000000U) +#define MBIST_ALG5_ME7_MP5_SHIFT (30U) +/*! ME7_MP5 - March Phase 5 + * 0b00..R0 - Read data background. + * 0b01..R1 - Read inverted data background. + * 0b10..W0 - Write data background. + * 0b11..W1 -Write inverted data background. + */ +#define MBIST_ALG5_ME7_MP5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_ALG5_ME7_MP5_SHIFT)) & MBIST_ALG5_ME7_MP5_MASK) +/*! @} */ + +/*! @name BGCR - Background Configuration */ +/*! @{ */ +#define MBIST_BGCR_DB0_MASK (0x1U) +#define MBIST_BGCR_DB0_SHIFT (0U) +/*! DB0 - Data Background 0 + * 0b0..No checkerboard data background will be used. + * 0b1..The checkerboard data background will be used. + */ +#define MBIST_BGCR_DB0(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB0_SHIFT)) & MBIST_BGCR_DB0_MASK) +#define MBIST_BGCR_DB1_MASK (0x2U) +#define MBIST_BGCR_DB1_SHIFT (1U) +/*! DB1 - Data Background 1 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB1(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB1_SHIFT)) & MBIST_BGCR_DB1_MASK) +#define MBIST_BGCR_DB2_MASK (0x4U) +#define MBIST_BGCR_DB2_SHIFT (2U) +/*! DB2 - Data Background 2 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB2(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB2_SHIFT)) & MBIST_BGCR_DB2_MASK) +#define MBIST_BGCR_DB3_MASK (0x8U) +#define MBIST_BGCR_DB3_SHIFT (3U) +/*! DB3 - Data Background 3 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB3(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB3_SHIFT)) & MBIST_BGCR_DB3_MASK) +#define MBIST_BGCR_DB4_MASK (0x10U) +#define MBIST_BGCR_DB4_SHIFT (4U) +/*! DB4 - Data Background 4 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB4(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB4_SHIFT)) & MBIST_BGCR_DB4_MASK) +#define MBIST_BGCR_DB5_MASK (0x20U) +#define MBIST_BGCR_DB5_SHIFT (5U) +/*! DB5 - Data Background 5 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB5(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB5_SHIFT)) & MBIST_BGCR_DB5_MASK) +#define MBIST_BGCR_DB6_MASK (0x40U) +#define MBIST_BGCR_DB6_SHIFT (6U) +/*! DB6 - Data Background 6 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB6(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB6_SHIFT)) & MBIST_BGCR_DB6_MASK) +#define MBIST_BGCR_DB7_MASK (0x80U) +#define MBIST_BGCR_DB7_SHIFT (7U) +/*! DB7 - Data Background 7 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB7(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB7_SHIFT)) & MBIST_BGCR_DB7_MASK) +#define MBIST_BGCR_DB8_MASK (0x100U) +#define MBIST_BGCR_DB8_SHIFT (8U) +/*! DB8 - Data Background 8 + * 0b0..This data background will not be used + * 0b1..This data background will be used + */ +#define MBIST_BGCR_DB8(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BGCR_DB8_SHIFT)) & MBIST_BGCR_DB8_MASK) +/*! @} */ + +/*! @name MSEL - Memory Selection 1 */ +/*! @{ */ +#define MBIST_MSEL_MSEL0_MASK (0x1U) +#define MBIST_MSEL_MSEL0_SHIFT (0U) +/*! MSEL0 - Memory Selection 0 + * 0b0..Ram 0 is not selected for the test. + * 0b1..Ram 0 is selected for the test. + */ +#define MBIST_MSEL_MSEL0(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL0_SHIFT)) & MBIST_MSEL_MSEL0_MASK) +#define MBIST_MSEL_MSEL1_MASK (0x2U) +#define MBIST_MSEL_MSEL1_SHIFT (1U) +/*! MSEL1 - Memory Selection 1 + * 0b0..Ram 1 is not selected for the test. + * 0b1..Ram 1 is selected for the test. + */ +#define MBIST_MSEL_MSEL1(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL1_SHIFT)) & MBIST_MSEL_MSEL1_MASK) +#define MBIST_MSEL_MSEL2_MASK (0x4U) +#define MBIST_MSEL_MSEL2_SHIFT (2U) +/*! MSEL2 - Memory Selection 2 + * 0b0..Ram 2 is not selected for the test. + * 0b1..Ram 2 is selected for the test. + */ +#define MBIST_MSEL_MSEL2(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL2_SHIFT)) & MBIST_MSEL_MSEL2_MASK) +#define MBIST_MSEL_MSEL3_MASK (0x8U) +#define MBIST_MSEL_MSEL3_SHIFT (3U) +/*! MSEL3 - Memory Selection 3 + * 0b0..Ram 3 is not selected for the test. + * 0b1..Ram 3 is selected for the test. + */ +#define MBIST_MSEL_MSEL3(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL3_SHIFT)) & MBIST_MSEL_MSEL3_MASK) +#define MBIST_MSEL_MSEL4_MASK (0x10U) +#define MBIST_MSEL_MSEL4_SHIFT (4U) +/*! MSEL4 - Memory Selection 4 + * 0b0..Ram 4 is not selected for the test. + * 0b1..Ram 4 is selected for the test. + */ +#define MBIST_MSEL_MSEL4(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL4_SHIFT)) & MBIST_MSEL_MSEL4_MASK) +#define MBIST_MSEL_MSEL5_MASK (0x20U) +#define MBIST_MSEL_MSEL5_SHIFT (5U) +/*! MSEL5 - Memory Selection 5 + * 0b0..Ram 5 is not selected for the test. + * 0b1..Ram 5 is selected for the test. + */ +#define MBIST_MSEL_MSEL5(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL5_SHIFT)) & MBIST_MSEL_MSEL5_MASK) +#define MBIST_MSEL_MSEL6_MASK (0x40U) +#define MBIST_MSEL_MSEL6_SHIFT (6U) +/*! MSEL6 - Memory Selection 6 + * 0b0..Ram 6 is not selected for the test. + * 0b1..Ram 6 is selected for the test. + */ +#define MBIST_MSEL_MSEL6(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL6_SHIFT)) & MBIST_MSEL_MSEL6_MASK) +#define MBIST_MSEL_MSEL7_MASK (0x80U) +#define MBIST_MSEL_MSEL7_SHIFT (7U) +/*! MSEL7 - Memory Selection 7 + * 0b0..Ram 7 is not selected for the test. + * 0b1..Ram 7 is selected for the test. + */ +#define MBIST_MSEL_MSEL7(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL7_SHIFT)) & MBIST_MSEL_MSEL7_MASK) +#define MBIST_MSEL_MSEL8_MASK (0x100U) +#define MBIST_MSEL_MSEL8_SHIFT (8U) +/*! MSEL8 - Memory Selection 8 + * 0b0..Ram 8 is not selected for the test. + * 0b1..Ram 8 is selected for the test. + */ +#define MBIST_MSEL_MSEL8(x) (((uint8_t)(((uint8_t)(x)) << MBIST_MSEL_MSEL8_SHIFT)) & MBIST_MSEL_MSEL8_MASK) +/*! @} */ + +/*! @name UDPR - User Defined Port Control */ +/*! @{ */ +#define MBIST_UDPR_UDPR0_MASK (0x1U) +#define MBIST_UDPR_UDPR0_SHIFT (0U) +#define MBIST_UDPR_UDPR0(x) (((uint16_t)(((uint16_t)(x)) << MBIST_UDPR_UDPR0_SHIFT)) & MBIST_UDPR_UDPR0_MASK) +#define MBIST_UDPR_UDPR1_MASK (0x2U) +#define MBIST_UDPR_UDPR1_SHIFT (1U) +#define MBIST_UDPR_UDPR1(x) (((uint16_t)(((uint16_t)(x)) << MBIST_UDPR_UDPR1_SHIFT)) & MBIST_UDPR_UDPR1_MASK) +#define MBIST_UDPR_UDPR12_MASK (0x1000U) +#define MBIST_UDPR_UDPR12_SHIFT (12U) +#define MBIST_UDPR_UDPR12(x) (((uint16_t)(((uint16_t)(x)) << MBIST_UDPR_UDPR12_SHIFT)) & MBIST_UDPR_UDPR12_MASK) +/*! @} */ + +/*! @name BSTART - BIST Start */ +/*! @{ */ +#define MBIST_BSTART_BSTART_MASK (0x3U) +#define MBIST_BSTART_BSTART_SHIFT (0U) +/*! BSTART - Start Command + * 0b00..No Operation + */ +#define MBIST_BSTART_BSTART(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTART_BSTART_SHIFT)) & MBIST_BSTART_BSTART_MASK) +#define MBIST_BSTART_DEAD_MASK (0x10U) +#define MBIST_BSTART_DEAD_SHIFT (4U) +#define MBIST_BSTART_DEAD(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTART_DEAD_SHIFT)) & MBIST_BSTART_DEAD_MASK) +#define MBIST_BSTART_LOOP_MASK (0xF00U) +#define MBIST_BSTART_LOOP_SHIFT (8U) +#define MBIST_BSTART_LOOP(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTART_LOOP_SHIFT)) & MBIST_BSTART_LOOP_MASK) +/*! @} */ + +/*! @name BRST - BIST Reset */ +/*! @{ */ +#define MBIST_BRST_BRST_MASK (0x1U) +#define MBIST_BRST_BRST_SHIFT (0U) +/*! BRST - Bist Soft Reset + * 0b1..FSLBIST3/ARMport general soft reset. + */ +#define MBIST_BRST_BRST(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BRST_BRST_SHIFT)) & MBIST_BRST_BRST_MASK) +#define MBIST_BRST_SRST_MASK (0x2U) +#define MBIST_BRST_SRST_SHIFT (1U) +/*! SRST - Bist Status Reset + * 0b1..FSLBIST3/ARMport Status reset. This resets: DSMs; BSMs; ipt_bist_status. + */ +#define MBIST_BRST_SRST(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BRST_SRST_SHIFT)) & MBIST_BRST_SRST_MASK) +/*! @} */ + +/*! @name SKIP - Programmable Skip Counter */ +/*! @{ */ +#define MBIST_SKIP_SCOUNTER_MASK (0xFFFFU) +#define MBIST_SKIP_SCOUNTER_SHIFT (0U) +#define MBIST_SKIP_SCOUNTER(x) (((uint16_t)(((uint16_t)(x)) << MBIST_SKIP_SCOUNTER_SHIFT)) & MBIST_SKIP_SCOUNTER_MASK) +/*! @} */ + +/*! @name BSTAT - BIST Status */ +/*! @{ */ +#define MBIST_BSTAT_BSTAT_1_0_MASK (0x3U) +#define MBIST_BSTAT_BSTAT_1_0_SHIFT (0U) +/*! BSTAT_1_0 - Bist Status 1 .. 0 + * 0b00..Bist has never ran (after reset state). + * 0b01..Bist is busy running a test. + * 0b10..Finished test with no unrepairable fails. + * 0b11..Finished test with unrepairable fails. + */ +#define MBIST_BSTAT_BSTAT_1_0(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTAT_BSTAT_1_0_SHIFT)) & MBIST_BSTAT_BSTAT_1_0_MASK) +#define MBIST_BSTAT_BSTAT_2_MASK (0x4U) +#define MBIST_BSTAT_BSTAT_2_SHIFT (2U) +/*! BSTAT_2 - Bist Status 2 + * 0b0..No error has been detected. + * 0b1..At least one error has been detected. + */ +#define MBIST_BSTAT_BSTAT_2(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTAT_BSTAT_2_SHIFT)) & MBIST_BSTAT_BSTAT_2_MASK) +#define MBIST_BSTAT_BSTAT_3_MASK (0x8U) +#define MBIST_BSTAT_BSTAT_3_SHIFT (3U) +/*! BSTAT_3 - Bist Status 3 + * 0b0..Bist is not on SOF or it is running. + * 0b1..Bist has stopped. + */ +#define MBIST_BSTAT_BSTAT_3(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTAT_BSTAT_3_SHIFT)) & MBIST_BSTAT_BSTAT_3_MASK) +#define MBIST_BSTAT_HOLD_ERR_MASK (0x20U) +#define MBIST_BSTAT_HOLD_ERR_SHIFT (5U) +/*! HOLD_ERR - Read Hold Error + * 0b0..No data stability error was found. + * 0b1..At least one data stability error was found. + */ +#define MBIST_BSTAT_HOLD_ERR(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BSTAT_HOLD_ERR_SHIFT)) & MBIST_BSTAT_HOLD_ERR_MASK) +/*! @} */ + +/*! @name FPM - BIST Fail Per Memory 1 */ +/*! @{ */ +#define MBIST_FPM_FPM0_MASK (0x1U) +#define MBIST_FPM_FPM0_SHIFT (0U) +/*! FPM0 - Fail on Memory 0 + * 0b0..Memory 0 passed the test. + * 0b1..Memory 0 failed the test. + */ +#define MBIST_FPM_FPM0(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM0_SHIFT)) & MBIST_FPM_FPM0_MASK) +#define MBIST_FPM_FPM1_MASK (0x2U) +#define MBIST_FPM_FPM1_SHIFT (1U) +/*! FPM1 - Fail on Memory 1 + * 0b0..Memory 1 passed the test. + * 0b1..Memory 1 failed the test. + */ +#define MBIST_FPM_FPM1(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM1_SHIFT)) & MBIST_FPM_FPM1_MASK) +#define MBIST_FPM_FPM2_MASK (0x4U) +#define MBIST_FPM_FPM2_SHIFT (2U) +/*! FPM2 - Fail on Memory 2 + * 0b0..Memory 2 passed the test. + * 0b1..Memory 2 failed the test. + */ +#define MBIST_FPM_FPM2(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM2_SHIFT)) & MBIST_FPM_FPM2_MASK) +#define MBIST_FPM_FPM3_MASK (0x8U) +#define MBIST_FPM_FPM3_SHIFT (3U) +/*! FPM3 - Fail on Memory 3 + * 0b0..Memory 3 passed the test. + * 0b1..Memory 3 failed the test. + */ +#define MBIST_FPM_FPM3(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM3_SHIFT)) & MBIST_FPM_FPM3_MASK) +#define MBIST_FPM_FPM4_MASK (0x10U) +#define MBIST_FPM_FPM4_SHIFT (4U) +/*! FPM4 - Fail on Memory 4 + * 0b0..Memory 4 passed the test. + * 0b1..Memory 4 failed the test. + */ +#define MBIST_FPM_FPM4(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM4_SHIFT)) & MBIST_FPM_FPM4_MASK) +#define MBIST_FPM_FPM5_MASK (0x20U) +#define MBIST_FPM_FPM5_SHIFT (5U) +/*! FPM5 - Fail on Memory 5 + * 0b0..Memory 5 passed the test. + * 0b1..Memory 5 failed the test. + */ +#define MBIST_FPM_FPM5(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM5_SHIFT)) & MBIST_FPM_FPM5_MASK) +#define MBIST_FPM_FPM6_MASK (0x40U) +#define MBIST_FPM_FPM6_SHIFT (6U) +/*! FPM6 - Fail on Memory 6 + * 0b0..Memory 6 passed the test. + * 0b1..Memory 6 failed the test. + */ +#define MBIST_FPM_FPM6(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM6_SHIFT)) & MBIST_FPM_FPM6_MASK) +#define MBIST_FPM_FPM7_MASK (0x80U) +#define MBIST_FPM_FPM7_SHIFT (7U) +/*! FPM7 - Fail on Memory 7 + * 0b0..Memory 7 passed the test. + * 0b1..Memory 7 failed the test. + */ +#define MBIST_FPM_FPM7(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM7_SHIFT)) & MBIST_FPM_FPM7_MASK) +#define MBIST_FPM_FPM8_MASK (0x100U) +#define MBIST_FPM_FPM8_SHIFT (8U) +/*! FPM8 - Fail on Memory 8 + * 0b0..Memory 8 passed the test. + * 0b1..Memory 8 failed the test. + */ +#define MBIST_FPM_FPM8(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FPM_FPM8_SHIFT)) & MBIST_FPM_FPM8_MASK) +/*! @} */ + +/*! @name BFPM - BIRA Fail Per Memory 1 */ +/*! @{ */ +#define MBIST_BFPM_BIRA_FAIL0_MASK (0x1U) +#define MBIST_BFPM_BIRA_FAIL0_SHIFT (0U) +/*! BIRA_FAIL0 - Bira Fail on Memory 0 + * 0b0..Memory 0 passed the test. + * 0b1..Memory 0 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL0(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL0_SHIFT)) & MBIST_BFPM_BIRA_FAIL0_MASK) +#define MBIST_BFPM_BIRA_FAIL1_MASK (0x2U) +#define MBIST_BFPM_BIRA_FAIL1_SHIFT (1U) +/*! BIRA_FAIL1 - Bira Fail on Memory 1 + * 0b0..Memory 1 passed the test. + * 0b1..Memory 1 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL1(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL1_SHIFT)) & MBIST_BFPM_BIRA_FAIL1_MASK) +#define MBIST_BFPM_BIRA_FAIL2_MASK (0x4U) +#define MBIST_BFPM_BIRA_FAIL2_SHIFT (2U) +/*! BIRA_FAIL2 - Bira Fail on Memory 2 + * 0b0..Memory 2 passed the test. + * 0b1..Memory 2 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL2(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL2_SHIFT)) & MBIST_BFPM_BIRA_FAIL2_MASK) +#define MBIST_BFPM_BIRA_FAIL3_MASK (0x8U) +#define MBIST_BFPM_BIRA_FAIL3_SHIFT (3U) +/*! BIRA_FAIL3 - Bira Fail on Memory 3 + * 0b0..Memory 3 passed the test. + * 0b1..Memory 3 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL3(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL3_SHIFT)) & MBIST_BFPM_BIRA_FAIL3_MASK) +#define MBIST_BFPM_BIRA_FAIL4_MASK (0x10U) +#define MBIST_BFPM_BIRA_FAIL4_SHIFT (4U) +/*! BIRA_FAIL4 - Bira Fail on Memory 4 + * 0b0..Memory 4 passed the test. + * 0b1..Memory 4 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL4(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL4_SHIFT)) & MBIST_BFPM_BIRA_FAIL4_MASK) +#define MBIST_BFPM_BIRA_FAIL5_MASK (0x20U) +#define MBIST_BFPM_BIRA_FAIL5_SHIFT (5U) +/*! BIRA_FAIL5 - Bira Fail on Memory 5 + * 0b0..Memory 5 passed the test. + * 0b1..Memory 5 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL5(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL5_SHIFT)) & MBIST_BFPM_BIRA_FAIL5_MASK) +#define MBIST_BFPM_BIRA_FAIL6_MASK (0x40U) +#define MBIST_BFPM_BIRA_FAIL6_SHIFT (6U) +/*! BIRA_FAIL6 - Bira Fail on Memory 6 + * 0b0..Memory 6 passed the test. + * 0b1..Memory 6 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL6(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL6_SHIFT)) & MBIST_BFPM_BIRA_FAIL6_MASK) +#define MBIST_BFPM_BIRA_FAIL7_MASK (0x80U) +#define MBIST_BFPM_BIRA_FAIL7_SHIFT (7U) +/*! BIRA_FAIL7 - Bira Fail on Memory 7 + * 0b0..Memory 7 passed the test. + * 0b1..Memory 7 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL7(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL7_SHIFT)) & MBIST_BFPM_BIRA_FAIL7_MASK) +#define MBIST_BFPM_BIRA_FAIL8_MASK (0x100U) +#define MBIST_BFPM_BIRA_FAIL8_SHIFT (8U) +/*! BIRA_FAIL8 - Bira Fail on Memory 8 + * 0b0..Memory 8 passed the test. + * 0b1..Memory 8 failed the test. + */ +#define MBIST_BFPM_BIRA_FAIL8(x) (((uint8_t)(((uint8_t)(x)) << MBIST_BFPM_BIRA_FAIL8_SHIFT)) & MBIST_BFPM_BIRA_FAIL8_MASK) +/*! @} */ + +/*! @name FSDR - FSM State Debug Register */ +/*! @{ */ +#define MBIST_FSDR_OP_MASK (0x3U) +#define MBIST_FSDR_OP_SHIFT (0U) +/*! OP - Operation + * 0b00..R0 + * 0b01..R1 + * 0b10..W0 + * 0b11..W1 + */ +#define MBIST_FSDR_OP(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FSDR_OP_SHIFT)) & MBIST_FSDR_OP_MASK) +#define MBIST_FSDR_MP_MASK (0x1CU) +#define MBIST_FSDR_MP_SHIFT (2U) +/*! MP - March Phase + * 0b000..MP0 + * 0b001..MP1 + * 0b010..MP2 + * 0b011..MP3 + * 0b100..MP4 + * 0b101..MP5 + */ +#define MBIST_FSDR_MP(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FSDR_MP_SHIFT)) & MBIST_FSDR_MP_MASK) +#define MBIST_FSDR_ME_MASK (0xE0U) +#define MBIST_FSDR_ME_SHIFT (5U) +/*! ME - March Element + * 0b000..ME0 + * 0b001..ME1 + * 0b010..ME2 + * 0b011..ME3 + * 0b100..ME4 + * 0b101..ME5 + * 0b110..ME6 + * 0b111..ME7 + */ +#define MBIST_FSDR_ME(x) (((uint8_t)(((uint8_t)(x)) << MBIST_FSDR_ME_SHIFT)) & MBIST_FSDR_ME_MASK) +/*! @} */ + +/*! @name ADR - Address Debug Register */ +/*! @{ */ +#define MBIST_ADR_ADDR_MASK (0x7FFU) +#define MBIST_ADR_ADDR_SHIFT (0U) +#define MBIST_ADR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << MBIST_ADR_ADDR_SHIFT)) & MBIST_ADR_ADDR_MASK) +/*! @} */ + +/*! @name DBG0 - Data Debug Register - Word 0 */ +/*! @{ */ +#define MBIST_DBG0_CDATA_0_MASK (0x1U) +#define MBIST_DBG0_CDATA_0_SHIFT (0U) +/*! CDATA_0 - Data Debug Register - Bit 0 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_0(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_0_SHIFT)) & MBIST_DBG0_CDATA_0_MASK) +#define MBIST_DBG0_CDATA_1_MASK (0x2U) +#define MBIST_DBG0_CDATA_1_SHIFT (1U) +/*! CDATA_1 - Data Debug Register - Bit 1 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_1(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_1_SHIFT)) & MBIST_DBG0_CDATA_1_MASK) +#define MBIST_DBG0_CDATA_2_MASK (0x4U) +#define MBIST_DBG0_CDATA_2_SHIFT (2U) +/*! CDATA_2 - Data Debug Register - Bit 2 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_2(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_2_SHIFT)) & MBIST_DBG0_CDATA_2_MASK) +#define MBIST_DBG0_CDATA_3_MASK (0x8U) +#define MBIST_DBG0_CDATA_3_SHIFT (3U) +/*! CDATA_3 - Data Debug Register - Bit 3 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_3(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_3_SHIFT)) & MBIST_DBG0_CDATA_3_MASK) +#define MBIST_DBG0_CDATA_4_MASK (0x10U) +#define MBIST_DBG0_CDATA_4_SHIFT (4U) +/*! CDATA_4 - Data Debug Register - Bit 4 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_4(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_4_SHIFT)) & MBIST_DBG0_CDATA_4_MASK) +#define MBIST_DBG0_CDATA_5_MASK (0x20U) +#define MBIST_DBG0_CDATA_5_SHIFT (5U) +/*! CDATA_5 - Data Debug Register - Bit 5 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_5(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_5_SHIFT)) & MBIST_DBG0_CDATA_5_MASK) +#define MBIST_DBG0_CDATA_6_MASK (0x40U) +#define MBIST_DBG0_CDATA_6_SHIFT (6U) +/*! CDATA_6 - Data Debug Register - Bit 6 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_6(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_6_SHIFT)) & MBIST_DBG0_CDATA_6_MASK) +#define MBIST_DBG0_CDATA_7_MASK (0x80U) +#define MBIST_DBG0_CDATA_7_SHIFT (7U) +/*! CDATA_7 - Data Debug Register - Bit 7 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_7(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_7_SHIFT)) & MBIST_DBG0_CDATA_7_MASK) +#define MBIST_DBG0_CDATA_8_MASK (0x100U) +#define MBIST_DBG0_CDATA_8_SHIFT (8U) +/*! CDATA_8 - Data Debug Register - Bit 8 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_8(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_8_SHIFT)) & MBIST_DBG0_CDATA_8_MASK) +#define MBIST_DBG0_CDATA_9_MASK (0x200U) +#define MBIST_DBG0_CDATA_9_SHIFT (9U) +/*! CDATA_9 - Data Debug Register - Bit 9 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_9(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_9_SHIFT)) & MBIST_DBG0_CDATA_9_MASK) +#define MBIST_DBG0_CDATA_10_MASK (0x400U) +#define MBIST_DBG0_CDATA_10_SHIFT (10U) +/*! CDATA_10 - Data Debug Register - Bit 10 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_10(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_10_SHIFT)) & MBIST_DBG0_CDATA_10_MASK) +#define MBIST_DBG0_CDATA_11_MASK (0x800U) +#define MBIST_DBG0_CDATA_11_SHIFT (11U) +/*! CDATA_11 - Data Debug Register - Bit 11 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_11(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_11_SHIFT)) & MBIST_DBG0_CDATA_11_MASK) +#define MBIST_DBG0_CDATA_12_MASK (0x1000U) +#define MBIST_DBG0_CDATA_12_SHIFT (12U) +/*! CDATA_12 - Data Debug Register - Bit 12 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_12(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_12_SHIFT)) & MBIST_DBG0_CDATA_12_MASK) +#define MBIST_DBG0_CDATA_13_MASK (0x2000U) +#define MBIST_DBG0_CDATA_13_SHIFT (13U) +/*! CDATA_13 - Data Debug Register - Bit 13 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_13(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_13_SHIFT)) & MBIST_DBG0_CDATA_13_MASK) +#define MBIST_DBG0_CDATA_14_MASK (0x4000U) +#define MBIST_DBG0_CDATA_14_SHIFT (14U) +/*! CDATA_14 - Data Debug Register - Bit 14 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_14(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_14_SHIFT)) & MBIST_DBG0_CDATA_14_MASK) +#define MBIST_DBG0_CDATA_15_MASK (0x8000U) +#define MBIST_DBG0_CDATA_15_SHIFT (15U) +/*! CDATA_15 - Data Debug Register - Bit 15 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_15(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_15_SHIFT)) & MBIST_DBG0_CDATA_15_MASK) +#define MBIST_DBG0_CDATA_16_MASK (0x10000U) +#define MBIST_DBG0_CDATA_16_SHIFT (16U) +/*! CDATA_16 - Data Debug Register - Bit 16 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_16(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_16_SHIFT)) & MBIST_DBG0_CDATA_16_MASK) +#define MBIST_DBG0_CDATA_17_MASK (0x20000U) +#define MBIST_DBG0_CDATA_17_SHIFT (17U) +/*! CDATA_17 - Data Debug Register - Bit 17 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_17(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_17_SHIFT)) & MBIST_DBG0_CDATA_17_MASK) +#define MBIST_DBG0_CDATA_18_MASK (0x40000U) +#define MBIST_DBG0_CDATA_18_SHIFT (18U) +/*! CDATA_18 - Data Debug Register - Bit 18 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_18(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_18_SHIFT)) & MBIST_DBG0_CDATA_18_MASK) +#define MBIST_DBG0_CDATA_19_MASK (0x80000U) +#define MBIST_DBG0_CDATA_19_SHIFT (19U) +/*! CDATA_19 - Data Debug Register - Bit 19 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_19(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_19_SHIFT)) & MBIST_DBG0_CDATA_19_MASK) +#define MBIST_DBG0_CDATA_20_MASK (0x100000U) +#define MBIST_DBG0_CDATA_20_SHIFT (20U) +/*! CDATA_20 - Data Debug Register - Bit 20 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_20(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_20_SHIFT)) & MBIST_DBG0_CDATA_20_MASK) +#define MBIST_DBG0_CDATA_21_MASK (0x200000U) +#define MBIST_DBG0_CDATA_21_SHIFT (21U) +/*! CDATA_21 - Data Debug Register - Bit 21 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_21(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_21_SHIFT)) & MBIST_DBG0_CDATA_21_MASK) +#define MBIST_DBG0_CDATA_22_MASK (0x400000U) +#define MBIST_DBG0_CDATA_22_SHIFT (22U) +/*! CDATA_22 - Data Debug Register - Bit 22 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_22(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_22_SHIFT)) & MBIST_DBG0_CDATA_22_MASK) +#define MBIST_DBG0_CDATA_23_MASK (0x800000U) +#define MBIST_DBG0_CDATA_23_SHIFT (23U) +/*! CDATA_23 - Data Debug Register - Bit 23 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_23(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_23_SHIFT)) & MBIST_DBG0_CDATA_23_MASK) +#define MBIST_DBG0_CDATA_24_MASK (0x1000000U) +#define MBIST_DBG0_CDATA_24_SHIFT (24U) +/*! CDATA_24 - Data Debug Register - Bit 24 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_24(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_24_SHIFT)) & MBIST_DBG0_CDATA_24_MASK) +#define MBIST_DBG0_CDATA_25_MASK (0x2000000U) +#define MBIST_DBG0_CDATA_25_SHIFT (25U) +/*! CDATA_25 - Data Debug Register - Bit 25 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_25(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_25_SHIFT)) & MBIST_DBG0_CDATA_25_MASK) +#define MBIST_DBG0_CDATA_26_MASK (0x4000000U) +#define MBIST_DBG0_CDATA_26_SHIFT (26U) +/*! CDATA_26 - Data Debug Register - Bit 26 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_26(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_26_SHIFT)) & MBIST_DBG0_CDATA_26_MASK) +#define MBIST_DBG0_CDATA_27_MASK (0x8000000U) +#define MBIST_DBG0_CDATA_27_SHIFT (27U) +/*! CDATA_27 - Data Debug Register - Bit 27 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_27(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_27_SHIFT)) & MBIST_DBG0_CDATA_27_MASK) +#define MBIST_DBG0_CDATA_28_MASK (0x10000000U) +#define MBIST_DBG0_CDATA_28_SHIFT (28U) +/*! CDATA_28 - Data Debug Register - Bit 28 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_28(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_28_SHIFT)) & MBIST_DBG0_CDATA_28_MASK) +#define MBIST_DBG0_CDATA_29_MASK (0x20000000U) +#define MBIST_DBG0_CDATA_29_SHIFT (29U) +/*! CDATA_29 - Data Debug Register - Bit 29 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_29(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_29_SHIFT)) & MBIST_DBG0_CDATA_29_MASK) +#define MBIST_DBG0_CDATA_30_MASK (0x40000000U) +#define MBIST_DBG0_CDATA_30_SHIFT (30U) +/*! CDATA_30 - Data Debug Register - Bit 30 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_30(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_30_SHIFT)) & MBIST_DBG0_CDATA_30_MASK) +#define MBIST_DBG0_CDATA_31_MASK (0x80000000U) +#define MBIST_DBG0_CDATA_31_SHIFT (31U) +/*! CDATA_31 - Data Debug Register - Bit 31 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG0_CDATA_31(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG0_CDATA_31_SHIFT)) & MBIST_DBG0_CDATA_31_MASK) +/*! @} */ + +/*! @name DBG1 - Data Debug Register - Word 1 */ +/*! @{ */ +#define MBIST_DBG1_CDATA_32_MASK (0x1U) +#define MBIST_DBG1_CDATA_32_SHIFT (0U) +/*! CDATA_32 - Data Debug Register - Bit 32 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_32(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_32_SHIFT)) & MBIST_DBG1_CDATA_32_MASK) +#define MBIST_DBG1_CDATA_33_MASK (0x2U) +#define MBIST_DBG1_CDATA_33_SHIFT (1U) +/*! CDATA_33 - Data Debug Register - Bit 33 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_33(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_33_SHIFT)) & MBIST_DBG1_CDATA_33_MASK) +#define MBIST_DBG1_CDATA_34_MASK (0x4U) +#define MBIST_DBG1_CDATA_34_SHIFT (2U) +/*! CDATA_34 - Data Debug Register - Bit 34 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_34(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_34_SHIFT)) & MBIST_DBG1_CDATA_34_MASK) +#define MBIST_DBG1_CDATA_35_MASK (0x8U) +#define MBIST_DBG1_CDATA_35_SHIFT (3U) +/*! CDATA_35 - Data Debug Register - Bit 35 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_35(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_35_SHIFT)) & MBIST_DBG1_CDATA_35_MASK) +#define MBIST_DBG1_CDATA_36_MASK (0x10U) +#define MBIST_DBG1_CDATA_36_SHIFT (4U) +/*! CDATA_36 - Data Debug Register - Bit 36 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_36(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_36_SHIFT)) & MBIST_DBG1_CDATA_36_MASK) +#define MBIST_DBG1_CDATA_37_MASK (0x20U) +#define MBIST_DBG1_CDATA_37_SHIFT (5U) +/*! CDATA_37 - Data Debug Register - Bit 37 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_37(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_37_SHIFT)) & MBIST_DBG1_CDATA_37_MASK) +#define MBIST_DBG1_CDATA_38_MASK (0x40U) +#define MBIST_DBG1_CDATA_38_SHIFT (6U) +/*! CDATA_38 - Data Debug Register - Bit 38 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_38(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_38_SHIFT)) & MBIST_DBG1_CDATA_38_MASK) +#define MBIST_DBG1_CDATA_39_MASK (0x80U) +#define MBIST_DBG1_CDATA_39_SHIFT (7U) +/*! CDATA_39 - Data Debug Register - Bit 39 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_39(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_39_SHIFT)) & MBIST_DBG1_CDATA_39_MASK) +#define MBIST_DBG1_CDATA_40_MASK (0x100U) +#define MBIST_DBG1_CDATA_40_SHIFT (8U) +/*! CDATA_40 - Data Debug Register - Bit 40 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_40(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_40_SHIFT)) & MBIST_DBG1_CDATA_40_MASK) +#define MBIST_DBG1_CDATA_41_MASK (0x200U) +#define MBIST_DBG1_CDATA_41_SHIFT (9U) +/*! CDATA_41 - Data Debug Register - Bit 41 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_41(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_41_SHIFT)) & MBIST_DBG1_CDATA_41_MASK) +#define MBIST_DBG1_CDATA_42_MASK (0x400U) +#define MBIST_DBG1_CDATA_42_SHIFT (10U) +/*! CDATA_42 - Data Debug Register - Bit 42 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_42(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_42_SHIFT)) & MBIST_DBG1_CDATA_42_MASK) +#define MBIST_DBG1_CDATA_43_MASK (0x800U) +#define MBIST_DBG1_CDATA_43_SHIFT (11U) +/*! CDATA_43 - Data Debug Register - Bit 43 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_43(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_43_SHIFT)) & MBIST_DBG1_CDATA_43_MASK) +#define MBIST_DBG1_CDATA_44_MASK (0x1000U) +#define MBIST_DBG1_CDATA_44_SHIFT (12U) +/*! CDATA_44 - Data Debug Register - Bit 44 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_44(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_44_SHIFT)) & MBIST_DBG1_CDATA_44_MASK) +#define MBIST_DBG1_CDATA_45_MASK (0x2000U) +#define MBIST_DBG1_CDATA_45_SHIFT (13U) +/*! CDATA_45 - Data Debug Register - Bit 45 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_45(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_45_SHIFT)) & MBIST_DBG1_CDATA_45_MASK) +#define MBIST_DBG1_CDATA_46_MASK (0x4000U) +#define MBIST_DBG1_CDATA_46_SHIFT (14U) +/*! CDATA_46 - Data Debug Register - Bit 46 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_46(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_46_SHIFT)) & MBIST_DBG1_CDATA_46_MASK) +#define MBIST_DBG1_CDATA_47_MASK (0x8000U) +#define MBIST_DBG1_CDATA_47_SHIFT (15U) +/*! CDATA_47 - Data Debug Register - Bit 47 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_47(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_47_SHIFT)) & MBIST_DBG1_CDATA_47_MASK) +#define MBIST_DBG1_CDATA_48_MASK (0x10000U) +#define MBIST_DBG1_CDATA_48_SHIFT (16U) +/*! CDATA_48 - Data Debug Register - Bit 48 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_48(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_48_SHIFT)) & MBIST_DBG1_CDATA_48_MASK) +#define MBIST_DBG1_CDATA_49_MASK (0x20000U) +#define MBIST_DBG1_CDATA_49_SHIFT (17U) +/*! CDATA_49 - Data Debug Register - Bit 49 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_49(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_49_SHIFT)) & MBIST_DBG1_CDATA_49_MASK) +#define MBIST_DBG1_CDATA_50_MASK (0x40000U) +#define MBIST_DBG1_CDATA_50_SHIFT (18U) +/*! CDATA_50 - Data Debug Register - Bit 50 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_50(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_50_SHIFT)) & MBIST_DBG1_CDATA_50_MASK) +#define MBIST_DBG1_CDATA_51_MASK (0x80000U) +#define MBIST_DBG1_CDATA_51_SHIFT (19U) +/*! CDATA_51 - Data Debug Register - Bit 51 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_51(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_51_SHIFT)) & MBIST_DBG1_CDATA_51_MASK) +#define MBIST_DBG1_CDATA_52_MASK (0x100000U) +#define MBIST_DBG1_CDATA_52_SHIFT (20U) +/*! CDATA_52 - Data Debug Register - Bit 52 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_52(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_52_SHIFT)) & MBIST_DBG1_CDATA_52_MASK) +#define MBIST_DBG1_CDATA_53_MASK (0x200000U) +#define MBIST_DBG1_CDATA_53_SHIFT (21U) +/*! CDATA_53 - Data Debug Register - Bit 53 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_53(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_53_SHIFT)) & MBIST_DBG1_CDATA_53_MASK) +#define MBIST_DBG1_CDATA_54_MASK (0x400000U) +#define MBIST_DBG1_CDATA_54_SHIFT (22U) +/*! CDATA_54 - Data Debug Register - Bit 54 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_54(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_54_SHIFT)) & MBIST_DBG1_CDATA_54_MASK) +#define MBIST_DBG1_CDATA_55_MASK (0x800000U) +#define MBIST_DBG1_CDATA_55_SHIFT (23U) +/*! CDATA_55 - Data Debug Register - Bit 55 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_55(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_55_SHIFT)) & MBIST_DBG1_CDATA_55_MASK) +#define MBIST_DBG1_CDATA_56_MASK (0x1000000U) +#define MBIST_DBG1_CDATA_56_SHIFT (24U) +/*! CDATA_56 - Data Debug Register - Bit 56 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_56(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_56_SHIFT)) & MBIST_DBG1_CDATA_56_MASK) +#define MBIST_DBG1_CDATA_57_MASK (0x2000000U) +#define MBIST_DBG1_CDATA_57_SHIFT (25U) +/*! CDATA_57 - Data Debug Register - Bit 57 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_57(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_57_SHIFT)) & MBIST_DBG1_CDATA_57_MASK) +#define MBIST_DBG1_CDATA_58_MASK (0x4000000U) +#define MBIST_DBG1_CDATA_58_SHIFT (26U) +/*! CDATA_58 - Data Debug Register - Bit 58 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_58(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_58_SHIFT)) & MBIST_DBG1_CDATA_58_MASK) +#define MBIST_DBG1_CDATA_59_MASK (0x8000000U) +#define MBIST_DBG1_CDATA_59_SHIFT (27U) +/*! CDATA_59 - Data Debug Register - Bit 59 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_59(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_59_SHIFT)) & MBIST_DBG1_CDATA_59_MASK) +#define MBIST_DBG1_CDATA_60_MASK (0x10000000U) +#define MBIST_DBG1_CDATA_60_SHIFT (28U) +/*! CDATA_60 - Data Debug Register - Bit 60 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_60(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_60_SHIFT)) & MBIST_DBG1_CDATA_60_MASK) +#define MBIST_DBG1_CDATA_61_MASK (0x20000000U) +#define MBIST_DBG1_CDATA_61_SHIFT (29U) +/*! CDATA_61 - Data Debug Register - Bit 61 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_61(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_61_SHIFT)) & MBIST_DBG1_CDATA_61_MASK) +#define MBIST_DBG1_CDATA_62_MASK (0x40000000U) +#define MBIST_DBG1_CDATA_62_SHIFT (30U) +/*! CDATA_62 - Data Debug Register - Bit 62 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_62(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_62_SHIFT)) & MBIST_DBG1_CDATA_62_MASK) +#define MBIST_DBG1_CDATA_63_MASK (0x80000000U) +#define MBIST_DBG1_CDATA_63_SHIFT (31U) +/*! CDATA_63 - Data Debug Register - Bit 63 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG1_CDATA_63(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG1_CDATA_63_SHIFT)) & MBIST_DBG1_CDATA_63_MASK) +/*! @} */ + +/*! @name DBG2 - Data Debug Register - Word 2 */ +/*! @{ */ +#define MBIST_DBG2_CDATA_64_MASK (0x1U) +#define MBIST_DBG2_CDATA_64_SHIFT (0U) +/*! CDATA_64 - Data Debug Register - Bit 64 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_64(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_64_SHIFT)) & MBIST_DBG2_CDATA_64_MASK) +#define MBIST_DBG2_CDATA_65_MASK (0x2U) +#define MBIST_DBG2_CDATA_65_SHIFT (1U) +/*! CDATA_65 - Data Debug Register - Bit 65 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_65(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_65_SHIFT)) & MBIST_DBG2_CDATA_65_MASK) +#define MBIST_DBG2_CDATA_66_MASK (0x4U) +#define MBIST_DBG2_CDATA_66_SHIFT (2U) +/*! CDATA_66 - Data Debug Register - Bit 66 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_66(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_66_SHIFT)) & MBIST_DBG2_CDATA_66_MASK) +#define MBIST_DBG2_CDATA_67_MASK (0x8U) +#define MBIST_DBG2_CDATA_67_SHIFT (3U) +/*! CDATA_67 - Data Debug Register - Bit 67 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_67(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_67_SHIFT)) & MBIST_DBG2_CDATA_67_MASK) +#define MBIST_DBG2_CDATA_68_MASK (0x10U) +#define MBIST_DBG2_CDATA_68_SHIFT (4U) +/*! CDATA_68 - Data Debug Register - Bit 68 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_68(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_68_SHIFT)) & MBIST_DBG2_CDATA_68_MASK) +#define MBIST_DBG2_CDATA_69_MASK (0x20U) +#define MBIST_DBG2_CDATA_69_SHIFT (5U) +/*! CDATA_69 - Data Debug Register - Bit 69 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_69(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_69_SHIFT)) & MBIST_DBG2_CDATA_69_MASK) +#define MBIST_DBG2_CDATA_70_MASK (0x40U) +#define MBIST_DBG2_CDATA_70_SHIFT (6U) +/*! CDATA_70 - Data Debug Register - Bit 70 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_70(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_70_SHIFT)) & MBIST_DBG2_CDATA_70_MASK) +#define MBIST_DBG2_CDATA_71_MASK (0x80U) +#define MBIST_DBG2_CDATA_71_SHIFT (7U) +/*! CDATA_71 - Data Debug Register - Bit 71 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_71(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_71_SHIFT)) & MBIST_DBG2_CDATA_71_MASK) +#define MBIST_DBG2_CDATA_72_MASK (0x100U) +#define MBIST_DBG2_CDATA_72_SHIFT (8U) +/*! CDATA_72 - Data Debug Register - Bit 72 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_72(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_72_SHIFT)) & MBIST_DBG2_CDATA_72_MASK) +#define MBIST_DBG2_CDATA_73_MASK (0x200U) +#define MBIST_DBG2_CDATA_73_SHIFT (9U) +/*! CDATA_73 - Data Debug Register - Bit 73 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_73(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_73_SHIFT)) & MBIST_DBG2_CDATA_73_MASK) +#define MBIST_DBG2_CDATA_74_MASK (0x400U) +#define MBIST_DBG2_CDATA_74_SHIFT (10U) +/*! CDATA_74 - Data Debug Register - Bit 74 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_74(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_74_SHIFT)) & MBIST_DBG2_CDATA_74_MASK) +#define MBIST_DBG2_CDATA_75_MASK (0x800U) +#define MBIST_DBG2_CDATA_75_SHIFT (11U) +/*! CDATA_75 - Data Debug Register - Bit 75 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_75(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_75_SHIFT)) & MBIST_DBG2_CDATA_75_MASK) +#define MBIST_DBG2_CDATA_76_MASK (0x1000U) +#define MBIST_DBG2_CDATA_76_SHIFT (12U) +/*! CDATA_76 - Data Debug Register - Bit 76 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_76(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_76_SHIFT)) & MBIST_DBG2_CDATA_76_MASK) +#define MBIST_DBG2_CDATA_77_MASK (0x2000U) +#define MBIST_DBG2_CDATA_77_SHIFT (13U) +/*! CDATA_77 - Data Debug Register - Bit 77 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_77(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_77_SHIFT)) & MBIST_DBG2_CDATA_77_MASK) +#define MBIST_DBG2_CDATA_78_MASK (0x4000U) +#define MBIST_DBG2_CDATA_78_SHIFT (14U) +/*! CDATA_78 - Data Debug Register - Bit 78 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_78(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_78_SHIFT)) & MBIST_DBG2_CDATA_78_MASK) +#define MBIST_DBG2_CDATA_79_MASK (0x8000U) +#define MBIST_DBG2_CDATA_79_SHIFT (15U) +/*! CDATA_79 - Data Debug Register - Bit 79 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_79(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_79_SHIFT)) & MBIST_DBG2_CDATA_79_MASK) +#define MBIST_DBG2_CDATA_80_MASK (0x10000U) +#define MBIST_DBG2_CDATA_80_SHIFT (16U) +/*! CDATA_80 - Data Debug Register - Bit 80 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_80(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_80_SHIFT)) & MBIST_DBG2_CDATA_80_MASK) +#define MBIST_DBG2_CDATA_81_MASK (0x20000U) +#define MBIST_DBG2_CDATA_81_SHIFT (17U) +/*! CDATA_81 - Data Debug Register - Bit 81 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_81(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_81_SHIFT)) & MBIST_DBG2_CDATA_81_MASK) +#define MBIST_DBG2_CDATA_82_MASK (0x40000U) +#define MBIST_DBG2_CDATA_82_SHIFT (18U) +/*! CDATA_82 - Data Debug Register - Bit 82 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_82(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_82_SHIFT)) & MBIST_DBG2_CDATA_82_MASK) +#define MBIST_DBG2_CDATA_83_MASK (0x80000U) +#define MBIST_DBG2_CDATA_83_SHIFT (19U) +/*! CDATA_83 - Data Debug Register - Bit 83 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_83(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_83_SHIFT)) & MBIST_DBG2_CDATA_83_MASK) +#define MBIST_DBG2_CDATA_84_MASK (0x100000U) +#define MBIST_DBG2_CDATA_84_SHIFT (20U) +/*! CDATA_84 - Data Debug Register - Bit 84 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_84(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_84_SHIFT)) & MBIST_DBG2_CDATA_84_MASK) +#define MBIST_DBG2_CDATA_85_MASK (0x200000U) +#define MBIST_DBG2_CDATA_85_SHIFT (21U) +/*! CDATA_85 - Data Debug Register - Bit 85 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_85(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_85_SHIFT)) & MBIST_DBG2_CDATA_85_MASK) +#define MBIST_DBG2_CDATA_86_MASK (0x400000U) +#define MBIST_DBG2_CDATA_86_SHIFT (22U) +/*! CDATA_86 - Data Debug Register - Bit 86 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_86(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_86_SHIFT)) & MBIST_DBG2_CDATA_86_MASK) +#define MBIST_DBG2_CDATA_87_MASK (0x800000U) +#define MBIST_DBG2_CDATA_87_SHIFT (23U) +/*! CDATA_87 - Data Debug Register - Bit 87 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_87(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_87_SHIFT)) & MBIST_DBG2_CDATA_87_MASK) +#define MBIST_DBG2_CDATA_88_MASK (0x1000000U) +#define MBIST_DBG2_CDATA_88_SHIFT (24U) +/*! CDATA_88 - Data Debug Register - Bit 88 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_88(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_88_SHIFT)) & MBIST_DBG2_CDATA_88_MASK) +#define MBIST_DBG2_CDATA_89_MASK (0x2000000U) +#define MBIST_DBG2_CDATA_89_SHIFT (25U) +/*! CDATA_89 - Data Debug Register - Bit 89 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_89(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_89_SHIFT)) & MBIST_DBG2_CDATA_89_MASK) +#define MBIST_DBG2_CDATA_90_MASK (0x4000000U) +#define MBIST_DBG2_CDATA_90_SHIFT (26U) +/*! CDATA_90 - Data Debug Register - Bit 90 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_90(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_90_SHIFT)) & MBIST_DBG2_CDATA_90_MASK) +#define MBIST_DBG2_CDATA_91_MASK (0x8000000U) +#define MBIST_DBG2_CDATA_91_SHIFT (27U) +/*! CDATA_91 - Data Debug Register - Bit 91 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_91(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_91_SHIFT)) & MBIST_DBG2_CDATA_91_MASK) +#define MBIST_DBG2_CDATA_92_MASK (0x10000000U) +#define MBIST_DBG2_CDATA_92_SHIFT (28U) +/*! CDATA_92 - Data Debug Register - Bit 92 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_92(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_92_SHIFT)) & MBIST_DBG2_CDATA_92_MASK) +#define MBIST_DBG2_CDATA_93_MASK (0x20000000U) +#define MBIST_DBG2_CDATA_93_SHIFT (29U) +/*! CDATA_93 - Data Debug Register - Bit 93 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_93(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_93_SHIFT)) & MBIST_DBG2_CDATA_93_MASK) +#define MBIST_DBG2_CDATA_94_MASK (0x40000000U) +#define MBIST_DBG2_CDATA_94_SHIFT (30U) +/*! CDATA_94 - Data Debug Register - Bit 94 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_94(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_94_SHIFT)) & MBIST_DBG2_CDATA_94_MASK) +#define MBIST_DBG2_CDATA_95_MASK (0x80000000U) +#define MBIST_DBG2_CDATA_95_SHIFT (31U) +/*! CDATA_95 - Data Debug Register - Bit 95 + * 0b0..Bit compare passed. + * 0b1..Bit compare failed. + */ +#define MBIST_DBG2_CDATA_95(x) (((uint32_t)(((uint32_t)(x)) << MBIST_DBG2_CDATA_95_SHIFT)) & MBIST_DBG2_CDATA_95_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MBIST_Register_Masks */ + +/*! + * @} + */ /* end of group MBIST_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MX8_MBIST_H */ + diff --git a/platform/devices/MX8/MX8_mcm.h b/platform/devices/MX8/MX8_mcm.h new file mode 100755 index 0000000..d947cb2 --- /dev/null +++ b/platform/devices/MX8/MX8_mcm.h @@ -0,0 +1,291 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_MCM_REGISTERS_H +#define HW_MCM_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + __I uint32_t REVINFO; /**< Core Type and Plaform Revision register, offset: 0x0 */ + __I uint32_t MEMCFG; /**< Memory Configuration register, offset: 0x4 */ + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + __IO uint32_t CR; /**< Control Register, offset: 0xC */ + __IO uint32_t ISCR; /**< Interrupt Status and control Register, offset: 0x10 */ + __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */ + __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */ + __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */ + __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ + __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ + __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ + uint8_t RESERVED_3[956]; + __IO uint32_t LMDR0; /**< Local Memory Descriptor Register, offset: 0x400 */ + __IO uint32_t LMDR1; /**< Local Memory Descriptor Register, offset: 0x404 */ + __IO uint32_t LMDR2; /**< Local Memory Descriptor Register, offset: 0x408 */ + __IO uint32_t LMDR3; /**< Local Memory Descriptor Register, offset: 0x40C */ + uint8_t RESERVED_4[112]; + __IO uint32_t LMPECR; /**< LMEM Parity & ECC Control Register, offset: 0x480 */ + uint8_t RESERVED_5[4]; + __IO uint32_t LMPEIR; /**< LMEM Parity & ECC Interrupt Register, offset: 0x488 */ + uint8_t RESERVED_6[4]; + __IO uint32_t LMFAR; /**< LMEM Fault Address Register, offset: 0x490 */ + __IO uint32_t LMFATR; /**< LMEM Fault Attribute Register, offset: 0x494 */ + uint8_t RESERVED_7[8]; + __IO uint32_t LMFDHR; /**< LMEM Fault Data High Register, offset: 0x4A0 */ + __IO uint32_t LMFDLR; /**< LMEM Fault Data Low Register, offset: 0x4A4 */ +} MCM_Type; + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +#define MCM_PLASC_ASC_MASK (0xFFU) +#define MCM_PLASC_ASC_SHIFT (0U) +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) + +/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +#define MCM_PLAMC_AMC_MASK (0xFFU) +#define MCM_PLAMC_AMC_SHIFT (0U) +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) + +/*! @name CR - Control Register */ +#define MCM_CR_DDRSIZE_MASK (0x300000U) +#define MCM_CR_DDRSIZE_SHIFT (20U) +#define MCM_CR_DDRSIZE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_DDRSIZE_SHIFT)) & MCM_CR_DDRSIZE_MASK) +#define MCM_CR_SRAMUAP_MASK (0x3000000U) +#define MCM_CR_SRAMUAP_SHIFT (24U) +#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK) +#define MCM_CR_SRAMUWP_MASK (0x4000000U) +#define MCM_CR_SRAMUWP_SHIFT (26U) +#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK) +#define MCM_CR_SRAMLAP_MASK (0x30000000U) +#define MCM_CR_SRAMLAP_SHIFT (28U) +#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK) +#define MCM_CR_SRAMLWP_MASK (0x40000000U) +#define MCM_CR_SRAMLWP_SHIFT (30U) +#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK) + +/*! @name ISCR - Interrupt Status and control Register */ +#define MCM_ISCR_IRQ_MASK (0x2U) +#define MCM_ISCR_IRQ_SHIFT (1U) +#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK) +#define MCM_ISCR_NMI_MASK (0x4U) +#define MCM_ISCR_NMI_SHIFT (2U) +#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK) +#define MCM_ISCR_DHREQ_MASK (0x8U) +#define MCM_ISCR_DHREQ_SHIFT (3U) +#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK) +#define MCM_ISCR_CWBER_MASK (0x10U) +#define MCM_ISCR_CWBER_SHIFT (4U) +#define MCM_ISCR_CWBER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK) +#define MCM_ISCR_FIOC_MASK (0x100U) +#define MCM_ISCR_FIOC_SHIFT (8U) +#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) +#define MCM_ISCR_FDZC_MASK (0x200U) +#define MCM_ISCR_FDZC_SHIFT (9U) +#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) +#define MCM_ISCR_FOFC_MASK (0x400U) +#define MCM_ISCR_FOFC_SHIFT (10U) +#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) +#define MCM_ISCR_FUFC_MASK (0x800U) +#define MCM_ISCR_FUFC_SHIFT (11U) +#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) +#define MCM_ISCR_FIXC_MASK (0x1000U) +#define MCM_ISCR_FIXC_SHIFT (12U) +#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) +#define MCM_ISCR_FIDC_MASK (0x8000U) +#define MCM_ISCR_FIDC_SHIFT (15U) +#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) +#define MCM_ISCR_CWBEE_MASK (0x100000U) +#define MCM_ISCR_CWBEE_SHIFT (20U) +#define MCM_ISCR_CWBEE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK) +#define MCM_ISCR_FIOCE_MASK (0x1000000U) +#define MCM_ISCR_FIOCE_SHIFT (24U) +#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) +#define MCM_ISCR_FDZCE_MASK (0x2000000U) +#define MCM_ISCR_FDZCE_SHIFT (25U) +#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) +#define MCM_ISCR_FOFCE_MASK (0x4000000U) +#define MCM_ISCR_FOFCE_SHIFT (26U) +#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) +#define MCM_ISCR_FUFCE_MASK (0x8000000U) +#define MCM_ISCR_FUFCE_SHIFT (27U) +#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) +#define MCM_ISCR_FIXCE_MASK (0x10000000U) +#define MCM_ISCR_FIXCE_SHIFT (28U) +#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) +#define MCM_ISCR_FIDCE_MASK (0x80000000U) +#define MCM_ISCR_FIDCE_SHIFT (31U) +#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) + +/*! @name ETBCC - ETB Counter Control register */ +#define MCM_ETBCC_CNTEN_MASK (0x1U) +#define MCM_ETBCC_CNTEN_SHIFT (0U) +#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK) +#define MCM_ETBCC_RSPT_MASK (0x6U) +#define MCM_ETBCC_RSPT_SHIFT (1U) +#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK) +#define MCM_ETBCC_RLRQ_MASK (0x8U) +#define MCM_ETBCC_RLRQ_SHIFT (3U) +#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK) +#define MCM_ETBCC_ETDIS_MASK (0x10U) +#define MCM_ETBCC_ETDIS_SHIFT (4U) +#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK) +#define MCM_ETBCC_ITDIS_MASK (0x20U) +#define MCM_ETBCC_ITDIS_SHIFT (5U) +#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK) + +/*! @name ETBRL - ETB Reload register */ +#define MCM_ETBRL_RELOAD_MASK (0x7FFU) +#define MCM_ETBRL_RELOAD_SHIFT (0U) +#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK) + +/*! @name ETBCNT - ETB Counter Value register */ +#define MCM_ETBCNT_COUNTER_MASK (0x7FFU) +#define MCM_ETBCNT_COUNTER_SHIFT (0U) +#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK) + +/*! @name FADR - Fault address register */ +#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) +#define MCM_FADR_ADDRESS_SHIFT (0U) +#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) + +/*! @name FATR - Fault attributes register */ +#define MCM_FATR_BEDA_MASK (0x1U) +#define MCM_FATR_BEDA_SHIFT (0U) +#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) +#define MCM_FATR_BEMD_MASK (0x2U) +#define MCM_FATR_BEMD_SHIFT (1U) +#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) +#define MCM_FATR_BESZ_MASK (0x30U) +#define MCM_FATR_BESZ_SHIFT (4U) +#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) +#define MCM_FATR_BEWT_MASK (0x80U) +#define MCM_FATR_BEWT_SHIFT (7U) +#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) +#define MCM_FATR_BEMN_MASK (0xF00U) +#define MCM_FATR_BEMN_SHIFT (8U) +#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) +#define MCM_FATR_BEOVR_MASK (0x80000000U) +#define MCM_FATR_BEOVR_SHIFT (31U) +#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) + +/*! @name FDR - Fault data register */ +#define MCM_FDR_DATA_MASK (0xFFFFFFFFU) +#define MCM_FDR_DATA_SHIFT (0U) +#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) + +/*! @name PID - Process ID register */ +#define MCM_PID_PID_MASK (0xFFU) +#define MCM_PID_PID_SHIFT (0U) +#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) + +/*! @name PID - Process ID register */ +#define MCM_LMPEIR_ENC_TCML_MASK (0x00000001U) +#define MCM_LMPEIR_ENC_TCML_SHIFT (0U) +#define MCM_LMPEIR_ENC_TCML(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_TCML_SHIFT)) & MCM_LMPEIR_ENC_TCML_MASK) +#define MCM_LMPEIR_ENC_TCMU_MASK (0x00000002U) +#define MCM_LMPEIR_ENC_TCMU_SHIFT (1U) +#define MCM_LMPEIR_ENC_TCMU(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_TCMU_SHIFT)) & MCM_LMPEIR_ENC_TCMU_MASK) +#define MCM_LMPEIR_PE_CCTAG_MASK (0x00100000U) +#define MCM_LMPEIR_PE_CCTAG_SHIFT (20U) +#define MCM_LMPEIR_PE_CCTAG(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_CCTAG_SHIFT)) & MCM_LMPEIR_PE_CCTAG_MASK) +#define MCM_LMPEIR_PE_CCDATA_MASK (0x00200000U) +#define MCM_LMPEIR_PE_CCDATA_SHIFT (21U) +#define MCM_LMPEIR_PE_CCDATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_CCDATA_SHIFT)) & MCM_LMPEIR_PE_CCDATA_MASK) +#define MCM_LMPEIR_PE_SCTAG_MASK (0x00400000U) +#define MCM_LMPEIR_PE_SCTAG_SHIFT (22U) +#define MCM_LMPEIR_PE_SCTAG(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SCTAG_SHIFT)) & MCM_LMPEIR_PE_SCTAG_MASK) +#define MCM_LMPEIR_PE_SCDATA_MASK (0x00800000U) +#define MCM_LMPEIR_PE_SCDATA_SHIFT (23U) +#define MCM_LMPEIR_PE_SCDATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SCDATA_SHIFT)) & MCM_LMPEIR_PE_SCDATA_MASK) +#define MCM_LMPEIR_PEELOC_MASK (0x1F000000U) +#define MCM_LMPEIR_PEELOC_SHIFT (24U) +#define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK) +#define MCM_LMPEIR_V_MASK (0x80000000U) +#define MCM_LMPEIR_V_SHIFT (31U) +#define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK) + + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +/** Array initializer of MCM peripheral base addresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } + +/*! + * @} + */ /* end of group MCM_Peripheral_Access_Layer */ + +#endif /* HW_MCM_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_mu.h b/platform/devices/MX8/MX8_mu.h new file mode 100755 index 0000000..cae01ea --- /dev/null +++ b/platform/devices/MX8/MX8_mu.h @@ -0,0 +1,278 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ + +#ifndef HW_MU_REGISTERS_H +#define HW_MU_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- MU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @brief Core B boot mode. + */ +typedef enum _mu_core_boot_mode +{ + kMU_CoreBootFromAddr0 = 0x00U, /*!< Boot from 0x00. */ + kMU_CoreBootFromDmem = 0x01U, /*!< Boot from DMEM base. */ + kMU_CoreBootFromImem = 0x02U /*!< Boot from IMEM base. */ +} mu_core_boot_mode_t; + +/*! + * @brief Power mode definition. + */ +typedef enum _mu_power_mode +{ + kMU_PowerModeRun = 0x00U, /*!< Run mode. */ + kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */ + kMU_PowerModeStop = 0x02U, /*!< STOP/VLPS mode. */ + kMU_PowerModeDsm = 0x03U /*!< DSM: LLS/VLLS mode. */ +} mu_power_mode_t; + +/*! + * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer + * @{ + */ + +/** MU - Register Layout Typedef */ +typedef struct { + __IO uint32_t TR[4]; /**< Transmit Register, array offset: 0x00, array step: 0x4 */ + __I uint32_t RR[4]; /**< Receive Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t SR; /**< Status Register, offset: 0x20 */ + __IO uint32_t CR; /**< Control Register, offset: 0x24 */ +} MU_Type; + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/*! @name TR - Transmit Register */ +#define MU_TR_DATA_MASK (0xFFFFFFFFU) +#define MU_TR_DATA_SHIFT (0U) +#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK) + +/* The count of MU_TR */ +#define MU_TR_COUNT (4U) + +/*! @name RR - Receive Register */ +#define MU_RR_DATA_MASK (0xFFFFFFFFU) +#define MU_RR_DATA_SHIFT (0U) +#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK) + +/* The count of MU_RR */ +#define MU_RR_COUNT (4U) + +/*! @name SR - Status Register */ +#define MU_SR_Fn_MASK (0x7U) +#define MU_SR_Fn_SHIFT (0U) +#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) +#define MU_SR_NMIC_MASK (0x8U) +#define MU_SR_NMIC_SHIFT (3U) +#define MU_SR_NMIC(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_NMIC_SHIFT)) & MU_SR_NMIC_MASK) +#define MU_SR_EP_MASK (0x10U) +#define MU_SR_EP_SHIFT (4U) +#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) +#define MU_SR_PM_MASK (0x60U) +#define MU_SR_PM_SHIFT (5U) +#define MU_SR_PM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_PM_SHIFT)) & MU_SR_PM_MASK) +#define MU_SR_FUP_MASK (0x100U) +#define MU_SR_FUP_SHIFT (8U) +#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) +#define MU_SR_TEn_MASK (0xF00000U) +#define MU_SR_TEn_SHIFT (20U) +#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) +#define MU_SR_RFn_MASK (0xF000000U) +#define MU_SR_RFn_SHIFT (24U) +#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) +#define MU_SR_GIPn_MASK (0xF0000000U) +#define MU_SR_GIPn_SHIFT (28U) +#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK) + +/*! @name CR - Control Register */ +#define MU_CR_Fn_MASK (0x7U) +#define MU_CR_Fn_SHIFT (0U) +#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK) +#define MU_CR_NMI_MASK (0x8U) +#define MU_CR_NMI_SHIFT (3U) +#define MU_CR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_NMI_SHIFT)) & MU_CR_NMI_MASK) +#define MU_CR_MUR_MASK (0x20U) +#define MU_CR_MUR_SHIFT (5U) +#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) +#define MU_CR_BRSTH_MASK (0x80U) +#define MU_CR_BRSTH_SHIFT (7U) +#define MU_CR_BRSTH(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BRSTH_SHIFT)) & MU_CR_BRSTH_MASK) +#define MU_CR_CLKE_MASK (0x100U) +#define MU_CR_CLKE_SHIFT (8U) +#define MU_CR_CLKE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_CLKE_SHIFT)) & MU_CR_CLKE_MASK) +#define MU_CR_BBOOT_MASK (0x600U) +#define MU_CR_BBOOT_SHIFT (9U) +#define MU_CR_BBOOT(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BBOOT_SHIFT)) & MU_CR_BBOOT_MASK) +#define MU_CR_GIRn_MASK (0xF0000U) +#define MU_CR_GIRn_SHIFT (16U) +#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) +#define MU_CR_TIEn_MASK (0xF00000U) +#define MU_CR_TIEn_SHIFT (20U) +#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) +#define MU_CR_RIEn_MASK (0xF000000U) +#define MU_CR_RIEn_SHIFT (24U) +#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) +#define MU_CR_GIEn_MASK (0xF0000000U) +#define MU_CR_GIEn_SHIFT (28U) +#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK) + + +/*! + * @} + */ /* end of group MU_Register_Masks */ + + +/* MU - Peripheral instance base addresses */ + +/** This define is used to access MU registers */ +#define DSC_MU_BASE_ADDR(X, Y) ((MU_Type*) (((uint32_t) DSC_BASE_ADDR(X)) \ + + 0xC000U + (0x80U * (Y)))) + +/** Peripheral MU0 base pointer */ +#define MU0 ((MU_Type *)MU0_BASE) +/** Peripheral MU1 base pointer */ +#define MU1 ((MU_Type *)MU1_BASE) +/** Peripheral MU2 base pointer */ +#define MU2 ((MU_Type *)MU2_BASE) +/** Peripheral MU3 base pointer */ +#define MU3 ((MU_Type *)MU3_BASE) +/** Peripheral MU4 base pointer */ +#define MU4 ((MU_Type *)MU4_BASE) +/** Peripheral MU5 base pointer */ +#define MU5 ((MU_Type *)MU5_BASE) +/** Peripheral MU6 base pointer */ +#define MU6 ((MU_Type *)MU6_BASE) +/** Peripheral MU7 base pointer */ +#define MU7 ((MU_Type *)MU7_BASE) +/** Peripheral MU8 base pointer */ +#define MU8 ((MU_Type *)MU8_BASE) +/** Peripheral MU9 base pointer */ +#define MU9 ((MU_Type *)MU9_BASE) +/** Peripheral MU10 base pointer */ +#define MU10 ((MU_Type *)MU10_BASE) +/** Peripheral MU11 base pointer */ +#define MU11 ((MU_Type *)MU11_BASE) +/** Peripheral MU12 base pointer */ +#define MU12 ((MU_Type *)MU12_BASE) +/** Peripheral MU13 base pointer */ +#define MU13 ((MU_Type *)MU13_BASE) +/** Peripheral MU14 base pointer */ +#define MU14 ((MU_Type *)MU14_BASE) +/** Peripheral MU15 base pointer */ +#define MU15 ((MU_Type *)MU15_BASE) +/** Peripheral MU16 base pointer */ +#define MU16 ((MU_Type *)MU16_BASE) +/** Peripheral MU17 base pointer */ +#define MU17 ((MU_Type *)MU17_BASE) +/** Peripheral MU18 base pointer */ +#define MU18 ((MU_Type *)MU18_BASE) +/** Peripheral MU19 base pointer */ +#define MU19 ((MU_Type *)MU19_BASE) +/** Peripheral MU20 base pointer */ +#define MU20 ((MU_Type *)MU20_BASE) +/** Peripheral MU21 base pointer */ +#define MU21 ((MU_Type *)MU21_BASE) +/** Peripheral MU22 base pointer */ +#define MU22 ((MU_Type *)MU22_BASE) +/** Peripheral MU23 base pointer */ +#define MU23 ((MU_Type *)MU23_BASE) +/** Peripheral MU24 base pointer */ +#define MU24 ((MU_Type *)MU24_BASE) + +/** Array initializer of MU peripheral base addresses */ +#define MU_BASE_ADDRS { MU0_BASE, MU1_BASE, \ + MU2_BASE, MU3_BASE, \ + MU4_BASE, MU5_BASE, \ + MU6_BASE, MU7_BASE, \ + MU8_BASE, MU9_BASE, \ + MU10_BASE, MU11_BASE, \ + MU12_BASE, MU13_BASE, \ + MU14_BASE, MU15_BASE, \ + MU16_BASE, MU17_BASE, \ + MU18_BASE, MU19_BASE, \ + MU20_BASE, MU21_BASE, \ + MU22_BASE, MU23_BASE, \ + MU24_BASE } +/** Array initializer of MU peripheral base pointers */ +#define MU_BASE_PTRS { MU0, MU1, MU2, \ + MU3, MU4, MU5, \ + MU6, MU7, MU8, \ + MU9, MU10, MU11, \ + MU12, MU13, MU14, \ + MU15, MU16, MU17, \ + MU18, MU19, MU20, \ + MU21, MU22, MU23, \ + MU24 } +/** Interrupt vectors for the MU peripheral type */ +#define MU_IRQS { NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn } + +/*! + * @} + */ /* end of group MU_Peripheral_Access_Layer */ + +#endif /* HW_MU_REGISTERS_H */ + diff --git a/platform/devices/MX8/MX8_pad.h b/platform/devices/MX8/MX8_pad.h new file mode 100755 index 0000000..7144dbc --- /dev/null +++ b/platform/devices/MX8/MX8_pad.h @@ -0,0 +1,303 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file MX8_pad.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for PAD + * + * CMSIS Peripheral Access Layer for PAD + */ + +#ifndef HW_PAD_REGISTERS_H +#define HW_PAD_REGISTERS_H + +#define IOMUXD_REG_BASE 0UL +#define REG32(X) ((uint32_t) (X)) + +#include "iomuxd.h" + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- PAD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PAD_Peripheral_Access_Layer PAD Peripheral Access Layer + * @{ + */ + +/** PAD - Register Layout Typedef */ +typedef struct { + __IO uint32_t RW; + __IO uint32_t SET; + __IO uint32_t CLR; + __IO uint32_t TOG; + uint32_t reserved[12]; +} PAD_Type; + +/** PADRING - Register Layout Typedef */ +typedef struct { + struct { + struct { + PAD_Type PAD[16]; + __I uint32_t GLOBAL; + uint32_t reserved[767]; + } GROUP[32]; + } RING[4]; +} PADRING_Type; + +/* ---------------------------------------------------------------------------- + -- PAD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PAD_Register_Masks PAD Register Masks + * @{ + */ + +/*! @name IOMUX - Register */ +#define IOMUX_REG_PAD_CTL_MASK (0x7FFFFU) +#define IOMUX_REG_PAD_CTL_SHIFT (0U) +#define IOMUX_REG_PAD_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_PAD_CTL_SHIFT)) & IOMUX_REG_PAD_CTL_MASK) +#define IOMUX_REG_WAKEUP_CTRL_MASK (0x380000U) +#define IOMUX_REG_WAKEUP_CTRL_SHIFT (19U) +#define IOMUX_REG_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_WAKEUP_CTRL_SHIFT)) & IOMUX_REG_WAKEUP_CTRL_MASK) +#define IOMUX_REG_WAKEUP_MASK_MASK (0x400000U) +#define IOMUX_REG_WAKEUP_MASK_SHIFT (22U) +#define IOMUX_REG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_WAKEUP_MASK_SHIFT)) & IOMUX_REG_WAKEUP_MASK_MASK) +#define IOMUX_REG_LP_CONFIG_MASK (0x1800000U) +#define IOMUX_REG_LP_CONFIG_SHIFT (23U) +#define IOMUX_REG_LP_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_LP_CONFIG_SHIFT)) & IOMUX_REG_LP_CONFIG_MASK) +#define IOMUX_REG_SW_CONFIG_MASK (0x6000000U) +#define IOMUX_REG_SW_CONFIG_SHIFT (25U) +#define IOMUX_REG_SW_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_SW_CONFIG_SHIFT)) & IOMUX_REG_SW_CONFIG_MASK) +#define IOMUX_REG_MUX_MODE_MASK (0x38000000U) +#define IOMUX_REG_MUX_MODE_SHIFT (27U) +#define IOMUX_REG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_MUX_MODE_SHIFT)) & IOMUX_REG_MUX_MODE_MASK) +#define IOMUX_REG_UPDATE_PAD_CTL_MASK (0x40000000U) +#define IOMUX_REG_UPDATE_PAD_CTL_SHIFT (30U) +#define IOMUX_REG_UPDATE_PAD_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_UPDATE_PAD_CTL_SHIFT)) & IOMUX_REG_UPDATE_PAD_CTL_MASK) +#define IOMUX_REG_UPDATE_MUX_MODE_MASK (0x80000000U) +#define IOMUX_REG_UPDATE_MUX_MODE_SHIFT (31U) +#define IOMUX_REG_UPDATE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_UPDATE_MUX_MODE_SHIFT)) & IOMUX_REG_UPDATE_MUX_MODE_MASK) + +/*! @name 28FDSOI_IOMUX - Register */ +#define IOMUX_REG_28FDSOI_PDRV_MASK (0x7U) +#define IOMUX_REG_28FDSOI_PDRV_SHIFT (0U) +#define IOMUX_REG_28FDSOI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_PDRV_SHIFT)) & IOMUX_REG_28FDSOI_PDRV_MASK) +#define IOMUX_REG_28FDSOI_PULL_MASK (0x60U) +#define IOMUX_REG_28FDSOI_PULL_SHIFT (5U) +#define IOMUX_REG_28FDSOI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_PULL_SHIFT)) & IOMUX_REG_28FDSOI_PULL_MASK) +#define IOMUX_REG_28FDSOI_WAKEUP_CTRL_MASK (0x380000U) +#define IOMUX_REG_28FDSOI_WAKEUP_CTRL_SHIFT (19U) +#define IOMUX_REG_28FDSOI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_WAKEUP_CTRL_SHIFT)) & IOMUX_REG_28FDSOI_WAKEUP_CTRL_MASK) +#define IOMUX_REG_28FDSOI_WAKEUP_MASK_MASK (0x400000U) +#define IOMUX_REG_28FDSOI_WAKEUP_MASK_SHIFT (22U) +#define IOMUX_REG_28FDSOI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_WAKEUP_MASK_SHIFT)) & IOMUX_REG_28FDSOI_WAKEUP_MASK_MASK) +#define IOMUX_REG_28FDSOI_LP_CONFIG_MASK (0x1800000U) +#define IOMUX_REG_28FDSOI_LP_CONFIG_SHIFT (23U) +#define IOMUX_REG_28FDSOI_LP_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_LP_CONFIG_SHIFT)) & IOMUX_REG_28FDSOI_LP_CONFIG_MASK) +#define IOMUX_REG_28FDSOI_SW_CONFIG_MASK (0x6000000U) +#define IOMUX_REG_28FDSOI_SW_CONFIG_SHIFT (25U) +#define IOMUX_REG_28FDSOI_SW_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_SW_CONFIG_SHIFT)) & IOMUX_REG_28FDSOI_SW_CONFIG_MASK) +#define IOMUX_REG_28FDSOI_MUX_MODE_MASK (0x38000000U) +#define IOMUX_REG_28FDSOI_MUX_MODE_SHIFT (27U) +#define IOMUX_REG_28FDSOI_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_MUX_MODE_SHIFT)) & IOMUX_REG_28FDSOI_MUX_MODE_MASK) +#define IOMUX_REG_28FDSOI_UPDATE_PAD_CTL_MASK (0x40000000U) +#define IOMUX_REG_28FDSOI_UPDATE_PAD_CTL_SHIFT (30U) +#define IOMUX_REG_28FDSOI_UPDATE_PAD_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_UPDATE_PAD_CTL_SHIFT)) & IOMUX_REG_28FDSOI_UPDATE_PAD_CTL_MASK) +#define IOMUX_REG_28FDSOI_UPDATE_MUX_MODE_MASK (0x80000000U) +#define IOMUX_REG_28FDSOI_UPDATE_MUX_MODE_SHIFT (31U) +#define IOMUX_REG_28FDSOI_UPDATE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_UPDATE_MUX_MODE_SHIFT)) & IOMUX_REG_28FDSOI_UPDATE_MUX_MODE_MASK) + +/*! @name 28FDSOI_HSIC - Register */ +#define IOMUX_REG_28FDSOI_HSIC_DSE_MASK (0x7U) +#define IOMUX_REG_28FDSOI_HSIC_DSE_SHIFT (0U) +#define IOMUX_REG_28FDSOI_HSIC_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_DSE_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_DSE_MASK) +#define IOMUX_REG_28FDSOI_HSIC_HYS_MASK (0x8U) +#define IOMUX_REG_28FDSOI_HSIC_HYS_SHIFT (3U) +#define IOMUX_REG_28FDSOI_HSIC_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_HYS_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_HYS_MASK) +#define IOMUX_REG_28FDSOI_HSIC_PS_MASK (0x30U) +#define IOMUX_REG_28FDSOI_HSIC_PS_SHIFT (4U) +#define IOMUX_REG_28FDSOI_HSIC_PS(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_PS_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_PS_MASK) +#define IOMUX_REG_28FDSOI_HSIC_PKE_MASK (0x40U) +#define IOMUX_REG_28FDSOI_HSIC_PKE_SHIFT (6U) +#define IOMUX_REG_28FDSOI_HSIC_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_PKE_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_PKE_MASK) +#define IOMUX_REG_28FDSOI_HSIC_PE_MASK (0x80U) +#define IOMUX_REG_28FDSOI_HSIC_PE_SHIFT (7U) +#define IOMUX_REG_28FDSOI_HSIC_PE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_PE_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_PE_MASK) +#define IOMUX_REG_28FDSOI_HSIC_WAKEUP_CTRL_MASK (0x380000U) +#define IOMUX_REG_28FDSOI_HSIC_WAKEUP_CTRL_SHIFT (19U) +#define IOMUX_REG_28FDSOI_HSIC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_WAKEUP_CTRL_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_WAKEUP_CTRL_MASK) +#define IOMUX_REG_28FDSOI_HSIC_WAKEUP_MASK_MASK (0x400000U) +#define IOMUX_REG_28FDSOI_HSIC_WAKEUP_MASK_SHIFT (22U) +#define IOMUX_REG_28FDSOI_HSIC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_WAKEUP_MASK_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_WAKEUP_MASK_MASK) +#define IOMUX_REG_28FDSOI_HSIC_LP_CONFIG_MASK (0x1800000U) +#define IOMUX_REG_28FDSOI_HSIC_LP_CONFIG_SHIFT (23U) +#define IOMUX_REG_28FDSOI_HSIC_LP_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_LP_CONFIG_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_LP_CONFIG_MASK) +#define IOMUX_REG_28FDSOI_HSIC_SW_CONFIG_MASK (0x6000000U) +#define IOMUX_REG_28FDSOI_HSIC_SW_CONFIG_SHIFT (25U) +#define IOMUX_REG_28FDSOI_HSIC_SW_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_SW_CONFIG_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_SW_CONFIG_MASK) +#define IOMUX_REG_28FDSOI_HSIC_MUX_MODE_MASK (0x38000000U) +#define IOMUX_REG_28FDSOI_HSIC_MUX_MODE_SHIFT (27U) +#define IOMUX_REG_28FDSOI_HSIC_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_MUX_MODE_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_MUX_MODE_MASK) +#define IOMUX_REG_28FDSOI_HSIC_UPDATE_PAD_CTL_MASK (0x40000000U) +#define IOMUX_REG_28FDSOI_HSIC_UPDATE_PAD_CTL_SHIFT (30U) +#define IOMUX_REG_28FDSOI_HSIC_UPDATE_PAD_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_UPDATE_PAD_CTL_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_UPDATE_PAD_CTL_MASK) +#define IOMUX_REG_28FDSOI_HSIC_UPDATE_MUX_MODE_MASK (0x80000000U) +#define IOMUX_REG_28FDSOI_HSIC_UPDATE_MUX_MODE_SHIFT (31U) +#define IOMUX_REG_28FDSOI_HSIC_UPDATE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_HSIC_UPDATE_MUX_MODE_SHIFT)) & IOMUX_REG_28FDSOI_HSIC_UPDATE_MUX_MODE_MASK) + +/*! @name 28FDSOI_COMP - Register */ +#define IOMUX_REG_28FDSOI_COMP_COMP_MASK (0x7U) +#define IOMUX_REG_28FDSOI_COMP_COMP_SHIFT (0U) +#define IOMUX_REG_28FDSOI_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_COMP_SHIFT)) & IOMUX_REG_28FDSOI_COMP_COMP_MASK) +#define IOMUX_REG_28FDSOI_COMP_FASTFRZ_EN_MASK (0x8U) +#define IOMUX_REG_28FDSOI_COMP_FASTFRZ_EN_SHIFT (3U) +#define IOMUX_REG_28FDSOI_COMP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_FASTFRZ_EN_SHIFT)) & IOMUX_REG_28FDSOI_COMP_FASTFRZ_EN_MASK) +#define IOMUX_REG_28FDSOI_COMP_PSW_OVR_MASK (0x10U) +#define IOMUX_REG_28FDSOI_COMP_PSW_OVR_SHIFT (4U) +#define IOMUX_REG_28FDSOI_COMP_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_PSW_OVR_SHIFT)) & IOMUX_REG_28FDSOI_COMP_PSW_OVR_MASK) +#define IOMUX_REG_28FDSOI_COMP_RASRCP_MASK (0x1E0U) +#define IOMUX_REG_28FDSOI_COMP_RASRCP_SHIFT (5U) +#define IOMUX_REG_28FDSOI_COMP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_RASRCP_SHIFT)) & IOMUX_REG_28FDSOI_COMP_RASRCP_MASK) +#define IOMUX_REG_28FDSOI_COMP_RASRCN_MASK (0x1E00U) +#define IOMUX_REG_28FDSOI_COMP_RASRCN_SHIFT (9U) +#define IOMUX_REG_28FDSOI_COMP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_RASRCN_SHIFT)) & IOMUX_REG_28FDSOI_COMP_RASRCN_MASK) +#define IOMUX_REG_28FDSOI_COMP_SELECT_NASRC_MASK (0x2000U) +#define IOMUX_REG_28FDSOI_COMP_SELECT_NASRC_SHIFT (13U) +#define IOMUX_REG_28FDSOI_COMP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_SELECT_NASRC_SHIFT)) & IOMUX_REG_28FDSOI_COMP_SELECT_NASRC_MASK) +#define IOMUX_REG_28FDSOI_COMP_COMPOK_MASK (0x4000U) +#define IOMUX_REG_28FDSOI_COMP_COMPOK_SHIFT (14U) +#define IOMUX_REG_28FDSOI_COMP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_COMPOK_SHIFT)) & IOMUX_REG_28FDSOI_COMP_COMPOK_MASK) +#define IOMUX_REG_28FDSOI_COMP_READ_NASRC_MASK (0x78000U) +#define IOMUX_REG_28FDSOI_COMP_READ_NASRC_SHIFT (15U) +#define IOMUX_REG_28FDSOI_COMP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_READ_NASRC_SHIFT)) & IOMUX_REG_28FDSOI_COMP_READ_NASRC_MASK) +#define IOMUX_REG_28FDSOI_COMP_SLEEP_MASK (0x1800000U) +#define IOMUX_REG_28FDSOI_COMP_SLEEP_SHIFT (23U) +#define IOMUX_REG_28FDSOI_COMP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_SLEEP_SHIFT)) & IOMUX_REG_28FDSOI_COMP_SLEEP_MASK) +#define IOMUX_REG_28FDSOI_COMP_UPDATE_PAD_CTL_MASK (0x40000000U) +#define IOMUX_REG_28FDSOI_COMP_UPDATE_PAD_CTL_SHIFT (30U) +#define IOMUX_REG_28FDSOI_COMP_UPDATE_PAD_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_UPDATE_PAD_CTL_SHIFT)) & IOMUX_REG_28FDSOI_COMP_UPDATE_PAD_CTL_MASK) +#define IOMUX_REG_28FDSOI_COMP_UPDATE_MUX_MODE_MASK (0x80000000U) +#define IOMUX_REG_28FDSOI_COMP_UPDATE_MUX_MODE_SHIFT (31U) +#define IOMUX_REG_28FDSOI_COMP_UPDATE_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUX_REG_28FDSOI_COMP_UPDATE_MUX_MODE_SHIFT)) & IOMUX_REG_28FDSOI_COMP_UPDATE_MUX_MODE_MASK) + +/*! + * @} + */ /* end of group PAD_Register_Masks */ + + +/*! + * @name Constants and macros for entire PAD_IOMUX register + */ +/** @{ */ +#define HW_PAD_IOMUX_ADDR(x, y) ((uintptr_t)(x) + (y)) +#define HW_PAD_IOMUX(x, y) (*(__IO PAD_Type *) HW_PAD_IOMUX_ADDR(x, y)) +#define HW_PAD_IOMUX_RD(x, y) (HW_PAD_IOMUX(x, y).RW) +#define HW_PAD_IOMUX_WR(x, y) (HW_PAD_IOMUX(x, y).RW) +/** @} */ + +/*! + * @} + */ /* end of group XRDC2_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* XRDC2_H */ + diff --git a/platform/devices/MX8/MX8_rep2.h b/platform/devices/MX8/MX8_rep2.h new file mode 100755 index 0000000..68ef5ae --- /dev/null +++ b/platform/devices/MX8/MX8_rep2.h @@ -0,0 +1,245 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file rep2.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for rep2 + * + * CMSIS Peripheral Access Layer for rep2 + */ + +#ifndef REP2_H +#define REP2_H /**< Symbol preventing repeated inclusion */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- REP2 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup REP2_Peripheral_Access_Layer REP2 Peripheral Access Layer + * @{ + */ + +/** REP2 - Register Layout Typedef */ +typedef struct { + __I uint32_t REPSTAT; /**< REP status Register, offset: 0x0 */ + __IO uint32_t IR; /**< Instruction Register, offset: 0x4 */ + uint8_t RESERVED_0[20]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x1C */ + __I uint32_t ECCSTAT; /**< ECC status Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PPSEL; /**< Power plane select Register, offset: 0x30 */ + uint8_t RESERVED_2[204]; + __IO uint32_t SSR[64]; /**< Solution Stage Register - word 0, offset: 0x100 */ +} REP2_Type; + +/* ---------------------------------------------------------------------------- + -- REP2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup REP2_Register_Masks REP2 Register Masks + * @{ + */ + +/*! @name REPSTAT - REP status Register */ +#define REP2_REPSTAT_IDL_MASK (0x1U) +#define REP2_REPSTAT_IDL_SHIFT (0U) +#define REP2_REPSTAT_IDL(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_IDL_SHIFT)) & REP2_REPSTAT_IDL_MASK) +#define REP2_REPSTAT_CIE_MASK (0x2U) +#define REP2_REPSTAT_CIE_SHIFT (1U) +#define REP2_REPSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_CIE_SHIFT)) & REP2_REPSTAT_CIE_MASK) +#define REP2_REPSTAT_INE_MASK (0x4U) +#define REP2_REPSTAT_INE_SHIFT (2U) +#define REP2_REPSTAT_INE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_INE_SHIFT)) & REP2_REPSTAT_INE_MASK) +#define REP2_REPSTAT_IAE_MASK (0x8U) +#define REP2_REPSTAT_IAE_SHIFT (3U) +#define REP2_REPSTAT_IAE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_IAE_SHIFT)) & REP2_REPSTAT_IAE_MASK) +#define REP2_REPSTAT_FXE_MASK (0x10U) +#define REP2_REPSTAT_FXE_SHIFT (4U) +#define REP2_REPSTAT_FXE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_FXE_SHIFT)) & REP2_REPSTAT_FXE_MASK) +#define REP2_REPSTAT_EME_MASK (0x20U) +#define REP2_REPSTAT_EME_SHIFT (5U) +#define REP2_REPSTAT_EME(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_EME_SHIFT)) & REP2_REPSTAT_EME_MASK) +#define REP2_REPSTAT_BXE_MASK (0x40U) +#define REP2_REPSTAT_BXE_SHIFT (6U) +#define REP2_REPSTAT_BXE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_BXE_SHIFT)) & REP2_REPSTAT_BXE_MASK) +#define REP2_REPSTAT_COFE_MASK (0x80U) +#define REP2_REPSTAT_COFE_SHIFT (7U) +#define REP2_REPSTAT_COFE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_COFE_SHIFT)) & REP2_REPSTAT_COFE_MASK) +#define REP2_REPSTAT_COWE_MASK (0x100U) +#define REP2_REPSTAT_COWE_SHIFT (8U) +#define REP2_REPSTAT_COWE(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_COWE_SHIFT)) & REP2_REPSTAT_COWE_MASK) +#define REP2_REPSTAT_ISA_MASK (0x400U) +#define REP2_REPSTAT_ISA_SHIFT (10U) +#define REP2_REPSTAT_ISA(x) (((uint32_t)(((uint32_t)(x)) << REP2_REPSTAT_ISA_SHIFT)) & REP2_REPSTAT_ISA_MASK) + +/*! @name IR - Instruction Register */ +#define REP2_IR_DREG_MASK (0xFFU) +#define REP2_IR_DREG_SHIFT (0U) +#define REP2_IR_DREG(x) (((uint32_t)(((uint32_t)(x)) << REP2_IR_DREG_SHIFT)) & REP2_IR_DREG_MASK) +#define REP2_IR_OPCODE_MASK (0xF00U) +#define REP2_IR_OPCODE_SHIFT (8U) +#define REP2_IR_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << REP2_IR_OPCODE_SHIFT)) & REP2_IR_OPCODE_MASK) + +/*! @name CTRL - Control Register */ +#define REP2_CTRL_ECCSTATRST_MASK (0x1U) +#define REP2_CTRL_ECCSTATRST_SHIFT (0U) +#define REP2_CTRL_ECCSTATRST(x) (((uint32_t)(((uint32_t)(x)) << REP2_CTRL_ECCSTATRST_SHIFT)) & REP2_CTRL_ECCSTATRST_MASK) +#define REP2_CTRL_ECCGENDIS_MASK (0x4U) +#define REP2_CTRL_ECCGENDIS_SHIFT (2U) +#define REP2_CTRL_ECCGENDIS(x) (((uint32_t)(((uint32_t)(x)) << REP2_CTRL_ECCGENDIS_SHIFT)) & REP2_CTRL_ECCGENDIS_MASK) +#define REP2_CTRL_ECCCHKDIS_MASK (0x8U) +#define REP2_CTRL_ECCCHKDIS_SHIFT (3U) +#define REP2_CTRL_ECCCHKDIS(x) (((uint32_t)(((uint32_t)(x)) << REP2_CTRL_ECCCHKDIS_SHIFT)) & REP2_CTRL_ECCCHKDIS_MASK) +#define REP2_CTRL_BISRWDT_MASK (0x30U) +#define REP2_CTRL_BISRWDT_SHIFT (4U) +#define REP2_CTRL_BISRWDT(x) (((uint32_t)(((uint32_t)(x)) << REP2_CTRL_BISRWDT_SHIFT)) & REP2_CTRL_BISRWDT_MASK) +#define REP2_CTRL_BISRUPDATE_MASK (0x40U) +#define REP2_CTRL_BISRUPDATE_SHIFT (6U) +#define REP2_CTRL_BISRUPDATE(x) (((uint32_t)(((uint32_t)(x)) << REP2_CTRL_BISRUPDATE_SHIFT)) & REP2_CTRL_BISRUPDATE_MASK) +#define REP2_CTRL_LOADSSR_MASK (0x80U) +#define REP2_CTRL_LOADSSR_SHIFT (7U) +#define REP2_CTRL_LOADSSR(x) (((uint32_t)(((uint32_t)(x)) << REP2_CTRL_LOADSSR_SHIFT)) & REP2_CTRL_LOADSSR_MASK) + +/*! @name ECCSTAT - Control Register */ +#define REP2_ECCSTAT_ESE_MASK (0x1U) +#define REP2_ECCSTAT_ESE_SHIFT (0U) +#define REP2_ECCSTAT_ESE(x) (((uint32_t)(((uint32_t)(x)) << REP2_ECCSTAT_ESE_SHIFT)) & REP2_ECCSTAT_ESE_MASK) +#define REP2_ECCSTAT_EME_MASK (0x2U) +#define REP2_ECCSTAT_EME_SHIFT (1U) +#define REP2_ECCSTAT_EME(x) (((uint32_t)(((uint32_t)(x)) << REP2_ECCSTAT_EME_SHIFT)) & REP2_ECCSTAT_EME_MASK) +#define REP2_ECCSTAT_SINGLEERR_MASK (0x3FCU) +#define REP2_ECCSTAT_SINGLEERR_SHIFT (2U) +#define REP2_ECCSTAT_SINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << REP2_ECCSTAT_SINGLEERR_SHIFT)) & REP2_ECCSTAT_SINGLEERR_MASK) +#define REP2_ECCSTAT_MULTIERR_MASK (0x3F0000U) +#define REP2_ECCSTAT_MULTIERR_SHIFT (16U) +#define REP2_ECCSTAT_MULTIERR(x) (((uint32_t)(((uint32_t)(x)) << REP2_ECCSTAT_MULTIERR_SHIFT)) & REP2_ECCSTAT_MULTIERR_MASK) + +/*! @name SSR - Solution Stage Register */ +#define REP2_SSR_DATA_MASK (0x3FFU) +#define REP2_SSR_DATA_SHIFT (0U) +#define REP2_SSR_DATA(x) (((uint32_t)(((uint32_t)(x)) << REP2_SSR_DATA_SHIFT)) & REP2_SSR_DATA_MASK) +#define REP2_SSR_ADDR_MASK (0xFFC00U) +#define REP2_SSR_ADDR_SHIFT (10U) +#define REP2_SSR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << REP2_SSR_ADDR_SHIFT)) & REP2_SSR_ADDR_MASK) +#define REP2_SSR_ECC_MASK (0x7F00000U) +#define REP2_SSR_ECC_SHIFT (20U) +#define REP2_SSR_ECC(x) (((uint32_t)(((uint32_t)(x)) << REP2_SSR_ECC_SHIFT)) & REP2_SSR_ECC_MASK) + +/*! + * @} + */ /* end of group REP2_Register_Masks */ + +/*! @name REP Instruction set */ +#define OPCODE_PROG_STORAGE (0x1) +#define OPCODE_READ_STORAGE (0x2) +#define OPCODE_GET_DATA (0x3) +#define OPCODE_LOAD_DATA (0x4) +#define OPCODE_CLEAR (0x5) +#define OPCODE_COMPARE_DATA (0x6) + +/*! @name REP Data Registers */ +#define DREG_ECID (0x1) +#define DREG_SSR (0x2) + +/* REP2 - Peripheral instance base addresses */ +/** Peripheral REP2 base pointer */ +#define REP2 ((REP2_Type *)REP2_BASE) +/** Array initializer of REP2 peripheral base addresses */ +#define REP2_BASE_ADDRS { REP2_BASE } +/** Array initializer of REP2 peripheral base pointers */ +#define REP2_BASE_PTRS { REP2 } + +/*! + * @} + */ /* end of group REP2_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +#endif /* REP2_H */ + diff --git a/platform/devices/MX8/MX8_smmu.h b/platform/devices/MX8/MX8_smmu.h new file mode 100755 index 0000000..cf1cc44 --- /dev/null +++ b/platform/devices/MX8/MX8_smmu.h @@ -0,0 +1,906 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_SMMU_REGISTERS_H +#define HW_SMMU_REGISTERS_H + +#include "stdint.h" + +#define SMMU_NUM_SMRG 32U +#define SMMU_NUM_CB 32U +#define SMMU_PAGESHIFT 12U + +#define SMMU_PAGESIZE (1U << SMMU_PAGESHIFT) +#define SMMU_PAGEMASK (SMMU_PAGESIZE - 1U) + +#define SMMU_GLOBAL_SIZE (SMMU_NUM_CB * PAGESIZE) +#define SMMU_CB_SIZE SMMU_GLOBAL_SIZE + +#define SMMU_CB_BASE(x) ((uintptr_t)(x) + SMMU_GLOBAL_SIZE) +#define SMMU_CBn_BASE(x, n) (SMMU_CB_BASE(x) + ((n) * PAGESIZE)) + +/******************************************************************************* + * HW_SMMU_SCR0 - Configuration Register 0 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_SCR0 - Configuration Register 0 (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t CLIENTPD : 1; + uint32_t GFRE : 1; + uint32_t GFIE : 1; + uint32_t EXIDENABLE : 1; + uint32_t GCFGFRE : 1; + uint32_t GCFGFIE : 1; + uint32_t TRANSIENTCFG : 2; + uint32_t STALLD : 1; + uint32_t GSE : 1; + uint32_t USFCFG : 1; + uint32_t VMIDPNE : 1; + uint32_t PTM : 1; + uint32_t FB : 1; + uint32_t BSU : 2; + uint32_t MEMATTR : 4; + uint32_t MTCFG : 1; + uint32_t SMCFCFG : 1; + uint32_t SHCFG : 2; + uint32_t RACFG : 2; + uint32_t WACFG : 2; + uint32_t NSCFG : 2; + uint32_t RESERVED0 : 2; + } B; +} hw_smmu_scr0_t; + +/*! + * @name Constants and macros for entire SMMU_SCR0 register + */ +/** @{ */ +#define HW_SMMU_SCR0_ADDR(x) ((uintptr_t)(x) + 0x0U) +#define HW_SMMU_SCR0(x) (*(__IO hw_smmu_scr0_t *) HW_SMMU_SCR0_ADDR(x)) + +#define HW_SMMU_NSCR0_ADDR(x) ((uintptr_t)(x) + 0x400U) +#define HW_SMMU_NSCR0(x) (*(__IO hw_smmu_scr0_t *) HW_SMMU_NSCR0_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SCR1 - Configuration Register 1 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_SCR1 - Configuration Register 1 (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t NSNUMCBO : 8; + uint32_t NSNUMSMRGO : 8; + uint32_t NSNUMIRPTO : 8; + uint32_t GASRAE : 1; + uint32_t GEFRO : 1; + uint32_t SIF : 1; + uint32_t SPMEN : 1; + uint32_t NSCAFRO : 1; + uint32_t RESERVED0 : 3; + } B; +} hw_smmu_scr1_t; + +/*! + * @name Constants and macros for entire SMMU_SCR1 register + */ +/** @{ */ +#define HW_SMMU_SCR1_ADDR(x) ((uintptr_t)(x) + 0x4U) +#define HW_SMMU_SCR1(x) (*(__IO hw_smmu_scr1_t *) HW_SMMU_SCR1_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SCR2 - Configuration Register 2 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_SCR2 - Configuration Register 2 (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t BPVMID : 8; + uint32_t RESERVED0 : 24; + } B; +} hw_smmu_scr2_t; + +/*! + * @name Constants and macros for entire SMMU_SCR2 register + */ +/** @{ */ +#define HW_SMMU_SCR2_ADDR(x) ((uintptr_t)(x) + 0x8U) +#define HW_SMMU_SCR2(x) (*(__IO hw_smmu_scr2_t *) HW_SMMU_SCR2_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SACR - Auxiliary Configuration Register + ******************************************************************************/ + +/*! + * @brief HW_SMMU_SACR - Auxiliary Configuration Register (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t RESERVED0 : 2; + uint32_t S1WC2EN : 1; + uint32_t S2WC2EN : 1; + uint32_t IPA2PA_CEN : 1; + uint32_t RESERVED1 : 3; + uint32_t SMTNMB_TLBEN : 1; + uint32_t MMUDISB_TLBEN : 1; + uint32_t S2CRB_TLBEN : 1; + uint32_t RESERVED2 : 5; + uint32_t PAGESIZE : 1; + uint32_t RESERVED3 : 7; + uint32_t DP4K_TCUDISB : 1; + uint32_t DP4K_TBUDISB : 1; + uint32_t CACHE_LOCK : 1; + uint32_t RESERVED4 : 5; + } B; +} hw_smmu_sacr_t; + +/*! + * @name Constants and macros for entire SMMU_ACR register + */ +/** @{ */ +#define HW_SMMU_SACR_ADDR(x) ((uintptr_t)(x) + 0x10U) +#define HW_SMMU_SACR(x) (*(__IO hw_smmu_sacr_t *) HW_SMMU_SACR_ADDR(x)) + +#define HW_SMMU_NSACR_ADDR(x) ((uintptr_t)(x) + 0x410U) +#define HW_SMMU_NSACR(x) (*(__IO hw_smmu_sacr_t *) HW_SMMU_NSACR_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_IDR0 - Identification Register 0 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_IDR0 - Identification Register 0 (RO) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t NUMSMRG : 8; + uint32_t EXIDS : 1; + uint32_t NUMSIDB : 4; + uint32_t BTM : 1; + uint32_t CTTW : 1; + uint32_t RESERVED0 : 1; + uint32_t NUMIRPT : 8; + uint32_t PTFS : 2; + uint32_t ATOSNS : 1; + uint32_t SMS : 1; + uint32_t NTS : 1; + uint32_t S2TS : 1; + uint32_t S1TS : 1; + uint32_t SES : 1; + } B; +} hw_smmu_idr0_t; + +/*! + * @name Constants and macros for entire SMMU_IDR0 register + */ +/** @{ */ +#define HW_SMMU_IDR0_ADDR(x) ((uintptr_t)(x) + 0x20U) +#define HW_SMMU_IDR0(x) (*(__I hw_smmu_idr0_t *) HW_SMMU_IDR0_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_IDR1 - Identification Register 1 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_IDR1 - Identification Register 1 (RO) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t NUMCB : 8; + uint32_t NUMSSDNDXB : 4; + uint32_t SSDTP : 2; + uint32_t RESERVED0 : 1; + uint32_t SMCD : 1; + uint32_t NUMS2CB : 8; + uint32_t RESERVED1 : 4; + uint32_t NUMPAGENDXB : 3; + uint32_t PAGESIZE : 1; + } B; +} hw_smmu_idr1_t; + +/*! + * @name Constants and macros for entire SMMU_IDR1 register + */ +/** @{ */ +#define HW_SMMU_IDR1_ADDR(x) ((uintptr_t)(x) + 0x24U) +#define HW_SMMU_IDR1(x) (*(__I hw_smmu_idr1_t *) HW_SMMU_IDR1_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_IDR2 - Identification Register 2 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_IDR2 - Identification Register 2 (RO) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t IAS : 4; + uint32_t OAS : 4; + uint32_t UBS : 4; + uint32_t PTFSV8 : 3; + uint32_t RESERVED0 : 17; + } B; +} hw_smmu_idr2_t; + +/*! + * @name Constants and macros for entire SMMU_IDR2 register + */ +/** @{ */ +#define HW_SMMU_IDR2_ADDR(x) ((uintptr_t)(x) + 0x28U) +#define HW_SMMU_IDR2(x) (*(__I hw_smmu_idr2_t *) HW_SMMU_IDR2_ADDR(x)) +/** @} */ + + +/******************************************************************************* + * HW_SMMU_IDR3-6 - Identification Register 3-6 + ******************************************************************************/ + +/*! + * @name Constants and macros for SMMU_IDR3-6 registers + */ +/** @{ */ +#define HW_SMMU_IDR3_ADDR(x) ((uintptr_t)(x) + 0x2CU) +#define HW_SMMU_IDR4_ADDR(x) ((uintptr_t)(x) + 0x30U) +#define HW_SMMU_IDR5_ADDR(x) ((uintptr_t)(x) + 0x34U) +#define HW_SMMU_IDR6_ADDR(x) ((uintptr_t)(x) + 0x38U) +/** @} */ + +/******************************************************************************* + * HW_SMMU_IDR7 - Identification Register 7 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_IDR7 - Identification Register 7 (RO) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t MINOR : 4; + uint32_t MAJOR : 4; + uint32_t RESERVED0 : 24; + } B; +} hw_smmu_idr7_t; + +/*! + * @name Constants and macros for entire SMMU_IDR7 register + */ +/** @{ */ +#define HW_SMMU_IDR7_ADDR(x) ((uintptr_t)(x) + 0x3CU) +#define HW_SMMU_IDR7(x) (*(__I hw_smmu_idr7_t *) HW_SMMU_IDR7_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SGFSR - Global Fault Status Register + ******************************************************************************/ + +/*! + * @brief SGFSR - Global Fault Status Register (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t ICF : 1; + uint32_t USF : 1; + uint32_t SMCF : 1; + uint32_t UCBF : 1; + uint32_t UCIF : 1; + uint32_t CAF : 1; + uint32_t EF : 1; + uint32_t PF : 1; + uint32_t UUT : 1; + uint32_t RESERVED0 : 22; + uint32_t MULTI : 1; + } B; +} hw_smmu_sgfsr_t; + +/*! + * @name Constants and macros for entire SMMU_SGFSR register + */ +/** @{ */ +#define HW_SMMU_SGFSR_ADDR(x) ((uintptr_t)(x) + 0x48U) +#define HW_SMMU_SGFSR(x) (*(__IO hw_smmu_sgfsr_t *) HW_SMMU_SGFSR_ADDR(x)) + +#define HW_SMMU_NSGFSR_ADDR(x) ((uintptr_t)(x) + 0x448U) +#define HW_SMMU_NSGFSR(x) (*(__IO hw_smmu_sgfsr_t *) HW_SMMU_NSGFSR_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SGFSYNR0 - Global Fault Syndrome Register 0 + ******************************************************************************/ + +/*! + * @brief SGFSYNR0 - Global Fault Syndrome Register 0 (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t NESTED : 1; + uint32_t WNR : 1; + uint32_t PNU : 1; + uint32_t IND : 1; + uint32_t NSSTATE : 1; + uint32_t NSATTR : 1; + uint32_t ATS : 1; + uint32_t RESERVED0 : 25; + } B; +} hw_smmu_sgfsynr0_t; + +/*! + * @name Constants and macros for entire SMMU_SGFSYNR0 register + */ +/** @{ */ +#define HW_SMMU_SGFSYNR0_ADDR(x) ((uintptr_t)(x) + 0x50U) +#define HW_SMMU_SGFSYNR0(x) (*(__IO hw_smmu_sgfsynr0_t *) HW_SMMU_SGFSYNR0_ADDR(x)) + +#define HW_SMMU_NSGFSYNR0_ADDR(x) ((uintptr_t)(x) + 0x450U) +#define HW_SMMU_NSGFSYNR0(x) (*(__IO hw_smmu_sgfsynr0_t *) HW_SMMU_NSGFSYNR0_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SGFSYNR1 - Global Fault Syndrome Register 1 + ******************************************************************************/ + +/*! + * @brief SGFSYNR1 - Global Fault Syndrome Register 1 (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t SID : 16; + uint32_t SSD : 16; + } B; +} hw_smmu_sgfsynr1_t; + +/*! + * @name Constants and macros for entire SMMU_SGFSYNR1 register + */ +/** @{ */ +#define HW_SMMU_SGFSYNR1_ADDR(x) ((uintptr_t)(x) + 0x54U) +#define HW_SMMU_SGFSYNR1(x) (*(__IO hw_smmu_sgfsynr1_t *) HW_SMMU_SGFSYNR1_ADDR(x)) + +#define HW_SMMU_NSGFSYNR1_ADDR(x) ((uintptr_t)(x) + 0x454U) +#define HW_SMMU_NSGFSYNR1(x) (*(__IO hw_smmu_sgfsynr1_t *) HW_SMMU_NSGFSYNR1_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_SGFSYNR2 - Global Fault Syndrome Register 2 + ******************************************************************************/ + +/*! + * @name Constants and macros for entire SMMU_SGFSYNR2 register + */ +/** @{ */ +#define HW_SMMU_SGFSYNR2_ADDR(x) ((uintptr_t)(x) + 0x58U) +#define HW_SMMU_SGFSYNR2(x) (*(__IO uint32_t *) HW_SMMU_SGFSYNR2_ADDR(x)) + +#define HW_SMMU_NSGFSYNR2_ADDR(x) ((uintptr_t)(x) + 0x458U) +#define HW_SMMU_NSGFSYNR2(x) (*(__IO uint32_t *) HW_SMMU_NSGFSYNR2_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_STLBIALL - TLB Invalidate All + ******************************************************************************/ + +/*! + * @name Constants and macros for entire SMMU_STLBIALL register + */ +/** @{ */ +#define HW_SMMU_STLBIALL_ADDR(x) ((uintptr_t)(x) + 0x60U) +#define HW_SMMU_STLBIALL(x) (*(__O uint32_t *) HW_SMMU_STLBIALL_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_TLBIVMID - TLB Invalidate by VMID + ******************************************************************************/ + +/*! + * @brief TLBIVMID - TLB Invalidate by VMID (WO) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t VMID : 8; + uint32_t RESERVED0 : 24; + } B; +} hw_smmu_tlbivmid_t; + +/*! + * @name Constants and macros for entire SMMU_TLBIVMID register + */ +/** @{ */ +#define HW_SMMU_TLBIVMID_ADDR(x) ((uintptr_t)(x) + 0x64U) +#define HW_SMMU_TLBIVMID(x) (*(__O hw_smmu_sgfsynr1_t *) HW_SMMU_TLBIVMID_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_TLBIALLNSNH - TLB Invalidate All Non-Secure Non-Hyp + ******************************************************************************/ + +/*! + * @name Constants and macros for entire SMMU_TLBIALLNSNH register + */ +/** @{ */ +#define HW_SMMU_TLBIALLNSNH_ADDR(x) ((uintptr_t)(x) + 0x68U) +#define HW_SMMU_TLBIALLNSNH(x) (*(__O uint32_t *) HW_SMMU_TLBIALLNSNH_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_TLBIALLNSNH - TLB Invalidate All Hyp + ******************************************************************************/ + +/*! + * @name Constants and macros for entire SMMU_TLBIALLH register + */ +/** @{ */ +#define HW_SMMU_TLBIALLH_ADDR(x) ((uintptr_t)(x) + 0x6CU) +#define HW_SMMU_TLBIALLH(x) (*(__O uint32_t *) HW_SMMU_TLBIALLH_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_STLBGSYNC - Global Synchronize TLB Invalidate + ******************************************************************************/ + +/*! + * @name Constants and macros for entire SMMU_STLBGSYNC register + */ +/** @{ */ +#define HW_SMMU_STLBGSYNC_ADDR(x) ((uintptr_t)(x) + 0x70U) +#define HW_SMMU_STLBGSYNC(x) (*(__O uint32_t *) HW_SMMU_STLBGSYNC_ADDR(x)) + +#define HW_SMMU_NSTLBGSYNC_ADDR(x) ((uintptr_t)(x) + 0x470U) +#define HW_SMMU_NSTLBGSYNC(x) (*(__O uint32_t *) HW_SMMU_NSTLBGSYNC_ADDR(x)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_STLBGSTATUS - Global TLB Status register + ******************************************************************************/ + +/*! + * @brief STLBGSTATUS - Global TLB Status register (RO) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t GSACTIVE : 1; + uint32_t RESERVED0 : 31; + } B; +} hw_smmu_stlbgstatus; + +/*! + * @name Constants and macros for entire STLBGSTATUS register + */ +/** @{ */ +#define HW_SMMU_STLBGSTATUS_ADDR(x) ((uintptr_t)(x) + 0x74U) +#define HW_SMMU_STLBGSTATUS(x) (*(__I _hw_smmu_stlbgstatus *) HW_SMMU_STLBGSTATUS_ADDR(x)) + +#define HW_SMMU_NSTLBGSTATUS_ADDR(x) ((uintptr_t)(x) + 0x474U) +#define HW_SMMU_NSTLBGSTATUS(x) (*(__I _hw_smmu_stlbgstatus *) HW_SMMU_NSTLBGSTATUS_ADDR(x)) +/** @} */ + + +/******************************************************************************* + * HW_SMMU_SMR - Stream Match Register + ******************************************************************************/ + +/*! + * @brief HW_SMMU_SMR - Stream Match Register (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t ID : 15; + uint32_t RESERVED0 : 1; + uint32_t MASK : 15; + uint32_t VALID : 1; + } B1; + struct + { + uint32_t EXID : 16; + uint32_t EXMASK : 16; + } B2; +} hw_smmu_smr_t; + +/*! + * @name Constants and macros for entire SMMU_SMR register + */ +/** @{ */ +#define HW_SMMU_SMR_ADDR(x, n) ((uintptr_t)(x) + 0x800U + (0x4U * (n))) +#define HW_SMMU_SMR(x, n) (*(__IO hw_smmu_smr_t *) HW_SMMU_SMR_ADDR(x, n)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_S2CR - Stream-to-Context Register + ******************************************************************************/ + +/*! + * @brief HW_SMMU_S2CR - Stream-to-Context Register (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t CBNDX : 8; + uint32_t SHCFG : 2; + uint32_t EXIDVALID : 1; + uint32_t MTCFG : 1; + uint32_t MEMATTR : 4; + uint32_t TYPE : 2; + uint32_t NSCFG : 2; + uint32_t RACFG : 2; + uint32_t WACFG : 2; + uint32_t PRIVCFG : 2; + uint32_t INSTCFG : 2; + uint32_t TRANSIENTCFG : 2; + uint32_t RESERVED0 : 2; + } B0; + struct + { + uint32_t VMID : 8; + uint32_t SHCFG : 2; + uint32_t EXIDVALID : 1; + uint32_t MTCFG : 1; + uint32_t MEMATTR : 4; + uint32_t TYPE : 2; + uint32_t NSCFG : 2; + uint32_t RACFG : 2; + uint32_t WACFG : 2; + uint32_t BSU : 2; + uint32_t FB : 1; + uint32_t RESERVED0 : 1; + uint32_t TRANSIENTCFG : 2; + uint32_t RESERVED1 : 2; + } B1; + struct + { + uint32_t RESERVED0 : 16; + uint32_t TYPE : 2; + uint32_t RESERVED1 : 14; + } B2; +} hw_smmu_s2cr_t; + +/*! + * @name Constants and macros for entire SMMU_S2CR register + */ +/** @{ */ +#define HW_SMMU_S2CR_ADDR(x, n) ((uintptr_t)(x) + 0xC00U + (0x4U * (n))) +#define HW_SMMU_S2CR(x, n) (*(__IO hw_smmu_s2cr_t *) HW_SMMU_S2CR_ADDR(x, n)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_CBAR - Stream-to-Context Register + ******************************************************************************/ + +/*! + * @brief HW_SMMU_CBAR - Context Bank Attribute Register (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t VMID : 8; + uint32_t RESERVED0 : 8; + uint32_t TYPE : 2; + uint32_t SBZ : 2; + uint32_t RESERVED1 : 4; + uint32_t IRPTNDX : 8; + } B0; + struct + { + uint32_t VMID : 8; + uint32_t BPSHCFG : 2; + uint32_t HYPC : 1; + uint32_t FB : 1; + uint32_t MEMATTR : 4; + uint32_t TYPE : 2; + uint32_t BSU : 2; + uint32_t RACFG : 2; + uint32_t WACFG : 2; + uint32_t IRPTNDX : 8; + } B1; + struct + { + uint32_t VMID : 8; + uint32_t RESERVED0 : 8; + uint32_t TYPE : 2; + uint32_t SBZ : 2; + uint32_t RESERVED1 : 4; + uint32_t IRPTNDX : 8; + } B2; + struct + { + uint32_t VMID : 8; + uint32_t CBNDX : 8; + uint32_t TYPE : 2; + uint32_t SBZ : 2; + uint32_t RESERVED0 : 4; + uint32_t IRPTNDX : 8; + } B3; +} hw_smmu_cbar_t; + +/*! + * @name Constants and macros for entire SMMU_CBAR register + */ +/** @{ */ +#define HW_SMMU_CBAR_ADDR(x, n) ((uintptr_t)(x) + 0x10000U + (0x4U * (n))) +#define HW_SMMU_CBAR(x, n) (*(__IO hw_smmu_cbar_t *) HW_SMMU_CBAR_ADDR(x, n)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_CBFRSYNRA - Context Bank Fault Restricted Syndrome Register A + ******************************************************************************/ + +/*! + * @brief CBFRSYNRA - Context Bank Fault Restricted Syndrome Register A (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t SID : 16; + uint32_t SSD : 16; + } B; +} hw_smmu_cbfrsynra_t; + +/*! + * @name Constants and macros for entire SMMU_CBFRSYNRA register + */ +/** @{ */ +#define HW_SMMU_CBFRSYNRA_ADDR(x, n) ((uintptr_t)(x) + 0x10400U + (0x4U * (n))) +#define HW_SMMU_CBFRSYNRA(x, n) (*(__IO hw_smmu_cbfrsynra_t *) HW_SMMU_CBFRSYNRA_ADDR(x, n)) +/** @} */ + +/******************************************************************************* + * HW_SMMU_CBA2R - Stream-to-Context Register 2 + ******************************************************************************/ + +/*! + * @brief HW_SMMU_CBA2R - Context Bank Attribute Register 2 (RW) + * + */ +typedef union +{ + uint32_t U; + struct + { + uint32_t VA64 : 1; + uint32_t MONC : 1; + uint32_t RESERVED0 : 30; + } B; +} hw_smmu_cba2r_t; + +/*! + * @name Constants and macros for entire SMMU_CBA2R register + */ +/** @{ */ +#define HW_SMMU_CBA2R_ADDR(x, n) ((uintptr_t)(x) + 0x10800U + (0x4U * (n))) +#define HW_SMMU_CBA2R(x, n) (*(__IO hw_smmu_cba2r_t *) HW_SMMU_CBA2R_ADDR(x, n)) +/** @} */ + +/******************************************************************************* + * hw_smmu_t - module struct + ******************************************************************************/ +/*! + * @brief All SMMU module registers. + */ +#pragma pack(1) +typedef struct +{ + /* GR0 - 64K */ + __IO hw_smmu_scr0_t SCR0; + __IO hw_smmu_scr0_t SCR1; + __IO hw_smmu_scr0_t SCR2; + uint32_t _reserved0; + __IO hw_smmu_sacr_t SACR; + uint32_t _reserved1[3]; + __I hw_smmu_idr0_t IDR0; + __I hw_smmu_idr1_t IDR1; + __I hw_smmu_idr2_t IDR2; + __I uint32_t IDR3; + __I uint32_t IDR4; + __I uint32_t IDR5; + __I uint32_t IDR6; + __I hw_smmu_idr7_t IDR7; + __IO uint32_t SGFAR[2]; + __IO hw_smmu_sgfsr_t SGFSR; + __O uint32_t SFSRRESTORE; + __IO hw_smmu_sgfsynr0_t SGFSYNR0; + __IO hw_smmu_sgfsynr1_t SGFSYNR1; + __IO uint32_t SGFSYNR2; + uint32_t _reserved2; + __O uint32_t STLBIALL; + __O hw_smmu_tlbivmid_t TLBIVMID; + __O uint32_t TLBIALLNSNH; + __O uint32_t TLBIALLH; + __O uint32_t STLBGSYNC; + __I hw_smmu_stlbgstatus STLBGSTATUS; + __O uint32_t TLBIVAH[2]; + __IO uint32_t DBGRPTRTBU; + __I uint32_t DBGRDATATBU; + __IO uint32_t DBGRPTRTCU; + __I uint32_t DBGRDATATCU; + uint32_t _reserved3[4]; + __O uint32_t STLBIVALM[2]; + __O uint32_t STLBIVAM[2]; + __O uint32_t TLBIVALH64[2]; + __O uint32_t TLBIVMIDS1; + __O uint32_t STLBIALLM; + __O uint32_t TLBIVAH64[2]; + uint32_t _reserved4[14]; + __O uint32_t SGATS1UR[2]; + __O uint32_t SGATS1UW[2]; + __O uint32_t SGATS1PR[2]; + __O uint32_t SGATS1PW[2]; + __O uint32_t SGATS12UR[2]; + __O uint32_t SGATS12UW[2]; + __O uint32_t SGATS12PR[2]; + __O uint32_t SGATS12PW[2]; + uint32_t _reserved5[16]; + __IO uint32_t SGPAR[2]; + __IO uint32_t SGATSR; + uint32_t _reserved6[157]; + __IO hw_smmu_scr0_t NSCR0; + uint32_t _reserved7; + __IO hw_smmu_scr2_t NSCR2; + uint32_t _reserved8; + __IO hw_smmu_sacr_t NSACR; + uint32_t _reserved9[11]; + __IO uint32_t NSGFAR[2]; + __IO hw_smmu_sgfsr_t NSGFSR; + __O uint32_t NSGFSRRESTORE; + __IO hw_smmu_sgfsynr0_t NSGFSYNR0; + __IO hw_smmu_sgfsynr1_t NSGFSYNR1; + __IO uint32_t NSGFSYNR2; + uint32_t _reserved10[5]; + __O uint32_t NSTLBGSYNC; + __I hw_smmu_stlbgstatus NSTLBGSTATUS; + uint32_t _reserved11[34]; + __O uint32_t NSGATS1UR[2]; + __O uint32_t NSGATS1UW[2]; + __O uint32_t NSGATS1PR[2]; + __O uint32_t NSGATS1PW[2]; + __O uint32_t NSGATS12UR[2]; + __O uint32_t NSGATS12UW[2]; + __O uint32_t NSGATS12PR[2]; + __O uint32_t NSGATS12PW[2]; + uint32_t _reserved12[16]; + __IO uint32_t NSGPAR[2]; + __IO uint32_t NSGATSR; + uint32_t _reserved13[157]; + __IO hw_smmu_smr_t SMR[128]; + uint32_t _reserved14[128]; + __IO hw_smmu_s2cr_t S2CR[128]; + uint32_t _reserved15[128]; + uint8_t _reserved16[SMMU_PAGESIZE - 4096]; + /* GR 1 - 64K */ + __IO hw_smmu_cbar_t CBAR[128]; + uint32_t _reserved20[128]; + hw_smmu_cbfrsynra_t CBFRSYNRA[128]; + uint32_t _reserved21[128]; + __IO hw_smmu_cba2r_t CBA2R[128]; + uint32_t _reserved22[384]; + uint8_t _reserved23[SMMU_PAGESIZE - 4096]; + /* Blank Global */ + uint8_t _reserved30[SMMU_NUM_CB - 2][SMMU_PAGESIZE]; + /* CB */ + uint8_t _reserved40[SMMU_NUM_CB][SMMU_PAGESIZE]; +} hw_smmu_t; +#pragma pack() + +/*! @brief Macro to access all SMMU registers. */ +/*! @param x SMMU module instance base address. */ +/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, + * use the '&' operator, like &HW_SMMU(SMMU0_BASE). */ +#define HW_SMMU(x) (*(hw_smmu_t *)(x)) + +#define SMMU0 ((hw_smmu_t*) SMMU0_BASE) + +#endif /* HW_SMMU_REGISTERS_H */ + diff --git a/platform/devices/MX8/MX8_snvs.h b/platform/devices/MX8/MX8_snvs.h new file mode 100755 index 0000000..07bf344 --- /dev/null +++ b/platform/devices/MX8/MX8_snvs.h @@ -0,0 +1,857 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2018 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_SNVS_REGISTERS_H +#define HW_SNVS_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + __IO uint32_t LPTGFCR; /**< SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44 */ + __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + __IO uint32_t LPTDC2R; /**< SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0 */ + __IO uint32_t LPTDSR; /**< SNVS_LP Tamper Detectors Status Register, offset: 0xA4 */ + __IO uint32_t LPTGF1CR; /**< SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8 */ + __IO uint32_t LPTGF2CR; /**< SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC */ + uint8_t RESERVED_1[80]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_2[2776]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) +#define SNVS_HPLR_LPTGFCR_SL_MASK (0x80U) +#define SNVS_HPLR_LPTGFCR_SL_SHIFT (7U) +#define SNVS_HPLR_LPTGFCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK) +#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) +#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) + +/*! @name HPCOMR - SNVS_HP Command Register */ +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) + +/*! @name HPCR - SNVS_HP Control Register */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) + +/*! @name HPSR - SNVS_HP Status Register */ +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) +#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U) +#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U) +#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK) +#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U) +#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U) +#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK) +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) + +/*! @name LPLR - SNVS_LP Lock Register */ +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) +#define SNVS_LPLR_LPTGFCR_HL_MASK (0x80U) +#define SNVS_LPLR_LPTGFCR_HL_SHIFT (7U) +#define SNVS_LPLR_LPTGFCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK) +#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) +#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) + +/*! @name LPCR - SNVS_LP Control Register */ +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) + +/*! @name LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register */ +#define SNVS_LPTGFCR_WMTGF_MASK (0x1FU) +#define SNVS_LPTGFCR_WMTGF_SHIFT (0U) +#define SNVS_LPTGFCR_WMTGF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK) +#define SNVS_LPTGFCR_WMTGF_EN_MASK (0x80U) +#define SNVS_LPTGFCR_WMTGF_EN_SHIFT (7U) +#define SNVS_LPTGFCR_WMTGF_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK) +#define SNVS_LPTGFCR_ETGF1_MASK (0x7F0000U) +#define SNVS_LPTGFCR_ETGF1_SHIFT (16U) +#define SNVS_LPTGFCR_ETGF1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK) +#define SNVS_LPTGFCR_ETGF1_EN_MASK (0x800000U) +#define SNVS_LPTGFCR_ETGF1_EN_SHIFT (23U) +#define SNVS_LPTGFCR_ETGF1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK) +#define SNVS_LPTGFCR_ETGF2_MASK (0x7F000000U) +#define SNVS_LPTGFCR_ETGF2_SHIFT (24U) +#define SNVS_LPTGFCR_ETGF2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK) +#define SNVS_LPTGFCR_ETGF2_EN_MASK (0x80000000U) +#define SNVS_LPTGFCR_ETGF2_EN_SHIFT (31U) +#define SNVS_LPTGFCR_ETGF2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK) + +/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) +#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) +#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) +#define SNVS_LPTDCR_CT_EN_MASK (0x10U) +#define SNVS_LPTDCR_CT_EN_SHIFT (4U) +#define SNVS_LPTDCR_CT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK) +#define SNVS_LPTDCR_TT_EN_MASK (0x20U) +#define SNVS_LPTDCR_TT_EN_SHIFT (5U) +#define SNVS_LPTDCR_TT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK) +#define SNVS_LPTDCR_VT_EN_MASK (0x40U) +#define SNVS_LPTDCR_VT_EN_SHIFT (6U) +#define SNVS_LPTDCR_VT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK) +#define SNVS_LPTDCR_WMT1_EN_MASK (0x80U) +#define SNVS_LPTDCR_WMT1_EN_SHIFT (7U) +#define SNVS_LPTDCR_WMT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK) +#define SNVS_LPTDCR_WMT2_EN_MASK (0x100U) +#define SNVS_LPTDCR_WMT2_EN_SHIFT (8U) +#define SNVS_LPTDCR_WMT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK) +#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) +#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) +#define SNVS_LPTDCR_ET2_EN_MASK (0x400U) +#define SNVS_LPTDCR_ET2_EN_SHIFT (10U) +#define SNVS_LPTDCR_ET2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK) +#define SNVS_LPTDCR_ET1P_MASK (0x800U) +#define SNVS_LPTDCR_ET1P_SHIFT (11U) +#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) +#define SNVS_LPTDCR_ET2P_MASK (0x1000U) +#define SNVS_LPTDCR_ET2P_SHIFT (12U) +#define SNVS_LPTDCR_ET2P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK) +#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) +#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) +#define SNVS_LPTDCR_LTDC_MASK (0x70000U) +#define SNVS_LPTDCR_LTDC_SHIFT (16U) +#define SNVS_LPTDCR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK) +#define SNVS_LPTDCR_HTDC_MASK (0x700000U) +#define SNVS_LPTDCR_HTDC_SHIFT (20U) +#define SNVS_LPTDCR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK) +#define SNVS_LPTDCR_VRC_MASK (0x7000000U) +#define SNVS_LPTDCR_VRC_SHIFT (24U) +#define SNVS_LPTDCR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK) +#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) +#define SNVS_LPTDCR_OSCB_SHIFT (28U) +#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) + +/*! @name LPSR - SNVS_LP Status Register */ +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) +#define SNVS_LPSR_CTD_MASK (0x10U) +#define SNVS_LPSR_CTD_SHIFT (4U) +#define SNVS_LPSR_CTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK) +#define SNVS_LPSR_TTD_MASK (0x20U) +#define SNVS_LPSR_TTD_SHIFT (5U) +#define SNVS_LPSR_TTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK) +#define SNVS_LPSR_VTD_MASK (0x40U) +#define SNVS_LPSR_VTD_SHIFT (6U) +#define SNVS_LPSR_VTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK) +#define SNVS_LPSR_WMT1D_MASK (0x80U) +#define SNVS_LPSR_WMT1D_SHIFT (7U) +#define SNVS_LPSR_WMT1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK) +#define SNVS_LPSR_WMT2D_MASK (0x100U) +#define SNVS_LPSR_WMT2D_SHIFT (8U) +#define SNVS_LPSR_WMT2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK) +#define SNVS_LPSR_ET1D_MASK (0x200U) +#define SNVS_LPSR_ET1D_SHIFT (9U) +#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) +#define SNVS_LPSR_ET2D_MASK (0x400U) +#define SNVS_LPSR_ET2D_SHIFT (10U) +#define SNVS_LPSR_ET2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK) +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) +#define SNVS_LPSR_SED_MASK (0x100000U) +#define SNVS_LPSR_SED_SHIFT (20U) +#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register */ +#define SNVS_LPTDC2R_ET3_EN_MASK (0x1U) +#define SNVS_LPTDC2R_ET3_EN_SHIFT (0U) +#define SNVS_LPTDC2R_ET3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK) +#define SNVS_LPTDC2R_ET4_EN_MASK (0x2U) +#define SNVS_LPTDC2R_ET4_EN_SHIFT (1U) +#define SNVS_LPTDC2R_ET4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK) +#define SNVS_LPTDC2R_ET5_EN_MASK (0x4U) +#define SNVS_LPTDC2R_ET5_EN_SHIFT (2U) +#define SNVS_LPTDC2R_ET5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK) +#define SNVS_LPTDC2R_ET6_EN_MASK (0x8U) +#define SNVS_LPTDC2R_ET6_EN_SHIFT (3U) +#define SNVS_LPTDC2R_ET6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK) +#define SNVS_LPTDC2R_ET7_EN_MASK (0x10U) +#define SNVS_LPTDC2R_ET7_EN_SHIFT (4U) +#define SNVS_LPTDC2R_ET7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK) +#define SNVS_LPTDC2R_ET8_EN_MASK (0x20U) +#define SNVS_LPTDC2R_ET8_EN_SHIFT (5U) +#define SNVS_LPTDC2R_ET8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK) +#define SNVS_LPTDC2R_ET9_EN_MASK (0x40U) +#define SNVS_LPTDC2R_ET9_EN_SHIFT (6U) +#define SNVS_LPTDC2R_ET9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK) +#define SNVS_LPTDC2R_ET10_EN_MASK (0x80U) +#define SNVS_LPTDC2R_ET10_EN_SHIFT (7U) +#define SNVS_LPTDC2R_ET10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK) +#define SNVS_LPTDC2R_ET3P_MASK (0x10000U) +#define SNVS_LPTDC2R_ET3P_SHIFT (16U) +#define SNVS_LPTDC2R_ET3P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK) +#define SNVS_LPTDC2R_ET4P_MASK (0x20000U) +#define SNVS_LPTDC2R_ET4P_SHIFT (17U) +#define SNVS_LPTDC2R_ET4P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK) +#define SNVS_LPTDC2R_ET5P_MASK (0x40000U) +#define SNVS_LPTDC2R_ET5P_SHIFT (18U) +#define SNVS_LPTDC2R_ET5P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK) +#define SNVS_LPTDC2R_ET6P_MASK (0x80000U) +#define SNVS_LPTDC2R_ET6P_SHIFT (19U) +#define SNVS_LPTDC2R_ET6P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK) +#define SNVS_LPTDC2R_ET7P_MASK (0x100000U) +#define SNVS_LPTDC2R_ET7P_SHIFT (20U) +#define SNVS_LPTDC2R_ET7P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK) +#define SNVS_LPTDC2R_ET8P_MASK (0x200000U) +#define SNVS_LPTDC2R_ET8P_SHIFT (21U) +#define SNVS_LPTDC2R_ET8P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK) +#define SNVS_LPTDC2R_ET9P_MASK (0x400000U) +#define SNVS_LPTDC2R_ET9P_SHIFT (22U) +#define SNVS_LPTDC2R_ET9P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK) +#define SNVS_LPTDC2R_ET10P_MASK (0x800000U) +#define SNVS_LPTDC2R_ET10P_SHIFT (23U) +#define SNVS_LPTDC2R_ET10P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK) + +/*! @name LPTDSR - SNVS_LP Tamper Detectors Status Register */ +#define SNVS_LPTDSR_ET3D_MASK (0x1U) +#define SNVS_LPTDSR_ET3D_SHIFT (0U) +#define SNVS_LPTDSR_ET3D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK) +#define SNVS_LPTDSR_ET4D_MASK (0x2U) +#define SNVS_LPTDSR_ET4D_SHIFT (1U) +#define SNVS_LPTDSR_ET4D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK) +#define SNVS_LPTDSR_ET5D_MASK (0x4U) +#define SNVS_LPTDSR_ET5D_SHIFT (2U) +#define SNVS_LPTDSR_ET5D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK) +#define SNVS_LPTDSR_ET6D_MASK (0x8U) +#define SNVS_LPTDSR_ET6D_SHIFT (3U) +#define SNVS_LPTDSR_ET6D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK) +#define SNVS_LPTDSR_ET7D_MASK (0x10U) +#define SNVS_LPTDSR_ET7D_SHIFT (4U) +#define SNVS_LPTDSR_ET7D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK) +#define SNVS_LPTDSR_ET8D_MASK (0x20U) +#define SNVS_LPTDSR_ET8D_SHIFT (5U) +#define SNVS_LPTDSR_ET8D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK) +#define SNVS_LPTDSR_ET9D_MASK (0x40U) +#define SNVS_LPTDSR_ET9D_SHIFT (6U) +#define SNVS_LPTDSR_ET9D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK) +#define SNVS_LPTDSR_ET10D_MASK (0x80U) +#define SNVS_LPTDSR_ET10D_SHIFT (7U) +#define SNVS_LPTDSR_ET10D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK) + +/*! @name LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register */ +#define SNVS_LPTGF1CR_ETGF3_MASK (0x7FU) +#define SNVS_LPTGF1CR_ETGF3_SHIFT (0U) +#define SNVS_LPTGF1CR_ETGF3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK) +#define SNVS_LPTGF1CR_ETGF3_EN_MASK (0x80U) +#define SNVS_LPTGF1CR_ETGF3_EN_SHIFT (7U) +#define SNVS_LPTGF1CR_ETGF3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK) +#define SNVS_LPTGF1CR_ETGF4_MASK (0x7F00U) +#define SNVS_LPTGF1CR_ETGF4_SHIFT (8U) +#define SNVS_LPTGF1CR_ETGF4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK) +#define SNVS_LPTGF1CR_ETGF4_EN_MASK (0x8000U) +#define SNVS_LPTGF1CR_ETGF4_EN_SHIFT (15U) +#define SNVS_LPTGF1CR_ETGF4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK) +#define SNVS_LPTGF1CR_ETGF5_MASK (0x7F0000U) +#define SNVS_LPTGF1CR_ETGF5_SHIFT (16U) +#define SNVS_LPTGF1CR_ETGF5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK) +#define SNVS_LPTGF1CR_ETGF5_EN_MASK (0x800000U) +#define SNVS_LPTGF1CR_ETGF5_EN_SHIFT (23U) +#define SNVS_LPTGF1CR_ETGF5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK) +#define SNVS_LPTGF1CR_ETGF6_MASK (0x7F000000U) +#define SNVS_LPTGF1CR_ETGF6_SHIFT (24U) +#define SNVS_LPTGF1CR_ETGF6(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK) +#define SNVS_LPTGF1CR_ETGF6_EN_MASK (0x80000000U) +#define SNVS_LPTGF1CR_ETGF6_EN_SHIFT (31U) +#define SNVS_LPTGF1CR_ETGF6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK) + +/*! @name LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register */ +#define SNVS_LPTGF2CR_ETGF7_MASK (0x7FU) +#define SNVS_LPTGF2CR_ETGF7_SHIFT (0U) +#define SNVS_LPTGF2CR_ETGF7(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK) +#define SNVS_LPTGF2CR_ETGF7_EN_MASK (0x80U) +#define SNVS_LPTGF2CR_ETGF7_EN_SHIFT (7U) +#define SNVS_LPTGF2CR_ETGF7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK) +#define SNVS_LPTGF2CR_ETGF8_MASK (0x7F00U) +#define SNVS_LPTGF2CR_ETGF8_SHIFT (8U) +#define SNVS_LPTGF2CR_ETGF8(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK) +#define SNVS_LPTGF2CR_ETGF8_EN_MASK (0x8000U) +#define SNVS_LPTGF2CR_ETGF8_EN_SHIFT (15U) +#define SNVS_LPTGF2CR_ETGF8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK) +#define SNVS_LPTGF2CR_ETGF9_MASK (0x7F0000U) +#define SNVS_LPTGF2CR_ETGF9_SHIFT (16U) +#define SNVS_LPTGF2CR_ETGF9(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK) +#define SNVS_LPTGF2CR_ETGF9_EN_MASK (0x800000U) +#define SNVS_LPTGF2CR_ETGF9_EN_SHIFT (23U) +#define SNVS_LPTGF2CR_ETGF9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK) +#define SNVS_LPTGF2CR_ETGF10_MASK (0x7F000000U) +#define SNVS_LPTGF2CR_ETGF10_SHIFT (24U) +#define SNVS_LPTGF2CR_ETGF10(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK) +#define SNVS_LPTGF2CR_ETGF10_EN_MASK (0x80000000U) +#define SNVS_LPTGF2CR_ETGF10_EN_SHIFT (31U) +#define SNVS_LPTGF2CR_ETGF10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (8U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +#endif /* HW_SNVS_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_stc.h b/platform/devices/MX8/MX8_stc.h new file mode 100755 index 0000000..f98793f --- /dev/null +++ b/platform/devices/MX8/MX8_stc.h @@ -0,0 +1,385 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file stc.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for stc + * + * CMSIS Peripheral Access Layer for stc + */ + +#ifndef STC_H +#define STC_H /**< Symbol preventing repeated inclusion */ + + +/* ---------------------------------------------------------------------------- + -- STC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup STC_Peripheral_Access_Layer STC Peripheral Access Layer + * @{ + */ + +/** STC - Register Layout Typedef */ +typedef struct { + __IO uint32_t INTERLEAVE_SEL; /**< Interleave Select, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __I uint32_t RVSD_HPR_ENABLE; /**< Highest Priority Request scheduler enable, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t UD_ENABLE; /**< Underrun Detection Enable, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TDM_ENABLE; /**< TDM Function Enable, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t TDM_ALWAYS_ALLOW; /**< TDM Always Allow, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t GLB_CSCHED_WAIT_COUNT; /**< Global Completion Scheduler Wait Count, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t MASK_ID[8]; /**< MASK for the AxID Hash Function, array offset: 0x60, array step: 0x4 */ + __IO uint32_t COMPARE_ID[8]; /**< COMPARE ID for the AxID Hash Function, array offset: 0x80, array step: 0x4 */ + __IO uint32_t MIN_QOS[8]; /**< Minimum QoS Clamp, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t MAX_QOS[8]; /**< Maximum QOS Clamp, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[32]; + __IO uint32_t PANIC_QOS_OFFSET[8]; /**< Panic QoS Offset value, array offset: 0x100, array step: 0x4 */ + __IO uint32_t HPR_QOS_OFFSET[8]; /**< Highest Priority QoS Offset value, array offset: 0x120, array step: 0x4 */ + __IO uint32_t UD_QOS_OFFSET[8]; /**< Underrun Detect QoS Offset value, array offset: 0x140, array step: 0x4 */ + __IO uint32_t UD_COUNT_DECR_VALUE[8]; /**< Decrement value of under run counter., array offset: 0x160, array step: 0x4 */ + __IO uint32_t UD_COUNT_THRESH_1[8]; /**< Underrun counter threshold 1, array offset: 0x180, array step: 0x4 */ + uint8_t RESERVED_7[96]; + __IO uint32_t UD_COUNT_THRESH_2[8]; /**< Underrun counter threshold 2, array offset: 0x200, array step: 0x4 */ + __IO uint32_t CSCHED_WAIT_COUNT[8]; /**< Category Completion Scheduler wait count for completion returns, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_8[32]; + __IO uint32_t TDM_QOS_OFFSET[8]; /**< TDM QoS OFFSET, array offset: 0x260, array step: 0x4 */ + uint8_t RESERVED_9[128]; + __IO uint32_t TDM_START0_COUNT[8]; /**< Time Division Multiplexed Start0 count, array offset: 0x300, array step: 0x4 */ + __IO uint32_t TDM_STOP0_COUNT[8]; /**< Time Division Multiplexed stop0 count, array offset: 0x320, array step: 0x4 */ + __IO uint32_t TDM_START1_COUNT[8]; /**< Time Division Multiplexed start1 count, array offset: 0x340, array step: 0x4 */ + __IO uint32_t TDM_STOP1_COUNT[8]; /**< Time Division Multiplexed stop1 count, array offset: 0x360, array step: 0x4 */ + __IO uint32_t TDM_START2_COUNT[8]; /**< Time Division Multiplexed start2 count, array offset: 0x380, array step: 0x4 */ + __IO uint32_t TDM_STOP2_COUNT[8]; /**< Time Division Multiplexed stop2 count, array offset: 0x3A0, array step: 0x4 */ + __IO uint32_t TDM_START3_COUNT[8]; /**< Time Division Multiplexed start3 count, array offset: 0x3C0, array step: 0x4 */ + __IO uint32_t TDM_STOP3_COUNT[8]; /**< Time Division Multiplexed stop3 count, array offset: 0x3E0, array step: 0x4 */ +} STC_Type; + +/* ---------------------------------------------------------------------------- + -- STC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup STC_Register_Masks STC Register Masks + * @{ + */ + +/*! @name INTERLEAVE_SEL - Interleave Select */ +#define STC_INTERLEAVE_SEL_INTERLEAVE_SEL_MASK (0x3U) +#define STC_INTERLEAVE_SEL_INTERLEAVE_SEL_SHIFT (0U) +#define STC_INTERLEAVE_SEL_INTERLEAVE_SEL(x) (((uint32_t)(((uint32_t)(x)) << STC_INTERLEAVE_SEL_INTERLEAVE_SEL_SHIFT)) & STC_INTERLEAVE_SEL_INTERLEAVE_SEL_MASK) + +/*! @name UD_ENABLE - Underrun Detection Enable */ +#define STC_UD_ENABLE_UD_ENABLE_MASK (0xFFU) +#define STC_UD_ENABLE_UD_ENABLE_SHIFT (0U) +#define STC_UD_ENABLE_UD_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << STC_UD_ENABLE_UD_ENABLE_SHIFT)) & STC_UD_ENABLE_UD_ENABLE_MASK) + +/*! @name TDM_ENABLE - TDM Function Enable */ +#define STC_TDM_ENABLE_TDM_ENABLE_MASK (0xFFU) +#define STC_TDM_ENABLE_TDM_ENABLE_SHIFT (0U) +#define STC_TDM_ENABLE_TDM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_ENABLE_TDM_ENABLE_SHIFT)) & STC_TDM_ENABLE_TDM_ENABLE_MASK) + +/*! @name TDM_ALWAYS_ALLOW - TDM Always Allow */ +#define STC_TDM_ALWAYS_ALLOW_TDM_ALWAYS_ALLOW_MASK (0xFFU) +#define STC_TDM_ALWAYS_ALLOW_TDM_ALWAYS_ALLOW_SHIFT (0U) +#define STC_TDM_ALWAYS_ALLOW_TDM_ALWAYS_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_ALWAYS_ALLOW_TDM_ALWAYS_ALLOW_SHIFT)) & STC_TDM_ALWAYS_ALLOW_TDM_ALWAYS_ALLOW_MASK) + +/*! @name GLB_CSCHED_WAIT_COUNT - Global Completion Scheduler Wait Count */ +#define STC_GLB_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_MASK (0x7U) +#define STC_GLB_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_SHIFT (0U) +#define STC_GLB_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_GLB_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_SHIFT)) & STC_GLB_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_MASK) + +/*! @name MASK_ID - MASK for the AxID Hash Function */ +#define STC_MASK_ID_MASK_ID_MASK (0xFFFU) +#define STC_MASK_ID_MASK_ID_SHIFT (0U) +#define STC_MASK_ID_MASK_ID(x) (((uint32_t)(((uint32_t)(x)) << STC_MASK_ID_MASK_ID_SHIFT)) & STC_MASK_ID_MASK_ID_MASK) + +/* The count of STC_MASK_ID */ +#define STC_MASK_ID_COUNT (8U) + +/*! @name COMPARE_ID - COMPARE ID for the AxID Hash Function */ +#define STC_COMPARE_ID_COMPARE_ID_MASK (0xFFFU) +#define STC_COMPARE_ID_COMPARE_ID_SHIFT (0U) +#define STC_COMPARE_ID_COMPARE_ID(x) (((uint32_t)(((uint32_t)(x)) << STC_COMPARE_ID_COMPARE_ID_SHIFT)) & STC_COMPARE_ID_COMPARE_ID_MASK) + +/* The count of STC_COMPARE_ID */ +#define STC_COMPARE_ID_COUNT (8U) + +/*! @name MIN_QOS - Minimum QoS Clamp */ +#define STC_MIN_QOS_MIN_QOS_MASK (0xFU) +#define STC_MIN_QOS_MIN_QOS_SHIFT (0U) +#define STC_MIN_QOS_MIN_QOS(x) (((uint32_t)(((uint32_t)(x)) << STC_MIN_QOS_MIN_QOS_SHIFT)) & STC_MIN_QOS_MIN_QOS_MASK) + +/* The count of STC_MIN_QOS */ +#define STC_MIN_QOS_COUNT (8U) + +/*! @name MAX_QOS - Maximum QOS Clamp */ +#define STC_MAX_QOS_MAX_QOS_MASK (0xFU) +#define STC_MAX_QOS_MAX_QOS_SHIFT (0U) +#define STC_MAX_QOS_MAX_QOS(x) (((uint32_t)(((uint32_t)(x)) << STC_MAX_QOS_MAX_QOS_SHIFT)) & STC_MAX_QOS_MAX_QOS_MASK) + +/* The count of STC_MAX_QOS */ +#define STC_MAX_QOS_COUNT (8U) + +/*! @name PANIC_QOS_OFFSET - Panic QoS Offset value */ +#define STC_PANIC_QOS_OFFSET_PANIC_QOS_OFFSET_MASK (0xFU) +#define STC_PANIC_QOS_OFFSET_PANIC_QOS_OFFSET_SHIFT (0U) +#define STC_PANIC_QOS_OFFSET_PANIC_QOS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << STC_PANIC_QOS_OFFSET_PANIC_QOS_OFFSET_SHIFT)) & STC_PANIC_QOS_OFFSET_PANIC_QOS_OFFSET_MASK) + +/* The count of STC_PANIC_QOS_OFFSET */ +#define STC_PANIC_QOS_OFFSET_COUNT (8U) + +/*! @name HPR_QOS_OFFSET - Highest Priority QoS Offset value */ +#define STC_HPR_QOS_OFFSET_HPR_QOS_OFFSET_MASK (0xFU) +#define STC_HPR_QOS_OFFSET_HPR_QOS_OFFSET_SHIFT (0U) +#define STC_HPR_QOS_OFFSET_HPR_QOS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << STC_HPR_QOS_OFFSET_HPR_QOS_OFFSET_SHIFT)) & STC_HPR_QOS_OFFSET_HPR_QOS_OFFSET_MASK) + +/* The count of STC_HPR_QOS_OFFSET */ +#define STC_HPR_QOS_OFFSET_COUNT (8U) + +/*! @name UD_QOS_OFFSET - Underrun Detect QoS Offset value */ +#define STC_UD_QOS_OFFSET_UD_QOS_OFFSET_MASK (0xFU) +#define STC_UD_QOS_OFFSET_UD_QOS_OFFSET_SHIFT (0U) +#define STC_UD_QOS_OFFSET_UD_QOS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << STC_UD_QOS_OFFSET_UD_QOS_OFFSET_SHIFT)) & STC_UD_QOS_OFFSET_UD_QOS_OFFSET_MASK) + +/* The count of STC_UD_QOS_OFFSET */ +#define STC_UD_QOS_OFFSET_COUNT (8U) + +/*! @name UD_COUNT_DECR_VALUE - Decrement value of under run counter. */ +#define STC_UD_COUNT_DECR_VALUE_UD_COUNT_DECR_VALUE_MASK (0x7FU) +#define STC_UD_COUNT_DECR_VALUE_UD_COUNT_DECR_VALUE_SHIFT (0U) +#define STC_UD_COUNT_DECR_VALUE_UD_COUNT_DECR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << STC_UD_COUNT_DECR_VALUE_UD_COUNT_DECR_VALUE_SHIFT)) & STC_UD_COUNT_DECR_VALUE_UD_COUNT_DECR_VALUE_MASK) + +/* The count of STC_UD_COUNT_DECR_VALUE */ +#define STC_UD_COUNT_DECR_VALUE_COUNT (8U) + +/*! @name UD_COUNT_THRESH_1 - Underrun counter threshold 1 */ +#define STC_UD_COUNT_THRESH_1_UD_COUNT_THRESH_1_MASK (0x7FU) +#define STC_UD_COUNT_THRESH_1_UD_COUNT_THRESH_1_SHIFT (0U) +#define STC_UD_COUNT_THRESH_1_UD_COUNT_THRESH_1(x) (((uint32_t)(((uint32_t)(x)) << STC_UD_COUNT_THRESH_1_UD_COUNT_THRESH_1_SHIFT)) & STC_UD_COUNT_THRESH_1_UD_COUNT_THRESH_1_MASK) + +/* The count of STC_UD_COUNT_THRESH_1 */ +#define STC_UD_COUNT_THRESH_1_COUNT (8U) + +/*! @name UD_COUNT_THRESH_2 - Underrun counter threshold 2 */ +#define STC_UD_COUNT_THRESH_2_UD_COUNT_THRESH_2_MASK (0x7FU) +#define STC_UD_COUNT_THRESH_2_UD_COUNT_THRESH_2_SHIFT (0U) +#define STC_UD_COUNT_THRESH_2_UD_COUNT_THRESH_2(x) (((uint32_t)(((uint32_t)(x)) << STC_UD_COUNT_THRESH_2_UD_COUNT_THRESH_2_SHIFT)) & STC_UD_COUNT_THRESH_2_UD_COUNT_THRESH_2_MASK) + +/* The count of STC_UD_COUNT_THRESH_2 */ +#define STC_UD_COUNT_THRESH_2_COUNT (8U) + +/*! @name CSCHED_WAIT_COUNT - Category Completion Scheduler wait count for completion returns */ +#define STC_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_MASK (0x3FU) +#define STC_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_SHIFT (0U) +#define STC_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_SHIFT)) & STC_CSCHED_WAIT_COUNT_CSCHED_WAIT_COUNT_MASK) + +/* The count of STC_CSCHED_WAIT_COUNT */ +#define STC_CSCHED_WAIT_COUNT_COUNT (8U) + +/*! @name TDM_QOS_OFFSET - TDM QoS OFFSET */ +#define STC_TDM_QOS_OFFSET_TDM_QOS_OFFSET_MASK (0xFU) +#define STC_TDM_QOS_OFFSET_TDM_QOS_OFFSET_SHIFT (0U) +#define STC_TDM_QOS_OFFSET_TDM_QOS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_QOS_OFFSET_TDM_QOS_OFFSET_SHIFT)) & STC_TDM_QOS_OFFSET_TDM_QOS_OFFSET_MASK) + +/* The count of STC_TDM_QOS_OFFSET */ +#define STC_TDM_QOS_OFFSET_COUNT (8U) + +/*! @name TDM_START0_COUNT - Time Division Multiplexed Start0 count */ +#define STC_TDM_START0_COUNT_TDM_START_COUNT_MASK (0x7FU) +#define STC_TDM_START0_COUNT_TDM_START_COUNT_SHIFT (0U) +#define STC_TDM_START0_COUNT_TDM_START_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_START0_COUNT_TDM_START_COUNT_SHIFT)) & STC_TDM_START0_COUNT_TDM_START_COUNT_MASK) + +/* The count of STC_TDM_START0_COUNT */ +#define STC_TDM_START0_COUNT_COUNT (8U) + +/*! @name TDM_STOP0_COUNT - Time Division Multiplexed stop0 count */ +#define STC_TDM_STOP0_COUNT_TDM_STOP_COUNT_MASK (0x7FU) +#define STC_TDM_STOP0_COUNT_TDM_STOP_COUNT_SHIFT (0U) +#define STC_TDM_STOP0_COUNT_TDM_STOP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_STOP0_COUNT_TDM_STOP_COUNT_SHIFT)) & STC_TDM_STOP0_COUNT_TDM_STOP_COUNT_MASK) + +/* The count of STC_TDM_STOP0_COUNT */ +#define STC_TDM_STOP0_COUNT_COUNT (8U) + +/*! @name TDM_START1_COUNT - Time Division Multiplexed start1 count */ +#define STC_TDM_START1_COUNT_TDM_START_COUNT_MASK (0x7FU) +#define STC_TDM_START1_COUNT_TDM_START_COUNT_SHIFT (0U) +#define STC_TDM_START1_COUNT_TDM_START_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_START1_COUNT_TDM_START_COUNT_SHIFT)) & STC_TDM_START1_COUNT_TDM_START_COUNT_MASK) + +/* The count of STC_TDM_START1_COUNT */ +#define STC_TDM_START1_COUNT_COUNT (8U) + +/*! @name TDM_STOP1_COUNT - Time Division Multiplexed stop1 count */ +#define STC_TDM_STOP1_COUNT_TDM_STOP_COUNT_MASK (0x7FU) +#define STC_TDM_STOP1_COUNT_TDM_STOP_COUNT_SHIFT (0U) +#define STC_TDM_STOP1_COUNT_TDM_STOP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_STOP1_COUNT_TDM_STOP_COUNT_SHIFT)) & STC_TDM_STOP1_COUNT_TDM_STOP_COUNT_MASK) + +/* The count of STC_TDM_STOP1_COUNT */ +#define STC_TDM_STOP1_COUNT_COUNT (8U) + +/*! @name TDM_START2_COUNT - Time Division Multiplexed start2 count */ +#define STC_TDM_START2_COUNT_TDM_START_COUNT_MASK (0x7FU) +#define STC_TDM_START2_COUNT_TDM_START_COUNT_SHIFT (0U) +#define STC_TDM_START2_COUNT_TDM_START_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_START2_COUNT_TDM_START_COUNT_SHIFT)) & STC_TDM_START2_COUNT_TDM_START_COUNT_MASK) + +/* The count of STC_TDM_START2_COUNT */ +#define STC_TDM_START2_COUNT_COUNT (8U) + +/*! @name TDM_STOP2_COUNT - Time Division Multiplexed stop2 count */ +#define STC_TDM_STOP2_COUNT_TDM_STOP_COUNT_MASK (0x7FU) +#define STC_TDM_STOP2_COUNT_TDM_STOP_COUNT_SHIFT (0U) +#define STC_TDM_STOP2_COUNT_TDM_STOP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_STOP2_COUNT_TDM_STOP_COUNT_SHIFT)) & STC_TDM_STOP2_COUNT_TDM_STOP_COUNT_MASK) + +/* The count of STC_TDM_STOP2_COUNT */ +#define STC_TDM_STOP2_COUNT_COUNT (8U) + +/*! @name TDM_START3_COUNT - Time Division Multiplexed start3 count */ +#define STC_TDM_START3_COUNT_TDM_START_COUNT_MASK (0x7FU) +#define STC_TDM_START3_COUNT_TDM_START_COUNT_SHIFT (0U) +#define STC_TDM_START3_COUNT_TDM_START_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_START3_COUNT_TDM_START_COUNT_SHIFT)) & STC_TDM_START3_COUNT_TDM_START_COUNT_MASK) + +/* The count of STC_TDM_START3_COUNT */ +#define STC_TDM_START3_COUNT_COUNT (8U) + +/*! @name TDM_STOP3_COUNT - Time Division Multiplexed stop3 count */ +#define STC_TDM_STOP3_COUNT_TDM_STOP_COUNT_MASK (0x7FU) +#define STC_TDM_STOP3_COUNT_TDM_STOP_COUNT_SHIFT (0U) +#define STC_TDM_STOP3_COUNT_TDM_STOP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << STC_TDM_STOP3_COUNT_TDM_STOP_COUNT_SHIFT)) & STC_TDM_STOP3_COUNT_TDM_STOP_COUNT_MASK) + +/* The count of STC_TDM_STOP3_COUNT */ +#define STC_TDM_STOP3_COUNT_COUNT (8U) + + +/*! + * @} + */ /* end of group STC_Register_Masks */ + + +/** Peripheral STC0 base pointer */ +#define STC0 ((STC_Type *)STC0_BASE) +/** Peripheral STC1 base pointer */ +#define STC1 ((STC_Type *)STC1_BASE) +/** Peripheral STC2 base pointer */ +#define STC2 ((STC_Type *)STC2_BASE) +/** Peripheral STC3 base pointer */ +#define STC3 ((STC_Type *)STC3_BASE) +/** Peripheral STC4 base pointer */ +#define STC4 ((STC_Type *)STC4_BASE) +/** Peripheral STC5 base pointer */ +#define STC5 ((STC_Type *)STC5_BASE) +/** Peripheral STC6 base pointer */ +#define STC6 ((STC_Type *)STC6_BASE) +/** Peripheral STC7 base pointer */ +#define STC7 ((STC_Type *)STC7_BASE) +/** Peripheral STC8 base pointer */ +#define STC8 ((STC_Type *)STC8_BASE) +/** Peripheral STC9 base pointer */ +#define STC9 ((STC_Type *)STC9_BASE) +/** Peripheral STC10 base pointer */ +#define STC10 ((STC_Type *)STC10_BASE) +/** Peripheral STC11 base pointer */ +#define STC11 ((STC_Type *)STC11_BASE) +/** Peripheral STC12 base pointer */ +#define STC12 ((STC_Type *)STC12_BASE) +/** Peripheral STC13 base pointer */ +#define STC13 ((STC_Type *)STC13_BASE) +/** Peripheral STC14 base pointer */ +#define STC14 ((STC_Type *)STC14_BASE) +/** Peripheral STC15 base pointer */ +#define STC15 ((STC_Type *)STC15_BASE) +/** Peripheral STC15 base pointer */ +#define STC16 ((STC_Type *)STC16_BASE) +/** Peripheral STC15 base pointer */ +#define STC17 ((STC_Type *)STC17_BASE) +/** Peripheral STC15 base pointer */ +#define STC18 ((STC_Type *)STC18_BASE) +/** Peripheral STC15 base pointer */ +#define STC19 ((STC_Type *)STC19_BASE) +/** Peripheral STC15 base pointer */ +#define STC20 ((STC_Type *)STC20_BASE) +/** Peripheral STC15 base pointer */ +#define STC21 ((STC_Type *)STC21_BASE) +/** Peripheral STC15 base pointer */ +#define STC22 ((STC_Type *)STC22_BASE) +/** Peripheral STC15 base pointer */ +#define STC23 ((STC_Type *)STC23_BASE) + + +/** Array initializer of STC peripheral base addresses */ +#define STC_BASE_ADDRS { STC0_BASE, STC1_BASE, \ + STC2_BASE, STC3_BASE, \ + STC2_BASE, STC3_BASE, \ + STC4_BASE, STC5_BASE, \ + STC6_BASE, STC7_BASE, \ + STC8_BASE, STC9_BASE, \ + STC10_BASE, STC11_BASE, \ + STC12_BASE, STC13_BASE, \ + STC14_BASE, STC15_BASE, \ + STC16_BASE, STC17_BASE, \ + STC18_BASE, STC19_BASE, \ + STC20_BASE, STC21_BASE, \ + STC22_BASE, STC23_BASE } +/** Array initializer of STC peripheral base pointers */ +#define STC_BASE_PTRS { STC0, STC1, STC2, STC3, \ + STC4, STC5, STC6, STC7, \ + STC8, STC9, STC10, STC11, \ + STC12, STC13, STC14, STC15, \ + STC16, STC17, STC18, STC19, \ + STC20, STC21, STC22, STC23 } + +/*! + * @} + */ /* end of group STC_Peripheral_Access_Layer */ + + +#endif /* STC_H */ + diff --git a/platform/devices/MX8/MX8_sysctr.h b/platform/devices/MX8/MX8_sysctr.h new file mode 100755 index 0000000..e66b8fd --- /dev/null +++ b/platform/devices/MX8/MX8_sysctr.h @@ -0,0 +1,214 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_SYSCTR_REGISTERS_H +#define HW_SYSCTR_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- SYSCTR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTR_Peripheral_Access_Layer SYSCTR Peripheral Access Layer + * @{ + */ + +/** SYSCTR_CTRL - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTCR; /**< Counter Control Register, offset: 0x0 */ + __IO uint32_t CNTSR; /**< Counter Status Register, offset: 0x4 */ + __IO uint32_t CNTCVL; /**< Counter Count Value Low, offset: 0x8 */ + __IO uint32_t CNTCVH; /**< Counter Count Value High, offset: 0xC */ + uint32_t RESERVED_0[4]; + __IO uint32_t CNTFID0; /**< Frequency Mode Table, Base Frequency, offset: 0x20 */ + __IO uint32_t CNTFID1; /**< Frequency Mode Table, Alternate Frequency, offset: 0x24 */ + __IO uint32_t CNTFID2; /**< Frequency Mode Table, End Marker, offset: 0x28 */ +} SYSCTR_CTRL_Type, *SYSCTR_CTRL_MemMapPtr; + +/** SYSCTR_RD - Register Layout Typedef */ +typedef struct { + uint32_t RESERVED_0[2]; + __IO uint32_t CNTCVL; /**< Counter Count Value Low, offset: 0x8 */ + __IO uint32_t CNTCVH; /**< Counter Count Value High, offset: 0xC */ +} SYSCTR_RD_Type, *SYSCTR_RD_MemMapPtr; + +/** SYSCTR_CMP - Register Layout Typedef */ +typedef struct { + uint32_t RESERVED_0[8]; + __IO uint32_t CMPCVL; /**< Counter Compare Value Low, offset: 0x20 */ + __IO uint32_t CMPCVH; /**< Counter Compare Value Low, offset: 0x24 */ + uint32_t RESERVED_1[1]; + __IO uint32_t CMPCR; /**< Counter Compare Control Register, offset: 0x2C */ +} SYSCTR_CMP_Type, *SYSCTR_CMP_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- SYSCTR_CTRL Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTR_CTRL_Register_Masks SYSCTR_CTRL Register Masks + * @{ + */ + +/* CNTCR Bit Fields */ +#define SYSCTR_CTRL_CNTCR_EN_SHIFT 0U +#define SYSCTR_CTRL_CNTCR_EN_WIDTH 1U +#define SYSCTR_CTRL_CNTCR_EN_MASK (1UL << SYSCTR_CTRL_CNTCR_EN_SHIFT) +#define SYSCTR_CTRL_CNTCR_HDBG_SHIFT 1U +#define SYSCTR_CTRL_CNTCR_HDBG_WIDTH 1U +#define SYSCTR_CTRL_CNTCR_HDBG_MASK (1UL << SYSCTR_CTRL_CNTCR_HDBG_SHIFT) +#define SYSCTR_CTRL_CNTCR_FCR0_SHIFT 8U +#define SYSCTR_CTRL_CNTCR_FCR0_WIDTH 1U +#define SYSCTR_CTRL_CNTCR_FCR0_MASK (1UL << SYSCTR_CTRL_CNTCR_FCR0_SHIFT) +#define SYSCTR_CTRL_CNTCR_FCR1_SHIFT 9U +#define SYSCTR_CTRL_CNTCR_FCR1_WIDTH 1U +#define SYSCTR_CTRL_CNTCR_FCR1_MASK (1UL << SYSCTR_CTRL_CNTCR_FCR1_SHIFT) +/* CNTSR Bit Fields */ +#define SYSCTR_CTRL_CNTSR_DBGH_SHIFT 0U +#define SYSCTR_CTRL_CNTSR_DBGH_WIDTH 1U +#define SYSCTR_CTRL_CNTSR_DBGH_MASK (1UL << SYSCTR_CTRL_CNTSR_DBGH_SHIFT) +#define SYSCTR_CTRL_CNTSR_FCA0_SHIFT 8U +#define SYSCTR_CTRL_CNTSR_FCA0_WIDTH 1U +#define SYSCTR_CTRL_CNTSR_FCA0_MASK (1UL << SYSCTR_CTRL_CNTSR_FCA0_SHIFT) +#define SYSCTR_CTRL_CNTSR_FCA1_SHIFT 9U +#define SYSCTR_CTRL_CNTSR_FCA1_WIDTH 1U +#define SYSCTR_CTRL_CNTSR_FCA1_MASK (1UL << SYSCTR_CTRL_CNTSR_FCA1_SHIFT) +/* CNTCVL Bit Fields */ +#define SYSCTR_CTRL_CNTCVL_CNTCV_SHIFT 0U +#define SYSCTR_CTRL_CNTCVL_CNTCV_WIDTH 32U +/* CNTCVH Bit Fields */ +#define SYSCTR_CTRL_CNTCVH_CNTCV_SHIFT 0U +#define SYSCTR_CTRL_CNTCVH_CNTCV_WIDTH 24U +/* CNTFID0 Bit Fields */ +#define SYSCTR_CTRL_CNTFID0_CNTFID_SHIFT 0U +#define SYSCTR_CTRL_CNTFID0_CNTFID_WIDTH 32U +/* CNTFID1 Bit Fields */ +#define SYSCTR_CTRL_CNTFID1_CNTFID_SHIFT 0U +#define SYSCTR_CTRL_CNTFID1_CNTFID_WIDTH 32U +/* CNTFID1 Bit Fields */ +#define SYSCTR_CTRL_CNTFID2_CNTFID_SHIFT 0U +#define SYSCTR_CTRL_CNTFID2_CNTFID_WIDTH 32U + +/*! + * @} + */ /* end of group SYSCTR_CTRL_Register_Masks */ + +/*! + * @addtogroup SYSCTR_RD_Register_Masks SYSCTR_RD Register Masks + * @{ + */ + +/* CNTCVL Bit Fields */ +#define SYSCTR_RD_CNTCVL_CNTCV_SHIFT 0U +#define SYSCTR_RD_CNTCVL_CNTCV_WIDTH 32U +/* CNTCVH Bit Fields */ +#define SYSCTR_RD_CNTCVH_CNTCV_SHIFT 0U +#define SYSCTR_RD_CNTCVH_CNTCV_WIDTH 24U + +/*! + * @} + */ /* end of group SYSCTR_RD_Register_Masks */ + +/*! + * @addtogroup SYSCTR_CMP_Register_Masks SYSCTR_CMP Register Masks + * @{ + */ + +/* CMPCVL Bit Fields */ +#define SYSCTR_CMP_CMPCVL_CMPCV_SHIFT 0U +#define SYSCTR_CMP_CMPCVL_CMPCV_WIDTH 32U +/* CMPCVH Bit Fields */ +#define SYSCTR_CMP_CMPCVH_CMPCV_SHIFT 0U +#define SYSCTR_CMP_CMPCVH_CMPCV_WIDTH 24U +/* CMPCR Bit Fields */ +#define SYSCTR_CMP_CMPCR_EN_SHIFT 0U +#define SYSCTR_CMP_CMPCR_EN_WIDTH 1U +#define SYSCTR_CMP_CMPCR_EN_MASK (1UL << SYSCTR_CMP_CMPCR_EN_SHIFT) +#define SYSCTR_CMP_CMPCR_IMASK_SHIFT 1U +#define SYSCTR_CMP_CMPCR_IMASK_WIDTH 1U +#define SYSCTR_CMP_CMPCR_IMASK_MASK (1UL << SYSCTR_CMP_CMPCR_IMASK_SHIFT) +#define SYSCTR_CMP_CMPCR_ISTAT_SHIFT 2U +#define SYSCTR_CMP_CMPCR_ISTAT_WIDTH 1U +#define SYSCTR_CMP_CMPCR_ISTAT_MASK (1UL << SYSCTR_CMP_CMPCR_ISTAT_SHIFT) + +/*! + * @} + */ /* end of group SYSCTR_CMP_Register_Masks */ + + +/* SYSCTR - Peripheral instance base addresses */ +/** Peripheral SYSCTR base pointer */ +#define SYSCTR_CTRL ((SYSCTR_CTRL_Type *)SYSCTR_CTRL_BASE) +#define SYSCTR_CTRL_BASE_PTR (SYSCTR_CTRL_BASE) +#define SYSCTR_RD ((SYSCTR_RD_Type *)SYSCTR_RD_BASE) +#define SYSCTR_RD_BASE_PTR (SYSCTR_RD_BASE) +#define SYSCTR_CMP ((SYSCTR_CMP_Type *)SYSCTR_CMP_BASE) +#define SYSCTR_CMP_BASE_PTR (SYSCTR_CMP_BASE) +#define SYSCTR_CMP1 ((SYSCTR_CMP_Type *)SYSCTR_CMP1_BASE) +#define SYSCTR_CMP1_BASE_PTR (SYSCTR_CMP1_BASE) +/** Interrupt vectors for the SYSCTR peripheral type */ +#define SYSCTR_IRQS { SYSCTR_CMP0_IRQn, SYSCTR_CMP1_IRQn, SYSCTR_CMP2_IRQn, SYSCTR_CMP3_IRQn } + + +/* ---------------------------------------------------------------------------- + -- SYSCTR - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCTR_Register_Accessor_Macros SYSCTR - Register accessor macros + * @{ + */ + + + + +/*! + * @} + */ /* end of group SYSCTR_Peripheral_Access_Layer */ + +#endif /* HW_SYSCTR_REGISTERS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8/MX8_wdog.h b/platform/devices/MX8/MX8_wdog.h new file mode 100755 index 0000000..897538b --- /dev/null +++ b/platform/devices/MX8/MX8_wdog.h @@ -0,0 +1,169 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ + +#ifndef HW_WDOG_REGISTERS_H +#define HW_WDOG_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ + __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ + __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name CS - Watchdog Control and Status Register */ +#define WDOG_CS_STOP_MASK (0x1U) +#define WDOG_CS_STOP_SHIFT (0U) +#define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_STOP_SHIFT)) & WDOG_CS_STOP_MASK) +#define WDOG_CS_WAIT_MASK (0x2U) +#define WDOG_CS_WAIT_SHIFT (1U) +#define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WAIT_SHIFT)) & WDOG_CS_WAIT_MASK) +#define WDOG_CS_DBG_MASK (0x4U) +#define WDOG_CS_DBG_SHIFT (2U) +#define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_DBG_SHIFT)) & WDOG_CS_DBG_MASK) +#define WDOG_CS_TST_MASK (0x18U) +#define WDOG_CS_TST_SHIFT (3U) +#define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_TST_SHIFT)) & WDOG_CS_TST_MASK) +#define WDOG_CS_UPDATE_MASK (0x20U) +#define WDOG_CS_UPDATE_SHIFT (5U) +#define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_UPDATE_SHIFT)) & WDOG_CS_UPDATE_MASK) +#define WDOG_CS_INT_MASK (0x40U) +#define WDOG_CS_INT_SHIFT (6U) +#define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_INT_SHIFT)) & WDOG_CS_INT_MASK) +#define WDOG_CS_EN_MASK (0x80U) +#define WDOG_CS_EN_SHIFT (7U) +#define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_EN_SHIFT)) & WDOG_CS_EN_MASK) +#define WDOG_CS_CLK_MASK (0x300U) +#define WDOG_CS_CLK_SHIFT (8U) +#define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CLK_SHIFT)) & WDOG_CS_CLK_MASK) +#define WDOG_CS_PRES_MASK (0x1000U) +#define WDOG_CS_PRES_SHIFT (12U) +#define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_PRES_SHIFT)) & WDOG_CS_PRES_MASK) +#define WDOG_CS_CMD32EN_MASK (0x2000U) +#define WDOG_CS_CMD32EN_SHIFT (13U) +#define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_CMD32EN_SHIFT)) & WDOG_CS_CMD32EN_MASK) +#define WDOG_CS_FLG_MASK (0x4000U) +#define WDOG_CS_FLG_SHIFT (14U) +#define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_FLG_SHIFT)) & WDOG_CS_FLG_MASK) +#define WDOG_CS_WIN_MASK (0x8000U) +#define WDOG_CS_WIN_SHIFT (15U) +#define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CS_WIN_SHIFT)) & WDOG_CS_WIN_MASK) + +/*! @name CNT - Watchdog Counter Register */ +#define WDOG_CNT_CNTLOW_MASK (0xFFU) +#define WDOG_CNT_CNTLOW_SHIFT (0U) +#define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) +#define WDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define WDOG_CNT_CNTHIGH_SHIFT (8U) +#define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) + +/*! @name TOVAL - Watchdog Timeout Value Register */ +#define WDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define WDOG_TOVAL_TOVALLOW_SHIFT (0U) +#define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) +#define WDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define WDOG_TOVAL_TOVALHIGH_SHIFT (8U) +#define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) + +/*! @name WIN - Watchdog Window Register */ +#define WDOG_WIN_WINLOW_MASK (0xFFU) +#define WDOG_WIN_WINLOW_SHIFT (0U) +#define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) +#define WDOG_WIN_WINHIGH_MASK (0xFF00U) +#define WDOG_WIN_WINHIGH_SHIFT (8U) +#define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG0 base pointer */ +#define WDOG0 ((WDOG_Type *)WDOG0_BASE) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { WDOG0_BASE, WDOG1_BASE, \ + WDOG2_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG0, WDOG1, WDOG2 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG0_IRQn } + +#define WDOG_UPDATE_KEY (0xD928C520U) +#define WDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +#endif /* HW_WDOG_REGISTERS_H */ + diff --git a/platform/devices/MX8/MX8_xrdc2.h b/platform/devices/MX8/MX8_xrdc2.h new file mode 100755 index 0000000..e99d87e --- /dev/null +++ b/platform/devices/MX8/MX8_xrdc2.h @@ -0,0 +1,523 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 1900 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** Revisions: +** +** ################################################################### +*/ + +/*! + * @file xrdc2.h + * @version 0.0 + * @date 0-00-00 + * @brief CMSIS Peripheral Access Layer for xrdc2 + * + * CMSIS Peripheral Access Layer for xrdc2 + */ + +#ifndef XRDC2_H +#define XRDC2_H /**< Symbol preventing repeated inclusion */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- XRDC2 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XRDC2_Peripheral_Access_Layer XRDC2 Peripheral Access Layer + * @{ + */ + +/** XRDC2 - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ + __I uint32_t SR; /**< Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4088]; + struct { /* offset: 0x1000, array step: 0x8 */ + __IO uint32_t MSC_MSAC_W0; /**< Memory Slot Access Control, array offset: 0x1000, array step: 0x8 */ + __IO uint32_t MSC_MSAC_W1; /**< Memory Slot Access Control, array offset: 0x1004, array step: 0x8 */ + } MSCI_MSAC_WK[128]; + uint8_t RESERVED_1[3072]; + struct { /* offset: 0x2000, array step: index*0x100, index2*0x8 */ + __IO uint32_t MDAC_MDA_W0; /**< Master Domain Assignment (W0), array offset: 0x2000, array step: index*0x100, index2*0x8 */ + __IO uint32_t MDAC_MDA_W1; /**< Master Domain Assignment (W1), array offset: 0x2004, array step: index*0x100, index2*0x8 */ + } MDACI_MDAJ[32][32]; + struct { /* offset: 0x4000, array step: index*0x800, index2*0x8 */ + __IO uint32_t PAC_PDAC_W0; /**< Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8 */ + __IO uint32_t PAC_PDAC_W1; /**< Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8 */ + } PACI_PDACJ[8][256]; + struct { /* offset: 0x8000, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W0; /**< Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W1; /**< Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W2; /**< Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W3; /**< Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W4; /**< Memory Region Descriptor, array offset: 0x8010, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W5; /**< Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20 */ + __IO uint32_t MRC_MRGD_W6; /**< Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20 */ + uint8_t RESERVED_0[4]; + } MRCI_MRGDJ[32][32]; +} XRDC2_Type; + +/* ---------------------------------------------------------------------------- + -- XRDC2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XRDC2_Register_Masks XRDC2 Register Masks + * @{ + */ + +/*! @name MCR - Module Control Register */ +#define XRDC2_MCR_GVLDM_MASK (0x1U) +#define XRDC2_MCR_GVLDM_SHIFT (0U) +#define XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) +#define XRDC2_MCR_GVLDC_MASK (0x2U) +#define XRDC2_MCR_GVLDC_SHIFT (1U) +#define XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) +#define XRDC2_MCR_GCL_MASK (0x30U) +#define XRDC2_MCR_GCL_SHIFT (4U) +#define XRDC2_MCR_GCL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK) + +/*! @name SR - Status Register */ +#define XRDC2_SR_DID_MASK (0xFU) +#define XRDC2_SR_DID_SHIFT (0U) +#define XRDC2_SR_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DID_SHIFT)) & XRDC2_SR_DID_MASK) +#define XRDC2_SR_HRL_MASK (0xF0U) +#define XRDC2_SR_HRL_SHIFT (4U) +#define XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK) +#define XRDC2_SR_GCLO_MASK (0xF00U) +#define XRDC2_SR_GCLO_SHIFT (8U) +#define XRDC2_SR_GCLO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK) + +/*! @name MSC_MSAC_W0 - Memory Slot Access Control */ +#define XRDC2_MSC_MSAC_W0_D0ACP_MASK (0x7U) +#define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT (0U) +#define XRDC2_MSC_MSAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D1ACP_MASK (0x38U) +#define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT (3U) +#define XRDC2_MSC_MSAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D2ACP_MASK (0x1C0U) +#define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT (6U) +#define XRDC2_MSC_MSAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D3ACP_MASK (0xE00U) +#define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT (9U) +#define XRDC2_MSC_MSAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D4ACP_MASK (0x7000U) +#define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT (12U) +#define XRDC2_MSC_MSAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D5ACP_MASK (0x38000U) +#define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT (15U) +#define XRDC2_MSC_MSAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D6ACP_MASK (0x1C0000U) +#define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT (18U) +#define XRDC2_MSC_MSAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK) +#define XRDC2_MSC_MSAC_W0_D7ACP_MASK (0xE00000U) +#define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT (21U) +#define XRDC2_MSC_MSAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK) +#define XRDC2_MSC_MSAC_W0_EALO_MASK (0xF000000U) +#define XRDC2_MSC_MSAC_W0_EALO_SHIFT (24U) +#define XRDC2_MSC_MSAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK) + +/* The count of XRDC2_MSC_MSAC_W0 */ +#define XRDC2_MSC_MSAC_W0_COUNT (128U) + +/*! @name MSC_MSAC_W1 - Memory Slot Access Control */ +#define XRDC2_MSC_MSAC_W1_D8ACP_MASK (0x7U) +#define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT (0U) +#define XRDC2_MSC_MSAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D9ACP_MASK (0x38U) +#define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT (3U) +#define XRDC2_MSC_MSAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D10ACP_MASK (0x1C0U) +#define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT (6U) +#define XRDC2_MSC_MSAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D11ACP_MASK (0xE00U) +#define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT (9U) +#define XRDC2_MSC_MSAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D12ACP_MASK (0x7000U) +#define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT (12U) +#define XRDC2_MSC_MSAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D13ACP_MASK (0x38000U) +#define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT (15U) +#define XRDC2_MSC_MSAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D14ACP_MASK (0x1C0000U) +#define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT (18U) +#define XRDC2_MSC_MSAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK) +#define XRDC2_MSC_MSAC_W1_D15ACP_MASK (0xE00000U) +#define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT (21U) +#define XRDC2_MSC_MSAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK) +#define XRDC2_MSC_MSAC_W1_EAL_MASK (0x3000000U) +#define XRDC2_MSC_MSAC_W1_EAL_SHIFT (24U) +#define XRDC2_MSC_MSAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK) +#define XRDC2_MSC_MSAC_W1_DL2_MASK (0x60000000U) +#define XRDC2_MSC_MSAC_W1_DL2_SHIFT (29U) +#define XRDC2_MSC_MSAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK) +#define XRDC2_MSC_MSAC_W1_VLD_MASK (0x80000000U) +#define XRDC2_MSC_MSAC_W1_VLD_SHIFT (31U) +#define XRDC2_MSC_MSAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK) + +/* The count of XRDC2_MSC_MSAC_W1 */ +#define XRDC2_MSC_MSAC_W1_COUNT (128U) + +/*! @name MDAC_MDA_W0 - Master Domain Assignment (W0) */ +#define XRDC2_MDAC_MDA_W0_MASK_MASK (0xFFFFU) +#define XRDC2_MDAC_MDA_W0_MASK_SHIFT (0U) +#define XRDC2_MDAC_MDA_W0_MASK(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK) +#define XRDC2_MDAC_MDA_W0_MATCH_MASK (0xFFFF0000U) +#define XRDC2_MDAC_MDA_W0_MATCH_SHIFT (16U) +#define XRDC2_MDAC_MDA_W0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK) + +/* The count of XRDC2_MDAC_MDA_W0 */ +#define XRDC2_MDAC_MDA_W0_COUNT (32U) + +/* The count of XRDC2_MDAC_MDA_W0 */ +#define XRDC2_MDAC_MDA_W0_COUNT2 (32U) + +/*! @name MDAC_MDA_W1 - Master Domain Assignment (W1) */ +#define XRDC2_MDAC_MDA_W1_SID_MASK (0xFFFFU) +#define XRDC2_MDAC_MDA_W1_SID_SHIFT (0U) +#define XRDC2_MDAC_MDA_W1_SID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SID_SHIFT)) & XRDC2_MDAC_MDA_W1_SID_MASK) +#define XRDC2_MDAC_MDA_W1_DID_MASK (0xF0000U) +#define XRDC2_MDAC_MDA_W1_DID_SHIFT (16U) +#define XRDC2_MDAC_MDA_W1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK) +#define XRDC2_MDAC_MDA_W1_PA_MASK (0x3000000U) +#define XRDC2_MDAC_MDA_W1_PA_SHIFT (24U) +#define XRDC2_MDAC_MDA_W1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK) +#define XRDC2_MDAC_MDA_W1_SA_MASK (0xC000000U) +#define XRDC2_MDAC_MDA_W1_SA_SHIFT (26U) +#define XRDC2_MDAC_MDA_W1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK) +#define XRDC2_MDAC_MDA_W1_DL_MASK (0x40000000U) +#define XRDC2_MDAC_MDA_W1_DL_SHIFT (30U) +#define XRDC2_MDAC_MDA_W1_DL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK) +#define XRDC2_MDAC_MDA_W1_VLD_MASK (0x80000000U) +#define XRDC2_MDAC_MDA_W1_VLD_SHIFT (31U) +#define XRDC2_MDAC_MDA_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK) + +/* The count of XRDC2_MDAC_MDA_W1 */ +#define XRDC2_MDAC_MDA_W1_COUNT (32U) + +/* The count of XRDC2_MDAC_MDA_W1 */ +#define XRDC2_MDAC_MDA_W1_COUNT2 (32U) + +/*! @name PAC_PDAC_W0 - Peripheral Domain Access Control */ +#define XRDC2_PAC_PDAC_W0_D0ACP_MASK (0x7U) +#define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT (0U) +#define XRDC2_PAC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D1ACP_MASK (0x38U) +#define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT (3U) +#define XRDC2_PAC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D2ACP_MASK (0x1C0U) +#define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT (6U) +#define XRDC2_PAC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D3ACP_MASK (0xE00U) +#define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT (9U) +#define XRDC2_PAC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D4ACP_MASK (0x7000U) +#define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT (12U) +#define XRDC2_PAC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D5ACP_MASK (0x38000U) +#define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT (15U) +#define XRDC2_PAC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D6ACP_MASK (0x1C0000U) +#define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT (18U) +#define XRDC2_PAC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK) +#define XRDC2_PAC_PDAC_W0_D7ACP_MASK (0xE00000U) +#define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT (21U) +#define XRDC2_PAC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK) +#define XRDC2_PAC_PDAC_W0_EALO_MASK (0xF000000U) +#define XRDC2_PAC_PDAC_W0_EALO_SHIFT (24U) +#define XRDC2_PAC_PDAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK) + +/* The count of XRDC2_PAC_PDAC_W0 */ +#define XRDC2_PAC_PDAC_W0_COUNT (8U) + +/* The count of XRDC2_PAC_PDAC_W0 */ +#define XRDC2_PAC_PDAC_W0_COUNT2 (256U) + +/*! @name PAC_PDAC_W1 - Peripheral Domain Access Control */ +#define XRDC2_PAC_PDAC_W1_D8ACP_MASK (0x7U) +#define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT (0U) +#define XRDC2_PAC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D9ACP_MASK (0x38U) +#define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT (3U) +#define XRDC2_PAC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D10ACP_MASK (0x1C0U) +#define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT (6U) +#define XRDC2_PAC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D11ACP_MASK (0xE00U) +#define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT (9U) +#define XRDC2_PAC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D12ACP_MASK (0x7000U) +#define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT (12U) +#define XRDC2_PAC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D13ACP_MASK (0x38000U) +#define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT (15U) +#define XRDC2_PAC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D14ACP_MASK (0x1C0000U) +#define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT (18U) +#define XRDC2_PAC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK) +#define XRDC2_PAC_PDAC_W1_D15ACP_MASK (0xE00000U) +#define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT (21U) +#define XRDC2_PAC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK) +#define XRDC2_PAC_PDAC_W1_EAL_MASK (0x3000000U) +#define XRDC2_PAC_PDAC_W1_EAL_SHIFT (24U) +#define XRDC2_PAC_PDAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK) +#define XRDC2_PAC_PDAC_W1_DL2_MASK (0x60000000U) +#define XRDC2_PAC_PDAC_W1_DL2_SHIFT (29U) +#define XRDC2_PAC_PDAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK) +#define XRDC2_PAC_PDAC_W1_VLD_MASK (0x80000000U) +#define XRDC2_PAC_PDAC_W1_VLD_SHIFT (31U) +#define XRDC2_PAC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK) + +/* The count of XRDC2_PAC_PDAC_W1 */ +#define XRDC2_PAC_PDAC_W1_COUNT (8U) + +/* The count of XRDC2_PAC_PDAC_W1 */ +#define XRDC2_PAC_PDAC_W1_COUNT2 (256U) + +/*! @name MRC_MRGD_W0 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W0_SRTADDR_MASK (0xFFFFF000U) +#define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT (12U) +#define XRDC2_MRC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK) + +/* The count of XRDC2_MRC_MRGD_W0 */ +#define XRDC2_MRC_MRGD_W0_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W0 */ +#define XRDC2_MRC_MRGD_W0_COUNT2 (32U) + +/*! @name MRC_MRGD_W1 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W1_SRTADDR_MASK (0xFU) +#define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT (0U) +#define XRDC2_MRC_MRGD_W1_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK) + +/* The count of XRDC2_MRC_MRGD_W1 */ +#define XRDC2_MRC_MRGD_W1_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W1 */ +#define XRDC2_MRC_MRGD_W1_COUNT2 (32U) + +/*! @name MRC_MRGD_W2 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W2_ENDADDR_MASK (0xFFFFF000U) +#define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT (12U) +#define XRDC2_MRC_MRGD_W2_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK) + +/* The count of XRDC2_MRC_MRGD_W2 */ +#define XRDC2_MRC_MRGD_W2_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W2 */ +#define XRDC2_MRC_MRGD_W2_COUNT2 (32U) + +/*! @name MRC_MRGD_W3 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W3_ENDADDR_MASK (0xFU) +#define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT (0U) +#define XRDC2_MRC_MRGD_W3_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK) + +/* The count of XRDC2_MRC_MRGD_W3 */ +#define XRDC2_MRC_MRGD_W3_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W3 */ +#define XRDC2_MRC_MRGD_W3_COUNT2 (32U) + +/*! @name MRC_MRGD_W4 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W4_RMSG_MASK (0xFU) +#define XRDC2_MRC_MRGD_W4_RMSG_SHIFT (0U) +#define XRDC2_MRC_MRGD_W4_RMSG(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W4_RMSG_SHIFT)) & XRDC2_MRC_MRGD_W4_RMSG_MASK) +#define XRDC2_MRC_MRGD_W4_DET_MASK (0x10000000U) +#define XRDC2_MRC_MRGD_W4_DET_SHIFT (28U) +#define XRDC2_MRC_MRGD_W4_DET(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W4_DET_SHIFT)) & XRDC2_MRC_MRGD_W4_DET_MASK) + +/* The count of XRDC2_MRC_MRGD_W4 */ +#define XRDC2_MRC_MRGD_W4_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W4 */ +#define XRDC2_MRC_MRGD_W4_COUNT2 (32U) + +/*! @name MRC_MRGD_W5 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W5_D0ACP_MASK (0x7U) +#define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT (0U) +#define XRDC2_MRC_MRGD_W5_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D1ACP_MASK (0x38U) +#define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT (3U) +#define XRDC2_MRC_MRGD_W5_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D2ACP_MASK (0x1C0U) +#define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT (6U) +#define XRDC2_MRC_MRGD_W5_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D3ACP_MASK (0xE00U) +#define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT (9U) +#define XRDC2_MRC_MRGD_W5_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D4ACP_MASK (0x7000U) +#define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT (12U) +#define XRDC2_MRC_MRGD_W5_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D5ACP_MASK (0x38000U) +#define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT (15U) +#define XRDC2_MRC_MRGD_W5_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D6ACP_MASK (0x1C0000U) +#define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT (18U) +#define XRDC2_MRC_MRGD_W5_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK) +#define XRDC2_MRC_MRGD_W5_D7ACP_MASK (0xE00000U) +#define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT (21U) +#define XRDC2_MRC_MRGD_W5_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK) +#define XRDC2_MRC_MRGD_W5_EALO_MASK (0xF000000U) +#define XRDC2_MRC_MRGD_W5_EALO_SHIFT (24U) +#define XRDC2_MRC_MRGD_W5_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK) + +/* The count of XRDC2_MRC_MRGD_W5 */ +#define XRDC2_MRC_MRGD_W5_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W5 */ +#define XRDC2_MRC_MRGD_W5_COUNT2 (32U) + +/*! @name MRC_MRGD_W6 - Memory Region Descriptor */ +#define XRDC2_MRC_MRGD_W6_D8ACP_MASK (0x7U) +#define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT (0U) +#define XRDC2_MRC_MRGD_W6_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D9ACP_MASK (0x38U) +#define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT (3U) +#define XRDC2_MRC_MRGD_W6_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D10ACP_MASK (0x1C0U) +#define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT (6U) +#define XRDC2_MRC_MRGD_W6_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D11ACP_MASK (0xE00U) +#define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT (9U) +#define XRDC2_MRC_MRGD_W6_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D12ACP_MASK (0x7000U) +#define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT (12U) +#define XRDC2_MRC_MRGD_W6_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D13ACP_MASK (0x38000U) +#define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT (15U) +#define XRDC2_MRC_MRGD_W6_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D14ACP_MASK (0x1C0000U) +#define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT (18U) +#define XRDC2_MRC_MRGD_W6_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK) +#define XRDC2_MRC_MRGD_W6_D15ACP_MASK (0xE00000U) +#define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT (21U) +#define XRDC2_MRC_MRGD_W6_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK) +#define XRDC2_MRC_MRGD_W6_EAL_MASK (0x3000000U) +#define XRDC2_MRC_MRGD_W6_EAL_SHIFT (24U) +#define XRDC2_MRC_MRGD_W6_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK) +#define XRDC2_MRC_MRGD_W6_DL2_MASK (0x60000000U) +#define XRDC2_MRC_MRGD_W6_DL2_SHIFT (29U) +#define XRDC2_MRC_MRGD_W6_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK) +#define XRDC2_MRC_MRGD_W6_VLD_MASK (0x80000000U) +#define XRDC2_MRC_MRGD_W6_VLD_SHIFT (31U) +#define XRDC2_MRC_MRGD_W6_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK) + +/* The count of XRDC2_MRC_MRGD_W6 */ +#define XRDC2_MRC_MRGD_W6_COUNT (32U) + +/* The count of XRDC2_MRC_MRGD_W6 */ +#define XRDC2_MRC_MRGD_W6_COUNT2 (32U) + + +/*! + * @} + */ /* end of group XRDC2_Register_Masks */ + + +/* XRDC2 - Peripheral instance base addresses */ +/** Peripheral XRDC2 base address */ +#define XRDC2_BASE (0u) +/** Peripheral d_ip_xrdc2_syn base pointer */ +#define XRDC2 ((XRDC2_Type *)XRDC2_BASE) +/** Array initializer of XRDC2 peripheral base addresses */ +#define XRDC2_BASE_ADDRS { XRDC2_BASE } +/** Array initializer of XRDC2 peripheral base pointers */ +#define XRDC2_BASE_PTRS { XRDC2 } + +/*! + * @} + */ /* end of group XRDC2_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* XRDC2_H */ + diff --git a/platform/devices/MX8/fsl_bitaccess.h b/platform/devices/MX8/fsl_bitaccess.h new file mode 100755 index 0000000..1757e0b --- /dev/null +++ b/platform/devices/MX8/fsl_bitaccess.h @@ -0,0 +1,204 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file + * + * Header file containing register access macros. + * + * \addtogroup Peripheral_access_layer (HAL) Device Peripheral Access Layer + * + * @{ + */ + +#ifndef FSL_BITACCESS_H +#define FSL_BITACCESS_H + +/*! + * @addtogroup SCF Register Access Macros + * @{ + */ + +#include +#include + +/******************************************************************************* + * Macros for generic register access + ******************************************************************************/ + +#define wr_l(a,v) (*(volatile uint32_t *)(a) = (v)) +#define rd_l(a) (*(volatile uint32_t *)(a)) + +#define WRITE32(a,v) (*(volatile uint32_t *)(a) = (v)) +#define READ32(a) (*(volatile uint32_t *)(a)) + +/* + * Macros for single instance registers + */ + +#define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) +#define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) +#define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) + +#define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) +#define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) +#define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) + +#define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) +#define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym + +#define BF_RD(reg, field) HW_##reg.B.field +#define BF_WR(reg, field, v) BW_##reg##_##field(v) + + +/******************************************************************************* + * Macros to create bitfield mask, shift, and width from CMSIS definitions + ******************************************************************************/ + +/* Bitfield Mask */ +#define SCF_BMSK(bitfield) (bitfield ## _MASK) + +/* Bitfield Left Shift */ +#define SCF_BLSH(bitfield) (bitfield ## _SHIFT) + +/* Bitfield Value */ +#define SCF_BVAL(bitfield, val) ((val) << (SCF_BLSH(bitfield))) + + +/******************************************************************************* + * Macros to set, clear, extact, and insert bitfields into register structures + * or local variables + ******************************************************************************/ + +/* Bitfield Set */ +#define SCF_BSET(var, bitfield) ((var) |= (SCF_BMSK(bitfield))) + +/* Bitfield Clear */ +#define SCF_BCLR(var, bitfield) ((var) &= (~(SCF_BMSK(bitfield)))) + +/* Multi Bitfield Set */ +#define SCF_MSET(var, bitfield) ((var) |= (bitfield)) + +/* Multi Bitfield Clear */ +#define SCF_MCLR(var, bitfield) ((var) &= ~(bitfield)) + +/* Bitfield Extract */ +#define SCF_BEXR(var, bitfield) (((var) & (SCF_BMSK(bitfield))) >> (SCF_BLSH(bitfield))) + +/* Bitfield Insert */ +#define SCF_BINS(var, bitfield, val) ((var) = ((var) & (~(SCF_BMSK(bitfield)))) | SCF_BVAL(bitfield, (val))) + +/* Clear bit using write-1-to-clear */ +#define SCF_W1C(var, bitfield) ((var) = (SCF_BMSK(bitfield))) + +#define BSET32(X,Y) \ + *((volatile uint32_t *)(X)) = ((*((volatile uint32_t *)(X))) | (Y)) +#define BCLR32(X,Y) \ + *((volatile uint32_t *)(X)) = ((*((volatile uint32_t *)(X))) & ~(Y)) +#define CAST32(X) (*( volatile uint32_t *)(X)) + +static inline void WAIT_REM32(uint32_t regis, uint32_t val, uint32_t mask, + uint16_t read_attempts) +{ + /* Loop until value */ + while((*((volatile uint32_t *)regis) & mask) != val) + { + ; /* Intentional empty while */ + } +} + +static inline void WRM32(uint32_t address, uint32_t write_data, uint32_t mask) +{ + /* Write long */ + wr_l(address, ((rd_l(address) & ~mask) | (write_data & mask))); +} + +/******************************************************************************* + * Macros to set, clear, extact, and insert bitfields into register structures + * that support SCT + ******************************************************************************/ + +#ifdef NO_DEVICE_ACCESS +/* Simulation does not have SCT hardware and must fallback to non-SCT definitions */ + +/* SCT Bitfield Set */ +#define SCF_SCT_BSET(var, bitfield) (SCF_BSET((var).RW, bitfield)) + +/* SCT Bitfield Clear */ +#define SCF_SCT_BCLR(var, bitfield) (SCF_BCLR((var).RW, bitfield)) + +/* SCT Multi Bitfield Set */ +#define SCF_SCT_MSET(var, bitfield) (SCF_MSET((var).RW, bitfield)) + +/* SCT Multi Bitfield Set */ +#define SCF_SCT_MCLR(var, bitfield) (SCF_MCLR((var).RW, bitfield)) + +/* SCT Bitfield Insert */ +#define SCF_SCT_BINS(var, bitfield, val) (SCF_BINS((var).RW, (bitfield), (val))) + +#else +/* SCT Bitfield Set */ +#define SCF_SCT_BSET(var, bitfield) ((var).SET = SCF_BMSK(bitfield)) + +/* SCT Bitfield Clear */ +#define SCF_SCT_BCLR(var, bitfield) ((var).CLR = SCF_BMSK(bitfield)) + +/* SCT Multi Bitfield Set */ +#define SCF_SCT_MSET(var, bitfield) ((var).SET = (bitfield)) + +/* SCT Multi Bitfield Set */ +#define SCF_SCT_MCLR(var, bitfield) ((var).CLR = (bitfield)) + +/* SCT Bitfield Insert */ +#define SCF_SCT_BINS(var, bitfield, val) (SCF_BINS((var).RW, (bitfield), (val))) + +#endif /* NO_DEVICE_ACCESS */ + +/*! + * @} + */ /* end of group SCF */ + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + +#endif /* FSL_BITACCESS_H */ + +/******************************************************************************/ diff --git a/platform/devices/MX8DXL/MX8DXL.h b/platform/devices/MX8DXL/MX8DXL.h new file mode 100755 index 0000000..26b1d81 --- /dev/null +++ b/platform/devices/MX8DXL/MX8DXL.h @@ -0,0 +1,651 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8DXL.h + * @version 1.7 + * @date 2015-05-16 + * @brief CMSIS Peripheral Access Layer for MX8DXL + * + * CMSIS Peripheral Access Layer for MX8DXL + */ + +#ifndef MX8DXL_H +#define MX8DXL_H /**< Symbol preventing repeated inclusion */ + +/* Check for valid CPU versions */ +#if !defined(SREV_A0) && !defined(SREV_A1) + #error "Invalid SOC revision!\n" +#endif + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0007U + + +/* ---------------------------------------------------------------------------- + -- Memory Map (SC perspective) + ---------------------------------------------------------------------------- */ + +#define LSIO_SS_BASE1 0x00000000U /* LSIO SS - slot 1 */ +#define OCRAM_ALIAS_BASE (LSIO_SS_BASE1+0x000000U) /* OCRAM alias */ +#define SC_ROM_BASE 0x00000000U /* SC ROM */ +#define OCRAM_BASE (LSIO_SS_BASE1+0x100000U) /* OCRAM */ +#define FSPI0_MEM_BASE (LSIO_SS_BASE1+0x8000000U) /* FlexSPI0 Memory */ +#define TCML_BASE 0x1FFE0000U /* SC TCML */ +#define TCMU_BASE 0x20000000U /* SC TCMU */ +#define CAAM_BASE 0x20400000U /* SC CAAM */ +#define ADM_BASE 0x20520000U /* SC ADM */ +#define OTP_BASE 0x20530000U /* SC OTP */ +#define SNVS_BASE 0x20540000U /* SC SNVS */ +#define MU0_BASE 0x20550000U /* SECO MU 1 */ +#define V2X_SS_BASE1 0x2C000000U /* V2X */ +#define MU7_BASE (V2X_SS_BASE1+0x000000U) /* V2X MU APP0 */ +#define MU8_BASE (V2X_SS_BASE1+0x010000U) /* V2X MU APP1 */ +#define MU9_BASE (V2X_SS_BASE1+0x020000U) /* V2X MU SHE */ +#define MU10_BASE (V2X_SS_BASE1+0x030000U) /* V2X MU HSM1 */ +#define MU11_BASE (V2X_SS_BASE1+0x040000U) /* V2X MU MSH2 */ +#define MU12_BASE (V2X_SS_BASE1+0x050000U) /* V2X MU SCU/DEBUG */ +#define SCU_SS_BASE0 0x30000000U /* SCU SS - slot 0 */ +#define TCML0_BASE (SCU_SS_BASE0+0x00FE0000U) /* SCU TCML */ +#define TCMU0_BASE (SCU_SS_BASE0+0x01000000U) /* SCU TCMU */ +#define MCU_0_SS_BASE0 0x34000000U /* MCU 0 SS - slot 0 */ +#define TCML1_BASE (MCU_0_SS_BASE0+0x0FE0000U) /* MCU 0 TCML */ +#define TCMU1_BASE (MCU_0_SS_BASE0+0x1000000U) /* MCU 0 TCMU */ +#define RGPIOB_BASE (MCU_0_SS_BASE0+0x30F0000U) /* MCU 0 RGPIO */ +#define LPUART1_BASE (MCU_0_SS_BASE0+0x3220000U) /* MCU 0 LPUART */ +#define LPI2C1_BASE (MCU_0_SS_BASE0+0x3230000U) /* MCU 0 LPI2C */ +#define WDOG1_BASE (MCU_0_SS_BASE0+0x3420000U) /* MCU 0 WDOG */ +#define MU13_BASE (MCU_0_SS_BASE0+0x3480000U) /* MCU 0 MU 1A */ +#define SYSCTR_CTRL_BASE 0x40000000U /* SC SYSCTR Control */ +#define SYSCTR_RD_BASE 0x40010000U /* SC SYSCTR Read */ +#define SYSCTR_CMP_BASE 0x40020000U /* SC SYSCTR Compare 0 */ +#define SYSCTR_CMP1_BASE 0x40020100U /* SC SYSCTR Compare 1 */ +#define LPC_BASE 0x40070000U /* SC LPC */ +#define CSGPR_BASE 0x40470000U /* CoreSight GPR */ +#define AP_1_DEBUG_APB_BASE 0x40600000U /* AP_1 Debug APB */ +#define AP_0_DEBUG_APB_BASE 0x40800000U /* AP_0 Debug APB */ +#define AP_2_DEBUG_APB_BASE 0x40800000U /* AP_2 Debug APB */ +#define RGPIOA_BASE 0x410F0000U /* SC RGPIO */ +#define LPIT0_BASE 0x41210000U /* SC LPIT */ +#define LPUART0_BASE 0x41220000U /* SC LPUART */ +#define LPI2C0_BASE 0x41230000U /* SC LPI2C */ +#define ASMC_BASE 0x41410000U /* SC ASMC */ +#define WDOG0_BASE 0x41420000U /* SC WDOG */ +#define MU1_BASE 0x41430000U /* SC MU 0B */ +#define MU2_BASE 0x41440000U /* SC MU 0A0 */ +#define MU3_BASE 0x41450000U /* SC MU 0A1 */ +#define MU4_BASE 0x41460000U /* SC MU 0A2 */ +#define MU5_BASE 0x41470000U /* SC MU 0A3 */ +#define MU6_BASE 0x41480000U /* SC MU 1A */ +#define MSI0_BASE 0x41800000U /* SC DSC MSI Ring 0 */ +#define DSC1_BASE 0x41820000U /* SC SC DSC */ +#define REP2_BASE 0x4182B000U /* SC MBIST MTR */ +#define MSI1_BASE 0x41A00000U /* SC DSC MSI Ring 1 */ +#define DSC19_BASE 0x41A60000U /* SC ADMA DSC */ +#define DSC22_BASE 0x41AC0000U /* SC MCU_0 DSC */ +#define DSC25_BASE 0x41B20000U /* SC CONN DSC */ +#define MSI2_BASE 0x41C00000U /* SC DSC MSI Ring 2 */ +#define DSC36_BASE 0x41C80000U /* SC DRC_0 DSC */ +#define DSC38_BASE 0x41CC0000U /* SC HSIO DSC */ +#define MSI3_BASE 0x41E00000U /* SC DSC MSI Ring 3 */ +#define DSC50_BASE 0x41E40000U /* SC DB DSC */ +#define DSC53_BASE 0x41EA0000U /* SC AP_2 DSC */ +#define DSC56_BASE 0x41F00000U /* SC LSIO DSC */ +#define PAD_BASE 0x41F80000U /* SC Pad */ +#define MSI4_BASE 0x41F9F000U /* SC Pad MSI Ring 0 */ +#define MSI5_BASE 0x41FBF000U /* SC Pad MSI Ring 1 */ +#define MSI6_BASE 0x41FDF000U /* SC Pad MSI Ring 2 */ +#define MSI7_BASE 0x41FFF000U /* SC Pad MSI Ring 3 */ +#define ADMA_SS_BASE2 0x51000000U /* ADMA SS - slot 2 */ +#define IRQSTR_SCU_BASE (ADMA_SS_BASE2+0x060000U) /* IRQSTR.SCU1 */ +#define GIC0_BASE (ADMA_SS_BASE2+0xA00000U) /* GIC 0 */ +#define ADMA_SS_BASE0 0x59000000U /* ADMA SS - slot 0 */ +#define DMA0_BASE (ADMA_SS_BASE0+0x1F0000U) /* ADMA eDMA 0 MP */ +#define ADMA_SS_BASE1 0x5A000000U /* ADMA SS - slot 1 */ +#define LPUART2_BASE (ADMA_SS_BASE1+0x060000U) /* ADMA LPUART 0 */ +#define LPUART3_BASE (ADMA_SS_BASE1+0x070000U) /* ADMA LPUART 1 */ +#define LPUART4_BASE (ADMA_SS_BASE1+0x080000U) /* ADMA LPUART 2 */ +#define LPUART5_BASE (ADMA_SS_BASE1+0x090000U) /* ADMA LPUART 3 */ +#define DMA1_BASE (ADMA_SS_BASE1+0x1F0000U) /* ADMA eDMA 2 MP */ +#define LPI2C2_BASE (ADMA_SS_BASE1+0x800000U) /* ADMA LPI2C 0 */ +#define LPI2C3_BASE (ADMA_SS_BASE1+0x810000U) /* ADMA LPI2C 1 */ +#define LPI2C4_BASE (ADMA_SS_BASE1+0x820000U) /* ADMA LPI2C 2 */ +#define LPI2C5_BASE (ADMA_SS_BASE1+0x830000U) /* ADMA LPI2C 3 */ +#define DMA2_BASE (ADMA_SS_BASE1+0x9F0000U) /* ADMA eDMA 3 MP */ +#define CONN_SS_BASE0 0x5B000000U /* CONN SS - slot 0 */ +#define SDHC0_BASE (CONN_SS_BASE0+0x010000U) /* CONN SDHC 0 */ +#define SDHC1_BASE (CONN_SS_BASE0+0x020000U) /* CONN SDHC 1 */ +#define SDHC2_BASE (CONN_SS_BASE0+0x030000U) /* CONN SDHC 2 */ +#define ENET0_BASE (CONN_SS_BASE0+0x040000U) /* CONN ENET 0 */ +#define ENET1_BASE (CONN_SS_BASE0+0x050000U) /* CONN ENET 1 */ +#define USB_0_BASE (CONN_SS_BASE0+0x0D0000U) /* CONN USB 0 */ +#define USB_1_BASE (CONN_SS_BASE0+0x0E0000U) /* CONN USB 1 */ +#define USB_0_PHY_BASE (CONN_SS_BASE0+0x100000U) /* CONN USB 0 PHY */ +#define USB_1_PHY_BASE (CONN_SS_BASE0+0x110000U) /* CONN USB 1 PHY */ +#define ENET0_LPCG (CONN_SS_BASE0+0x230000U) /* CONN ENET 0 LPCG */ +#define NAND_BASE (CONN_SS_BASE0+0x810000U) /* CONN NAND */ +#define DB_SS_BASE0 0x5C000000U /* DB SS - slot 0 */ +#define DRC_LPCG_2 (DB_SS_BASE0+0x080000U) /* DRC LPCG 2 */ +#define DRC_LPCG_4 (DB_SS_BASE0+0x0B0000U) /* DRC LPCG 4 */ +#define DRC_LPCG_0 (DB_SS_BASE0+0x0C0000U) /* DRC LPCG 0 */ +#define DRC_LPCG_1 (DB_SS_BASE0+0x0D0000U) /* DRC LPCG 1 */ +#define DRC_LPCG_3 (DB_SS_BASE0+0x0F0000U) /* DRC LPCG 3 */ +#define DB_NIC0_GPV (DB_SS_BASE0+0x400000U) /* DB NIC0 GPV */ +#define DB_LPCG_PG0_BASE (DB_SS_BASE0+0x4F0000U) /* DB PG0 LPCG */ +#define DB_LPCG_PG1_BASE (DB_SS_BASE0+0x5F0000U) /* DB PG1 LPCG */ +#define DB_LPCG_PG2_BASE (DB_SS_BASE0+0x6F0000U) /* DB PG2 LPCG */ +#define DB_LPCG_BN_BASE (DB_SS_BASE0+0xAF0000U) /* DB BN LPCG */ +#define LSIO_SS_BASE0 0x5D000000U /* LSIO SS - slot 0 */ +#define PWM0_BASE (LSIO_SS_BASE0+0x000000U) /* LSIO PWM 0 */ +#define PWM1_BASE (LSIO_SS_BASE0+0x010000U) /* LSIO PWM 1 */ +#define PWM2_BASE (LSIO_SS_BASE0+0x020000U) /* LSIO PWM 2 */ +#define PWM3_BASE (LSIO_SS_BASE0+0x030000U) /* LSIO PWM 3 */ +#define PWM4_BASE (LSIO_SS_BASE0+0x040000U) /* LSIO PWM 4 */ +#define PWM5_BASE (LSIO_SS_BASE0+0x050000U) /* LSIO PWM 5 */ +#define PWM6_BASE (LSIO_SS_BASE0+0x060000U) /* LSIO PWM 6 */ +#define PWM7_BASE (LSIO_SS_BASE0+0x070000U) /* LSIO PWM 7 */ +#define GPIO0_BASE (LSIO_SS_BASE0+0x080000U) /* LSIO GPIO 0 */ +#define GPIO1_BASE (LSIO_SS_BASE0+0x090000U) /* LSIO GPIO 1 */ +#define GPIO2_BASE (LSIO_SS_BASE0+0x0A0000U) /* LSIO GPIO 2 */ +#define GPIO3_BASE (LSIO_SS_BASE0+0x0B0000U) /* LSIO GPIO 3 */ +#define GPIO4_BASE (LSIO_SS_BASE0+0x0C0000U) /* LSIO GPIO 4 */ +#define GPIO5_BASE (LSIO_SS_BASE0+0x0D0000U) /* LSIO GPIO 5 */ +#define GPIO6_BASE (LSIO_SS_BASE0+0x0E0000U) /* LSIO GPIO 6 */ +#define GPIO7_BASE (LSIO_SS_BASE0+0x0F0000U) /* LSIO GPIO 7 */ +#define FSPI0_BASE (LSIO_SS_BASE0+0x120000U) /* FSPI0 */ +#define FSPI1_BASE (LSIO_SS_BASE0+0x130000U) /* FSPI1 */ +#define GPT0_BASE (LSIO_SS_BASE0+0x140000U) /* LSIO GPT 0 */ +#define GPT1_BASE (LSIO_SS_BASE0+0x150000U) /* LSIO GPT 1 */ +#define GPT2_BASE (LSIO_SS_BASE0+0x160000U) /* LSIO GPT 2 */ +#define GPT3_BASE (LSIO_SS_BASE0+0x170000U) /* LSIO GPT 3 */ +#define GPT4_BASE (LSIO_SS_BASE0+0x180000U) /* LSIO GPT 4 */ +#define KPP_BASE (LSIO_SS_BASE0+0x1A0000U) /* LSIO KPP */ +#define MU14_BASE (LSIO_SS_BASE0+0x1B0000U) /* LSIO MU 0A */ +#define MU15_BASE (LSIO_SS_BASE0+0x1C0000U) /* LSIO MU 1A */ +#define MU16_BASE (LSIO_SS_BASE0+0x1D0000U) /* LSIO MU 2A */ +#define MU17_BASE (LSIO_SS_BASE0+0x1E0000U) /* LSIO MU 3A */ +#define MU18_BASE (LSIO_SS_BASE0+0x1F0000U) /* LSIO MU 4A */ +#define IEE_BASE (LSIO_SS_BASE0+0x320000U) /* IEE */ +#define IEE_R0_BASE (LSIO_SS_BASE0+0x330000U) /* IEE R0 */ +#define IEE_R1_BASE (LSIO_SS_BASE0+0x340000U) /* IEE R1 */ +#define HSIO_0_SS_BASE0 0x5F000000U /* HSIO 0 SS - slot 0 */ +#define HSIO_0_LPCG_GPIO (HSIO_0_SS_BASE0+0x100000U) /* HSIO 0 GPIO LPCG */ +#define HSIO_0_SS_BASE2 0x70000000U /* HSIO 0 SS - slot 2 */ +#define DDR_BASE0 0x80000000U /* DDR */ +#define MCM_BASE 0xE0080000U /* SC MCM */ +#define LMEM_BASE 0xE0082000U /* SC LMEM */ +#define DDR_BASE0_END 0xFFFFFFFFU /* Top of DDR 0 */ +#define LSIO_SS_BASE2 0x400000000ULL /* LSIO SS - slot 2 */ +#define FSPI1_MEM_BASE (LSIO_SS_BASE2+0x0U) /* FlexSPI1 Memory */ +#define DDR_BASE1 0x880000000ULL /* DDR - high mem */ +#define DDR_BASE1_END 0xFFFFFFFFFULL /* Top of DDR 1 */ + +/* Unused */ + +#define DSC2_BASE 0 +#define DSC3_BASE 0 +#define DSC4_BASE 0 +#define DSC5_BASE 0 +#define DSC6_BASE 0 +#define DSC7_BASE 0 +#define DSC8_BASE 0 +#define DSC9_BASE 0 +#define DSC10_BASE 0 +#define DSC11_BASE 0 +#define DSC12_BASE 0 +#define DSC13_BASE 0 +#define DSC14_BASE 0 +#define DSC15_BASE 0 +#define DSC17_BASE 0 +#define DSC18_BASE 0 +#define DSC20_BASE 0 +#define DSC21_BASE 0 +#define DSC23_BASE 0 +#define DSC24_BASE 0 +#define DSC26_BASE 0 +#define DSC27_BASE 0 +#define DSC28_BASE 0 +#define DSC29_BASE 0 +#define DSC30_BASE 0 +#define DSC31_BASE 0 +#define DSC33_BASE 0 +#define DSC34_BASE 0 +#define DSC35_BASE 0 +#define DSC37_BASE 0 +#define DSC39_BASE 0 +#define DSC40_BASE 0 +#define DSC41_BASE 0 +#define DSC42_BASE 0 +#define DSC43_BASE 0 +#define DSC44_BASE 0 +#define DSC45_BASE 0 +#define DSC46_BASE 0 +#define DSC47_BASE 0 +#define DSC49_BASE 0 +#define DSC51_BASE 0 +#define DSC52_BASE 0 +#define DSC54_BASE 0 +#define DSC55_BASE 0 +#define DSC57_BASE 0 +#define DSC58_BASE 0 +#define DSC59_BASE 0 +#define DSC60_BASE 0 +#define DSC61_BASE 0 +#define DSC62_BASE 0 +#define DSC63_BASE 0 +#define WDOG2_BASE 0 +#define RGPIOC_BASE 0 +#define LPI2C6_BASE 0 +#define LPI2C7_BASE 0 +#define LPI2C8_BASE 0 +#define LPI2C9_BASE 0 +#define LPI2C10_BASE 0 +#define LPI2C11_BASE 0 +#define LPI2C12_BASE 0 +#define LPI2C13_BASE 0 +#define LPI2C14_BASE 0 +#define LPI2C15_BASE 0 +#define LPI2C16_BASE 0 +#define LPI2C17_BASE 0 +#define LPI2C18_BASE 0 +#define LPI2C19_BASE 0 +#define LPI2C20_BASE 0 +#define LPI2C21_BASE 0 +#define LPI2C22_BASE 0 +#define LPI2C23_BASE 0 +#define LPI2C24_BASE 0 +#define LPI2C25_BASE 0 +#define LPUART6_BASE 0 +#define LPUART7_BASE 0 +#define LPUART8_BASE 0 +#define DMA3_BASE 0 +#define DMA4_BASE 0 +#define DMA5_BASE 0 +#define DMA6_BASE 0 +#define ISI0_BASE 0 +#define ISI1_BASE 0 +#define ISI2_BASE 0 +#define ISI3_BASE 0 +#define ISI4_BASE 0 +#define ISI5_BASE 0 +#define ISI6_BASE 0 +#define ISI7_BASE 0 +#define ISI8_BASE 0 +#define ISI9_BASE 0 +#define ISI10_BASE 0 +#define ISI11_BASE 0 +#define ISI12_BASE 0 +#define ISI13_BASE 0 +#define ISI14_BASE 0 +#define ISI15_BASE 0 +#define ISI16_BASE 0 +#define ISI17_BASE 0 +#define ISI18_BASE 0 +#define ISI19_BASE 0 +#define ISI20_BASE 0 +#define ISI21_BASE 0 +#define ISI22_BASE 0 +#define ISI23_BASE 0 +#define MU19_BASE 0 +#define MU20_BASE 0 +#define MU21_BASE 0 +#define MU22_BASE 0 +#define MU23_BASE 0 +#define MU24_BASE 0 +#define STC0_BASE 0 +#define STC1_BASE 0 +#define STC2_BASE 0 +#define STC3_BASE 0 +#define STC4_BASE 0 +#define STC5_BASE 0 +#define STC6_BASE 0 +#define STC7_BASE 0 +#define STC8_BASE 0 +#define STC9_BASE 0 +#define STC10_BASE 0 +#define STC11_BASE 0 +#define STC12_BASE 0 +#define STC13_BASE 0 +#define STC14_BASE 0 +#define STC15_BASE 0 +#define STC16_BASE 0 +#define STC17_BASE 0 +#define STC18_BASE 0 +#define STC19_BASE 0 +#define STC20_BASE 0 +#define STC21_BASE 0 +#define STC22_BASE 0 +#define STC23_BASE 0 + + +/* ---------------------------------------------------------------------------- + -- Device Mapping + ---------------------------------------------------------------------------- */ + +#define DMA_AUDIO0 DMA0 +#define DMA_PERIPH0 DMA1 +#define DMA_PERIPH1 DMA2 +#define DSC_SC DSC1 +#define DSC_ADMA DSC19 +#define DSC_MCU_0 DSC22 +#define DSC_CONN DSC25 +#define DSC_DRC_0 DSC36 +#define DSC_HSIO DSC38 +#define DSC_DB DSC50 +#define DSC_AP_2 DSC53 +#define DSC_LSIO DSC56 +#define GPIO_SC RGPIOA +#define GPIO_MCU_0 RGPIOB +#define LPI2C_SC LPI2C0 +#define LPI2C_MCU_0 LPI2C1 +#define LPI2C_0 LPI2C2 +#define LPI2C_1 LPI2C3 +#define LPI2C_2 LPI2C4 +#define LPI2C_3 LPI2C5 +#define LPIT_SC LPIT0 +#define LPUART_SC LPUART0 +#define LPUART_MCU_0 LPUART1 +#define LPUART_0 LPUART2 +#define LPUART_1 LPUART3 +#define LPUART_2 LPUART4 +#define LPUART_3 LPUART5 +#define MU_SECO MU0 +#define MU_SC_0B MU1 +#define MU_SC_0A0 MU2 +#define MU_SC_0A1 MU3 +#define MU_SC_0A2 MU4 +#define MU_SC_0A3 MU5 +#define MU_SC_1A MU6 +#define MU_V2X_0A MU7 +#define MU_V2X_1A MU8 +#define MU_V2X_2A MU9 +#define MU_V2X_3A MU10 +#define MU_V2X_4A MU11 +#define MU_V2X MU12 +#define MU_MCU_0_1A MU13 +#define MU_LSIO_0A MU14 +#define MU_LSIO_1A MU15 +#define MU_LSIO_2A MU16 +#define MU_LSIO_3A MU17 +#define MU_LSIO_4A MU18 +#define TCMU_SC TCMU0_BASE +#define TCMU_MCU_0 TCMU1_BASE +#define TCML_SC TCML0_BASE +#define TCML_MCU_0 TCML1_BASE +#define WDOG_SC WDOG0 +#define WDOG_MCU_0 WDOG1 + +/* ---------------------------------------------------------------------------- + -- CoreSight Granular Power Requestor Mappings + ---------------------------------------------------------------------------- */ +#define CSGPR_CPWRUPREQ (CSGPR_BASE+0x000U) +#define CSGPR_CPWRUPACK (CSGPR_BASE+0x004U) +#define CSGPR_CLAIMSET (CSGPR_BASE+0xFA0U) +#define CSGPR_CLAIMCLR (CSGPR_BASE+0xFA4U) +#define CSGPR_LAR (CSGPR_BASE+0xFB0U) +#define CSGPR_LSR (CSGPR_BASE+0xFB4U) + +#define CSGPR_IDX_A35 5U +#define CSGPR_IDX_MCU_0 6U + +#define CSGPR_XOR_DSC_REG 1U +#define CSGPR_XOR_DSC_MASK 0x0000FFFFU +#define CSGPR_ACK_DSC_REG 2U +#define CSGPR_ACK_DSC_MASK 0xFFFF0000U + +/* ---------------------------------------------------------------------------- + -- GIC Mappings + ---------------------------------------------------------------------------- */ +#define GICD_BASE (GIC0_BASE+0x000000U) +#define GICR_BASE (GIC0_BASE+0x100000U) + +#define GICD_CTLR_OFS (0x0000U) +#define GICD_CTLR_RWP_MASK (0x80000000U) + +#define GICR_WAKER_OFS (0x0014U) +#define GICR_WAKER_PA_MASK (0x00000002U) +#define GICR_WAKER_CA_MASK (0x00000004U) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 256 /**< Number of interrupts in the Vector table */ + + /* Auxiliary constants */ +#define NotAvail_IRQn -128 /**< Not available device specific interrupt */ + + /* Core interrupts */ +#define NonMaskableInt_IRQn -14 /**< Non Maskable Interrupt */ +#define HardFault_IRQn -13 /**< Cortex-M4 SV Hard Fault Interrupt */ +#define MemoryManagement_IRQn -12 /**< Cortex-M4 Memory Management Interrupt */ +#define BusFault_IRQn -11 /**< Cortex-M4 Bus Fault Interrupt */ +#define UsageFault_IRQn -10 /**< Cortex-M4 Usage Fault Interrupt */ +#define SVCall_IRQn -5 /**< Cortex-M4 SV Call Interrupt */ +#define DebugMonitor_IRQn -4 /**< Cortex-M4 Debug Monitor Interrupt */ +#define PendSV_IRQn -2 /**< Cortex-M4 Pend SV Interrupt */ +#define SysTick_IRQn -1 /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ +#define Reserved0_IRQn 0 /**< Reserved interrupt */ +#define Reserved1_IRQn 1 /**< Reserved interrupt */ +#define Reserved2_IRQn 2 /**< Reserved interrupt */ +#define Reserved3_IRQn 3 /**< Reserved interrupt */ +#define Reserved4_IRQn 4 /**< Reserved interrupt */ +#define MCM_IRQn 5 /**< MCM interrupt */ +#define DebugWake_IRQn 6 /**< Debug wake interrupt */ +#define OCOTP_Bank0_IRQn 7 /**< OCOTP bank0 interrupt */ +#define Reserved8_IRQn 8 /**< Reserved interrupt */ +#define Reserved9_IRQn 9 /**< Reserved interrupt */ +#define INTMUX0_8_IRQn 10 /**< INTMUX0_8 interrupt */ +#define INTMUX0_9_IRQn 11 /**< INTMUX0_9 interrupt */ +#define INTMUX0_10_IRQn 12 /**< INTMUX0_10 interrupt */ +#define INTMUX0_11_IRQn 13 /**< INTMUX0_11 interrupt */ +#define INTMUX0_12_IRQn 14 /**< INTMUX0_12 interrupt */ +#define INTMUX0_13_IRQn 15 /**< INTMUX0_13 interrupt */ +#define INTMUX0_14_IRQn 16 /**< INTMUX0_14 interrupt */ +#define INTMUX0_15_IRQn 17 /**< INTMUX0_15 interrupt */ +#define Reserved18_IRQn 18 /**< Reserved interrupt */ +#define TPM0_IRQn 19 /**< TPM0 interrupt */ +#define Reserved20_IRQn 20 /**< Reserved interrupt */ +#define Reserved21_IRQn 21 /**< Reserved interrupt */ +#define LPIT0_IRQn 22 /**< LPIT0 interrupt */ +#define Reserved23_IRQn 23 /**< Reserved interrupt */ +#define Reserved24_IRQn 24 /**< Reserved interrupt */ +#define LPUART0_IRQn 25 /**< LPUART0 interrupt */ +#define Reserved26_IRQn 26 /**< Reserved interrupt */ +#define LPI2C0_IRQn 27 /**< LPI2C0 interrupt */ +#define Reserved28_IRQn 28 /**< Reserved interrupt */ +#define MU0_B0_IRQn 29 /**< MU0_B0 interrupt */ +#define SECO_MU_NMI_IRQn 30 /**< SECO_MU_NMI interrupt */ +#define SECO_MU_IRQn 31 /**< SECO_MU interrupt */ +#define INTMUX0_0_IRQn 32 /**< INTMUX0_0 interrupt */ +#define INTMUX0_1_IRQn 33 /**< INTMUX0_1 interrupt */ +#define INTMUX0_2_IRQn 34 /**< INTMUX0_2 interrupt */ +#define INTMUX0_3_IRQn 35 /**< INTMUX0_3 interrupt */ +#define INTMUX0_4_IRQn 36 /**< INTMUX0_4 interrupt */ +#define INTMUX0_5_IRQn 37 /**< INTMUX0_5 interrupt */ +#define INTMUX0_6_IRQn 38 /**< INTMUX0_6 interrupt */ +#define INTMUX0_7_IRQn 39 /**< INTMUX0_7 interrupt */ +#define SYSCTR_CMP3_IRQn 40 /**< SYSCTR_CMP3 interrupt */ +#define SYSCTR_CMP2_IRQn 41 /**< SYSCTR_CMP2 interrupt */ +#define SYSCTR_CMP1_IRQn 42 /**< SYSCTR_CMP1 interrupt */ +#define SYSCTR_CMP0_IRQn 43 /**< SYSCTR_CMP0 interrupt */ +#define MU0_B1_IRQn 44 /**< MU0_B1 interrupt */ +#define MU0_B2_IRQn 45 /**< MU0_B2 interrupt */ +#define MU0_B3_IRQn 46 /**< MU0_B3 interrupt */ +#define PMIC_INT_IRQn 47 /**< PMIC_INT interrupt */ +#define PMIC_EarlyWarning_IRQn 48 /**< PMIC_EarlyWarning interrupt */ +#define MU1_A_IRQn 49 /**< MU1_A interrupt */ +#define SWI_IRQn 50 /**< Software interrupt */ +#define Reserved51_IRQn 51 /**< Reserved interrupt */ +#define CAAM_IRQ0_IRQn 52 /**< CAAM_IRQ0 interrupt */ +#define CAAM_IRQ1_IRQn 53 /**< CAAM_IRQ1 interrupt */ +#define CAAM_IRQ2_IRQn 54 /**< CAAM_IRQ2 interrupt */ +#define CAAM_IRQ3_IRQn 55 /**< CAAM_IRQ3 interrupt */ +#define CAAM_RTIC_IRQn 56 /**< CAAM_RTIC interrupt */ +#define CAAM_Error_IRQn 57 /**< CAAM_Error interrupt */ +#define SNVS_Functional_IRQn 58 /**< SNVS_Functional interrupt */ +#define SNVS_SecurityViolation_IRQn 59 /**< SNVS_SecurityViolation interrupt */ +#define SNVS_Periodic_IRQn 60 /**< SNVS_Periodic interrupt */ +#define SNVS_Button_IRQn 61 /**< SNVS_Button interrupt */ +#define SNVS_Alarm_IRQn 62 /**< Reserved interrupt */ +#define SNVS_PowerOff_IRQn 63 /**< Reserved interrupt */ +#define DSC00_IRQn 64 /**< DSC0 interrupt */ +#define DSC_SCU_IRQn 64 /**< DSC0 interrupt */ +#define DSC_DB_IRQn 65 /**< DSC1 interrupt */ +#define DSC02_IRQn 66 /**< DSC2 interrupt */ +#define DSC03_IRQn 67 /**< DSC3 interrupt */ +#define DSC_HSIO_IRQn 68 /**< DSC4 interrupt */ +#define DSC05_IRQn 69 /**< DSC5 interrupt */ +#define DSC06_IRQn 70 /**< DSC6 interrupt */ +#define DSC_CM4_0_IRQn 71 /**< DSC7 interrupt */ +#define DSC08_IRQn 72 /**< DSC8 interrupt */ +#define DSC09_IRQn 73 /**< DSC9 interrupt */ +#define DSC_LSIO_IRQn 74 /**< DSC10 interrupt */ +#define DSC11_IRQn 75 /**< DSC11 interrupt */ +#define DSC_CA35_IRQn 76 /**< DSC12 interrupt */ +#define DSC13_IRQn 77 /**< DSC13 interrupt */ +#define DSC14_IRQn 78 /**< DSC14 interrupt */ +#define DSC15_IRQn 79 /**< DSC15 interrupt */ +#define DSC_Connectivity_IRQn 80 /**< DSC16 interrupt */ +#define DSC17_IRQn 81 /**< DSC17 interrupt */ +#define DSC18_IRQn 82 /**< DSC18 interrupt */ +#define DSC19_IRQn 83 /**< DSC19 interrupt */ +#define DSC20_IRQn 84 /**< DSC20 interrupt */ +#define DSC21_IRQn 85 /**< DSC21 interrupt */ +#define DSC_DRC_0_IRQn 86 /**< DSC22 interrupt */ +#define DSC23_IRQn 87 /**< DSC23 interrupt */ +#define DSC24_IRQn 88 /**< DSC24 interrupt */ +#define DSC25_IRQn 89 /**< DSC25 interrupt */ +#define DSC26_IRQn 90 /**< DSC26 interrupt */ +#define DSC27_IRQn 91 /**< DSC27 interrupt */ +#define DSC_ADMA_IRQn 92 /**< DSC28 interrupt */ +#define DSC29_IRQn 93 /**< DSC29 interrupt */ +#define DSC30_IRQn 94 /**< DSC30 interrupt */ +#define DSC31_IRQn 95 /**< DSC31 interrupt */ +#define IOMUX31_IRQn 96 /**< IOMUX31 interrupt */ +#define IOMUX30_IRQn 97 /**< IOMUX30 interrupt */ +#define IOMUX29_IRQn 98 /**< IOMUX29 interrupt */ +#define IOMUX28_IRQn 99 /**< IOMUX28 interrupt */ +#define IOMUX27_IRQn 100 /**< IOMUX27 interrupt */ +#define IOMUX26_IRQn 101 /**< IOMUX26 interrupt */ +#define IOMUX25_IRQn 102 /**< IOMUX25 interrupt */ +#define IOMUX24_IRQn 103 /**< IOMUX24 interrupt */ +#define IOMUX23_IRQn 104 /**< IOMUX23 interrupt */ +#define IOMUX22_IRQn 105 /**< IOMUX22 interrupt */ +#define IOMUX21_IRQn 106 /**< IOMUX21 interrupt */ +#define IOMUX20_IRQn 107 /**< IOMUX20 interrupt */ +#define IOMUX19_IRQn 108 /**< IOMUX19 interrupt */ +#define IOMUX18_IRQn 109 /**< IOMUX18 interrupt */ +#define IOMUX17_IRQn 110 /**< IOMUX17 interrupt */ +#define IOMUX16_IRQn 111 /**< IOMUX16 interrupt */ +#define IOMUX15_IRQn 112 /**< IOMUX15 interrupt */ +#define IOMUX14_IRQn 113 /**< IOMUX14 interrupt */ +#define IOMUX13_IRQn 114 /**< IOMUX13 interrupt */ +#define IOMUX12_IRQn 115 /**< IOMUX12 interrupt */ +#define IOMUX11_IRQn 116 /**< IOMUX11 interrupt */ +#define IOMUX10_IRQn 117 /**< IOMUX10 interrupt */ +#define IOMUX9_IRQn 118 /**< IOMUX9 interrupt */ +#define IOMUX8_IRQn 119 /**< IOMUX8 interrupt */ +#define IOMUX7_IRQn 120 /**< IOMUX7 interrupt */ +#define IOMUX6_IRQn 121 /**< IOMUX6 interrupt */ +#define IOMUX5_IRQn 122 /**< IOMUX5 interrupt */ +#define IOMUX4_IRQn 123 /**< IOMUX4 interrupt */ +#define IOMUX3_IRQn 124 /**< IOMUX3 interrupt */ +#define IOMUX2_IRQn 125 /**< IOMUX2 interrupt */ +#define IOMUX1_IRQn 126 /**< IOMUX1 interrupt */ +#define IOMUX0_IRQn 127 /**< IOMUX0 interrupt */ +#define NUM_NVIC_IRQn 128 /**< Number of NVIC interrupts */ + +typedef int IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex-M Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MX8DXL.h" /* Device specific configuration file */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t LDRD (const __IO uint32_t *addr) +{ + union + { + uint32_t w32[2]; + uint64_t w64; + } llr; + + __ASM volatile ("ldrd %0, %1, %2" : "=r" (llr.w32[0]), "=r" (llr.w32[1]) : "Q" (*addr) ); + + return(llr.w64); +} + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + +#endif /* MX8DXL_H */ + +/* MX8DXL.h, eof. */ diff --git a/platform/devices/MX8DXL/MX8DXL_features.h b/platform/devices/MX8DXL/MX8DXL_features.h new file mode 100755 index 0000000..87fdd21 --- /dev/null +++ b/platform/devices/MX8DXL/MX8DXL_features.h @@ -0,0 +1,461 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef MX8_FEATURES_H +#define MX8_FEATURES_H + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0U) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0U) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0U) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0U) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0U) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0U) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0U) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0U) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0U) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0U) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0U) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0U) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0U) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0U) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0U) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0U) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0U) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0U) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (1U) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0U) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0U) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0U) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0U) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (5U) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0U) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0U) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0U) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0U) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0U) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (1U) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0U) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0U) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0U) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0U) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0U) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0U) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0U) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0U) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0U) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0U) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (2U) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (8U) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0U) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (0U) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0U) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0U) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0U) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0U) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0U) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0U) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0U) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0U) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0U) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (1U) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0U) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0U) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0U) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6U) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0U) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (6U) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0U) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (1U) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0U) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0U) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0U) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0U) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0U) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0U) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0U) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0U) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0U) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0U) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0U) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (19U) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0U) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0U) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0U) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0U) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0U) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0U) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0U) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0U) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0U) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0U) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0U) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0U) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0U) +/* @brief QuadSPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPIO_COUNT (0U) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0U) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0U) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0U) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0U) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0U) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0U) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0U) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (0U) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0U) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0U) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0U) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0U) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0U) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1U) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0U) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0U) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0U) +/* @brief STC availability on the SoC. */ +#define FSL_FEATURE_SOC_STC_COUNT (12U) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0U) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0U) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0U) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0U) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0U) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0U) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0U) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0U) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0U) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0U) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0U) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0U) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0U) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2U) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0U) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0U) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0U) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0U) + +/* LMEM module features */ + +/* @brief Has process identifier support. */ +#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1U) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0U) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1U) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1U) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1U) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1U) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0U) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0U) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1U) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1U) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0U) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0U) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1U) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0U) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1U) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART_SC) ? (32) : \ + (((x) == LPUART_MCU_0) ? (32) : \ + (((x) == LPUART_0) ? (64) : \ + (((x) == LPUART_1) ? (64) : \ + (((x) == LPUART_2) ? (64) : \ + (((x) == LPUART_3) ? (64) : (-1))))))) + +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10U) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1U) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0U) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0U) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1U) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0U) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0U) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0U) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1U) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0U) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0U) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == 0 ? (0) : (-1)) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1U) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1U) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1U) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1U) +#define FSL_FEATURE_LPUART0_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART1_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART2_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART3_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART4_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART5_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART6_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART7_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART8_HAS_NO_IRQ (1U) + +/* DSC module features */ + +#define FSL_FEATURE_DSC_HAS_PER_RESET (1U) + +/* MU module features */ + +/* @brief MU side for current core */ +#define FSL_FEATURE_MU_SIDE_A (0U) +#define FSL_FEATURE_MU_NO_RSTH (1U) +#define FSL_FEATURE_MU_NO_HR (1U) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1U) +/* @brief WDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1U) + +/* LPI2C module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4U) + +#define FSL_FEATURE_I2C_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C0_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C1_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C2_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C3_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C4_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C5_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C6_HAS_NO_IRQ (1U) + +/* PORT module features */ + +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1U) + +/* GPIO module features */ + +#define FSL_FEATURE_GPIO_HAS_NO_INTERRUPT (1U) + +/* PAD module features */ + +/* @brief Pads are for 28LPP. */ +#define FSL_FEATURE_PAD_HAS_28LPP (0U) +/* @brief Pads are for 28FDSOI. */ +#define FSL_FEATURE_PAD_HAS_28FDSOI (1U) + +/* SECO module features */ + +/* @brief SECO protocol version */ +#define FSL_FEATURE_SECO_VER (2U) + +/* OTP module features */ +#define FSL_FEATURE_OTP_16K_1H_OFS_START (16U) +#define FSL_FEATURE_OTP_16K_1H_OFS_END (271U) +#define FSL_FEATURE_OTP_16K_2H_OFS_START (544U) +#define FSL_FEATURE_OTP_16K_2H_OFS_END (799U) + +/* CSR module features */ +#define FSL_FEATURE_CSR_HAS_CSR (0U) +#define FSL_FEATURE_CSR_HAS_CSR2 (1U) +#define FSL_FEATURE_CSR_HAS_CSR3 (1U) +#define FSL_FEATURE_CSR_HAS_LPCG (0U) + +#define FSL_FEATURE_DPLL_VER (18U) +#define FSL_FEATURE_AV_PLL_ENABLE_ALT (0U) + +#define FSL_FEATURE_PCIE_DPLL_SS (1U) + +/* DSC config */ +#define FSL_FEATURE_DSC_SSSLICE_CNT (8U) +#define FSL_FEATURE_DSC_SLSLICE_CNT (17U) +#define FSL_FEATURE_DSC_CSLICE_CNT (1U) +#define FSL_FEATURE_DSC_GPR_CTRL_CNT (3U) + +#endif /* MX8_FEATURES_H */ + diff --git a/platform/devices/MX8DXL/MX8DXL_fuse_map.h b/platform/devices/MX8DXL/MX8DXL_fuse_map.h new file mode 100755 index 0000000..fb11525 --- /dev/null +++ b/platform/devices/MX8DXL/MX8DXL_fuse_map.h @@ -0,0 +1,283 @@ +/* +** ################################################################### +** Processors: MX8DXL +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8DXL +** +** Copyright 2017-2018 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef HW_FUSES_H +#define HW_FUSES_H + +/******************************************************************************* + * Macros + ******************************************************************************/ +#if !defined(NO_DEVICE_ACCESS) + #define OTP_GET_FUSE_STATE(_REG, SHFT, MSK) \ + ((((uint32_t)(OTP->FUSE[(_REG)].RW)) >> (SHFT)) & (MSK)) +#else + #define OTP_GET_FUSE_STATE(_REG, SHFT, MSK) \ + (((temp_fuses[(_REG)]) >> (SHFT)) & (MSK)) +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define OTP_CAAM_DIS OTP_GET_FUSE_STATE(0x003U, 0U, 0x00000001U) +#define OTP_IEE_DIS OTP_GET_FUSE_STATE(0x003U, 1U, 0x00000001U) +#define OTP_V2X_ROM_PATCH_EN OTP_GET_FUSE_STATE(0x003U, 2U, 0x00000001U) +#define OTP_V2X_PKC_BA414_DIS OTP_GET_FUSE_STATE(0x003U, 3U, 0x00000001U) +#define OTP_MMCAU_DIS OTP_GET_FUSE_STATE(0x003U, 4U, 0x00000001U) +#define OTP_ARM_CRYPT_EXT OTP_GET_FUSE_STATE(0x003U, 5U, 0x00000001U) +#define OTP_V2X_FW_ENCRYPTED OTP_GET_FUSE_STATE(0x003U, 6U, 0x00000001U) +#define OTP_V2X_FW_SIGNED OTP_GET_FUSE_STATE(0x003U, 7U, 0x00000001U) +#define OTP_V2X_ROM_IMG_VERIFY OTP_GET_FUSE_STATE(0x003U, 8U, 0x00000001U) +#define OTP_SNVS_DIS OTP_GET_FUSE_STATE(0x003U, 10U, 0x00000001U) +#define OTP_V2X_DEBUG_DIS OTP_GET_FUSE_STATE(0x003U, 11U, 0x00000001U) +#define OTP_V2X_DBG_KEY_EXCHG OTP_GET_FUSE_STATE(0x003U, 12U, 0x00000001U) +#define OTP_V2X_DBG_ON_REQ OTP_GET_FUSE_STATE(0x003U, 13U, 0x00000001U) +#define OTP_ATTEST_DIS OTP_GET_FUSE_STATE(0x003U, 14U, 0x00000001U) +#define OTP_PUF_ENB OTP_GET_FUSE_STATE(0x003U, 15U, 0x00000001U) +#define OTP_FUSE_LIFE_CYCLE OTP_GET_FUSE_STATE(0x004U, 0U, 0x000003FFU) +#define OTP_SDP_DIS OTP_GET_FUSE_STATE(0x004U, 10U, 0x00000001U) +#define OTP_SDP_W_ONLY OTP_GET_FUSE_STATE(0x004U, 11U, 0x00000001U) +#define OTP_SREV_XOR OTP_GET_FUSE_STATE(0x004U, 12U, 0x00000007U) +#define OTP_SREV_ROM OTP_GET_FUSE_STATE(0x004U, 15U, 0x00000001U) +#define OTP_SJC_DIS OTP_GET_FUSE_STATE(0x005U, 0U, 0x00000001U) +#define OTP_OEM_SEC_CONFIG OTP_GET_FUSE_STATE(0x005U, 5U, 0x00000003U) +#define OTP_SCU_SEC_CONFIG OTP_GET_FUSE_STATE(0x005U, 7U, 0x00000003U) +#define OTP_OTP_CHLG_RESP_DIS OTP_GET_FUSE_STATE(0x005U, 10U, 0x00000001U) +#define OTP_TZ_CHLG_RESP_DIS OTP_GET_FUSE_STATE(0x005U, 11U, 0x00000001U) +#define OTP_ARRAY_IS_PROG OTP_GET_FUSE_STATE(0x005U, 15U, 0x00000001U) +#define OTP_AP_2_DIS OTP_GET_FUSE_STATE(0x006U, 0U, 0x0000000FU) +#define OTP_AP_2_0_DIS OTP_GET_FUSE_STATE(0x006U, 0U, 0x00000001U) +#define OTP_AP_2_1_DIS OTP_GET_FUSE_STATE(0x006U, 1U, 0x00000001U) +#define OTP_AP_2_MAX_FREQ OTP_GET_FUSE_STATE(0x006U, 8U, 0x0000000FU) +#define OTP_TEMP_GRADE OTP_GET_FUSE_STATE(0x006U, 12U, 0x00000003U) +#define OTP_DSP_DIS OTP_GET_FUSE_STATE(0x008U, 0U, 0x00000001U) +#define OTP_MCU_0_DIS OTP_GET_FUSE_STATE(0x008U, 1U, 0x00000001U) +#define OTP_V2X_DIS OTP_GET_FUSE_STATE(0x008U, 3U, 0x00000001U) +#define OTP_PCIE_B_DIS OTP_GET_FUSE_STATE(0x008U, 5U, 0x00000001U) +#define OTP_USB2_1_DIS OTP_GET_FUSE_STATE(0x008U, 8U, 0x00000001U) +#define OTP_USB2_2_OTG_DIS OTP_GET_FUSE_STATE(0x008U, 9U, 0x00000001U) +#define OTP_ETH_0_DIS OTP_GET_FUSE_STATE(0x008U, 12U, 0x00000001U) +#define OTP_ETH_1_DIS OTP_GET_FUSE_STATE(0x008U, 13U, 0x00000001U) +#define OTP_DRC_0_DIS OTP_GET_FUSE_STATE(0x009U, 8U, 0x0000000FU) +#define OTP_CAN_DIS OTP_GET_FUSE_STATE(0x00AU, 0U, 0x00000001U) +#define OTP_ENET1_FREQ_LIMIT OTP_GET_FUSE_STATE(0x00AU, 1U, 0x00000001U) +#define OTP_ENET2_FREQ_LIMIT OTP_GET_FUSE_STATE(0x00AU, 2U, 0x00000001U) +#define OTP_FIPS_MODE OTP_GET_FUSE_STATE(0x00AU, 3U, 0x00000001U) +#define OTP_FIPS_MODE_DIS OTP_GET_FUSE_STATE(0x00AU, 4U, 0x00000001U) + +#define OTP_PATCH_ALLOC0 OTP_GET_FUSE_STATE(0x00AU, 3U, 0x00000001U) +#define OTP_PATCH_ALLOC1 OTP_GET_FUSE_STATE(0x00AU, 4U, 0x00000001U) +#define OTP_PATCH_ALLOC2 OTP_GET_FUSE_STATE(0x00AU, 5U, 0x00000001U) + +#define OTP_EARLY_FUS_PROG OTP_GET_FUSE_STATE(0x00EU, 0U, 0x00000001U) +#define OTP_SCU_FUS_PROG OTP_GET_FUSE_STATE(0x00EU, 1U, 0x00000001U) +#define OTP_ALL_FUS_PROG OTP_GET_FUSE_STATE(0x00EU, 2U, 0x00000001U) +#define OTP_SECO_OPEN_8E OTP_GET_FUSE_STATE(0x00EU, 3U, 0x00000001U) +#define OTP_SECO_CLOSED_8E OTP_GET_FUSE_STATE(0x00EU, 4U, 0x00000001U) +#define OTP_SECO_SECURED_8E OTP_GET_FUSE_STATE(0x00EU, 5U, 0x00000001U) +#define OTP_ROM_INF_LOOP OTP_GET_FUSE_STATE(0x00EU, 8U, 0x00000001U) +#define OTP_BT_DIR_DIS OTP_GET_FUSE_STATE(0x00EU, 9U, 0x00000001U) +#define OTP_ROM_CONT_BITS OTP_GET_FUSE_STATE(0x00EU, 10U, 0x0000001FU) +#define OTP_SHELF_MODE OTP_GET_FUSE_STATE(0x00EU, 15U, 0x00000001U) + +/******************************************************************************* + * Trim & other fuses + ******************************************************************************/ + +#define OTP_UNIQUE_ID_L OTP_GET_FUSE_STATE(0x010U, 0U, 0xFFFFFFFFU) +#define OTP_UNIQUE_ID_H OTP_GET_FUSE_STATE(0x011U, 0U, 0xFFFFFFFFU) + +#define OTP_LOT_NO_ENC_L OTP_GET_FUSE_STATE(0x010U, 0U, 0xFFFFFFFFU) +#define OTP_LOT_NO_ENC_H OTP_GET_FUSE_STATE(0x011U, 0U, 0x000007FFU) +#define OTP_WAFER_NO OTP_GET_FUSE_STATE(0x011U, 11U, 0x0000001FU) +#define OTP_DIE_Y_COORD OTP_GET_FUSE_STATE(0x011U, 16U, 0x000000FFU) +#define OTP_DIE_X_COORD OTP_GET_FUSE_STATE(0x011U, 24U, 0x000000FFU) + +#define OTP_BT_MODE_FUS OTP_GET_FUSE_STATE(0x012U, 0U, 0x0000003FU) +#define OTP_BT_FUS_SEL OTP_GET_FUSE_STATE(0x012U, 6U, 0x00000001U) +#define OTP_BT_FORCE_COLD OTP_GET_FUSE_STATE(0x012U, 7U, 0x00000001U) + +#define OTP_WDOG_EN OTP_GET_FUSE_STATE(0x012U, 8U, 0x00000001U) +#define OTP_WDOG_TO OTP_GET_FUSE_STATE(0x012U, 9U, 0x00000003U) +#define OTP_SCU_DCACHE_DIS OTP_GET_FUSE_STATE(0x012U, 11U, 0x00000001U) +#define OTP_SCU_ICACHE_DIS OTP_GET_FUSE_STATE(0x012U, 12U, 0x00000001U) +#define OTP_AP_MMU_DCACHE_DIS OTP_GET_FUSE_STATE(0x012U, 13U, 0x00000001U) +#define OTP_AP_ICACHE_DIS OTP_GET_FUSE_STATE(0x012U, 14U, 0x00000001U) +#define OTP_SDMMC_MAN_DIS OTP_GET_FUSE_STATE(0x012U, 18U, 0x00000001U) +#define OTP_REC_BOOT_EN OTP_GET_FUSE_STATE(0x012U, 19U, 0x00000001U) +#define OTP_SCU_BT_F_GPIO_SEL OTP_GET_FUSE_STATE(0x012U, 20U, 0x00000007U) +#define OTP_SCU_BT_F_IND OTP_GET_FUSE_STATE(0x012U, 23U, 0x00000001U) +#define OTP_FLEXSPI_DLL OTP_GET_FUSE_STATE(0x012U, 24U, 0x0000000FU) +#define OTP_OVR_NAND OTP_GET_FUSE_STATE(0x012U, 28U, 0x00000001U) +#define OTP_OVR_NAND_VAL OTP_GET_FUSE_STATE(0x012U, 29U, 0x00000001U) +#define OTP_OVR_FLX_SPI OTP_GET_FUSE_STATE(0x012U, 30U, 0x00000001U) +#define OTP_OVR_FLX_SPI_VAL OTP_GET_FUSE_STATE(0x012U, 31U, 0x00000001U) +#define OTP_FAST_BOOT OTP_GET_FUSE_STATE(0x013U, 0U, 0x00000001U) +#define OTP_FAST_BOOT_ACK OTP_GET_FUSE_STATE(0x013U, 1U, 0x00000001U) +#define OTP_USDHC_BT_SPD OTP_GET_FUSE_STATE(0x013U, 2U, 0x00000003U) +#define OTP_MMC_BUS_W OTP_GET_FUSE_STATE(0x013U, 4U, 0x00000003U) +#define OTP_FAST_FRZ_DIS OTP_GET_FUSE_STATE(0x013U, 6U, 0x00000001U) + +#define OTP_USDHC_CYC_DLY OTP_GET_FUSE_STATE(0x013U, 8U, 0x00000001U) +#define OTP_USDHC_CYC_INT OTP_GET_FUSE_STATE(0x013U, 9U, 0x00000001U) +#define OTP_USDHC_CYC_EN OTP_GET_FUSE_STATE(0x013U, 10U, 0x00000001U) +#define OTP_USDHC_DLL_EN OTP_GET_FUSE_STATE(0x013U, 11U, 0x00000001U) +#define OTP_SD_LOOPBCK OTP_GET_FUSE_STATE(0x013U, 12U, 0x00000001U) +#define OTP_USDHC_PD_PULLDWN OTP_GET_FUSE_STATE(0x013U, 13U, 0x00000001U) +#define OTP_SD_CAL_STEP OTP_GET_FUSE_STATE(0x013U, 14U, 0x00000003U) +#define OTP_USDHC_DLL_DLY OTP_GET_FUSE_STATE(0x013U, 16U, 0x0000007FU) +#define OTP_USDHC_DLL_SEL OTP_GET_FUSE_STATE(0x013U, 23U, 0x00000001U) +#define OTP_USDHC_PD_SET_OVR OTP_GET_FUSE_STATE(0x013U, 24U, 0x00000007U) +#define OTP_NAND_PD_SET_OVR OTP_GET_FUSE_STATE(0x013U, 27U, 0x00000007U) +#define OTP_CS_NUM_NAND OTP_GET_FUSE_STATE(0x013U, 30U, 0x00000003U) + +#define OTP_DBGEN_DBGEN OTP_GET_FUSE_STATE(0x016U, 0U, 0x000000FFU) +#define OTP_DBGEN_NIDEN OTP_GET_FUSE_STATE(0x016U, 8U, 0x000000FFU) +#define OTP_DBGEN_SPIDEN OTP_GET_FUSE_STATE(0x016U, 16U, 0x000000FFU) +#define OTP_DBGEN_SPNIDEN OTP_GET_FUSE_STATE(0x016U, 24U, 0x000000FFU) + +#define OTP_DPLL_CALIB_V2 OTP_GET_FUSE_STATE(0x01BU, 3U, 0x00000001U) + +#define OTP_OSC_CAP_TRIM OTP_GET_FUSE_STATE(0x01EU, 0U, 0x0000000FU) +#define OTP_TMP_MON_TRM_LO OTP_GET_FUSE_STATE(0x01EU, 4U, 0x0000003FU) +#define OTP_TMP_MON_TRM_HI OTP_GET_FUSE_STATE(0x01EU, 10U, 0x0000003FU) +#define OTP_TMP_MON_TRM_SHLF_LO OTP_GET_FUSE_STATE(0x01EU, 20U, 0x0000003FU) +#define OTP_TMP_MON_TRM_SHLF_HI OTP_GET_FUSE_STATE(0x01EU, 26U, 0x0000003FU) +#define OTP_BANDGAP_TRM OTP_GET_FUSE_STATE(0x01FU, 0U, 0x0000001FU) +#define OTP_32K_INT_IRC_TRM OTP_GET_FUSE_STATE(0x01FU, 5U, 0x0000001FU) +#define OTP_CLK_MON_TRM_LO OTP_GET_FUSE_STATE(0x01FU, 10U, 0x0000000FU) +#define OTP_CLK_MON_TRM_HI OTP_GET_FUSE_STATE(0x01FU, 14U, 0x0000000FU) +#define OTP_V_MON_TRM_LO OTP_GET_FUSE_STATE(0x01FU, 18U, 0x0000000FU) +#define OTP_V_MON_TRM_HI OTP_GET_FUSE_STATE(0x01FU, 22U, 0x0000000FU) +#define OTP_V_MON_TAM_DIS OTP_GET_FUSE_STATE(0x01FU, 26U, 0x00000001U) +#define OTP_CLK_MON_DIS OTP_GET_FUSE_STATE(0x01FU, 27U, 0x00000001U) +#define OTP_TMP_MON_DIS OTP_GET_FUSE_STATE(0x01FU, 28U, 0x00000001U) +#define OTP_SNVS_C_V_TRM OTP_GET_FUSE_STATE(0x01FU, 30U, 0x00000003U) + +#define OTP_SCU_REFGEN OTP_GET_FUSE_STATE(0x064U, 0U, 0x000000FFU) +#define OTP_AP_2_REFGEN OTP_GET_FUSE_STATE(0x064U, 8U, 0x000000FFU) +#define OTP_DRC_REFGEN OTP_GET_FUSE_STATE(0x064U, 24U, 0x000000FFU) +#define OTP_GPU_0_REFGEN OTP_GET_FUSE_STATE(0x065U, 8U, 0x000000FFU) +#define OTP_ADMA_REFGEN OTP_GET_FUSE_STATE(0x065U, 24U, 0x000000FFU) +#define OTP_CONN_REFGEN OTP_GET_FUSE_STATE(0x066U, 0U, 0x000000FFU) +#define OTP_HSIO_REFGEN OTP_GET_FUSE_STATE(0x066U, 24U, 0x000000FFU) + +#define OTP_USB_PHY_TRM OTP_GET_FUSE_STATE(0x067U, 0U, 0x000FFFFFU) +#define OTP_CSI_0_RCAL_TRIM OTP_GET_FUSE_STATE(0x069U, 8U, 0x00000003U) +#define OTP_DSI_0_RCAL_TRIM OTP_GET_FUSE_STATE(0x067U, 20U, 0x00000003U) +#define OTP_DSI_1_RCAL_TRIM OTP_GET_FUSE_STATE(0x067U, 22U, 0x00000003U) + +#define OTP_TMP_SENS_SCU OTP_GET_FUSE_STATE(0x06AU, 2U, 0x000003FFU) +#define OTP_TMP_SENS_3 OTP_GET_FUSE_STATE(0x06AU, 12U, 0x000003FFU) +#define OTP_TMP_SENS_4 OTP_GET_FUSE_STATE(0x06AU, 22U, 0x000003FFU) +#define OTP_TMP_SENS_DRC0 OTP_GET_FUSE_STATE(0x06BU, 2U, 0x000003FFU) +#define OTP_TMP_SENS_6 OTP_GET_FUSE_STATE(0x06BU, 12U, 0x000003FFU) +#define OTP_TMP_SENS_7 OTP_GET_FUSE_STATE(0x06BU, 22U, 0x000003FFU) + +#define OTP_ROM_PATCH 0x070U +#define OTP_ROM_PATCH_SIZE 62U +#define OTP_SECO_PATCH 0x0D0U +#define OTP_SECO_PATCH_SIZE 32U +#define OTP_SECO_PATCH2 0x190U +#define OTP_SECO_PATCH2_SIZE 32U +#define OTP_V2X_PATCH 0x1F2U +#define OTP_V2X_PATCH_SIZE 11U + +#define OTP_DERATE_DLL_FRQ OTP_GET_FUSE_STATE(0x0AEU, 0U, 0x00000001U) +#define OTP_EXT_OSC_SEL OTP_GET_FUSE_STATE(0x0AEU, 1U, 0x00000001U) +#define OTP_USE_INT_OSC OTP_GET_FUSE_STATE(0x0AEU, 2U, 0x00000001U) +#define OTP_SINGLE_END_CLK OTP_GET_FUSE_STATE(0x0AEU, 3U, 0x00000001U) + +#define OTP_24MHZ_REGH_LV OTP_GET_FUSE_STATE(0x100U, 0U, 0x00000007U) +#define OTP_24MHZ_REGL_LV OTP_GET_FUSE_STATE(0x100U, 3U, 0x00000007U) +#define OTP_ROSC_FREQ_OFF OTP_GET_FUSE_STATE(0x100U, 8U, 0x00FFFFFFU) + +#define OTP_DPLL_TRM OTP_GET_FUSE_STATE(0x101U, 0U, 0xFFFFFFFFU) +#define OTP_DPLL_TRM_VALID OTP_GET_FUSE_STATE(0x101U, 0U, 0x00800000U) + +#define OTP_24MHZ_DIFF_VALID OTP_GET_FUSE_STATE(0x102U, 31U, 0x00000001U) +#define OTP_24MHZ_DIFF_DRV0 OTP_GET_FUSE_STATE(0x102U, 0U, 0x00000003U) +#define OTP_24MHZ_DIFF_DRV1 OTP_GET_FUSE_STATE(0x102U, 4U, 0x00000003U) +#define OTP_24MHZ_DIFF_TERM_RES OTP_GET_FUSE_STATE(0x102U, 8U, 0x00000003U) +#define OTP_24MHZ_DIFF_DRV_IN OTP_GET_FUSE_STATE(0x102U, 10U, 0x00000003U) +#define OTP_24MHZ_DIFF_SQRUP OTP_GET_FUSE_STATE(0x102U, 12U, 0x00000003U) +#define OTP_SCU_REG_TRIM OTP_GET_FUSE_STATE(0x102U, 16U, 0x00000007U) + +#define OTP_DSI_0_VOH_CLK_TRIM OTP_GET_FUSE_STATE(0x103U, 0U, 0x00000007U) +#define OTP_DSI_0_VOH_D3_TRIM OTP_GET_FUSE_STATE(0x103U, 3U, 0x00000007U) +#define OTP_DSI_0_VOH_D2_TRIM OTP_GET_FUSE_STATE(0x103U, 6U, 0x00000007U) +#define OTP_DSI_0_VOH_D1_TRIM OTP_GET_FUSE_STATE(0x103U, 9U, 0x00000007U) +#define OTP_DSI_0_VOH_D0_TRIM OTP_GET_FUSE_STATE(0x103U, 12U, 0x00000007U) +#define OTP_DSI_1_VOH_CLK_TRIM OTP_GET_FUSE_STATE(0x103U, 16U, 0x00000007U) +#define OTP_DSI_1_VOH_D3_TRIM OTP_GET_FUSE_STATE(0x103U, 19U, 0x00000007U) +#define OTP_DSI_1_VOH_D2_TRIM OTP_GET_FUSE_STATE(0x103U, 22U, 0x00000007U) +#define OTP_DSI_1_VOH_D1_TRIM OTP_GET_FUSE_STATE(0x103U, 25U, 0x00000007U) +#define OTP_DSI_1_VOH_D0_TRIM OTP_GET_FUSE_STATE(0x103U, 28U, 0x00000007U) + +#define OTP_ROM_LITERAL 0x10CU +#define OTP_ROM_LITERAL_SIZE 4U + +#define OTP_24MHZ_CL_TUNE_VALID OTP_GET_FUSE_STATE(0x1F0U, 31U, 0x00000001U) +#define OTP_24MHZ_CL_TUNE_LV OTP_GET_FUSE_STATE(0x1F0U, 0U, 0x000000FFU) + +#define OTP_DPLL_TABLE_SELECT_VALID OTP_GET_FUSE_STATE(0x1FDU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_SELECT_BITS OTP_GET_FUSE_STATE(0x1FDU, 0U, 0x003FFFFFU) + +#define OTP_DPLL_TABLE_0_VALID OTP_GET_FUSE_STATE(0x1FEU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_0_V6 OTP_GET_FUSE_STATE(0x1FEU, 26U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V5 OTP_GET_FUSE_STATE(0x1FEU, 21U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V4 OTP_GET_FUSE_STATE(0x1FEU, 16U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V3 OTP_GET_FUSE_STATE(0x1FEU, 11U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V2 OTP_GET_FUSE_STATE(0x1FEU, 6U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V1 OTP_GET_FUSE_STATE(0x1FEU, 0U, 0x0000003FU) + +#define OTP_DPLL_TABLE_1_VALID OTP_GET_FUSE_STATE(0x1FFU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_1_V6 OTP_GET_FUSE_STATE(0x1FFU, 26U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V5 OTP_GET_FUSE_STATE(0x1FFU, 21U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V4 OTP_GET_FUSE_STATE(0x1FFU, 16U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V3 OTP_GET_FUSE_STATE(0x1FFU, 11U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V2 OTP_GET_FUSE_STATE(0x1FFU, 6U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V1 OTP_GET_FUSE_STATE(0x1FFU, 0U, 0x0000003FU) + +#define OTP_TMP_SENS_SCU_OFS OTP_GET_FUSE_STATE(0x1F1U, 0U, 0x000000FFU) +#define OTP_TMP_SENS_DRC0_OFS OTP_GET_FUSE_STATE(0x1F1U, 8U, 0x000000FFU) + +#endif /* HW_FUSES_H */ + diff --git a/platform/devices/MX8DXL/MX8DXL_otp.h b/platform/devices/MX8DXL/MX8DXL_otp.h new file mode 100755 index 0000000..9145340 --- /dev/null +++ b/platform/devices/MX8DXL/MX8DXL_otp.h @@ -0,0 +1,318 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_OTP_REGISTERS_H +#define HW_OTP_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- OTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTP_Peripheral_Access_Layer OTP Peripheral Access Layer + * @{ + */ + +/** OTP - Register Layout Typedef */ +typedef struct +{ + __IO uint32_t RW; + __IO uint32_t SET; + __IO uint32_t CLR; + __IO uint32_t TOG; +} OTP_Reg; + +typedef struct +{ + OTP_Reg CTRL; + OTP_Reg PDN; + OTP_Reg DATA; + OTP_Reg READ_CTRL; + OTP_Reg READ_FUSE_DATA; + OTP_Reg SW_STICKY; + OTP_Reg SCS; + OTP_Reg CRC_ADDR; + OTP_Reg CRC_VALUE; + OTP_Reg STATUS; + __I uint32_t STARTWORD; + uint8_t RESERVED_0[12]; + __I uint32_t VERSION; + uint8_t RESERVED_1[1356]; + struct { + __I uint32_t RW; + __I uint32_t SET; + __I uint32_t CLR; + __I uint32_t TOG; + } LOCKED[17]; + uint8_t RESERVED_3[240]; + OTP_Reg FUSE[528]; +} OTP_Type; + +/* ---------------------------------------------------------------------------- + -- OTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTP_Register_Masks OTP Register Masks + * @{ + */ + +/*! @name OTP Register */ +#define OTP_BIT0_MASK (0x00000001U) +#define OTP_BIT0_SHIFT (0U) +#define OTP_BIT0(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT1_MASK (0x00000002U) +#define OTP_BIT1_SHIFT (1U) +#define OTP_BIT1(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT2_MASK (0x00000004U) +#define OTP_BIT2_SHIFT (2U) +#define OTP_BIT2(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT3_MASK (0x00000008U) +#define OTP_BIT3_SHIFT (3U) +#define OTP_BIT3(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT4_MASK (0x00000010U) +#define OTP_BIT4_SHIFT (4U) +#define OTP_BIT4(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT5_MASK (0x00000020U) +#define OTP_BIT5_SHIFT (5U) +#define OTP_BIT5(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT6_MASK (0x00000040U) +#define OTP_BIT6_SHIFT (6U) +#define OTP_BIT6(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT7_MASK (0x00000080U) +#define OTP_BIT7_SHIFT (7U) +#define OTP_BIT7(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT8_MASK (0x00000100U) +#define OTP_BIT8_SHIFT (8U) +#define OTP_BIT8(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT9_MASK (0x00000200U) +#define OTP_BIT9_SHIFT (9U) +#define OTP_BIT9(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT10_MASK (0x00000400U) +#define OTP_BIT10_SHIFT (10U) +#define OTP_BIT10(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT11_MASK (0x00000800U) +#define OTP_BIT11_SHIFT (11U) +#define OTP_BIT11(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT12_MASK (0x00001000U) +#define OTP_BIT12_SHIFT (12U) +#define OTP_BIT12(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT13_MASK (0x00002000U) +#define OTP_BIT13_SHIFT (13U) +#define OTP_BIT13(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT14_MASK (0x00004000U) +#define OTP_BIT14_SHIFT (14U) +#define OTP_BIT14(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT15_MASK (0x00008000U) +#define OTP_BIT15_SHIFT (15U) +#define OTP_BIT15(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT16_MASK (0x00010000U) +#define OTP_BIT16_SHIFT (16U) +#define OTP_BIT16(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT17_MASK (0x00020000U) +#define OTP_BIT17_SHIFT (17U) +#define OTP_BIT17(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT18_MASK (0x00040000U) +#define OTP_BIT18_SHIFT (18U) +#define OTP_BIT18(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT19_MASK (0x00080000U) +#define OTP_BIT19_SHIFT (19U) +#define OTP_BIT19(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT20_MASK (0x00100000U) +#define OTP_BIT20_SHIFT (20U) +#define OTP_BIT20(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT21_ASK (0x00200000U) +#define OTP_BIT21_SHIFT (21U) +#define OTP_BIT21(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT22_MASK (0x00400000U) +#define OTP_BIT22_SHIFT (22U) +#define OTP_BIT22(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT23_MASK (0x00800000U) +#define OTP_BIT23_SHIFT (23U) +#define OTP_BIT23(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT24_MASK (0x01000000U) +#define OTP_BIT24_SHIFT (24U) +#define OTP_BIT24(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT25_MASK (0x02000000U) +#define OTP_BIT25_SHIFT (25U) +#define OTP_BIT25(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT26_MASK (0x04000000U) +#define OTP_BIT26_SHIFT (26U) +#define OTP_BIT26(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT27_MASK (0x08000000U) +#define OTP_BIT27_SHIFT (27U) +#define OTP_BIT27(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT28_MASK (0x10000000U) +#define OTP_BIT28_SHIFT (28U) +#define OTP_BIT28(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT29_MASK (0x20000000U) +#define OTP_BIT29_SHIFT (29U) +#define OTP_BIT29(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT30_MASK (0x40000000U) +#define OTP_BIT30_SHIFT (30U) +#define OTP_BIT30(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT31_MASK (0x80000000U) +#define OTP_BIT31_SHIFT (31U) +#define OTP_BIT31(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE0_MASK (0x0000000FU) +#define OTP_NIBBLE0_SHIFT (0U) +#define OTP_NIBBLE0(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE1_MASK (0x000000F0U) +#define OTP_NIBBLE1_SHIFT (4U) +#define OTP_NIBBLE1(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE2_MASK (0x00000F00U) +#define OTP_NIBBLE2_SHIFT (8U) +#define OTP_NIBBLE2(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE3_MASK (0x0000F000U) +#define OTP_NIBBLE3_SHIFT (12U) +#define OTP_NIBBLE3(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE4_MASK (0x000F0000U) +#define OTP_NIBBLE4_SHIFT (16U) +#define OTP_NIBBLE4(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE5_MASK (0x00F00000U) +#define OTP_NIBBLE5_SHIFT (20U) +#define OTP_NIBBLE5(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE6_MASK (0x0F000000U) +#define OTP_NIBBLE6_SHIFT (24U) +#define OTP_NIBBLE6(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE7_MASK (0xF0000000U) +#define OTP_NIBBLE7_SHIFT (28U) +#define OTP_NIBBLE7(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! + * @} + */ /* end of group OTP_Register_Masks */ + +/* OTP - Peripheral instance base addresses */ +/** Peripheral OTPA base pointer */ +#define OTP ((OTP_Type *)OTP_BASE) +/** Array initializer of OTP peripheral base addresses */ +#define OTP_BASE_ADDRS { OTP_BASE } +/** Array initializer of OTP peripheral base pointers */ +#define OTP_BASE_PTRS { OTP } + +/*! + * @} + */ /* end of group OTP_Peripheral_Access_Layer */ + +#endif /* HW_OTP_REGISTERS_H */ diff --git a/platform/devices/MX8DXL/Makefile b/platform/devices/MX8DXL/Makefile new file mode 100755 index 0000000..42e08cc --- /dev/null +++ b/platform/devices/MX8DXL/Makefile @@ -0,0 +1,14 @@ + +objs_mx8 := system_MX8DXL.o handlers_MX8DXL.o + +ifdef ROM +objs_mx8 += gcc/startup_rom_MX8DXL.o +else +objs_mx8 += gcc/startup_MX8DXL.o +endif + +OBJS += \ + $(foreach object,$(objs_mx8),$(OUT)/devices/MX8DXL/$(object)) + +DIRS += $(OUT)/devices/MX8DXL/gcc + diff --git a/platform/devices/MX8DXL/fsl_clock.h b/platform/devices/MX8DXL/fsl_clock.h new file mode 100755 index 0000000..ed09101 --- /dev/null +++ b/platform/devices/MX8DXL/fsl_clock.h @@ -0,0 +1,367 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef HW_CLOCKS_H +#define HW_CLOCKS_H + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define SC_XTAL32K_FREQ_HZ 32768U +#define SC_XTAL24M_FREQ_HZ 24000000U +#define SC_ROSC_FREQ_HZ 200000000U +#define SC_PLL0_STARTUP_FREQ_HZ 1056000000U + +#define SC_MSLICE_ROOT0_RESET_DIV 1U // 200 MHz / 1 = 200 MHz (CM4, BUS) +#define SC_MSLICE_ROOT1_RESET_DIV 2U // 200 MHz / 2 = 100 MHz (SECO, IPG) +#define SC_MSLICE_ROOT2_RESET_DIV 2U // 200 MHz / 2 = 100 MHz (CAAM) +#define SC_MSLICE_ROOT3_RESET_DIV 1U // 200 MHz / 1 = 200 MHz (MSI) + +#define SC_MSLICE_ROOT0_STARTUP_DIV 4U // 1056 MHz / 4 = 264 MHz (CM4, BUS) +#define SC_MSLICE_ROOT1_STARTUP_DIV 8U // 1056 MHz / 8 = 132 MHz (SECO, IPG) +#define SC_MSLICE_ROOT2_STARTUP_DIV 3U // 1056 MHz / 3 = 352 MHz (CAAM) +#define SC_MSLICE_ROOT3_STARTUP_DIV 5U // 1056 MHz / 5 = 211 MHz (MSI) + +#define SC_MCU_STARTUP_FREQ_HZ (SC_PLL0_STARTUP_FREQ_HZ/SC_MSLICE_ROOT0_STARTUP_DIV) +#define SC_MCU_STARTUP_FREQ_MHZ (SC_MCU_STARTUP_FREQ_HZ/1000000U) +#define SC_MCU_LPM_FREQ_HZ (SC_ROSC_FREQ_HZ/SC_MSLICE_ROOT0_STARTUP_DIV) +#define SC_MCU_LPM_FREQ_MHZ (SC_MCU_LPM_FREQ_HZ/1000000U) +#define SC_SYSTICK_NSEC_TO_TICKS(nsec) ((SC_MCU_STARTUP_FREQ_MHZ * (nsec)) / 1000U) + +#define SC_LPIT_ROOT_FREQ_HZ 24000000U +#define SC_LPIT_ROOT_DIV 3U +#define SC_LPIT_FREQ_HZ (SC_LPIT_ROOT_FREQ_HZ / SC_LPIT_ROOT_DIV) +#define SC_LPIT_MSEC_TO_TICKS(msec) (SC_LPIT_FREQ_HZ * (msec) / 1000U) + +#define SC_BG_SVC_MSEC 10U // Background service interval in msec +#define SC_WDOG_SVC_MSEC 5U // WDOG service interval in msec +#define SC_BG_TIMEOUT_MSEC 100U // Background timeout in msec +#define SC_BG_TIMEOUT (SC_BG_TIMEOUT_MSEC / SC_WDOG_SVC_MSEC) + +/*! @brief Clock ip name array for LPUART. */ + +/* Note: This array should have FSL_FEATURE_SOC_LPUART_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define LPUART_CLOCKS {kCLOCK_LPUART_SC, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/*! @brief Clock ip name array for LPI2C. */ + +/* Note: This array should have FSL_FEATURE_SOC_LPI2C_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define LPI2C_CLOCKS {kCLOCK_LPI2C_SC, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/* Note: This array should have FSL_FEATURE_SOC_IGPIO_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define GPIO_CLOCKS {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/* Note: This array should have FSL_FEATURE_SOC_MU_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define MU_CLOCKS {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid} + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_NmInvalid = 0U, +} clock_name_t; + +/*! + * @brief Clock source for peripherals that support various clock selections. + */ +typedef enum _clock_ip_src +{ + kCLOCK_SrcInvalid = 0U, +} clock_ip_src_t; + +/*! + * @brief Peripheral clock name difinition used for clock gate, clock source + * and clock divider setting. It is defined as the corresponding register address. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_TCMC_SC = LPCG__SS_SCU__CM4__TCMC_HCLK__BASE, + kCLOCK_MMCAU_SC = LPCG__SS_SCU__CM4__MMCAU_HCLK__BASE, + kCLOCK_TPM_SC = LPCG__SS_SCU__TPM1__IPG_CLK__BASE, + kCLOCK_LPIT_SC = LPCG__SS_SCU__LPIT1__IPG_CLK__BASE, + kCLOCK_LPUART_SC = LPCG__SS_SCU__LPUART1__IPG_CLK__BASE, + kCLOCK_LPI2C_SC = LPCG__SS_SCU__LPI2C1__IPG_CLK__BASE +} clock_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Enable IPG and BAUD clocks */ + volatile uint32_t lpcgVal = (1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN); + + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + + /* Wait for clocks to start */ + uint32_t stopMask = (1UL << LPCG__SS_SCU__IPG_CLK__STOP) | + (1UL << LPCG__SS_SCU__PER_CLK__STOP); + + while ((*((volatile uint32_t *) (uint32_t) name) & stopMask) != 0U) + { + ; /* Intentional empty while */ + } + + /* Perform extra write as workaround for TKT322331 */ + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + } +#endif +} + +/*! + * @brief Enable the hardware clock gating for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableHWCG(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Enable IPG and BAUD clocks */ + uint32_t lpcgVal = (1UL << LPCG__SS_SCU__PER_CLK__HWEN); + + *((volatile uint32_t *) (uint32_t) name) |= lpcgVal; + } +#endif +} + +/*! + * @brief Enable the clock for specific IP using exclusive access. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClockEx(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Use exclusive access to enable IPG and BAUD clocks */ + uint32_t volatile lpcgVal = (1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN); + + do + { + lpcgVal |= __LDREXW((volatile uint32_t *) (uint32_t) name); + } while (__STREXW(lpcgVal, ((volatile uint32_t *) (uint32_t) name)) != 0U); + + /* Wait for clocks to start */ + uint32_t stopMask = (1UL << LPCG__SS_SCU__IPG_CLK__STOP) | + (1UL << LPCG__SS_SCU__PER_CLK__STOP); + + while ((*((volatile uint32_t *) (uint32_t) name) & stopMask) != 0U) + { + ; /* Intentional empty while */ + } + + /* Perform extra write as workaround for TKT322331 */ + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + + } +#endif +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Disable IPG and BAUD clocks */ + uint32_t lpcgVal = 0U; + + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + } +#endif +} + +/*! + * @brief Enter exclusive attempt to disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline uint32_t CLOCK_DisableClockExEnter(clock_ip_name_t name) +{ +#ifndef SIMU + /* Use exclusive access to disable IPG and BAUD clocks */ + uint32_t lpcgVal = ~((1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN)); + + if (name != kCLOCK_IpInvalid) + { + lpcgVal = __LDREXW((volatile uint32_t *) (uint32_t) name); + } + + return lpcgVal; +#else + return 0U; +#endif +} + +/*! + * @brief Leave exclusive attempt to disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClockExLeave(clock_ip_name_t name, + uint32_t lpcgVal) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + (void)__STREXW(lpcgVal, ((volatile uint32_t *) (uint32_t) name)); + } +#endif +} + +/*! + * @brief Check whether the clock is already enabled and configured by + * any other core. + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @return True if clock is already enabled, otherwise false. + */ +static inline bool CLOCK_IsEnabledByOtherCore(clock_ip_name_t name) +{ + return false; +} + +/*! + * @brief Set the clock source for specific IP module. + * + * Set the clock source for specific IP, not all modules need to set the + * clock source, should only use this function for the modules need source + * setting. + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @param src Clock source to set. + */ +static inline void CLOCK_SetIpSrc(clock_ip_name_t name, clock_ip_src_t src) +{ +} + +/*! + * @brief Set the clock source and divider for specific IP module. + * + * Set the clock source and divider for specific IP, not all modules need to + * set the clock source and divider, should only use this function for the + * modules need source and divider setting. + * + * Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]). + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @param src Clock source to set. + * @param divValue The divider value. + * @param fracValue The fraction multiply value. + */ +static inline void CLOCK_SetIpSrcDiv(clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue) +{ +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Gets the clock frequency for a specific IP module. + * + * This function gets the IP module clock frequency based on PCC registers. It is + * only used for the IP modules which could select clock source by PCC[PCS]. + * + * @param name Which peripheral to get, see \ref clock_ip_name_t. + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetIpFreq(clock_ip_name_t name); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* HW_CLOCKS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8DXL/handlers_MX8DXL.h b/platform/devices/MX8DXL/handlers_MX8DXL.h new file mode 100755 index 0000000..9a063a9 --- /dev/null +++ b/platform/devices/MX8DXL/handlers_MX8DXL.h @@ -0,0 +1,98 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * Header for handlers. + */ + +#ifndef HANDLERS_H +#define HANDLERS_H + +/* Includes */ + +/* Defines */ + +/* Types */ + +/* Functions */ + +void sc_handlers_init(void); +void DefaultISR(void); +void NMI_IRQHandler(uint32_t *sp); +void MCM_IRQHandler(uint32_t *sp); +void DebugWake_IRQHandler(void); +void SWI_IRQHandler(void); +void LPIT_SCU_IRQHandler(uint32_t *sp); +void DSC_SCU_IRQHandler(void); +void DSC_DB_IRQHandler(void); +void DSC_LSIO_IRQHandler(void); +void DSC_CM4_0_IRQHandler(void); +void DSC_CA35_IRQHandler(void); +void DSC_DRC_0_IRQHandler(void); +void DSC_ADMA_IRQHandler(void); +void IOMUX_CommonHandler(uint8_t irq, uint8_t ring, uint8_t group); +void IOMUX0_IRQHandler(void); +void IOMUX1_IRQHandler(void); +void IOMUX2_IRQHandler(void); +void IOMUX3_IRQHandler(void); +void IOMUX4_IRQHandler(void); +void IOMUX5_IRQHandler(void); +void IOMUX6_IRQHandler(void); +void IOMUX7_IRQHandler(void); +void IOMUX8_IRQHandler(void); +void IOMUX9_IRQHandler(void); +void SYSCTR_CMP0_IRQHandler(void); +void SYSCTR_CMP1_IRQHandler(void); +void ss_earlywdog_handler_sc(void); +void ss_csreq_handler_a35(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_mcu(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_dbgpwrup(uint32_t idx, uint32_t cpwrupreq); +void SNVS_Functional_IRQHandler(void); +#if HAS_SS_AP_2 +sc_bool_t ss_dbg_status_a35(sc_dsc_t dsc); +void ss_dbg_resume_a35(sc_dsc_t dsc); +#endif + +/* Global Variables */ + +extern uint32_t gLPITcnt; + +#endif /* #if !defined(HANDLERS_H) */ + diff --git a/platform/devices/MX8DXL/linker/gcc/MX8DXL_flash.ld b/platform/devices/MX8DXL/linker/gcc/MX8DXL_flash.ld new file mode 100755 index 0000000..ea63e74 --- /dev/null +++ b/platform/devices/MX8DXL/linker/gcc/MX8DXL_flash.ld @@ -0,0 +1,61 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Specify the memory areas */ +MEMORY +{ + m_rom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* Vector table and code to emulate ROM */ + .rom : + { + . = ALIGN(8); + KEEP(*(.rom)) + . = ALIGN(0x80); + } > m_rom +} + diff --git a/platform/devices/MX8DXL/linker/gcc/MX8DXL_overlay.t.ld b/platform/devices/MX8DXL/linker/gcc/MX8DXL_overlay.t.ld new file mode 100755 index 0000000..7b1d0b1 --- /dev/null +++ b/platform/devices/MX8DXL/linker/gcc/MX8DXL_overlay.t.ld @@ -0,0 +1,312 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* DO NOT EDIT - This file auto generated by $cmd */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_ocram (RX) : ORIGIN = 0x00100000, LENGTH = 0x00040000 + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002ED80 + m_ovl (RX) : ORIGIN = 0x2000F000, LENGTH = 0x00000FF0 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + OVERLAY : NOCROSSREFS + { +<% $counter = 0 %> +<%OV_LIST%> + .test$counter { */test_$tests[$counter].o(.text*) */test_$tests[$counter].o(.rodata*) } +<% $counter++; return 'OV_LIST' if $counter < scalar(@tests); '' %> + } > m_ovl AT> m_ocram + + .test_ovly_table : + { + . = ALIGN(4); + __ovly_table = .; + LONG(0x34982933); LONG(0); LONG($last); +<% $counter = 0 %> +<%TB_LIST%> + LONG(ABSOLUTE(ADDR(.test$counter))); LONG(SIZEOF(.test$counter)); LONG(LOADADDR(.test$counter)); +<% $counter++; return 'TB_LIST' if $counter < scalar(@tests); '' %> + LONG(0); LONG(0); LONG(0); + } > m_ocram + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8DXL/linker/gcc/MX8DXL_tcm.ld b/platform/devices/MX8DXL/linker/gcc/MX8DXL_tcm.ld new file mode 100755 index 0000000..55984d3 --- /dev/null +++ b/platform/devices/MX8DXL/linker/gcc/MX8DXL_tcm.ld @@ -0,0 +1,288 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002fd70 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8DXL/system_MX8DXL.h b/platform/devices/MX8DXL/system_MX8DXL.h new file mode 100755 index 0000000..ade2b54 --- /dev/null +++ b/platform/devices/MX8DXL/system_MX8DXL.h @@ -0,0 +1,198 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2017- 2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_H +#define SYSTEM_H /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defines */ + +/* Reset requires 32 cycles of xtal24M to propagate. SysTick clocked from + ROSC will be used for delay. + + ROSC @ 200 MHz +*/ +#define RESET_WAIT_ROSC_CYCLES (((SC_ROSC_FREQ_HZ / SC_XTAL24M_FREQ_HZ) + 1U) * 32U) + +/* Define delay for top-level top-level SSI power switch chains. + */ +#define SYSCTR_NSEC_TO_CYCLES(nsec) ((((nsec) * SC_MCU_STARTUP_FREQ_MHZ) + 999U) / 1000U) +#define SSI_CHAIN_LF_CYCLES (SYSCTR_NSEC_TO_CYCLES(500U)) +#define SSI_CHAIN_HF_CYCLES (SYSCTR_NSEC_TO_CYCLES(2000U)) + +/* OSC24M lock spec unknown, use conservative 4ms */ +#define OSC24M_WAIT_ROSC_CYCLES (4*SC_ROSC_FREQ_HZ/1000U) + +/* Address for environment event trigger */ +#define SC_ENV_TRIG_ADDR 0x2000FFF0U + +/* Query to determine if firmware loaded by ROM */ +#ifndef SIMU +#define SCFW_LOADED_BY_ROM ((DSC_SC->GPR_CTRL[0].RW & BIT(31))) +#else +#define SCFW_LOADED_BY_ROM (0x80000000U) +#endif + +/* Query to determine boot mode + * BOOT_MODE[7:0] tied to DSC.GPR_STAT[0] bits [23:16] + */ +#define SC_BOOT_MODE ((DSC_SC->GPR_STAT[0].RW & 0x00FF0000U) >> 16U) + +/* BOOT_MODE = Infinite loop mode = bXXXX1110 = 0x0E */ +#define SC_BOOT_MODE_INF_LOOP 0x0EU + +/* Margin to wake system early from LLS for WDOG servicing */ +#define SC_WAKE_MARGIN_MSEC 5U + +#ifdef DEBUG +extern uint32_t __DEBUG_DATA[]; +#define SCFW_DBG_READY (__DEBUG_DATA[0]) +#define SCFW_DBG_SKIPS (__DEBUG_DATA[1]) +#define SCFW_DBG_DUMP_PTR (&(__DEBUG_DATA[2])) +#define SCFW_DBG_DUMP_R0 (__DEBUG_DATA[2]) +#define SCFW_DBG_DUMP_R1 (__DEBUG_DATA[3]) +#define SCFW_DBG_DUMP_R2 (__DEBUG_DATA[4]) +#define SCFW_DBG_DUMP_R3 (__DEBUG_DATA[5]) +#define SCFW_DBG_DUMP_R12 (__DEBUG_DATA[6]) +#define SCFW_DBG_DUMP_LR (__DEBUG_DATA[7]) +#define SCFW_DBG_DUMP_PC (__DEBUG_DATA[8]) +#define SCFW_DBG_DUMP_PSR (__DEBUG_DATA[9]) +#define SCFW_DBG_SCTR_TICKS (__DEBUG_DATA[10]) +#define SCFW_DBG_RSVD0 (__DEBUG_DATA[11]) +#define SCFW_DBG_TX_PTR (&__DEBUG_DATA[12]) +#define SCFW_DBG_RX_PTR (&__DEBUG_DATA[13]) +#endif + +#define SC_ENV_TRIG_DUMP 0xc0ffee10U //!< Start dump +#define SC_ENV_TRIG_KILL 0xc0ffee20U //!< Kill execution + +/* Types */ + +/*! + * This type is used to indicate the trigger event. + */ +typedef uint32_t sc_env_trig_event_t; + +/** + * @brief Generate environment event trigger + * + */ +void SystemEventTrigger (sc_env_trig_event_t event); + +/** + * @brief Enter firmware critical section. + * + */ +void SystemEnterCS(void); + +/** + * @brief Exit firmware critical section. + * + */ +void SystemExitCS(void); + +/** + * @brief Get active exception. + * + */ +uint32_t SystemGetActiveException(void); + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit(void); + +void SystemInitPostCRT(void); + +/** + * @brief Prepares to enter Low-Power Mode (LPM) + * + */ +void SystemPrepareLPM(void); + +void SystemEnterLPM(void); + +/** + * @brief Delays the specified number of usec + * + */ +void SystemTimeDelay(uint32_t usec); + +void SystemDebugWaitAttach(void); + +void CommonFault_Handler(uint32_t *sp); + +void SystemDebugHalt(void); + +void SystemExit(void); + +void HardFault_Handler(uint32_t *sp); + +void MemManage_Handler(uint32_t *sp); + +void BusFault_Handler(uint32_t *sp); + +void UsageFault_Handler(uint32_t *sp); + +void SystemDebugResume(void); + +#if defined(DEBUG) || defined(HAS_TEST) +uint32_t SystemMemoryProbe(void *addr, void *val, uint8_t width); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_H_) */ diff --git a/platform/devices/MX8QM/MX8QM.h b/platform/devices/MX8QM/MX8QM.h new file mode 100755 index 0000000..77b0ec0 --- /dev/null +++ b/platform/devices/MX8QM/MX8QM.h @@ -0,0 +1,757 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8QM.h + * @version 1.7 + * @date 2015-05-16 + * @brief CMSIS Peripheral Access Layer for MX8QM + * + * CMSIS Peripheral Access Layer for MX8QM + */ + +#ifndef MX8QM_H +#define MX8QM_H /**< Symbol preventing repeated inclusion */ + +/* Check for valid CPU versions */ +#if !defined(SREV_B0) + #error "Invalid SOC revision!\n" +#endif + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0007U + + +/* ---------------------------------------------------------------------------- + -- Memory Map (SC perspective) + ---------------------------------------------------------------------------- */ + +#define LSIO_SS_BASE1 0x00000000U /* LSIO SS - slot 1 */ +#define OCRAM_ALIAS_BASE (LSIO_SS_BASE1+0x000000U) /* OCRAM alias */ +#define SC_ROM_BASE 0x00000000U /* SC ROM */ +#define OCRAM_BASE (LSIO_SS_BASE1+0x100000U) /* OCRAM */ +#define FSPI0_MEM_BASE (LSIO_SS_BASE1+0x8000000U) /* FlexSPI0 Memory */ +#define TCML_BASE 0x1FFE0000U /* SC TCML */ +#define TCMU_BASE 0x20000000U /* SC TCMU */ +#define CAAM_BASE 0x20400000U /* SC CAAM */ +#define ADM_BASE 0x20520000U /* SC ADM */ +#define OTP_BASE 0x20530000U /* SC OTP */ +#define SNVS_BASE 0x20540000U /* SC SNVS */ +#define MU0_BASE 0x20550000U /* SECO MU 1 */ +#define VPU_SS_BASE1 0x2C000000U /* VPU SS - slot 1 */ +#define VPU_SCB_BASE (VPU_SS_BASE1+0x0070000U) /* VPU SCB */ +#define VPU_MFD_BASE (VPU_SS_BASE1+0x01B0000U) /* VPU Decoder */ +#define LPUART1_BASE (VPU_SS_BASE1+0x0200000U) /* VPU LPUART */ +#define MU7_BASE (VPU_SS_BASE1+0x1010000U) /* VPU MU 0 */ +#define MU8_BASE (VPU_SS_BASE1+0x1030000U) /* VPU MU 1 */ +#define SCU_SS_BASE0 0x30000000U /* SCU SS - slot 0 */ +#define TCML0_BASE (SCU_SS_BASE0+0x00FE0000U) /* SCU TCML */ +#define TCMU0_BASE (SCU_SS_BASE0+0x01000000U) /* SCU TCMU */ +#define MCU_0_SS_BASE0 0x34000000U /* MCU 0 SS - slot 0 */ +#define TCML1_BASE (MCU_0_SS_BASE0+0x0FE0000U) /* MCU 0 TCML */ +#define TCMU1_BASE (MCU_0_SS_BASE0+0x1000000U) /* MCU 0 TCMU */ +#define RGPIOB_BASE (MCU_0_SS_BASE0+0x30F0000U) /* MCU 0 RGPIO */ +#define LPUART2_BASE (MCU_0_SS_BASE0+0x3220000U) /* MCU 0 LPUART */ +#define LPI2C1_BASE (MCU_0_SS_BASE0+0x3230000U) /* MCU 0 LPI2C */ +#define WDOG1_BASE (MCU_0_SS_BASE0+0x3420000U) /* MCU 0 WDOG */ +#define MU9_BASE (MCU_0_SS_BASE0+0x3480000U) /* MCU 0 MU 1A */ +#define MCU_1_SS_BASE0 0x38000000U /* MCU 1 SS - slot 0 */ +#define TCML2_BASE (MCU_1_SS_BASE0+0x0FE0000U) /* MCU 1 TCML */ +#define TCMU2_BASE (MCU_1_SS_BASE0+0x1000000U) /* MCU 1 TCMU */ +#define RGPIOC_BASE (MCU_1_SS_BASE0+0x30F0000U) /* MCU 1 RGPIO */ +#define LPUART3_BASE (MCU_1_SS_BASE0+0x3220000U) /* MCU 1 LPUART */ +#define LPI2C2_BASE (MCU_1_SS_BASE0+0x3230000U) /* MCU 1 LPI2C */ +#define WDOG2_BASE (MCU_1_SS_BASE0+0x3420000U) /* MCU 1 WDOG */ +#define MU10_BASE (MCU_1_SS_BASE0+0x3480000U) /* MCU 1 MU 1A */ +#define SYSCTR_CTRL_BASE 0x40000000U /* SC SYSCTR Control */ +#define SYSCTR_RD_BASE 0x40010000U /* SC SYSCTR Read */ +#define SYSCTR_CMP_BASE 0x40020000U /* SC SYSCTR Compare 0 */ +#define SYSCTR_CMP1_BASE 0x40020100U /* SC SYSCTR Compare 1 */ +#define LPC_BASE 0x40070000U /* SC LPC */ +#define CSGPR_BASE 0x40470000U /* CoreSight GPR */ +#define AP_1_DEBUG_APB_BASE 0x40600000U /* AP_1 Debug APB */ +#define AP_0_DEBUG_APB_BASE 0x40800000U /* AP_0 Debug APB */ +#define AP_2_DEBUG_APB_BASE 0x40800000U /* AP_2 Debug APB */ +#define RGPIOA_BASE 0x410F0000U /* SC RGPIO */ +#define LPIT0_BASE 0x41210000U /* SC LPIT */ +#define LPUART0_BASE 0x41220000U /* SC LPUART */ +#define LPI2C0_BASE 0x41230000U /* SC LPI2C */ +#define ASMC_BASE 0x41410000U /* SC ASMC */ +#define WDOG0_BASE 0x41420000U /* SC WDOG */ +#define MU1_BASE 0x41430000U /* SC MU 0B */ +#define MU2_BASE 0x41440000U /* SC MU 0A0 */ +#define MU3_BASE 0x41450000U /* SC MU 0A1 */ +#define MU4_BASE 0x41460000U /* SC MU 0A2 */ +#define MU5_BASE 0x41470000U /* SC MU 0A3 */ +#define MU6_BASE 0x41480000U /* SC MU 1A */ +#define MSI0_BASE 0x41800000U /* SC DSC MSI Ring 0 */ +#define DSC1_BASE 0x41820000U /* SC SC DSC */ +#define REP2_BASE 0x4182B000U /* SC MBIST MTR */ +#define MSI1_BASE 0x41A00000U /* SC DSC MSI Ring 1 */ +#define DSC17_BASE 0x41A20000U /* SC MCU_0 DSC */ +#define DSC18_BASE 0x41A40000U /* SC DRC_0 DSC */ +#define DSC19_BASE 0x41A60000U /* SC DC_1 DSC */ +#define DSC20_BASE 0x41A80000U /* SC MCU_1 DSC */ +#define DSC21_BASE 0x41AA0000U /* SC GPU_1 DSC */ +#define DSC22_BASE 0x41AC0000U /* SC CONN DSC */ +#define DSC23_BASE 0x41AE0000U /* SC VPU DSC */ +#define DSC25_BASE 0x41B20000U /* SC CCI DSC */ +#define MSI2_BASE 0x41C00000U /* SC DSC MSI Ring 2 */ +#define DSC33_BASE 0x41C20000U /* SC AP_1 DSC */ +#define DSC34_BASE 0x41C40000U /* SC DB DSC */ +#define DSC35_BASE 0x41C60000U /* SC AP_0 DSC */ +#define DSC36_BASE 0x41C80000U /* SC HSIO DSC */ +#define DSC37_BASE 0x41CA0000U /* SC LSIO DSC */ +#define DSC38_BASE 0x41CC0000U /* SC GPU_0 DSC */ +#define DSC39_BASE 0x41CE0000U /* SC DC_0 DSC */ +#define DSC40_BASE 0x41D00000U /* SC DRC_1 DSC */ +#define DSC41_BASE 0x41D20000U /* SC DMA DSC */ +#define MSI3_BASE 0x41E00000U /* SC DSC MSI Ring 3 */ +#define DSC49_BASE 0x41E20000U /* SC DBLOG DSC */ +#define DSC50_BASE 0x41E40000U /* SC IMG DSC */ +#define DSC51_BASE 0x41E60000U /* SC AUDIO DSC */ +#define DSC52_BASE 0x41E80000U /* SC HDMI DSC */ +#define DSC53_BASE 0x41EA0000U /* SC HDMI_RX DSC */ +#define DSC54_BASE 0x41EC0000U /* SC CSI_1 DSC */ +#define DSC55_BASE 0x41EE0000U /* SC CSI_0 DSC */ +#define DSC56_BASE 0x41F00000U /* SC MIPI_1 DSC */ +#define DSC57_BASE 0x41F20000U /* SC MIPI_0 DSC */ +#define DSC58_BASE 0x41F40000U /* SC LVDS_1 DSC */ +#define DSC59_BASE 0x41F60000U /* SC LVDS_0 DSC */ +#define PAD_BASE 0x41F80000U /* SC Pad */ +#define MSI4_BASE 0x41F9F000U /* SC Pad MSI Ring 0 */ +#define MSI5_BASE 0x41FBF000U /* SC Pad MSI Ring 1 */ +#define MSI6_BASE 0x41FDF000U /* SC Pad MSI Ring 2 */ +#define MSI7_BASE 0x41FFF000U /* SC Pad MSI Ring 3 */ +#define DBLOG_SS_BASE0 0x51000000U /* DBLOGIC SS - slot 0 */ +#define IRQSTR_SCU_BASE (DBLOG_SS_BASE0+0x060000U) /* IRQSTR.SCU1 */ +#define SMMU0_BASE (DBLOG_SS_BASE0+0x400000U) /* SMMU 0 */ +#define GIC0_BASE (DBLOG_SS_BASE0+0xA00000U) /* GIC 0 */ +#define AP_SS_BASE0 0x52000000U /* AP SS - slot 0 */ +#define CCI_BASE (AP_SS_BASE0+0x90000U) /* CCI */ +#define GPU_0_SS_BASE0 0x53000000U /* GPU 0 SS - slot 0 */ +#define GPU_1_SS_BASE0 0x54000000U /* GPU 1 SS - slot 0 */ +#define VPU_SS_BASE0 0x55000000U /* VPU SS - slot 0 */ +#define DSP_DRAM_BASE (VPU_SS_BASE0+0x6E8000U) /* DSP DRAM */ +#define DSP_DRAM1_BASE (VPU_SS_BASE0+0x6F0000U) /* DSP DRAM 1 */ +#define DSP_IRAM_BASE (VPU_SS_BASE0+0x6F8000U) /* DSP IRAM */ +#define DSP_OCRAM_BASE (VPU_SS_BASE0+0x700000U) /* DSP OCRAM */ +#define DC_0_SS_BASE0 0x56000000U /* DC 0 SS - slot 0 */ +#define DC_0_ADDR_0 (DC_0_SS_BASE0+0x00000U) /* DC 0 test addr 0 */ +#define DC_0_ADDR_1 (DC_0_SS_BASE0+0x10000U) /* DC 0 test addr 1 */ +#define DC_0_MSI_BASE (DC_0_SS_BASE0+0x200000U) /* DC_0 MSI CTRL */ +#define MIPI_0_SS_BASE (DC_0_SS_BASE0+0x220000U) /* MIPI 0 */ +#define LPI2C3_BASE (MIPI_0_SS_BASE+0x6000U) /* MIPI 0 LPI2C 0 */ +#define LPI2C4_BASE (MIPI_0_SS_BASE+0x7000U) /* MIPI 0 LPI2C 1 */ +#define LVDS_0_SS_BASE (DC_0_SS_BASE0+0x240000U) /* LVDS 0 */ +#define LPI2C5_BASE (LVDS_0_SS_BASE+0x6000U) /* LVDS 0 LPI2C 0 */ +#define LPI2C6_BASE (LVDS_0_SS_BASE+0x7000U) /* LVDS 0 LPI2C 1 */ +#define HDMI_SS_BASE (DC_0_SS_BASE0+0x260000U) /* HDMI */ +#define LPI2C7_BASE (HDMI_SS_BASE+0x6000U) /* HDMI LPI2C */ +#define DC_1_SS_BASE0 0x57000000U /* DC 1 SS - slot 0 */ +#define DC_1_ADDR_0 (DC_1_SS_BASE0+0x00000U) /* DC 1 test addr 0 */ +#define DC_1_ADDR_1 (DC_1_SS_BASE0+0x10000U) /* DC 1 test addr 1 */ +#define DC_1_MSI_BASE (DC_1_SS_BASE0+0x200000U) /* DC_1 MSI CTRL */ +#define MIPI_1_SS_BASE (DC_1_SS_BASE0+0x220000U) /* MIPI 1 */ +#define LPI2C8_BASE (MIPI_1_SS_BASE+0x6000U) /* MIPI 1 LPI2C 0 */ +#define LPI2C9_BASE (MIPI_1_SS_BASE+0x7000U) /* MIPI 1 LPI2C 1 */ +#define LVDS_1_SS_BASE (DC_1_SS_BASE0+0x240000U) /* LVDS 1 */ +#define LPI2C10_BASE (LVDS_1_SS_BASE+0x6000U) /* LVDS 1 LPI2C 0 */ +#define LPI2C11_BASE (LVDS_1_SS_BASE+0x7000U) /* LVDS 1 LPI2C 1 */ +#define IMG_SS_BASE0 0x58000000U /* IMG SS - slot 0 */ +#define IMG_0_GPIO_BASE (IMG_SS_BASE0+0x000000U) /* IMG GPIO */ +#define ISI0_BASE (IMG_SS_BASE0+0x100000U) /* IMG CH0 */ +#define ISI1_BASE (IMG_SS_BASE0+0x110000U) /* IMG CH1 */ +#define ISI2_BASE (IMG_SS_BASE0+0x120000U) /* IMG CH2 */ +#define ISI3_BASE (IMG_SS_BASE0+0x130000U) /* IMG CH3 */ +#define ISI4_BASE (IMG_SS_BASE0+0x140000U) /* IMG CH4 */ +#define ISI5_BASE (IMG_SS_BASE0+0x150000U) /* IMG CH5 */ +#define ISI6_BASE (IMG_SS_BASE0+0x160000U) /* IMG CH6 */ +#define ISI7_BASE (IMG_SS_BASE0+0x170000U) /* IMG CH7 */ +#define IMG_0_MSI_BASE (IMG_SS_BASE0+0x200000U) /* IMG MSI CTRL */ +#define CSI_0_SS_BASE (IMG_SS_BASE0+0x220000U) /* CSI 0 */ +#define LPI2C12_BASE (CSI_0_SS_BASE+0x6000U) /* CSI 0 LPI2C 0 */ +#define CSI_1_SS_BASE (IMG_SS_BASE0+0x240000U) /* CSI 1 */ +#define LPI2C13_BASE (CSI_1_SS_BASE+0x6000U) /* CSI 1 LPI2C 0 */ +#define HDMI_RX_SS_BASE (IMG_SS_BASE0+0x260000U) /* HDMI RX */ +#define LPI2C14_BASE (HDMI_RX_SS_BASE+0x6000U) /* HDMI RX LPI2C */ +#define AUDIO_SS_BASE0 0x59000000U /* AUDIO SS - slot 0 */ +#define DMA0_BASE (AUDIO_SS_BASE0+0x1F0000U) /* Audio eDMA 0 MP */ +#define DMA1_BASE (AUDIO_SS_BASE0+0x9F0000U) /* Audio eDMA 1 MP */ +#define DMA_SS_BASE0 0x5A000000U /* DMA SS - slot 0 */ +#define LPUART4_BASE (DMA_SS_BASE0+0x060000U) /* DMA LPUART 0 */ +#define LPUART5_BASE (DMA_SS_BASE0+0x070000U) /* DMA LPUART 1 */ +#define LPUART6_BASE (DMA_SS_BASE0+0x080000U) /* DMA LPUART 2 */ +#define LPUART7_BASE (DMA_SS_BASE0+0x090000U) /* DMA LPUART 3 */ +#define LPUART8_BASE (DMA_SS_BASE0+0x0A0000U) /* DMA LPUART 4 */ +#define DMA2_BASE (DMA_SS_BASE0+0x1F0000U) /* DMA eDMA 0 MP */ +#define LPI2C15_BASE (DMA_SS_BASE0+0x800000U) /* DMA LPI2C 0 */ +#define LPI2C16_BASE (DMA_SS_BASE0+0x810000U) /* DMA LPI2C 1 */ +#define LPI2C17_BASE (DMA_SS_BASE0+0x820000U) /* DMA LPI2C 2 */ +#define LPI2C18_BASE (DMA_SS_BASE0+0x830000U) /* DMA LPI2C 3 */ +#define LPI2C19_BASE (DMA_SS_BASE0+0x840000U) /* DMA LPI2C 4 */ +#define DMA3_BASE (DMA_SS_BASE0+0x9F0000U) /* DMA eDMA 1 MP */ +#define CONN_SS_BASE0 0x5B000000U /* CONN SS - slot 0 */ +#define SDHC0_BASE (CONN_SS_BASE0+0x010000U) /* CONN SDHC 0 */ +#define SDHC1_BASE (CONN_SS_BASE0+0x020000U) /* CONN SDHC 1 */ +#define SDHC2_BASE (CONN_SS_BASE0+0x030000U) /* CONN SDHC 2 */ +#define ENET0_BASE (CONN_SS_BASE0+0x040000U) /* CONN ENET 0 */ +#define ENET1_BASE (CONN_SS_BASE0+0x050000U) /* CONN ENET 1 */ +#define DMA4_BASE (CONN_SS_BASE0+0x070000U) /* CONN eDMA MP */ +#define USB_0_BASE (CONN_SS_BASE0+0x0D0000U) /* CONN USB 0 */ +#define USB_1_BASE (CONN_SS_BASE0+0x0E0000U) /* CONN USB 1 */ +#define USB_0_PHY_BASE (CONN_SS_BASE0+0x100000U) /* CONN USB 0 PHY */ +#define USB_1_PHY_BASE (CONN_SS_BASE0+0x110000U) /* CONN USB 1 PHY */ +#define ENET0_LPCG (CONN_SS_BASE0+0x230000U) /* CONN ENET 0 LPCG */ +#define NAND_BASE (CONN_SS_BASE0+0x810000U) /* CONN NAND */ +#define DB_SS_BASE0 0x5C000000U /* DB SS - slot 0 */ +#define DRC_0_LPCG_0 (DB_SS_BASE0+0x0C0000U) /* DRC 0 LPCG 0 */ +#define DRC_0_LPCG_1 (DB_SS_BASE0+0x0D0000U) /* DRC 0 LPCG 1 */ +#define DRC_0_LPCG_2 (DB_SS_BASE0+0x0E0000U) /* DRC 0 LPCG 2 */ +#define DRC_0_LPCG_3 (DB_SS_BASE0+0x0F0000U) /* DRC 0 LPCG 3 */ +#define DRC_1_LPCG_0 (DB_SS_BASE0+0x1C0000U) /* DRC 1 LPCG 0 */ +#define DRC_1_LPCG_1 (DB_SS_BASE0+0x1D0000U) /* DRC 1 LPCG 1 */ +#define DRC_1_LPCG_2 (DB_SS_BASE0+0x1E0000U) /* DRC 1 LPCG 2 */ +#define DRC_1_LPCG_3 (DB_SS_BASE0+0x1F0000U) /* DRC 1 LPCG 3 */ +#define STC0_BASE (DB_SS_BASE0+0x400000U) /* DB PG0 STC 0 */ +#define STC1_BASE (DB_SS_BASE0+0x410000U) /* DB PG0 STC 1 */ +#define STC2_BASE (DB_SS_BASE0+0x420000U) /* DB PG0 STC 2 */ +#define STC3_BASE (DB_SS_BASE0+0x430000U) /* DB PG0 STC 3 */ +#define DB_LPCG_PG0_BASE (DB_SS_BASE0+0x4F0000U) /* DB PG0 LPCG */ +#define STC4_BASE (DB_SS_BASE0+0x500000U) /* DB PG1 STC 0 */ +#define STC5_BASE (DB_SS_BASE0+0x510000U) /* DB PG1 STC 1 */ +#define STC6_BASE (DB_SS_BASE0+0x520000U) /* DB PG1 STC 2 */ +#define STC7_BASE (DB_SS_BASE0+0x530000U) /* DB PG1 STC 3 */ +#define DB_LPCG_PG1_BASE (DB_SS_BASE0+0x5F0000U) /* DB PG1 LPCG */ +#define STC8_BASE (DB_SS_BASE0+0x600000U) /* DB PG2 STC 0 */ +#define STC9_BASE (DB_SS_BASE0+0x610000U) /* DB PG2 STC 1 */ +#define STC10_BASE (DB_SS_BASE0+0x620000U) /* DB PG2 STC 2 */ +#define STC11_BASE (DB_SS_BASE0+0x630000U) /* DB PG2 STC 3 */ +#define DB_LPCG_PG2_BASE (DB_SS_BASE0+0x6F0000U) /* DB PG2 LPCG */ +#define STC12_BASE (DB_SS_BASE0+0x700000U) /* DB PG3 STC 0 */ +#define STC13_BASE (DB_SS_BASE0+0x710000U) /* DB PG3 STC 1 */ +#define STC14_BASE (DB_SS_BASE0+0x720000U) /* DB PG3 STC 2 */ +#define STC15_BASE (DB_SS_BASE0+0x730000U) /* DB PG3 STC 3 */ +#define DB_LPCG_PG3_BASE (DB_SS_BASE0+0x7F0000U) /* DB PG3 LPCG */ +#define DB_LPCG_BN_BASE (DB_SS_BASE0+0xAF0000U) /* DB BN LPCG */ +#define LSIO_SS_BASE0 0x5D000000U /* LSIO SS - slot 0 */ +#define PWM0_BASE (LSIO_SS_BASE0+0x000000U) /* LSIO PWM 0 */ +#define PWM1_BASE (LSIO_SS_BASE0+0x010000U) /* LSIO PWM 1 */ +#define PWM2_BASE (LSIO_SS_BASE0+0x020000U) /* LSIO PWM 2 */ +#define PWM3_BASE (LSIO_SS_BASE0+0x030000U) /* LSIO PWM 3 */ +#define PWM4_BASE (LSIO_SS_BASE0+0x040000U) /* LSIO PWM 4 */ +#define PWM5_BASE (LSIO_SS_BASE0+0x050000U) /* LSIO PWM 5 */ +#define PWM6_BASE (LSIO_SS_BASE0+0x060000U) /* LSIO PWM 6 */ +#define PWM7_BASE (LSIO_SS_BASE0+0x070000U) /* LSIO PWM 7 */ +#define GPIO0_BASE (LSIO_SS_BASE0+0x080000U) /* LSIO GPIO 0 */ +#define GPIO1_BASE (LSIO_SS_BASE0+0x090000U) /* LSIO GPIO 1 */ +#define GPIO2_BASE (LSIO_SS_BASE0+0x0A0000U) /* LSIO GPIO 2 */ +#define GPIO3_BASE (LSIO_SS_BASE0+0x0B0000U) /* LSIO GPIO 3 */ +#define GPIO4_BASE (LSIO_SS_BASE0+0x0C0000U) /* LSIO GPIO 4 */ +#define GPIO5_BASE (LSIO_SS_BASE0+0x0D0000U) /* LSIO GPIO 5 */ +#define GPIO6_BASE (LSIO_SS_BASE0+0x0E0000U) /* LSIO GPIO 6 */ +#define GPIO7_BASE (LSIO_SS_BASE0+0x0F0000U) /* LSIO GPIO 7 */ +#define FSPI0_BASE (LSIO_SS_BASE0+0x120000U) /* FSPI0 */ +#define FSPI1_BASE (LSIO_SS_BASE0+0x130000U) /* FSPI1 */ +#define GPT0_BASE (LSIO_SS_BASE0+0x140000U) /* LSIO GPT 0 */ +#define GPT1_BASE (LSIO_SS_BASE0+0x150000U) /* LSIO GPT 1 */ +#define GPT2_BASE (LSIO_SS_BASE0+0x160000U) /* LSIO GPT 2 */ +#define GPT3_BASE (LSIO_SS_BASE0+0x170000U) /* LSIO GPT 3 */ +#define GPT4_BASE (LSIO_SS_BASE0+0x180000U) /* LSIO GPT 4 */ +#define KPP_BASE (LSIO_SS_BASE0+0x1A0000U) /* LSIO KPP */ +#define MU11_BASE (LSIO_SS_BASE0+0x1B0000U) /* LSIO MU 0A */ +#define MU12_BASE (LSIO_SS_BASE0+0x1C0000U) /* LSIO MU 1A */ +#define MU13_BASE (LSIO_SS_BASE0+0x1D0000U) /* LSIO MU 2A */ +#define MU14_BASE (LSIO_SS_BASE0+0x1E0000U) /* LSIO MU 3A */ +#define MU15_BASE (LSIO_SS_BASE0+0x1F0000U) /* LSIO MU 4A */ +#define IEE_BASE (LSIO_SS_BASE0+0x320000U) /* IEE */ +#define IEE_R0_BASE (LSIO_SS_BASE0+0x330000U) /* IEE R0 */ +#define IEE_R1_BASE (LSIO_SS_BASE0+0x340000U) /* IEE R1 */ +#define HSIO_0_SS_BASE0 0x5F000000U /* HSIO 0 SS - slot 0 */ +#define HSIO_0_LPCG_GPIO (HSIO_0_SS_BASE0+0x100000U) /* HSIO 0 GPIO LPCG */ +#define HSIO_0_SS_BASE1 0x60000000U /* HSIO 0 SS - slot 1 */ +#define HSIO_0_SS_BASE2 0x70000000U /* HSIO 0 SS - slot 2 */ +#define DDR_BASE0 0x80000000U /* DDR */ +#define MCM_BASE 0xE0080000U /* SC MCM */ +#define LMEM_BASE 0xE0082000U /* SC LMEM */ +#define DDR_BASE0_END 0xFFFFFFFFU /* Top of DDR 0 */ +#define LSIO_SS_BASE2 0x400000000ULL /* LSIO SS - slot 2 */ +#define FSPI1_MEM_BASE (LSIO_SS_BASE2+0x0U) /* FlexSPI1 Memory */ +#define DDR_BASE1 0x880000000ULL /* DDR - Hi */ +#define DDR_BASE1_END 0xFFFFFFFFFULL /* Top of DDR 1 */ + +/* Unused */ + +#define DSC2_BASE 0 +#define DSC3_BASE 0 +#define DSC4_BASE 0 +#define DSC5_BASE 0 +#define DSC6_BASE 0 +#define DSC7_BASE 0 +#define DSC8_BASE 0 +#define DSC9_BASE 0 +#define DSC10_BASE 0 +#define DSC11_BASE 0 +#define DSC12_BASE 0 +#define DSC13_BASE 0 +#define DSC14_BASE 0 +#define DSC15_BASE 0 +#define DSC24_BASE 0 +#define DSC26_BASE 0 +#define DSC27_BASE 0 +#define DSC28_BASE 0 +#define DSC29_BASE 0 +#define DSC30_BASE 0 +#define DSC31_BASE 0 +#define DSC42_BASE 0 +#define DSC43_BASE 0 +#define DSC44_BASE 0 +#define DSC45_BASE 0 +#define DSC46_BASE 0 +#define DSC47_BASE 0 +#define DSC60_BASE 0 +#define DSC61_BASE 0 +#define DSC62_BASE 0 +#define DSC63_BASE 0 +#define LPI2C20_BASE 0 +#define LPI2C21_BASE 0 +#define LPI2C22_BASE 0 +#define LPI2C23_BASE 0 +#define LPI2C24_BASE 0 +#define LPI2C25_BASE 0 +#define DMA5_BASE 0 +#define DMA6_BASE 0 +#define ISI8_BASE 0 +#define ISI9_BASE 0 +#define ISI10_BASE 0 +#define ISI11_BASE 0 +#define ISI12_BASE 0 +#define ISI13_BASE 0 +#define ISI14_BASE 0 +#define ISI15_BASE 0 +#define ISI16_BASE 0 +#define ISI17_BASE 0 +#define ISI18_BASE 0 +#define ISI19_BASE 0 +#define ISI20_BASE 0 +#define ISI21_BASE 0 +#define ISI22_BASE 0 +#define ISI23_BASE 0 +#define MU16_BASE 0 +#define MU17_BASE 0 +#define MU18_BASE 0 +#define MU19_BASE 0 +#define MU20_BASE 0 +#define MU21_BASE 0 +#define MU22_BASE 0 +#define MU23_BASE 0 +#define MU24_BASE 0 +#define STC16_BASE 0 +#define STC17_BASE 0 +#define STC18_BASE 0 +#define STC19_BASE 0 +#define STC20_BASE 0 +#define STC21_BASE 0 +#define STC22_BASE 0 +#define STC23_BASE 0 + + +/* ---------------------------------------------------------------------------- + -- Device Mapping + ---------------------------------------------------------------------------- */ + +#define DMA_AUDIO0 DMA0 +#define DMA_AUDIO1 DMA1 +#define DMA_PERIPH0 DMA2 +#define DMA_PERIPH1 DMA3 +#define DMA_CONN DMA4 +#define DSC_SC DSC1 +#define DSC_MCU_0 DSC17 +#define DSC_DRC_0 DSC18 +#define DSC_DC_1 DSC19 +#define DSC_MCU_1 DSC20 +#define DSC_GPU_1 DSC21 +#define DSC_CONN DSC22 +#define DSC_VPU DSC23 +#define DSC_CCI DSC25 +#define DSC_AP_1 DSC33 +#define DSC_DB DSC34 +#define DSC_AP_0 DSC35 +#define DSC_HSIO DSC36 +#define DSC_LSIO DSC37 +#define DSC_GPU_0 DSC38 +#define DSC_DC_0 DSC39 +#define DSC_DRC_1 DSC40 +#define DSC_DMA DSC41 +#define DSC_DBLOG DSC49 +#define DSC_IMG DSC50 +#define DSC_AUDIO DSC51 +#define DSC_HDMI DSC52 +#define DSC_HDMI_RX DSC53 +#define DSC_CSI_1 DSC54 +#define DSC_CSI_0 DSC55 +#define DSC_MIPI_1 DSC56 +#define DSC_MIPI_0 DSC57 +#define DSC_LVDS_1 DSC58 +#define DSC_LVDS_0 DSC59 +#define GPIO_SC RGPIOA +#define GPIO_MCU_0 RGPIOB +#define GPIO_MCU_1 RGPIOC +#define ISI_IMG_0_CH0 ISI0 +#define ISI_IMG_0_CH1 ISI1 +#define ISI_IMG_0_CH2 ISI2 +#define ISI_IMG_0_CH3 ISI3 +#define ISI_IMG_0_CH4 ISI4 +#define ISI_IMG_0_CH5 ISI5 +#define ISI_IMG_0_CH6 ISI6 +#define ISI_IMG_0_CH7 ISI7 +#define LPI2C_SC LPI2C0 +#define LPI2C_MCU_0 LPI2C1 +#define LPI2C_MCU_1 LPI2C2 +#define LPI2C_MIPI0_0 LPI2C3 +#define LPI2C_MIPI0_1 LPI2C4 +#define LPI2C_LVDS0_0 LPI2C5 +#define LPI2C_LVDS0_1 LPI2C6 +#define LPI2C_HDMI LPI2C7 +#define LPI2C_MIPI1_0 LPI2C8 +#define LPI2C_MIPI1_1 LPI2C9 +#define LPI2C_LVDS1_0 LPI2C10 +#define LPI2C_LVDS1_1 LPI2C11 +#define LPI2C_CSI0_0 LPI2C12 +#define LPI2C_CSI1_0 LPI2C13 +#define LPI2C_HDMI_RX LPI2C14 +#define LPI2C_0 LPI2C15 +#define LPI2C_1 LPI2C16 +#define LPI2C_2 LPI2C17 +#define LPI2C_3 LPI2C18 +#define LPI2C_4 LPI2C19 +#define LPIT_SC LPIT0 +#define LPUART_SC LPUART0 +#define LPUART_VPU_0 LPUART1 +#define LPUART_MCU_0 LPUART2 +#define LPUART_MCU_1 LPUART3 +#define LPUART_0 LPUART4 +#define LPUART_1 LPUART5 +#define LPUART_2 LPUART6 +#define LPUART_3 LPUART7 +#define LPUART_4 LPUART8 +#define MU_SECO MU0 +#define MU_SC_0B MU1 +#define MU_SC_0A0 MU2 +#define MU_SC_0A1 MU3 +#define MU_SC_0A2 MU4 +#define MU_SC_0A3 MU5 +#define MU_SC_1A MU6 +#define MU_VPU_0 MU7 +#define MU_VPU_1 MU8 +#define MU_MCU_0_1A MU9 +#define MU_MCU_1_1A MU10 +#define MU_LSIO_0A MU11 +#define MU_LSIO_1A MU12 +#define MU_LSIO_2A MU13 +#define MU_LSIO_3A MU14 +#define MU_LSIO_4A MU15 +#define STC_PG0_0 STC0 +#define STC_PG0_1 STC1 +#define STC_PG0_2 STC2 +#define STC_PG0_3 STC3 +#define STC_PG1_0 STC4 +#define STC_PG1_1 STC5 +#define STC_PG1_2 STC6 +#define STC_PG1_3 STC7 +#define STC_PG2_0 STC8 +#define STC_PG2_1 STC9 +#define STC_PG2_2 STC10 +#define STC_PG2_3 STC11 +#define STC_PG3_0 STC12 +#define STC_PG3_1 STC13 +#define STC_PG3_2 STC14 +#define STC_PG3_3 STC15 +#define TCMU_SC TCMU0_BASE +#define TCMU_MCU_0 TCMU1_BASE +#define TCMU_MCU_1 TCMU2_BASE +#define TCML_SC TCML0_BASE +#define TCML_MCU_0 TCML1_BASE +#define TCML_MCU_1 TCML2_BASE +#define WDOG_SC WDOG0 +#define WDOG_MCU_0 WDOG1 +#define WDOG_MCU_1 WDOG2 + +/* ---------------------------------------------------------------------------- + -- CoreSight Granular Power Requestor Mappings + ---------------------------------------------------------------------------- */ +#define CSGPR_CPWRUPREQ (CSGPR_BASE+0x000U) +#define CSGPR_CPWRUPACK (CSGPR_BASE+0x004U) +#define CSGPR_CLAIMSET (CSGPR_BASE+0xFA0U) +#define CSGPR_CLAIMCLR (CSGPR_BASE+0xFA4U) +#define CSGPR_LAR (CSGPR_BASE+0xFB0U) +#define CSGPR_LSR (CSGPR_BASE+0xFB4U) + +#define CSGPR_IDX_A72 4U +#define CSGPR_IDX_A53 5U +#define CSGPR_IDX_MCU_0 6U +#define CSGPR_IDX_MCU_1 7U +#define CSGPR_IDX_VPU 8U + +#define CSGPR_XOR_DSC_REG 1U +#define CSGPR_XOR_DSC_MASK 0x0000FFFFU +#define CSGPR_ACK_DSC_REG 2U +#define CSGPR_ACK_DSC_MASK 0xFFFF0000U + +/* ---------------------------------------------------------------------------- + -- GIC Mappings + ---------------------------------------------------------------------------- */ +#define GICD_BASE (GIC0_BASE+0x000000U) +#define GICR_BASE (GIC0_BASE+0x100000U) + +#define GICD_CTLR_OFS (0x0000U) +#define GICD_CTLR_RWP_MASK (0x80000000U) + +#define GICR_WAKER_OFS (0x0014U) +#define GICR_WAKER_PA_MASK (0x00000002U) +#define GICR_WAKER_CA_MASK (0x00000004U) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 256 /**< Number of interrupts in the Vector table */ + +/* Auxiliary constants */ +#define NotAvail_IRQn -128 /**< Not available device specific interrupt */ + +/* Core interrupts */ +#define NonMaskableInt_IRQn -14 /**< Non Maskable Interrupt */ +#define HardFault_IRQn -13 /**< Cortex-M4 SV Hard Fault Interrupt */ +#define MemoryManagement_IRQn -12 /**< Cortex-M4 Memory Management Interrupt */ +#define BusFault_IRQn -11 /**< Cortex-M4 Bus Fault Interrupt */ +#define UsageFault_IRQn -10 /**< Cortex-M4 Usage Fault Interrupt */ +#define SVCall_IRQn -5 /**< Cortex-M4 SV Call Interrupt */ +#define DebugMonitor_IRQn -4 /**< Cortex-M4 Debug Monitor Interrupt */ +#define PendSV_IRQn -2 /**< Cortex-M4 Pend SV Interrupt */ +#define SysTick_IRQn -1 /**< Cortex-M4 System Tick Interrupt */ + +/* Device specific interrupts */ +#define Reserved0_IRQn 0 /**< Reserved interrupt */ +#define Reserved1_IRQn 1 /**< Reserved interrupt */ +#define Reserved2_IRQn 2 /**< Reserved interrupt */ +#define Reserved3_IRQn 3 /**< Reserved interrupt */ +#define Reserved4_IRQn 4 /**< Reserved interrupt */ +#define MCM_IRQn 5 /**< MCM interrupt */ +#define DebugWake_IRQn 6 /**< Debug wake interrupt */ +#define OCOTP_Bank0_IRQn 7 /**< OCOTP bank0 interrupt */ +#define OCOTP_Bank1_IRQn 8 /**< OCOTP bank1 interrupt */ +#define Reserved9_IRQn 9 /**< Reserved interrupt */ +#define INTMUX0_8_IRQn 10 /**< INTMUX0_8 interrupt */ +#define INTMUX0_9_IRQn 11 /**< INTMUX0_9 interrupt */ +#define INTMUX0_10_IRQn 12 /**< INTMUX0_10 interrupt */ +#define INTMUX0_11_IRQn 13 /**< INTMUX0_11 interrupt */ +#define INTMUX0_12_IRQn 14 /**< INTMUX0_12 interrupt */ +#define INTMUX0_13_IRQn 15 /**< INTMUX0_13 interrupt */ +#define INTMUX0_14_IRQn 16 /**< INTMUX0_14 interrupt */ +#define INTMUX0_15_IRQn 17 /**< INTMUX0_15 interrupt */ +#define Reserved18_IRQn 18 /**< Reserved interrupt */ +#define TPM0_IRQn 19 /**< TPM0 interrupt */ +#define Reserved20_IRQn 20 /**< Reserved interrupt */ +#define Reserved21_IRQn 21 /**< Reserved interrupt */ +#define LPIT0_IRQn 22 /**< LPIT0 interrupt */ +#define Reserved23_IRQn 23 /**< Reserved interrupt */ +#define Reserved24_IRQn 24 /**< Reserved interrupt */ +#define LPUART0_IRQn 25 /**< LPUART0 interrupt */ +#define Reserved26_IRQn 26 /**< Reserved interrupt */ +#define LPI2C0_IRQn 27 /**< LPI2C0 interrupt */ +#define Reserved28_IRQn 28 /**< Reserved interrupt */ +#define MU0_B0_IRQn 29 /**< MU0_B0 interrupt */ +#define SECO_MU_NMI_IRQn 30 /**< SECO_MU_NMI interrupt */ +#define SECO_MU_IRQn 31 /**< SECO_MU interrupt */ +#define INTMUX0_0_IRQn 32 /**< INTMUX0_0 interrupt */ +#define INTMUX0_1_IRQn 33 /**< INTMUX0_1 interrupt */ +#define INTMUX0_2_IRQn 34 /**< INTMUX0_2 interrupt */ +#define INTMUX0_3_IRQn 35 /**< INTMUX0_3 interrupt */ +#define INTMUX0_4_IRQn 36 /**< INTMUX0_4 interrupt */ +#define INTMUX0_5_IRQn 37 /**< INTMUX0_5 interrupt */ +#define INTMUX0_6_IRQn 38 /**< INTMUX0_6 interrupt */ +#define INTMUX0_7_IRQn 39 /**< INTMUX0_7 interrupt */ +#define SYSCTR_CMP3_IRQn 40 /**< SYSCTR_CMP3 interrupt */ +#define SYSCTR_CMP2_IRQn 41 /**< SYSCTR_CMP2 interrupt */ +#define SYSCTR_CMP1_IRQn 42 /**< SYSCTR_CMP1 interrupt */ +#define SYSCTR_CMP0_IRQn 43 /**< SYSCTR_CMP0 interrupt */ +#define MU0_B1_IRQn 44 /**< MU0_B1 interrupt */ +#define MU0_B2_IRQn 45 /**< MU0_B2 interrupt */ +#define MU0_B3_IRQn 46 /**< MU0_B3 interrupt */ +#define PMIC_INT_IRQn 47 /**< PMIC_INT interrupt */ +#define PMIC_EarlyWarning_IRQn 48 /**< PMIC_EarlyWarning interrupt */ +#define MU1_A_IRQn 49 /**< MU1_A interrupt */ +#define SWI_IRQn 50 /**< Software interrupt */ +#define SWI_DQS2DQ_IRQn 51 /**< DQS2DQ Software interrupt */ +#define CAAM_IRQ0_IRQn 52 /**< CAAM_IRQ0 interrupt */ +#define CAAM_IRQ1_IRQn 53 /**< CAAM_IRQ1 interrupt */ +#define CAAM_IRQ2_IRQn 54 /**< CAAM_IRQ2 interrupt */ +#define CAAM_IRQ3_IRQn 55 /**< CAAM_IRQ3 interrupt */ +#define CAAM_RTIC_IRQn 56 /**< CAAM_RTIC interrupt */ +#define CAAM_Error_IRQn 57 /**< CAAM_Error interrupt */ +#define SNVS_Functional_IRQn 58 /**< SNVS_Functional interrupt */ +#define SNVS_SecurityViolation_IRQn 59 /**< SNVS_SecurityViolation interrupt */ +#define SNVS_Periodic_IRQn 60 /**< SNVS_Periodic interrupt */ +#define SNVS_Button_IRQn 61 /**< SNVS_Button interrupt */ +#define SNVS_Alarm_IRQn 62 /**< Reserved interrupt */ +#define SNVS_PowerOff_IRQn 63 /**< Reserved interrupt */ +#define DSC00_IRQn 64 /**< DSC0 interrupt */ +#define DSC_SCU_IRQn 64 /**< DSC0 interrupt */ +#define DSC_DB_IRQn 65 /**< DSC1 interrupt */ +#define DSC_DRC_1_IRQn 66 /**< DSC2 interrupt */ +#define DSC03_IRQn 67 /**< DSC3 interrupt */ +#define DSC_HSIO_IRQn 68 /**< DSC4 interrupt */ +#define DSC_CA72_IRQn 69 /**< DSC5 interrupt */ +#define DSC_CCI_IRQn 70 /**< DSC6 interrupt */ +#define DSC_CM4_0_IRQn 71 /**< DSC7 interrupt */ +#define DSC_CM4_1_IRQn 72 /**< DSC8 interrupt */ +#define DSC_GPU_1_IRQn 73 /**< DSC9 interrupt */ +#define DSC_LSIO_IRQn 74 /**< DSC10 interrupt */ +#define DSC_GPU_0_IRQn 75 /**< DSC11 interrupt */ +#define DSC_CA53_IRQn 76 /**< DSC12 interrupt */ +#define DSC_DBLOG_IRQn 77 /**< DSC13 interrupt */ +#define DSC_DC_1_IRQn 78 /**< DSC14 interrupt */ +#define DSC_VPUCORE_IRQn 79 /**< DSC15 interrupt */ +#define DSC_Connectivity_IRQn 80 /**< DSC16 interrupt */ +#define DSC_DI_LVDS_0_IRQn 81 /**< DSC17 interrupt */ +#define DSC_DI_LVDS_1_IRQn 82 /**< DSC18 interrupt */ +#define DSC_DMA_IRQn 83 /**< DSC19 interrupt */ +#define DSC_VPU_IRQn 84 /**< DSC20 interrupt */ +#define DSC21_IRQn 85 /**< DSC21 interrupt */ +#define DSC_DRC_0_IRQn 86 /**< DSC22 interrupt */ +#define DSC_DC_0_IRQn 87 /**< DSC23 interrupt */ +#define DSC_MIPI_CSI_0_IRQn 88 /**< DSC24 interrupt */ +#define DSC_MIPI_CSI_1_IRQn 89 /**< DSC25 interrupt */ +#define DSC_RX_HDMI_IRQn 90 /**< DSC26 interrupt */ +#define DSC_Imaging_IRQn 91 /**< DSC27 interrupt */ +#define DSC_Audio_IRQn 92 /**< DSC28 interrupt */ +#define DSC_DI_HDMI_IRQn 93 /**< DSC29 interrupt */ +#define DSC_DI_MIPI_0_IRQn 94 /**< DSC30 interrupt */ +#define DSC_DI_MIPI_1_IRQn 95 /**< DSC31 interrupt */ +#define DSC31_IRQn 95 /**< DSC31 interrupt */ +#define IOMUX31_IRQn 96 /**< IOMUX31 interrupt */ +#define IOMUX30_IRQn 97 /**< IOMUX30 interrupt */ +#define IOMUX29_IRQn 98 /**< IOMUX29 interrupt */ +#define IOMUX28_IRQn 99 /**< IOMUX28 interrupt */ +#define IOMUX27_IRQn 100 /**< IOMUX27 interrupt */ +#define IOMUX26_IRQn 101 /**< IOMUX26 interrupt */ +#define IOMUX25_IRQn 102 /**< IOMUX25 interrupt */ +#define IOMUX24_IRQn 103 /**< IOMUX24 interrupt */ +#define IOMUX23_IRQn 104 /**< IOMUX23 interrupt */ +#define IOMUX22_IRQn 105 /**< IOMUX22 interrupt */ +#define IOMUX21_IRQn 106 /**< IOMUX21 interrupt */ +#define IOMUX20_IRQn 107 /**< IOMUX20 interrupt */ +#define IOMUX19_IRQn 108 /**< IOMUX19 interrupt */ +#define IOMUX18_IRQn 109 /**< IOMUX18 interrupt */ +#define IOMUX17_IRQn 110 /**< IOMUX17 interrupt */ +#define IOMUX16_IRQn 111 /**< IOMUX16 interrupt */ +#define IOMUX15_IRQn 112 /**< IOMUX15 interrupt */ +#define IOMUX14_IRQn 113 /**< IOMUX14 interrupt */ +#define IOMUX13_IRQn 114 /**< IOMUX13 interrupt */ +#define IOMUX12_IRQn 115 /**< IOMUX12 interrupt */ +#define IOMUX11_IRQn 116 /**< IOMUX11 interrupt */ +#define IOMUX10_IRQn 117 /**< IOMUX10 interrupt */ +#define IOMUX9_IRQn 118 /**< IOMUX9 interrupt */ +#define IOMUX8_IRQn 119 /**< IOMUX8 interrupt */ +#define IOMUX7_IRQn 120 /**< IOMUX7 interrupt */ +#define IOMUX6_IRQn 121 /**< IOMUX6 interrupt */ +#define IOMUX5_IRQn 122 /**< IOMUX5 interrupt */ +#define IOMUX4_IRQn 123 /**< IOMUX4 interrupt */ +#define IOMUX3_IRQn 124 /**< IOMUX3 interrupt */ +#define IOMUX2_IRQn 125 /**< IOMUX2 interrupt */ +#define IOMUX1_IRQn 126 /**< IOMUX1 interrupt */ +#define IOMUX0_IRQn 127 /**< IOMUX0 interrupt */ +#define NUM_NVIC_IRQn 128 /**< Number of NVIC interrupts */ + +typedef int IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex-M Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex-M Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MX8QM.h" /* Device specific configuration file */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t LDRD (const __IO uint32_t *addr) +{ + union + { + uint32_t w32[2]; + uint64_t w64; + } llr; + + __ASM volatile ("ldrd %0, %1, %2" : "=r" (llr.w32[0]), "=r" (llr.w32[1]) : "Q" (*addr) ); + + return(llr.w64); +} + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + +#endif /* MX8QM_H */ + +/* MX8QM.h, eof. */ diff --git a/platform/devices/MX8QM/MX8QM_features.h b/platform/devices/MX8QM/MX8QM_features.h new file mode 100755 index 0000000..3142674 --- /dev/null +++ b/platform/devices/MX8QM/MX8QM_features.h @@ -0,0 +1,460 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef MX8_FEATURES_H +#define MX8_FEATURES_H + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0U) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0U) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0U) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0U) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0U) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0U) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0U) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0U) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0U) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0U) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0U) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0U) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0U) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0U) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0U) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0U) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0U) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0U) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (2U) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0U) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0U) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0U) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0U) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (5U) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0U) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0U) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0U) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0U) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0U) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (1U) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0U) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0U) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0U) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0U) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0U) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0U) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0U) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0U) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0U) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0U) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (3U) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (8U) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0U) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (0U) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0U) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0U) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0U) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0U) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0U) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0U) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0U) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0U) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0U) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (1U) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0U) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0U) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0U) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8U) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0U) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (20U) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0U) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (1U) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0U) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0U) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0U) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0U) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0U) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0U) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0U) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0U) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0U) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0U) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0U) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (16U) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0U) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0U) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0U) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0U) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0U) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0U) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0U) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0U) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0U) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0U) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0U) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0U) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0U) +/* @brief QuadSPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPIO_COUNT (0U) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0U) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0U) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0U) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0U) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0U) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0U) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0U) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (0U) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0U) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0U) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0U) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0U) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0U) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1U) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0U) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0U) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0U) +/* @brief STC availability on the SoC. */ +#define FSL_FEATURE_SOC_STC_COUNT (16U) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0U) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0U) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0U) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0U) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0U) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0U) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0U) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0U) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0U) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0U) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0U) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0U) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0U) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (3U) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0U) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0U) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0U) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0U) + +/* LMEM module features */ + +/* @brief Has process identifier support. */ +#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1U) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0U) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1U) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1U) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1U) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1U) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0U) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0U) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1U) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1U) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0U) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0U) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1U) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0U) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1U) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART_SC) ? (32) : \ + (((x) == LPUART_MCU_0) ? (32) : \ + (((x) == LPUART_MCU_1) ? (32) : \ + (((x) == LPUART_0) ? (64) : \ + (((x) == LPUART_1) ? (64) : \ + (((x) == LPUART_2) ? (64) : \ + (((x) == LPUART_3) ? (64) : \ + (((x) == LPUART_4) ? (64) : (-1))))))))) + +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10U) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1U) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0U) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0U) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1U) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0U) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0U) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0U) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1U) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0U) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0U) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == 0 ? (0) : (-1)) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1U) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1U) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1U) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1U) +#define FSL_FEATURE_LPUART0_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART1_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART2_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART3_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART4_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART5_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART6_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART7_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART8_HAS_NO_IRQ (1U) + +/* MU module features */ + +/* @brief MU side for current core */ +#define FSL_FEATURE_MU_SIDE_A (0U) +#define FSL_FEATURE_MU_NO_RSTH (1U) +#define FSL_FEATURE_MU_NO_HR (1U) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1U) +/* @brief WDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1U) + +/* LPI2C module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4U) + +#define FSL_FEATURE_I2C_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C0_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C1_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C2_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C3_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C4_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C5_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C6_HAS_NO_IRQ (1U) + +/* PORT module features */ + +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1U) + +/* GPIO module features */ + +#define FSL_FEATURE_GPIO_HAS_NO_INTERRUPT (1U) + +/* PAD module features */ + +/* @brief Pads are for 28LPP. */ +#define FSL_FEATURE_PAD_HAS_28LPP (0U) +/* @brief Pads are for 28FDSOI. */ +#define FSL_FEATURE_PAD_HAS_28FDSOI (1U) + +/* SECO module features */ + +/* @brief SECO protocol version */ +#define FSL_FEATURE_SECO_VER (1U) + +/* OTP module features */ + +#define FSL_FEATURE_OTP_8K_OFS_START (16U) +#define FSL_FEATURE_OTP_8K_OFS_END (271U) +#define FSL_FEATURE_OTP_16K_OFS_START (288U) +#define FSL_FEATURE_OTP_16K_OFS_END (799U) + +#define FSL_FEATURE_DPLL_VER (18U) +#define FSL_FEATURE_AV_PLL_ENABLE_ALT (1U) + +#define FSL_FEATURE_PCIE_DPLL_SS (0U) + +/* CSR module features */ +#define FSL_FEATURE_CSR_HAS_CSR (0U) +#define FSL_FEATURE_CSR_HAS_CSR2 (1U) +#define FSL_FEATURE_CSR_HAS_CSR3 (1U) +#define FSL_FEATURE_CSR_HAS_LPCG (0U) + +/* DSC config */ +#define FSL_FEATURE_DSC_SSSLICE_CNT (8U) +#define FSL_FEATURE_DSC_SLSLICE_CNT (17U) +#define FSL_FEATURE_DSC_CSLICE_CNT (1U) +#define FSL_FEATURE_DSC_GPR_CTRL_CNT (3U) + +#endif /* MX8_FEATURES_H_ */ + diff --git a/platform/devices/MX8QM/MX8QM_fuse_map.h b/platform/devices/MX8QM/MX8QM_fuse_map.h new file mode 100755 index 0000000..08284b8 --- /dev/null +++ b/platform/devices/MX8QM/MX8QM_fuse_map.h @@ -0,0 +1,307 @@ +/* +** ################################################################### +** Processors: MX8QM +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8QM +** +** Copyright 2017-2018 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef HW_FUSES_H +#define HW_FUSES_H + +/******************************************************************************* + * Macros + ******************************************************************************/ + +#if !defined(NO_DEVICE_ACCESS) + #define OTP_GET_FUSE_STATE(_REG, SHFT, MSK) \ + ((((uint32_t)(OTP->FUSE[(_REG)].RW)) >> (SHFT)) & (MSK)) +#else + #define OTP_GET_FUSE_STATE(_REG, SHFT, MSK) \ + (((temp_fuses[(_REG)]) >> (SHFT)) & (MSK)) +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define OTP_CAAM_DIS OTP_GET_FUSE_STATE(0x003U, 0U, 0x00000001U) +#define OTP_IEE_DIS OTP_GET_FUSE_STATE(0x003U, 1U, 0x00000001U) +#define OTP_DTCP_DIS OTP_GET_FUSE_STATE(0x003U, 2U, 0x00000001U) +#define OTP_HDCP_DIS OTP_GET_FUSE_STATE(0x003U, 3U, 0x00000001U) +#define OTP_MMCAU_DIS OTP_GET_FUSE_STATE(0x003U, 4U, 0x00000001U) +#define OTP_ARM_CRYPT_EXT OTP_GET_FUSE_STATE(0x003U, 5U, 0x00000001U) +#define OTP_SNVS_DIS OTP_GET_FUSE_STATE(0x003U, 10U, 0x00000001U) +#define OTP_SECO_CLOSED_83 OTP_GET_FUSE_STATE(0x003U, 12U, 0x00000001U) +#define OTP_SECO_SECURED_83 OTP_GET_FUSE_STATE(0x003U, 13U, 0x00000001U) +#define OTP_ATTEST_DIS OTP_GET_FUSE_STATE(0x003U, 14U, 0x00000001U) +#define OTP_PUF_ENB OTP_GET_FUSE_STATE(0x003U, 15U, 0x00000001U) +#define OTP_FUSE_LIFE_CYCLE OTP_GET_FUSE_STATE(0x004U, 0U, 0x000003FFU) +#define OTP_SDP_DIS OTP_GET_FUSE_STATE(0x004U, 10U, 0x00000001U) +#define OTP_SDP_W_ONLY OTP_GET_FUSE_STATE(0x004U, 11U, 0x00000001U) +#define OTP_SREV_XOR OTP_GET_FUSE_STATE(0x004U, 12U, 0x00000007U) +#define OTP_SREV_ROM OTP_GET_FUSE_STATE(0x004U, 15U, 0x00000001U) +#define OTP_SJC_DIS OTP_GET_FUSE_STATE(0x005U, 0U, 0x00000001U) +#define OTP_JTAG_SEC_MODE OTP_GET_FUSE_STATE(0x005U, 1U, 0x00000003U) +#define OTP_TZ_DBG_DIS OTP_GET_FUSE_STATE(0x005U, 3U, 0x00000001U) +#define OTP_OEM_SEC_CONFIG OTP_GET_FUSE_STATE(0x005U, 5U, 0x00000003U) +#define OTP_SCU_SEC_CONFIG OTP_GET_FUSE_STATE(0x005U, 7U, 0x00000003U) +#define OTP_SECO_GLITCH_DET OTP_GET_FUSE_STATE(0x005U, 9U, 0x00000001U) +#define OTP_OTP_CHLG_RESP_DIS OTP_GET_FUSE_STATE(0x005U, 10U, 0x00000001U) +#define OTP_TZ_CHLG_RESP_DIS OTP_GET_FUSE_STATE(0x005U, 11U, 0x00000001U) +#define OTP_ARRAY_IS_PROG OTP_GET_FUSE_STATE(0x005U, 15U, 0x00000001U) +#define OTP_AP_0_DIS OTP_GET_FUSE_STATE(0x006U, 0U, 0x0000000FU) +#define OTP_AP_0_0_DIS OTP_GET_FUSE_STATE(0x006U, 0U, 0x00000001U) +#define OTP_AP_0_1_DIS OTP_GET_FUSE_STATE(0x006U, 1U, 0x00000001U) +#define OTP_AP_0_2_DIS OTP_GET_FUSE_STATE(0x006U, 2U, 0x00000001U) +#define OTP_AP_0_3_DIS OTP_GET_FUSE_STATE(0x006U, 3U, 0x00000001U) +#define OTP_AP_1_DIS OTP_GET_FUSE_STATE(0x006U, 4U, 0x00000003U) +#define OTP_AP_1_0_DIS OTP_GET_FUSE_STATE(0x006U, 4U, 0x00000001U) +#define OTP_AP_1_1_DIS OTP_GET_FUSE_STATE(0x006U, 5U, 0x00000001U) +#define OTP_AP_0_MAX_FREQ OTP_GET_FUSE_STATE(0x006U, 8U, 0x0000000FU) +#define OTP_AP_1_MAX_FREQ OTP_GET_FUSE_STATE(0x006U, 12U, 0x0000000FU) +#define OTP_GPU_0_DIS OTP_GET_FUSE_STATE(0x007U, 0U, 0x00000001U) +#define OTP_GPU_1_DIS OTP_GET_FUSE_STATE(0x007U, 1U, 0x00000001U) +#define OTP_GPU_MAX_FREQ OTP_GET_FUSE_STATE(0x007U, 4U, 0x0000000FU) +#define OTP_DC_0_DIS OTP_GET_FUSE_STATE(0x007U, 8U, 0x00000003U) +#define OTP_DC_1_DIS OTP_GET_FUSE_STATE(0x007U, 10U, 0x00000003U) +#define OTP_VPU_DIS OTP_GET_FUSE_STATE(0x007U, 12U, 0x0000000FU) +#define OTP_VPU_ENC0_DIS OTP_GET_FUSE_STATE(0x007U, 12U, 0x00000001U) +#define OTP_VPU_ENC1_DIS OTP_GET_FUSE_STATE(0x007U, 13U, 0x00000001U) +#define OTP_VPU_DEC_DIS OTP_GET_FUSE_STATE(0x007U, 14U, 0x00000003U) +#define OTP_DSP_DIS OTP_GET_FUSE_STATE(0x008U, 0U, 0x00000001U) +#define OTP_MCU_0_DIS OTP_GET_FUSE_STATE(0x008U, 1U, 0x00000001U) +#define OTP_MCU_1_DIS OTP_GET_FUSE_STATE(0x008U, 2U, 0x00000001U) +#define OTP_SATA_DIS OTP_GET_FUSE_STATE(0x008U, 4U, 0x00000001U) +#define OTP_PCIE_A_DIS OTP_GET_FUSE_STATE(0x008U, 5U, 0x00000001U) +#define OTP_PCIE_B_DIS OTP_GET_FUSE_STATE(0x008U, 6U, 0x00000001U) +#define OTP_USB2_1_DIS OTP_GET_FUSE_STATE(0x008U, 8U, 0x00000001U) +#define OTP_USB2_2_OTG_DIS OTP_GET_FUSE_STATE(0x008U, 9U, 0x00000001U) +#define OTP_USB_SS_DIS OTP_GET_FUSE_STATE(0x008U, 10U, 0x00000001U) +#define OTP_USB2_3_OTG_DIS OTP_GET_FUSE_STATE(0x008U, 11U, 0x00000001U) +#define OTP_ETH_0_DIS OTP_GET_FUSE_STATE(0x008U, 12U, 0x00000001U) +#define OTP_ETH_1_DIS OTP_GET_FUSE_STATE(0x008U, 13U, 0x00000001U) +#define OTP_HDMI_TX_DIS OTP_GET_FUSE_STATE(0x009U, 0U, 0x00000001U) +#define OTP_MIPI_0_DIS OTP_GET_FUSE_STATE(0x009U, 1U, 0x00000001U) +#define OTP_MIPI_1_DIS OTP_GET_FUSE_STATE(0x009U, 2U, 0x00000001U) +#define OTP_HDMI_RX_DIS OTP_GET_FUSE_STATE(0x009U, 4U, 0x00000001U) +#define OTP_CSI_0_DIS OTP_GET_FUSE_STATE(0x009U, 5U, 0x00000001U) +#define OTP_CSI_1_DIS OTP_GET_FUSE_STATE(0x009U, 6U, 0x00000001U) +#define OTP_CSI_2_DIS OTP_GET_FUSE_STATE(0x009U, 7U, 0x00000001U) +#define OTP_DRC_0_DIS OTP_GET_FUSE_STATE(0x009U, 8U, 0x0000000FU) +#define OTP_DRC_1_DIS OTP_GET_FUSE_STATE(0x009U, 12U, 0x0000000FU) +#define OTP_CAN_DIS OTP_GET_FUSE_STATE(0x00AU, 0U, 0x00000001U) +#define OTP_FIPS_MODE OTP_GET_FUSE_STATE(0x00AU, 3U, 0x00000001U) +#define OTP_FIPS_MODE_DIS OTP_GET_FUSE_STATE(0x00AU, 4U, 0x00000001U) + +///////////////////////////////////////////////////////////////////////////// +#define OTP_ADM_SECURITY_MSKL OTP_GET_FUSE_STATE(0x00CU, 0U, 0x0000FFFFU) +#define OTP_ADM_SECURITY_MSKU OTP_GET_FUSE_STATE(0x00DU, 0U, 0x0000FFFFU) + +#define OTP_FUSES_VALID OTP_GET_FUSE_STATE(0x00EU, 0U, 0x00000007U) + +#define OTP_ROM_CONTROL OTP_GET_FUSE_STATE(0x00EU, 8U, 0x000000FFU) + +#define OTP_READ_LOCKS OTP_GET_FUSE_STATE(0x00FU, 0U, 0x000080FFU) + +#define OTP_UNIQUE_ID_L OTP_GET_FUSE_STATE(0x010U, 0U, 0xFFFFFFFFU) +#define OTP_UNIQUE_ID_H OTP_GET_FUSE_STATE(0x011U, 0U, 0xFFFFFFFFU) + +#define OTP_LOT_NUM_ENCL OTP_GET_FUSE_STATE(0x010U, 0U, 0xFFFFFFFFU) +#define OTP_LOT_NUM_ENCU OTP_GET_FUSE_STATE(0x011U, 0U, 0xFFFFFFFFU) + +#define OTP_BOOT_MODE_FUSES OTP_GET_FUSE_STATE(0x012U, 0U, 0xFFFFFFFFU) +#define OTP_USDHC_OPTIONS OTP_GET_FUSE_STATE(0x013U, 0U, 0xFFFFFFFFU) +///////////////////////////////////////////////////////////////redo + +#define OTP_PROG_FUSE_VERSION_AP_1_OPP OTP_GET_FUSE_STATE(0x01bU, 0U, 0x00000001U) +#define OTP_PROG_FUSE_VERSION_SQRUP OTP_GET_FUSE_STATE(0x01bU, 1U, 0x00000001U) +#define OTP_PROG_FUSE_VERSION_1_7V_CAL OTP_GET_FUSE_STATE(0x01bU, 2U, 0x00000001U) +#define OTP_DPLL_CALIB_V2 OTP_GET_FUSE_STATE(0x01bU, 3U, 0x00000001U) +#define OTP_PROG_FUSE_TRIM_LDO OTP_GET_FUSE_STATE(0x01bU, 4U, 0x00000001U) +#define OTP_PROG_FUSE_GPU_NM_625 OTP_GET_FUSE_STATE(0x01bU, 7U, 0x00000001U) + +#define OTP_OSC_CAP_TRM_32K OTP_GET_FUSE_STATE(0x01eU, 0U, 0x0000000FU) +#define OTP_TMP_MON_TRM_LO OTP_GET_FUSE_STATE(0x01eU, 4U, 0x0000003FU) +#define OTP_TMP_MON_TRM_HI OTP_GET_FUSE_STATE(0x01eU, 10U, 0x0000003FU) +#define OTP_TMP_MON_TRM_RES OTP_GET_FUSE_STATE(0x01eU, 16U, 0x0000000FU) +#define OTP_TMP_MON_TRM_SHLF_LO OTP_GET_FUSE_STATE(0x01eU, 20U, 0x0000003FU) +#define OTP_TMP_MON_TRM_SHLF_HI OTP_GET_FUSE_STATE(0x01eU, 26U, 0x0000003FU) +#define OTP_SNVS_BNDGAP_TRM OTP_GET_FUSE_STATE(0x01fU, 0U, 0x0000001FU) +#define OTP_32K_IRC_TRM OTP_GET_FUSE_STATE(0x01fU, 5U, 0x0000001FU) +#define OTP_CLK_MON_TRM_LO OTP_GET_FUSE_STATE(0x01fU, 10U, 0x0000000FU) +#define OTP_CLK_MON_TRM_HI OTP_GET_FUSE_STATE(0x01fU, 14U, 0x0000000FU) +#define OTP_V_MON_TRM_LO OTP_GET_FUSE_STATE(0x01fU, 18U, 0x0000000FU) +#define OTP_V_MON_TRM_HI OTP_GET_FUSE_STATE(0x01fU, 22U, 0x0000000FU) +#define OTP_V_MON_TAMP_DIS OTP_GET_FUSE_STATE(0x01fU, 26U, 0x00000001U) +#define OTP_CLK_MON_DIS OTP_GET_FUSE_STATE(0x01fU, 27U, 0x00000001U) +#define OTP_TMP_MON_DIS OTP_GET_FUSE_STATE(0x01fU, 28U, 0x00000001U) +#define OTP_SNVS_CORE_V_TRM OTP_GET_FUSE_STATE(0x01fU, 30U, 0x00000002U) + +#define OTP_REFGEN_SCU OTP_GET_FUSE_STATE(0x064U, 0U, 0x000000FFU) +#define OTP_REFGEN_AP_0 OTP_GET_FUSE_STATE(0x064U, 8U, 0x000000FFU) +#define OTP_REFGEN_AP_1 OTP_GET_FUSE_STATE(0x064U, 16U, 0x000000FFU) +#define OTP_REFGEN_DRC0 OTP_GET_FUSE_STATE(0x064U, 24U, 0x000000FFU) +#define OTP_REFGEN_DRC1 OTP_GET_FUSE_STATE(0x065U, 0U, 0x000000FFU) +#define OTP_REFGEN_GPU0 OTP_GET_FUSE_STATE(0x065U, 8U, 0x000000FFU) +#define OTP_REFGEN_GPU1 OTP_GET_FUSE_STATE(0x065U, 16U, 0x000000FFU) +#define OTP_REFGEN_DMA OTP_GET_FUSE_STATE(0x065U, 24U, 0x000000FFU) +#define OTP_REFGEN_DI_CNCT OTP_GET_FUSE_STATE(0x066U, 0U, 0x000000FFU) +#define OTP_REFGEN_DI_HDMI OTP_GET_FUSE_STATE(0x066U, 8U, 0x000000FFU) +#define OTP_REFGEN_RX_HDMI OTP_GET_FUSE_STATE(0x066U, 16U, 0x000000FFU) +#define OTP_REFGEN_HSIO OTP_GET_FUSE_STATE(0x066U, 24U, 0x000000FFU) +#define OTP_REFGEN_VPU OTP_GET_FUSE_STATE(0x069U, 0U, 0x000000FFU) + +#define OTP_USB_PHY_TRM OTP_GET_FUSE_STATE(0x067U, 0U, 0x000FFFFFU) +#define OTP_DSI0_TRM OTP_GET_FUSE_STATE(0x067U, 20U, 0x00000003U) +#define OTP_DSI1_TRM OTP_GET_FUSE_STATE(0x067U, 22U, 0x00000003U) +#define OTP_CHARGE_PUMP OTP_GET_FUSE_STATE(0x067U, 27U, 0x0000001FU) +#define OTP_WLEVEL_BIAS_AP_0 OTP_GET_FUSE_STATE(0x068U, 0U, 0x000000FFU) +#define OTP_WLEVEL_BIAS_AP_1 OTP_GET_FUSE_STATE(0x068U, 8U, 0x000000FFU) +#define OTP_WLEVEL_BIAS_GPU0 OTP_GET_FUSE_STATE(0x068U, 16U, 0x000000FFU) +#define OTP_WLEVEL_BIAS_GPU1 OTP_GET_FUSE_STATE(0x068U, 24U, 0x000000FFU) +#define OTP_CSI0_TRM OTP_GET_FUSE_STATE(0x069U, 8U, 0x00000003U) +#define OTP_CSI1_TRM OTP_GET_FUSE_STATE(0x069U, 10U, 0x00000003U) +#define OTP_TMP_SENS_SCU OTP_GET_FUSE_STATE(0x069U, 12U, 0x000003FFU) +#define OTP_TMP_SENS_AP_0 OTP_GET_FUSE_STATE(0x069U, 22U, 0x000003FFU) +#define OTP_TMP_SENS_AP_1 OTP_GET_FUSE_STATE(0x06aU, 2U, 0x000003FFU) +#define OTP_TMP_SENS_GPU0 OTP_GET_FUSE_STATE(0x06aU, 12U, 0x000003FFU) +#define OTP_TMP_SENS_GPU1 OTP_GET_FUSE_STATE(0x06aU, 22U, 0x000003FFU) +#define OTP_TMP_SENS_DRC0 OTP_GET_FUSE_STATE(0x06bU, 2U, 0x000003FFU) +#define OTP_TMP_SENS_DRC1 OTP_GET_FUSE_STATE(0x06bU, 12U, 0x000003FFU) +#define OTP_TMP_SENS_VPU OTP_GET_FUSE_STATE(0x06bU, 22U, 0x000003FFU) + +#define OTP_BIAS_AP_0_OD_COLD OTP_GET_FUSE_STATE(0x06CU, 0U, 0x000000FFU) +#define OTP_BIAS_AP_1_OD_COLD OTP_GET_FUSE_STATE(0x06CU, 8U, 0x000000FFU) +#define OTP_BIAS_GPX0_OD_COLD OTP_GET_FUSE_STATE(0x06CU, 16U, 0x000000FFU) +#define OTP_BIAS_GPX1_OD_COLD OTP_GET_FUSE_STATE(0x06CU, 24U, 0x000000FFU) +#define OTP_BIAS_GPX0_NM_COLD OTP_GET_FUSE_STATE(0x06DU, 16U, 0x000000FFU) +#define OTP_BIAS_GPX1_NM_COLD OTP_GET_FUSE_STATE(0x06DU, 24U, 0x000000FFU) + +#define OTP_BIAS_AP_0_OD_HOT OTP_GET_FUSE_STATE(0x06EU, 0U, 0x000000FFU) +#define OTP_BIAS_AP_1_OD_HOT OTP_GET_FUSE_STATE(0x06EU, 8U, 0x000000FFU) +#define OTP_BIAS_GPX0_OD_HOT OTP_GET_FUSE_STATE(0x06EU, 16U, 0x000000FFU) +#define OTP_BIAS_GPX1_OD_HOT OTP_GET_FUSE_STATE(0x06EU, 24U, 0x000000FFU) +#define OTP_BIAS_GPX0_NM_HOT OTP_GET_FUSE_STATE(0x06FU, 16U, 0x000000FFU) +#define OTP_BIAS_GPX1_NM_HOT OTP_GET_FUSE_STATE(0x06FU, 24U, 0x000000FFU) + +#define OTP_ROM_PATCH 0x070U +#define OTP_ROM_PATCH_SIZE 62U +#define OTP_V2X_PATCH_SIZE 0U + +#define OTP_SINGLE_END_CLK OTP_GET_FUSE_STATE(0x0AEU, 4U, 0x00000001U) + +#define OTP_24MHZ_REGH_LV OTP_GET_FUSE_STATE(0x100U, 0U, 0x00000007U) +#define OTP_24MHZ_REGL_LV OTP_GET_FUSE_STATE(0x100U, 3U, 0x00000007U) +#define OTP_ROSC_FREQ_OFF OTP_GET_FUSE_STATE(0x100U, 8U, 0x00FFFFFFU) + +#define OTP_DPLL_TRM OTP_GET_FUSE_STATE(0x101U, 0U, 0xFFFFFFFFU) +#define OTP_DPLL_TRM_VALID OTP_GET_FUSE_STATE(0x101U, 0U, 0x00800000U) +#define OTP_t_SNVS_BNDGAP_TRM OTP_GET_FUSE_STATE(0x104U, 8U, 0x0000001FU) +#define OTP_t_32K_INT_TRM OTP_GET_FUSE_STATE(0x104U, 13U, 0x0000001FU) +#define OTP_t_TMP_SENS_SCU_0 OTP_GET_FUSE_STATE(0x104U, 20U, 0x000003FFU) +#define OTP_t_TMP_SENS_AP_0_1 OTP_GET_FUSE_STATE(0x105U, 6U, 0x000003FFU) +#define OTP_t_CHARGE_PUMP OTP_GET_FUSE_STATE(0x105U, 27U, 0x0000001FU) +#define OTP_t_OSC_CAP_TRIM_32K OTP_GET_FUSE_STATE(0x106U, 0U, 0x0000000FU) +#define OTP_t_TMP_MON_TRM_LO OTP_GET_FUSE_STATE(0x106U, 4U, 0x0000003FU) +#define OTP_t_TMP_MON_TRM_HI OTP_GET_FUSE_STATE(0x106U, 10U, 0x0000003FU) +#define OTP_t_TMP_MON_TRM_RES OTP_GET_FUSE_STATE(0x106U, 16U, 0x0000000FU) +#define OTP_t_TMP_MON_SHLF_LO OTP_GET_FUSE_STATE(0x106U, 20U, 0x0000003FU) +#define OTP_t_TMP_MON_SHLF_HI OTP_GET_FUSE_STATE(0x106U, 26U, 0x0000003FU) +#define OTP_t_CLK_MON_TRM_LO OTP_GET_FUSE_STATE(0x107U, 10U, 0x0000000FU) +#define OTP_t_CLK_MON_TRM_HI OTP_GET_FUSE_STATE(0x107U, 14U, 0x0000000FU) +#define OTP_t_V_MON_TRM_LO OTP_GET_FUSE_STATE(0x107U, 18U, 0x0000000FU) +#define OTP_t_V_MON_TRM_HI OTP_GET_FUSE_STATE(0x107U, 22U, 0x0000000FU) +#define OTP_t_SNVS_CORE_V_TRM OTP_GET_FUSE_STATE(0x107U, 30U, 0x0000000CU) + +#define OTP_24MHZ_DIFF_VALID OTP_GET_FUSE_STATE(0x102U, 31U, 0x00000001U) +#define OTP_24MHZ_DIFF_DRV0 OTP_GET_FUSE_STATE(0x102U, 0U, 0x00000003U) +#define OTP_24MHZ_DIFF_DRV1 OTP_GET_FUSE_STATE(0x102U, 4U, 0x00000003U) +#define OTP_24MHZ_DIFF_TERM_RES OTP_GET_FUSE_STATE(0x102U, 8U, 0x00000003U) +#define OTP_24MHZ_DIFF_DRV_IN OTP_GET_FUSE_STATE(0x102U, 10U, 0x00000003U) +#define OTP_24MHZ_DIFF_SQRUP OTP_GET_FUSE_STATE(0x102U, 12U, 0x00000003U) +#define OTP_SCU_REG_TRIM OTP_GET_FUSE_STATE(0x102U, 16U, 0x00000007U) +#define OTP_VPU_REG0_TRIM OTP_GET_FUSE_STATE(0x102U, 19U, 0x00000007U) +#define OTP_VPU_REG1_TRIM OTP_GET_FUSE_STATE(0x102U, 22U, 0x00000007U) + +#define OTP_CSI_0_RCAL_TRIM OTP_GET_FUSE_STATE(0x069U, 8U, 0x00000003U) +#define OTP_CSI_1_RCAL_TRIM OTP_GET_FUSE_STATE(0x069U, 10U, 0x00000003U) +#define OTP_DSI_0_RCAL_TRIM OTP_GET_FUSE_STATE(0x067U, 20U, 0x00000003U) +#define OTP_DSI_1_RCAL_TRIM OTP_GET_FUSE_STATE(0x067U, 22U, 0x00000003U) + +#define OTP_DSI_0_VOH_CLK_TRIM OTP_GET_FUSE_STATE(0x103U, 0U, 0x00000007U) +#define OTP_DSI_0_VOH_D3_TRIM OTP_GET_FUSE_STATE(0x103U, 3U, 0x00000007U) +#define OTP_DSI_0_VOH_D2_TRIM OTP_GET_FUSE_STATE(0x103U, 6U, 0x00000007U) +#define OTP_DSI_0_VOH_D1_TRIM OTP_GET_FUSE_STATE(0x103U, 9U, 0x00000007U) +#define OTP_DSI_0_VOH_D0_TRIM OTP_GET_FUSE_STATE(0x103U, 12U, 0x00000007U) +#define OTP_DSI_1_VOH_CLK_TRIM OTP_GET_FUSE_STATE(0x103U, 16U, 0x00000007U) +#define OTP_DSI_1_VOH_D3_TRIM OTP_GET_FUSE_STATE(0x103U, 19U, 0x00000007U) +#define OTP_DSI_1_VOH_D2_TRIM OTP_GET_FUSE_STATE(0x103U, 22U, 0x00000007U) +#define OTP_DSI_1_VOH_D1_TRIM OTP_GET_FUSE_STATE(0x103U, 25U, 0x00000007U) +#define OTP_DSI_1_VOH_D0_TRIM OTP_GET_FUSE_STATE(0x103U, 28U, 0x00000007U) + +#define OTP_24MHZ_CL_TUNE_LV OTP_GET_FUSE_STATE(0x1F0U, 0U, 0x000000FFU) +#define OTP_24MHZ_CL_TUNE_VALID OTP_GET_FUSE_STATE(0x1F0U, 31U, 0x00000001U) + +#define OTP_TMP_SENS_SCU_OFS OTP_GET_FUSE_STATE(0x301U, 0U, 0x000000FFU) +#define OTP_TMP_SENS_AP_0_OFS OTP_GET_FUSE_STATE(0x301U, 8U, 0x000000FFU) +#define OTP_TMP_SENS_AP_1_OFS OTP_GET_FUSE_STATE(0x301U, 16U, 0x000000FFU) +#define OTP_TMP_SENS_GPU0_OFS OTP_GET_FUSE_STATE(0x301U, 24U, 0x000000FFU) +#define OTP_TMP_SENS_GPU1_OFS OTP_GET_FUSE_STATE(0x302U, 0U, 0x000000FFU) +#define OTP_TMP_SENS_DRC0_OFS OTP_GET_FUSE_STATE(0x302U, 8U, 0x000000FFU) +#define OTP_TMP_SENS_DRC1_OFS OTP_GET_FUSE_STATE(0x302U, 16U, 0x000000FFU) +#define OTP_TMP_SENS_VPU_OFS OTP_GET_FUSE_STATE(0x302U, 24U, 0x000000FFU) + +#define OTP_DPLL_TABLE_SELECT_VALID OTP_GET_FUSE_STATE(0x31DU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_SELECT_BITS OTP_GET_FUSE_STATE(0x31DU, 0U, 0x003FFFFFU) + +#define OTP_DPLL_TABLE_0_VALID OTP_GET_FUSE_STATE(0x31EU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_0_V6 OTP_GET_FUSE_STATE(0x31EU, 26U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V5 OTP_GET_FUSE_STATE(0x31EU, 21U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V4 OTP_GET_FUSE_STATE(0x31EU, 16U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V3 OTP_GET_FUSE_STATE(0x31EU, 11U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V2 OTP_GET_FUSE_STATE(0x31EU, 6U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V1 OTP_GET_FUSE_STATE(0x31EU, 0U, 0x0000003FU) + +#define OTP_DPLL_TABLE_1_VALID OTP_GET_FUSE_STATE(0x31FU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_1_V6 OTP_GET_FUSE_STATE(0x31FU, 26U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V5 OTP_GET_FUSE_STATE(0x31FU, 21U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V4 OTP_GET_FUSE_STATE(0x31FU, 16U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V3 OTP_GET_FUSE_STATE(0x31FU, 11U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V2 OTP_GET_FUSE_STATE(0x31FU, 6U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V1 OTP_GET_FUSE_STATE(0x31FU, 0U, 0x0000003FU) + +#endif /* HW_FUSES_H */ + diff --git a/platform/devices/MX8QM/MX8QM_otp.h b/platform/devices/MX8QM/MX8QM_otp.h new file mode 100755 index 0000000..e6c7398 --- /dev/null +++ b/platform/devices/MX8QM/MX8QM_otp.h @@ -0,0 +1,317 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_OTP_REGISTERS_H +#define HW_OTP_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- OTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTP_Peripheral_Access_Layer OTP Peripheral Access Layer + * @{ + */ + +/** OTP - Register Layout Typedef */ +typedef struct +{ + __IO uint32_t RW; + __IO uint32_t SET; + __IO uint32_t CLR; + __IO uint32_t TOG; +} OTP_Reg; + +typedef struct +{ + OTP_Reg CTRL; + OTP_Reg PDN; + OTP_Reg DATA; + OTP_Reg READ_CTRL; + OTP_Reg READ_FUSE_DATA; + OTP_Reg SW_STICKY; + OTP_Reg SCS; + OTP_Reg CRC_ADDR; + OTP_Reg CRC_VALUE; + OTP_Reg STATUS[2]; + uint8_t RESERVED_0[32]; + __I uint32_t VERSION; + uint8_t RESERVED_1[1324]; + struct { + __I uint32_t RW; + __I uint32_t SET; + __I uint32_t CLR; + __I uint32_t TOG; + } LOCKED[26]; + uint8_t RESERVED_3[96]; + OTP_Reg FUSE[800]; +} OTP_Type; + +/* ---------------------------------------------------------------------------- + -- OTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTP_Register_Masks OTP Register Masks + * @{ + */ + +/*! @name OTP Register */ +#define OTP_BIT0_MASK (0x00000001U) +#define OTP_BIT0_SHIFT (0U) +#define OTP_BIT0(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT1_MASK (0x00000002U) +#define OTP_BIT1_SHIFT (1U) +#define OTP_BIT1(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT2_MASK (0x00000004U) +#define OTP_BIT2_SHIFT (2U) +#define OTP_BIT2(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT3_MASK (0x00000008U) +#define OTP_BIT3_SHIFT (3U) +#define OTP_BIT3(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT4_MASK (0x00000010U) +#define OTP_BIT4_SHIFT (4U) +#define OTP_BIT4(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT5_MASK (0x00000020U) +#define OTP_BIT5_SHIFT (5U) +#define OTP_BIT5(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT6_MASK (0x00000040U) +#define OTP_BIT6_SHIFT (6U) +#define OTP_BIT6(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT7_MASK (0x00000080U) +#define OTP_BIT7_SHIFT (7U) +#define OTP_BIT7(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT8_MASK (0x00000100U) +#define OTP_BIT8_SHIFT (8U) +#define OTP_BIT8(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT9_MASK (0x00000200U) +#define OTP_BIT9_SHIFT (9U) +#define OTP_BIT9(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT10_MASK (0x00000400U) +#define OTP_BIT10_SHIFT (10U) +#define OTP_BIT10(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT11_MASK (0x00000800U) +#define OTP_BIT11_SHIFT (11U) +#define OTP_BIT11(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT12_MASK (0x00001000U) +#define OTP_BIT12_SHIFT (12U) +#define OTP_BIT12(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT13_MASK (0x00002000U) +#define OTP_BIT13_SHIFT (13U) +#define OTP_BIT13(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT14_MASK (0x00004000U) +#define OTP_BIT14_SHIFT (14U) +#define OTP_BIT14(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT15_MASK (0x00008000U) +#define OTP_BIT15_SHIFT (15U) +#define OTP_BIT15(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT16_MASK (0x00010000U) +#define OTP_BIT16_SHIFT (16U) +#define OTP_BIT16(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT17_MASK (0x00020000U) +#define OTP_BIT17_SHIFT (17U) +#define OTP_BIT17(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT18_MASK (0x00040000U) +#define OTP_BIT18_SHIFT (18U) +#define OTP_BIT18(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT19_MASK (0x00080000U) +#define OTP_BIT19_SHIFT (19U) +#define OTP_BIT19(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT20_MASK (0x00100000U) +#define OTP_BIT20_SHIFT (20U) +#define OTP_BIT20(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT21_ASK (0x00200000U) +#define OTP_BIT21_SHIFT (21U) +#define OTP_BIT21(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT22_MASK (0x00400000U) +#define OTP_BIT22_SHIFT (22U) +#define OTP_BIT22(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT23_MASK (0x00800000U) +#define OTP_BIT23_SHIFT (23U) +#define OTP_BIT23(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT24_MASK (0x01000000U) +#define OTP_BIT24_SHIFT (24U) +#define OTP_BIT24(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT25_MASK (0x02000000U) +#define OTP_BIT25_SHIFT (25U) +#define OTP_BIT25(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT26_MASK (0x04000000U) +#define OTP_BIT26_SHIFT (26U) +#define OTP_BIT26(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT27_MASK (0x08000000U) +#define OTP_BIT27_SHIFT (27U) +#define OTP_BIT27(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT28_MASK (0x10000000U) +#define OTP_BIT28_SHIFT (28U) +#define OTP_BIT28(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT29_MASK (0x20000000U) +#define OTP_BIT29_SHIFT (29U) +#define OTP_BIT29(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT30_MASK (0x40000000U) +#define OTP_BIT30_SHIFT (30U) +#define OTP_BIT30(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT31_MASK (0x80000000U) +#define OTP_BIT31_SHIFT (31U) +#define OTP_BIT31(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE0_MASK (0x0000000FU) +#define OTP_NIBBLE0_SHIFT (0U) +#define OTP_NIBBLE0(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE1_MASK (0x000000F0U) +#define OTP_NIBBLE1_SHIFT (4U) +#define OTP_NIBBLE1(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE2_MASK (0x00000F00U) +#define OTP_NIBBLE2_SHIFT (8U) +#define OTP_NIBBLE2(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE3_MASK (0x0000F000U) +#define OTP_NIBBLE3_SHIFT (12U) +#define OTP_NIBBLE3(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE4_MASK (0x000F0000U) +#define OTP_NIBBLE4_SHIFT (16U) +#define OTP_NIBBLE4(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE5_MASK (0x00F00000U) +#define OTP_NIBBLE5_SHIFT (20U) +#define OTP_NIBBLE5(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE6_MASK (0x0F000000U) +#define OTP_NIBBLE6_SHIFT (24U) +#define OTP_NIBBLE6(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE7_MASK (0xF0000000U) +#define OTP_NIBBLE7_SHIFT (28U) +#define OTP_NIBBLE7(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! + * @} + */ /* end of group OTP_Register_Masks */ + +/* OTP - Peripheral instance base addresses */ +/** Peripheral OTPA base pointer */ +#define OTP ((OTP_Type *)OTP_BASE) +/** Array initializer of OTP peripheral base addresses */ +#define OTP_BASE_ADDRS { OTP_BASE } +/** Array initializer of OTP peripheral base pointers */ +#define OTP_BASE_PTRS { OTP } + +/*! + * @} + */ /* end of group OTP_Peripheral_Access_Layer */ + +#endif /* HW_OTP_REGISTERS_H */ diff --git a/platform/devices/MX8QM/Makefile b/platform/devices/MX8QM/Makefile new file mode 100755 index 0000000..6391816 --- /dev/null +++ b/platform/devices/MX8QM/Makefile @@ -0,0 +1,14 @@ + +objs_mx8 := system_MX8QM.o handlers_MX8QM.o + +ifdef ROM +objs_mx8 += gcc/startup_rom_MX8QM.o +else +objs_mx8 += gcc/startup_MX8QM.o +endif + +OBJS += \ + $(foreach object,$(objs_mx8),$(OUT)/devices/MX8QM/$(object)) + +DIRS += $(OUT)/devices/MX8QM/gcc + diff --git a/platform/devices/MX8QM/fsl_clock.h b/platform/devices/MX8QM/fsl_clock.h new file mode 100755 index 0000000..ac7c7db --- /dev/null +++ b/platform/devices/MX8QM/fsl_clock.h @@ -0,0 +1,372 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef HW_CLOCKS_H +#define HW_CLOCKS_H + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define SC_XTAL32K_FREQ_HZ 32768U +#define SC_XTAL24M_FREQ_HZ 24000000U +#define SC_ROSC_FREQ_HZ 200000000U +#define SC_PLL0_STARTUP_FREQ_HZ 1056000000U + +#define SC_MSLICE_ROOT0_RESET_DIV 1U // 200 MHz / 1 = 200 MHz (CM4, BUS) +#define SC_MSLICE_ROOT1_RESET_DIV 2U // 200 MHz / 2 = 100 MHz (SECO, IPG) +#define SC_MSLICE_ROOT2_RESET_DIV 2U // 200 MHz / 2 = 100 MHz (CAAM) +#define SC_MSLICE_ROOT3_RESET_DIV 1U // 200 MHz / 1 = 200 MHz (MSI) + +#define SC_MSLICE_ROOT0_STARTUP_DIV 4U // 1056 MHz / 4 = 264 MHz (CM4, BUS) +#define SC_MSLICE_ROOT1_STARTUP_DIV 8U // 1056 MHz / 8 = 132 MHz (SECO, IPG) +#define SC_MSLICE_ROOT2_STARTUP_DIV 3U // 1056 MHz / 3 = 352 MHz (CAAM) +#define SC_MSLICE_ROOT3_STARTUP_DIV 5U // 1056 MHz / 5 = 211 MHz (MSI) + +#define SC_MCU_STARTUP_FREQ_HZ (SC_PLL0_STARTUP_FREQ_HZ/SC_MSLICE_ROOT0_STARTUP_DIV) +#define SC_MCU_STARTUP_FREQ_MHZ (SC_MCU_STARTUP_FREQ_HZ/1000000U) +#define SC_MCU_LPM_FREQ_HZ (SC_ROSC_FREQ_HZ/SC_MSLICE_ROOT0_STARTUP_DIV) +#define SC_MCU_LPM_FREQ_MHZ (SC_MCU_LPM_FREQ_HZ/1000000U) +#define SC_SYSTICK_NSEC_TO_TICKS(nsec) ((SC_MCU_STARTUP_FREQ_MHZ * (nsec)) / 1000U) + +#define SC_LPIT_ROOT_FREQ_HZ 24000000U +#define SC_LPIT_ROOT_DIV 3U +#define SC_LPIT_FREQ_HZ (SC_LPIT_ROOT_FREQ_HZ / SC_LPIT_ROOT_DIV) +#define SC_LPIT_MSEC_TO_TICKS(msec) (SC_LPIT_FREQ_HZ * (msec) / 1000U) + +#define SC_BG_SVC_MSEC 10U // Background service interval in msec +#define SC_WDOG_SVC_MSEC 5U // WDOG service interval in msec +#define SC_BG_TIMEOUT_MSEC 100U // Background timeout in msec +#define SC_BG_TIMEOUT (SC_BG_TIMEOUT_MSEC / SC_WDOG_SVC_MSEC) + +/*! @brief Clock ip name array for LPUART. */ + +/* Note: This array should have FSL_FEATURE_SOC_LPUART_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define LPUART_CLOCKS {kCLOCK_LPUART_SC, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/*! @brief Clock ip name array for LPI2C. */ + +/* Note: This array should have FSL_FEATURE_SOC_LPI2C_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define LPI2C_CLOCKS {kCLOCK_LPI2C_SC, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/* Note: This array should have FSL_FEATURE_SOC_IGPIO_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define GPIO_CLOCKS {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/* Note: This array should have FSL_FEATURE_SOC_MU_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define MU_CLOCKS {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid} + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_NmInvalid = 0U, +} clock_name_t; + +/*! + * @brief Clock source for peripherals that support various clock selections. + */ +typedef enum _clock_ip_src +{ + kCLOCK_SrcInvalid = 0U, +} clock_ip_src_t; + +/*! + * @brief Peripheral clock name difinition used for clock gate, clock source + * and clock divider setting. It is defined as the corresponding register address. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_TCMC_SC = LPCG__SS_SCU__CM4__TCMC_HCLK__BASE, + kCLOCK_MMCAU_SC = LPCG__SS_SCU__CM4__MMCAU_HCLK__BASE, + kCLOCK_TPM_SC = LPCG__SS_SCU__TPM1__IPG_CLK__BASE, + kCLOCK_LPIT_SC = LPCG__SS_SCU__LPIT1__IPG_CLK__BASE, + kCLOCK_LPUART_SC = LPCG__SS_SCU__LPUART1__IPG_CLK__BASE, + kCLOCK_LPI2C_SC = LPCG__SS_SCU__LPI2C1__IPG_CLK__BASE +} clock_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Enable IPG and BAUD clocks */ + volatile uint32_t lpcgVal = (1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN); + + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + + /* Wait for clocks to start */ + uint32_t stopMask = (1UL << LPCG__SS_SCU__IPG_CLK__STOP) | + (1UL << LPCG__SS_SCU__PER_CLK__STOP); + + while ((*((volatile uint32_t *) (uint32_t) name) & stopMask) != 0U) + { + ; /* Intentional empty while */ + } + + /* Perform extra write as workaround for TKT322331 */ + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + } +#endif +} + +/*! + * @brief Enable the hardware clock gating for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableHWCG(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Enable IPG and BAUD clocks */ + uint32_t lpcgVal = (1UL << LPCG__SS_SCU__PER_CLK__HWEN); + + *((volatile uint32_t *) (uint32_t) name) |= lpcgVal; + } +#endif +} + +/*! + * @brief Enable the clock for specific IP using exclusive access. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClockEx(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Use exclusive access to enable IPG and BAUD clocks */ + uint32_t volatile lpcgVal = (1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN); + + do + { + lpcgVal |= __LDREXW((volatile uint32_t *) (uint32_t) name); + } while (__STREXW(lpcgVal, ((volatile uint32_t *) (uint32_t) name)) != 0U); + + /* Wait for clocks to start */ + uint32_t stopMask = (1UL << LPCG__SS_SCU__IPG_CLK__STOP) | + (1UL << LPCG__SS_SCU__PER_CLK__STOP); + + while ((*((volatile uint32_t *) (uint32_t) name) & stopMask) != 0U) + { + ; /* Intentional empty while */ + } + + /* Perform extra write as workaround for TKT322331 */ + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + + } +#endif +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Disable IPG and BAUD clocks */ + uint32_t lpcgVal = 0U; + + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + } +#endif +} + +/*! + * @brief Enter exclusive attempt to disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline uint32_t CLOCK_DisableClockExEnter(clock_ip_name_t name) +{ +#ifndef SIMU + /* Use exclusive access to disable IPG and BAUD clocks */ + uint32_t lpcgVal = ~((1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN)); + + if (name != kCLOCK_IpInvalid) + { + lpcgVal = __LDREXW((volatile uint32_t *) (uint32_t) name); + } + + return lpcgVal; +#else + return 0U; +#endif +} + +/*! + * @brief Leave exclusive attempt to disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClockExLeave(clock_ip_name_t name, + uint32_t lpcgVal) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + (void)__STREXW(lpcgVal, ((volatile uint32_t *) (uint32_t) name)); + } +#endif +} + +/*! + * @brief Check whether the clock is already enabled and configured by + * any other core. + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @return True if clock is already enabled, otherwise false. + */ +static inline bool CLOCK_IsEnabledByOtherCore(clock_ip_name_t name) +{ + return false; +} + +/*! + * @brief Set the clock source for specific IP module. + * + * Set the clock source for specific IP, not all modules need to set the + * clock source, should only use this function for the modules need source + * setting. + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @param src Clock source to set. + */ +static inline void CLOCK_SetIpSrc(clock_ip_name_t name, clock_ip_src_t src) +{ +} + +/*! + * @brief Set the clock source and divider for specific IP module. + * + * Set the clock source and divider for specific IP, not all modules need to + * set the clock source and divider, should only use this function for the + * modules need source and divider setting. + * + * Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]). + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @param src Clock source to set. + * @param divValue The divider value. + * @param fracValue The fraction multiply value. + */ +static inline void CLOCK_SetIpSrcDiv(clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue) +{ +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Gets the clock frequency for a specific IP module. + * + * This function gets the IP module clock frequency based on PCC registers. It is + * only used for the IP modules which could select clock source by PCC[PCS]. + * + * @param name Which peripheral to get, see \ref clock_ip_name_t. + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetIpFreq(clock_ip_name_t name); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* HW_CLOCKS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8QM/handlers_MX8QM.h b/platform/devices/MX8QM/handlers_MX8QM.h new file mode 100755 index 0000000..71d22b5 --- /dev/null +++ b/platform/devices/MX8QM/handlers_MX8QM.h @@ -0,0 +1,122 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * Header for handlers. + */ + +#ifndef HANDLERS_H +#define HANDLERS_H + +/* Includes */ + +/* Defines */ + +/* Types */ + +/* Functions */ + +void sc_handlers_init(void); +void DefaultISR(void); +void NMI_IRQHandler(uint32_t *sp); +void MCM_IRQHandler(uint32_t *sp); +void DebugWake_IRQHandler(void); +void SWI_IRQHandler(void); +void SWI_DQS2DQ_Handler(void); +void LPIT_SCU_IRQHandler(uint32_t *sp); +void DSC_SCU_IRQHandler(void); +void DSC_LSIO_IRQHandler(void); +void DSC_CM4_0_IRQHandler(void); +void DSC_CM4_1_IRQHandler(void); +void DSC_CA53_IRQHandler(void); +void DSC_CA72_IRQHandler(void); +void DSC_DRC_0_IRQHandler(void); +void DSC_DRC_1_IRQHandler(void); +void DSC_GPU_0_IRQHandler(void); +void DSC_GPU_1_IRQHandler(void); +void DSC_VPU_IRQHandler(void); +void DSC_DBLOG_IRQHandler(void); +void IOMUX_CommonHandler(uint8_t irq, uint8_t ring, uint8_t group); +void IOMUX0_IRQHandler(void); +void IOMUX1_IRQHandler(void); +void IOMUX2_IRQHandler(void); +void IOMUX3_IRQHandler(void); +void IOMUX4_IRQHandler(void); +void IOMUX5_IRQHandler(void); +void IOMUX6_IRQHandler(void); +void IOMUX7_IRQHandler(void); +void IOMUX8_IRQHandler(void); +void IOMUX9_IRQHandler(void); +void IOMUX10_IRQHandler(void); +void IOMUX11_IRQHandler(void); +void IOMUX12_IRQHandler(void); +void IOMUX13_IRQHandler(void); +void IOMUX14_IRQHandler(void); +void IOMUX15_IRQHandler(void); +void IOMUX16_IRQHandler(void); +void IOMUX17_IRQHandler(void); +void IOMUX18_IRQHandler(void); +void IOMUX19_IRQHandler(void); +void IOMUX20_IRQHandler(void); +void SYSCTR_CMP0_IRQHandler(void); +void SYSCTR_CMP1_IRQHandler(void); +void SNVS_Functional_IRQHandler(void); +void ss_earlywdog_handler_sc(void); +void ss_csreq_handler_a72(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_a53(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_mcu(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_dbgpwrup(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_hdmi_tx(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_hdmi_rx(uint32_t idx, uint32_t cpwrupreq); +#if HAS_SS_AP_0 +sc_bool_t ss_dbg_status_a53(sc_dsc_t dsc); +void ss_dbg_resume_a53(sc_dsc_t dsc); +#endif +#if HAS_SS_AP_1 +sc_bool_t ss_dbg_status_a72(sc_dsc_t dsc); +void ss_dbg_resume_a72(sc_dsc_t dsc); +#endif + +/* Global Variables */ + +extern uint32_t gLPITcnt; + +#endif /* #if !defined(HANDLERS_H) */ + diff --git a/platform/devices/MX8QM/linker/gcc/MX8QM_flash.ld b/platform/devices/MX8QM/linker/gcc/MX8QM_flash.ld new file mode 100755 index 0000000..ea63e74 --- /dev/null +++ b/platform/devices/MX8QM/linker/gcc/MX8QM_flash.ld @@ -0,0 +1,61 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Specify the memory areas */ +MEMORY +{ + m_rom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* Vector table and code to emulate ROM */ + .rom : + { + . = ALIGN(8); + KEEP(*(.rom)) + . = ALIGN(0x80); + } > m_rom +} + diff --git a/platform/devices/MX8QM/linker/gcc/MX8QM_overlay.ld b/platform/devices/MX8QM/linker/gcc/MX8QM_overlay.ld new file mode 100644 index 0000000..2b49196 --- /dev/null +++ b/platform/devices/MX8QM/linker/gcc/MX8QM_overlay.ld @@ -0,0 +1,391 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* DO NOT EDIT - This file auto generated by overlay_ld.pl */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +OCRAM_ADDR = 0x100000; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_ocram (RX) : ORIGIN = 0x00100000, LENGTH = 0x00040000 + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002ED80 + m_ovl (RX) : ORIGIN = 0x2000F000, LENGTH = 0x00000FF0 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + OVERLAY : NOCROSSREFS + { + .test0 { */test_dsc.o(.text*) */test_dsc.o(.rodata*) } + .test1 { */test_pll.o(.text*) */test_pll.o(.rodata*) } + .test2 { */test_snvs.o(.text*) */test_snvs.o(.rodata*) } + .test3 { */test_pmic.o(.text*) */test_pmic.o(.rodata*) } + .test4 { */test_dblogic.o(.text*) */test_dblogic.o(.rodata*) } + .test5 { */test_db.o(.text*) */test_db.o(.rodata*) } + .test6 { */test_drc.o(.text*) */test_drc.o(.rodata*) } + .test7 { */test_lsio.o(.text*) */test_lsio.o(.rodata*) } + .test8 { */test_dma.o(.text*) */test_dma.o(.rodata*) } + .test9 { */test_conn.o(.text*) */test_conn.o(.rodata*) } + .test10 { */test_cci.o(.text*) */test_cci.o(.rodata*) } + .test11 { */test_ap.o(.text*) */test_ap.o(.rodata*) } + .test12 { */test_audio.o(.text*) */test_audio.o(.rodata*) } + .test13 { */test_dc.o(.text*) */test_dc.o(.rodata*) } + .test14 { */test_mipi.o(.text*) */test_mipi.o(.rodata*) } + .test15 { */test_lvds.o(.text*) */test_lvds.o(.rodata*) } + .test16 { */test_dc_lvds.o(.text*) */test_dc_lvds.o(.rodata*) } + .test17 { */test_hdmi.o(.text*) */test_hdmi.o(.rodata*) } + .test18 { */test_img.o(.text*) */test_img.o(.rodata*) } + .test19 { */test_csi.o(.text*) */test_csi.o(.rodata*) } + .test20 { */test_hdmi_rx.o(.text*) */test_hdmi_rx.o(.rodata*) } + .test21 { */test_gpu.o(.text*) */test_gpu.o(.rodata*) } + .test22 { */test_vpu.o(.text*) */test_vpu.o(.rodata*) } + .test23 { */test_hsio.o(.text*) */test_hsio.o(.rodata*) } + .test24 { */test_mcu.o(.text*) */test_mcu.o(.rodata*) } + .test25 { */test_lcdif.o(.text*) */test_lcdif.o(.rodata*) } + .test26 { */test_isi.o(.text*) */test_isi.o(.rodata*) } + .test27 { */test_pd.o(.text*) */test_pd.o(.rodata*) } + .test28 { */test_pm.o(.text*) */test_pm.o(.rodata*) } + .test29 { */test_timer.o(.text*) */test_timer.o(.rodata*) } + .test30 { */test_rm.o(.text*) */test_rm.o(.rodata*) } + .test31 { */test_misc.o(.text*) */test_misc.o(.rodata*) } + .test32 { */test_pad.o(.text*) */test_pad.o(.rodata*) } + .test33 { */test_rm2.o(.text*) */test_rm2.o(.rodata*) } + .test34 { */test_seco.o(.text*) */test_seco.o(.rodata*) } + .test35 { */test_hexdump.o(.text*) */test_hexdump.o(.rodata*) } + .test36 { */test_ddr.o(.text*) */test_ddr.o(.rodata*) } + .test37 { */test_audio_pll.o(.text*) */test_audio_pll.o(.rodata*) } + .test38 { */test_temp.o(.text*) */test_temp.o(.rodata*) } + .test39 { */test_uboot.o(.text*) */test_uboot.o(.rodata*) } + .test40 { */test_xrdc.o(.text*) */test_xrdc.o(.rodata*) } + .test41 { */test_dump.o(.text*) */test_dump.o(.rodata*) } + .test42 { */test_rpc.o(.text*) */test_rpc.o(.rodata*) } + } > m_ovl AT> m_ocram + + .test_ovly_table : + { + . = ALIGN(4); + __ovly_table = .; + LONG(0x34982933); LONG(0); LONG(42); + LONG(ABSOLUTE(ADDR(.test0))); LONG(SIZEOF(.test0)); LONG(LOADADDR(.test0)); + LONG(ABSOLUTE(ADDR(.test1))); LONG(SIZEOF(.test1)); LONG(LOADADDR(.test1)); + LONG(ABSOLUTE(ADDR(.test2))); LONG(SIZEOF(.test2)); LONG(LOADADDR(.test2)); + LONG(ABSOLUTE(ADDR(.test3))); LONG(SIZEOF(.test3)); LONG(LOADADDR(.test3)); + LONG(ABSOLUTE(ADDR(.test4))); LONG(SIZEOF(.test4)); LONG(LOADADDR(.test4)); + LONG(ABSOLUTE(ADDR(.test5))); LONG(SIZEOF(.test5)); LONG(LOADADDR(.test5)); + LONG(ABSOLUTE(ADDR(.test6))); LONG(SIZEOF(.test6)); LONG(LOADADDR(.test6)); + LONG(ABSOLUTE(ADDR(.test7))); LONG(SIZEOF(.test7)); LONG(LOADADDR(.test7)); + LONG(ABSOLUTE(ADDR(.test8))); LONG(SIZEOF(.test8)); LONG(LOADADDR(.test8)); + LONG(ABSOLUTE(ADDR(.test9))); LONG(SIZEOF(.test9)); LONG(LOADADDR(.test9)); + LONG(ABSOLUTE(ADDR(.test10))); LONG(SIZEOF(.test10)); LONG(LOADADDR(.test10)); + LONG(ABSOLUTE(ADDR(.test11))); LONG(SIZEOF(.test11)); LONG(LOADADDR(.test11)); + LONG(ABSOLUTE(ADDR(.test12))); LONG(SIZEOF(.test12)); LONG(LOADADDR(.test12)); + LONG(ABSOLUTE(ADDR(.test13))); LONG(SIZEOF(.test13)); LONG(LOADADDR(.test13)); + LONG(ABSOLUTE(ADDR(.test14))); LONG(SIZEOF(.test14)); LONG(LOADADDR(.test14)); + LONG(ABSOLUTE(ADDR(.test15))); LONG(SIZEOF(.test15)); LONG(LOADADDR(.test15)); + LONG(ABSOLUTE(ADDR(.test16))); LONG(SIZEOF(.test16)); LONG(LOADADDR(.test16)); + LONG(ABSOLUTE(ADDR(.test17))); LONG(SIZEOF(.test17)); LONG(LOADADDR(.test17)); + LONG(ABSOLUTE(ADDR(.test18))); LONG(SIZEOF(.test18)); LONG(LOADADDR(.test18)); + LONG(ABSOLUTE(ADDR(.test19))); LONG(SIZEOF(.test19)); LONG(LOADADDR(.test19)); + LONG(ABSOLUTE(ADDR(.test20))); LONG(SIZEOF(.test20)); LONG(LOADADDR(.test20)); + LONG(ABSOLUTE(ADDR(.test21))); LONG(SIZEOF(.test21)); LONG(LOADADDR(.test21)); + LONG(ABSOLUTE(ADDR(.test22))); LONG(SIZEOF(.test22)); LONG(LOADADDR(.test22)); + LONG(ABSOLUTE(ADDR(.test23))); LONG(SIZEOF(.test23)); LONG(LOADADDR(.test23)); + LONG(ABSOLUTE(ADDR(.test24))); LONG(SIZEOF(.test24)); LONG(LOADADDR(.test24)); + LONG(ABSOLUTE(ADDR(.test25))); LONG(SIZEOF(.test25)); LONG(LOADADDR(.test25)); + LONG(ABSOLUTE(ADDR(.test26))); LONG(SIZEOF(.test26)); LONG(LOADADDR(.test26)); + LONG(ABSOLUTE(ADDR(.test27))); LONG(SIZEOF(.test27)); LONG(LOADADDR(.test27)); + LONG(ABSOLUTE(ADDR(.test28))); LONG(SIZEOF(.test28)); LONG(LOADADDR(.test28)); + LONG(ABSOLUTE(ADDR(.test29))); LONG(SIZEOF(.test29)); LONG(LOADADDR(.test29)); + LONG(ABSOLUTE(ADDR(.test30))); LONG(SIZEOF(.test30)); LONG(LOADADDR(.test30)); + LONG(ABSOLUTE(ADDR(.test31))); LONG(SIZEOF(.test31)); LONG(LOADADDR(.test31)); + LONG(ABSOLUTE(ADDR(.test32))); LONG(SIZEOF(.test32)); LONG(LOADADDR(.test32)); + LONG(ABSOLUTE(ADDR(.test33))); LONG(SIZEOF(.test33)); LONG(LOADADDR(.test33)); + LONG(ABSOLUTE(ADDR(.test34))); LONG(SIZEOF(.test34)); LONG(LOADADDR(.test34)); + LONG(ABSOLUTE(ADDR(.test35))); LONG(SIZEOF(.test35)); LONG(LOADADDR(.test35)); + LONG(ABSOLUTE(ADDR(.test36))); LONG(SIZEOF(.test36)); LONG(LOADADDR(.test36)); + LONG(ABSOLUTE(ADDR(.test37))); LONG(SIZEOF(.test37)); LONG(LOADADDR(.test37)); + LONG(ABSOLUTE(ADDR(.test38))); LONG(SIZEOF(.test38)); LONG(LOADADDR(.test38)); + LONG(ABSOLUTE(ADDR(.test39))); LONG(SIZEOF(.test39)); LONG(LOADADDR(.test39)); + LONG(ABSOLUTE(ADDR(.test40))); LONG(SIZEOF(.test40)); LONG(LOADADDR(.test40)); + LONG(ABSOLUTE(ADDR(.test41))); LONG(SIZEOF(.test41)); LONG(LOADADDR(.test41)); + LONG(ABSOLUTE(ADDR(.test42))); LONG(SIZEOF(.test42)); LONG(LOADADDR(.test42)); + LONG(0); LONG(0); LONG(0); + } > m_ocram + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8QM/linker/gcc/MX8QM_overlay.t.ld b/platform/devices/MX8QM/linker/gcc/MX8QM_overlay.t.ld new file mode 100755 index 0000000..61ec153 --- /dev/null +++ b/platform/devices/MX8QM/linker/gcc/MX8QM_overlay.t.ld @@ -0,0 +1,313 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* DO NOT EDIT - This file auto generated by $cmd */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +OCRAM_ADDR = 0x100000; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_ocram (RX) : ORIGIN = 0x00100000, LENGTH = 0x00040000 + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002ED80 + m_ovl (RX) : ORIGIN = 0x2000F000, LENGTH = 0x00000FF0 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + OVERLAY : NOCROSSREFS + { +<% $counter = 0 %> +<%OV_LIST%> + .test$counter { */test_$tests[$counter].o(.text*) */test_$tests[$counter].o(.rodata*) } +<% $counter++; return 'OV_LIST' if $counter < scalar(@tests); '' %> + } > m_ovl AT> m_ocram + + .test_ovly_table : + { + . = ALIGN(4); + __ovly_table = .; + LONG(0x34982933); LONG(0); LONG($last); +<% $counter = 0 %> +<%TB_LIST%> + LONG(ABSOLUTE(ADDR(.test$counter))); LONG(SIZEOF(.test$counter)); LONG(LOADADDR(.test$counter)); +<% $counter++; return 'TB_LIST' if $counter < scalar(@tests); '' %> + LONG(0); LONG(0); LONG(0); + } > m_ocram + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8QM/linker/gcc/MX8QM_tcm.ld b/platform/devices/MX8QM/linker/gcc/MX8QM_tcm.ld new file mode 100755 index 0000000..55984d3 --- /dev/null +++ b/platform/devices/MX8QM/linker/gcc/MX8QM_tcm.ld @@ -0,0 +1,288 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002fd70 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8QM/system_MX8QM.h b/platform/devices/MX8QM/system_MX8QM.h new file mode 100755 index 0000000..c2511f0 --- /dev/null +++ b/platform/devices/MX8QM/system_MX8QM.h @@ -0,0 +1,198 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_H +#define SYSTEM_H /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defines */ + +/* Reset requires 32 cycles of xtal24M to propagate. SysTick clocked from + ROSC will be used for delay. + + ROSC @ 200 MHz +*/ +#define RESET_WAIT_ROSC_CYCLES (((SC_ROSC_FREQ_HZ / SC_XTAL24M_FREQ_HZ) + 1U) * 32U) + +/* Define delay for top-level top-level SSI power switch chains. + */ +#define SYSCTR_NSEC_TO_CYCLES(nsec) ((((nsec) * SC_MCU_STARTUP_FREQ_MHZ) + 999U) / 1000U) +#define SSI_CHAIN_LF_CYCLES (SYSCTR_NSEC_TO_CYCLES(500U)) +#define SSI_CHAIN_HF_CYCLES (SYSCTR_NSEC_TO_CYCLES(2000U)) + +/* OSC24M lock spec unknown, use conservative 4ms */ +#define OSC24M_WAIT_ROSC_CYCLES (4*SC_ROSC_FREQ_HZ/1000U) + +/* Address for environment event trigger */ +#define SC_ENV_TRIG_ADDR 0x2000FFF0U + +/* Query to determine if firmware loaded by ROM */ +#ifndef SIMU +#define SCFW_LOADED_BY_ROM ((DSC_SC->GPR_CTRL[0].RW & BIT(31))) +#else +#define SCFW_LOADED_BY_ROM (0x80000000U) +#endif + +/* Query to determine boot mode + * BOOT_MODE[7:0] tied to DSC.GPR_STAT[0] bits [23:16] + */ +#define SC_BOOT_MODE ((DSC_SC->GPR_STAT[0].RW & 0x00FF0000U) >> 16U) + +/* BOOT_MODE = Infinite loop mode = bXX111000 = 0x38 */ +#define SC_BOOT_MODE_INF_LOOP 0x38U + +/* Margin to wake system early from LLS for WDOG servicing */ +#define SC_WAKE_MARGIN_MSEC 5U + +#ifdef DEBUG +extern uint32_t __DEBUG_DATA[]; +#define SCFW_DBG_READY (__DEBUG_DATA[0]) +#define SCFW_DBG_SKIPS (__DEBUG_DATA[1]) +#define SCFW_DBG_DUMP_PTR (&(__DEBUG_DATA[2])) +#define SCFW_DBG_DUMP_R0 (__DEBUG_DATA[2]) +#define SCFW_DBG_DUMP_R1 (__DEBUG_DATA[3]) +#define SCFW_DBG_DUMP_R2 (__DEBUG_DATA[4]) +#define SCFW_DBG_DUMP_R3 (__DEBUG_DATA[5]) +#define SCFW_DBG_DUMP_R12 (__DEBUG_DATA[6]) +#define SCFW_DBG_DUMP_LR (__DEBUG_DATA[7]) +#define SCFW_DBG_DUMP_PC (__DEBUG_DATA[8]) +#define SCFW_DBG_DUMP_PSR (__DEBUG_DATA[9]) +#define SCFW_DBG_SCTR_TICKS (__DEBUG_DATA[10]) +#define SCFW_DBG_RSVD0 (__DEBUG_DATA[11]) +#define SCFW_DBG_TX_PTR (&__DEBUG_DATA[12]) +#define SCFW_DBG_RX_PTR (&__DEBUG_DATA[13]) +#endif + +#define SC_ENV_TRIG_DUMP 0xc0ffee10U //!< Start dump +#define SC_ENV_TRIG_KILL 0xc0ffee20U //!< Kill execution + +/* Types */ + +/*! + * This type is used to indicate the trigger event. + */ +typedef uint32_t sc_env_trig_event_t; + +/** + * @brief Generate environment event trigger + * + */ +void SystemEventTrigger (sc_env_trig_event_t event); + +/** + * @brief Enter firmware critical section. + * + */ +void SystemEnterCS(void); + +/** + * @brief Exit firmware critical section. + * + */ +void SystemExitCS(void); + +/** + * @brief Get active exception. + * + */ +uint32_t SystemGetActiveException(void); + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit(void); + +void SystemInitPostCRT(void); + +/** + * @brief Prepares to enter Low-Power Mode (LPM) + * + */ +void SystemPrepareLPM(void); + +void SystemEnterLPM(void); + +/** + * @brief Delays the specified number of usec + * + */ +void SystemTimeDelay(uint32_t usec); + +void SystemDebugWaitAttach(void); + +void CommonFault_Handler(uint32_t *sp); + +void SystemDebugHalt(void); + +void SystemExit(void); + +void HardFault_Handler(uint32_t *sp); + +void MemManage_Handler(uint32_t *sp); + +void BusFault_Handler(uint32_t *sp); + +void UsageFault_Handler(uint32_t *sp); + +void SystemDebugResume(void); + +#if defined(DEBUG) || defined(HAS_TEST) +uint32_t SystemMemoryProbe(void *addr, void *val, uint8_t width); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_H_) */ diff --git a/platform/devices/MX8QX/MX8QX.h b/platform/devices/MX8QX/MX8QX.h new file mode 100755 index 0000000..b25d40b --- /dev/null +++ b/platform/devices/MX8QX/MX8QX.h @@ -0,0 +1,704 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * @file MX8QX.h + * @version 1.7 + * @date 2015-05-16 + * @brief CMSIS Peripheral Access Layer for MX8QX + * + * CMSIS Peripheral Access Layer for MX8QX + */ + +#ifndef MX8QX_H +#define MX8QX_H /**< Symbol preventing repeated inclusion */ + +/* Check for valid CPU versions */ +#if !defined(SREV_B0) && !defined(SREV_C0) + #error "Invalid SOC revision!\n" +#endif + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0007U + + +/* ---------------------------------------------------------------------------- + -- Memory Map (SC perspective) + ---------------------------------------------------------------------------- */ + +#define LSIO_SS_BASE1 0x00000000U /* LSIO SS - slot 1 */ +#define OCRAM_ALIAS_BASE (LSIO_SS_BASE1+0x000000U) /* OCRAM alias */ +#define SC_ROM_BASE 0x00000000U /* SC ROM */ +#define OCRAM_BASE (LSIO_SS_BASE1+0x100000U) /* OCRAM */ +#define FSPI0_MEM_BASE (LSIO_SS_BASE1+0x8000000U) /* FlexSPI0 Memory */ +#define TCML_BASE 0x1FFE0000U /* SC TCML */ +#define TCMU_BASE 0x20000000U /* SC TCMU */ +#define CAAM_BASE 0x20400000U /* SC CAAM */ +#define ADM_BASE 0x20520000U /* SC ADM */ +#define OTP_BASE 0x20530000U /* SC OTP */ +#define SNVS_BASE 0x20540000U /* SC SNVS */ +#define MU0_BASE 0x20550000U /* SECO MU 1 */ +#define VPU_SS_BASE1 0x2C000000U /* VPU SS - slot 1 */ +#define VPU_SCB_BASE (VPU_SS_BASE1+0x0070000U) /* VPU SCB */ +#define VPU_MFD_BASE (VPU_SS_BASE1+0x01B0000U) /* VPU Decoder */ +#define MU7_BASE (VPU_SS_BASE1+0x1010000U) /* VPU MU 0 */ +#define MU8_BASE (VPU_SS_BASE1+0x1030000U) /* VPU MU 1 */ +#define SCU_SS_BASE0 0x30000000U /* SCU SS - slot 0 */ +#define TCML0_BASE (SCU_SS_BASE0+0x00FE0000U) /* SCU TCML */ +#define TCMU0_BASE (SCU_SS_BASE0+0x01000000U) /* SCU TCMU */ +#define MCU_0_SS_BASE0 0x34000000U /* MCU 0 SS - slot 0 */ +#define TCML1_BASE (MCU_0_SS_BASE0+0x0FE0000U) /* MCU 0 TCML */ +#define TCMU1_BASE (MCU_0_SS_BASE0+0x1000000U) /* MCU 0 TCMU */ +#define RGPIOB_BASE (MCU_0_SS_BASE0+0x30F0000U) /* MCU 0 RGPIO */ +#define LPUART1_BASE (MCU_0_SS_BASE0+0x3220000U) /* MCU 0 LPUART */ +#define LPI2C1_BASE (MCU_0_SS_BASE0+0x3230000U) /* MCU 0 LPI2C */ +#define WDOG1_BASE (MCU_0_SS_BASE0+0x3420000U) /* MCU 0 WDOG */ +#define MU9_BASE (MCU_0_SS_BASE0+0x3480000U) /* MCU 0 MU 1A */ +#define SYSCTR_CTRL_BASE 0x40000000U /* SC SYSCTR Control */ +#define SYSCTR_RD_BASE 0x40010000U /* SC SYSCTR Read */ +#define SYSCTR_CMP_BASE 0x40020000U /* SC SYSCTR Compare 0 */ +#define SYSCTR_CMP1_BASE 0x40020100U /* SC SYSCTR Compare 1 */ +#define LPC_BASE 0x40070000U /* SC LPC */ +#define CSGPR_BASE 0x40470000U /* CoreSight GPR */ +#define AP_1_DEBUG_APB_BASE 0x40600000U /* AP_1 Debug APB */ +#define AP_0_DEBUG_APB_BASE 0x40800000U /* AP_0 Debug APB */ +#define AP_2_DEBUG_APB_BASE 0x40800000U /* AP_2 Debug APB */ +#define RGPIOA_BASE 0x410F0000U /* SC RGPIO */ +#define LPIT0_BASE 0x41210000U /* SC LPIT */ +#define LPUART0_BASE 0x41220000U /* SC LPUART */ +#define LPI2C0_BASE 0x41230000U /* SC LPI2C */ +#define ASMC_BASE 0x41410000U /* SC ASMC */ +#define WDOG0_BASE 0x41420000U /* SC WDOG */ +#define MU1_BASE 0x41430000U /* SC MU 0B */ +#define MU2_BASE 0x41440000U /* SC MU 0A0 */ +#define MU3_BASE 0x41450000U /* SC MU 0A1 */ +#define MU4_BASE 0x41460000U /* SC MU 0A2 */ +#define MU5_BASE 0x41470000U /* SC MU 0A3 */ +#define MU6_BASE 0x41480000U /* SC MU 1A */ +#define MSI0_BASE 0x41800000U /* SC DSC MSI Ring 0 */ +#define DSC1_BASE 0x41820000U /* SC SC DSC */ +#define REP2_BASE 0x4182B000U /* SC MBIST MTR */ +#define MSI1_BASE 0x41A00000U /* SC DSC MSI Ring 1 */ +#define DSC19_BASE 0x41A60000U /* SC ADMA DSC */ +#define DSC22_BASE 0x41AC0000U /* SC GPU_0 DSC */ +#define DSC25_BASE 0x41B20000U /* SC DB DSC */ +#define DSC26_BASE 0x41B40000U /* SC AP_2 DSC */ +#define DSC27_BASE 0x41B60000U /* SC MCU_0 DSC */ +#define MSI2_BASE 0x41C00000U /* SC DSC MSI Ring 2 */ +#define DSC36_BASE 0x41C80000U /* SC DRC_0 DSC */ +#define DSC37_BASE 0x41CA0000U /* SC DC_0 DSC */ +#define DSC38_BASE 0x41CC0000U /* SC HSIO DSC */ +#define DSC39_BASE 0x41CE0000U /* SC CONN DSC */ +#define DSC40_BASE 0x41D00000U /* SC VPU DSC */ +#define MSI3_BASE 0x41E00000U /* SC DSC MSI Ring 3 */ +#define DSC50_BASE 0x41E40000U /* SC IMG DSC */ +#define DSC51_BASE 0x41E60000U /* SC LSIO DSC */ +#define DSC56_BASE 0x41F00000U /* SC MIPI_1 DSC */ +#define DSC57_BASE 0x41F20000U /* SC MIPI_0 DSC */ +#define DSC58_BASE 0x41F40000U /* SC CSI_0 DSC */ +#define DSC59_BASE 0x41F60000U /* SC PI_0 DSC */ +#define PAD_BASE 0x41F80000U /* SC Pad */ +#define MSI4_BASE 0x41F9F000U /* SC Pad MSI Ring 0 */ +#define MSI5_BASE 0x41FBF000U /* SC Pad MSI Ring 1 */ +#define MSI6_BASE 0x41FDF000U /* SC Pad MSI Ring 2 */ +#define MSI7_BASE 0x41FFF000U /* SC Pad MSI Ring 3 */ +#define ADMA_SS_BASE2 0x51000000U /* ADMA SS - slot 2 */ +#define IRQSTR_SCU_BASE (ADMA_SS_BASE2+0x060000U) /* IRQSTR.SCU1 */ +#define GIC0_BASE (ADMA_SS_BASE2+0xA00000U) /* GIC 0 */ +#define GPU_0_SS_BASE0 0x53000000U /* GPU 0 SS - slot 0 */ +#define DC_0_SS_BASE0 0x56000000U /* DC 0 SS - slot 0 */ +#define DC_0_ADDR_0 (DC_0_SS_BASE0+0x00000U) /* DC 0 test addr 0 */ +#define DC_0_ADDR_1 (DC_0_SS_BASE0+0x10000U) /* DC 0 test addr 1 */ +#define DC_0_MSI_BASE (DC_0_SS_BASE0+0x200000U) /* DC_0 MSI CTRL */ +#define MIPI_0_SS_BASE (DC_0_SS_BASE0+0x220000U) /* MIPI 0 */ +#define LPI2C2_BASE (MIPI_0_SS_BASE+0x6000U) /* MIPI 0 LPI2C 0 */ +#define LPI2C3_BASE (MIPI_0_SS_BASE+0x7000U) /* MIPI 0 LPI2C 1 */ +#define MIPI_1_SS_BASE (DC_0_SS_BASE0+0x240000U) /* MIPI 1 */ +#define LPI2C4_BASE (MIPI_1_SS_BASE+0x6000U) /* MIPI 1 LPI2C 0 */ +#define LPI2C5_BASE (MIPI_1_SS_BASE+0x7000U) /* MIPI 1 LPI2C 1 */ +#define IMG_SS_BASE0 0x58000000U /* IMG SS - slot 0 */ +#define IMG_0_GPIO_BASE (IMG_SS_BASE0+0x000000U) /* IMG GPIO */ +#define ISI0_BASE (IMG_SS_BASE0+0x100000U) /* IMG CH0 */ +#define ISI1_BASE (IMG_SS_BASE0+0x110000U) /* IMG CH1 */ +#define ISI2_BASE (IMG_SS_BASE0+0x120000U) /* IMG CH2 */ +#define ISI3_BASE (IMG_SS_BASE0+0x130000U) /* IMG CH3 */ +#define ISI4_BASE (IMG_SS_BASE0+0x140000U) /* IMG CH4 */ +#define ISI5_BASE (IMG_SS_BASE0+0x150000U) /* IMG CH5 */ +#define ISI6_BASE (IMG_SS_BASE0+0x160000U) /* IMG CH6 */ +#define ISI7_BASE (IMG_SS_BASE0+0x170000U) /* IMG CH7 */ +#define IMG_0_MSI_BASE (IMG_SS_BASE0+0x200000U) /* IMG MSI CTRL */ +#define CSI_0_SS_BASE (IMG_SS_BASE0+0x220000U) /* CSI 0 */ +#define LPI2C6_BASE (CSI_0_SS_BASE+0x6000U) /* CSI 0 LPI2C 0 */ +#define PI_0_SS_BASE (IMG_SS_BASE0+0x260000U) /* PI 0 */ +#define PI_0_BASE (PI_0_SS_BASE+0x1000U) /* PI 0 */ +#define LPI2C7_BASE (PI_0_SS_BASE+0x6000U) /* PI 0 LPI2C */ +#define ADMA_SS_BASE0 0x59000000U /* ADMA SS - slot 0 */ +#define DMA0_BASE (ADMA_SS_BASE0+0x1F0000U) /* ADMA eDMA 0 MP */ +#define DSP_DRAM_BASE (ADMA_SS_BASE0+0x6E8000U) /* DSP DRAM */ +#define DSP_DRAM1_BASE (ADMA_SS_BASE0+0x6F0000U) /* DSP DRAM 1 */ +#define DSP_IRAM_BASE (ADMA_SS_BASE0+0x6F8000U) /* DSP IRAM */ +#define DSP_OCRAM_BASE (ADMA_SS_BASE0+0x700000U) /* DSP OCRAM */ +#define DMA1_BASE (ADMA_SS_BASE0+0x9F0000U) /* ADMA eDMA 1 MP */ +#define ADMA_SS_BASE1 0x5A000000U /* ADMA SS - slot 1 */ +#define LPUART2_BASE (ADMA_SS_BASE1+0x060000U) /* ADMA LPUART 0 */ +#define LPUART3_BASE (ADMA_SS_BASE1+0x070000U) /* ADMA LPUART 1 */ +#define LPUART4_BASE (ADMA_SS_BASE1+0x080000U) /* ADMA LPUART 2 */ +#define LPUART5_BASE (ADMA_SS_BASE1+0x090000U) /* ADMA LPUART 3 */ +#define DMA2_BASE (ADMA_SS_BASE1+0x1F0000U) /* ADMA eDMA 2 MP */ +#define LPI2C8_BASE (ADMA_SS_BASE1+0x800000U) /* ADMA LPI2C 0 */ +#define LPI2C9_BASE (ADMA_SS_BASE1+0x810000U) /* ADMA LPI2C 1 */ +#define LPI2C10_BASE (ADMA_SS_BASE1+0x820000U) /* ADMA LPI2C 2 */ +#define LPI2C11_BASE (ADMA_SS_BASE1+0x830000U) /* ADMA LPI2C 3 */ +#define DMA3_BASE (ADMA_SS_BASE1+0x9F0000U) /* ADMA eDMA 3 MP */ +#define CONN_SS_BASE0 0x5B000000U /* CONN SS - slot 0 */ +#define SDHC0_BASE (CONN_SS_BASE0+0x010000U) /* CONN SDHC 0 */ +#define SDHC1_BASE (CONN_SS_BASE0+0x020000U) /* CONN SDHC 1 */ +#define SDHC2_BASE (CONN_SS_BASE0+0x030000U) /* CONN SDHC 2 */ +#define ENET0_BASE (CONN_SS_BASE0+0x040000U) /* CONN ENET 0 */ +#define ENET1_BASE (CONN_SS_BASE0+0x050000U) /* CONN ENET 1 */ +#define DMA4_BASE (CONN_SS_BASE0+0x070000U) /* CONN eDMA MP */ +#define USB_0_BASE (CONN_SS_BASE0+0x0D0000U) /* CONN USB 0 */ +#define USB_1_BASE (CONN_SS_BASE0+0x0E0000U) /* CONN USB 1 */ +#define USB_0_PHY_BASE (CONN_SS_BASE0+0x100000U) /* CONN USB 0 PHY */ +#define USB_1_PHY_BASE (CONN_SS_BASE0+0x110000U) /* CONN USB 1 PHY */ +#define ENET0_LPCG (CONN_SS_BASE0+0x230000U) /* CONN ENET 0 LPCG */ +#define NAND_BASE (CONN_SS_BASE0+0x810000U) /* CONN NAND */ +#define DB_SS_BASE0 0x5C000000U /* DB SS - slot 0 */ +#define DRC_LPCG_6 (DB_SS_BASE0+0x090000U) /* DRC LPCG 6 */ +#define DRC_LPCG_5 (DB_SS_BASE0+0x0A0000U) /* DRC LPCG 5 - fixed */ +#define DRC_LPCG_4 (DB_SS_BASE0+0x0B0000U) /* DRC LPCG 4 - fixed */ +#define DRC_LPCG_0 (DB_SS_BASE0+0x0C0000U) /* DRC LPCG 0 */ +#define DRC_LPCG_1 (DB_SS_BASE0+0x0D0000U) /* DRC LPCG 1 */ +#define DRC_LPCG_2 (DB_SS_BASE0+0x0E0000U) /* DRC LPCG 2 - doesn't exist */ +#define DRC_LPCG_3 (DB_SS_BASE0+0x0F0000U) /* DRC LPCG 3 */ +#define STC0_BASE (DB_SS_BASE0+0x400000U) /* DB PG0 STC 0 */ +#define STC1_BASE (DB_SS_BASE0+0x410000U) /* DB PG0 STC 1 */ +#define STC2_BASE (DB_SS_BASE0+0x420000U) /* DB PG0 STC 2 */ +#define STC3_BASE (DB_SS_BASE0+0x430000U) /* DB PG0 STC 3 */ +#define DB_LPCG_PG0_BASE (DB_SS_BASE0+0x4F0000U) /* DB PG0 LPCG */ +#define STC4_BASE (DB_SS_BASE0+0x500000U) /* DB PG1 STC 0 */ +#define STC5_BASE (DB_SS_BASE0+0x510000U) /* DB PG1 STC 1 */ +#define STC6_BASE (DB_SS_BASE0+0x520000U) /* DB PG1 STC 2 */ +#define STC7_BASE (DB_SS_BASE0+0x530000U) /* DB PG1 STC 3 */ +#define DB_LPCG_PG1_BASE (DB_SS_BASE0+0x5F0000U) /* DB PG1 LPCG */ +#define STC8_BASE (DB_SS_BASE0+0x600000U) /* DB PG2 STC 0 */ +#define STC9_BASE (DB_SS_BASE0+0x610000U) /* DB PG2 STC 1 */ +#define STC10_BASE (DB_SS_BASE0+0x620000U) /* DB PG2 STC 2 */ +#define STC11_BASE (DB_SS_BASE0+0x630000U) /* DB PG2 STC 3 */ +#define DB_LPCG_PG2_BASE (DB_SS_BASE0+0x6F0000U) /* DB PG2 LPCG */ +#define DB_LPCG_BN_BASE (DB_SS_BASE0+0xAF0000U) /* DB BN LPCG */ +#define LSIO_SS_BASE0 0x5D000000U /* LSIO SS - slot 0 */ +#define PWM0_BASE (LSIO_SS_BASE0+0x000000U) /* LSIO PWM 0 */ +#define PWM1_BASE (LSIO_SS_BASE0+0x010000U) /* LSIO PWM 1 */ +#define PWM2_BASE (LSIO_SS_BASE0+0x020000U) /* LSIO PWM 2 */ +#define PWM3_BASE (LSIO_SS_BASE0+0x030000U) /* LSIO PWM 3 */ +#define PWM4_BASE (LSIO_SS_BASE0+0x040000U) /* LSIO PWM 4 */ +#define PWM5_BASE (LSIO_SS_BASE0+0x050000U) /* LSIO PWM 5 */ +#define PWM6_BASE (LSIO_SS_BASE0+0x060000U) /* LSIO PWM 6 */ +#define PWM7_BASE (LSIO_SS_BASE0+0x070000U) /* LSIO PWM 7 */ +#define GPIO0_BASE (LSIO_SS_BASE0+0x080000U) /* LSIO GPIO 0 */ +#define GPIO1_BASE (LSIO_SS_BASE0+0x090000U) /* LSIO GPIO 1 */ +#define GPIO2_BASE (LSIO_SS_BASE0+0x0A0000U) /* LSIO GPIO 2 */ +#define GPIO3_BASE (LSIO_SS_BASE0+0x0B0000U) /* LSIO GPIO 3 */ +#define GPIO4_BASE (LSIO_SS_BASE0+0x0C0000U) /* LSIO GPIO 4 */ +#define GPIO5_BASE (LSIO_SS_BASE0+0x0D0000U) /* LSIO GPIO 5 */ +#define GPIO6_BASE (LSIO_SS_BASE0+0x0E0000U) /* LSIO GPIO 6 */ +#define GPIO7_BASE (LSIO_SS_BASE0+0x0F0000U) /* LSIO GPIO 7 */ +#define FSPI0_BASE (LSIO_SS_BASE0+0x120000U) /* FSPI0 */ +#define FSPI1_BASE (LSIO_SS_BASE0+0x130000U) /* FSPI1 */ +#define GPT0_BASE (LSIO_SS_BASE0+0x140000U) /* LSIO GPT 0 */ +#define GPT1_BASE (LSIO_SS_BASE0+0x150000U) /* LSIO GPT 1 */ +#define GPT2_BASE (LSIO_SS_BASE0+0x160000U) /* LSIO GPT 2 */ +#define GPT3_BASE (LSIO_SS_BASE0+0x170000U) /* LSIO GPT 3 */ +#define GPT4_BASE (LSIO_SS_BASE0+0x180000U) /* LSIO GPT 4 */ +#define KPP_BASE (LSIO_SS_BASE0+0x1A0000U) /* LSIO KPP */ +#define MU10_BASE (LSIO_SS_BASE0+0x1B0000U) /* LSIO MU 0A */ +#define MU11_BASE (LSIO_SS_BASE0+0x1C0000U) /* LSIO MU 1A */ +#define MU12_BASE (LSIO_SS_BASE0+0x1D0000U) /* LSIO MU 2A */ +#define MU13_BASE (LSIO_SS_BASE0+0x1E0000U) /* LSIO MU 3A */ +#define MU14_BASE (LSIO_SS_BASE0+0x1F0000U) /* LSIO MU 4A */ +#define IEE_BASE (LSIO_SS_BASE0+0x320000U) /* IEE */ +#define IEE_R0_BASE (LSIO_SS_BASE0+0x330000U) /* IEE R0 */ +#define IEE_R1_BASE (LSIO_SS_BASE0+0x340000U) /* IEE R1 */ +#define HSIO_0_SS_BASE0 0x5F000000U /* HSIO 0 SS - slot 0 */ +#define HSIO_0_LPCG_GPIO (HSIO_0_SS_BASE0+0x100000U) /* HSIO 0 GPIO LPCG */ +#define HSIO_0_SS_BASE2 0x70000000U /* HSIO 0 SS - slot 2 */ +#define DDR_BASE0 0x80000000U /* DDR */ +#define MCM_BASE 0xE0080000U /* SC MCM */ +#define LMEM_BASE 0xE0082000U /* SC LMEM */ +#define DDR_BASE0_END 0xFFFFFFFFU /* Top of DDR 0 */ +#define LSIO_SS_BASE2 0x400000000ULL /* LSIO SS - slot 2 */ +#define FSPI1_MEM_BASE (LSIO_SS_BASE2+0x0U) /* FlexSPI1 Memory */ +#define DDR_BASE1 0x880000000ULL /* DDR - high mem */ +#define DDR_BASE1_END 0xFFFFFFFFFULL /* Top of DDR 1 */ + +/* Unused */ + +#define DSC2_BASE 0 +#define DSC3_BASE 0 +#define DSC4_BASE 0 +#define DSC5_BASE 0 +#define DSC6_BASE 0 +#define DSC7_BASE 0 +#define DSC8_BASE 0 +#define DSC9_BASE 0 +#define DSC10_BASE 0 +#define DSC11_BASE 0 +#define DSC12_BASE 0 +#define DSC13_BASE 0 +#define DSC14_BASE 0 +#define DSC15_BASE 0 +#define DSC17_BASE 0 +#define DSC18_BASE 0 +#define DSC20_BASE 0 +#define DSC21_BASE 0 +#define DSC23_BASE 0 +#define DSC24_BASE 0 +#define DSC28_BASE 0 +#define DSC29_BASE 0 +#define DSC30_BASE 0 +#define DSC31_BASE 0 +#define DSC33_BASE 0 +#define DSC34_BASE 0 +#define DSC35_BASE 0 +#define DSC41_BASE 0 +#define DSC42_BASE 0 +#define DSC43_BASE 0 +#define DSC44_BASE 0 +#define DSC45_BASE 0 +#define DSC46_BASE 0 +#define DSC47_BASE 0 +#define DSC49_BASE 0 +#define DSC52_BASE 0 +#define DSC53_BASE 0 +#define DSC54_BASE 0 +#define DSC55_BASE 0 +#define DSC60_BASE 0 +#define DSC61_BASE 0 +#define DSC62_BASE 0 +#define DSC63_BASE 0 +#define WDOG2_BASE 0 +#define RGPIOC_BASE 0 +#define LPI2C12_BASE 0 +#define LPI2C13_BASE 0 +#define LPI2C14_BASE 0 +#define LPI2C15_BASE 0 +#define LPI2C16_BASE 0 +#define LPI2C17_BASE 0 +#define LPI2C18_BASE 0 +#define LPI2C19_BASE 0 +#define LPI2C20_BASE 0 +#define LPI2C21_BASE 0 +#define LPI2C22_BASE 0 +#define LPI2C23_BASE 0 +#define LPI2C24_BASE 0 +#define LPI2C25_BASE 0 +#define LPUART6_BASE 0 +#define LPUART7_BASE 0 +#define LPUART8_BASE 0 +#define DMA5_BASE 0 +#define DMA6_BASE 0 +#define ISI8_BASE 0 +#define ISI9_BASE 0 +#define ISI10_BASE 0 +#define ISI11_BASE 0 +#define ISI12_BASE 0 +#define ISI13_BASE 0 +#define ISI14_BASE 0 +#define ISI15_BASE 0 +#define ISI16_BASE 0 +#define ISI17_BASE 0 +#define ISI18_BASE 0 +#define ISI19_BASE 0 +#define ISI20_BASE 0 +#define ISI21_BASE 0 +#define ISI22_BASE 0 +#define ISI23_BASE 0 +#define MU15_BASE 0 +#define MU16_BASE 0 +#define MU17_BASE 0 +#define MU18_BASE 0 +#define MU19_BASE 0 +#define MU20_BASE 0 +#define MU21_BASE 0 +#define MU22_BASE 0 +#define MU23_BASE 0 +#define MU24_BASE 0 +#define STC12_BASE 0 +#define STC13_BASE 0 +#define STC14_BASE 0 +#define STC15_BASE 0 +#define STC16_BASE 0 +#define STC17_BASE 0 +#define STC18_BASE 0 +#define STC19_BASE 0 +#define STC20_BASE 0 +#define STC21_BASE 0 +#define STC22_BASE 0 +#define STC23_BASE 0 + + +/* ---------------------------------------------------------------------------- + -- Device Mapping + ---------------------------------------------------------------------------- */ + +#define DMA_AUDIO0 DMA0 +#define DMA_AUDIO1 DMA1 +#define DMA_PERIPH0 DMA2 +#define DMA_PERIPH1 DMA3 +#define DMA_CONN DMA4 +#define DSC_SC DSC1 +#define DSC_ADMA DSC19 +#define DSC_GPU_0 DSC22 +#define DSC_DB DSC25 +#define DSC_AP_2 DSC26 +#define DSC_MCU_0 DSC27 +#define DSC_DRC_0 DSC36 +#define DSC_DC_0 DSC37 +#define DSC_HSIO DSC38 +#define DSC_CONN DSC39 +#define DSC_VPU DSC40 +#define DSC_IMG DSC50 +#define DSC_LSIO DSC51 +#define DSC_MIPI_1 DSC56 +#define DSC_MIPI_0 DSC57 +#define DSC_CSI_0 DSC58 +#define DSC_PI_0 DSC59 +#define GPIO_SC RGPIOA +#define GPIO_MCU_0 RGPIOB +#define ISI_IMG_0_CH0 ISI0 +#define ISI_IMG_0_CH1 ISI1 +#define ISI_IMG_0_CH2 ISI2 +#define ISI_IMG_0_CH3 ISI3 +#define ISI_IMG_0_CH4 ISI4 +#define ISI_IMG_0_CH5 ISI5 +#define ISI_IMG_0_CH6 ISI6 +#define ISI_IMG_0_CH7 ISI7 +#define LPI2C_SC LPI2C0 +#define LPI2C_MCU_0 LPI2C1 +#define LPI2C_MIPI0_0 LPI2C2 +#define LPI2C_MIPI0_1 LPI2C3 +#define LPI2C_MIPI1_0 LPI2C4 +#define LPI2C_MIPI1_1 LPI2C5 +#define LPI2C_CSI0_0 LPI2C6 +#define LPI2C_PI_0 LPI2C7 +#define LPI2C_0 LPI2C8 +#define LPI2C_1 LPI2C9 +#define LPI2C_2 LPI2C10 +#define LPI2C_3 LPI2C11 +#define LPIT_SC LPIT0 +#define LPUART_SC LPUART0 +#define LPUART_MCU_0 LPUART1 +#define LPUART_0 LPUART2 +#define LPUART_1 LPUART3 +#define LPUART_2 LPUART4 +#define LPUART_3 LPUART5 +#define MU_SECO MU0 +#define MU_SC_0B MU1 +#define MU_SC_0A0 MU2 +#define MU_SC_0A1 MU3 +#define MU_SC_0A2 MU4 +#define MU_SC_0A3 MU5 +#define MU_SC_1A MU6 +#define MU_VPU_0 MU7 +#define MU_VPU_1 MU8 +#define MU_MCU_0_1A MU9 +#define MU_LSIO_0A MU10 +#define MU_LSIO_1A MU11 +#define MU_LSIO_2A MU12 +#define MU_LSIO_3A MU13 +#define MU_LSIO_4A MU14 +#define STC_PG0_0 STC0 +#define STC_PG0_1 STC1 +#define STC_PG0_2 STC2 +#define STC_PG0_3 STC3 +#define STC_PG1_0 STC4 +#define STC_PG1_1 STC5 +#define STC_PG1_2 STC6 +#define STC_PG1_3 STC7 +#define STC_PG2_0 STC8 +#define STC_PG2_1 STC9 +#define STC_PG2_2 STC10 +#define STC_PG2_3 STC11 +#define TCMU_SC TCMU0_BASE +#define TCMU_MCU_0 TCMU1_BASE +#define TCML_SC TCML0_BASE +#define TCML_MCU_0 TCML1_BASE +#define WDOG_SC WDOG0 +#define WDOG_MCU_0 WDOG1 + +/* ---------------------------------------------------------------------------- + -- CoreSight Granular Power Requestor Mappings + ---------------------------------------------------------------------------- */ +#define CSGPR_CPWRUPREQ (CSGPR_BASE+0x000U) +#define CSGPR_CPWRUPACK (CSGPR_BASE+0x004U) +#define CSGPR_CLAIMSET (CSGPR_BASE+0xFA0U) +#define CSGPR_CLAIMCLR (CSGPR_BASE+0xFA4U) +#define CSGPR_LAR (CSGPR_BASE+0xFB0U) +#define CSGPR_LSR (CSGPR_BASE+0xFB4U) + +#define CSGPR_IDX_A35 5U +#define CSGPR_IDX_MCU_0 6U + +#define CSGPR_XOR_DSC_REG 1U +#define CSGPR_XOR_DSC_MASK 0x0000FFFFU +#define CSGPR_ACK_DSC_REG 2U +#define CSGPR_ACK_DSC_MASK 0xFFFF0000U + +/* ---------------------------------------------------------------------------- + -- GIC Mappings + ---------------------------------------------------------------------------- */ +#define GICD_BASE (GIC0_BASE+0x000000U) +#define GICR_BASE (GIC0_BASE+0x100000U) + +#define GICD_CTLR_OFS (0x0000U) +#define GICD_CTLR_RWP_MASK (0x80000000U) + +#define GICR_WAKER_OFS (0x0014U) +#define GICR_WAKER_PA_MASK (0x00000002U) +#define GICR_WAKER_CA_MASK (0x00000004U) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 256 /**< Number of interrupts in the Vector table */ + + /* Auxiliary constants */ +#define NotAvail_IRQn -128 /**< Not available device specific interrupt */ + + /* Core interrupts */ +#define NonMaskableInt_IRQn -14 /**< Non Maskable Interrupt */ +#define HardFault_IRQn -13 /**< Cortex-M4 SV Hard Fault Interrupt */ +#define MemoryManagement_IRQn -12 /**< Cortex-M4 Memory Management Interrupt */ +#define BusFault_IRQn -11 /**< Cortex-M4 Bus Fault Interrupt */ +#define UsageFault_IRQn -10 /**< Cortex-M4 Usage Fault Interrupt */ +#define SVCall_IRQn -5 /**< Cortex-M4 SV Call Interrupt */ +#define DebugMonitor_IRQn -4 /**< Cortex-M4 Debug Monitor Interrupt */ +#define PendSV_IRQn -2 /**< Cortex-M4 Pend SV Interrupt */ +#define SysTick_IRQn -1 /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ +#define Reserved0_IRQn 0 /**< Reserved interrupt */ +#define Reserved1_IRQn 1 /**< Reserved interrupt */ +#define Reserved2_IRQn 2 /**< Reserved interrupt */ +#define Reserved3_IRQn 3 /**< Reserved interrupt */ +#define Reserved4_IRQn 4 /**< Reserved interrupt */ +#define MCM_IRQn 5 /**< MCM interrupt */ +#define DebugWake_IRQn 6 /**< Debug wake interrupt */ +#define OCOTP_Bank0_IRQn 7 /**< OCOTP bank0 interrupt */ +#define OCOTP_Bank1_IRQn 8 /**< OCOTP bank1 interrupt */ +#define Reserved9_IRQn 9 /**< Reserved interrupt */ +#define INTMUX0_8_IRQn 10 /**< INTMUX0_8 interrupt */ +#define INTMUX0_9_IRQn 11 /**< INTMUX0_9 interrupt */ +#define INTMUX0_10_IRQn 12 /**< INTMUX0_10 interrupt */ +#define INTMUX0_11_IRQn 13 /**< INTMUX0_11 interrupt */ +#define INTMUX0_12_IRQn 14 /**< INTMUX0_12 interrupt */ +#define INTMUX0_13_IRQn 15 /**< INTMUX0_13 interrupt */ +#define INTMUX0_14_IRQn 16 /**< INTMUX0_14 interrupt */ +#define INTMUX0_15_IRQn 17 /**< INTMUX0_15 interrupt */ +#define Reserved18_IRQn 18 /**< Reserved interrupt */ +#define TPM0_IRQn 19 /**< TPM0 interrupt */ +#define Reserved20_IRQn 20 /**< Reserved interrupt */ +#define Reserved21_IRQn 21 /**< Reserved interrupt */ +#define LPIT0_IRQn 22 /**< LPIT0 interrupt */ +#define Reserved23_IRQn 23 /**< Reserved interrupt */ +#define Reserved24_IRQn 24 /**< Reserved interrupt */ +#define LPUART0_IRQn 25 /**< LPUART0 interrupt */ +#define Reserved26_IRQn 26 /**< Reserved interrupt */ +#define LPI2C0_IRQn 27 /**< LPI2C0 interrupt */ +#define Reserved28_IRQn 28 /**< Reserved interrupt */ +#define MU0_B0_IRQn 29 /**< MU0_B0 interrupt */ +#define SECO_MU_NMI_IRQn 30 /**< SECO_MU_NMI interrupt */ +#define SECO_MU_IRQn 31 /**< SECO_MU interrupt */ +#define INTMUX0_0_IRQn 32 /**< INTMUX0_0 interrupt */ +#define INTMUX0_1_IRQn 33 /**< INTMUX0_1 interrupt */ +#define INTMUX0_2_IRQn 34 /**< INTMUX0_2 interrupt */ +#define INTMUX0_3_IRQn 35 /**< INTMUX0_3 interrupt */ +#define INTMUX0_4_IRQn 36 /**< INTMUX0_4 interrupt */ +#define INTMUX0_5_IRQn 37 /**< INTMUX0_5 interrupt */ +#define INTMUX0_6_IRQn 38 /**< INTMUX0_6 interrupt */ +#define INTMUX0_7_IRQn 39 /**< INTMUX0_7 interrupt */ +#define SYSCTR_CMP3_IRQn 40 /**< SYSCTR_CMP3 interrupt */ +#define SYSCTR_CMP2_IRQn 41 /**< SYSCTR_CMP2 interrupt */ +#define SYSCTR_CMP1_IRQn 42 /**< SYSCTR_CMP1 interrupt */ +#define SYSCTR_CMP0_IRQn 43 /**< SYSCTR_CMP0 interrupt */ +#define MU0_B1_IRQn 44 /**< MU0_B1 interrupt */ +#define MU0_B2_IRQn 45 /**< MU0_B2 interrupt */ +#define MU0_B3_IRQn 46 /**< MU0_B3 interrupt */ +#define PMIC_INT_IRQn 47 /**< PMIC_INT interrupt */ +#define PMIC_EarlyWarning_IRQn 48 /**< PMIC_EarlyWarning interrupt */ +#define MU1_A_IRQn 49 /**< MU1_A interrupt */ +#define SWI_IRQn 50 /**< Software interrupt */ +#define SWI_DQS2DQ_IRQn 51 /**< DQS2DQ Software interrupt */ +#define CAAM_IRQ0_IRQn 52 /**< CAAM_IRQ0 interrupt */ +#define CAAM_IRQ1_IRQn 53 /**< CAAM_IRQ1 interrupt */ +#define CAAM_IRQ2_IRQn 54 /**< CAAM_IRQ2 interrupt */ +#define CAAM_IRQ3_IRQn 55 /**< CAAM_IRQ3 interrupt */ +#define CAAM_RTIC_IRQn 56 /**< CAAM_RTIC interrupt */ +#define CAAM_Error_IRQn 57 /**< CAAM_Error interrupt */ +#define SNVS_Functional_IRQn 58 /**< SNVS_Functional interrupt */ +#define SNVS_SecurityViolation_IRQn 59 /**< SNVS_SecurityViolation interrupt */ +#define SNVS_Periodic_IRQn 60 /**< SNVS_Periodic interrupt */ +#define SNVS_Button_IRQn 61 /**< SNVS_Button interrupt */ +#define SNVS_Alarm_IRQn 62 /**< Reserved interrupt */ +#define SNVS_PowerOff_IRQn 63 /**< Reserved interrupt */ +#define DSC00_IRQn 64 /**< DSC0 interrupt */ +#define DSC_SCU_IRQn 64 /**< DSC0 interrupt */ +#define DSC_DB_IRQn 65 /**< DSC1 interrupt */ +#define DSC02_IRQn 66 /**< DSC2 interrupt */ +#define DSC03_IRQn 67 /**< DSC3 interrupt */ +#define DSC_HSIO_IRQn 68 /**< DSC4 interrupt */ +#define DSC05_IRQn 69 /**< DSC5 interrupt */ +#define DSC06_IRQn 70 /**< DSC6 interrupt */ +#define DSC_CM4_0_IRQn 71 /**< DSC7 interrupt */ +#define DSC08_IRQn 72 /**< DSC8 interrupt */ +#define DSC09_IRQn 73 /**< DSC9 interrupt */ +#define DSC_LSIO_IRQn 74 /**< DSC10 interrupt */ +#define DSC_GPU_0_IRQn 75 /**< DSC11 interrupt */ +#define DSC_CA35_IRQn 76 /**< DSC12 interrupt */ +#define DSC13_IRQn 77 /**< DSC13 interrupt */ +#define DSC14_IRQn 78 /**< DSC14 interrupt */ +#define DSC15_IRQn 79 /**< DSC15 interrupt */ +#define DSC_Connectivity_IRQn 80 /**< DSC16 interrupt */ +#define DSC17_IRQn 81 /**< DSC17 interrupt */ +#define DSC18_IRQn 82 /**< DSC18 interrupt */ +#define DSC19_IRQn 83 /**< DSC19 interrupt */ +#define DSC_VPU_IRQn 84 /**< DSC20 interrupt */ +#define DSC21_IRQn 85 /**< DSC21 interrupt */ +#define DSC_DRC_0_IRQn 86 /**< DSC22 interrupt */ +#define DSC_DC_0_IRQn 87 /**< DSC23 interrupt */ +#define DSC_MIPI_CSI_0_IRQn 88 /**< DSC24 interrupt */ +#define DSC25_IRQn 89 /**< DSC25 interrupt */ +#define DSC_CI_PI_IRQn 90 /**< DSC26 interrupt */ +#define DSC_Imaging_IRQn 91 /**< DSC27 interrupt */ +#define DSC_ADMA_IRQn 92 /**< DSC28 interrupt */ +#define DSC29_IRQn 93 /**< DSC29 interrupt */ +#define DSC_DI_MIPI_0_IRQn 94 /**< DSC30 interrupt */ +#define DSC_DI_MIPI_1_IRQn 95 /**< DSC31 interrupt */ +#define DSC31_IRQn 95 /**< DSC31 interrupt */ +#define IOMUX31_IRQn 96 /**< IOMUX31 interrupt */ +#define IOMUX30_IRQn 97 /**< IOMUX30 interrupt */ +#define IOMUX29_IRQn 98 /**< IOMUX29 interrupt */ +#define IOMUX28_IRQn 99 /**< IOMUX28 interrupt */ +#define IOMUX27_IRQn 100 /**< IOMUX27 interrupt */ +#define IOMUX26_IRQn 101 /**< IOMUX26 interrupt */ +#define IOMUX25_IRQn 102 /**< IOMUX25 interrupt */ +#define IOMUX24_IRQn 103 /**< IOMUX24 interrupt */ +#define IOMUX23_IRQn 104 /**< IOMUX23 interrupt */ +#define IOMUX22_IRQn 105 /**< IOMUX22 interrupt */ +#define IOMUX21_IRQn 106 /**< IOMUX21 interrupt */ +#define IOMUX20_IRQn 107 /**< IOMUX20 interrupt */ +#define IOMUX19_IRQn 108 /**< IOMUX19 interrupt */ +#define IOMUX18_IRQn 109 /**< IOMUX18 interrupt */ +#define IOMUX17_IRQn 110 /**< IOMUX17 interrupt */ +#define IOMUX16_IRQn 111 /**< IOMUX16 interrupt */ +#define IOMUX15_IRQn 112 /**< IOMUX15 interrupt */ +#define IOMUX14_IRQn 113 /**< IOMUX14 interrupt */ +#define IOMUX13_IRQn 114 /**< IOMUX13 interrupt */ +#define IOMUX12_IRQn 115 /**< IOMUX12 interrupt */ +#define IOMUX11_IRQn 116 /**< IOMUX11 interrupt */ +#define IOMUX10_IRQn 117 /**< IOMUX10 interrupt */ +#define IOMUX9_IRQn 118 /**< IOMUX9 interrupt */ +#define IOMUX8_IRQn 119 /**< IOMUX8 interrupt */ +#define IOMUX7_IRQn 120 /**< IOMUX7 interrupt */ +#define IOMUX6_IRQn 121 /**< IOMUX6 interrupt */ +#define IOMUX5_IRQn 122 /**< IOMUX5 interrupt */ +#define IOMUX4_IRQn 123 /**< IOMUX4 interrupt */ +#define IOMUX3_IRQn 124 /**< IOMUX3 interrupt */ +#define IOMUX2_IRQn 125 /**< IOMUX2 interrupt */ +#define IOMUX1_IRQn 126 /**< IOMUX1 interrupt */ +#define IOMUX0_IRQn 127 /**< IOMUX0 interrupt */ +#define NUM_NVIC_IRQn 128 /**< Number of NVIC interrupts */ + +typedef int IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex-M Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex-M Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MX8QX.h" /* Device specific configuration file */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t LDRD (const __IO uint32_t *addr) +{ + union + { + uint32_t w32[2]; + uint64_t w64; + } llr; + + __ASM volatile ("ldrd %0, %1, %2" : "=r" (llr.w32[0]), "=r" (llr.w32[1]) : "Q" (*addr) ); + + return(llr.w64); +} + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + +#endif /* MX8QX_H */ + +/* MX8QX.h, eof. */ diff --git a/platform/devices/MX8QX/MX8QX_features.h b/platform/devices/MX8QX/MX8QX_features.h new file mode 100755 index 0000000..1973e5a --- /dev/null +++ b/platform/devices/MX8QX/MX8QX_features.h @@ -0,0 +1,457 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef MX8_FEATURES_H +#define MX8_FEATURES_H + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0U) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0U) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0U) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0U) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0U) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0U) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0U) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0U) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0U) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0U) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0U) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0U) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0U) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0U) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (0U) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0U) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0U) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0U) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (1U) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (0U) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0U) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0U) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0U) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (5U) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0U) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0U) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (0U) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0U) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0U) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (1U) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0U) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (0U) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0U) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0U) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0U) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0U) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0U) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0U) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0U) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0U) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (2U) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (8U) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0U) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (0U) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (0U) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0U) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0U) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0U) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0U) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0U) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0U) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0U) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0U) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (1U) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0U) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0U) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0U) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (6U) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0U) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (12U) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0U) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (1U) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0U) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0U) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0U) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0U) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0U) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0U) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0U) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0U) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0U) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0U) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0U) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (15U) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0U) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0U) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0U) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0U) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0U) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0U) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0U) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0U) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0U) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0U) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0U) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0U) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0U) +/* @brief QuadSPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPIO_COUNT (0U) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0U) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0U) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0U) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_RNG_COUNT (0U) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0U) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0U) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0U) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (0U) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0U) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0U) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0U) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0U) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0U) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1U) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (0U) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0U) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0U) +/* @brief STC availability on the SoC. */ +#define FSL_FEATURE_SOC_STC_COUNT (12U) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0U) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0U) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0U) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0U) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0U) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0U) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0U) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0U) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (0U) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0U) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0U) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0U) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0U) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2U) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0U) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0U) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0U) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0U) + +/* LMEM module features */ + +/* @brief Has process identifier support. */ +#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (1U) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0U) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1U) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1U) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1U) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1U) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0U) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0U) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1U) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1U) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0U) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0U) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1U) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0U) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1U) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) \ + (((x) == LPUART_SC) ? (32) : \ + (((x) == LPUART_MCU_0) ? (32) : \ + (((x) == LPUART_0) ? (64) : \ + (((x) == LPUART_1) ? (64) : \ + (((x) == LPUART_2) ? (64) : \ + (((x) == LPUART_3) ? (64) : (-1))))))) + +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10U) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9U) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1U) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0U) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0U) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1U) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0U) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0U) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0U) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1U) +/* @brief Lin break detect available (has bit BDH[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0U) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0U) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == 0 ? (0) : (-1)) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1U) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1U) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1U) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1U) +#define FSL_FEATURE_LPUART0_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART1_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART2_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART3_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART4_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART5_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART6_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART7_HAS_NO_IRQ (1U) +#define FSL_FEATURE_LPUART8_HAS_NO_IRQ (1U) + +/* MU module features */ + +/* @brief MU side for current core */ +#define FSL_FEATURE_MU_SIDE_A (0U) +#define FSL_FEATURE_MU_NO_RSTH (1U) +#define FSL_FEATURE_MU_NO_HR (1U) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1U) +/* @brief WDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1U) + +/* LPI2C module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4U) + +#define FSL_FEATURE_I2C_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C0_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C1_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C2_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C3_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C4_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C5_HAS_NO_IRQ (1U) +#define FSL_FEATURE_I2C6_HAS_NO_IRQ (1U) + +/* PORT module features */ + +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1U) + +/* GPIO module features */ + +#define FSL_FEATURE_GPIO_HAS_NO_INTERRUPT (1U) + +/* PAD module features */ + +/* @brief Pads are for 28LPP. */ +#define FSL_FEATURE_PAD_HAS_28LPP (0U) +/* @brief Pads are for 28FDSOI. */ +#define FSL_FEATURE_PAD_HAS_28FDSOI (1U) + +/* SECO module features */ + +/* @brief SECO protocol version */ +#define FSL_FEATURE_SECO_VER (2U) + +/* OTP module features */ +#define FSL_FEATURE_OTP_16K_1H_OFS_START (16U) +#define FSL_FEATURE_OTP_16K_1H_OFS_END (271U) +#define FSL_FEATURE_OTP_16K_2H_OFS_START (544U) +#define FSL_FEATURE_OTP_16K_2H_OFS_END (799U) + +/* CSR module features */ +#define FSL_FEATURE_CSR_HAS_CSR (0U) +#define FSL_FEATURE_CSR_HAS_CSR2 (1U) +#define FSL_FEATURE_CSR_HAS_CSR3 (1U) +#define FSL_FEATURE_CSR_HAS_LPCG (0U) + +#define FSL_FEATURE_DPLL_VER (18U) +#define FSL_FEATURE_AV_PLL_ENABLE_ALT (0U) + +#define FSL_FEATURE_PCIE_DPLL_SS (0U) + +/* DSC config */ +#define FSL_FEATURE_DSC_SSSLICE_CNT (8U) +#define FSL_FEATURE_DSC_SLSLICE_CNT (17U) +#define FSL_FEATURE_DSC_CSLICE_CNT (1U) +#define FSL_FEATURE_DSC_GPR_CTRL_CNT (3U) + +#endif /* MX8_FEATURES_H */ + diff --git a/platform/devices/MX8QX/MX8QX_fuse_map.h b/platform/devices/MX8QX/MX8QX_fuse_map.h new file mode 100755 index 0000000..2a73506 --- /dev/null +++ b/platform/devices/MX8QX/MX8QX_fuse_map.h @@ -0,0 +1,292 @@ +/* +** ################################################################### +** Processors: MX8QX +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8QX +** +** Copyright 2017-2018 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef HW_FUSES_H +#define HW_FUSES_H + +/******************************************************************************* + * Macros + ******************************************************************************/ +#if !defined(NO_DEVICE_ACCESS) + #define OTP_GET_FUSE_STATE(_REG, SHFT, MSK) \ + ((((uint32_t)(OTP->FUSE[(_REG)].RW)) >> (SHFT)) & (MSK)) +#else + #define OTP_GET_FUSE_STATE(_REG, SHFT, MSK) \ + (((temp_fuses[(_REG)]) >> (SHFT)) & (MSK)) +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define OTP_CAAM_DIS OTP_GET_FUSE_STATE(0x003U, 0U, 0x00000001U) +#define OTP_IEE_DIS OTP_GET_FUSE_STATE(0x003U, 1U, 0x00000001U) +#define OTP_DTCP_DIS OTP_GET_FUSE_STATE(0x003U, 2U, 0x00000001U) +#define OTP_MMCAU_DIS OTP_GET_FUSE_STATE(0x003U, 4U, 0x00000001U) +#define OTP_ARM_CRYPT_EXT OTP_GET_FUSE_STATE(0x003U, 5U, 0x00000001U) +#define OTP_SNVS_DIS OTP_GET_FUSE_STATE(0x003U, 10U, 0x00000001U) +#define OTP_SECO_CLOSED_83 OTP_GET_FUSE_STATE(0x003U, 12U, 0x00000001U) +#define OTP_SECO_SECURED_83 OTP_GET_FUSE_STATE(0x003U, 13U, 0x00000001U) +#define OTP_ATTEST_DIS OTP_GET_FUSE_STATE(0x003U, 14U, 0x00000001U) +#define OTP_PUF_ENB OTP_GET_FUSE_STATE(0x003U, 15U, 0x00000001U) +#define OTP_FUSE_LIFE_CYCLE OTP_GET_FUSE_STATE(0x004U, 0U, 0x000003FFU) +#define OTP_SDP_DIS OTP_GET_FUSE_STATE(0x004U, 10U, 0x00000001U) +#define OTP_SDP_W_ONLY OTP_GET_FUSE_STATE(0x004U, 11U, 0x00000001U) +#define OTP_SREV_XOR OTP_GET_FUSE_STATE(0x004U, 12U, 0x00000007U) +#define OTP_SREV_ROM OTP_GET_FUSE_STATE(0x004U, 15U, 0x00000001U) +#define OTP_SJC_DIS OTP_GET_FUSE_STATE(0x005U, 0U, 0x00000001U) +#define OTP_JTAG_SEC_MODE OTP_GET_FUSE_STATE(0x005U, 1U, 0x00000003U) +#define OTP_TZ_DBG_DIS OTP_GET_FUSE_STATE(0x005U, 3U, 0x00000001U) +#define OTP_OEM_SEC_CONFIG OTP_GET_FUSE_STATE(0x005U, 5U, 0x00000003U) +#define OTP_SCU_SEC_CONFIG OTP_GET_FUSE_STATE(0x005U, 7U, 0x00000003U) +#define OTP_SECO_GLITCH_DET OTP_GET_FUSE_STATE(0x005U, 9U, 0x00000001U) +#define OTP_OTP_CHLG_RESP_DIS OTP_GET_FUSE_STATE(0x005U, 10U, 0x00000001U) +#define OTP_TZ_CHLG_RESP_DIS OTP_GET_FUSE_STATE(0x005U, 11U, 0x00000001U) +#define OTP_ARRAY_IS_PROG OTP_GET_FUSE_STATE(0x005U, 15U, 0x00000001U) +#define OTP_AP_2_DIS OTP_GET_FUSE_STATE(0x006U, 0U, 0x0000000FU) +#define OTP_AP_2_0_DIS OTP_GET_FUSE_STATE(0x006U, 0U, 0x00000001U) +#define OTP_AP_2_1_DIS OTP_GET_FUSE_STATE(0x006U, 1U, 0x00000001U) +#define OTP_AP_2_2_DIS OTP_GET_FUSE_STATE(0x006U, 2U, 0x00000001U) +#define OTP_AP_2_3_DIS OTP_GET_FUSE_STATE(0x006U, 3U, 0x00000001U) +#define OTP_AP_2_MAX_FREQ OTP_GET_FUSE_STATE(0x006U, 8U, 0x0000000FU) +#define OTP_TEMP_GRADE OTP_GET_FUSE_STATE(0x006U, 12U, 0x00000003U) +#define OTP_GPU_0_DIS OTP_GET_FUSE_STATE(0x007U, 0U, 0x00000001U) +#define OTP_GPU_MAX_FREQ OTP_GET_FUSE_STATE(0x007U, 4U, 0x0000000FU) +#define OTP_DC_0_DIS OTP_GET_FUSE_STATE(0x007U, 8U, 0x00000003U) +#define OTP_VPU_DIS OTP_GET_FUSE_STATE(0x007U, 12U, 0x0000000FU) +#define OTP_VPU_ENC0_DIS OTP_GET_FUSE_STATE(0x007U, 12U, 0x00000001U) +#define OTP_VPU_ENC1_DIS OTP_GET_FUSE_STATE(0x007U, 13U, 0x00000001U) +#define OTP_VPU_DEC_DIS OTP_GET_FUSE_STATE(0x007U, 14U, 0x00000003U) +#define OTP_DSP_DIS OTP_GET_FUSE_STATE(0x008U, 0U, 0x00000001U) +#define OTP_MCU_0_DIS OTP_GET_FUSE_STATE(0x008U, 1U, 0x00000001U) +#define OTP_SATA_DIS OTP_GET_FUSE_STATE(0x008U, 4U, 0x00000001U) +#define OTP_PCIE_B_DIS OTP_GET_FUSE_STATE(0x008U, 5U, 0x00000001U) +#define OTP_PCIE_A_DIS OTP_GET_FUSE_STATE(0x008U, 6U, 0x00000001U) +#define OTP_USB2_1_DIS OTP_GET_FUSE_STATE(0x008U, 8U, 0x00000001U) +#define OTP_USB2_2_OTG_DIS OTP_GET_FUSE_STATE(0x008U, 9U, 0x00000001U) +#define OTP_USB_SS_DIS OTP_GET_FUSE_STATE(0x008U, 10U, 0x00000001U) +#define OTP_USB2_3_OTG_DIS OTP_GET_FUSE_STATE(0x008U, 11U, 0x00000001U) +#define OTP_ETH_0_DIS OTP_GET_FUSE_STATE(0x008U, 12U, 0x00000001U) +#define OTP_ETH_1_DIS OTP_GET_FUSE_STATE(0x008U, 13U, 0x00000001U) +#define OTP_MIPI_0_DIS OTP_GET_FUSE_STATE(0x009U, 1U, 0x00000001U) +#define OTP_MIPI_1_DIS OTP_GET_FUSE_STATE(0x009U, 2U, 0x00000001U) +#define OTP_CSI_0_DIS OTP_GET_FUSE_STATE(0x009U, 5U, 0x00000001U) +#define OTP_CSI_1_DIS OTP_GET_FUSE_STATE(0x009U, 6U, 0x00000001U) +#define OTP_CSI_2_DIS OTP_GET_FUSE_STATE(0x009U, 7U, 0x00000001U) +#define OTP_DRC_0_DIS OTP_GET_FUSE_STATE(0x009U, 8U, 0x0000000FU) +#define OTP_CAN_DIS OTP_GET_FUSE_STATE(0x00AU, 0U, 0x00000001U) +#define OTP_ENET1_FREQ_LIMIT OTP_GET_FUSE_STATE(0x00AU, 1U, 0x00000001U) +#define OTP_ENET2_FREQ_LIMIT OTP_GET_FUSE_STATE(0x00AU, 2U, 0x00000001U) +#define OTP_FIPS_MODE OTP_GET_FUSE_STATE(0x00AU, 3U, 0x00000001U) +#define OTP_FIPS_MODE_DIS OTP_GET_FUSE_STATE(0x00AU, 4U, 0x00000001U) + +#define OTP_EARLY_FUS_PROG OTP_GET_FUSE_STATE(0x00EU, 0U, 0x00000001U) +#define OTP_SCU_FUS_PROG OTP_GET_FUSE_STATE(0x00EU, 1U, 0x00000001U) +#define OTP_ALL_FUS_PROG OTP_GET_FUSE_STATE(0x00EU, 2U, 0x00000001U) +#define OTP_SECO_OPEN_8E OTP_GET_FUSE_STATE(0x00EU, 3U, 0x00000001U) +#define OTP_SECO_CLOSED_8E OTP_GET_FUSE_STATE(0x00EU, 4U, 0x00000001U) +#define OTP_SECO_SECURED_8E OTP_GET_FUSE_STATE(0x00EU, 5U, 0x00000001U) +#define OTP_ROM_INF_LOOP OTP_GET_FUSE_STATE(0x00EU, 8U, 0x00000001U) +#define OTP_BT_DIR_DIS OTP_GET_FUSE_STATE(0x00EU, 9U, 0x00000001U) +#define OTP_ROM_CONT_BITS OTP_GET_FUSE_STATE(0x00EU, 10U, 0x0000001FU) +#define OTP_SHELF_MODE OTP_GET_FUSE_STATE(0x00EU, 15U, 0x00000001U) + +/******************************************************************************* + * Trim & other fuses + ******************************************************************************/ + +#define OTP_UNIQUE_ID_L OTP_GET_FUSE_STATE(0x010U, 0U, 0xFFFFFFFFU) +#define OTP_UNIQUE_ID_H OTP_GET_FUSE_STATE(0x011U, 0U, 0xFFFFFFFFU) + +#define OTP_LOT_NO_ENC_L OTP_GET_FUSE_STATE(0x010U, 0U, 0xFFFFFFFFU) +#define OTP_LOT_NO_ENC_H OTP_GET_FUSE_STATE(0x011U, 0U, 0x000007FFU) +#define OTP_WAFER_NO OTP_GET_FUSE_STATE(0x011U, 11U, 0x0000001FU) +#define OTP_DIE_Y_COORD OTP_GET_FUSE_STATE(0x011U, 16U, 0x000000FFU) +#define OTP_DIE_X_COORD OTP_GET_FUSE_STATE(0x011U, 24U, 0x000000FFU) + +#define OTP_BT_MODE_FUS OTP_GET_FUSE_STATE(0x012U, 0U, 0x0000003FU) +#define OTP_BT_FUS_SEL OTP_GET_FUSE_STATE(0x012U, 6U, 0x00000001U) +#define OTP_BT_FORCE_COLD OTP_GET_FUSE_STATE(0x012U, 7U, 0x00000001U) + +#define OTP_WDOG_EN OTP_GET_FUSE_STATE(0x012U, 8U, 0x00000001U) +#define OTP_WDOG_TO OTP_GET_FUSE_STATE(0x012U, 9U, 0x00000003U) +#define OTP_SCU_DCACHE_DIS OTP_GET_FUSE_STATE(0x012U, 11U, 0x00000001U) +#define OTP_SCU_ICACHE_DIS OTP_GET_FUSE_STATE(0x012U, 12U, 0x00000001U) +#define OTP_AP_MMU_DCACHE_DIS OTP_GET_FUSE_STATE(0x012U, 13U, 0x00000001U) +#define OTP_AP_ICACHE_DIS OTP_GET_FUSE_STATE(0x012U, 14U, 0x00000001U) +#define OTP_SDMMC_MAN_DIS OTP_GET_FUSE_STATE(0x012U, 18U, 0x00000001U) +#define OTP_REC_BOOT_EN OTP_GET_FUSE_STATE(0x012U, 19U, 0x00000001U) +#define OTP_SCU_BT_F_GPIO_SEL OTP_GET_FUSE_STATE(0x012U, 20U, 0x00000007U) +#define OTP_SCU_BT_F_IND OTP_GET_FUSE_STATE(0x012U, 23U, 0x00000001U) +#define OTP_FLEXSPI_DLL OTP_GET_FUSE_STATE(0x012U, 24U, 0x0000000FU) +#define OTP_OVR_NAND OTP_GET_FUSE_STATE(0x012U, 28U, 0x00000001U) +#define OTP_OVR_NAND_VAL OTP_GET_FUSE_STATE(0x012U, 29U, 0x00000001U) +#define OTP_OVR_FLX_SPI OTP_GET_FUSE_STATE(0x012U, 30U, 0x00000001U) +#define OTP_OVR_FLX_SPI_VAL OTP_GET_FUSE_STATE(0x012U, 31U, 0x00000001U) +#define OTP_FAST_BOOT OTP_GET_FUSE_STATE(0x013U, 0U, 0x00000001U) +#define OTP_FAST_BOOT_ACK OTP_GET_FUSE_STATE(0x013U, 1U, 0x00000001U) +#define OTP_USDHC_BT_SPD OTP_GET_FUSE_STATE(0x013U, 2U, 0x00000003U) +#define OTP_MMC_BUS_W OTP_GET_FUSE_STATE(0x013U, 4U, 0x00000003U) +#define OTP_FAST_FRZ_DIS OTP_GET_FUSE_STATE(0x013U, 6U, 0x00000001U) + +#define OTP_USDHC_CYC_DLY OTP_GET_FUSE_STATE(0x013U, 8U, 0x00000001U) +#define OTP_USDHC_CYC_INT OTP_GET_FUSE_STATE(0x013U, 9U, 0x00000001U) +#define OTP_USDHC_CYC_EN OTP_GET_FUSE_STATE(0x013U, 10U, 0x00000001U) +#define OTP_USDHC_DLL_EN OTP_GET_FUSE_STATE(0x013U, 11U, 0x00000001U) +#define OTP_SD_LOOPBCK OTP_GET_FUSE_STATE(0x013U, 12U, 0x00000001U) +#define OTP_USDHC_PD_PULLDWN OTP_GET_FUSE_STATE(0x013U, 13U, 0x00000001U) +#define OTP_SD_CAL_STEP OTP_GET_FUSE_STATE(0x013U, 14U, 0x00000003U) +#define OTP_USDHC_DLL_DLY OTP_GET_FUSE_STATE(0x013U, 16U, 0x0000007FU) +#define OTP_USDHC_DLL_SEL OTP_GET_FUSE_STATE(0x013U, 23U, 0x00000001U) +#define OTP_USDHC_PD_SET_OVR OTP_GET_FUSE_STATE(0x013U, 24U, 0x00000007U) +#define OTP_NAND_PD_SET_OVR OTP_GET_FUSE_STATE(0x013U, 27U, 0x00000007U) +#define OTP_CS_NUM_NAND OTP_GET_FUSE_STATE(0x013U, 30U, 0x00000003U) + +#define OTP_DBGEN_DBGEN OTP_GET_FUSE_STATE(0x016U, 0U, 0x000000FFU) +#define OTP_DBGEN_NIDEN OTP_GET_FUSE_STATE(0x016U, 8U, 0x000000FFU) +#define OTP_DBGEN_SPIDEN OTP_GET_FUSE_STATE(0x016U, 16U, 0x000000FFU) +#define OTP_DBGEN_SPNIDEN OTP_GET_FUSE_STATE(0x016U, 24U, 0x000000FFU) + +#define OTP_DPLL_CALIB_V2 OTP_GET_FUSE_STATE(0x01BU, 3U, 0x00000001U) +#define OTP_KS1_07V_SUPPORT OTP_GET_FUSE_STATE(0x01BU, 6U, 0x00000001U) + +#define OTP_OSC_CAP_TRIM OTP_GET_FUSE_STATE(0x01EU, 0U, 0x0000000FU) +#define OTP_TMP_MON_TRM_LO OTP_GET_FUSE_STATE(0x01EU, 4U, 0x0000003FU) +#define OTP_TMP_MON_TRM_HI OTP_GET_FUSE_STATE(0x01EU, 10U, 0x0000003FU) +#define OTP_TMP_MON_TRM_SHLF_LO OTP_GET_FUSE_STATE(0x01EU, 20U, 0x0000003FU) +#define OTP_TMP_MON_TRM_SHLF_HI OTP_GET_FUSE_STATE(0x01EU, 26U, 0x0000003FU) +#define OTP_BANDGAP_TRM OTP_GET_FUSE_STATE(0x01FU, 0U, 0x0000001FU) +#define OTP_32K_INT_IRC_TRM OTP_GET_FUSE_STATE(0x01FU, 5U, 0x0000001FU) +#define OTP_CLK_MON_TRM_LO OTP_GET_FUSE_STATE(0x01FU, 10U, 0x0000000FU) +#define OTP_CLK_MON_TRM_HI OTP_GET_FUSE_STATE(0x01FU, 14U, 0x0000000FU) +#define OTP_V_MON_TRM_LO OTP_GET_FUSE_STATE(0x01FU, 18U, 0x0000000FU) +#define OTP_V_MON_TRM_HI OTP_GET_FUSE_STATE(0x01FU, 22U, 0x0000000FU) +#define OTP_V_MON_TAM_DIS OTP_GET_FUSE_STATE(0x01FU, 26U, 0x00000001U) +#define OTP_CLK_MON_DIS OTP_GET_FUSE_STATE(0x01FU, 27U, 0x00000001U) +#define OTP_TMP_MON_DIS OTP_GET_FUSE_STATE(0x01FU, 28U, 0x00000001U) +#define OTP_SNVS_C_V_TRM OTP_GET_FUSE_STATE(0x01FU, 30U, 0x00000003U) + +#define OTP_SCU_REFGEN OTP_GET_FUSE_STATE(0x064U, 0U, 0x000000FFU) +#define OTP_AP_2_REFGEN OTP_GET_FUSE_STATE(0x064U, 8U, 0x000000FFU) +#define OTP_DRC_REFGEN OTP_GET_FUSE_STATE(0x064U, 24U, 0x000000FFU) +#define OTP_GPU_0_REFGEN OTP_GET_FUSE_STATE(0x065U, 8U, 0x000000FFU) +#define OTP_ADMA_REFGEN OTP_GET_FUSE_STATE(0x065U, 24U, 0x000000FFU) +#define OTP_CONN_REFGEN OTP_GET_FUSE_STATE(0x066U, 0U, 0x000000FFU) +#define OTP_HSIO_REFGEN OTP_GET_FUSE_STATE(0x066U, 24U, 0x000000FFU) + +#define OTP_USB_PHY_TRM OTP_GET_FUSE_STATE(0x067U, 0U, 0x000FFFFFU) +#define OTP_CSI_0_RCAL_TRIM OTP_GET_FUSE_STATE(0x069U, 8U, 0x00000003U) +#define OTP_DSI_0_RCAL_TRIM OTP_GET_FUSE_STATE(0x067U, 20U, 0x00000003U) +#define OTP_DSI_1_RCAL_TRIM OTP_GET_FUSE_STATE(0x067U, 22U, 0x00000003U) + +#define OTP_TMP_SENS_SCU OTP_GET_FUSE_STATE(0x06AU, 2U, 0x000003FFU) +#define OTP_TMP_SENS_3 OTP_GET_FUSE_STATE(0x06AU, 12U, 0x000003FFU) +#define OTP_TMP_SENS_4 OTP_GET_FUSE_STATE(0x06AU, 22U, 0x000003FFU) +#define OTP_TMP_SENS_DRC0 OTP_GET_FUSE_STATE(0x06BU, 2U, 0x000003FFU) +#define OTP_TMP_SENS_6 OTP_GET_FUSE_STATE(0x06BU, 12U, 0x000003FFU) +#define OTP_TMP_SENS_7 OTP_GET_FUSE_STATE(0x06BU, 22U, 0x000003FFU) + +#define OTP_ROM_PATCH 0x070U +#define OTP_ROM_PATCH_SIZE 62U +#define OTP_V2X_PATCH_SIZE 0U + +#define OTP_DERATE_DLL_FRQ OTP_GET_FUSE_STATE(0x0AEU, 0U, 0x00000001U) +#define OTP_EXT_OSC_SEL OTP_GET_FUSE_STATE(0x0AEU, 1U, 0x00000001U) +#define OTP_USE_INT_OSC OTP_GET_FUSE_STATE(0x0AEU, 2U, 0x00000001U) +#define OTP_SINGLE_END_CLK OTP_GET_FUSE_STATE(0x0AEU, 3U, 0x00000001U) + +#define OTP_24MHZ_REGH_LV OTP_GET_FUSE_STATE(0x100U, 0U, 0x00000007U) +#define OTP_24MHZ_REGL_LV OTP_GET_FUSE_STATE(0x100U, 3U, 0x00000007U) +#define OTP_ROSC_FREQ_OFF OTP_GET_FUSE_STATE(0x100U, 8U, 0x00FFFFFFU) + +#define OTP_DPLL_TRM OTP_GET_FUSE_STATE(0x101U, 0U, 0xFFFFFFFFU) +#define OTP_DPLL_TRM_VALID OTP_GET_FUSE_STATE(0x101U, 0U, 0x00800000U) + +#define OTP_24MHZ_DIFF_VALID OTP_GET_FUSE_STATE(0x102U, 31U, 0x00000001U) +#define OTP_24MHZ_DIFF_DRV0 OTP_GET_FUSE_STATE(0x102U, 0U, 0x00000003U) +#define OTP_24MHZ_DIFF_DRV1 OTP_GET_FUSE_STATE(0x102U, 4U, 0x00000003U) +#define OTP_24MHZ_DIFF_TERM_RES OTP_GET_FUSE_STATE(0x102U, 8U, 0x00000003U) +#define OTP_24MHZ_DIFF_DRV_IN OTP_GET_FUSE_STATE(0x102U, 10U, 0x00000003U) +#define OTP_24MHZ_DIFF_SQRUP OTP_GET_FUSE_STATE(0x102U, 12U, 0x00000003U) +#define OTP_SCU_REG_TRIM OTP_GET_FUSE_STATE(0x102U, 16U, 0x00000007U) +#define OTP_VPU_REG0_TRIM OTP_GET_FUSE_STATE(0x102U, 19U, 0x00000007U) +#define OTP_VPU_REG1_TRIM OTP_GET_FUSE_STATE(0x102U, 22U, 0x00000007U) + +#define OTP_DSI_0_VOH_CLK_TRIM OTP_GET_FUSE_STATE(0x103U, 0U, 0x00000007U) +#define OTP_DSI_0_VOH_D3_TRIM OTP_GET_FUSE_STATE(0x103U, 3U, 0x00000007U) +#define OTP_DSI_0_VOH_D2_TRIM OTP_GET_FUSE_STATE(0x103U, 6U, 0x00000007U) +#define OTP_DSI_0_VOH_D1_TRIM OTP_GET_FUSE_STATE(0x103U, 9U, 0x00000007U) +#define OTP_DSI_0_VOH_D0_TRIM OTP_GET_FUSE_STATE(0x103U, 12U, 0x00000007U) +#define OTP_DSI_1_VOH_CLK_TRIM OTP_GET_FUSE_STATE(0x103U, 16U, 0x00000007U) +#define OTP_DSI_1_VOH_D3_TRIM OTP_GET_FUSE_STATE(0x103U, 19U, 0x00000007U) +#define OTP_DSI_1_VOH_D2_TRIM OTP_GET_FUSE_STATE(0x103U, 22U, 0x00000007U) +#define OTP_DSI_1_VOH_D1_TRIM OTP_GET_FUSE_STATE(0x103U, 25U, 0x00000007U) +#define OTP_DSI_1_VOH_D0_TRIM OTP_GET_FUSE_STATE(0x103U, 28U, 0x00000007U) + +#define OTP_ROM_LITERAL 0x10CU +#define OTP_ROM_LITERAL_SIZE 4U + +#define OTP_24MHZ_CL_TUNE_VALID OTP_GET_FUSE_STATE(0x1F0U, 31U, 0x00000001U) +#define OTP_24MHZ_CL_TUNE_LV OTP_GET_FUSE_STATE(0x1F0U, 0U, 0x000000FFU) + +#define OTP_DPLL_TABLE_SELECT_VALID OTP_GET_FUSE_STATE(0x1FDU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_SELECT_BITS OTP_GET_FUSE_STATE(0x1FDU, 0U, 0x003FFFFFU) + +#define OTP_DPLL_TABLE_0_VALID OTP_GET_FUSE_STATE(0x1FEU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_0_V6 OTP_GET_FUSE_STATE(0x1FEU, 26U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V5 OTP_GET_FUSE_STATE(0x1FEU, 21U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V4 OTP_GET_FUSE_STATE(0x1FEU, 16U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V3 OTP_GET_FUSE_STATE(0x1FEU, 11U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V2 OTP_GET_FUSE_STATE(0x1FEU, 6U, 0x0000001FU) +#define OTP_DPLL_TABLE_0_V1 OTP_GET_FUSE_STATE(0x1FEU, 0U, 0x0000003FU) + +#define OTP_DPLL_TABLE_1_VALID OTP_GET_FUSE_STATE(0x1FFU, 31U, 0x00000001U) +#define OTP_DPLL_TABLE_1_V6 OTP_GET_FUSE_STATE(0x1FFU, 26U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V5 OTP_GET_FUSE_STATE(0x1FFU, 21U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V4 OTP_GET_FUSE_STATE(0x1FFU, 16U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V3 OTP_GET_FUSE_STATE(0x1FFU, 11U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V2 OTP_GET_FUSE_STATE(0x1FFU, 6U, 0x0000001FU) +#define OTP_DPLL_TABLE_1_V1 OTP_GET_FUSE_STATE(0x1FFU, 0U, 0x0000003FU) + +#define OTP_TMP_SENS_SCU_OFS OTP_GET_FUSE_STATE(0x1F1U, 0U, 0x000000FFU) +#define OTP_TMP_SENS_DRC0_OFS OTP_GET_FUSE_STATE(0x1F1U, 8U, 0x000000FFU) + +#endif /* HW_FUSES_H */ + diff --git a/platform/devices/MX8QX/MX8QX_otp.h b/platform/devices/MX8QX/MX8QX_otp.h new file mode 100755 index 0000000..9145340 --- /dev/null +++ b/platform/devices/MX8QX/MX8QX_otp.h @@ -0,0 +1,318 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* + * WARNING! DO NOT EDIT THIS FILE DIRECTLY! + * + * This file was generated automatically and any changes may be lost. + */ +#ifndef HW_OTP_REGISTERS_H +#define HW_OTP_REGISTERS_H + +/* ---------------------------------------------------------------------------- + -- OTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTP_Peripheral_Access_Layer OTP Peripheral Access Layer + * @{ + */ + +/** OTP - Register Layout Typedef */ +typedef struct +{ + __IO uint32_t RW; + __IO uint32_t SET; + __IO uint32_t CLR; + __IO uint32_t TOG; +} OTP_Reg; + +typedef struct +{ + OTP_Reg CTRL; + OTP_Reg PDN; + OTP_Reg DATA; + OTP_Reg READ_CTRL; + OTP_Reg READ_FUSE_DATA; + OTP_Reg SW_STICKY; + OTP_Reg SCS; + OTP_Reg CRC_ADDR; + OTP_Reg CRC_VALUE; + OTP_Reg STATUS; + __I uint32_t STARTWORD; + uint8_t RESERVED_0[12]; + __I uint32_t VERSION; + uint8_t RESERVED_1[1356]; + struct { + __I uint32_t RW; + __I uint32_t SET; + __I uint32_t CLR; + __I uint32_t TOG; + } LOCKED[17]; + uint8_t RESERVED_3[240]; + OTP_Reg FUSE[528]; +} OTP_Type; + +/* ---------------------------------------------------------------------------- + -- OTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTP_Register_Masks OTP Register Masks + * @{ + */ + +/*! @name OTP Register */ +#define OTP_BIT0_MASK (0x00000001U) +#define OTP_BIT0_SHIFT (0U) +#define OTP_BIT0(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT1_MASK (0x00000002U) +#define OTP_BIT1_SHIFT (1U) +#define OTP_BIT1(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT2_MASK (0x00000004U) +#define OTP_BIT2_SHIFT (2U) +#define OTP_BIT2(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT3_MASK (0x00000008U) +#define OTP_BIT3_SHIFT (3U) +#define OTP_BIT3(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT4_MASK (0x00000010U) +#define OTP_BIT4_SHIFT (4U) +#define OTP_BIT4(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT5_MASK (0x00000020U) +#define OTP_BIT5_SHIFT (5U) +#define OTP_BIT5(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT6_MASK (0x00000040U) +#define OTP_BIT6_SHIFT (6U) +#define OTP_BIT6(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT7_MASK (0x00000080U) +#define OTP_BIT7_SHIFT (7U) +#define OTP_BIT7(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT8_MASK (0x00000100U) +#define OTP_BIT8_SHIFT (8U) +#define OTP_BIT8(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT9_MASK (0x00000200U) +#define OTP_BIT9_SHIFT (9U) +#define OTP_BIT9(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT10_MASK (0x00000400U) +#define OTP_BIT10_SHIFT (10U) +#define OTP_BIT10(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT11_MASK (0x00000800U) +#define OTP_BIT11_SHIFT (11U) +#define OTP_BIT11(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT12_MASK (0x00001000U) +#define OTP_BIT12_SHIFT (12U) +#define OTP_BIT12(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT13_MASK (0x00002000U) +#define OTP_BIT13_SHIFT (13U) +#define OTP_BIT13(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT14_MASK (0x00004000U) +#define OTP_BIT14_SHIFT (14U) +#define OTP_BIT14(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT15_MASK (0x00008000U) +#define OTP_BIT15_SHIFT (15U) +#define OTP_BIT15(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT16_MASK (0x00010000U) +#define OTP_BIT16_SHIFT (16U) +#define OTP_BIT16(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT17_MASK (0x00020000U) +#define OTP_BIT17_SHIFT (17U) +#define OTP_BIT17(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT18_MASK (0x00040000U) +#define OTP_BIT18_SHIFT (18U) +#define OTP_BIT18(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT19_MASK (0x00080000U) +#define OTP_BIT19_SHIFT (19U) +#define OTP_BIT19(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT20_MASK (0x00100000U) +#define OTP_BIT20_SHIFT (20U) +#define OTP_BIT20(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT21_ASK (0x00200000U) +#define OTP_BIT21_SHIFT (21U) +#define OTP_BIT21(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT22_MASK (0x00400000U) +#define OTP_BIT22_SHIFT (22U) +#define OTP_BIT22(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT23_MASK (0x00800000U) +#define OTP_BIT23_SHIFT (23U) +#define OTP_BIT23(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT24_MASK (0x01000000U) +#define OTP_BIT24_SHIFT (24U) +#define OTP_BIT24(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT25_MASK (0x02000000U) +#define OTP_BIT25_SHIFT (25U) +#define OTP_BIT25(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT26_MASK (0x04000000U) +#define OTP_BIT26_SHIFT (26U) +#define OTP_BIT26(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT27_MASK (0x08000000U) +#define OTP_BIT27_SHIFT (27U) +#define OTP_BIT27(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT28_MASK (0x10000000U) +#define OTP_BIT28_SHIFT (28U) +#define OTP_BIT28(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT29_MASK (0x20000000U) +#define OTP_BIT29_SHIFT (29U) +#define OTP_BIT29(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT30_MASK (0x40000000U) +#define OTP_BIT30_SHIFT (30U) +#define OTP_BIT30(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_BIT31_MASK (0x80000000U) +#define OTP_BIT31_SHIFT (31U) +#define OTP_BIT31(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE0_MASK (0x0000000FU) +#define OTP_NIBBLE0_SHIFT (0U) +#define OTP_NIBBLE0(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE1_MASK (0x000000F0U) +#define OTP_NIBBLE1_SHIFT (4U) +#define OTP_NIBBLE1(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE2_MASK (0x00000F00U) +#define OTP_NIBBLE2_SHIFT (8U) +#define OTP_NIBBLE2(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE3_MASK (0x0000F000U) +#define OTP_NIBBLE3_SHIFT (12U) +#define OTP_NIBBLE3(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE4_MASK (0x000F0000U) +#define OTP_NIBBLE4_SHIFT (16U) +#define OTP_NIBBLE4(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE5_MASK (0x00F00000U) +#define OTP_NIBBLE5_SHIFT (20U) +#define OTP_NIBBLE5(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE6_MASK (0x0F000000U) +#define OTP_NIBBLE6_SHIFT (24U) +#define OTP_NIBBLE6(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! @name OTP Register */ +#define OTP_NIBBLE7_MASK (0xF0000000U) +#define OTP_NIBBLE7_SHIFT (28U) +#define OTP_NIBBLE7(x) (((uint32_t)(((uint32_t)(x)) << OTP_PDOR_PDO_SHIFT)) & OTP_PDOR_PDO_MASK) + +/*! + * @} + */ /* end of group OTP_Register_Masks */ + +/* OTP - Peripheral instance base addresses */ +/** Peripheral OTPA base pointer */ +#define OTP ((OTP_Type *)OTP_BASE) +/** Array initializer of OTP peripheral base addresses */ +#define OTP_BASE_ADDRS { OTP_BASE } +/** Array initializer of OTP peripheral base pointers */ +#define OTP_BASE_PTRS { OTP } + +/*! + * @} + */ /* end of group OTP_Peripheral_Access_Layer */ + +#endif /* HW_OTP_REGISTERS_H */ diff --git a/platform/devices/MX8QX/Makefile b/platform/devices/MX8QX/Makefile new file mode 100755 index 0000000..4cba83b --- /dev/null +++ b/platform/devices/MX8QX/Makefile @@ -0,0 +1,14 @@ + +objs_mx8 := system_MX8QX.o handlers_MX8QX.o + +ifdef ROM +objs_mx8 += gcc/startup_rom_MX8QX.o +else +objs_mx8 += gcc/startup_MX8QX.o +endif + +OBJS += \ + $(foreach object,$(objs_mx8),$(OUT)/devices/MX8QX/$(object)) + +DIRS += $(OUT)/devices/MX8QX/gcc + diff --git a/platform/devices/MX8QX/fsl_clock.h b/platform/devices/MX8QX/fsl_clock.h new file mode 100755 index 0000000..77719f1 --- /dev/null +++ b/platform/devices/MX8QX/fsl_clock.h @@ -0,0 +1,367 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef HW_CLOCKS_H +#define HW_CLOCKS_H + +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define SC_XTAL32K_FREQ_HZ 32768U +#define SC_XTAL24M_FREQ_HZ 24000000U +#define SC_ROSC_FREQ_HZ 200000000U +#define SC_PLL0_STARTUP_FREQ_HZ 1056000000U + +#define SC_MSLICE_ROOT0_RESET_DIV 1U // 200 MHz / 1 = 200 MHz (CM4, BUS) +#define SC_MSLICE_ROOT1_RESET_DIV 2U // 200 MHz / 2 = 100 MHz (SECO, IPG) +#define SC_MSLICE_ROOT2_RESET_DIV 2U // 200 MHz / 2 = 100 MHz (CAAM) +#define SC_MSLICE_ROOT3_RESET_DIV 1U // 200 MHz / 1 = 200 MHz (MSI) + +#define SC_MSLICE_ROOT0_STARTUP_DIV 4U // 1056 MHz / 4 = 264 MHz (CM4, BUS) +#define SC_MSLICE_ROOT1_STARTUP_DIV 8U // 1056 MHz / 8 = 132 MHz (SECO, IPG) +#define SC_MSLICE_ROOT2_STARTUP_DIV 3U // 1056 MHz / 3 = 352 MHz (CAAM) +#define SC_MSLICE_ROOT3_STARTUP_DIV 5U // 1056 MHz / 5 = 211 MHz (MSI) + +#define SC_MCU_STARTUP_FREQ_HZ (SC_PLL0_STARTUP_FREQ_HZ/SC_MSLICE_ROOT0_STARTUP_DIV) +#define SC_MCU_STARTUP_FREQ_MHZ (SC_MCU_STARTUP_FREQ_HZ/1000000U) +#define SC_MCU_LPM_FREQ_HZ (SC_ROSC_FREQ_HZ/SC_MSLICE_ROOT0_STARTUP_DIV) +#define SC_MCU_LPM_FREQ_MHZ (SC_MCU_LPM_FREQ_HZ/1000000U) +#define SC_SYSTICK_NSEC_TO_TICKS(nsec) ((SC_MCU_STARTUP_FREQ_MHZ * (nsec)) / 1000U) + +#define SC_LPIT_ROOT_FREQ_HZ 24000000U +#define SC_LPIT_ROOT_DIV 3U +#define SC_LPIT_FREQ_HZ (SC_LPIT_ROOT_FREQ_HZ / SC_LPIT_ROOT_DIV) +#define SC_LPIT_MSEC_TO_TICKS(msec) (SC_LPIT_FREQ_HZ * (msec) / 1000U) + +#define SC_BG_SVC_MSEC 10U // Background service interval in msec +#define SC_WDOG_SVC_MSEC 5U // WDOG service interval in msec +#define SC_BG_TIMEOUT_MSEC 100U // Background timeout in msec +#define SC_BG_TIMEOUT (SC_BG_TIMEOUT_MSEC / SC_WDOG_SVC_MSEC) + +/*! @brief Clock ip name array for LPUART. */ + +/* Note: This array should have FSL_FEATURE_SOC_LPUART_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define LPUART_CLOCKS {kCLOCK_LPUART_SC, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/*! @brief Clock ip name array for LPI2C. */ + +/* Note: This array should have FSL_FEATURE_SOC_LPI2C_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define LPI2C_CLOCKS {kCLOCK_LPI2C_SC, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/* Note: This array should have FSL_FEATURE_SOC_IGPIO_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define GPIO_CLOCKS {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/* Note: This array should have FSL_FEATURE_SOC_MU_COUNT entries. + * Unused/unsupported entries are marked as invalid. + */ +#define MU_CLOCKS {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid} + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_NmInvalid = 0U, +} clock_name_t; + +/*! + * @brief Clock source for peripherals that support various clock selections. + */ +typedef enum _clock_ip_src +{ + kCLOCK_SrcInvalid = 0U, +} clock_ip_src_t; + +/*! + * @brief Peripheral clock name difinition used for clock gate, clock source + * and clock divider setting. It is defined as the corresponding register address. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_TCMC_SC = LPCG__SS_SCU__CM4__TCMC_HCLK__BASE, + kCLOCK_MMCAU_SC = LPCG__SS_SCU__CM4__MMCAU_HCLK__BASE, + kCLOCK_TPM_SC = LPCG__SS_SCU__TPM1__IPG_CLK__BASE, + kCLOCK_LPIT_SC = LPCG__SS_SCU__LPIT1__IPG_CLK__BASE, + kCLOCK_LPUART_SC = LPCG__SS_SCU__LPUART1__IPG_CLK__BASE, + kCLOCK_LPI2C_SC = LPCG__SS_SCU__LPI2C1__IPG_CLK__BASE +} clock_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Enable IPG and BAUD clocks */ + volatile uint32_t lpcgVal = (1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN); + + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + + /* Wait for clocks to start */ + uint32_t stopMask = (1UL << LPCG__SS_SCU__IPG_CLK__STOP) | + (1UL << LPCG__SS_SCU__PER_CLK__STOP); + + while ((*((volatile uint32_t *) (uint32_t) name) & stopMask) != 0U) + { + ; /* Intentional empty while */ + } + + /* Perform extra write as workaround for TKT322331 */ + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + } +#endif +} + +/*! + * @brief Enable the hardware clock gating for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableHWCG(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Enable IPG and BAUD clocks */ + uint32_t lpcgVal = (1UL << LPCG__SS_SCU__PER_CLK__HWEN); + + *((volatile uint32_t *) (uint32_t) name) |= lpcgVal; + } +#endif +} + +/*! + * @brief Enable the clock for specific IP using exclusive access. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClockEx(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Use exclusive access to enable IPG and BAUD clocks */ + uint32_t volatile lpcgVal = (1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN); + + do + { + lpcgVal |= __LDREXW((volatile uint32_t *) (uint32_t) name); + } while (__STREXW(lpcgVal, ((volatile uint32_t *) (uint32_t) name)) != 0U); + + /* Wait for clocks to start */ + uint32_t stopMask = (1UL << LPCG__SS_SCU__IPG_CLK__STOP) | + (1UL << LPCG__SS_SCU__PER_CLK__STOP); + + while ((*((volatile uint32_t *) (uint32_t) name) & stopMask) != 0U) + { + ; /* Intentional empty while */ + } + + /* Perform extra write as workaround for TKT322331 */ + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + + } +#endif +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + /* Disable IPG and BAUD clocks */ + uint32_t lpcgVal = 0U; + + *((volatile uint32_t *) (uint32_t) name) = lpcgVal; + } +#endif +} + +/*! + * @brief Enter exclusive attempt to disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline uint32_t CLOCK_DisableClockExEnter(clock_ip_name_t name) +{ +#ifndef SIMU + /* Use exclusive access to disable IPG and BAUD clocks */ + uint32_t lpcgVal = ~((1UL << LPCG__SS_SCU__IPG_CLK__SWEN) | + (1UL << LPCG__SS_SCU__PER_CLK__SWEN)); + + if (name != kCLOCK_IpInvalid) + { + lpcgVal = __LDREXW((volatile uint32_t *) (uint32_t) name); + } + + return lpcgVal; +#else + return 0U; +#endif +} + +/*! + * @brief Leave exclusive attempt to disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClockExLeave(clock_ip_name_t name, + uint32_t lpcgVal) +{ +#ifndef SIMU + if (name != kCLOCK_IpInvalid) + { + (void)__STREXW(lpcgVal, ((volatile uint32_t *) (uint32_t) name)); + } +#endif +} + +/*! + * @brief Check whether the clock is already enabled and configured by + * any other core. + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @return True if clock is already enabled, otherwise false. + */ +static inline bool CLOCK_IsEnabledByOtherCore(clock_ip_name_t name) +{ + return false; +} + +/*! + * @brief Set the clock source for specific IP module. + * + * Set the clock source for specific IP, not all modules need to set the + * clock source, should only use this function for the modules need source + * setting. + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @param src Clock source to set. + */ +static inline void CLOCK_SetIpSrc(clock_ip_name_t name, clock_ip_src_t src) +{ +} + +/*! + * @brief Set the clock source and divider for specific IP module. + * + * Set the clock source and divider for specific IP, not all modules need to + * set the clock source and divider, should only use this function for the + * modules need source and divider setting. + * + * Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]). + * + * @param name Which peripheral to check, see \ref clock_ip_name_t. + * @param src Clock source to set. + * @param divValue The divider value. + * @param fracValue The fraction multiply value. + */ +static inline void CLOCK_SetIpSrcDiv(clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue) +{ +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Gets the clock frequency for a specific IP module. + * + * This function gets the IP module clock frequency based on PCC registers. It is + * only used for the IP modules which could select clock source by PCC[PCS]. + * + * @param name Which peripheral to get, see \ref clock_ip_name_t. + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetIpFreq(clock_ip_name_t name); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* HW_CLOCKS_H */ + +/* EOF */ + diff --git a/platform/devices/MX8QX/handlers_MX8QX.h b/platform/devices/MX8QX/handlers_MX8QX.h new file mode 100755 index 0000000..decc1bf --- /dev/null +++ b/platform/devices/MX8QX/handlers_MX8QX.h @@ -0,0 +1,103 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright 2018-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * Header for handlers. + */ + +#ifndef HANDLERS_H +#define HANDLERS_H + +/* Includes */ + +/* Defines */ + +/* Types */ + +/* Functions */ + +void sc_handlers_init(void); +void DefaultISR(void); +void NMI_IRQHandler(uint32_t *sp); +void MCM_IRQHandler(uint32_t *sp); +void DebugWake_IRQHandler(void); +void SWI_IRQHandler(void); +void SWI_DQS2DQ_Handler(void); +void LPIT_SCU_IRQHandler(uint32_t *sp); +void DSC_SCU_IRQHandler(void); +void DSC_LSIO_IRQHandler(void); +void DSC_CM4_0_IRQHandler(void); +void DSC_CA35_IRQHandler(void); +void DSC_DRC_0_IRQHandler(void); +void DSC_GPU_0_IRQHandler(void); +void DSC_VPU_IRQHandler(void); +void DSC_ADMA_IRQHandler(void); +void IOMUX_CommonHandler(uint8_t irq, uint8_t ring, uint8_t group); +void IOMUX0_IRQHandler(void); +void IOMUX1_IRQHandler(void); +void IOMUX2_IRQHandler(void); +void IOMUX3_IRQHandler(void); +void IOMUX4_IRQHandler(void); +void IOMUX5_IRQHandler(void); +void IOMUX6_IRQHandler(void); +void IOMUX7_IRQHandler(void); +void IOMUX8_IRQHandler(void); +void IOMUX9_IRQHandler(void); +void IOMUX10_IRQHandler(void); +void IOMUX11_IRQHandler(void); +void IOMUX12_IRQHandler(void); +void SYSCTR_CMP0_IRQHandler(void); +void SYSCTR_CMP1_IRQHandler(void); +void SNVS_Functional_IRQHandler(void); +void ss_earlywdog_handler_sc(void); +void ss_csreq_handler_a35(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_mcu(uint32_t idx, uint32_t cpwrupreq); +void ss_csreq_handler_dbgpwrup(uint32_t idx, uint32_t cpwrupreq); +#if HAS_SS_AP_2 +sc_bool_t ss_dbg_status_a35(sc_dsc_t dsc); +void ss_dbg_resume_a35(sc_dsc_t dsc); +#endif + +/* Global Variables */ + +extern uint32_t gLPITcnt; + +#endif /* #if !defined(HANDLERS_H) */ + diff --git a/platform/devices/MX8QX/linker/gcc/MX8QX_flash.ld b/platform/devices/MX8QX/linker/gcc/MX8QX_flash.ld new file mode 100755 index 0000000..ea63e74 --- /dev/null +++ b/platform/devices/MX8QX/linker/gcc/MX8QX_flash.ld @@ -0,0 +1,61 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Specify the memory areas */ +MEMORY +{ + m_rom (RX) : ORIGIN = 0x00000000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* Vector table and code to emulate ROM */ + .rom : + { + . = ALIGN(8); + KEEP(*(.rom)) + . = ALIGN(0x80); + } > m_rom +} + diff --git a/platform/devices/MX8QX/linker/gcc/MX8QX_overlay.t.ld b/platform/devices/MX8QX/linker/gcc/MX8QX_overlay.t.ld new file mode 100755 index 0000000..7b1d0b1 --- /dev/null +++ b/platform/devices/MX8QX/linker/gcc/MX8QX_overlay.t.ld @@ -0,0 +1,312 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/* DO NOT EDIT - This file auto generated by $cmd */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_ocram (RX) : ORIGIN = 0x00100000, LENGTH = 0x00040000 + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002ED80 + m_ovl (RX) : ORIGIN = 0x2000F000, LENGTH = 0x00000FF0 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + OVERLAY : NOCROSSREFS + { +<% $counter = 0 %> +<%OV_LIST%> + .test$counter { */test_$tests[$counter].o(.text*) */test_$tests[$counter].o(.rodata*) } +<% $counter++; return 'OV_LIST' if $counter < scalar(@tests); '' %> + } > m_ovl AT> m_ocram + + .test_ovly_table : + { + . = ALIGN(4); + __ovly_table = .; + LONG(0x34982933); LONG(0); LONG($last); +<% $counter = 0 %> +<%TB_LIST%> + LONG(ABSOLUTE(ADDR(.test$counter))); LONG(SIZEOF(.test$counter)); LONG(LOADADDR(.test$counter)); +<% $counter++; return 'TB_LIST' if $counter < scalar(@tests); '' %> + LONG(0); LONG(0); LONG(0); + } > m_ocram + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8QX/linker/gcc/MX8QX_tcm.ld b/platform/devices/MX8QX/linker/gcc/MX8QX_tcm.ld new file mode 100755 index 0000000..55984d3 --- /dev/null +++ b/platform/devices/MX8QX/linker/gcc/MX8QX_tcm.ld @@ -0,0 +1,288 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x1000; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x1000; +EMUL_SIZE = DEFINED(__emul_size__) ? __emul_size__ : 0x0010; +DEBUG_DATA_SIZE = DEFINED(__debug_data_size__) ? __debug_data_size__ : 0x0040; + +/* GUARD_LOG2 defines the power-of-2 size of the MPU guard region + * used for runtime detection of stack/heap overflow. Default + * value is 11 => guard region = 2^11 = 2K + */ +GUARD_LOG2 = DEFINED(__guard_log2__) ? __guard_log2__ : 11; +GUARD_SIZE = (1 << GUARD_LOG2); + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x1ffe0000, LENGTH = 0x00000280 + m_text (RX) : ORIGIN = 0x1ffe0280, LENGTH = 0x0002fd70 + m_emul (RX) : ORIGIN = 0x2000fff0, LENGTH = 0x00000010 + m_data (RW) : ORIGIN = 0x20010000, LENGTH = 0x0000cfc0 + m_debug (RW) : ORIGIN = 0x2001cfc0, LENGTH = 0x00000040 + m_data_2 (RW) : ORIGIN = 0x2001d000, LENGTH = 0x00002800 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(0x80); + __VECTOR_TABLE = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into TCM */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + /* Constants/strings linked to end of image and are allowed to spill over + from TCML to TCMU without access penalty (DCODE bus access). Alignment + faults must be enabled to ensure an access across the boundary is detected + not occur */ + .rodata : + { + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(64); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .emul : + { + __EMUL = .; + . += EMUL_SIZE; + } > m_emul + + /* Ensure .data 64-byte aligned for optimized copy */ + .data : AT( LOADADDR(.fini_array) + SIZEOF(.fini_array)) + { + . = ALIGN(64); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(64); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + copy_start = LOADADDR(.interrupts); + copy_end = copy_start; + copy_dest = copy_start; + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + + /* Uninitialized data section with NO zeroization + * + * Note: section attribute NOLOAD prevents the linker from allocating space in + * the loadable image (i.e. section type marked NOBITS instead of PROGBITS) + */ + .noinit (NOLOAD) : + { + . = ALIGN(64); + __NoInitBase = .; + *(.noinit) + *(.noinit*) + . = ALIGN(64); + __NoInitEnd = .; + } > m_data + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(64); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; + __END_BSS = .; + __FREE_TCM_START = .; + } > m_data + + .debug_data : + { + __FREE_TCM_END = .; + __DEBUG_DATA = .; + . += DEBUG_DATA_SIZE; + } > m_debug + + .heap : + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + . = ALIGN(64); + } > m_data_2 + + .guard : + { + . = ALIGN(GUARD_SIZE); + __GuardStart = .; + . += GUARD_SIZE; + __GuardLimit = .; + } > m_data_2 + + __GuardSizeMpuField = (GUARD_LOG2 - 1) << 1; + + .stack : + { + . = ALIGN(64); + . += STACK_SIZE; + . = ALIGN(64); + } > m_data_2 + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + __FREE_TCM_BYTES = __FREE_TCM_END - __FREE_TCM_START; + __FREE_TCM_WORDS = __FREE_TCM_BYTES >> 2; + + /DISCARD/ : { *(.interp) } + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __GuardLimit, "region m_data_2 overflowed with stack and heap") + ASSERT(__DATA_END < __EMUL, "region m_text overflowed with initialized data") +} + diff --git a/platform/devices/MX8QX/system_MX8QX.h b/platform/devices/MX8QX/system_MX8QX.h new file mode 100755 index 0000000..5534314 --- /dev/null +++ b/platform/devices/MX8QX/system_MX8QX.h @@ -0,0 +1,198 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*! + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef SYSTEM_H +#define SYSTEM_H /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defines */ + +/* Reset requires 32 cycles of xtal24M to propagate. SysTick clocked from + ROSC will be used for delay. + + ROSC @ 200 MHz +*/ +#define RESET_WAIT_ROSC_CYCLES (((SC_ROSC_FREQ_HZ / SC_XTAL24M_FREQ_HZ) + 1U) * 32U) + +/* Define delay for top-level top-level SSI power switch chains. + */ +#define SYSCTR_NSEC_TO_CYCLES(nsec) ((((nsec) * SC_MCU_STARTUP_FREQ_MHZ) + 999U) / 1000U) +#define SSI_CHAIN_LF_CYCLES (SYSCTR_NSEC_TO_CYCLES(500U)) +#define SSI_CHAIN_HF_CYCLES (SYSCTR_NSEC_TO_CYCLES(2000U)) + +/* OSC24M lock spec unknown, use conservative 4ms */ +#define OSC24M_WAIT_ROSC_CYCLES (4*SC_ROSC_FREQ_HZ/1000U) + +/* Address for environment event trigger */ +#define SC_ENV_TRIG_ADDR 0x2000FFF0U + +/* Query to determine if firmware loaded by ROM */ +#ifndef SIMU +#define SCFW_LOADED_BY_ROM ((DSC_SC->GPR_CTRL[0].RW & BIT(31))) +#else +#define SCFW_LOADED_BY_ROM (0x80000000U) +#endif + +/* Query to determine boot mode + * BOOT_MODE[7:0] tied to DSC.GPR_STAT[0] bits [23:16] + */ +#define SC_BOOT_MODE ((DSC_SC->GPR_STAT[0].RW & 0x00FF0000U) >> 16U) + +/* BOOT_MODE = Infinite loop mode = bXXXX1110 = 0x0E */ +#define SC_BOOT_MODE_INF_LOOP 0x0EU + +/* Margin to wake system early from LLS for WDOG servicing */ +#define SC_WAKE_MARGIN_MSEC 5U + +#ifdef DEBUG +extern uint32_t __DEBUG_DATA[]; +#define SCFW_DBG_READY (__DEBUG_DATA[0]) +#define SCFW_DBG_SKIPS (__DEBUG_DATA[1]) +#define SCFW_DBG_DUMP_PTR (&(__DEBUG_DATA[2])) +#define SCFW_DBG_DUMP_R0 (__DEBUG_DATA[2]) +#define SCFW_DBG_DUMP_R1 (__DEBUG_DATA[3]) +#define SCFW_DBG_DUMP_R2 (__DEBUG_DATA[4]) +#define SCFW_DBG_DUMP_R3 (__DEBUG_DATA[5]) +#define SCFW_DBG_DUMP_R12 (__DEBUG_DATA[6]) +#define SCFW_DBG_DUMP_LR (__DEBUG_DATA[7]) +#define SCFW_DBG_DUMP_PC (__DEBUG_DATA[8]) +#define SCFW_DBG_DUMP_PSR (__DEBUG_DATA[9]) +#define SCFW_DBG_SCTR_TICKS (__DEBUG_DATA[10]) +#define SCFW_DBG_RSVD0 (__DEBUG_DATA[11]) +#define SCFW_DBG_TX_PTR (&__DEBUG_DATA[12]) +#define SCFW_DBG_RX_PTR (&__DEBUG_DATA[13]) +#endif + +#define SC_ENV_TRIG_DUMP 0xc0ffee10U //!< Start dump +#define SC_ENV_TRIG_KILL 0xc0ffee20U //!< Kill execution + +/* Types */ + +/*! + * This type is used to indicate the trigger event. + */ +typedef uint32_t sc_env_trig_event_t; + +/** + * @brief Generate environment event trigger + * + */ +void SystemEventTrigger (sc_env_trig_event_t event); + +/** + * @brief Enter firmware critical section. + * + */ +void SystemEnterCS(void); + +/** + * @brief Exit firmware critical section. + * + */ +void SystemExitCS(void); + +/** + * @brief Get active exception. + * + */ +uint32_t SystemGetActiveException(void); + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit(void); + +void SystemInitPostCRT(void); + +/** + * @brief Prepares to enter Low-Power Mode (LPM) + * + */ +void SystemPrepareLPM(void); + +void SystemEnterLPM(void); + +/** + * @brief Delays the specified number of usec + * + */ +void SystemTimeDelay(uint32_t usec); + +void SystemDebugWaitAttach(void); + +void CommonFault_Handler(uint32_t *sp); + +void SystemDebugHalt(void); + +void SystemExit(void); + +void HardFault_Handler(uint32_t *sp); + +void MemManage_Handler(uint32_t *sp); + +void BusFault_Handler(uint32_t *sp); + +void UsageFault_Handler(uint32_t *sp); + +void SystemDebugResume(void); + +#if defined(DEBUG) || defined(HAS_TEST) +uint32_t SystemMemoryProbe(void *addr, void *val, uint8_t width); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* #if !defined(SYSTEM_H_) */ diff --git a/platform/devices/Makefile b/platform/devices/Makefile new file mode 100755 index 0000000..b6b824f --- /dev/null +++ b/platform/devices/Makefile @@ -0,0 +1,20 @@ + +ifeq ($(HW), REAL) + objs_devices := startup.o memops.o memops_test.o memcpy-armv7m.o aeabi_memset-thumb2.o +else + objs_devices := stub.o +endif + +OBJS += \ + $(foreach object,$(objs_devices),$(OUT)/devices/$(object)) + +DIRS += $(OUT)/devices + +ifeq ($(HW), REAL) + + SUBCOMPS := $(DEVICE) + + include $(foreach subcomp,$(SUBCOMPS),$(rootdir)/$(SRC)/devices/$(subcomp)/Makefile) + +endif + diff --git a/platform/devices/fsl_device_registers.h b/platform/devices/fsl_device_registers.h new file mode 100755 index 0000000..86863aa --- /dev/null +++ b/platform/devices/fsl_device_registers.h @@ -0,0 +1,191 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef FSL_DEVICE_REGISTERS_H +#define FSL_DEVICE_REGISTERS_H + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if defined(CPU_MX8QM) + + #define MX8_SERIES + + /* CPU specific feature definitions */ + #include "MX8QM/MX8QM_features.h" + /* CMSIS-style register definitions */ + #include "MX8QM/MX8QM.h" + #include "MX8/MX8_dsc.h" + #include "MX8/MX8_dsc_ai.h" + #include "MX8/MX8_csr.h" + #include "MX8/MX8_xrdc2.h" + #include "MX8/MX8_mu.h" + #include "MX8/MX8_lmem_cache.h" + #include "MX8/MX8_lpuart.h" + #include "MX8/MX8_lpit.h" + #include "MX8/MX8_sysctr.h" + #include "MX8/MX8_wdog.h" + #include "MX8/MX8_pad.h" + #include "MX8/MX8_lpcg.h" + #include "MX8/MX8_lpi2c.h" + #include "MX8/MX8_gpio.h" + #include "MX8/MX8_igpio.h" + #include "MX8/MX8_mcm.h" + #include "MX8/MX8_dma3.h" + #include "MX8/MX8_snvs.h" + #include "MX8/MX8_asmc.h" + #include "MX8/MX8_lpc.h" + #include "MX8QM/MX8QM_otp.h" + #include "MX8/MX8_stc.h" + #include "MX8/MX8_rep2.h" + #include "MX8/MX8_mbist.h" + #include "MX8/MX8_isi.h" + #include "MX8/MX8_adm.h" + #include "MX8/MX8_jpgdec.h" + #include "MX8/MX8_jpgenc.h" + #include "MX8/MX8_drc.h" + #include "MX8/MX8_ddrc.h" + #include "MX8/MX8_ddr_phy.h" + #include "MX8/MX8_drc_perf.h" + #include "MX8/MX8_flexspi.h" + /* Register access macros */ + #include "MX8/fsl_bitaccess.h" + #include "MX8QM/MX8QM_fuse_map.h" + +#elif defined(CPU_MX8QX) + + #define MX8_SERIES + + /* CPU specific feature definitions */ + #include "MX8QX/MX8QX_features.h" + /* CMSIS-style register definitions */ + #include "MX8QX/MX8QX.h" + #include "MX8/MX8_dsc.h" + #include "MX8/MX8_dsc_ai.h" + #include "MX8/MX8_csr.h" + #include "MX8/MX8_xrdc2.h" + #include "MX8/MX8_mu.h" + #include "MX8/MX8_lmem_cache.h" + #include "MX8/MX8_lpuart.h" + #include "MX8/MX8_lpit.h" + #include "MX8/MX8_sysctr.h" + #include "MX8/MX8_wdog.h" + #include "MX8/MX8_pad.h" + #include "MX8/MX8_lpcg.h" + #include "MX8/MX8_lpi2c.h" + #include "MX8/MX8_gpio.h" + #include "MX8/MX8_igpio.h" + #include "MX8/MX8_mcm.h" + #include "MX8/MX8_dma3.h" + #include "MX8/MX8_snvs.h" + #include "MX8/MX8_asmc.h" + #include "MX8/MX8_lpc.h" + #include "MX8QX/MX8QX_otp.h" + #include "MX8/MX8_stc.h" + #include "MX8/MX8_rep2.h" + #include "MX8/MX8_mbist.h" + #include "MX8/MX8_isi.h" + #include "MX8/MX8_adm.h" + #include "MX8/MX8_jpgdec.h" + #include "MX8/MX8_jpgenc.h" + #include "MX8/MX8_drc.h" + #include "MX8/MX8_ddrc.h" + #include "MX8/MX8_ddr_phy.h" + #include "MX8/MX8_drc_perf.h" + #include "MX8/MX8_flexspi.h" + /* Register access macros */ + #include "MX8/fsl_bitaccess.h" + #include "MX8QX/MX8QX_fuse_map.h" + +#elif defined(CPU_MX8DXL) + + #define MX8_SERIES + + /* CPU specific feature definitions */ + #include "MX8DXL/MX8DXL_features.h" + /* CMSIS-style register definitions */ + #include "MX8DXL/MX8DXL.h" + #include "MX8/MX8_dsc.h" + #include "MX8/MX8_dsc_ai.h" + #include "MX8/MX8_csr.h" + #include "MX8/MX8_ecsr_reset.h" + #include "MX8/MX8_xrdc2.h" + #include "MX8/MX8_mu.h" + #include "MX8/MX8_lmem_cache.h" + #include "MX8/MX8_lpuart.h" + #include "MX8/MX8_lpit.h" + #include "MX8/MX8_sysctr.h" + #include "MX8/MX8_wdog.h" + #include "MX8/MX8_pad.h" + #include "MX8/MX8_lpcg.h" + #include "MX8/MX8_lpi2c.h" + #include "MX8/MX8_gpio.h" + #include "MX8/MX8_igpio.h" + #include "MX8/MX8_mcm.h" + #include "MX8/MX8_dma3.h" + #include "MX8/MX8_snvs.h" + #include "MX8/MX8_asmc.h" + #include "MX8/MX8_lpc.h" + #include "MX8DXL/MX8DXL_otp.h" + #include "MX8/MX8_rep2.h" + #include "MX8/MX8_mbist.h" + #include "MX8/MX8_isi.h" + #include "MX8/MX8_adm.h" + #include "MX8/MX8_drc.h" + #include "MX8/MX8_ddrc.h" + #include "MX8/MX8_ddr_phy.h" + #include "MX8/MX8_drc_perf.h" + #include "MX8/MX8_flexspi.h" + /* Register access macros */ + #include "MX8/fsl_bitaccess.h" + #include "MX8DXL/MX8DXL_fuse_map.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* FSL_DEVICE_REGISTERS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/devices/memops.h b/platform/devices/memops.h new file mode 100644 index 0000000..9f48fad --- /dev/null +++ b/platform/devices/memops.h @@ -0,0 +1,52 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** Memory operations for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** Copyright 2017-2018 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef MEMOPS_H +#define MEMOPS_H + +void memset_unrolled_8(uint32_t *pMem, uint32_t *pEnd, uint32_t val); +void memset_unrolled_28(uint32_t *pMem, uint32_t *pEnd, uint32_t val); + +#endif /* MEMOPS_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/platform/devices/startup.h b/platform/devices/startup.h new file mode 100755 index 0000000..f2e5b10 --- /dev/null +++ b/platform/devices/startup.h @@ -0,0 +1,61 @@ +/* +** ################################################################### +** Processors: MX8 +** +** Compilers: GNU C Compiler +** +** Abstract: +** CMSIS Peripheral Access Layer for MX8 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +#ifndef STARTUP_H +#define STARTUP_H + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Make necessary initializations for RAM. + * + * - Copy initialized data from ROM to RAM. + * - Clear the zero-initialized data section. + * - Copy the vector table from ROM to RAM. This could be an option. + */ +void init_data_bss(void); + +#endif /* STARTUP_H*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/platform/drivers/analog/Makefile b/platform/drivers/analog/Makefile new file mode 100755 index 0000000..33a1b0b --- /dev/null +++ b/platform/drivers/analog/Makefile @@ -0,0 +1,9 @@ + +OBJS += $(OUT)/drivers/analog/fsl_analog.o +OBJS += $(OUT)/drivers/analog/fsl_analog_refgen.o +OBJS += $(OUT)/drivers/analog/fsl_analog_bias.o +OBJS += $(OUT)/drivers/analog/fsl_analog_pll.o +OBJS += $(OUT)/drivers/analog/fsl_vdetect.o + +DIRS += $(OUT)/drivers/analog + diff --git a/platform/drivers/analog/fsl_analog.h b/platform/drivers/analog/fsl_analog.h new file mode 100755 index 0000000..d684f71 --- /dev/null +++ b/platform/drivers/analog/fsl_analog.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_ANALOG_H +#define DRV_ANALOG_H + +#include "fsl_common.h" +#include "main/scfw.h" +#include "main/main.h" +#include "main/soc.h" + +#define MAX_DRV_CUR 3U +#define MAX_TRIM 7U +#define MAX_CLKIN 3U + +#define SE_XTAL_24MHZ 0x1U +#define DIFF_XTAL_24MHZ 0x2U + +typedef struct +{ + uint32_t regl_lv; + uint32_t regh_lv; + uint32_t cl_tune_lv; +} xtalosc24_config_t; + +typedef struct +{ + uint32_t drv0, drv1; +} root_config_t; + +typedef struct +{ + uint32_t drv0, drv1; + uint32_t drv_in; + uint32_t term_res; +} rptr_config_t; + +typedef struct +{ + uint32_t drv_in; + uint32_t term_res, sqrup; +} term_config_t; + +#ifndef NO_REFGEN +#ifdef AUTOCAL +uint32_t RefgenCalibrateAuto(uint8_t base_idx); +#endif +void RefgenSetup(uint8_t base_idx, uint32_t refgen, sc_bool_t anamix); +sc_bool_t RefgenEnabled(uint8_t base_idx, uint8_t tog); +sc_bool_t RefgenTrimmed(uint8_t base_idx, uint8_t tog); +void RefgenSetEn(uint8_t base_idx, uint8_t tog, sc_bool_t enable); +#endif +void BandgapSetEn(uint8_t base_idx, uint8_t tog, sc_bool_t enable); +void BandgapSetTrim(uint8_t base_idx, uint8_t tog, uint32_t trim_val); +void BandgapSelfBiasOff(uint8_t base_idx, uint8_t tog); +sc_bool_t PhyLdoEnabled(uint8_t base_idx, uint8_t tog); +void PhyLdoSetEn(uint8_t base_idx,uint8_t tog,uint32_t target,sc_bool_t enable); +sc_bool_t HPPllRegEnabled(uint8_t base_idx,uint8_t tog); +void HPPllRegSetEn(uint8_t base_idx,uint8_t tog, uint32_t target, sc_bool_t enable); +sc_bool_t AVPllRegEnabled(uint8_t base_idx, uint8_t tog); +void AVPllRegSetEn(uint8_t base_idx,uint8_t tog,uint32_t target, sc_bool_t enable); + +/*! + * Convert celsius to temp sensor value. + * + * @param[in] base_idx resource with sensor + * @param[in] celsius whole part of temp + * @param[in] tenths fractional part of temp + * @param[out] val value to return + */ +void ANA_Temp2Val(uint8_t base_idx, int16_t celsius, int8_t tenths, + uint32_t *val); +/*! + * Convert temp sensor value to celsius. + * + * @param[in] dsc resource with sensor + * @param[in] val value to convert + * @param[out] celsius whole part of temp to return + * @param[out] tenths fractional part of temp to return + */ +void ANA_Val2Temp(uint8_t base_idx, uint32_t val, int16_t *celsius, + int8_t *tenths); + +void ANA_BIAS_Calc(uint8_t bias_encoded, uint8_t *asym, uint8_t *vctrl); +sc_bool_t ANA_BIAS_Enabled(uint8_t base_idx, uint8_t bias_mask); +void ANA_BIAS_SetupEn(uint8_t base_idx, uint8_t bias_mask, sc_bool_t enable, + uint32_t delay); +void ANA_BIAS_ClearRefVCtrl(uint8_t base_idx); +void ANA_BIAS_SetRefVCtrl(uint8_t base_idx, uint8_t vctrl); + +/* Diff Clock functions */ +void ANA_XtalOsc24Init (uint32_t regl_lv, uint32_t regh_lv, uint32_t cl_tune_lv); +void ANA_DiffClkRootInit (uint32_t drv0, uint32_t drv1); +void ANA_DiffClkRptrInit (uint32_t drv0, uint32_t drv1, uint32_t drv_in, + uint32_t term_res); +void ANA_DiffClkTermInit (uint32_t drv_in, uint32_t sqrup, uint32_t term_res); +void ANA_XtalOsc24Setup (uint8_t base_idx, uint8_t tog, sc_bool_t enable); +void ANA_DiffClkRootSetup (uint8_t base_idx, uint8_t tog, uint8_t clkin, + sc_bool_t mux_en, sc_bool_t mux_en_diff, sc_bool_t enable); +void ANA_DiffClkRptrSetup (uint8_t base_idx, uint8_t tog, sc_bool_t standalone, + uint32_t reg_trim, sc_bool_t enable); +void ANA_DiffClkTermSetup (uint8_t base_idx, uint8_t tog, sc_bool_t enable); + +/* vdetect functions*/ +void ANA_vdetect_init(sc_dsc_t dsc, uint8_t status_sel); +sc_err_t ANA_vdetect_find_dly(sc_dsc_t dsc, uint8_t *adly, uint8_t *fdly); + +#endif diff --git a/platform/drivers/common/fsl_common.h b/platform/drivers/common/fsl_common.h new file mode 100755 index 0000000..8c21e52 --- /dev/null +++ b/platform/drivers/common/fsl_common.h @@ -0,0 +1,669 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/** @{ */ +/*! @brief common driver version 2.2.4. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) +/** @} */ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/** @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/** @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/** @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/** @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if(defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__XCC__)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes))) +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/** @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/** @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/** @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/** @} */ + +#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) +void DefaultISR(void); +#endif +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + + /*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delay_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ + void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/platform/drivers/csr/Makefile b/platform/drivers/csr/Makefile new file mode 100755 index 0000000..fc60ec3 --- /dev/null +++ b/platform/drivers/csr/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/csr/fsl_csr.o + +DIRS += $(OUT)/drivers/csr + diff --git a/platform/drivers/csr/fsl_csr.h b/platform/drivers/csr/fsl_csr.h new file mode 100755 index 0000000..6ecbb15 --- /dev/null +++ b/platform/drivers/csr/fsl_csr.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_CSR_H +#define DRV_CSR_H + +/*! + * @addtogroup csr_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "fsl_device_registers.h" + +/* Defines */ + +#if (defined(FSL_FEATURE_CSR_HAS_CSR) && FSL_FEATURE_CSR_HAS_CSR) +/*! + * This define is used to access CSR registers. + */ +#define CSR_BASE_ADDR(X) ((CSR_Type*) (((sc_saddr_t) DSC_BASE_ADDR(X)) \ + + 0x9000U)) +#endif + +#if (defined(FSL_FEATURE_CSR_HAS_CSR2) && FSL_FEATURE_CSR_HAS_CSR2) +/*! + * This define is used to access CSR2 registers. + */ +#define CSR2_BASE_ADDR(X) ((CSR2_Type*) (((sc_saddr_t) DSC_BASE_ADDR(X)) \ + + 0xF000U)) + +#endif + +#if (defined(FSL_FEATURE_CSR_HAS_CSR3) && FSL_FEATURE_CSR_HAS_CSR3) +/*! + * This define is used to access CSR3 registers. + */ +#define CSR3_BASE_ADDR(X) ((CSR2_Type*) (((sc_saddr_t) DSC_BASE_ADDR(X)) \ + + 0x9000U)) +#endif + +/* Types */ + +/* Functions */ + +#if (defined(FSL_FEATURE_CSR_HAS_CSR) && FSL_FEATURE_CSR_HAS_CSR) +void CSR_SetCSR(sc_dsc_t dsc, uint32_t csr_num, uint32_t csr_val, + sc_bool_t enable); +uint32_t CSR_GetCSR(sc_dsc_t dsc, uint32_t csr_num); +#endif + +#if (defined(FSL_FEATURE_CSR_HAS_CSR2) && FSL_FEATURE_CSR_HAS_CSR2) +void CSR_SetCSR2(sc_dsc_t dsc, uint32_t csr_num, uint32_t csr_val, + sc_bool_t enable); +uint32_t CSR_GetCSR2(sc_dsc_t dsc, uint32_t csr_num); +#endif + +#if (defined(FSL_FEATURE_CSR_HAS_CSR3) && FSL_FEATURE_CSR_HAS_CSR3) +void CSR_SetCSR3(sc_dsc_t dsc, uint32_t csr_num, uint32_t csr_val, + sc_bool_t enable); +uint32_t CSR_GetCSR3(sc_dsc_t dsc, uint32_t csr_num); +#endif + +#if (defined(FSL_FEATURE_CSR_HAS_LPCG) && FSL_FEATURE_CSR_HAS_LPCG) +void CSR_SetLPPG(sc_dsc_t dsc, uint32_t pg_num, uint32_t pg_val, + sc_bool_t enable); +uint32_t CSR_GetLPPG(sc_dsc_t dsc, uint32_t pg_num); +#endif + +#endif /* DRV_CSR_H */ + +/** @} */ + diff --git a/platform/drivers/drc/Makefile b/platform/drivers/drc/Makefile new file mode 100755 index 0000000..853fc87 --- /dev/null +++ b/platform/drivers/drc/Makefile @@ -0,0 +1,10 @@ + +OBJS += $(OUT)/drivers/drc/fsl_drc.o +OBJS += $(OUT)/drivers/drc/fsl_drc_dqs2dq.o +OBJS += $(OUT)/drivers/drc/fsl_drc_cbt.o +OBJS += $(OUT)/drivers/drc/fsl_drc_derate.o +OBJS += $(OUT)/drivers/drc/fsl_drc_rdbi_deskew.o +OBJS += $(OUT)/drivers/drc/fsl_drc_dram_vref.o + +DIRS += $(OUT)/drivers/drc + diff --git a/platform/drivers/drc/fsl_drc.h b/platform/drivers/drc/fsl_drc.h new file mode 100755 index 0000000..8afcf27 --- /dev/null +++ b/platform/drivers/drc/fsl_drc.h @@ -0,0 +1,59 @@ +/* + * Copyright 2018-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DRC_H +#define DRV_DRC_H + +/*! + * @addtogroup drc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ +#include "fsl_device_registers.h" + +/* Defines */ + +/* Types */ + +/* Externs */ + +/* Functions */ + +void ddr_enter_retention(uint32_t total_drc_num, ddrc drc_inst[], ddr_phy drc_phy_inst[]); +void ddr_exit_retention(uint32_t total_drc_num, const ddrc drc_inst[], const ddr_phy drc_phy_inst[]); +uint8_t ddrc_mrr(uint32_t ddr_num, uint32_t rank, uint32_t MR_addr); +void ddrc_mrw(uint32_t ddr_num, uint32_t rank, uint32_t MR_addr, uint32_t MR_data); + +#endif /* DRV_DRC_H */ + +/** @} */ + diff --git a/platform/drivers/drc/fsl_drc_cbt.h b/platform/drivers/drc/fsl_drc_cbt.h new file mode 100755 index 0000000..6879f39 --- /dev/null +++ b/platform/drivers/drc/fsl_drc_cbt.h @@ -0,0 +1,62 @@ +/* + * Copyright 2018-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DRC_CBT_H +#define DRV_DRC_CBT_H + +/*! + * @addtogroup drc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +/* Defines */ + +/* Types */ + +/* Externs */ + +/* Functions */ + +/*! + * This function performs DDR command bus training. + * + * @param[in] phy_ptr0 initial value of PTR0 + * @param[in] phy_ptr1 initial value of PTR1 + * @param[in] total_num_drc number of DDR controllers used + */ +void run_cbt(uint32_t phy_ptr0, uint32_t phy_ptr1, uint32_t total_num_drc); + +#endif /* DRV_DRC_CBT_H */ + +/** @} */ + diff --git a/platform/drivers/drc/fsl_drc_derate.h b/platform/drivers/drc/fsl_drc_derate.h new file mode 100755 index 0000000..1096da0 --- /dev/null +++ b/platform/drivers/drc/fsl_drc_derate.h @@ -0,0 +1,72 @@ +/* + * Copyright 2019-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DRC_DERATE_H +#define DRV_DRC_DERATE_H + +/*! + * @addtogroup drc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "fsl_device_registers.h" + +/* Defines */ + +/* Types */ + +/* Externs */ + +/* Functions */ + +/*! + * This function initializes the DDR derate mechanism. + * + * @param[in] total_num_drc number of DDR controllers used + */ +void ddrc_lpddr4_derate_init(uint32_t total_num_drc); + +/*! + * This function performs periodic DDR derate training. + * + * @param[in] total_num_drc number of DDR controllers used + * + * @return Returns SC_TRUE if timer is suppose to continue polling, + * otherwise SC_FALSE. + */ +sc_bool_t ddrc_lpddr4_derate_periodic(uint32_t total_num_drc); + +#endif /* DRV_DRC_DERATE_H */ + +/** @} */ + diff --git a/platform/drivers/drc/fsl_drc_dqs2dq.h b/platform/drivers/drc/fsl_drc_dqs2dq.h new file mode 100755 index 0000000..61e6d69 --- /dev/null +++ b/platform/drivers/drc/fsl_drc_dqs2dq.h @@ -0,0 +1,58 @@ +/* + * Copyright 2018-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DRC_DQS2DQ_H +#define DRV_DRC_DQS2DQ_H + +/*! + * @addtogroup drc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "fsl_device_registers.h" + +/* Defines */ + +/* Types */ + +/* Externs */ + +/* Functions */ + +void dqs2dq_init(uint32_t num); +void dqs2dq_periodic(void); + +#endif /* DRV_DRC_DQS2DQ_H */ + +/** @} */ + diff --git a/platform/drivers/drc/fsl_drc_dram_vref.h b/platform/drivers/drc/fsl_drc_dram_vref.h new file mode 100755 index 0000000..c7c2100 --- /dev/null +++ b/platform/drivers/drc/fsl_drc_dram_vref.h @@ -0,0 +1,71 @@ +/* + * Copyright 2018-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DRC_DRAM_VREF_H +#define DRV_DRC_DRAM_VREF_H + +/*! + * @addtogroup drc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +/* Defines */ + +/* Types */ + +/* Externs */ + +/* Functions */ + +/*! + * This function performs DDR VREF training via software. + * + * @param[in] phy_ptr0 initial value of PTR0 + * @param[in] phy_ptr1 initial value of PTR1 + * @param[in] total_num_drc number of DDR controllers used + */ +void DRAM_VREF_training_sw(uint32_t ddr_num); + +/*! + * This function performs DDR VREF training via hardware. + * + * @param[in] phy_ptr0 initial value of PTR0 + * @param[in] phy_ptr1 initial value of PTR1 + * @param[in] total_num_drc number of DDR controllers used + */ +void DRAM_VREF_training_hw(uint32_t ddr_num); + +#endif /* DRV_DRC_DRAM_VREF_H */ + +/** @} */ + diff --git a/platform/drivers/drc/fsl_drc_rdbi_deskew.h b/platform/drivers/drc/fsl_drc_rdbi_deskew.h new file mode 100755 index 0000000..1fd56b6 --- /dev/null +++ b/platform/drivers/drc/fsl_drc_rdbi_deskew.h @@ -0,0 +1,60 @@ +/* + * Copyright 2019-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DRC_RDBI_DESKEW_H +#define DRV_DRC_RDBI_DESKEW_H + +/*! + * @addtogroup drc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +/* Defines */ + +/* Types */ + +/* Externs */ + +/* Functions */ + +/*! + * This function performs DDR deskew training. + * + * @param[in] ddr_num index of DDR controller (0 or 1) + */ +void RDBI_bit_deskew(uint32_t ddr_num); + +#endif /* DRV_DRC_RDBI_DESKEW_H */ + +/** @} */ + diff --git a/platform/drivers/dsc/Makefile b/platform/drivers/dsc/Makefile new file mode 100755 index 0000000..e905f1c --- /dev/null +++ b/platform/drivers/dsc/Makefile @@ -0,0 +1,7 @@ + +OBJS += $(OUT)/drivers/dsc/fsl_dsc.o +OBJS += $(OUT)/drivers/dsc/fsl_dsc_ai.o + + +DIRS += $(OUT)/drivers/dsc + diff --git a/platform/drivers/dsc/fsl_dsc.h b/platform/drivers/dsc/fsl_dsc.h new file mode 100755 index 0000000..933c576 --- /dev/null +++ b/platform/drivers/dsc/fsl_dsc.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_DSC_H +#define DRV_DSC_H + +/*! + * @addtogroup dsc_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "fsl_device_registers.h" +#include "ss/inf/inf.h" + +/* Defines */ + +#define DSC_SIZE 0x20000U //!< Size of DSC address space + +#define DSC_CLK_TYPE_W 4U //!< Width of a clock type +#define DSC_INDEX_W 6U //!< Width of the index +#define DSC_PDOM_W 3U //!< Width of the power domain type +#define DSC_GPR_W 7U //!< Width of the gpr bit type +#define DSC_PLLDIV_W 3U //!< Width of the PLL DIV clk. +#define DSC_CLK_SRC_W 3U //!< Width of DSC CLK src +#define DSC_AI_TYPE_W 2U //!< Width of the AI type +#define DSC_CLK_MODE_W 3U //!< Width of the DSC clock slice mode +#define DSC_NUM_LPCG_W 8U //!< Width of the num lpcg + +#define MEM_NORMAL 0U +#define MEM_ESILICON 1U + +#define SLICE_SMALL_MULTI_MAX_DIV 31U +#define SLICE_LARGE_MAX_DIV 255U + +/*! + * @name Short defines for sc_pm_clk_parent_t + */ +/** @{ */ +#define XTAL 0U /*! < Parent is XTAL. */ +#define PLL0 1U /*! < Parent is PLL0 */ +#define PLL1 2U /*! < Parent is PLL1 or PLL0/2 */ +#define PLL2 3U /*! < Parent in PLL2 or PLL0/4 */ +#define BYPS 4U /*! < Parent is a bypass clock. */ +#define DUMMY 5U /*! < DUMMY entry */ +/** @} */ + +/*! + * @name Defines for sc_pm_clk_mode_t + */ +/** @{ */ +#define SC_PM_CLK_MODE_ROM_INIT 0U /*!< Clock is initialized by ROM */ +#define SC_PM_CLK_MODE_OFF 1U /*!< Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2U /*!< Clock is enabled */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3U /*!< Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4U /*!< Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /*!< Clock is in SW-HW autogate mode */ +/** @} */ + +/*! + * This define is used to access DSC registers. + */ +#ifdef NO_DEVICE_ACCESS + #define DSC_BASE_ADDR(X) ((DSC_Type*) (temp_dsc + ((X) * DSC_SIZE))) +#else + #define DSC_BASE_ADDR(X) ((DSC_Type*) (MSI0_BASE + ((X) * DSC_SIZE))) +#endif + +/*! Define to fill in a dsc_clk_info_t variable PLL_DIV set */ +#define CNFO(R, S, G, RL, PD, CM, CT, I, DIV) \ + { \ + .rate = (R), \ + .src = (S), \ + .sw_gate = (G), \ + .rate_locked = (RL), \ + .pd = (PD), \ + .clk_mode = (SC_PM_CLK_MODE_##CM), \ + .clk_type = (DSC_##CT), \ + .index = (I), \ + .pll_div = (DIV) \ + } + +/* Types */ + +/*! + * This type is used to declare a clock mode. + */ +typedef uint8_t sc_pm_clk_mode_t; + +typedef uint8_t dsc_pdom_t; + +#define DSC_SMALL_SINGLE_CLK_ROOT 0U +#define DSC_LARGE_SINGLE_CLK_ROOT 1U +#define DSC_MULTI_CLK_ROOT 2U +#define DSC_CPU_CLK_ROOT 3U +#define DSC_GPR_CLK_ROOT 4U +#define DSC_PLL_DUMMY 5U +#define DSC_BYPASS 6U +#define DSC_XTAL 7U +#define DSC_PLL_DIG 9U +#define DSC_PLL_PERF 10U +#define DSC_PLL_AV 11U +#define DSC_PLL_DIG_AUD 12U + +typedef uint8_t dsc_clk_type_t; + +typedef uint32_t dsc_gpr_t; + +/*! + * This type is used to store static constant info about the clocks in + * the subsystem. The clock indexs in the ss_rsrc_info references + * this. + */ +typedef struct +{ + sc_pm_clock_rate_t rate; //!< Default clock rate + sc_pm_clk_parent_t src : DSC_CLK_SRC_W; //!< Clock source for the slice + uint8_t pll_div : DSC_PLLDIV_W; //!< Divided PLL is the source for the slice + uint8_t sw_gate : SC_BOOL_W; //!< 0=no lpcg, 1=lpcg + uint8_t rate_locked : SC_BOOL_W; //!< 0=user rated, 1=locked + dsc_pdom_t pd : DSC_PDOM_W; //!< Power domain clock feeds + sc_pm_clk_mode_t clk_mode : SC_PM_CLOCK_MODE_W; //!< Default clock mode when SS is powered up. + dsc_clk_type_t clk_type : DSC_CLK_TYPE_W; //!< Type of clock slice + uint8_t index : DSC_INDEX_W; //!< Index into clock/PLL type +} dsc_clk_info_t; + +#define AI_NONE 0U +#define AI_COMMON 1U +#define AI_TEMP 2U +#define AI_TEMP_SEQ 3U + +typedef uint8_t dsc_ai_type_t; + +typedef struct +{ + uint32_t div0; + uint32_t div1; + uint32_t div2; + uint32_t div3; +} dsc_mslice_div_t; + +/* Externs */ + +#ifdef NO_DEVICE_ACCESS + /*! + * This variable is used to access fake DSCs. + */ + extern uint8_t temp_dsc[]; + #define HAS_TEMP_DSC + /*! + * This variable is used to access fake DSC AIs. + */ + extern uint32_t temp_dsc_ai[][32][32]; + extern sc_bool_t temp_ai_direct; + #define HAS_TEMP_DSC_AI + + #define DSC_AI_DIRECT(X) temp_ai_direct = (X) +#else + #define DSC_AI_DIRECT(X) NOP +#endif + +/* Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +/*! + * This function initializes the DSC AON HW. It's mostly used to initialize + * fake HW for the simulation builds to have the correct reset state. + * + * @param[in] dsc DSC to initialize + * @param[in] ai_type type of analog interface + * + * This is only called once at startup. It is not a reset and should not be + * called when a subsystem is powered up. + */ +void DSC_Init(sc_dsc_t dsc, dsc_ai_type_t ai_type); + +void DSC_Reset(uint8_t pd, sc_dsc_t dsc, uint32_t reset_mask); +void DSC_SetReset(sc_dsc_t dsc, uint32_t val, sc_bool_t enable); +uint32_t DSC_GetReset(sc_dsc_t dsc); +void DSC_SetMemTiming(sc_dsc_t dsc, sc_bool_t hs_enable, + sc_bool_t ls_enable, uint8_t pd); +void DSC_SetGPRControl(sc_dsc_t dsc, uint32_t gpr_num, uint32_t gpr_val, + sc_bool_t enable); +void DSC_InsGPRControl(sc_dsc_t dsc, uint32_t gpr_num, uint32_t gpr_pos, + uint32_t mask, uint32_t val); +uint32_t DSC_GetGPRControl(sc_dsc_t dsc, uint32_t gpr_num); +uint32_t DSC_GetGPRStatus(sc_dsc_t dsc, uint32_t gpr_num); +void DSC_WaitGPRStatus(sc_dsc_t dsc, uint32_t gpr_num, uint32_t gpr_mask, + uint32_t gpr_val); +void DSC_EnableIrq(sc_dsc_t dsc, uint64_t mask, sc_bool_t enable); +uint64_t DSC_GetIrqPending(sc_dsc_t dsc); +uint64_t DSC_GetIrqStatus(sc_dsc_t dsc); + +void DSC_EnableAnamixAI(sc_dsc_t dsc); +sc_bool_t DSC_AnamixAIEnabled(sc_dsc_t dsc); +#ifndef NO_ANAMIX +void DSC_DisableAnamixAI(sc_dsc_t dsc); +void DSC_EnablePhymixAI(sc_dsc_t dsc); +#endif + +#ifdef ANAMIX_BROADCAST +void DSC_AIBroadcastWrite(sc_dsc_t dsc, uint32_t toggle, uint16_t addr, + uint32_t data); +#endif +void DSC_AIRegisterWrite(sc_dsc_t dsc, uint8_t src_sel, uint16_t addr, + uint32_t data); +void DSC_AIRegisterRead(sc_dsc_t dsc, uint8_t src_sel, uint16_t addr, + uint32_t *data); + +/** @} */ + +/*! + * @name Power Functions + * @{ + */ +sc_bool_t DSC_PdEnabled(uint8_t pd, sc_dsc_t dsc); +void DSC_PdEnable(uint8_t pd, sc_dsc_t dsc, uint8_t ss_pd, + uint32_t reset_mask, sc_bool_t reboot); +void DSC_PdDisable(uint8_t pd, sc_dsc_t dsc, uint8_t ss_pd, + uint32_t reset_mask, sc_bool_t reboot); +void DSC_IsolationDisable(sc_dsc_t dsc, uint8_t pd, uint8_t misc, + sc_bool_t enable); + +/** @} */ + +/*! + * @name Clock Functions + * @{ + */ +sc_bool_t DSC_SliceReset(sc_dsc_t dsc, const dsc_clk_info_t *clk_info); +sc_err_t DSC_CheckClockMode(sc_dsc_t dsc, + const dsc_clk_info_t *clk, sc_pm_clk_mode_t mode); +void DSC_SetClockMode(sc_dsc_t dsc, const dsc_clk_info_t *clk, + sc_pm_clk_mode_t mode); +void DSC_ClkSetRate(sc_dsc_t dsc, const dsc_clk_info_t *clk, + uint32_t rate_div, uint32_t parent_rate); +void DSC_MSliceGetDiv(sc_dsc_t dsc, dsc_mslice_div_t *p_mslice_div); +void DSC_MSliceSetDiv(sc_dsc_t dsc, const dsc_mslice_div_t *p_mslice_div); +void DSC_ClkSetParent(sc_dsc_t dsc, const dsc_clk_info_t *clk, + sc_pm_clk_parent_t parent); +sc_pm_clk_parent_t DSC_ClkGetParent(sc_dsc_t dsc, const dsc_clk_info_t *clk); +uint32_t DSC_ClkGetRateDiv(sc_dsc_t dsc, const dsc_clk_info_t *clk); +void DSC_FuncClkToggle(sc_dsc_t dsc, dsc_clk_type_t clk_type, uint32_t val, sc_bool_t enable); + +/** @} */ + +/*! + * @name AI Clock Functions + * @{ + */ +sc_bool_t DSC_AIPllEnabled(sc_dsc_t dsc, uint8_t pll_index, dsc_clk_type_t pll_type); +void DSC_AIPllEnable(sc_dsc_t dsc, uint8_t pll_index, + dsc_clk_type_t pll_type); +uint32_t DSC_AIPllGetRate(sc_dsc_t dsc, uint8_t pll_index, + dsc_clk_type_t pll_type); +uint32_t DSC_AIPllSetRate(sc_dsc_t dsc, uint8_t pll_index, + dsc_clk_type_t pll_type, uint32_t rate, sc_bool_t powered, sc_bool_t ssc_enable); +void DSC_AIPllDisable(sc_dsc_t dsc, uint8_t pll_index, + dsc_clk_type_t pll_type); +uint32_t DSC_CalcBestPllFreqParent(dsc_clk_type_t pll_type, uint32_t rate, + sc_pm_clk_parent_t *parent, sc_bool_t fixed_parent, uint32_t max_div); + +/** @} */ + +/*! + * @name AI Temp Sensor Functions + * @{ + */ + +void DSC_AIPowerTemp(sc_dsc_t dsc, sc_bool_t enable, sc_bool_t run); +void DSC_AITriggerTemp(sc_dsc_t dsc); +void DSC_AISetTemp(sc_dsc_t dsc, uint32_t idx, uint16_t val); +sc_err_t DSC_AIGetTemp(sc_dsc_t dsc, uint32_t idx, uint16_t *val); +void DSC_AIClearTemp(sc_dsc_t dsc, uint32_t idx); +void DSC_AIDisablePanicTemp(sc_dsc_t dsc); + +/** @} */ + +#if defined(DEBUG) || defined(GCOV) + /*! + * @name Debug Functions + * @{ + */ + + /*! + * This function dumps the DSC. It's only used for debug. Should + * only be called if the power domain containing the DSC is powered on. + */ + void DSC_Dump(sc_dsc_t dsc); + + /** @} */ +#endif + +#endif /* DRV_DSC_H */ + +/** @} */ + diff --git a/platform/drivers/gpio/fsl_gpio.h b/platform/drivers/gpio/fsl_gpio.h new file mode 100755 index 0000000..28014d4 --- /dev/null +++ b/platform/drivers/gpio/fsl_gpio.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* This file maps GPIO functions to RGPIO functions. It cannot be used at the + same time as the IGPIO driver! */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "drivers/rgpio/fsl_rgpio.h" + +#define kGPIO_DigitalInput kRGPIO_DigitalInput +#define kGPIO_DigitalOutput kRGPIO_DigitalOutput + +#define gpio_pin_config_t rgpio_pin_config_t + +#define GPIO_PinInit RGPIO_PinInit +#define GPIO_WritePinOutput RGPIO_WritePinOutput +#define GPIO_SetPinsOutput RGPIO_SetPinsOutput +#define GPIO_ClearPinsOutput RGPIO_ClearPinsOutput +#define GPIO_TogglePinsOutput RGPIO_TogglePinsOutput +#define GPIO_ReadPinInput RGPIO_ReadPinInput +#define GPIO_GetPinsInterruptFlags RGPIO_GetPinsInterruptFlags +#define GPIO_ClearPinsInterruptFlags RGPIO_ClearPinsInterruptFlags + +#endif /* _FSL_GPIO_H_*/ diff --git a/platform/drivers/igpio/Makefile b/platform/drivers/igpio/Makefile new file mode 100755 index 0000000..ee8c054 --- /dev/null +++ b/platform/drivers/igpio/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/igpio/fsl_gpio.o + +DIRS += $(OUT)/drivers/igpio + diff --git a/platform/drivers/igpio/fsl_gpio.h b/platform/drivers/igpio/fsl_gpio.h new file mode 100755 index 0000000..c704ddc --- /dev/null +++ b/platform/drivers/igpio/fsl_gpio.h @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +/*! @brief GPIO driver version 2.0.3. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/** @} */ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param Config pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); +/** @} */ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + GPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else + base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else + base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32U); + + return (((base->DR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current input value of the GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinRead(base, pin); +} +/** @} */ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + +/*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32U); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current GPIO pin pad status. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinReadPadStatus(base, pin); +} + +/** @} */ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pinInterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Sets the current pin interrupt mode. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortEnableInterrupts(base, mask); +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortDisableInterrupts(base, mask); +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + return base->ISR; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + return GPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISR = mask; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClearInterruptFlags(base, mask); +} +/** @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/platform/drivers/lmem/Makefile b/platform/drivers/lmem/Makefile new file mode 100755 index 0000000..103d4bc --- /dev/null +++ b/platform/drivers/lmem/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/lmem/fsl_lmem_cache.o + +DIRS += $(OUT)/drivers/lmem + diff --git a/platform/drivers/lmem/fsl_lmem_cache.h b/platform/drivers/lmem/fsl_lmem_cache.h new file mode 100755 index 0000000..cda24be --- /dev/null +++ b/platform/drivers/lmem/fsl_lmem_cache.h @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LMEM_CACHE_H_ +#define _FSL_LMEM_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lmem_cache + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +/*! @brief LMEM controller driver version 2.1.2. */ +#define FSL_LMEM_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/** @} */ + +#define LMEM_CACHE_LINE_SIZE (0x10U) /*!< Cache line is 16-bytes. */ +#define LMEM_CACHE_SIZE_ONEWAY (4096U) /*!< Cache size is 4K-bytes one way. */ + +/*! @brief LMEM cache mode options. */ +typedef enum _lmem_cache_mode +{ + kLMEM_NonCacheable = 0x0U, /*!< Cache mode: non-cacheable. */ + kLMEM_CacheWriteThrough = 0x2U, /*!< Cache mode: write-through. */ + kLMEM_CacheWriteBack = 0x3U /*!< Cache mode: write-back. */ +} lmem_cache_mode_t; + +/*! @brief LMEM cache regions. */ +typedef enum _lmem_cache_region +{ + kLMEM_CacheRegion15 = 0U, /*!< Cache Region 15. */ + kLMEM_CacheRegion14, /*!< Cache Region 14. */ + kLMEM_CacheRegion13, /*!< Cache Region 13. */ + kLMEM_CacheRegion12, /*!< Cache Region 12. */ + kLMEM_CacheRegion11, /*!< Cache Region 11. */ + kLMEM_CacheRegion10, /*!< Cache Region 10. */ + kLMEM_CacheRegion9, /*!< Cache Region 9. */ + kLMEM_CacheRegion8, /*!< Cache Region 8. */ + kLMEM_CacheRegion7, /*!< Cache Region 7. */ + kLMEM_CacheRegion6, /*!< Cache Region 6. */ + kLMEM_CacheRegion5, /*!< Cache Region 5. */ + kLMEM_CacheRegion4, /*!< Cache Region 4. */ + kLMEM_CacheRegion3, /*!< Cache Region 3. */ + kLMEM_CacheRegion2, /*!< Cache Region 2. */ + kLMEM_CacheRegion1, /*!< Cache Region 1. */ + kLMEM_CacheRegion0 /*!< Cache Region 0. */ +} lmem_cache_region_t; + +/*! @brief LMEM cache line command. */ +typedef enum _lmem_cache_line_command +{ + kLMEM_CacheLineSearchReadOrWrite = 0U, /*!< Cache line search and read or write. */ + kLMEM_CacheLineInvalidate, /*!< Cache line invalidate. */ + kLMEM_CacheLinePush, /*!< Cache line push. */ + kLMEM_CacheLineClear, /*!< Cache line clear. */ +} lmem_cache_line_command_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Local Memory Processor Code Bus Cache Control + *@{ + */ + +/*! + * @brief Enables/disables the processor code bus cache. + * This function enables/disables the cache. The function first invalidates the entire cache + * and then enables/disables both the cache and write buffers. + * + * @param base LMEM peripheral base address. + * @param enable The enable or disable flag. + * true - enable the code cache. + * false - disable the code cache. + */ +void LMEM_EnableCodeCache(LMEM_Type *base, bool enable); + +/*! + * @brief Enables/disables the processor code bus write buffer. + * + * @param base LMEM peripheral base address. + * @param enable The enable or disable flag. + * true - enable the code bus write buffer. + * false - disable the code bus write buffer. + */ +static inline void LMEM_EnableCodeWriteBuffer(LMEM_Type *base, bool enable) +{ + if (enable) + { + base->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK; + } + else + { + base->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK; + } +} + +/*! + * @brief Invalidates the processor code bus cache. + * This function invalidates the cache both ways, which means that + * it unconditionally clears valid bits and modifies bits of a cache entry. + * + * @param base LMEM peripheral base address. + */ +void LMEM_CodeCacheInvalidateAll(LMEM_Type *base); + +/*! + * @brief Pushes all modified lines in the processor code bus cache. + * This function pushes all modified lines in both ways in the entire cache. + * It pushes a cache entry if it is valid and modified and clears the modified bit. If + * the entry is not valid or not modified, leave as is. This action does not clear the valid + * bit. A cache push is synonymous with a cache flush. + * + * @param base LMEM peripheral base address. + */ +void LMEM_CodeCachePushAll(LMEM_Type *base); + +/*! + * @brief Clears the processor code bus cache. + * This function clears the entire cache and pushes (flushes) and + * invalidates the operation. + * Clear - Pushes a cache entry if it is valid and modified, then clears the valid and + * modified bits. If the entry is not valid or not modified, clear the valid bit. + * + * @param base LMEM peripheral base address. + */ +void LMEM_CodeCacheClearAll(LMEM_Type *base); + +/*! + * @brief Invalidates a specific line in the processor code bus cache. + * This function invalidates a specific line in the cache + * based on the physical address passed in by the user. + * Invalidate - Unconditionally clears valid and modified bits of a cache entry. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + */ +void LMEM_CodeCacheInvalidateLine(LMEM_Type *base, uint32_t address); + +/*! + * @brief Invalidates multiple lines in the processor code bus cache. + * This function invalidates multiple lines in the cache + * based on the physical address and length in bytes passed in by the + * user. If the function detects that the length meets or exceeds half the + * cache, the function performs an entire cache invalidate function, which is + * more efficient than invalidating the cache line-by-line. + * Because the cache consists of two ways and line commands based on the physical address searches both ways, + * check half the total amount of cache. + * Invalidate - Unconditionally clear valid and modified bits of a cache entry. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param length The length in bytes of the total amount of cache lines. + */ +void LMEM_CodeCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length); + +/*! + * @brief Pushes a specific modified line in the processor code bus cache. + * This function pushes a specific modified line based on the physical address passed in + * by the user. + * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If the + * entry is not valid or not modified, leave as is. This action does not clear the valid + * bit. A cache push is synonymous with a cache flush. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + */ +void LMEM_CodeCachePushLine(LMEM_Type *base, uint32_t address); + +/*! + * @brief Pushes multiple modified lines in the processor code bus cache. + * This function pushes multiple modified lines in the cache + * based on the physical address and length in bytes passed in by the + * user. If the function detects that the length meets or exceeds half of the + * cache, the function performs an cache push function, which is + * more efficient than pushing the modified lines in the cache line-by-line. + * Because the cache consists of two ways and line commands based on the physical address searches both ways, + * check half the total amount of cache. + * Push - Push a cache entry if it is valid and modified, then clear the modified bit. If + * the entry is not valid or not modified, leave as is. This action does not clear the valid + * bit. A cache push is synonymous with a cache flush. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param length The length in bytes of the total amount of cache lines. + */ +void LMEM_CodeCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length); + +/*! + * @brief Clears a specific line in the processor code bus cache. + * This function clears a specific line based on the physical address passed in + * by the user. + * Clear - Push a cache entry if it is valid and modified, then clear the valid and + * modify bits. If entry not valid or not modified, clear the valid bit. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + */ +void LMEM_CodeCacheClearLine(LMEM_Type *base, uint32_t address); + +/*! + * @brief Clears multiple lines in the processor code bus cache. + * This function clears multiple lines in the cache + * based on the physical address and length in bytes passed in by the + * user. If the function detects that the length meets or exceeds half the total amount of + * cache, the function performs a cache clear function which is + * more efficient than clearing the lines in the cache line-by-line. + * Because the cache consists of two ways and line commands based on the physical address searches both ways, + * check half the total amount of cache. + * Clear - Push a cache entry if it is valid and modified, then clear the valid and + * modify bits. If entry not valid or not modified, clear the valid bit. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param length The length in bytes of the total amount of cache lines. + */ +void LMEM_CodeCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length); + +#if (!defined(FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE)) || !FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE +/*! + * @brief Demotes the cache mode of a region in processor code bus cache. + * This function allows the user to demote the cache mode of a region within the device's + * memory map. Demoting the cache mode reduces the cache function applied to a memory + * region from write-back to write-through to non-cacheable. The function checks to see + * if the requested cache mode is higher than or equal to the current cache mode, and if + * so, returns an error. After a region is demoted, its cache mode can only be raised + * by a reset, which returns it to its default state which is the highest cache configure for + * each region. + * To maintain cache coherency, changes to the cache mode should be completed while the + * address space being changed is not being accessed or the cache is disabled. Before a + * cache mode change, this function completes a cache clear all command to push and invalidate any + * cache entries that may have changed. + * + * @param base LMEM peripheral base address. + * @param region The desired region to demote of type lmem_cache_region_t. + * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t. + * @return The execution result. + * kStatus_Success The cache demote operation is successful. + * kStatus_Fail The cache demote operation is failure. + */ +status_t LMEM_CodeCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode); +#endif /* FSL_FEATURE_LMEM_SUPPORT_ICACHE_DEMOTE_REMOVE */ + +/** @} */ + +#if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE +/*! + * @name Local Memory Processor System Bus Cache Control + *@{ + */ + +/*! + * @brief Enables/disables the processor system bus cache. + * This function enables/disables the cache. It first invalidates the entire cache, + * then enables /disable both the cache and write buffer. + * + * @param base LMEM peripheral base address. + * @param enable The enable or disable flag. + * true - enable the system cache. + * false - disable the system cache. + */ +void LMEM_EnableSystemCache(LMEM_Type *base, bool enable); + +/*! + * @brief Enables/disables the processor system bus write buffer. + * + * @param base LMEM peripheral base address. + * @param enable The enable or disable flag. + * true - enable the system bus write buffer. + * false - disable the system bus write buffer. + */ +static inline void LMEM_EnableSystemWriteBuffer(LMEM_Type *base, bool enable) +{ + if (enable) + { + base->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK; + } + else + { + base->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK; + } +} + +/*! + * @brief Invalidates the processor system bus cache. + * This function invalidates the entire cache both ways. + * Invalidate - Unconditionally clear valid and modify bits of a cache entry + * + * @param base LMEM peripheral base address. + */ +void LMEM_SystemCacheInvalidateAll(LMEM_Type *base); + +/*! + * @brief Pushes all modified lines in the processor system bus cache. + * This function pushes all modified lines in both ways (the entire cache). + * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If + * the entry is not valid or not modified, leave as is. This action does not clear the valid + * bit. A cache push is synonymous with a cache flush. + * + * @param base LMEM peripheral base address. + */ +void LMEM_SystemCachePushAll(LMEM_Type *base); + +/*! + * @brief Clears the entire processor system bus cache. + * This function clears the entire cache, which is a push (flush) and + * invalidate operation. + * Clear - Push a cache entry if it is valid and modified, then clear the valid and + * modify bits. If the entry is not valid or not modified, clear the valid bit. + * + * @param base LMEM peripheral base address. + */ +void LMEM_SystemCacheClearAll(LMEM_Type *base); + +/*! + * @brief Invalidates a specific line in the processor system bus cache. + * This function invalidates a specific line in the cache + * based on the physical address passed in by the user. + * Invalidate - Unconditionally clears valid and modify bits of a cache entry. + * + * @param base LMEM peripheral base address. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param address The physical address of the cache line. + */ +void LMEM_SystemCacheInvalidateLine(LMEM_Type *base, uint32_t address); + +/*! + * @brief Invalidates multiple lines in the processor system bus cache. + * This function invalidates multiple lines in the cache + * based on the physical address and length in bytes passed in by the + * user. If the function detects that the length meets or exceeds half of the + * cache, the function performs an entire cache invalidate function (which is + * more efficient than invalidating the cache line-by-line). + * Because the cache consists of two ways and line commands based on the physical address searches both ways, + * check half the total amount of cache. + * Invalidate - Unconditionally clear valid and modify bits of a cache entry + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param length The length in bytes of the total amount of cache lines. + */ +void LMEM_SystemCacheInvalidateMultiLines(LMEM_Type *base, uint32_t address, uint32_t length); + +/*! + * @brief Pushes a specific modified line in the processor system bus cache. + * This function pushes a specific modified line based on the physical address passed in + * by the user. + * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If + * the entry is not valid or not modified, leave as is. This action does not clear the valid + * bit. A cache push is synonymous with a cache flush. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + */ +void LMEM_SystemCachePushLine(LMEM_Type *base, uint32_t address); + +/*! + * @brief Pushes multiple modified lines in the processor system bus cache. + * This function pushes multiple modified lines in the cache + * based on the physical address and length in bytes passed in by the + * user. If the function detects that the length meets or exceeds half of the + * cache, the function performs an entire cache push function (which is + * more efficient than pushing the modified lines in the cache line-by-line). + * Because the cache consists of two ways and line commands based on the physical address searches both ways, + * check half the total amount of cache. + * Push - Push a cache entry if it is valid and modified, then clear the modify bit. If + * the entry is not valid or not modified, leave as is. This action does not clear the valid + * bit. A cache push is synonymous with a cache flush. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param length The length in bytes of the total amount of cache lines. + */ +void LMEM_SystemCachePushMultiLines(LMEM_Type *base, uint32_t address, uint32_t length); + +/*! + * @brief Clears a specific line in the processor system bus cache. + * This function clears a specific line based on the physical address passed in + * by the user. + * Clear - Push a cache entry if it is valid and modified, then clear the valid and + * modify bits. If the entry is not valid or not modified, clear the valid bit. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + */ +void LMEM_SystemCacheClearLine(LMEM_Type *base, uint32_t address); + +/*! + * @brief Clears multiple lines in the processor system bus cache. + * This function clears multiple lines in the cache + * based on the physical address and length in bytes passed in by the + * user. If the function detects that the length meets or exceeds half of the + * cache, the function performs an entire cache clear function (which is + * more efficient than clearing the lines in the cache line-by-line). + * Because the cache consists of two ways and line commands based on the physical address searches both ways, + * check half the total amount of cache. + * Clear - Push a cache entry if it is valid and modified, then clear the valid and + * modify bits. If the entry is not valid or not modified, clear the valid bit. + * + * @param base LMEM peripheral base address. + * @param address The physical address of the cache line. Should be 16-byte aligned address. + * If not, it is changed to the 16-byte aligned memory address. + * @param length The length in bytes of the total amount of cache lines. + */ +void LMEM_SystemCacheClearMultiLines(LMEM_Type *base, uint32_t address, uint32_t length); + +/*! + * @brief Demotes the cache mode of a region in the processor system bus cache. + * This function allows the user to demote the cache mode of a region within the device's + * memory map. Demoting the cache mode reduces the cache function applied to a memory + * region from write-back to write-through to non-cacheable. The function checks to see + * if the requested cache mode is higher than or equal to the current cache mode, and if + * so, returns an error. After a region is demoted, its cache mode can only be raised + * by a reset, which returns it to its default state which is the highest cache configure + * for each region. + * To maintain cache coherency, changes to the cache mode should be completed while the + * address space being changed is not being accessed or the cache is disabled. Before a + * cache mode change, this function completes a cache clear all command to push and invalidate any + * cache entries that may have changed. + * + * @param base LMEM peripheral base address. + * @param region The desired region to demote of type lmem_cache_region_t. + * @param cacheMode The new, demoted cache mode of type lmem_cache_mode_t. + * @return The execution result. + * kStatus_Success The cache demote operation is successful. + * kStatus_Fail The cache demote operation is failure. + */ +status_t LMEM_SystemCacheDemoteRegion(LMEM_Type *base, lmem_cache_region_t region, lmem_cache_mode_t cacheMode); + +/** @} */ +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LMEM_CACHE_H_*/ diff --git a/platform/drivers/lpcg/Makefile b/platform/drivers/lpcg/Makefile new file mode 100755 index 0000000..9b6aec0 --- /dev/null +++ b/platform/drivers/lpcg/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/lpcg/fsl_lpcg.o + +DIRS += $(OUT)/drivers/lpcg + diff --git a/platform/drivers/lpcg/fsl_lpcg.h b/platform/drivers/lpcg/fsl_lpcg.h new file mode 100755 index 0000000..0474d80 --- /dev/null +++ b/platform/drivers/lpcg/fsl_lpcg.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_LPCG_H +#define DRV_LPCG_H + +/*! + * @addtogroup lpcg_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "fsl_device_registers.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +void LPCG_ClockOff(uint32_t lpcg_addr, uint8_t clk); +void LPCG_ClockOn(uint32_t lpcg_addr, uint8_t clk); +void LPCG_ClockAutoGate(uint32_t lpcg_addr, uint8_t clk); +void LPCG_AllClockOff(uint32_t lpcg_addr); +void LPCG_AllClockOn(uint32_t lpcg_addr); +void LPCG_AllClockAutoGate(uint32_t lpcg_addr); +void LPCG_AllClockAutoGateMasked(uint32_t lpcg_addr, uint32_t mask); + +#endif /* DRV_LPCG_H */ + +/** @} */ + diff --git a/platform/drivers/lpi2c/Makefile b/platform/drivers/lpi2c/Makefile new file mode 100644 index 0000000..44e180d --- /dev/null +++ b/platform/drivers/lpi2c/Makefile @@ -0,0 +1,4 @@ + +OBJS += $(OUT)/drivers/lpi2c/fsl_lpi2c.o + +DIRS += $(OUT)/drivers/lpi2c diff --git a/platform/drivers/lpi2c/fsl_lpi2c.h b/platform/drivers/lpi2c/fsl_lpi2c.h new file mode 100755 index 0000000..16361b4 --- /dev/null +++ b/platform/drivers/lpi2c/fsl_lpi2c.h @@ -0,0 +1,1268 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPI2C_H_ +#define _FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! @file */ + +/*! @name Driver version */ +/** @{ */ +/*! @brief LPI2C driver version 2.1.11. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 11)) +/** @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout polling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/** @{ */ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param config Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/** @} */ + +/*! @name Status */ +/** @{ */ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/** @} */ + +/*! @name Interrupts */ +/** @{ */ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of _lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/** @} */ + +/*! @name DMA control */ +/** @{ */ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MRDR; +} + +/** @} */ + +/*! @name FIFO control */ +/** @{ */ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/** @} */ + +/*! @name Bus operations */ +/** @{ */ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return ((base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/** @} */ + +/*! @name Non-blocking */ +/** @{ */ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/** @} */ + +/*! @name IRQ handler */ +/** @{ */ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/** @} */ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/** @{ */ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/** @} */ + +/*! @name Slave status */ +/** @{ */ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} + +/** @} */ + +/*! @name Slave interrupts */ +/** @{ */ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/** @} */ + +/*! @name Slave DMA control */ +/** @{ */ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/** @} */ + +/*! @name Slave bus operations */ +/** @{ */ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return ((base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/** @} */ + +/*! @name Slave non-blocking */ +/** @{ */ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/** @} */ + +/*! @name Slave IRQ handler */ +/** @{ */ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/** @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_LPI2C_H_ */ diff --git a/platform/drivers/lpit/Makefile b/platform/drivers/lpit/Makefile new file mode 100755 index 0000000..0fe0901 --- /dev/null +++ b/platform/drivers/lpit/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/lpit/fsl_lpit.o + +DIRS += $(OUT)/drivers/lpit + diff --git a/platform/drivers/lpit/fsl_lpit.h b/platform/drivers/lpit/fsl_lpit.h new file mode 100755 index 0000000..c6234f6 --- /dev/null +++ b/platform/drivers/lpit/fsl_lpit.h @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPIT_H_ +#define _FSL_LPIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpit + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +#define FSL_LPIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ + /** @{ */ + +/*! + * @brief List of LPIT channels + * @note Actual number of available channels is SoC-dependent + */ +typedef enum _lpit_chnl +{ + kLPIT_Chnl_0 = 0U, /*!< LPIT channel number 0*/ + kLPIT_Chnl_1, /*!< LPIT channel number 1 */ + kLPIT_Chnl_2, /*!< LPIT channel number 2 */ + kLPIT_Chnl_3, /*!< LPIT channel number 3 */ +} lpit_chnl_t; + +/*! @brief Mode options available for the LPIT timer. */ +typedef enum _lpit_timer_modes +{ + kLPIT_PeriodicCounter = 0U, /*!< Use the all 32-bits, counter loads and decrements to zero */ + kLPIT_DualPeriodicCounter, /*!< Counter loads, lower 16-bits decrement to zero, then + upper 16-bits decrement */ + kLPIT_TriggerAccumulator, /*!< Counter loads on first trigger and decrements on each trigger */ + kLPIT_InputCapture /*!< Counter loads with 0xFFFFFFFF, decrements to zero. It stores + the inverse of the current value when a input trigger is detected */ +} lpit_timer_modes_t; + +/*! + * @brief Trigger options available. + * + * This is used for both internal and external trigger sources. The actual trigger options + * available is SoC-specific, user should refer to the reference manual. + */ +typedef enum _lpit_trigger_select +{ + kLPIT_Trigger_TimerChn0 = 0U, /*!< Channel 0 is selected as a trigger source */ + kLPIT_Trigger_TimerChn1, /*!< Channel 1 is selected as a trigger source */ + kLPIT_Trigger_TimerChn2, /*!< Channel 2 is selected as a trigger source */ + kLPIT_Trigger_TimerChn3, /*!< Channel 3 is selected as a trigger source */ + kLPIT_Trigger_TimerChn4, /*!< Channel 4 is selected as a trigger source */ + kLPIT_Trigger_TimerChn5, /*!< Channel 5 is selected as a trigger source */ + kLPIT_Trigger_TimerChn6, /*!< Channel 6 is selected as a trigger source */ + kLPIT_Trigger_TimerChn7, /*!< Channel 7 is selected as a trigger source */ + kLPIT_Trigger_TimerChn8, /*!< Channel 8 is selected as a trigger source */ + kLPIT_Trigger_TimerChn9, /*!< Channel 9 is selected as a trigger source */ + kLPIT_Trigger_TimerChn10, /*!< Channel 10 is selected as a trigger source */ + kLPIT_Trigger_TimerChn11, /*!< Channel 11 is selected as a trigger source */ + kLPIT_Trigger_TimerChn12, /*!< Channel 12 is selected as a trigger source */ + kLPIT_Trigger_TimerChn13, /*!< Channel 13 is selected as a trigger source */ + kLPIT_Trigger_TimerChn14, /*!< Channel 14 is selected as a trigger source */ + kLPIT_Trigger_TimerChn15 /*!< Channel 15 is selected as a trigger source */ +} lpit_trigger_select_t; + +/*! @brief Trigger source options available */ +typedef enum _lpit_trigger_source +{ + kLPIT_TriggerSource_External = 0U, /*!< Use external trigger input */ + kLPIT_TriggerSource_Internal /*!< Use internal trigger */ +} lpit_trigger_source_t; + +/*! + * @brief List of LPIT interrupts. + * + * @note Number of timer channels are SoC-specific. See the SoC Reference Manual. + */ +typedef enum _lpit_interrupt_enable +{ + kLPIT_Channel0TimerInterruptEnable = (1U << 0), /*!< Channel 0 Timer interrupt */ + kLPIT_Channel1TimerInterruptEnable = (1U << 1), /*!< Channel 1 Timer interrupt */ + kLPIT_Channel2TimerInterruptEnable = (1U << 2), /*!< Channel 2 Timer interrupt */ + kLPIT_Channel3TimerInterruptEnable = (1U << 3), /*!< Channel 3 Timer interrupt */ +} lpit_interrupt_enable_t; + +/*! + * @brief List of LPIT status flags + * + * @note Number of timer channels are SoC-specific. See the SoC Reference Manual. + */ +typedef enum _lpit_status_flags +{ + kLPIT_Channel0TimerFlag = (1U << 0), /*!< Channel 0 Timer interrupt flag */ + kLPIT_Channel1TimerFlag = (1U << 1), /*!< Channel 1 Timer interrupt flag */ + kLPIT_Channel2TimerFlag = (1U << 2), /*!< Channel 2 Timer interrupt flag */ + kLPIT_Channel3TimerFlag = (1U << 3), /*!< Channel 3 Timer interrupt flag */ +} lpit_status_flags_t; + +/*! @brief Structure to configure the channel timer. */ +typedef struct _lpit_chnl_params +{ + bool chainChannel; /*!< true: Timer chained to previous timer; + false: Timer not chained */ + lpit_timer_modes_t timerMode; /*!< Timers mode of operation. */ + lpit_trigger_select_t triggerSelect; /*!< Trigger selection for the timer */ + lpit_trigger_source_t triggerSource; /*!< Decides if we use external or internal trigger. */ + bool enableReloadOnTrigger; /*!< true: Timer reloads when a trigger is detected; + false: No effect */ + bool enableStopOnTimeout; /*!< true: Timer will stop after timeout; + false: does not stop after timeout */ + bool enableStartOnTrigger; /*!< true: Timer starts when a trigger is detected; + false: decrement immediately */ +} lpit_chnl_params_t; + +/*! + * @brief LPIT configuration structure + * + * This structure holds the configuration settings for the LPIT peripheral. To initialize this + * structure to reasonable defaults, call the LPIT_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _lpit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ + bool enableRunInDoze; /*!< true: Timers run in doze mode; false: Timers stop in doze mode */ +} lpit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the LPIT clock and configures the peripheral for a basic operation. + * + * This function issues a software reset to reset all channels and registers except the Module + * Control register. + * + * @note This API should be called at the beginning of the application using the LPIT driver. + * + * @param base LPIT peripheral base address. + * @param config Pointer to the user configuration structure. + */ +void LPIT_Init(LPIT_Type *base, const lpit_config_t *config); + +/*! + * @brief Disables the module and gates the LPIT clock. + * + * @param base LPIT peripheral base address. + */ +void LPIT_Deinit(LPIT_Type *base); + +/*! + * @brief Fills in the LPIT configuration structure with default settings. + * + * The default values are: + * @code + * config->enableRunInDebug = false; + * config->enableRunInDoze = false; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void LPIT_GetDefaultConfig(lpit_config_t *config); + +/*! + * @brief Sets up an LPIT channel based on the user's preference. + * + * This function sets up the operation mode to one of the options available in the + * enumeration ::lpit_timer_modes_t. It sets the trigger source as either internal or external, + * trigger selection and the timers behaviour when a timeout occurs. It also chains + * the timer if a prior timer if requested by the user. + * + * @param base LPIT peripheral base address. + * @param channel Channel that is being configured. + * @param chnlSetup Configuration parameters. + */ +status_t LPIT_SetupChannel(LPIT_Type *base, lpit_chnl_t channel, const lpit_chnl_params_t *chnlSetup); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base LPIT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lpit_interrupt_enable_t + */ +static inline void LPIT_EnableInterrupts(LPIT_Type *base, uint32_t mask) +{ + base->MIER |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base LPIT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lpit_interrupt_enable_t + */ +static inline void LPIT_DisableInterrupts(LPIT_Type *base, uint32_t mask) +{ + base->MIER &= ~mask; +} + +/*! + * @brief Gets the enabled LPIT interrupts. + * + * @param base LPIT peripheral base address. + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lpit_interrupt_enable_t + */ +static inline uint32_t LPIT_GetEnabledInterrupts(LPIT_Type *base) +{ + return base->MIER; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPIT status flags. + * + * @param base LPIT peripheral base address. + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lpit_status_flags_t + */ +static inline uint32_t LPIT_GetStatusFlags(LPIT_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPIT status flags. + * + * @param base LPIT peripheral base address. + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lpit_status_flags_t + */ +static inline void LPIT_ClearStatusFlags(LPIT_Type *base, uint32_t mask) +{ + /* Writing a 1 to the status bit will clear the flag */ + base->MSR = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting down from the value set by this function until it reaches 0, at which point + * it generates an interrupt and loads this register value again. + * Writing a new value to this register does not restart the timer. Instead, the value + * is loaded after the timer expires. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks. + * + * @param base LPIT peripheral base address. + * @param channel Timer channel number. + * @param ticks Timer period in units of ticks. + */ +static inline void LPIT_SetTimerPeriod(LPIT_Type *base, lpit_chnl_t channel, uint32_t ticks) +{ + base->CHANNEL[channel].TVAL = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to microseconds or milliseconds. + * + * @param base LPIT peripheral base address. + * @param channel Timer channel number. + * + * @return Current timer counting value in ticks. + */ +static inline uint32_t LPIT_GetCurrentTimerCount(LPIT_Type *base, lpit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load the period value and count down to 0. When the timer + * reaches 0, it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base LPIT peripheral base address. + * @param channel Timer channel number. + */ +static inline void LPIT_StartTimer(LPIT_Type *base, lpit_chnl_t channel) +{ + uint32_t shift = LPIT_SETTEN_SET_T_EN_0_MASK; + + base->SETTEN |= shift << ((uint32_t)channel); +} +/*! + * @brief Stops the timer counting. + * + * @param base LPIT peripheral base address. + * @param channel Timer channel number. + */ +static inline void LPIT_StopTimer(LPIT_Type *base, lpit_chnl_t channel) +{ + uint32_t shift = LPIT_CLRTEN_CLR_T_EN_0_MASK; + + base->CLRTEN |= shift << ((uint32_t)channel); +} + +/*! @}*/ + +/*! + * @brief Performs a software reset on the LPIT module. + * + * This resets all channels and registers except the Module Control Register. + * + * @param base LPIT peripheral base address. + */ +static inline void LPIT_Reset(LPIT_Type *base) +{ + base->MCR |= LPIT_MCR_SW_RST_MASK; + base->MCR &= ~LPIT_MCR_SW_RST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_LPIT_H__ */ diff --git a/platform/drivers/lpuart/Makefile b/platform/drivers/lpuart/Makefile new file mode 100755 index 0000000..a2e6a89 --- /dev/null +++ b/platform/drivers/lpuart/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/lpuart/fsl_lpuart.o + +DIRS += $(OUT)/drivers/lpuart + diff --git a/platform/drivers/lpuart/fsl_lpuart.h b/platform/drivers/lpuart/fsl_lpuart.h new file mode 100755 index 0000000..22c15bd --- /dev/null +++ b/platform/drivers/lpuart/fsl_lpuart.h @@ -0,0 +1,864 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +/*! @brief LPUART driver version 2.3.0. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/** @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITY bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/** @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/** @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/** @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} + +/** @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/** @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/** @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/platform/drivers/mtr/Makefile b/platform/drivers/mtr/Makefile new file mode 100644 index 0000000..159105d --- /dev/null +++ b/platform/drivers/mtr/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/mtr/fsl_mtr.o + +DIRS += $(OUT)/drivers/mtr + diff --git a/platform/drivers/mtr/fsl_mtr.h b/platform/drivers/mtr/fsl_mtr.h new file mode 100755 index 0000000..0d6c2d8 --- /dev/null +++ b/platform/drivers/mtr/fsl_mtr.h @@ -0,0 +1,68 @@ +/* + * Copyright 2018-2019 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FSL_MTR_H +#define FSL_MTR_H + +#include "fsl_common.h" + +/*! + * @addtogroup mtr + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +sc_bool_t MTR_repair_mem(uint8_t power_plane_sel); + +sc_bool_t MTR_bisr_xfer(uint32_t bisr_addr, uint32_t start_addr, uint32_t end_addr); + +sc_bool_t MTR_bisr_soft_reset(uint32_t bisr_addr); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_MTR_H */ diff --git a/platform/drivers/mu/Makefile b/platform/drivers/mu/Makefile new file mode 100755 index 0000000..0e6156e --- /dev/null +++ b/platform/drivers/mu/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/mu/fsl_mu.o + +DIRS += $(OUT)/drivers/mu + diff --git a/platform/drivers/mu/fsl_mu.h b/platform/drivers/mu/fsl_mu.h new file mode 100755 index 0000000..e727ac0 --- /dev/null +++ b/platform/drivers/mu/fsl_mu.h @@ -0,0 +1,741 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_MU_H_ +#define _FSL_MU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mu + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Compatibility Macros */ +#ifndef MU_CR_NMI_MASK +#define MU_CR_NMI_MASK 0U +#endif + +#if (defined(FSL_FEATURE_MU_HAS_RESET_INT) && FSL_FEATURE_MU_HAS_RESET_INT) + +#ifndef FSL_FEATURE_MU_HAS_RESET_ASSERT_INT +#define FSL_FEATURE_MU_HAS_RESET_ASSERT_INT 1 +#endif + +#ifndef FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT +#define FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT 1 +#endif + +#endif /* FSL_FEATURE_MU_HAS_RESET_INT */ + +/*! @name Driver version */ +/** @{ */ +/*! @brief MU driver version 2.0.3. */ +#define FSL_MU_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/** @} */ + +/*! + * @brief MU status flags. + */ +enum _mu_status_flags +{ + kMU_Tx0EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 3U)), /*!< TX0 empty. */ + kMU_Tx1EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 2U)), /*!< TX1 empty. */ + kMU_Tx2EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 1U)), /*!< TX2 empty. */ + kMU_Tx3EmptyFlag = (1U << (MU_SR_TEn_SHIFT + 0U)), /*!< TX3 empty. */ + + kMU_Rx0FullFlag = (1U << (MU_SR_RFn_SHIFT + 3U)), /*!< RX0 full. */ + kMU_Rx1FullFlag = (1U << (MU_SR_RFn_SHIFT + 2U)), /*!< RX1 full. */ + kMU_Rx2FullFlag = (1U << (MU_SR_RFn_SHIFT + 1U)), /*!< RX2 full. */ + kMU_Rx3FullFlag = (1U << (MU_SR_RFn_SHIFT + 0U)), /*!< RX3 full. */ + + kMU_GenInt0Flag = (int)(1U << (MU_SR_GIPn_SHIFT + 3U)), /*!< General purpose interrupt 0 pending. */ + kMU_GenInt1Flag = (1U << (MU_SR_GIPn_SHIFT + 2U)), /*!< General purpose interrupt 0 pending. */ + kMU_GenInt2Flag = (1U << (MU_SR_GIPn_SHIFT + 1U)), /*!< General purpose interrupt 0 pending. */ + kMU_GenInt3Flag = (1U << (MU_SR_GIPn_SHIFT + 0U)), /*!< General purpose interrupt 0 pending. */ + + kMU_EventPendingFlag = MU_SR_EP_MASK, /*!< MU event pending. */ + kMU_FlagsUpdatingFlag = MU_SR_FUP_MASK, /*!< MU flags update is on-going. */ + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, /*!< The other core reset assert interrupt pending. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) + kMU_ResetDeassertInterruptFlag = MU_SR_RDIP_MASK, /*!< The other core reset de-assert interrupt pending. */ +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) + kMU_OtherSideInResetFlag = MU_SR_RS_MASK /*!< The other side is in reset. */ +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + kMU_MuResetInterruptFlag = MU_SR_MURIP_MASK, /*!< The other side initializes MU reset. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + kMU_HardwareResetInterruptFlag = MU_SR_HRIP_MASK, /*!< Current side has been hardware reset by the other side. */ +#endif +}; + +/*! + * @brief MU interrupt source to enable. + */ +enum _mu_interrupt_enable +{ + kMU_Tx0EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 3U)), /*!< TX0 empty. */ + kMU_Tx1EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 2U)), /*!< TX1 empty. */ + kMU_Tx2EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 1U)), /*!< TX2 empty. */ + kMU_Tx3EmptyInterruptEnable = (1U << (MU_CR_TIEn_SHIFT + 0U)), /*!< TX3 empty. */ + + kMU_Rx0FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 3U)), /*!< RX0 full. */ + kMU_Rx1FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 2U)), /*!< RX1 full. */ + kMU_Rx2FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 1U)), /*!< RX2 full. */ + kMU_Rx3FullInterruptEnable = (1U << (MU_CR_RIEn_SHIFT + 0U)), /*!< RX3 full. */ + + kMU_GenInt0InterruptEnable = (int)(1U << (MU_CR_GIEn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ + kMU_GenInt1InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ + kMU_GenInt2InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ + kMU_GenInt3InterruptEnable = (1U << (MU_CR_GIEn_SHIFT + 0U)), /*!< General purpose interrupt 3. */ + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + kMU_ResetAssertInterruptEnable = MU_CR_RAIE_MASK, /*!< The other core reset assert interrupt. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + kMU_ResetDeassertInterruptEnable = MU_CR_RDIE_MASK, /*!< The other core reset de-assert interrupt. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + kMU_MuResetInterruptEnable = MU_CR_MURIE_MASK, /*!< The other side initializes MU reset. The interrupt + is ORed with the general purpose interrupt 3. The + general purpose interrupt 3 is issued when the other side + set the MU reset and this interrupt is enabled. */ +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + kMU_HardwareResetInterruptEnable = MU_CR_HRIE_MASK, /*!< Current side has been hardware reset by the other side. */ +#endif +}; + +/*! + * @brief MU interrupt that could be triggered to the other core. + */ +enum _mu_interrupt_trigger +{ +#if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI) + kMU_NmiInterruptTrigger = MU_CR_NMI_MASK, /*!< NMI interrupt. */ +#endif + kMU_GenInt0InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 3U)), /*!< General purpose interrupt 0. */ + kMU_GenInt1InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 2U)), /*!< General purpose interrupt 1. */ + kMU_GenInt2InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 1U)), /*!< General purpose interrupt 2. */ + kMU_GenInt3InterruptTrigger = (1U << (MU_CR_GIRn_SHIFT + 0U)) /*!< General purpose interrupt 3. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name MU initialization. + * @{ + */ +/*! + * @brief Initializes the MU module. + * + * This function enables the MU clock only. + * + * @param base MU peripheral base address. + */ +void MU_Init(MU_Type *base); + +/*! + * @brief De-initializes the MU module. + * + * This function disables the MU clock only. + * + * @param base MU peripheral base address. + */ +void MU_Deinit(MU_Type *base); + +/** @} */ + +/*! + * @name MU Message + * @{ + */ + +/*! + * @brief Writes a message to the TX register. + * + * This function writes a message to the specific TX register. It does not check + * whether the TX register is empty or not. The upper layer should make sure the TX + * register is empty before calling this function. This function can be used + * in ISR for better performance. + * + * @code + * while (!(kMU_Tx0EmptyFlag & MU_GetStatusFlags(base))) { } Wait for TX0 register empty. + * MU_SendMsgNonBlocking(base, 0U, MSG_VAL); Write message to the TX0 register. + * @endcode + * + * @param base MU peripheral base address. + * @param regIndex TX register index. + * @param msg Message to send. + */ +static inline void MU_SendMsgNonBlocking(MU_Type *base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + + base->TR[regIndex] = msg; +} + +/*! + * @brief Blocks to send a message. + * + * This function waits until the TX register is empty and sends the message. + * + * @param base MU peripheral base address. + * @param regIndex TX register index. + * @param msg Message to send. + */ +void MU_SendMsg(MU_Type *base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Reads a message from the RX register. + * + * This function reads a message from the specific RX register. It does not check + * whether the RX register is full or not. The upper layer should make sure the RX + * register is full before calling this function. This function can be used + * in ISR for better performance. + * + * @code + * uint32_t msg; + * while (!(kMU_Rx0FullFlag & MU_GetStatusFlags(base))) + * { + * } Wait for the RX0 register full. + * + * msg = MU_ReceiveMsgNonBlocking(base, 0U); Read message from RX0 register. + * @endcode + * + * @param base MU peripheral base address. + * @param regIndex TX register index. + * @return The received message. + */ +static inline uint32_t MU_ReceiveMsgNonBlocking(MU_Type *base, uint32_t regIndex) +{ + assert(regIndex < MU_TR_COUNT); + + return base->RR[regIndex]; +} + +/*! + * @brief Blocks to receive a message. + * + * This function waits until the RX register is full and receives the message. + * + * @param base MU peripheral base address. + * @param regIndex RX register index. + * @return The received message. + */ +uint32_t MU_ReceiveMsg(MU_Type *base, uint32_t regIndex); + +/** @} */ + +/*! + * @name MU Flags + * @{ + */ + +/*! + * @brief Sets the 3-bit MU flags reflect on the other MU side. + * + * This function sets the 3-bit MU flags directly. Every time the 3-bit MU flags are changed, + * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are + * updating to the other side. After the 3-bit MU flags are updated, the status flag + * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, + * the flags cannot be changed. The upper layer should make sure the status flag + * \c kMU_FlagsUpdatingFlag is cleared before calling this function. + * + * @code + * while (kMU_FlagsUpdatingFlag & MU_GetStatusFlags(base)) + * { + * } Wait for previous MU flags updating. + * + * MU_SetFlagsNonBlocking(base, 0U); Set the mU flags. + * @endcode + * + * @param base MU peripheral base address. + * @param flags The 3-bit MU flags to set. + */ +static inline void MU_SetFlagsNonBlocking(MU_Type *base, uint32_t flags) +{ + uint32_t reg = base->CR; + reg = (reg & ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | MU_CR_Fn_MASK)) | MU_CR_Fn(flags); + base->CR = reg; +} + +/*! + * @brief Blocks setting the 3-bit MU flags reflect on the other MU side. + * + * This function blocks setting the 3-bit MU flags. Every time the 3-bit MU flags are changed, + * the status flag \c kMU_FlagsUpdatingFlag asserts indicating the 3-bit MU flags are + * updating to the other side. After the 3-bit MU flags are updated, the status flag + * \c kMU_FlagsUpdatingFlag is cleared by hardware. During the flags updating period, + * the flags cannot be changed. This function waits for the MU status flag + * \c kMU_FlagsUpdatingFlag cleared and sets the 3-bit MU flags. + * + * @param base MU peripheral base address. + * @param flags The 3-bit MU flags to set. + */ +void MU_SetFlags(MU_Type *base, uint32_t flags); + +/*! + * @brief Gets the current value of the 3-bit MU flags set by the other side. + * + * This function gets the current 3-bit MU flags on the current side. + * + * @param base MU peripheral base address. + * @return flags Current value of the 3-bit flags. + */ +static inline uint32_t MU_GetFlags(MU_Type *base) +{ + return (base->SR & MU_SR_Fn_MASK) >> MU_SR_Fn_SHIFT; +} + +/** @} */ + +/*! + * @name Status and Interrupt. + * @{ + */ + +/*! + * @brief Gets the MU status flags. + * + * This function returns the bit mask of the MU status flags. See _mu_status_flags. + * + * @code + * uint32_t flags; + * flags = MU_GetStatusFlags(base); Get all status flags. + * if (kMU_Tx0EmptyFlag & flags) + * { + * The TX0 register is empty. Message can be sent. + * MU_SendMsgNonBlocking(base, 0U, MSG0_VAL); + * } + * if (kMU_Tx1EmptyFlag & flags) + * { + * The TX1 register is empty. Message can be sent. + * MU_SendMsgNonBlocking(base, 1U, MSG1_VAL); + * } + * @endcode + * + * @param base MU peripheral base address. + * @return Bit mask of the MU status flags, see _mu_status_flags. + */ +static inline uint32_t MU_GetStatusFlags(MU_Type *base) +{ + return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_MASK +#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) + | MU_SR_RS_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + | MU_SR_RAIP_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + | MU_SR_RDIP_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + | MU_SR_MURIP_MASK +#endif +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + | MU_SR_HRIP_MASK +#endif + )); +} + +/*! + * @brief Gets the MU IRQ pending status. + * + * This function returns the bit mask of the pending MU IRQs. + * + * @param base MU peripheral base address. + * @return Bit mask of the MU IRQs pending. + */ +static inline uint32_t MU_GetInterruptsPending(MU_Type *base) +{ + uint32_t irqMask = base->CR & (MU_CR_GIRn_MASK | MU_CR_TIEn_MASK | MU_CR_RIEn_MASK); + return (base->SR & irqMask); +} + +/*! + * @brief Clears the specific MU status flags. + * + * This function clears the specific MU status flags. The flags to clear should + * be passed in as bit mask. See _mu_status_flags. + * + * @code + * Clear general interrupt 0 and general interrupt 1 pending flags. + * MU_ClearStatusFlags(base, kMU_GenInt0Flag | kMU_GenInt1Flag); + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the MU status flags. See _mu_status_flags. The following + * flags are cleared by hardware, this function could not clear them. + * - kMU_Tx0EmptyFlag + * - kMU_Tx1EmptyFlag + * - kMU_Tx2EmptyFlag + * - kMU_Tx3EmptyFlag + * - kMU_Rx0FullFlag + * - kMU_Rx1FullFlag + * - kMU_Rx2FullFlag + * - kMU_Rx3FullFlag + * - kMU_EventPendingFlag + * - kMU_FlagsUpdatingFlag + * - kMU_OtherSideInResetFlag + */ +static inline void MU_ClearStatusFlags(MU_Type *base, uint32_t mask) +{ + /* regMask is the mask of w1c status bits. */ + uint32_t regMask = MU_SR_GIPn_MASK; + +#if (defined(FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + regMask |= MU_SR_RAIP_MASK; +#endif +#if (defined(FSL_FEATURE_MU_HAS_RESET_DEASSERT_INT) && FSL_FEATURE_MU_HAS_RESET_ASSERT_INT) + regMask |= MU_SR_RDIP_MASK; +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_MURIP) && FSL_FEATURE_MU_HAS_SR_MURIP) + regMask |= MU_SR_MURIP_MASK; +#endif + +#if (defined(FSL_FEATURE_MU_HAS_SR_HRIP) && FSL_FEATURE_MU_HAS_SR_HRIP) + regMask |= MU_SR_HRIP_MASK; +#endif + + base->SR = (mask & regMask); +} + +/*! + * @brief Enables the specific MU interrupts. + * + * This function enables the specific MU interrupts. The interrupts to enable + * should be passed in as bit mask. See _mu_interrupt_enable. + * + * @code + * Enable general interrupt 0 and TX0 empty interrupt. + * MU_EnableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. + */ +static inline void MU_EnableInterrupts(MU_Type *base, uint32_t mask) +{ + uint32_t reg = base->CR; + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | mask; + base->CR = reg; +} + +/*! + * @brief Disables the specific MU interrupts. + * + * This function disables the specific MU interrupts. The interrupts to disable + * should be passed in as bit mask. See _mu_interrupt_enable. + * + * @code + * Disable general interrupt 0 and TX0 empty interrupt. + * MU_DisableInterrupts(base, kMU_GenInt0InterruptEnable | kMU_Tx0EmptyInterruptEnable); + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the MU interrupts. See _mu_interrupt_enable. + */ +static inline void MU_DisableInterrupts(MU_Type *base, uint32_t mask) +{ + uint32_t reg = base->CR; + reg &= ~((MU_CR_GIRn_MASK | MU_CR_NMI_MASK) | mask); + base->CR = reg; +} + +/*! + * @brief Triggers interrupts to the other core. + * + * This function triggers the specific interrupts to the other core. The interrupts + * to trigger are passed in as bit mask. See \ref _mu_interrupt_trigger. + * The MU should not trigger an interrupt to the other core when the previous interrupt + * has not been processed by the other core. This function checks whether the + * previous interrupts have been processed. If not, it returns an error. + * + * @code + * if (kStatus_Success != MU_TriggerInterrupts(base, kMU_GenInt0InterruptTrigger | kMU_GenInt2InterruptTrigger)) + * { + * Previous general purpose interrupt 0 or general purpose interrupt 2 + * has not been processed by the other core. + * } + * @endcode + * + * @param base MU peripheral base address. + * @param mask Bit mask of the interrupts to trigger. See _mu_interrupt_trigger. + * @retval kStatus_Success Interrupts have been triggered successfully. + * @retval kStatus_Fail Previous interrupts have not been accepted. + */ +status_t MU_TriggerInterrupts(MU_Type *base, uint32_t mask); + +#if !(defined(FSL_FEATURE_MU_NO_NMI) && FSL_FEATURE_MU_NO_NMI) +/*! + * @brief Clear non-maskable interrupt (NMI) sent by the other core. + * + * This function clears non-maskable interrupt (NMI) sent by the other core. + * + * @param base MU peripheral base address. + */ +static inline void MU_ClearNmi(MU_Type *base) +{ + base->SR = MU_SR_NMIC_MASK; +} +#endif /* FSL_FEATURE_MU_NO_NMI */ + +/** @} */ + +/*! + * @name MU misc functions + * @{ + */ + +#if !(defined(FSL_FEATURE_MU_NO_RSTH) && FSL_FEATURE_MU_NO_RSTH) +/*! + * @brief Boots the core at B side. + * + * This function sets the B side core's boot configuration and releases the + * core from reset. + * + * @param base MU peripheral base address. + * @param mode Core B boot mode. + * @note Only MU side A can use this function. + */ +void MU_BootCoreB(MU_Type *base, mu_core_boot_mode_t mode); + +/*! + * @brief Holds the core reset of B side. + * + * This function causes the core of B side to be held in reset following any reset event. + * + * @param base MU peripheral base address. + * @note Only A side could call this function. + */ +static inline void MU_HoldCoreBReset(MU_Type *base) +{ +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + base->CCR |= MU_CCR_RSTH_MASK; +#else /* FSL_FEATURE_MU_HAS_CCR */ + uint32_t reg = base->CR; + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_RSTH_MASK; + base->CR = reg; +#endif /* FSL_FEATURE_MU_HAS_CCR */ +} + +/*! + * @brief Boots the other core. + * + * This function boots the other core with a boot configuration. + * + * @param base MU peripheral base address. + * @param mode The other core boot mode. + */ +void MU_BootOtherCore(MU_Type *base, mu_core_boot_mode_t mode); + +/*! + * @brief Holds the other core reset. + * + * This function causes the other core to be held in reset following any reset event. + * + * @param base MU peripheral base address. + */ +static inline void MU_HoldOtherCoreReset(MU_Type *base) +{ + /* + * MU_HoldOtherCoreReset and MU_HoldCoreBReset are the same, MU_HoldCoreBReset + * is kept for compatible with older platforms. + */ + MU_HoldCoreBReset(base); +} +#endif /* FSL_FEATURE_MU_NO_RSTH */ + +#if !(defined(FSL_FEATURE_MU_NO_MUR) && FSL_FEATURE_MU_NO_MUR) +/*! + * @brief Resets the MU for both A side and B side. + * + * This function resets the MU for both A side and B side. Before reset, it is + * recommended to interrupt processor B, because this function may affect the + * ongoing processor B programs. + * + * @param base MU peripheral base address. + * @note For some platforms, only MU side A could use this function, check + * reference manual for details. + */ +static inline void MU_ResetBothSides(MU_Type *base) +{ + uint32_t reg = base->CR; + reg = (reg & ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK)) | MU_CR_MUR_MASK; + base->CR = reg; + +#if (defined(FSL_FEATURE_MU_HAS_SR_RS) && FSL_FEATURE_MU_HAS_SR_RS) + /* Wait for the other side out of reset. */ + while (0U != (base->SR & MU_SR_RS_MASK)) + { + } +#endif /* FSL_FEATURE_MU_HAS_SR_RS */ +} +#endif /* FSL_FEATURE_MU_NO_MUR */ + +#if (defined(FSL_FEATURE_MU_HAS_HRM) && FSL_FEATURE_MU_HAS_HRM) +/*! + * @brief Mask hardware reset by the other core. + * + * The other core could call MU_HardwareResetOtherCore() to reset current core. + * To mask the reset, call this function and pass in true. + * + * @param base MU peripheral base address. + * @param mask Pass true to mask the hardware reset, pass false to unmask it. + */ +static inline void MU_MaskHardwareReset(MU_Type *base, bool mask) +{ +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + if (mask) + { + base->CCR |= MU_CCR_HRM_MASK; + } + else + { + base->CCR &= ~MU_CCR_HRM_MASK; + } +#else /* FSL_FEATURE_MU_HAS_CCR */ + if (mask) + { + base->CR |= MU_CR_HRM_MASK; + } + else + { + base->CR &= ~MU_CR_HRM_MASK; + } +#endif /* FSL_FEATURE_MU_HAS_CCR */ +} +#endif /* FSL_FEATURE_MU_HAS_HRM */ + +#if !(defined(FSL_FEATURE_MU_NO_HR) && FSL_FEATURE_MU_NO_HR) +/*! + * @brief Hardware reset the other core. + * + * This function resets the other core, the other core could mask the + * hardware reset by calling MU_MaskHardwareReset. The hardware reset + * mask feature is only available for some platforms. + * This function could be used together with MU_BootOtherCore to control the + * other core reset workflow. + * + * Example 1: Reset the other core, and no hold reset + * @code + * MU_HardwareResetOtherCore(MU_A, true, false, bootMode); + * @endcode + * In this example, the core at MU side B will reset with the specified boot mode. + * + * Example 2: Reset the other core and hold it, then boot the other core later. + * @code + * Here the other core enters reset, and the reset is hold + * MU_HardwareResetOtherCore(MU_A, true, true, modeDontCare); + * Current core boot the other core when necessary. + * MU_BootOtherCore(MU_A, bootMode); + * @endcode + * + * @param base MU peripheral base address. + * @param waitReset Wait the other core enters reset. + * - true: Wait until the other core enters reset, if the other + * core has masked the hardware reset, then this function will + * be blocked. + * - false: Don't wait the reset. + * @param holdReset Hold the other core reset or not. + * - true: Hold the other core in reset, this function returns + * directly when the other core enters reset. + * - false: Don't hold the other core in reset, this function + * waits until the other core out of reset. + * @param bootMode Boot mode of the other core, if @p holdReset is true, this + * parameter is useless. + */ +void MU_HardwareResetOtherCore(MU_Type *base, bool waitReset, bool holdReset, mu_core_boot_mode_t bootMode); +#endif /* FSL_FEATURE_MU_NO_HR */ + +#if !(defined(FSL_FEATURE_MU_NO_CLKE) && FSL_FEATURE_MU_NO_CLKE) +/*! + * @brief Enables or disables the clock on the other core. + * + * This function enables or disables the platform clock on the other core when + * that core enters a stop mode. If disabled, the platform clock for the other + * core is disabled when it enters stop mode. If enabled, the platform clock + * keeps running on the other core in stop mode, until this core also enters + * stop mode. + * + * @param base MU peripheral base address. + * @param enable Enable or disable the clock on the other core. + */ +static inline void MU_SetClockOnOtherCoreEnable(MU_Type *base, bool enable) +{ +#if (defined(FSL_FEATURE_MU_HAS_CCR) && FSL_FEATURE_MU_HAS_CCR) + if (enable) + { + base->CCR |= MU_CCR_CLKE_MASK; + } + else + { + base->CCR &= ~MU_CCR_CLKE_MASK; + } +#else /* FSL_FEATURE_MU_HAS_CCR */ + uint32_t reg = base->CR; + + reg &= ~(MU_CR_GIRn_MASK | MU_CR_NMI_MASK); + + if (enable) + { + reg |= MU_CR_CLKE_MASK; + } + else + { + reg &= ~MU_CR_CLKE_MASK; + } + + base->CR = reg; +#endif /* FSL_FEATURE_MU_HAS_CCR */ +} +#endif /* FSL_FEATURE_MU_NO_CLKE */ + +#if !(defined(FSL_FEATURE_MU_NO_PM) && FSL_FEATURE_MU_NO_PM) +/*! + * @brief Gets the power mode of the other core. + * + * This function gets the power mode of the other core. + * + * @param base MU peripheral base address. + * @return Power mode of the other core. + */ +static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type *base) +{ + uint32_t ret = (base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT; + + return (mu_power_mode_t)ret; +} +#endif /* FSL_FEATURE_MU_NO_PM */ + +/** @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/** @} */ + +#endif /* _FSL_MU_H_*/ diff --git a/platform/drivers/nic400/Makefile b/platform/drivers/nic400/Makefile new file mode 100644 index 0000000..4d1f9a8 --- /dev/null +++ b/platform/drivers/nic400/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/nic400/fsl_nic400.o + +DIRS += $(OUT)/drivers/nic400 + diff --git a/platform/drivers/nic400/fsl_nic400.h b/platform/drivers/nic400/fsl_nic400.h new file mode 100755 index 0000000..2828f75 --- /dev/null +++ b/platform/drivers/nic400/fsl_nic400.h @@ -0,0 +1,98 @@ +/* + * Copyright 2017-2019 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FSL_NIC400_H +#define FSL_NIC400_H + +#include "fsl_common.h" + +/*! + * @addtogroup nic400_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +/*! @brief NIC400 driver version 1.0.0. */ +#define FSL_NIC400_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/** @} */ + +/*! @brief NIC400 Master interface base offset. */ +#define NIC400_MSTR_INTF_OFFSET 0x00002000U + +/*! @brief NIC400 Slave interface base offset. */ +#define NIC400_SLV_INTF_OFFSET 0x00042000U + +/*! @brief NIC400 Internal interface base offset. */ +#define NIC400_INT_INTF_OFFSET 0x000C2000U + +/*! @brief NIC400 Slave interface size. */ +#define NIC400_SLV_INTF_BLKSZ 0x00001000U + +/*! @brief NIC400 Max index of Slave interface. */ +#define NIC400_MAX_SLV_INTF_IDX 127U + +#define NIC400_ASIB_READ_QOS_REG 0x100U +#define NIC400_ASIB_WRITE_QOS_REG 0x104U +#define NIC400_ASIB_FN_MOD_REG 0x108U + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Set NIC400 ASIB register. + */ +void NIC400_Set_ASIB(uint32_t base, uint8_t slave_num, + uint16_t register_offset, uint8_t val); + +/*! + * @brief Get NIC400 ASIB register. + */ +uint32_t NIC400_Get_ASIB(uint32_t base, uint8_t slave_num, + uint16_t register_offset); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_NIC400_H */ + diff --git a/platform/drivers/otp/Makefile b/platform/drivers/otp/Makefile new file mode 100755 index 0000000..646211c --- /dev/null +++ b/platform/drivers/otp/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/otp/fsl_otp.o + +DIRS += $(OUT)/drivers/otp + diff --git a/platform/drivers/otp/fsl_otp.h b/platform/drivers/otp/fsl_otp.h new file mode 100755 index 0000000..41eb615 --- /dev/null +++ b/platform/drivers/otp/fsl_otp.h @@ -0,0 +1,60 @@ +/* + * Copyright 2017-2019 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_OTP_H +#define DRV_OTP_H + +/*! + * @addtogroup otp_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "svc/misc/api.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +sc_err_t OTP_Read(OTP_Type *base, uint32_t word, uint32_t *val); +sc_err_t OTP_Write(OTP_Type *base, uint32_t word, const uint32_t *val); +sc_err_t OTP_Set_Fuse(uint32_t word, const uint32_t *val); +sc_err_t OTP_Get_Fuse(uint32_t word, uint32_t *val); +sc_err_t OTP_Check_Locked(uint32_t word, sc_bool_t *locked); + +#endif /* DRV_OTP_H */ + +/** @} */ + diff --git a/platform/drivers/pad/Makefile b/platform/drivers/pad/Makefile new file mode 100755 index 0000000..e1df43d --- /dev/null +++ b/platform/drivers/pad/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/pad/fsl_pad.o + +DIRS += $(OUT)/drivers/pad + diff --git a/platform/drivers/pad/fsl_pad.h b/platform/drivers/pad/fsl_pad.h new file mode 100755 index 0000000..66c8d15 --- /dev/null +++ b/platform/drivers/pad/fsl_pad.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_PAD_H +#define DRV_PAD_H + +/*! + * @addtogroup pad_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "fsl_device_registers.h" + +/* Defines */ + +/*! + * This define is used to access PAD registers. + */ +#ifdef NO_DEVICE_ACCESS + #define PAD_BASE_ADDR ((PADRING_Type*) (temp_pad)) +#else + #define PAD_BASE_ADDR ((PADRING_Type*) (PAD_BASE)) +#endif + +/* Types */ + +/* Externs */ + +#ifdef NO_DEVICE_ACCESS + /*! + * This variable is used to access fake pads. + */ + extern uint8_t temp_pad[]; +#endif + +/* Functions */ + +void PAD_Init(void); +uint8_t PAD_ExtractMux(uint32_t val); +void PAD_Set(sc_saddr_t ofs, uint32_t val); +void PAD_Get(sc_saddr_t ofs, uint32_t *val); +void PAD_SetMux(sc_saddr_t ofs, uint8_t mux, uint8_t config, + uint8_t iso); +void PAD_GetMux(sc_saddr_t ofs, uint8_t *mux, uint8_t *config, + uint8_t *iso); +void PAD_SetGP(sc_saddr_t ofs, uint32_t ctrl); +void PAD_GetGP(sc_saddr_t ofs, uint32_t *ctrl); +#if FSL_FEATURE_PAD_HAS_28FDSOI +void PAD_SetGP28Fdsoi(sc_saddr_t ofs, uint8_t dse, uint8_t ps); +void PAD_GetGP28Fdsoi(sc_saddr_t ofs, uint8_t *dse, uint8_t *ps); +void PAD_SetGP28FdsoiHsic(sc_saddr_t ofs, uint8_t dse, sc_bool_t hys, + uint8_t pus, sc_bool_t pke, sc_bool_t pue); +void PAD_GetGP28FdsoiHsic(sc_saddr_t ofs, uint8_t *dse, sc_bool_t *hys, + uint8_t *pus, sc_bool_t *pke, sc_bool_t *pue); +void PAD_SetGP28FdsoiComp(sc_saddr_t ofs, uint8_t compen, sc_bool_t fastfrz, + uint8_t rasrcp, uint8_t rasrcn, sc_bool_t nasrc_sel, sc_bool_t psw_ovr); +void PAD_GetGP28FdsoiComp(sc_saddr_t ofs, uint8_t *compen, sc_bool_t *fastfrz, + uint8_t *rasrcp, uint8_t *rasrcn, sc_bool_t *nasrc_sel, sc_bool_t *compok, + uint8_t *nasrc, sc_bool_t *psw_ovr); +#endif +void PAD_SetWakeup(sc_saddr_t ofs, uint8_t wakeup); +void PAD_GetWakeup(sc_saddr_t ofs, uint8_t *wakeup); +void PAD_SetAll(sc_saddr_t ofs, uint8_t mux, uint8_t config, + uint8_t iso, uint32_t ctrl, uint8_t wakeup); +void PAD_GetAll(sc_saddr_t ofs, uint8_t *mux, uint8_t *config, + uint8_t *iso, uint32_t *ctrl, uint8_t *wakeup); + +#ifdef DEBUG + /*! + * @name Debug Functions + * @{ + */ + + /*! + * This function dumps the pads. It's only used for debug. Should + * only be called if the power domain containing the PAD is powered on. + */ + void PAD_Dump(void); + + /** @} */ +#endif + +#endif /* DRV_PAD_H */ + +/** @} */ + diff --git a/platform/drivers/pmic/Makefile b/platform/drivers/pmic/Makefile new file mode 100755 index 0000000..4010ffc --- /dev/null +++ b/platform/drivers/pmic/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/pmic/fsl_pmic.o + +DIRS += $(OUT)/drivers/pmic + diff --git a/platform/drivers/pmic/doxygen/fsl_pmic.dox b/platform/drivers/pmic/doxygen/fsl_pmic.dox new file mode 100755 index 0000000..4d0e8a2 --- /dev/null +++ b/platform/drivers/pmic/doxygen/fsl_pmic.dox @@ -0,0 +1,9 @@ +/*! +@defgroup pmic_driver PMIC: Power Management IC Driver +Module for the PMIC driver. + +@details It is an SDK driver for the PMIC module of i.MX devices. PMIC users +shoud not call the PMIC driver functions directly. Instead, use the PMIC access +macros. This allows for quick PMIC change and dynamic PMIC binding. + +*/ diff --git a/platform/drivers/pmic/fsl_pmic.c b/platform/drivers/pmic/fsl_pmic.c new file mode 100755 index 0000000..b0c0a1a --- /dev/null +++ b/platform/drivers/pmic/fsl_pmic.c @@ -0,0 +1,637 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "fsl_device_registers.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "fsl_common.h" + +/* Local Defines */ +#define MAX_DATA_LENGTH 8U +#define POLY 0x1DU /* SAE J1850 Polynomial */ + +/* Local Functions */ + +uint8_t pf8x00_crc_data(uint8_t addr, uint8_t reg, const uint8_t * const data, + uint32_t msg_size); + +/* Local Variables */ + +/*--------------------------------------------------------------------------*/ +/* Write to the PMIC via the I2C */ +/*--------------------------------------------------------------------------*/ +status_t i2c_write_sub(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength) +{ + status_t status = I32(kStatus_Success); + size_t rx, tx; + + do + { + /* Send start and device address */ + status = LPI2C_MasterStart(LPI2C_PMIC, device_addr, + kLPI2C_Write); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* Send register address */ + status = LPI2C_MasterSend(LPI2C_PMIC, ®, 1); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* Send data */ + status = LPI2C_MasterSend(LPI2C_PMIC, data, dataLength); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* Send stop */ + status = LPI2C_MasterStop(LPI2C_PMIC); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* FIFO empty barrier */ + do + { + LPI2C_MasterGetFifoCounts(LPI2C_PMIC, &rx, &tx); + } + while(tx > 0U); + /* if we get this far we have succeeded */ + } while (SC_FALSE); + + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Write to the PMIC via the I2C (with clock management) */ +/*--------------------------------------------------------------------------*/ +status_t i2c_write(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength) +{ +#ifdef SC_MANAGE_LPI2C_CLK + // Enable clocking using LPCG + if (LPI2C_PMIC == LPI2C_SC) + { + CLOCK_EnableClockEx(kCLOCK_LPI2C_SC); + } + + // Do the transfer + status_t stat = i2c_write_sub(device_addr, reg, data, dataLength); + + if(stat != I32(kStatus_Success))/* do a MasterStop if we ever fail */ + { + pmic_print(1, "I2C Error: %d \n", stat); + (void) LPI2C_MasterStop(LPI2C_PMIC); + } + + if (LPI2C_PMIC == LPI2C_SC) + { + // Enter exclusive attempt to disable clock + uint32_t lpcgVal = CLOCK_DisableClockExEnter(kCLOCK_LPI2C_SC); + + // Check if conditions allow clock gating + if (!LPI2C_MasterGetBusIdleState(LPI2C_PMIC)) + { + // Mask to disable IPG and BAUD clocks + uint32_t lpcgMask = ~(BIT(LPCG__SS_SCU__IPG_CLK__SWEN) | + BIT(LPCG__SS_SCU__PER_CLK__SWEN)); + + lpcgVal &= lpcgMask; + } + + // Leave exclusive attempt to disable clock + CLOCK_DisableClockExLeave(kCLOCK_LPI2C_SC, lpcgVal); + } + + return stat; +#else + return i2c_write_sub(device_addr, reg, data, dataLength); +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Write to the PMIC via the I2C with CRC and clock management */ +/*--------------------------------------------------------------------------*/ +status_t i2c_j1850_write(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength) +{ status_t status = I32(kStatus_Success); + uint8_t crc; + size_t rx,tx; + +#ifdef SC_MANAGE_LPI2C_CLK + // Enable clocking using LPCG + if (LPI2C_PMIC == LPI2C_SC) + { + CLOCK_EnableClockEx(kCLOCK_LPI2C_SC); + } +#endif + /* calculate the CRC for data */ + crc = pf8x00_crc_data((device_addr << 1), reg, data, dataLength); + + // Do the transfer + do + { /* use a do while loop to jump out if error */ + + status = LPI2C_MasterStart(LPI2C_PMIC, device_addr, kLPI2C_Write); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterSend(LPI2C_PMIC, ®, 1); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterSend(LPI2C_PMIC, data, dataLength); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterSend(LPI2C_PMIC, &crc, 1); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterStop(LPI2C_PMIC); + if (status != I32(kStatus_Success)) + { + break; + } + + do/* FIFO empty barrier */ + { + LPI2C_MasterGetFifoCounts(LPI2C_PMIC, &rx, &tx); + } + while(tx>0U); + /* if we got here we succeeded */ + } while (SC_FALSE); + + if (status != I32(kStatus_Success)) + { + pmic_print(1, "LPI2C error kStatus = %x", status); + (void)LPI2C_MasterStop(LPI2C_PMIC); + } + +#ifdef SC_MANAGE_LPI2C_CLK + // Disable Clock after write + if (LPI2C_PMIC == LPI2C_SC) + { + // Enter exclusive attempt to disable clock + uint32_t lpcgVal = CLOCK_DisableClockExEnter(kCLOCK_LPI2C_SC); + + // Check if conditions allow clock gating + if (!LPI2C_MasterGetBusIdleState(LPI2C_PMIC)) + { + // Mask to disable IPG and BAUD clocks + uint32_t lpcgMask = ~(BIT(LPCG__SS_SCU__IPG_CLK__SWEN) | + BIT(LPCG__SS_SCU__PER_CLK__SWEN)); + + lpcgVal &= lpcgMask; + } + + // Leave exclusive attempt to disable clock + CLOCK_DisableClockExLeave(kCLOCK_LPI2C_SC, lpcgVal); + } +#endif + + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Read from the PMIC via the I2C with CRC and clock management */ +/*--------------------------------------------------------------------------*/ +status_t i2c_j1850_read(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength) +{ + status_t status = I32(kStatus_Success); + + if (dataLength > MAX_DATA_LENGTH) + { + status = I32(kStatus_OutOfRange); + } + else + { + uint32_t flags; + uint8_t crc; + uint8_t buff[MAX_DATA_LENGTH + 1U]; + + /* Init CRC */ + buff[dataLength] = 0U; + +#ifdef SC_MANAGE_LPI2C_CLK + // Enable clocking using LPCG + if (LPI2C_PMIC == LPI2C_SC) + { + CLOCK_EnableClockEx(kCLOCK_LPI2C_SC); + } +#endif + + /* Calculate the CRC for address + register */ + crc = pf8x00_crc_data(((device_addr << 1) | 0x1U), reg, data, 0U); + + // Do the transfer + do + {/* use a true while loop to jump out if error */ + + status = LPI2C_MasterStart(LPI2C_PMIC, device_addr, kLPI2C_Write); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterSend(LPI2C_PMIC, ®, 1); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterSend(LPI2C_PMIC, &crc, 1); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterStart(LPI2C_PMIC, device_addr, kLPI2C_Read); + if (status != I32(kStatus_Success)) + { + break; + } + + status = LPI2C_MasterReceive(LPI2C_PMIC, buff, dataLength + 1U); + if (status != I32(kStatus_Success)) { break;} + + while (SC_TRUE) + { + flags = LPI2C_MasterGetStatusFlags(LPI2C_PMIC); + + if ((flags & U32(kLPI2C_MasterNackDetectFlag)) == 0U) + { + break; + } + + if ((flags & i2c_error_flags) != 0U) + { + pmic_print(1, "i2c error flag: %d \n", flags); + } + } + + status = LPI2C_MasterStop(LPI2C_PMIC); + /* if we got here we succeeded */ + } while (SC_FALSE); + + /* Calculate CRC with data returned and check for validity */ + crc = pf8x00_crc_data(((device_addr << 1) | 0x1U), reg, buff, dataLength); + if (crc != buff[dataLength]) + { + status = I32(kStatus_Fail); + pmic_print(1,"CRC returned not correct got %x expected %x\n", + buff[dataLength], crc); + } + + if (status != I32(kStatus_Success)) + { + pmic_print(1, "LPI2C error kStatus = %x", status); + (void)LPI2C_MasterStop(LPI2C_PMIC); + } + else + { + /* Copy out data */ + uint8_t *ptr = (uint8_t*) data; + + for (uint8_t index = 0U; index < dataLength; index++) + { + ptr[index] = buff[index]; + } + } + +#ifdef SC_MANAGE_LPI2C_CLK + // Disable Clock after write + if (LPI2C_PMIC == LPI2C_SC) + { + // Enter exclusive attempt to disable clock + uint32_t lpcgVal = CLOCK_DisableClockExEnter(kCLOCK_LPI2C_SC); + + // Check if conditions allow clock gating + if (!LPI2C_MasterGetBusIdleState(LPI2C_PMIC)) + { + // Mask to disable IPG and BAUD clocks + uint32_t lpcgMask = ~(BIT(LPCG__SS_SCU__IPG_CLK__SWEN) | + BIT(LPCG__SS_SCU__PER_CLK__SWEN)); + + lpcgVal &= lpcgMask; + } + + // Leave exclusive attempt to disable clock + CLOCK_DisableClockExLeave(kCLOCK_LPI2C_SC, lpcgVal); + } +#endif + } + + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Read from the PMIC via I2C */ +/*--------------------------------------------------------------------------*/ +status_t i2c_read_sub(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength) +{ + status_t status = I32(kStatus_Success); + uint32_t flags; + + do + { + /* Send start and device address */ + status = LPI2C_MasterStart(LPI2C_PMIC, device_addr, kLPI2C_Write); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* Send register */ + status = LPI2C_MasterSend(LPI2C_PMIC, ®, 1); + /* Check for error */ + if (status != I32(kStatus_Success) ) + { + break; + } + + /* Read response address */ + status = LPI2C_MasterStart(LPI2C_PMIC, device_addr, kLPI2C_Read); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* Read data */ + status = LPI2C_MasterReceive(LPI2C_PMIC, data, dataLength); + /* Check for error */ + if (status != I32(kStatus_Success)) + { + break; + } + + /* Check for error */ + while (SC_TRUE) + { + flags = LPI2C_MasterGetStatusFlags(LPI2C_PMIC); + + if ((flags & U32(kLPI2C_MasterNackDetectFlag)) == 0U) + { + break; + } + + if ((flags & i2c_error_flags) != 0U) + { + pmic_print(1, "i2c error flag: %d \n", flags); + } + } + /* Stop transfer */ + status = LPI2C_MasterStop(LPI2C_PMIC); + /* if we got here we had a succesful read */ + } while (SC_FALSE); + + return status; +} + +/*--------------------------------------------------------------------------*/ +/* Read from the PMIC via I2C (with clock management) */ +/*--------------------------------------------------------------------------*/ +status_t i2c_read(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength) +{ +#ifdef SC_MANAGE_LPI2C_CLK + // Enable clocking using LPCG + if (LPI2C_PMIC == LPI2C_SC) + { + CLOCK_EnableClockEx(kCLOCK_LPI2C_SC); + } + + // Do the transfer + status_t stat = i2c_read_sub(device_addr, reg, data, dataLength); + + if(stat != I32(kStatus_Success))/* do a MasterStop if we ever fail */ + { + pmic_print(1, "I2C error : %d \n", stat); + (void) LPI2C_MasterStop(LPI2C_PMIC); + } + + if (LPI2C_PMIC == LPI2C_SC) + { + // Enter exclusive attempt to disable clock + uint32_t lpcgVal = CLOCK_DisableClockExEnter(kCLOCK_LPI2C_SC); + + // Check if conditions allow clock gating + if (!LPI2C_MasterGetBusIdleState(LPI2C_PMIC)) + { + // Mask to disable IPG and BAUD clocks + uint32_t lpcgMask = ~(BIT(LPCG__SS_SCU__IPG_CLK__SWEN) | + BIT(LPCG__SS_SCU__PER_CLK__SWEN)); + + lpcgVal &= lpcgMask; + } + + // Leave exclusive attempt to disable clock + CLOCK_DisableClockExLeave(kCLOCK_LPI2C_SC, lpcgVal); + } + + return stat; +#else + return i2c_read_sub(device_addr, reg, data, dataLength); +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC device ID */ +/*--------------------------------------------------------------------------*/ +uint8_t pmic_get_device_id(uint8_t address) +{ + status_t status; + uint32_t flags; + uint8_t dev_id_read = 0U; + uint8_t dev_reg = 0U; + + #ifdef SC_MANAGE_LPI2C_CLK + // Enable clocking using LPCG + if (LPI2C_PMIC == LPI2C_SC) + { + CLOCK_EnableClockEx(kCLOCK_LPI2C_SC); + } + #endif + + do + { + /* Send master blocking data to slave */ + status = LPI2C_MasterStart(LPI2C_PMIC, address, kLPI2C_Write); + if (status != I32(kStatus_Success)) /* check if status valid */ + { + break; + } + + status = LPI2C_MasterSend(LPI2C_PMIC, &dev_reg, 1);/* send reg 0 address */ + if (status != I32(kStatus_Success)) /* check if status valid */ + { + break; + } + + status = LPI2C_MasterStart(LPI2C_PMIC, address, kLPI2C_Read); + if (status != I32(kStatus_Success)) /* check if status valid */ + { + break; + } + + status = LPI2C_MasterReceive(LPI2C_PMIC, &dev_id_read, 1); + if (status != I32(kStatus_Success)) /* check if status valid */ + { + break; + } + + while (SC_TRUE) + { + flags = LPI2C_MasterGetStatusFlags(LPI2C_PMIC); + + if ((flags & U32(kLPI2C_MasterNackDetectFlag)) == 0U) + { + break; + } + + if ((flags & i2c_error_flags) != 0U) + { + pmic_print(1, "i2c error flag: %d \n", flags); + } + } + + status = LPI2C_MasterStop(LPI2C_PMIC); + /* if we got here it was successful up until stop */ + } while (SC_FALSE); + + if ((status != I32(kStatus_Success)) && (status != I32(kStatus_LPI2C_Nak))) + {/* reset if there was an error */ + pmic_print(1, "I2C Error %d \n", status); + (void)LPI2C_MasterStop(LPI2C_PMIC); + dev_id_read = 0U; + } + + #ifdef SC_MANAGE_LPI2C_CLK + if (LPI2C_PMIC == LPI2C_SC) + { + // Enter exclusive attempt to disable clock + uint32_t lpcgVal = CLOCK_DisableClockExEnter(kCLOCK_LPI2C_SC); + + // Check if conditions allow clock gating + if (!LPI2C_MasterGetBusIdleState(LPI2C_PMIC)) + { + // Mask to disable IPG and BAUD clocks + uint32_t lpcgMask = ~(BIT(LPCG__SS_SCU__IPG_CLK__SWEN) | + BIT(LPCG__SS_SCU__PER_CLK__SWEN)); + + lpcgVal &= lpcgMask; + } + + // Leave exclusive attempt to disable clock + CLOCK_DisableClockExLeave(kCLOCK_LPI2C_SC, lpcgVal); + } + #endif + + return dev_id_read; +} + +/*--------------------------------------------------------------------------*/ +/* Helper Function for j1850 crc write or read */ +/*--------------------------------------------------------------------------*/ +uint8_t pf8x00_crc_data(uint8_t addr, uint8_t reg, const uint8_t * const data, + uint32_t msg_size) +{ + uint8_t rtn = 0U; + const uint8_t *d = data; + + /* Check return pointer */ + if (d != NULL) + { + uint8_t i, j, crc = 0xFFU; + + /* CRC the address first */ + crc ^= addr; + for (i = 0U; i < 8U; i++) + { + crc = ((crc & 0x80U) != 0U) ? ((crc << 1U) ^ POLY ) + : U8(crc << 1U); + } + + /* CRC the register address next */ + crc ^= reg; + for (i = 0U; i < 8U; i++) + { + crc = ((crc & 0x80U) != 0U) ? ((crc << 1U) ^ POLY ) + : U8(crc << 1U); + } + + /* Finally do the data */ + j = 0U; + while (j < msg_size) + { + crc ^= *d; + d++; + /* Loop over all data */ + for (i = 0U; i < 8U; i++) + { + crc = ((crc & 0x80U) != 0U) ? ((crc << 1U) ^ POLY ) + : U8(crc << 1U); + } + j++; + } + + rtn = crc; + } + + return rtn; +} + diff --git a/platform/drivers/pmic/fsl_pmic.h b/platform/drivers/pmic/fsl_pmic.h new file mode 100755 index 0000000..c07019f --- /dev/null +++ b/platform/drivers/pmic/fsl_pmic.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_PMIC_H +#define DRV_PMIC_H + +/*! + * @addtogroup pmic_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "drivers/lpi2c/fsl_lpi2c.h" + +/* Defines */ +#define i2c_error_flags (U32(kLPI2C_MasterArbitrationLostFlag) | \ + U32(kLPI2C_MasterFifoErrFlag) | \ + U32(kLPI2C_MasterPinLowTimeoutFlag) | \ + U32(kLPI2C_MasterDataMatchFlag) | \ + U32(kLPI2C_MasterBusyFlag) | \ + U32(kLPI2C_MasterBusBusyFlag)) +/* Types */ + +/*! + * This type is used to declare which PMIC to address + */ +typedef uint8_t pmic_id_t; + +/*! + * Structure for ID and Revision of PMIC + */ +typedef struct +{ + uint8_t device_id; /*!< dev ID value (reg location may differ per device) */ + uint8_t si_rev; /*!< silicon revision value read from device */ +} pmic_version_t; + +/*! + * This function is a simple write to an i2c register on the PMIC + * + * @param[in] device_addr I2C address of device + * @param[in] reg address of register on device + * @param[in] data data to be written + * @param[in] dataLength length of data to be written + * + * @return Returns the status of the write (success = kStatus_Success) + * + * Return errors + * - kStatus_Fail if any of the transactions failed + * + * Note there is no clock management in this function + */ +status_t i2c_write_sub(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength); + +/*! + * This function writes an i2c register on the PMIC device + * with clock management + * + * @param[in] device_addr I2C address of device + * @param[in] reg address of register on device + * @param[in] data data to be written + * @param[in] dataLength length of data to be written + * + * @return Returns the status of the write (success = kStatus_Success) + * + * Return errors + * - kStatus_Fail if any of the transactions failed + */ + +status_t i2c_write(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength); + +/*! + * This function is a simple read of an i2c register on the PMIC + * + * @param[in] device_addr I2C address of device + * @param[in] reg address of register on device + * @param[out] data data to be read + * @param[in] dataLength length of data to be read + * + * @returns Returns the status of the read (success = kStatus_Success) + * + * Return errors + * - kStatus_Fail if any of the transactions failed + */ + +status_t i2c_read_sub(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength); + +/*! + * This function reads an i2c register on the PMIC device + * with clock management + * + * @param[in] device_addr I2C address of device + * @param[in] reg address of register on device + * @param[out] data data to be read + * @param[in] dataLength length of data to be read + * + * @returns Returns the status of the read (success = kStatus_Success) + * + * Return errors + * - kStatus_Fail if any of the transactions failed + */ + +status_t i2c_read(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength); + + +/*! + * This function writes an i2c register on the PMIC device + * with j1850 CRC appended and clock management + * + * @param[in] device_addr I2C address of device + * @param[in] reg address of register on device + * @param[in] data data to be written + * @param[in] dataLength length of data to be written + * + * @return Returns the status of the write (success = kStatus_Success) + * + * Return errors + * - kStatus_Fail if any of the transactions failed + */ +status_t i2c_j1850_write(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength); + +/*! + * This function reads an i2c register on the PMIC device with j1850 CRC + * and clock management + * + * @param[in] device_addr I2C address of device + * @param[in] reg address of register on device + * @param[out] data data to be read + * @param[in] dataLength length of data to be read + * + * @returns Returns the status of the read (success = kStatus_Success) + * + * Return errors + * - kStatus_Fail if any of the transactions failed + */ +status_t i2c_j1850_read(uint8_t device_addr, uint8_t reg, void *data, + uint32_t dataLength); + +/*! + * This function reads the register at address 0x0 for the Device ID + * + * @param[in] address I2C address of device + * + * @returns Returns the device ID + * + * Return Errors + * - 0 if any error in the function + */ +uint8_t pmic_get_device_id(uint8_t address); + +#endif + +/** @} */ + diff --git a/platform/drivers/pmic/pf100/Makefile b/platform/drivers/pmic/pf100/Makefile new file mode 100755 index 0000000..03e610a --- /dev/null +++ b/platform/drivers/pmic/pf100/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/pmic/pf100/fsl_pf100.o + +DIRS += $(OUT)/drivers/pmic/pf100 + diff --git a/platform/drivers/pmic/pf100/doxygen/fsl_pf100.dox b/platform/drivers/pmic/pf100/doxygen/fsl_pf100.dox new file mode 100755 index 0000000..e9ae7cd --- /dev/null +++ b/platform/drivers/pmic/pf100/doxygen/fsl_pf100.dox @@ -0,0 +1,8 @@ +/*! +@defgroup pf100_driver PF100: PF100 Power Management IC Driver +Module for the PF100 PMIC driver. + +@details This is an SDK driver for the NXP PF100 PMIC. For more information, +see the PF100 Datasheet. + +*/ diff --git a/platform/drivers/pmic/pf100/fsl_pf100.c b/platform/drivers/pmic/pf100/fsl_pf100.c new file mode 100755 index 0000000..dbc4445 --- /dev/null +++ b/platform/drivers/pmic/pf100/fsl_pf100.c @@ -0,0 +1,689 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "fsl_device_registers.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/pf100/fsl_pf100.h" +#include "fsl_common.h" + +/* Local Defines */ +#define VGEN_EN 0x10U /*!< Voltage Generator enable mask */ +#define SW_VOLT_MASK 0x3FU /*!< Switching regulator voltage mask */ +#define VGEN_VOLT_MASK 0xFU /*!< LDO regulator voltage mask */ +#define SW_BIT6_MASK 0x40U /*!< Voltage Range selection bit mask */ +#define SW_MODE_MASK 0xFU +#define VGEN_MODE_MASK (0x7U << 4U) + +/* Defines */ + +/*! + * @name Defines for pf100_ctl_regs_t + */ +/** @{ */ +#define DEVICEID 0x00U +#define SILICONREVID 0x03U +#define FABID 0x04U +#define INTSTAT0 0x05U +#define INTMASK0 0x06U +#define INTSENSE0 0x07U +#define INTSTAT1 0x08U +#define INTMASK1 0x09U +#define INTSENSE1 0x0AU +#define INTSTAT3 0x0EU +#define INTMASK3 0x0FU +#define INTSENSE3 0x10U +#define INTSTAT4 0x11U +#define INTMASK4 0x12U +#define INTSENSE4 0x13U +#define COINCTL 0x1AU +#define PWRCTL 0x1BU +#define MEMA 0x1CU +#define MEMB 0x1DU +#define MEMC 0x1EU +#define MEMD 0x1FU +/** @} */ + +/*! + * @name Defines for pmic_ints_t + */ +/** @{ */ +#define THERM110 BIT8(2U) +#define THERM120 BIT8(3U) +#define THERM125 BIT8(4U) +#define THERM130 BIT8(5U) +/** @} */ + + +/* Types */ +/*! + * This type is used to offset from a register + */ +typedef uint8_t pf100_ctl_regs_t; + +/*! + * This type is used to encode the temperature + */ +typedef uint8_t pmic_ints_t; + +/* Local Functions */ + +/* Local Variables */ + +struct sw_range +{ + uint32_t sw2; /* 0 = un-initialized */ + uint32_t sw3a; /* 1 = low voltage range */ + uint32_t sw3b; /* 2 = high voltage range */ + uint32_t sw4; +}; + +static struct sw_range switching_range = {0U, 0U, 0U, 0U}; + +/*--------------------------------------------------------------------------*/ +/* Get PMIC version */ +/*--------------------------------------------------------------------------*/ +pmic_version_t pf100_get_pmic_version(pmic_id_t id) +{ + pmic_version_t ver; + + if (kStatus_Success != i2c_read(id, DEVICEID, &ver.device_id, 1U)) + { + ver.device_id = 0U; + } + if (kStatus_Success != i2c_read(id, SILICONREVID, &ver.si_rev, 1U)) + { + ver.si_rev = 0U; + } + + ver.device_id &= 0x1FU; + ver.si_rev &= 0xFFU; + + return ver; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Regulator Voltage */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf100_pmic_set_voltage(pmic_id_t id, uint32_t pmic_reg, + uint32_t vol_mv, uint32_t mode_to_set) +{ + status_t err; + uint32_t mode_offset = 0U; + uint32_t new_volt = 0U; + uint8_t val = 0U; + uint32_t volt_mask = SW_VOLT_MASK; + uint8_t pmic_reg8; + + if (pmic_reg >= 0x100U) + { + return SC_ERR_PARM; + } + else + { + pmic_reg8 = U8(pmic_reg); + } + + switch (mode_to_set) + { + case SW_STBY_MODE: + mode_offset = 1U; + break; + case SW_OFF_MODE: + mode_offset = 2U; + break; + default:/* if not stby or off assume run mode */ + ; /* Intentional empty default */ + break; + } + + /* Calculate step voltage */ + switch (pmic_reg8) + { + case SW1AB: + case SW1C: + if (vol_mv < 300U) + { + vol_mv = 300U; + } + new_volt = (vol_mv - 300U) / 25U; + break; + case SW2:/* variable step size based on operating range determined by SW2[6] */ + if (switching_range.sw2 == 0U) + { + if (i2c_read(id, pmic_reg8, &val, 1U) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val &= SW_BIT6_MASK; /* mask off other bits */ + if (val != 0U) + { + switching_range.sw2 = 2U;/* set high voltage range */ + } + else + { + switching_range.sw2 = 1U;/* set low voltage range */ + } + } + if (vol_mv < 400U * switching_range.sw2) + { + vol_mv = 400U * switching_range.sw2; + } + new_volt = (vol_mv - 400U * switching_range.sw2) / 25U * switching_range.sw2; + break; + case SW3A: + if (switching_range.sw3a == 0U) + { + if (i2c_read(id, pmic_reg8, &val, 1U) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val &= SW_BIT6_MASK; /* mask off other bits */ + if (val != 0U) + { + switching_range.sw3a = 2U;/* set high voltage range */ + } + else + { + switching_range.sw3a = 1U;/* set low voltage range */ + } + } + if (vol_mv < (400U * switching_range.sw3a)) + { + vol_mv = 400U * switching_range.sw3a; + } + new_volt = (vol_mv - 400U * switching_range.sw3a) / 25U * switching_range.sw3a; + break; + case SW3B: + if (switching_range.sw3b == 0U) + { + if (i2c_read(id, pmic_reg8, &val, 1U) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val &= SW_BIT6_MASK; /* mask off other bits */ + if (val != 0U) + { + switching_range.sw3b = 2;/* set high voltage range */ + } + else + { + switching_range.sw3b = 1U;/* set low voltage range */ + } + } + if (vol_mv < (400U * switching_range.sw3b)) + { + vol_mv = 400U * switching_range.sw3b; + } + new_volt = (vol_mv - 400U * switching_range.sw3b) / 25U * switching_range.sw3b; + break; + case SW4: + if (switching_range.sw4 == 0U) + { + if (i2c_read(id, pmic_reg8, &val, 1U) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val &= SW_BIT6_MASK; /* mask off other bits */ + if (val != 0U) + { + switching_range.sw4 = 2U;/* set high voltage range */ + } + else + { + switching_range.sw4 = 1U;/* set low voltage range */ + } + } + if (vol_mv < (400U * switching_range.sw4)) + { + vol_mv = 400U * switching_range.sw4; + } + new_volt = (vol_mv - 400U * switching_range.sw4) / 25U * switching_range.sw4; + break; + case VGEN1: + case VGEN2: + if (vol_mv < 800U) + { + vol_mv = 800U; + } + new_volt = ((vol_mv - 800U) / 50U); + volt_mask = VGEN_VOLT_MASK; + break; + case VGEN3: + case VGEN4: + case VGEN5: + case VGEN6: + if (vol_mv < 1800U) + { + vol_mv = 1800U; + } + new_volt = ((vol_mv - 1800U) / 100U); + volt_mask = VGEN_VOLT_MASK; + break; + default: + ; /* Intentional empty default */ + break; + } + + /* Read PMIC register */ + err = i2c_read(id, pmic_reg8 + mode_offset, &val, 1U); + if (err != kStatus_Success) + { + error_print("pmic_set_volt - Fail I2C rd PMIC %d, reg %u\n", + id, pmic_reg8); + + return SC_ERR_FAIL; + } + + /* Update voltage */ + val &= ~volt_mask; + val |= new_volt; + + /* Update PMIC register */ + err = i2c_write(id, pmic_reg8 + mode_offset, &val, 1U); + if (err != kStatus_Success) + { + error_print("pmic_set_volt - Fail to wr PMIC %d, reg %u\n", + id, pmic_reg8); + + return SC_ERR_FAIL; + } + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC Regulator Voltage */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf100_pmic_get_voltage(pmic_id_t id, uint32_t pmic_reg, + uint32_t *vol_mv, uint32_t mode_to_get) +{ + status_t err; + uint8_t mode_offset = 0U; + uint8_t val = 0, val2 = 0U; + uint8_t pmic_reg8; + + if (pmic_reg >= 0x100U) + { + return SC_ERR_PARM; + } + else + { + pmic_reg8 = U8(pmic_reg); + } + + switch (mode_to_get) + { + case SW_STBY_MODE: + mode_offset = 1U; + break; + case SW_OFF_MODE: + mode_offset = 2U; + break; + default:/* if not stby or off assume run mode */ + ; /* Intentional empty default */ + break; + } + + /* Read PMIC register */ + err = i2c_read(id, pmic_reg8 + mode_offset, &val, 1U); + if (err != kStatus_Success) + { + error_print("pmic_get_volt - Fail I2C rd PMIC %d, reg %u\n", + id, pmic_reg8); + + return SC_ERR_FAIL; + } + + /* Calculate voltage */ + switch (pmic_reg8) + { + case SW1AB: + case SW1C: + val &= SW_VOLT_MASK; + *vol_mv = (U32(val) * 25UL) + 300UL; + break; + case SW2:/* variable step size based on operating range determined by SW2[6] */ + val &= SW_VOLT_MASK; + if (switching_range.sw2 == 0U) + { + if (i2c_read(id, pmic_reg8, &val2, 1) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val2 &= SW_BIT6_MASK; /* mask off other bits */ + if (val2 != 0U) + { + switching_range.sw2 = 2U;/* set high voltage range */ + } + else + { + switching_range.sw2 = 1U;/* set low voltage range */ + } + } + *vol_mv = (val * 25U * switching_range.sw2) + 400U * switching_range.sw2; + break; + case SW3A: + val &= SW_VOLT_MASK; + if (switching_range.sw3a == 0U) + { + if (i2c_read(id, pmic_reg8, &val2, 1) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val2 &= SW_BIT6_MASK; /* mask off other bits */ + if (val2 != 0U) + { + switching_range.sw3a = 2u;/* set high voltage range */ + } + else + { + switching_range.sw3a = 1U;/* set low voltage range */ + } + } + *vol_mv = (val * 25U * switching_range.sw3a) + 400U * switching_range.sw3a; + break; + case SW3B: + val &= SW_VOLT_MASK; + if (switching_range.sw3b == 0U) + { + if (i2c_read(id, pmic_reg8, &val2, 1) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val2 &= SW_BIT6_MASK; /* mask off other bits */ + if (val2 != 0U) + { + switching_range.sw3b = 2U;/* set high voltage range */ + } + else + { + switching_range.sw3b = 1U;/* set low voltage range */ + } + } + *vol_mv = (val * 25U*switching_range.sw3b) + 400U*switching_range.sw3b; + break; + case SW4: + val &= SW_VOLT_MASK; + if (switching_range.sw4 == 0U) + { + if (i2c_read(id, pmic_reg8, &val2, 1) != kStatus_Success) + { + return SC_ERR_FAIL; /* return if voltage range read failed */ + } + val2 &= SW_BIT6_MASK; /* mask off other bits */ + if (val2 != 0U) + { + switching_range.sw4 = 2U;/* set high voltage range */ + } + else + { + switching_range.sw4 = 1U;/* set low voltage range */ + } + } + *vol_mv = (U32(val) * 25UL * switching_range.sw4) + 400UL * switching_range.sw4; + break; + case VGEN1: + case VGEN2: + val &= VGEN_VOLT_MASK; + *vol_mv = (U32(val) * 50UL) + 800UL; + break; + case VGEN3: + case VGEN4: + case VGEN5: + case VGEN6: + val &= VGEN_VOLT_MASK; + *vol_mv = (U32(val) * 100UL) + 1800UL; + break; + default: + ; /* Intentional empty default */ + break; + } + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Regulator Mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf100_pmic_set_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t mode) +{ + status_t err; + uint32_t val = 0U; + uint32_t mask = VGEN_MODE_MASK; + uint8_t pmic_reg8; + + if (pmic_reg >= 0x100U) + { + return SC_ERR_PARM; + } + else + { + pmic_reg8 = U8(pmic_reg); + } + + switch (pmic_reg8) + { + case SW1AB: + mask = SW_MODE_MASK; + pmic_reg8 = 0x23U; + break; + case SW1C: + mask = SW_MODE_MASK; + pmic_reg8 = 0x31U; + break; + case SW2: + mask = SW_MODE_MASK; + pmic_reg8 = 0x38U; + break; + case SW3A: + mask = SW_MODE_MASK; + pmic_reg8 = 0x3FU; + break; + case SW3B: + mask = SW_MODE_MASK; + pmic_reg8 = 0x46U; + break; + case SW4: + mask = SW_MODE_MASK; + pmic_reg8 = 0x4DU; + break; + default: + ; /* Intentional empty default */ + break; + } + + /* Read PMIC register */ + err = i2c_read(id, pmic_reg8, &val, 1U); + if (err != kStatus_Success) + { + error_print("pmic_set_mode - Fail read PMIC %d, reg %u\n", + id, pmic_reg8); + + return SC_ERR_FAIL; + } + + /* Update mode */ + val &= ~mask; + val |= mode; + + /* Update PMIC register */ + (void) i2c_write(id, pmic_reg8, &val, 1U); + if (err != kStatus_Success) + { + error_print("pmic_set_mode - Fail set mode %u PMIC %d, reg %u\n", + mode, id, pmic_reg8); + + return SC_ERR_FAIL; + } + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC temp */ +/*--------------------------------------------------------------------------*/ +uint32_t pf100_get_pmic_temp(pmic_id_t id) +{ + uint8_t sense = 0U; + + (void) i2c_read(id, INTSENSE0, &sense, 1U); + + if ((sense & THERM130) != 0U) + { + return 130U; + } + else if ((sense & THERM125) != 0U) + { + return 125U; + } + else if ((sense & THERM120) != 0U) + { + return 120U; + } + else if ((sense & THERM110) != 0U) + { + return 110U; + } + else + { + ; /* Intentional empty else */ + } + + return 100U; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC temp alarm */ +/*--------------------------------------------------------------------------*/ +uint32_t pf100_set_pmic_temp_alarm(pmic_id_t id, uint32_t temp) +{ + uint8_t mask; + + /* Round value and determine mask */ + if (temp <= 110U) + { + temp = 110U; + mask = THERM110; + } + else if (temp <= 120U) + { + temp = 120U; + mask = THERM120; + } + else if (temp <= 125U) + { + temp = 125U; + mask = THERM125; + } + else if (temp <= 130U) + { + temp = 130U; + mask = THERM130; + } + else + { + temp = 135U; + mask = 0U; + } + + /* Write new mask */ + mask = (~mask) & 0x3FU; + (void) i2c_write(id, INTMASK0, &mask, 1U); + + return temp; +} + +/*--------------------------------------------------------------------------*/ +/* Access registers of the PF100 */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf100_pmic_register_access(pmic_id_t id, uint32_t address, + sc_bool_t read_write, uint8_t* value) +{ + status_t err; + + if (read_write == SC_FALSE) + { + err = i2c_read(id, address, value, 1U); + if (err != kStatus_Success) + { + error_print("PMIC reg acc - Fail to rd PMIC %x, reg %x\n", + id, address); + + return SC_ERR_FAIL; + } + } + else + { + err = i2c_write(id, address, value, 1U); + if (err != kStatus_Success) + { + error_print("PMIC reg acc - Fail to wr PMIC %x, reg %x\n", + id, address); + + return SC_ERR_FAIL; + } + } + + return SC_ERR_NONE; + +}; + +/*--------------------------------------------------------------------------*/ +/* Service PMIC interrupt */ +/*--------------------------------------------------------------------------*/ +sc_bool_t pf100_pmic_irq_service(pmic_id_t id) +{ + uint8_t mask = 0U; + uint8_t status = 0U; + + /* PMIC pending? */ + (void) i2c_read(id, INTSTAT0, &status, 1U); + (void) i2c_read(id, INTMASK0, &mask, 1U); + status &= ~mask; + if (status != kStatus_Success) + { + /* Mask off to prevent repeat */ + mask = 0x3F; + (void) i2c_write(id, INTMASK0, &mask, 1U); + + /* Clear */ + (void) i2c_write(id, INTSTAT0, &status, 1U); + + return SC_TRUE; + } + + return SC_FALSE; +} + diff --git a/platform/drivers/pmic/pf100/fsl_pf100.h b/platform/drivers/pmic/pf100/fsl_pf100.h new file mode 100755 index 0000000..0aa2120 --- /dev/null +++ b/platform/drivers/pmic/pf100/fsl_pf100.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_PMIC_PF100_H +#define DRV_PMIC_PF100_H + +/*! + * @addtogroup pf100_driver + * @{ + */ + +/*! @file */ + +/*! + * @name Defines for pf100_vol_regs_t + */ +/** @{ */ +#define SW1AB 0x20U /*!< Base register for SW1AB control */ +#define SW1C 0x2EU /*!< Base register for SW1C control */ +#define SW2 0x35U /*!< Base register for SW2 control */ +#define SW3A 0x3cU /*!< Base register for SW3A control */ +#define SW3B 0x43U /*!< Base register for SW3B control */ +#define SW4 0x4AU /*!< Base register for SW4 control */ +#define VGEN1 0x6CU /*!< Base register for VGEN1 control */ +#define VGEN2 0x6DU /*!< Base register for VGEN2 control */ +#define VGEN3 0x6EU /*!< Base register for VGEN3 control */ +#define VGEN4 0x6FU /*!< Base register for VGEN4 control */ +#define VGEN5 0x70U /*!< Base register for VGEN5 control */ +#define VGEN6 0x71U /*!< Base register for VGEN6 control */ +/** @} */ + +/*! + * @name Defines for sw_pmic_mode_t + */ +/** @{ */ +#define SW_MODE_OFF_STBY_OFF 0x0U /*!< Normal Mode: OFF, Standby Mode: OFF */ +#define SW_MODE_PWM_STBY_OFF 0x1U /*!< Normal Mode: PWM, Standby Mode: OFF */ +#define SW_MODE_PFM_STBY_OFF 0x3U /*!< Normal Mode: PFM, Standby Mode: OFF */ +#define SW_MODE_APS_STBY_OFF 0x4U /*!< Normal Mode: APS, Standby Mode: OFF */ +#define SW_MODE_PWM_STBY_PWM 0x5U /*!< Normal Mode: PWM, Standby Mode: PWM */ +#define SW_MODE_PWM_STBY_APS 0x6U /*!< Normal Mode: PWM, Standby Mode: APS */ +#define SW_MODE_APS_STBY_APS 0x8U /*!< Normal Mode: APS, Standby Mode: APS */ +#define SW_MODE_APS_STBY_PFM 0xCU /*!< Normal Mode: APS, Standby Mode: PFM */ +#define SW_MODE_PWM_STBY_PFM 0xDU /*!< Normal Mode: PWM, Standby Mode: PFM */ +/** @} */ + + +/*! + * @name Defines for vgen_pmic_mode_t + */ +/** @{ */ +#define VGEN_MODE_OFF (0x0U << 4U) /*!< VGEN always OFF */ +#define VGEN_MODE_ON (0x1U << 4U) /*!< VGEN always ON */ +#define VGEN_MODE_STBY_OFF (0x3U << 4U) /*!< VGEN Run: ON STBY: OFF */ +#define VGEN_MODE_LP (0x5U << 4U) /*!< VGEN Run: LPWR STBY: LPWR */ +#define VGEN_MODE_LP2 (0x7U << 4U) /*!< VGEN Run: LPWR STBY: LPWR */ +/** @} */ + + +/*! + * @name Defines for sw_vmode_reg_t + */ +/** @{ */ +#define SW_RUN_MODE 0U /*!< SW run mode voltage */ +#define SW_STBY_MODE 1U /*!< SW standby mode voltage */ +#define SW_OFF_MODE 2U /*!< SW off/sleep mode voltage */ +/** @} */ + +/*! + * This type is used to indicate which register to address. + * + * Refer to the PF100 Datasheet for the description of regsiter. + */ +typedef uint8_t pf100_vol_regs_t; +/*! + * This type is used to indicate a switching regulator mode. + * + * Refer to the PF100 Datasheet for the description of each mode. + */ +typedef uint8_t sw_pmic_mode_t; +/*! + * This type is used to indicate a VGEN (LDO) regulator mode. + * + * Refer to the LDO control register description in the PF100 Datasheet + * for possible mode combinations. + */ +typedef uint8_t vgen_pmic_mode_t; +/*! + * This type encodes which voltage mode register to set when calling + * [pf100_pmic_set_voltage()](@ref pf100_pmic_set_voltage). + * + * Possible modes are Run, Standby and Off/Sleep. + */ +typedef uint8_t sw_vmode_reg_t; + +/*! + * This function returns the device ID and revision for the PF100 PMIC. + * + * @param[in] id I2C address of PMIC device + * + * @return Returns a structure with the device ID and revision. + */ +pmic_version_t pf100_get_pmic_version( pmic_id_t id); + +/*! + * This function sets the voltage of a corresponding voltage regulator for the + * PF100 PMIC. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + * see [pf100_vol_regs_t](@ref pf100_vol_regs_t) + * @param[in] vol_mv New voltage setpoint for the regulator in millivolts + * @param[in] mode_to_set Mode to set the voltage for run, standby and off; + * only applicable to switching regulators, ignored + * otherwise; see [sw_vmode_reg_t](@ref sw_vmode_reg_t) + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t pf100_pmic_set_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t vol_mv, + uint32_t mode_to_set); + +/*! + * This function gets the voltage on a corresponding voltage regulator for the + * PF100 PMIC. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + * see [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[out] vol_mv pointer to return voltage in millivolts + * @param[in] mode_to_get Mode to get the voltage for run, standby and off; + * only applicable to switching regulators, ignored + * otherwise; see [sw_vmode_reg_t](@ref sw_vmode_reg_t) + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + */ +sc_err_t pf100_pmic_get_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t *vol_mv, + uint32_t mode_to_get); + +/*! + * This function sets the mode of the specified regulator. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + see [pf100_vol_regs_t](@ref pf100_vol_regs_t) + * @param[in] mode mode to set the regulator; + * see [vgen_pmic_mode_t](@ref vgen_pmic_mode_t) + * and [sw_pmic_mode_t](@ref sw_pmic_mode_t) + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t pf100_pmic_set_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t mode); + +/*! + * This function gets the current PMIC temperature as sensed by the + * PMIC temperature sensor. + * + * @param[in] id I2C address of PMIC device + * + * @return returns the temp sensed by the PMIC in a UINT32 in Celsius + * + * Return errors: + * - SC_ERR_CONFIG if temperature monitor is not enabled + * + * Note PMIC PF100 temp is returned as the highest temp sensor enabled. + */ +uint32_t pf100_get_pmic_temp(pmic_id_t id); + +/*! + * This function sets the temp alarm for the PMIC in Celsius + * + * @param[in] id I2C address of PMIC device + * @param[in] temp Temperature to set the alarm + * + * Note the granularity for PF100 PMIC only allows the following + * values: + * 110 + * 120 + * 125 + * 130 + * 135 + * + * @return Returns the temperature that the alarm is set to in Celsius + */ +uint32_t pf100_set_pmic_temp_alarm(pmic_id_t id, uint32_t temp); + +/* + * This function allows access to individual registers of the PF100 + * + * @param[in] id I2C address of PMIC device + * @param[in] address register address to access + * @param[in] read_write bool indicating read(SC_FALSE/0) or write(SC_TRUE/1) + * @param[in,out] value value to read or to set + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * + */ +sc_err_t pf100_pmic_register_access(pmic_id_t id, uint32_t address, + sc_bool_t read_write, uint8_t* value); + +/*! + * This function services the interrupt for the temp alarm + * + * @param[in] id I2C address of PMIC device + * + * @return Returns SC_TRUE if there was a temperature interrupt to be cleared + */ +sc_bool_t pf100_pmic_irq_service(pmic_id_t id); + +#endif + +/** @} */ + diff --git a/platform/drivers/pmic/pf8100/Makefile b/platform/drivers/pmic/pf8100/Makefile new file mode 100755 index 0000000..84d1109 --- /dev/null +++ b/platform/drivers/pmic/pf8100/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/pmic/pf8100/fsl_pf8100.o + +DIRS += $(OUT)/drivers/pmic/pf8100 + diff --git a/platform/drivers/pmic/pf8100/doxygen/fsl_pf8100.dox b/platform/drivers/pmic/pf8100/doxygen/fsl_pf8100.dox new file mode 100755 index 0000000..dbf6359 --- /dev/null +++ b/platform/drivers/pmic/pf8100/doxygen/fsl_pf8100.dox @@ -0,0 +1,10 @@ +/*! +@defgroup pf8100_driver PF8100: PF8100 Power Management IC Driver +Module for the PF8100 PMIC driver. + +@details This is an SDK driver for the NXP PF8100 PMIC. For more information, +see the PF8100 Datasheet. + +If CRC operations are needed PMIC_CRC must be defined globally (usually in board.h) + +*/ diff --git a/platform/drivers/pmic/pf8100/fsl_pf8100.c b/platform/drivers/pmic/pf8100/fsl_pf8100.c new file mode 100755 index 0000000..f966c4d --- /dev/null +++ b/platform/drivers/pmic/pf8100/fsl_pf8100.c @@ -0,0 +1,1037 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* This driver meets SRS requirements PMIC_00010, PMIC_00020, PMIC_00030, + and PMIC_00040 */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "fsl_device_registers.h" +#include "drivers/pmic/fsl_pmic.h" +#include "drivers/lpi2c/fsl_lpi2c.h" +#include "drivers/pmic/pf8100/fsl_pf8100.h" +#include "fsl_common.h" + +/* Local Defines */ + +/*! + * @name Defines for PF8100 masks + */ +#define SW_VOLT_MASK 0x3FU +#define LDO_VOLT_MASK 0xFU +#define MODE_MASK 0xFU +#define TMP_MON_EN_MSK 0x10U +#define THERM_I_MSK 0x3FU + +#define NOT_DETECTED 0xE0U +#define A0_SI_REV 0x10U +#define B0_SI_REV 0x20U +#define C0_SI_REV 0x30U + +/* Local Functions */ + +static inline sc_err_t check_si_rev(uint8_t address); + +/* Local Variables */ + +/* variable to keep track of silicon revision + * 0xE0 is not detected + * 0x00 is A0 + * 0x01 is B0 */ +static uint8_t si_rev = NOT_DETECTED; + +/*! + * Defines for pf8100_ctl_regs_t + */ +/** @{ */ +#define PF8100_DEVICEID 0x00U +#define PF8100_SILICONREVID 0x01U +#define PF8100_THERMINT 0x07U +#define PF8100_THERMMASK 0x08U +#define PF8100_THERMSENSE 0x09U +#define PF8100_VMONEN1 0x35U +#define PF8100_VMONEN2 0x36U +#define PF8100_CTRL1 0x37U +#define PF8100_CTRL2 0x38U +#define PF8100_CTRL3 0x39U +#define PF8100_PWRUPCTRL 0x3AU +#define PF8100_VSNVS 0x9DU +#define PF8100_PG_SEL 0x9FU +#define PF8100_RANDOM_GEN 0x33U +#define PF8100_RANDOM_CHK 0x34U +#define PF8100_WD_CONFIG 0x43U +#define PF8100_WD_CLEAR 0x44U + +/* Below are all secure register definitions */ +#define PF8100_FSOB_FLAGS 0x2AU +#define PF8100_ABIST_OV1 0x2CU +#define PF8100_ABIST_OV2 0x2DU +#define PF8100_ABIST_UV1 0x2EU +#define PF8100_ABIST_UV2 0x2FU +#define PF8100_ABIST_RUN 0x31U +#define PF8100_VMONEN1 0x35U +#define PF8100_VMONEN2 0x36U +#define PF8100_CTRL1 0x37U + +/** @} */ + + +/*! + * Defines for sw_regs_t + */ +/** @{ */ +#define sw_config1 0x00U +#define sw_config2 0x01U +#define sw_pwrup 0x02U +#define sw_mode1 0x03U +#define sw_run_volt 0x04U +#define sw_stby_volt 0x05U +/** @} */ + +/*! + * Defines for ldo_regs_t + */ +/** @{ */ +#define ldo_config1 0x00U +#define ldo_config2 0x01U +#define ldo_pwrup 0x02U +#define ldo_run_volt 0x03U +#define ldo_stby_volt 0x04U +/** @} */ + +/*! + * Defines for temp_msk_t + */ +/** @{ */ +#define THERM80 BIT(0U) +#define THERM95 BIT(1U) +#define THERM110 BIT(2U) +#define THERM125 BIT(3U) +#define THERM140 BIT(4U) +#define THERM155 BIT(5U) +/** @} */ + +/*! + * This type is used to declare control register offsets in + * a readable manner for the PF8100/PF8200 + */ +typedef uint8_t pf8100_ctl_regs_t; + +/*! + * This type is used to model the register structure of switching + * regulators in the PF8100 + */ +typedef uint8_t sw_regs_t; + +/*! + * This type is used to model the register structure of LDOs + * in the PF8100 + */ +typedef uint8_t ldo_regs_t; + +/*! + * This type is used to define the different temperature masks + */ +typedef uint8_t temp_msk_t; + +#ifdef PMIC_SECURE_WRITE +/* listing of secure registers */ +static const uint32_t secure_reg_list[] = +{ + PF8100_FSOB_FLAGS, + PF8100_ABIST_OV1, + PF8100_ABIST_OV2, + PF8100_ABIST_UV1, + PF8100_ABIST_UV2, + PF8100_ABIST_RUN, + PF8100_VMONEN1, + PF8100_VMONEN2, + PF8100_CTRL1 +}; +#endif + +static const uint32_t sw7v_lookup[32] = +{ + 1000U, /* value in mV for VSW7 arranged by index */ + 1100U, + 1200U, + 1250U, + 1300U, + 1350U, + 1500U, + 1600U, + 1800U, + 1850U, + 2000U, + 2100U, + 2150U, + 2250U, + 2300U, + 2400U, + 2500U, + 2800U, + 3150U, + 3200U, + 3250U, + 3300U, + 3350U, + 3400U, + 3500U, + 3800U, + 4000U, + 4100U, + 4100U, + 4100U, + 4100U, + 4100U +}; + +static const uint32_t ldo_table_a0[16] = +{ + 1500U, /* lookup for LDO values A0*/ + 1800U, + 1850U, + 2500U, + 2750U, + 2800U, + 2850U, + 3000U, + 3100U, + 3150U, + 3200U, + 3300U, + 3350U, + 4000U, + 4900U, + 5000U +}; + +static const uint32_t ldo_table_b0[16] = +{ + 1500U, /* lookup for LDO values B0*/ + 1600U, + 1800U, + 1850U, + 2150U, + 2500U, + 2800U, + 3000U, + 3100U, + 3150U, + 3200U, + 3300U, + 3350U, + 4000U, + 4900U, + 5000U +}; + +static const uint32_t ldo_table[16] = +{ + 1500U, /* lookup for LDO values in C0 going forward*/ + 1600U, + 1800U, + 1850U, + 2150U, + 2500U, + 2800U, + 3000U, + 3100U, + 3150U, + 3200U, + 3300U, + 3350U, + 1650U, + 1700U, + 5000U +}; + +/*--------------------------------------------------------------------------*/ +/* Get PMIC version */ +/*--------------------------------------------------------------------------*/ +pmic_version_t pf8100_get_pmic_version(pmic_id_t id) +{ + pmic_version_t ver; + + /* Read device ID */ + if (((status_t) kStatus_Success) != I2C_READ(id, PF8100_DEVICEID, + &ver.device_id, 1U)) + { + ver.device_id = 0U; + } + + /* Read PMIC version */ + if (((status_t) kStatus_Success) != I2C_READ(id, PF8100_SILICONREVID, + &ver.si_rev, 1U)) + { + ver.si_rev = 0U; + } + + /* Mask results */ + ver.device_id &= 0xFFU; + ver.si_rev &= 0xFFU; + + /* Return results */ + if(ver.si_rev != 0U) + { + si_rev = ver.si_rev; + } + + return ver; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Regulator Voltage */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_set_voltage(pmic_id_t id, uint32_t pmic_reg, + uint32_t vol_mv, uint32_t mode_to_set) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t val = 0U; + uint8_t pmic_reg8 = U8(pmic_reg); + + /* Check parameters */ + ASRT_ERR(pmic_reg < 0x100U, SC_ERR_PARM); + + /* Check PMIC version */ + ASRT_ERR(check_si_rev(id) == SC_ERR_NONE, SC_ERR_FAIL); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + const uint32_t *ldo_lookup = ldo_table; + + /* Select table based on PMIC rev */ + if(si_rev == A0_SI_REV) + { + ldo_lookup = ldo_table_a0; + } + else if ((si_rev == B0_SI_REV) || (si_rev == C0_SI_REV)) + { + ldo_lookup = ldo_table_b0; + } + else + { + ; /* Intentional empty else */ + } + + /* Select supply */ + switch (pmic_reg8) + { + /* Switcher */ + case PF8100_SW1: + case PF8100_SW2: + case PF8100_SW3: + case PF8100_SW4: + case PF8100_SW5: + case PF8100_SW6: + if (vol_mv == 1800U) + { + val = 0xB1U; + } + else if((vol_mv > 1500U) || (vol_mv < 400U)) + { + err = SC_ERR_PARM; + } + /* Shift 3 for floating math */ + else + { + val = (uint8_t)(((vol_mv * 1000U) - 400000U) / 6250U); + } + + if (err == SC_ERR_NONE) + { + pmic_reg8 = U2B(mode_to_set) ? (pmic_reg8 + sw_run_volt) + : (pmic_reg8 + sw_stby_volt); + } + break; + case PF8100_SW7: + if ((vol_mv < 1000U) || (vol_mv > 4100U)) + { + err = SC_ERR_PARM; + } + else + { + /* Use lookup table to get near requested V */ + val = 0U; + while ((val < 32U) && (sw7v_lookup[val] < vol_mv)) + { + val++; + } + pmic_reg8 = pmic_reg8 + sw_run_volt; + } + break; + /* LDO */ + case PF8100_LDO1: + case PF8100_LDO2: + case PF8100_LDO3: + case PF8100_LDO4: + if ((vol_mv < 1500U) || (vol_mv > 5000U)) + { + err = SC_ERR_PARM; + } + else + { + /* Use lookup table to step through possible voltages */ + val = 0U; + for (val = 0U; val < 16U; val ++) + { + if (ldo_lookup[val] == vol_mv) + { + break; + } + } + if (val == 16U) + { + /* Return unavaliable if not found in LDO values */ + err = SC_ERR_UNAVAILABLE; + } + else + { + pmic_reg8 = U2B(mode_to_set) + ? (pmic_reg8 + ldo_run_volt) + : (pmic_reg8 + ldo_stby_volt); + } + } + break; + default: + err = SC_ERR_PARM; + break; + } + } + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + status_t status; + + /* Write PMIC register */ + status = I2C_WRITE(id, pmic_reg8, &val, 1); + if (status != (status_t) kStatus_Success) + { + error_print("pmic_set_voltage - Failed to wr" + " PMIC %d, reg %u\n", id, pmic_reg8); + + /* Return error */ + err = SC_ERR_FAIL; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC Regulator Voltage */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_get_voltage(pmic_id_t id, uint32_t pmic_reg, + uint32_t* vol_mv, uint32_t mode_to_get) +{ + sc_err_t err = SC_ERR_NONE; + const uint32_t *ldo_lookup = ldo_table; + uint8_t pmic_reg8 = U8(pmic_reg); + + /* Check parameters */ + ASRT_ERR(pmic_reg < 0x100U, SC_ERR_PARM); + + /* Check PMIC version */ + ASRT_ERR(check_si_rev(id) == SC_ERR_NONE, SC_ERR_FAIL); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + /* Select table based on PMIC rev */ + if (si_rev == A0_SI_REV) + { + ldo_lookup = ldo_table_a0; + } + else if ((si_rev == B0_SI_REV) || (si_rev == C0_SI_REV)) + { + ldo_lookup = ldo_table_b0; + } + else + { + ; /* Intentional empty else */ + } + + /* Select supply */ + switch (pmic_reg8) + { + /* Switcher */ + case PF8100_SW1: + case PF8100_SW2: + case PF8100_SW3: + case PF8100_SW4: + case PF8100_SW5: + case PF8100_SW6: + /* Add offset for corresponding LDO voltage */ + pmic_reg8 = U2B(mode_to_get) ? (pmic_reg8 + sw_run_volt) : + (pmic_reg8 + sw_stby_volt); + break; + case PF8100_SW7: + /* Add offset for corresponding LDO voltage */ + pmic_reg8 = pmic_reg8 + sw_run_volt; + break; + /* LDO */ + case PF8100_LDO1: + case PF8100_LDO2: + case PF8100_LDO3: + case PF8100_LDO4: + /* Add offset for corresponding LDO voltage */ + pmic_reg8 = U2B(mode_to_get) ? (pmic_reg8 + ldo_run_volt) : + (pmic_reg8 + ldo_stby_volt); + break; + default: + err = SC_ERR_PARM; + break; + } + } + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + uint8_t val = 0U; + status_t status; + + /* Read voltage value from PMIC */ + status = I2C_READ(id, pmic_reg8, &val, 1U); + if (status != (status_t) kStatus_Success) + { + error_print("pmic_get_voltage - Failed to rd for" + " PMIC %d, reg %u\n", id, pmic_reg8); + + err = SC_ERR_FAIL; + } + else + { + /* Convert binary value to mV value */ + switch (pmic_reg) + { + case PF8100_SW1: + case PF8100_SW2: + case PF8100_SW3: + case PF8100_SW4: + case PF8100_SW5: + case PF8100_SW6: + /* 0xB1 (177) == 1.8V*/ + if (val == 0xB1U) + { + *vol_mv = 1800U; + } + /* We are in the .4V to 1.5V range */ + *vol_mv = ((U32(val) * 6250U) + 400000U) / 1000U; + break; + case PF8100_SW7: + /* Obtain voltage from sw7 lookup table */ + *vol_mv = sw7v_lookup[val]; + break; + case PF8100_LDO1: + case PF8100_LDO2: + case PF8100_LDO3: + case PF8100_LDO4: + /* Obtain voltage from LDO lookup table */ + *vol_mv = ldo_lookup[val]; + break; + default: + ; /* Intentional empty default */ + break; + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC Regulator Mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_set_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t mode) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t pmic_reg8 = U8(pmic_reg); + + /* Check parameters */ + ASRT_ERR(pmic_reg < 0x100U, SC_ERR_PARM); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + /* Check to make sure a switching supply passed */ + switch (pmic_reg8) + { + /* Switchers */ + case PF8100_SW1: + case PF8100_SW2: + case PF8100_SW3: + case PF8100_SW4: + case PF8100_SW5: + case PF8100_SW6: + case PF8100_SW7: + pmic_reg8 = pmic_reg8 + sw_mode1; + break; + /* LDOs */ + case PF8100_LDO1: + case PF8100_LDO2: + case PF8100_LDO3: + case PF8100_LDO4: + pmic_reg8 = pmic_reg8 + ldo_config2; + break; + default: + err = SC_ERR_PARM; + break; + } + } + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + uint32_t val = 0U; + status_t status; + + /* Read from PMIC */ + status = I2C_READ(id, pmic_reg8, &val, 1U); + + /* Check for success? */ + if (status != (status_t) kStatus_Success) + { + error_print("pmic_set_mode - Failed to rd PMIC %d" + ", reg %u\n", id, pmic_reg8); + + /* Return error */ + err = SC_ERR_FAIL; + } + else + { + /* Calculate value */ + val &= ~MODE_MASK; + val |= mode & MODE_MASK; + + /* Write to PMIC */ + status = I2C_WRITE(id, pmic_reg8, &val, 1U); + + /* Check for success? */ + if (status != (status_t) kStatus_Success) + { + error_print("pmic_set_mode - Failed set mode %u" + " PMIC %d, reg %u\n", mode, id, pmic_reg8); + + /* Return error */ + err = SC_ERR_FAIL; + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC Regulator Mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_get_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t *mode) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t pmic_reg8= U8(pmic_reg); + + /* Check parameters */ + ASRT_ERR(pmic_reg < 0x100U, SC_ERR_PARM); + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + /* Check to make sure a switching supply passed */ + switch (pmic_reg8) + { + /* Switchers */ + case PF8100_SW1: + case PF8100_SW2: + case PF8100_SW3: + case PF8100_SW4: + case PF8100_SW5: + case PF8100_SW6: + case PF8100_SW7: + pmic_reg8 = pmic_reg8 + sw_mode1; + break; + /* LDOs */ + case PF8100_LDO1: + case PF8100_LDO2: + case PF8100_LDO3: + case PF8100_LDO4: + pmic_reg8 = pmic_reg8 + ldo_config2; + break; + default: + err = SC_ERR_PARM; + break; + } + } + + /* Check for error? */ + if (err == SC_ERR_NONE) + { + uint32_t val = 0U; + status_t status; + + /* Read from PMIC */ + status = I2C_READ(id, pmic_reg8, &val, 1U); + + /* Check for success? */ + if (status != (status_t) kStatus_Success) + { + error_print("pmic_get_mode - Failed to rd PMIC %d" + ", reg %u\n", id, pmic_reg8); + + /* Return error */ + err = SC_ERR_FAIL; + } + else + { + /* Return result */ + val &= MODE_MASK; + *mode = val; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get PMIC temp */ +/*--------------------------------------------------------------------------*/ +uint32_t pf8100_get_pmic_temp(pmic_id_t id) +{ + uint32_t rtn = 70U; /* return 10 degrees below lowest alarm */ + uint8_t sense = 0U, reg = 0U; + + /* Enabled monitor if off */ + (void) I2C_READ(id, PF8100_CTRL1, ®, 1U); + if((reg & TMP_MON_EN_MSK) == 0U) + { + reg |= TMP_MON_EN_MSK; + (void) I2C_WRITE(id, PF8100_CTRL1, ®, 1U); + } + + /* Read temp sense */ + (void) I2C_READ(id, PF8100_THERMSENSE, &sense, 1U); + + /* Check temp 155C */ + if ((sense & THERM155) != 0U) + { + rtn = 155U; + } + /* Check temp 140C */ + else if ((sense & THERM140) != 0U) + { + rtn = 140U; + } + /* Check temp 125C */ + else if ((sense & THERM125) != 0U) + { + rtn = 125U; + } + /* Check temp 110C */ + else if ((sense & THERM110) != 0U) + { + rtn = 110U; + } + /* Check temp 95C */ + else if ((sense & THERM95) != 0U) + { + rtn = 95U; + } + /* Check temp 80C */ + else if ((sense & THERM80) != 0U) + { + rtn = 80U; + } + else + { + ; /* Intentional empty else */ + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Set PMIC temp alarm */ +/*--------------------------------------------------------------------------*/ +uint32_t pf8100_set_pmic_temp_alarm(pmic_id_t id, uint32_t temp) +{ + uint8_t mask, reg = 0U; + + mask = THERM_I_MSK; /* start with all temp alarms enabled */ + if (temp > 80U) /* if less than 80 enable all alarms above 80 */ + { + /* subtract and round temp */ + mask = (mask << ((temp - 80U) / 15U)) & THERM_I_MSK; + } + mask = (~mask) & THERM_I_MSK; + + /* Write new mask */ + (void) I2C_READ(id, PF8100_THERMMASK, ®, 1U); + reg &= U8(~THERM_I_MSK); + reg |= mask; + (void) I2C_WRITE(id, PF8100_THERMMASK, ®, 1U); + + /* Enabled monitor if off */ + (void) I2C_READ(id, PF8100_CTRL1, ®, 1U); + if((reg & TMP_MON_EN_MSK) == 0U) + { + reg |= TMP_MON_EN_MSK; + (void) I2C_WRITE(id, PF8100_CTRL1, ®, 1U); + } + + return temp; +} + +#ifdef PMIC_SECURE_WRITE +/*--------------------------------------------------------------------------*/ +/* check if register need secure write */ +/*--------------------------------------------------------------------------*/ +bool pf8200_reg_need_secure_write(uint8_t reg_address) +{ + uint8_t i; + sc_bool_t secure = SC_FALSE; + for (i = 0; i < ARRAY_SIZE(secure_reg_list); i++) { + if (secure_reg_list[i] == reg_address) + secure = SC_TRUE; + } + return secure; +} +#endif + +/*--------------------------------------------------------------------------*/ +/* Access registers of the PF8100 */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_register_access(pmic_id_t id, uint32_t address, + sc_bool_t read_write, uint8_t* value) +{ + sc_err_t err = SC_ERR_NONE; + status_t status; + + if (read_write == SC_FALSE) + { + status = I2C_READ(id, U8(address), value, 1U); + if (status != (status_t) kStatus_Success) + { + error_print("PMIC reg acc - Failed to rd PMIC" + " %x, reg %x\n", id, address); + + err = SC_ERR_FAIL; + } + } + else + { + status = I2C_WRITE(id, U8(address), value, 1U); + if (status != (status_t) kStatus_Success) + { + error_print("PMIC reg acc - Failed to wr PMIC" + " %x, reg %x\n", id, address); + + err = SC_ERR_FAIL; + } +#ifdef PMIC_SECURE_WRITE + uint8_t temp; + #ifndef PMIC_CRC + #error CRC must be defined for secure writes + #endif + + /* do secure write if one of the protected registers */ + if (pf8200_reg_need_secure_write(address)) + { + /* read RANDOM_GEN register */ + status |= I2C_READ(id, U8(PF8100_RANDOM_GEN), &temp, 1U); + if (status != (status_t) kStatus_Success) + { + error_print("PMIC reg acc - Failed rd PMIC" + " %x, reg %x\n", id, address); + + err = SC_ERR_FAIL; + } + /* Write RANDOM_GEN value to RANDOM_CHK */ + status = I2C_WRITE(id, U8(PF8100_RANDOM_CHK), &temp, 1U); + if (status != (status_t) kStatus_Success) + { + error_print("PMIC register access - Failed wr PMIC" + " %x, reg %x\n", id, address); + + err = SC_ERR_FAIL; + } + } +#endif + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Service PMIC interrupt */ +/*--------------------------------------------------------------------------*/ +sc_bool_t pf8100_pmic_irq_service(pmic_id_t id) +{ + sc_bool_t rtn = SC_FALSE; + uint8_t mask = 0U; + uint8_t therm_stat = 0U; + + /* PMIC THERM */ + (void) I2C_READ(id, PF8100_THERMINT, &therm_stat, 1U); + (void) I2C_READ(id, PF8100_THERMMASK, &mask, 1U); + therm_stat &= ~mask; + if (therm_stat != 0U) + { + mask = THERM_I_MSK; + /* Mask off to prevent repeat */ + (void) I2C_WRITE(id, PF8100_THERMMASK, &mask, 1U); + + /* Clear */ + (void) I2C_WRITE(id, PF8100_THERMINT, &therm_stat, 1U); + + rtn = SC_TRUE; + } + + /*! @todo enable other interrupt sources to be cleared */ + + return rtn; +} + + +/*--------------------------------------------------------------------------*/ +/* Check for Silicon Revision */ +/*--------------------------------------------------------------------------*/ +static inline sc_err_t check_si_rev(uint8_t address) +{ + sc_err_t err = SC_ERR_NONE; + uint8_t buff = NOT_DETECTED; + + /* Check if already detected? */ + if (si_rev == NOT_DETECTED) + { + /* Read silicon rev from PMIC */ + if (I2C_READ(address, PF8100_SILICONREVID, &buff, 1U) + == (status_t) kStatus_Success) + { + /* Return result */ + si_rev = buff; + } + else + { + /* Return error */ + err = SC_ERR_FAIL; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Enable PF8100 WDOG related bits */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_wdog_enable(pmic_id_t id, sc_bool_t wd_en, + sc_bool_t stby_en, sc_bool_t wdi_stby_active) +{ + uint8_t val = 0U; /* disable all bits by default */ + sc_err_t err = SC_ERR_NONE; + + /* read the CTRL1 register */ + err |= pf8100_pmic_register_access(id, PF8100_CTRL1, SC_FALSE, &val); + + /* wdog enable bit */ + if (wd_en) { val |= 0x8U;} + /* wdog stby enable bit */ + if (stby_en) { val |= 0x4U;} + /* wdi stby enable */ + if (wdi_stby_active) { val |= 0x2U;} + + /* write back the modified register */ + err |= pf8100_pmic_register_access(id, PF8100_CTRL1, SC_TRUE, &val); + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Disable PF8100 WDOG related bits */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_wdog_disable(pmic_id_t id, sc_bool_t wd_dis, + sc_bool_t stby_en, sc_bool_t wdi_stby_active) +{ + uint8_t val = 0U; /* disable all bits by default */ + sc_err_t err = SC_ERR_NONE; + + /* read the CTRL1 register */ + err |= pf8100_pmic_register_access(id, PF8100_CTRL1, SC_FALSE, &val); + + /* wdog disabled */ + if (wd_dis) { val &= 0xF7U;} + /* wdog stby disabled */ + if (stby_en) { val &= 0xFBU;} + /* wdi stby enable disabled */ + if (wdi_stby_active) { val &= 0xFDU;} + + /* write back the modified register */ + err |= pf8100_pmic_register_access(id, PF8100_CTRL1, SC_TRUE, &val); + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set PF8100 WDOG timeout */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_wdog_set_timeout(pmic_id_t id, uint32_t* timeout) +{ + uint8_t counter = 0; + sc_err_t err = SC_ERR_NONE; + if ((*timeout > 0U) && (*timeout < 32768U)) + { + while ((*timeout < BIT32(counter)) && (counter < 0x0FU)) + {counter++;} + + counter = counter & 0x0FU; /* Mask to make sure we only write the bits we want */ + err = pf8100_pmic_register_access(id, PF8100_WD_CONFIG, SC_TRUE, &counter); + if (err == SC_ERR_NONE) + { + *timeout = BIT32(counter); /* return the exact timeout in ms */ + } + } + else + { + err = SC_ERR_PARM; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Service PF8100 WDOG */ +/*--------------------------------------------------------------------------*/ +sc_err_t pf8100_pmic_wdog_service(pmic_id_t id) +{ + uint8_t val = 0x1U; /* write a 1 to bit 0 for the WD_CLEAR register */ + return pf8100_pmic_register_access(id, PF8100_WD_CLEAR, SC_TRUE, &val); +} + diff --git a/platform/drivers/pmic/pf8100/fsl_pf8100.h b/platform/drivers/pmic/pf8100/fsl_pf8100.h new file mode 100755 index 0000000..c8d0a40 --- /dev/null +++ b/platform/drivers/pmic/pf8100/fsl_pf8100.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_PMIC_PF8100_H +#define DRV_PMIC_PF8100_H + +/*! + * @addtogroup pf8100_driver + * @{ + */ + +/*! @file */ + +#ifdef PMIC_CRC /* alias the crc functions if CRC is defined */ + #define I2C_WRITE i2c_j1850_write + #define I2C_READ i2c_j1850_read +#else + #define I2C_WRITE i2c_write + #define I2C_READ i2c_read +#endif + +/*! + * @name Defines for pf8100_vregs_t + */ +/** @{ */ +#define PF8100_CTRL1 0x37U /*!< CTRL1 register of PF8100/PF8200 */ +#define PF8100_SW1 0x4DU /*!< Base register for SW1 regulator control */ +#define PF8100_SW2 0x55U /*!< Base register for SW2 regulator control */ +#define PF8100_SW3 0x5DU /*!< Base register for SW3 regulator control */ +#define PF8100_SW4 0x65U /*!< Base register for SW4 regulator control */ +#define PF8100_SW5 0x6DU /*!< Base register for SW5 regulator control */ +#define PF8100_SW6 0x75U /*!< Base register for SW6 regulator control */ +#define PF8100_SW7 0x7DU /*!< Base register for SW7 regulator control */ +#define PF8100_LDO1 0x85U /*!< Base register for LDO1 regulator control */ +#define PF8100_LDO2 0x8BU /*!< Base register for LDO2 regulator control */ +#define PF8100_LDO3 0x91U /*!< Base register for LDO3 regulator control */ +#define PF8100_LDO4 0x97U /*!< Base register for LDO4 regulator control */ +/** @} */ + +/*! + * @name Defines for sw_mode_t + */ +/** @{ */ +#define SW_RUN_OFF 0x0U /*!< Run mode: OFF */ +#define SW_RUN_PWM 0x1U /*!< Run mode: PWM */ +#define SW_RUN_PFM 0x2U /*!< Run mode: PFM */ +#define SW_RUN_ASM 0x3U /*!< Run mode: ASM */ +#define SW_STBY_OFF (0x0U << 2U) /*!< Standby mode: OFF */ +#define SW_STBY_PWM (0x1U << 2U) /*!< Standby mode: PWM */ +#define SW_STBY_PFM (0x2U << 2U) /*!< Standby mode: PFM */ +#define SW_STBY_ASM (0x3U << 2U) /*!< Standby mode: ASM */ +/** @} */ + +/*! + * @name Defines for ldo_mode_t + */ +/** @{ */ +#define RUN_OFF_STBY_OFF 0x0U /*!< Run mode: OFF, Standby mode: OFF */ +#define RUN_OFF_STBY_EN 0x1U /*!< Run mode: OFF, Standby mode: ON */ +#define RUN_EN_STBY_OFF 0x2U /*!< Run mode: ON, Standby mode: OFF */ +#define RUN_EN_STBY_EN 0x3U /*!< Run mode: ON, Standby mode: ON */ +#define VSELECT_EN 0x8U /*!< Enable VSELECT input pin for LDO 2 only */ +/** @} */ + +/*! + * @name Defines for vmode_reg_t + */ +/** @{ */ +#define REG_STBY_MODE 0U +#define REG_RUN_MODE 1U +/** @} */ + +/*! + * This type is used to indicate which register to address. + * + * Refer to the PF8100 Datasheet for the description of regsiter. + */ +typedef uint8_t pf8100_vregs_t; + +/*! + * This type is used to indicate a switching regulator mode. + * + * Refer to the PF8100 Datasheet for the description of each mode. + * + * These modes are used in combination to designate a run and standby mode + * i.e. (SW_RUN_PWM | SW_STBY_OFF). + */ +typedef uint8_t sw_mode_t; + +/*! + * This type is used to indicate an LDO regulator mode. + * + * Refer to the PF8100 Datasheet for the description of each mode. + */ +typedef uint8_t ldo_mode_t; + +/*! + * This type is used to indicate a Switching regulator voltage setpoint + * + * Refer to the PF8100 Datasheet for the description of each mode. + */ +typedef uint8_t vmode_reg_t; + +/* Functions prototypes */ + +/*! + * This function returns the device ID and revision for the PF8100 PMIC. + * + * @param[in] id I2C address of PMIC device + * + * @return Returns a structure with the device ID and revision. + */ +pmic_version_t pf8100_get_pmic_version(pmic_id_t id); + +/*! + * This function sets the voltage of a corresponding voltage regulator for the + * PF8100 PMIC. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + * see [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[in] vol_mv New voltage setpoint for the regulator in millivolts + * @param[in] mode_to_set Mode to set the voltage for run (RUN or STANDBY) + * + * @return Returns an error code (SC_ERR_NONE = success) + + * Note \a mode_to_set is SC_TRUE for RUN and SC_FALSE for STANDBY. + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t pf8100_pmic_set_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t vol_mv, + uint32_t mode_to_set); + +/*! + * This function gets the voltage on a corresponding voltage regulator for the + * PF8100 PMIC. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + * see [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[out] vol_mv pointer to return voltage in millivolts + * @param[in] mode_to_get Mode to get the voltage for (RUN or STANDBY) + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Note \a mode_to_get is SC_TRUE for RUN and SC_FALSE for STANDBY. + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + */ +sc_err_t pf8100_pmic_get_voltage(pmic_id_t id, uint32_t pmic_reg, uint32_t *vol_mv, + uint32_t mode_to_get); + +/*! + * This function sets the mode of the specified regulator. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + see [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[in] mode mode to set the regulator; + * see [sw_mode_t](@ref sw_mode_t) + * and [ldo_mode_t](@ref ldo_mode_t) + * + * Note SW modes are used in combination to designate a run and standby mode + * i.e. (SW_RUN_PWM | SW_STBY_OFF). + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t pf8100_pmic_set_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t mode); + +/*! + * This function gets the mode of the specified regulator. + * + * @param[in] id I2C address of PMIC device + * @param[in] pmic_reg Register corresponding to regulator; + see [pf8100_vregs_t](@ref pf8100_vregs_t) + * @param[out] mode pointer to return mode in raw hex form + * + * Note SW modes are used in combination to designate a run and standby mode + * i.e. (SW_RUN_PWM | SW_STBY_OFF). + * + * @return Returns an error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * - SC_ERR_FAIL if writing the register failed + */ +sc_err_t pf8100_pmic_get_mode(pmic_id_t id, uint32_t pmic_reg, uint32_t *mode); +/*! + * This function gets the current PMIC temperature as sensed by the + * PMIC temperature sensor. + * + * @param[in] id I2C address of PMIC device + * + * @return returns the temp sensed by the PMIC in a UINT32 in Celsius + * + * Return errors: + * - SC_ERR_CONFIG if temperature monitor is not enabled + * + * Note PMIC PF100 temp is returned as the highest temp sensor enabled. + */ +uint32_t pf8100_get_pmic_temp(pmic_id_t id); + +/*! + * This function sets the temp alarm for the PMIC in Celsius + * + * @param[in] id I2C address of PMIC device + * @param[in] temp Temperature to set the alarm + * + * Note the granularity for PF100 PMIC only allows the following + * values: + * 80 + * 95 + * 110 + * 125 + * 140 + * 155 + * + * @return Returns the temperature that the alarm is set to in Celsius + */ +uint32_t pf8100_set_pmic_temp_alarm(pmic_id_t id, uint32_t temp); + +/* + * This function allows access to individual registers of the PF8100 + * + * @param[in] id I2C address of PMIC device + * @param[in] address register address to access + * @param[in] read_write bool indicating read(SC_FALSE/0) or write(SC_TRUE/1) + * @param[in,out] value value to read or to set + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * + */ +sc_err_t pf8100_pmic_register_access(pmic_id_t id, uint32_t address, + sc_bool_t read_write, uint8_t* value); + +/*! + * This function services the interrupt for the temp alarm + * + * @param[in] id I2C address of PMIC device + * + * @return Returns SC_TRUE if the temperature interrupt was cleared + */ +sc_bool_t pf8100_pmic_irq_service(pmic_id_t id); + +/* + * This function enables PF8100 internal WDOG configuration bits + * + * @param[in] id I2C address of PMIC device + * @param[in] wd_en bool indicating to enable(SC_TRUE/1) or to + * ignore the wdog bit + * @param[in] stby_en bool indicating whether to set(SC_TRUE/1) wdog stby en + * bit or ignore(SC_FALSE/0) + * @param[in] wdi_stby_active bool indicating whether wdi stby active bit should be + * set(SC_TRUE/1) or ignored(SC_FALSE/0) + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * + */ +sc_err_t pf8100_pmic_wdog_enable(pmic_id_t id, sc_bool_t wd_en, + sc_bool_t stby_en, sc_bool_t wdi_stby_active); + +/* + * This function disables PF8100 internal WDOG configuration bits + * + * @param[in] id I2C address of PMIC device + * @param[in] wd_dis bool indicating to clear(SC_TRUE/1) or + * ignore wdog enable bit(SC_FALSE/0) + * @param[in] stby_en bool indicating if stby enable bit will be + * cleared(SC_TRUE/1) or ignored(SC_FALSE/0) + * @param[in] wdi_stby_active bool indicating whether to clear(SC_TRUE/1) + * or ignore(SC_FALSE/0) wdi_stby_active bit + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * + */ +sc_err_t pf8100_pmic_wdog_disable(pmic_id_t id, sc_bool_t wd_dis, + sc_bool_t stby_en, sc_bool_t wdi_stby_active); +/* + * This function sets the timeout of the PF8100 internal WDOG + * + * @param[in] id I2C address of PMIC device + * @param[in,out] timeout Desired timeout in ms. The function will + * calculate next largest interval and return the + * exact timeout value in ms. + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * + */ +sc_err_t pf8100_pmic_wdog_set_timeout(pmic_id_t id, uint32_t* timeout); + +/* + * This function services the PF8100 internal WDOG + * + * @param[in] id I2C address of PMIC device + * + * @return Returns ar error code (SC_ERR_NONE = success) + * + * Return errors: + * - SC_ERR_PARM if invalid parameters + * + */ +sc_err_t pf8100_pmic_wdog_service(pmic_id_t id); + +#endif + +/** @} */ + diff --git a/platform/drivers/reset/Makefile b/platform/drivers/reset/Makefile new file mode 100755 index 0000000..7c3acab --- /dev/null +++ b/platform/drivers/reset/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/reset/fsl_reset.o + +DIRS += $(OUT)/drivers/reset + diff --git a/platform/drivers/reset/fsl_reset.h b/platform/drivers/reset/fsl_reset.h new file mode 100755 index 0000000..4a5c9e8 --- /dev/null +++ b/platform/drivers/reset/fsl_reset.h @@ -0,0 +1,58 @@ +/* + * Copyright 2019-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_RESET_H +#define DRV_RESET_H + +/*! + * @addtogroup reset_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "fsl_device_registers.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +void RESET_Peripheral(ECSR_Reset_Type *base, uint32_t reset_reg, + uint32_t reset_mask, sc_bool_t old_sequence, + uint8_t bus_ack_timeout); + +#endif /* DRV_RESET_H */ + +/** @} */ + diff --git a/platform/drivers/rgpio/Makefile b/platform/drivers/rgpio/Makefile new file mode 100755 index 0000000..cfc65d8 --- /dev/null +++ b/platform/drivers/rgpio/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/rgpio/fsl_rgpio.o + +DIRS += $(OUT)/drivers/rgpio + diff --git a/platform/drivers/rgpio/fsl_rgpio.h b/platform/drivers/rgpio/fsl_rgpio.h new file mode 100755 index 0000000..9fc41c9 --- /dev/null +++ b/platform/drivers/rgpio/fsl_rgpio.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RGPIO_H_ +#define _FSL_RGPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rgpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +/*! @brief RGPIO driver version 2.0.2. */ +#define FSL_RGPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/** @} */ + +/*! @brief RGPIO direction definition */ +typedef enum _rgpio_pin_direction +{ + kRGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kRGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} rgpio_pin_direction_t; + +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief RGPIO checker attribute */ +typedef enum _rgpio_checker_attribute +{ + kRGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kRGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kRGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ +} rgpio_checker_attribute_t; +#endif + +/*! + * @brief The RGPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _rgpio_pin_config +{ + rgpio_pin_direction_t pinDirection; /*!< RGPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} rgpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup rgpio_driver + * @{ + */ + +/*! @name RGPIO Configuration */ +/** @{ */ + +/*! + * @brief Initializes a RGPIO pin used by the board. + * + * To initialize the RGPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the RGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO port pin number + * @param config RGPIO pin configuration pointer + */ +void RGPIO_PinInit(RGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config); + +/*! + * @brief Gets the RGPIO instance according to the RGPIO base + * + * @param base RGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval RGPIO instance + */ +uint32_t RGPIO_GetInstance(RGPIO_Type *base); +/** @} */ + +/*! @name RGPIO Output Operations */ +/** @{ */ + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO pin number + * @param output RGPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void RGPIO_PinWrite(RGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinWrite. + */ +static inline void RGPIO_WritePinOutput(RGPIO_Type *base, uint32_t pin, uint8_t output) +{ + RGPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortSet(RGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortSet. + */ +static inline void RGPIO_SetPinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 0. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortClear(RGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Sets the output level of the multiple RGPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClear. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_ClearPinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple RGPIO pins. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +static inline void RGPIO_PortToggle(RGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple RGPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortToggle. + */ +static inline void RGPIO_TogglePinsOutput(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortToggle(base, mask); +} +/** @} */ + +/*! @name RGPIO Input Operations */ +/** @{ */ + +/*! + * @brief Reads the current input value of the RGPIO port. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param pin RGPIO pin number + * @retval RGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t RGPIO_PinRead(RGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*! + * @brief Reads the current input value of the RGPIO port. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PinRead. + */ +static inline uint32_t RGPIO_ReadPinInput(RGPIO_Type *base, uint32_t pin) +{ + return RGPIO_PinRead(base, pin); +} + +/** @} */ + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! @name RGPIO Interrupt */ +/** @{ */ + +/*! + * @brief Reads the RGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @retval The current RGPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t RGPIO_PortGetInterruptFlags(RGPIO_Type *base); + +/*! + * @brief Reads the RGPIO port interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortGetInterruptFlags. + */ +static inline uint32_t RGPIO_GetPinsInterruptFlags(RGPIO_Type *base) +{ + return RGPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears multiple RGPIO pin interrupt status flags. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +void RGPIO_PortClearInterruptFlags(RGPIO_Type *base, uint32_t mask); + +/*! + * @brief Clears multiple RGPIO pin interrupt status flags. + * @deprecated Do not use this function. It has been superceded by @ref RGPIO_PortClearInterruptFlags. + */ +static inline void RGPIO_ClearPinsInterruptFlags(RGPIO_Type *base, uint32_t mask) +{ + RGPIO_PortClearInterruptFlags(base, mask); +} +#endif +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The RGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base RGPIO peripheral base pointer (RGPIOA, RGPIOB, RGPIOC, and so on.) + * @param mask RGPIO pin number macro + */ +void RGPIO_CheckAttributeBytes(RGPIO_Type *base, rgpio_checker_attribute_t attribute); +#endif + +/** @} */ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO registers are aliased to the IOPORT interface. + * Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/** @{ */ + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); + +/*! + * @brief Initializes the FGPIO peripheral. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortInit. + */ +static inline void FGPIO_Init(FGPIO_Type *base) +{ + FGPIO_PortInit(base); +} +#endif +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * Define a digital input pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * rgpio_pin_config_t config = + * { + * kRGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const rgpio_pin_config_t *config); + +/*! + * @brief Gets the FGPIO instance according to the RGPIO base + * + * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval FGPIO instance + */ +uint32_t FGPIO_GetInstance(FGPIO_Type *base); +/** @} */ + +/*! @name FGPIO Output Operations */ +/** @{ */ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinWrite. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + FGPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortSet. + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClear. + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortToggle. + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortToggle(base, mask); +} +/** @} */ + +/*! @name FGPIO Input Operations */ +/** @{ */ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} + +/*! + * @brief Reads the current input value of the FGPIO port. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PinRead + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return FGPIO_PinRead(base, pin); +} +/** @} */ + +#if defined(FSL_FEATURE_SOC_PORT_COUNT) && FSL_FEATURE_SOC_PORT_COUNT +/*! @name FGPIO Interrupt */ +/** @{ */ + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortGetInterruptFlags. + */ +static inline uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + return FGPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * @deprecated Do not use this function. It has been superceded by @ref FGPIO_PortClearInterruptFlags. + */ +static inline void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + FGPIO_PortClearInterruptFlags(base, mask); +} +#endif +#if defined(FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_RGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the RGPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, rgpio_checker_attribute_t attribute); +#endif + +/** @} */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_RGPIO_H_*/ diff --git a/platform/drivers/seco/fsl_seco.h b/platform/drivers/seco/fsl_seco.h new file mode 100755 index 0000000..6b971f6 --- /dev/null +++ b/platform/drivers/seco/fsl_seco.h @@ -0,0 +1,927 @@ +/* + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_SECO_H +#define DRV_SECO_H + +/*! + * @addtogroup seco_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" +#include "svc/seco/api.h" + +/* Defines */ + +/*! + * @name Defines for seco_lifecycle_t + */ +/** @{ */ +#define SECO_LIFECYCLE_DEFAULT BIT(0) /*!< Default fab mode (early_fuses_pgrm not blown) */ +#define SECO_LIFECYCLE_FAB BIT(1) /*!< Fab mode */ +#define SECO_LIFECYCLE_NO_SECRETS BIT(2) /*!< No secrets */ +#define SECO_LIFECYCLE_SECRETS BIT(3) /*!< With Secrets */ +#define SECO_LIFECYCLE_SC_FW_CLSD BIT(4) /*!< SCU FW Closed */ +#define SECO_LIFECYCLE_SECO_FW_CLSD BIT(5) /*!< SECO FW Closed */ +#define SECO_LIFECYCLE_CLOSED BIT(6) /*!< Closed */ +#define SECO_LIFECYCLE_CLOSED_FW BIT(7) /*!< Closed with FW */ +#define SECO_LIFECYCLE_PART_RTN BIT(8, /*!< Partial field return */ +#define SECO_LIFECYCLE_RTN BIT(9) /*!< Field return */ +#define SECO_LIFECYCLE_NO_RTN BIT(10) /*!< No Return */ +/** @} */ + +/*! + * @name Defines for seco_snvs_id_t + */ +/** @{ */ +#define AHAB_SNVS_ID_INIT 0x00U /*!< Init SNVS */ +#define AHAB_SNVS_ID_POWER_OFF 0x01U /*!< Power off the system */ +#define AHAB_SNVS_ID_SRTC 0x02U /*!< R/W the SRTC */ +#define AHAB_SNVS_ID_SRTC_CALB 0x03U /*!< R/W the SRTC calibration */ +#define AHAB_SNVS_ID_SRTC_ALRM 0x04U /*!< R/W the SRTC alarm */ +#define AHAB_SNVS_ID_RTC 0x05U /*!< R/W the RTC */ +#define AHAB_SNVS_ID_RTC_CALB 0x06U /*!< R/W the RTC calibration */ +#define AHAB_SNVS_ID_RTC_ALRM 0x07U /*!< R/W the RTC alarm */ +#define AHAB_SNVS_ID_BTN_CONFIG 0x08U /*!< R/W the button configuration */ +#define AHAB_SNVS_ID_BTN_MASK 0x09U /*!< R/W the button mask */ +#define AHAB_SNVS_ID_BTN 0x0AU /*!< R/W the button state */ +#define AHAB_SNVS_ID_BTN_CLEAR 0x0BU /*!< Clear the button IRQ */ +#define AHAB_SNVS_ID_SSM_STATE 0x0CU /*!< Read the SSM state */ +#define AHAB_SNVS_ID_BTN_TIME 0x0DU /*!< R/W the button time parameters */ +#define AHAB_SNVS_ID_WAKE_UP_IT 0x0EU /*!< Clear the wake IRQ */ +/** @} */ + +/*! + * @name Defines for SNVS access + */ +/** @{ */ +#define SECO_SNVS_READ 0U /*!< SNVS read operation */ +#define SECO_SNVS_WRITE 1U /*!< SNVS write operation */ +/** @} */ + +/*! + * @name Macros for version parsing + */ +/** @{ */ +#define SECO_PROD_VER(X) (((X) >> 16) & 0x7FFFUL) /*!< Extract SECO production ver */ +#define SECO_MAJOR_VER(X) (((X) >> 4) & 0xFFFUL) /*!< Extract SECO major ver */ +#define SECO_MINOR_VER(X) ((X) & 0xFUL) /*!< Extract SECO minor ver */ +/** @} */ + +/*! + * @name Defines for V2X state + */ +/** @{ */ +#define V2X_STATE_AUTH_RX 0x01U /*!< Authentication request received */ +#define V2X_STATE_PROV_NORMAL 0x02U /*!< Provisioned successfully in normal mode */ +#define V2X_STATE_PROV_DEBUG 0x04U /*!< Provisioned successfully in debug mode */ +#define V2X_STATE_AUTH_IP 0x08U /*!< Authentication on going */ +#define V2X_STATE_AUTH_SUCCESS 0x10U /*!< Authentication success */ +#define V2X_STATE_AUTH_FAIL 0x20U /*!< Authentication failure */ +#define V2X_STATE_CRYPTO_DIS 0x40U /*!< Crypto accelerators disabled */ +#define V2X_STATE_HOLD_EN 0x80U /*!< V2X provisioning on hold */ +/** @} */ + +/*! + * @name Defines for V2X power mode and state + */ +/** @{ */ +#define V2X_POWER_STATE_UNKNOWN 0U /*!< Unknown power state */ +#define V2X_POWER_STATE_ON 1U /*!< Power on state */ +#define V2X_POWER_STATE_LP 2U /*!< Low power state */ +#define V2X_POWER_STATE_STBY 3U /*!< Standby state */ +#define V2X_POWER_STATE_OFF 4U /*!< Power off state */ +/** @} */ + +/*! + * @name Defines for V2X power flags + */ +/** @{ */ +#define V2X_POWER_NONE 0x00U /*!< No flags */ +#define V2X_POWER_FORCE 0x01U /*!< Force power state change */ +/** @} */ + +/*! + * @name Defines for V2X recovery flags + */ +/** @{ */ +#define V2X_RECOVER_NONE 0x00U /*!< No flags */ +#define V2X_RECOVER_AUTH 0x01U /*!< Send FW recovery */ +/** @} */ + +#ifdef NO_DEVICE_ACCESS + /*! + * This variable is used to access fake SECO. + */ + extern uint32_t temp_seco[]; + #define HAS_TEMP_SECO +#endif + +/* Types */ + +/*! + * This type is used to return the lifecycle. + */ +typedef uint16_t seco_lifecycle_t; + +/*! + * This type is used to indicate the ID of anSNVS register to access. + */ +typedef uint8_t seco_snvs_id_t; + +/* Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +/*! + * This function initializes the SECO driver. + * + * @param[in] phase Init phase + * + * Called when SCFW boots. + */ +void SECO_Init(boot_phase_t phase); + +/*! + * This function configures the CAAM MP. + * + * @param[in] master Index of job ring / out + * @param[in] lock Lock state of config + * @param[in] sa Secure state + * @param[in] did XRDC2 Domain ID + * @param[in] sid SMMU Stream ID + * + * Called by the Resource Manager to configure CAAM job ring access and + * output parameters. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_CAAM_Config(uint16_t master, sc_bool_t lock, sc_rm_spa_t sa, + sc_rm_did_t did, sc_rm_sid_t sid); + +/*! + * This function clears the CAAM MP cache. It is called by the Power + * Manager when CAAM power state is lost. + */ +void SECO_ClearCache(void); + +/*! + * This function configures MU ownership. + * + * @param[in] mu Index of MU + * @param[in] sa Secure state + * @param[in] did XRDC2 Domain ID + * + * Called by the Resource Manager to configure MU access. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_MU_Config(uint8_t mu, sc_rm_spa_t sa, sc_rm_did_t did); + +/*! + * This function partitions the monotonic counter. + * + * @param[in] she number of SHE bits + * + * SECO uses an OTP monotonic counter to protect the SHE and HSM key-stores + * from roll-back attack. This function is used to define the number of + * monotonic counter bits allocated to SHE use. Two monotonic counter bits + * are used to store this information while the remaining bits are allocated + * to the HSM user. This function must be called before any SHE or HSM key stores + * are created in the system, otherwise the default configuration is applied. + * + * If the partition has been already configured, any attempt to re-configure + * the SHE partition to a different value will result in a failure response. + * + * @return Returns the current number of SHE bits. + * + * See the SECO API Reference Guide for more info. + */ +uint16_t SECO_SetMonoCounterPartition(uint16_t she); + +/*! + * This function configures the SECO in FIPS mode. + * + * @param[in] mode FIPS mode + * + * This function permanently configures the SECO in FIPS approved mode. When in + * FIPS approved mode the following services will be disabled and receive a + * failure response: + * + * - Encrypted boot is not supported + * - Attestation is not supported + * - Manufacturing protection is not supported + * - DTCP load + * - SHE services are not supported + * - Assign JR is not supported (all JRs owned by SECO) + * + * @return Returns the failure reason. + * + * See the SECO API Reference Guide for more info. + */ +uint32_t SECO_SetFipsMode(uint8_t mode); + +/*! + * This function will securely zeroize all plaintext secret and private + * cryptographic keys and CSPs within the module. + * + * @param[in] addr address of message block + * + * Note \a addr must be a pointer to a signed message block. + * + * This function is effective when the part is configured in FIPS approved + * mode only, no effects otherwise. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_FipsKeyZero(sc_faddr_t addr); + +/** @} */ + +/*! + * @name Power Mangement Functions + * @{ + */ + +/*! + * This function notifies SECO that a subsystem power state has changed. + * + * @param[in] ss Subsystem + * @param[in] inst Subsystem instance + * @param[in] up Power state + * + * Called by the Power Manager when subsystem power state changes. + */ +void SECO_Power(sc_sub_t ss, uint32_t inst, sc_bool_t up); + +/*! + * This function notifies SECO that CAAM is powering down. + * + * Called by the Power Manager before powering down the CAAM. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_CAAM_PowerDown(void); + +/*! + * This function notifies SECO the system is entering low power mode. + * + * Called by the Power Manager before entering LPM. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_EnterLPM(void); + +/*! + * This function notifies SECO the system is has exited low power mode. + * + * Called by the Power Manager before after exiting LPM. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_ExitLPM(void); + +/** @} */ + +/*! + * @name Image Functions + * @{ + */ + +/*! + * This function loads a SECO image. + * + * @param[in] addr_src address of image source + * @param[in] addr_dst address of image destination + * @param[in] len lenth of image to load + * @param[in] fw SC_TRUE = firmware load + * + * This is used to load images via the SECO. Examples include SECO + * Firmware and IVT/CSF data used for authentication. These are usually + * loaded into SECO TCM. \a addr_src is in secure memory. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_Image_Load(sc_faddr_t addr_src, sc_faddr_t addr_dst, uint32_t len, + sc_bool_t fw); + +/*! + * This function is used to authenticate a SECO image or command. + * + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * @param[in] mask1 metadata + * @param[in] mask2 metadata + * + * This is used to authenticate a SECO image or issue a security + * command. \a addr often points to an container. It is also + * just data (or even unused) for some commands. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_Authenticate(sc_seco_auth_cmd_t cmd, sc_faddr_t addr, + uint32_t mask1, uint32_t mask2); + +/** @} */ + +/*! + * @name Lifecycle Functions + * @{ + */ + +/*! + * This function is used get the lifecycle from the ADM. + * + * @return Returns the lifecycle. + */ +seco_lifecycle_t SECO_Get_Lifecycle(void); + +/*! + * This function updates the lifecycle of the device. + * + * @param[in] change desired lifecycle transistion + * + * This function is used for going from Open to NXP Closed to OEM Closed. + * Note \a change is NOT the new desired lifecycle. It is a lifecycle + * transition as documented in the SECO API Reference Guide. + * + * If any SECO request fails or only succeeds because the part is in an + * "OEM open" lifecycle, then a request to transition from "NXP closed" + * to "OEM closed" will also fail. For example, booting a signed container + * when the OEM SRK is not fused will succeed, but as it is an abnormal + * situation, a subsequent request to transition the lifecycle will return + * an error via seco_err. + */ +void SECO_ForwardLifecycle(uint32_t change); + +/*! + * This function updates the lifecycle to one of the return lifecycles. + * + * @param[in] addr address of message block + * + * Note \a addr must be a pointer to a signed message block. + * + * To switch back to NXP states (Full Field Return), message must be signed + * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM + * SRK. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_ReturnLifecycle(sc_faddr_t addr); + +/*! + * This function is used to commit into the fuses any new SRK revocation + * and FW version information that have been found in the primary and + * secondary containers. + * + * @param[in,out] info pointer to information type to be committed + * + * The return \a info will contain what was actually committed. + */ +void SECO_Commit(uint32_t *info); + +/** @} */ + +/*! + * @name Attestation Functions + * @{ + */ + +/*! + * This function is used to set the attestation mode. + * + * @param[in] mode mode + * + * This is used to set the SECO attestation mode. This can be prover + * or verfier. See the SECO API Reference Guide for more on the + * suported modes, mode values, and mode behavior. + */ +void SECO_AttestMode(uint32_t mode); + +/*! + * This function is used to request atestation. + * + * @param[in] nonce unique value + * + * This is used to ask SECO to perform an attestation. The result depends + * on the attestation mode. After this call, the signature can be + * requested or a verify can be requested. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_Attest(uint64_t nonce); + +/*! + * This function is used to retrieve the attestation public key. + * Mode must be verifier. + * + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 96 bytes of space. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_GetAttestPublicKey(sc_faddr_t addr); + +/*! + * This function is used to retrieve attestation signature and parameters. + * Mode must be provider. + * + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parmater must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 120 bytes of space. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_GetAttestSign(sc_faddr_t addr); + +/*! + * This function is used to verify attestation. Mode must be verifier. + * + * @param[in] addr address of signature + * + * The \a addr parmater must point to an address SECO can access. It must be + * 64-bit aligned. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_AttestVerify(sc_faddr_t addr); + +/** @} */ + +/*! + * @name Key Functions + * @{ + */ + +/*! + * This function is used to generate a SECO key blob. + * + * @param[in] id key identifier + * @param[in] load_addr load address + * @param[in] export_addr export address + * @param[in] max_size max export size + * + * This function is used to encapsulate sensitive keys in a specific structure + * called a blob, which provides both confidentiality and integrity protection. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_GenKeyBlob(uint32_t id, sc_faddr_t load_addr, + sc_faddr_t export_addr, uint16_t max_size); + +/*! + * This function is used to load a SECO key. + * + * @param[in] id key identifier + * @param[in] addr key address + * + * This function is used to install private cryptographic keys encapsulated + * in a blob previously generated by SECO. The controller can be either the + * IEE or the VPU. The blob header carries the controller type and the key + * size, as provided by the user when generating the key blob. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_LoadKey(uint32_t id, sc_faddr_t addr); + +/** @} */ + +/*! + * @name Manufacturing Protection Functions + * @{ + */ + +/*! + * This function is used to get the manufacturing protection public key. + * + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * This function is supported only in OEM-closed lifecycle. It generates + * the mfg public key and stores it in a specific location in the secure + * memory. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_GetMPKey(sc_faddr_t dst_addr, uint16_t dst_size); + +/*! + * This function is used to update the manufacturing protection message + * register. + * + * @param[in] addr data address + * @param[in] size size + * @param[in] lock lock_reg + * + * This function is supported only in OEM-closed lifecycle. It updates the + * content of the MPMR (Manufacturing Protection Message register of 256 + * bits). This register will be appended to the input-data message when + * generating the signature. Please refer to the CAAM block guide for details. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_UpdateMPMR(sc_faddr_t addr, uint8_t size, uint8_t lock); + +/*! + * This function is used to get the manufacturing protection signature. + * + * @param[in] msg_addr message address + * @param[in] msg_size message size + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * This function is used to generate an ECDSA signature for an input-data + * message and to store it in a specific location in the secure memory. It + * is only supported in OEM-closed lifecycle. In order to get the ECDSA + * signature, the RNG must be initialized. In case it has not been started + * an error will be returned. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_GetMPSign(sc_faddr_t msg_addr, uint16_t msg_size, + sc_faddr_t dst_addr, uint16_t dst_size); + +/** @} */ + +#ifdef HAS_V2X + +/*! + * @name V2X Functions + * @{ + */ + +/*! + * This function is used to forward a message received from V2X. + * + * @param[in] buf pointer to message buffer + * + * @return Returns number of words in response. + */ +uint8_t SECO_V2X_Forward(uint32_t *buf); + +/*! + * This function sends a ping to V2X through SECO. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_V2X_Ping(void); + +/*! + * This function is used to set a control variable indicating whether or not the + * configuration of the V2X must be done as soon as possible or should be delayed + * and left under the control of the SCU. + * + * @param[in] hold_value 0=no delay, 1=delay + * + * See the SECO API Reference Guide for more info. + */ +void SECO_V2X_Hold(uint32_t hold_value); + +/*! + * This function is used to provision the V2X either in "normal" mode or in "debug" + * mode. Provisioning for debug request will be accepted only in NXP open LC. In NXP + * closed LC, the SECO_EnableDebug() function must be used instead. + * + * @param[in] provision_mode 0=normal, 1=debug + * + * See the SECO API Reference Guide for more info. + */ +void SECO_V2X_Provision(uint32_t provision_mode); + +/*! + * This function returns the v2x_state (provisioned, successfully authenticated, etc.). + * It should be sent after the v2x_authenticate_request in order to get the result + * of the v2x authentication once finished. + * + * @param[out] req_status V2X authentication request status + * @param[out] power_state V2X power state + * + * @return Returns the V2X state. + * + * - Bit 0: v2x authentication request received + * - Bit 1: v2x provisioned successfully in normal mode + * - Bit 2: v2x provisioned successfully in debug mode + * - Bit 3: v2x authentication on going + * - Bit 4: v2x authentication success + * - Bit 5: v2x authentication failure + * - Bit 6: v2x crypto disabled + * - Bit 7: v2x hold enabled + * + * See the SECO API Reference Guide for more info. + */ +uint8_t SECO_V2X_GetState(uint32_t *req_status, uint8_t *power_state); + +/*! + * This function sets the V2X power state on SECO. If the request is successful, + * the V2X power state will be updated on SECO. Otherwise, the requested power state + * is not allowed and error will be reported via seco_err. + * + * @param[in] power_mode requested power mode + * @param[in] flags flags to pass to SECO + * @param[out] addr pointer to return FW address + * + * See the SECO API Reference Guide for more info. + */ +void SECO_V2X_Power(uint8_t power_mode, uint8_t flags, sc_saddr_t *addr); + + /*! + * This function will recover the V2X firmware after a power off. If the flag is + * V2X_RECOVER_AUTH, SECO will send a V2X authenticate request to V2X using the + * V2X container header from the last V2X authenticate request. + * + * @param[in] flags flags to pass to SECO + * + * See the SECO API Reference Guide for more info. + */ +void SECO_V2X_FW_Recovery(uint8_t flags); + + /*! + * This function will notify SECO that the V2X images used for the last V2X + * authentication have been/will be move to a new location given in parameter. + * If the request is successful SECO will use the new location of the images + * for V2X recovery. + * + * @param[in] addr new V2X FW address + * + * See the SECO API Reference Guide for more info. + */ +void SECO_V2X_Remap_FW(sc_saddr_t addr); + +/** @} */ + +#endif + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used to return the SECO FW build info. + * + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + * @param[out] dirty pointer to return dirty flag + * + * See the SECO API Reference Guide for more info. + */ +void SECO_Version(uint32_t *version, uint32_t *commit, sc_bool_t *dirty); + +/*! + * This function is used to return SECO chip info. + * + * @param[out] lc pointer to return lifecycle + * @param[out] monotonic pointer to return monotonic counter + * @param[out] uid_l pointer to return UID (lower 32 bits) + * @param[out] uid_h pointer to return UID (upper 32 bits) + * + * See the SECO API Reference Guide for more info. + */ +void SECO_ChipInfo(uint16_t *lc, uint16_t *monotonic, + uint32_t *uid_l, uint32_t *uid_h); + +/*! + * This function notifies SECO that a JTAG connection has been made. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_AttachDebug(void); + +/*! + * This function securely enables debug. + * + * @param[in] addr address of message block + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_EnableDebug(sc_faddr_t addr); + +/*! + * This function is used to return an event from the SECO error log. + * + * @param[out] idx index of event to return + * + * @return Returns the event. + * + * Read of \a idx 0 captures events from SECO. Loop starting + * with 0 until an error is returned to dump all events. + * + * See the SECO API Reference Guide for more info. + */ +uint32_t SECO_GetEvent(uint8_t idx); + +/*! + * This function dumps low-level SECO debug info to the SCU debug + * UART. + */ +void SECO_DumpDebug(void); + +/*! + * This function return the internal SECO error number returned by + * the last SECO function call. It is valid if seco_err != SC_R_NONE. + * + * See the SECO API Reference Guide for a description of these + * internal error codes. + * + * @return Returns the error number. + */ +uint32_t SECO_ErrNumber(void); + +/** @} */ + +/*! + * @name Miscellaneous Functions + * @{ + */ + +/*! + * This function sends a ping to SECO. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_Ping(void); + +/*! + * This function sends a a message to SECO to service the + * 24H watchdog. SCFW sends this periodically. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_KickWdog(void); + +/*! + * This function writes a given fuse word index. + * + * @param[in] word fuse word index + * @param[in] val fuse write value + * + * The command is passed as is to SECO. SECO uses part of the + * \a word parameter to indicate if the fuse should be locked + * after programming. See the "Write common fuse" section of + * the SECO API Reference Guide for more info. + */ +void SECO_WriteFuse(uint32_t word, uint32_t val); + +/*! + * This function securely writes a group of fuse words. + * + * @param[in] addr address of message block + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_SecureWriteFuse(sc_faddr_t addr); + +/*! + * This function applies a patch. + * + * @param[in] addr address of message block + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_ScuPatch(sc_faddr_t addr); + +/*! + * This function starts the random number generator. + * + * @return Returns the state of RNG. + * + * The RNG is started automatically after all CPUs are booted. This + * function can be used to start earlier and to check the status. + * + * See the SECO API Reference Guide for more info. + */ +sc_seco_rng_stat_t SECO_StartRNG(void); + +/*! + * This function is used to send a generic signed message to the + * SECO SHE/HSM components. + * + * @param[in] addr address of message block + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_SABSignedMesg(sc_faddr_t addr); + +/** @} */ + +/*! + * @name SNVS Functions + * @{ + */ + +/*! + * This function write an SNVS parameter. + * + * @param[in] id ID of parameter to write + * @param[in] val value to write + * + * This function is used by the SNVS driver. Users should + * call that driver instead of this function. + * + * See the SECO API Reference Guide for more info. + */ +void SECO_WriteSNVS(seco_snvs_id_t id, uint32_t val); + +/*! + * This function reads an SNVS parameter. + * + * @param[in] id ID of parameter to read + * + * This function is used by the SNVS driver. Users should + * call that driver instead of this function. + * + * @return Returns the value read. + * + * See the SECO API Reference Guide for more info. + */ +uint32_t SECO_ReadSNVS(seco_snvs_id_t id); + +/*! + * This function is used to manage the SNVS. It allows reading and + * writing of various SNVS registers. + * + * @param[in] id ID of parameter to read + * @param[in] access Access type (read or write) + * @param[in,out] val pointer to value to read or write + * @param[in] size number of words to read or write + * + * For info on what the SNVS registers do, refer to the SNVS section + * of the SRM. + * + * Note many aspects of the SNVS are used by SECO and not available for + * use (e.g. LPGPR0) and this function will not allow access to those + * registers/fields. See the SECO API Reference Guide for more info. + */ +void SECO_ManageSNVS(uint8_t id, uint8_t access, uint32_t *val, uint8_t size); + +/*! + * This function is used to manage the SNVS DGO. It allows reading and + * writing of various privileged SNVS DGO registers. + * + * @param[in] id ID of parameter to read + * @param[in] access Access type (read or write) + * @param[in,out] val pointer to value to read or write + * + * For info on what the SNVS registers do, refer to the SNVS section + * of the SRM. + */ +void SECO_ManageSNVS_DGO(uint8_t id, uint8_t access, uint32_t *val); + +/** @} */ + +/* Externs */ + +/*! SECO error return */ +extern sc_err_t seco_err; + +#endif /* DRV_SECO_H */ + +/** @} */ + diff --git a/platform/drivers/seco/v2/Makefile b/platform/drivers/seco/v2/Makefile new file mode 100755 index 0000000..9159b55 --- /dev/null +++ b/platform/drivers/seco/v2/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/seco/v2/fsl_seco.o + +DIRS += $(OUT)/drivers/seco/v2 + diff --git a/platform/drivers/snvs/fsl_snvs.h b/platform/drivers/snvs/fsl_snvs.h new file mode 100755 index 0000000..b3eef1f --- /dev/null +++ b/platform/drivers/snvs/fsl_snvs.h @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_SNVS_H +#define DRV_SNVS_H + +/*! + * @addtogroup snvs_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +/*! + * @name Defines for snvs_btn_config_t + * + * Used to configure which feature of the button (BTN) input signal + * constitutes "active". + * + * BTN_CONFIG field in the SNVS_HP regsiter. See the SNVS section + * of the SRM. + */ +/** @{ */ +#define SNVS_DRV_BTN_CONFIG_ACTIVELOW 0U /*!< Button signal is active low */ +#define SNVS_DRV_BTN_CONFIG_ACTIVEHIGH 1U /*!< Button signal is active high */ +#define SNVS_DRV_BTN_CONFIG_RISINGEDGE 2U /*!< Button signal is active on the rising edge */ +#define SNVS_DRV_BTN_CONFIG_FALLINGEDGE 3U /*!< Button signal is active on the falling edge */ +#define SNVS_DRV_BTN_CONFIG_ANYEDGE 4U /*!< Button signal is active on any edge */ +/** @} */ + +/*! + * @name Defines for snvs_btn_on_time_t + * + * Used to configure the period of time after BTN is asserted before + * SoC power is turned on. + * + * ON_TIME field in the SNVS_LP regsiter. See the SNVS section + * of the SRM. + */ +/** @{ */ +#define SNVS_DRV_BTN_ON_50MS 0U /*!< 500 msec off->on transition time */ +#define SNVS_DRV_BTN_ON_100MS 1U /*!< 50 msec off->on transition time */ +#define SNVS_DRV_BTN_ON_500MS 2U /*!< 100 msec off->on transition time */ +#define SNVS_DRV_BTN_ON_0MS 3U /*!< 0 msec off->on transition time */ +/** @} */ + +/*! + * @name Defines for snvs_btn_debounce_t + * + * Use to configure the amount of debounce time for the BTN input signal. + * + * DEBOUNCE field in the SNVS_LP regsiter. See the SNVS section + * of the SRM. + */ +/** @{ */ +#define SNVS_DRV_BTN_DEBOUNCE_50MS 0U /*!< 50 msec debounce */ +#define SNVS_DRV_BTN_DEBOUNCE_100MS 1U /*!< 100 msec debounce */ +#define SNVS_DRV_BTN_DEBOUNCE_500MS 2U /*!< 500 msec debounce */ +#define SNVS_DRV_BTN_DEBOUNCE_0MS 3U /*!< 0 msec debounce */ +/** @} */ + +/*! + * @name Defines for snvs_btn_press_time_t + * + * Used to configure the button press time out values for the PMIC logic. + * + * BTN_PRESS_TIME field in the SNVS_LP regsiter. See the SNVS section + * of the SRM. + */ +/** @{ */ +#define SNVS_DRV_BTN_PRESS_5S 0U /*!< 5 secs */ +#define SNVS_DRV_BTN_PRESS_10S 1U /*!< 10 secs */ +#define SNVS_DRV_BTN_PRESS_15S 2U /*!< 15 secs */ +#define SNVS_DRV_BTN_PRESS_OFF 3U /*!< Long press disabled */ +/** @} */ + +/* Types */ + +/*! + * This type is used configure the button active state. + */ +typedef uint8_t snvs_btn_config_t; + +/*! + * This type is used configure the button on time. + */ +typedef uint8_t snvs_btn_on_time_t; + +/*! + * This type is used configure the button debounce time. + */ +typedef uint8_t snvs_btn_debounce_t; + +/*! + * This type is used configure the button press time. + */ +typedef uint8_t snvs_btn_press_time_t; + +/* SNVS Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +/*! + * @brief Initialize SNVS driver. + * + * This function initializes the SNVS driver. + * + * @param phase init phase + */ +void SNVS_Init(boot_phase_t phase); + +/** @} */ + +/*! + * @name SRTC Functions + * @{ + */ + +/*! + * @brief Power off system. + * + * This function asserts the signal to the PMIC to force a power off. + */ +void SNVS_PowerOff(void); + +/*! + * @brief Set the secure RTC. + * + * This function sets the secure RTC. + * + * @param seconds time to set + */ +void SNVS_SetSecureRtc(uint32_t seconds); + +/*! + * @brief Get the secure RTC. + * + * This function returns the secure RTC time. + * + * @param seconds pointer to return seconds + */ +void SNVS_GetSecureRtc(uint32_t *seconds); + +/*! + * @brief Set the secure RTC calibration value. + * + * This function sets the secure RTC calibration value. + * See the SNVS section of the SRM for more info. + * + * @param count counts to add/subtract per 32768 ticks + */ +void SNVS_SetSecureRtcCalb(int8_t count); + +/*! + * @brief Get the secure RTC calibration value. + * + * This function returns the secure RTC calibration value. + * See the SNVS section of the SRM for more info. + * + * @param count pointer to return count + */ +void SNVS_GetSecureRtcCalb(int8_t *count); + +/*! + * @brief Set secure RTC alarm. + * + * This function sets the secure RTC alarm and enables it. + * + * @param seconds alarm to set + * + * If seconds=UINT32_MAX then disable alarm. + */ +void SNVS_SetSecureRtcAlarm(uint32_t seconds); + +/*! + * @brief Get secure RTC alarm. + * + * This function returns the secure RTC alarm. + * + * @param seconds pointer to return alarm + */ +void SNVS_GetSecureRtcAlarm(uint32_t *seconds); + +/*! + * @brief Set the RTC. + * + * This function sets the RTC. + * + * @param seconds time to set + */ +void SNVS_SetRtc(uint32_t seconds); + +/*! + * @brief Get the RTC. + * + * This function returns the RTC time. + * + * @param seconds pointer to return seconds + */ +void SNVS_GetRtc(uint32_t *seconds); + +/*! + * @brief Set the RTC calibration value. + * + * This function sets the RTC calibration value. + * See the SNVS section of the SRM for more info. + * + * @param count counts to add/subtract per 32768 ticks + */ +void SNVS_SetRtcCalb(int8_t count); + +/*! + * @brief Set RTC alarm. + * + * This function sets the RTC alarm and enables it. + * + * @param seconds alarm to set + * + * If seconds=UINT32_MAX then disable alarm. + */ +void SNVS_SetRtcAlarm(uint32_t seconds); + +/*! + * @brief Get RTC alarm. + * + * This function returns the RTC alarm. + * + * @param seconds pointer to return alarm + */ +void SNVS_GetRtcAlarm(uint32_t *seconds); + +/*! + * @brief Configure the ON/OFF button. + * + * This function configures the button detection and IRQ. + * See the SNVS section of the SRM for more info. + * + * @param config button configuration (see BTN_CONFIG in SRM) + * @param enable button IRQ enable (see BTN_MASK in SRM) + * + * For info on the arguments, see the SNVS section of the SRM. + */ +void SNVS_ConfigButton(snvs_btn_config_t config, sc_bool_t enable); + +/*! + * @brief Configure the ON/OFF button timing parameters. + * + * This function configures the button timing parameters. + * See the SNVS section of the SRM for more info. + * + * @param on button turn on time (see ON_TIME in SRM) + * @param debounce button debounce time (see DEBOUNCE in SRM) + * @param press button turn off time (see BTN_PRESS_TIME in SRM) + * + * For info on the arguments, see the SNVS section of the SRM. + */ +void SNVS_ButtonTime(snvs_btn_on_time_t on, snvs_btn_debounce_t debounce, + snvs_btn_press_time_t press); + +/*! + * @brief Get button status. + * + * This function returns the status of the button. + * See the SNVS section of the SRM for more info. BTN in HPSR. + * + * @return Returns the button status. + */ +sc_bool_t SNVS_GetButtonStatus(void); + +/*! + * @brief Clear button IRQ. + * + * This function clears a pending button IRQ. + */ +void SNVS_ClearButtonIRQ(void); + +/*! + * @brief Enter low power mode. + * + * This function prepares the SNVS for low power mode. It copies various data + * from the HP section to the LP section. + */ +void SNVS_EnterLPM(void); + +/*! + * @brief Exit low power mode. + * + * This function restores SNVS data from the LP section to the HP section. + */ +void SNVS_ExitLPM(void); + +/*! + * @brief Get the SNVS System Security Monitor State (SSM). + * + * This function returns the System Security Monitor State (SSM). + * See the SNVS section of the SRM for more info. SSM_ST in HPSR. + * + * @return Returns the state of the monitor. + */ +uint32_t SNVS_GetState(void); + +/*! + * @brief Enable SNVS Security Violation Interrupt. + * + * This function is used to re-enable the security violation interrupt. The + * interrupt is automatically masked when the interrupt occurs. + */ +void SNVS_SecurityViolation_Enable(void); + +/*! + * @brief SNVS security violation IRQ handler. + * + * This function is called when the security violation IRQ is asserted. It + * automatically masks the security violation interrupt which must then be + * re-enabled using SNVS_SecurityViolation_Enable(). + */ +void SNVS_SecurityViolation_IRQHandler(void); + +/*! + * @brief SNVS power off IRQ handler. + * + * This function is called when the power off IRQ is asserted. + */ +void SNVS_PowerOff_IRQHandler(void); + +/*! + * @brief Read a GP register. + * + * This function is called to read one of the four LPGPR[0-3]. Note that + * SECO and SCFW may use some of these so only a limited number may be available + * for cusotmer use. See the [Porting Guide](@ref PORT_SNVS). + * + * @param idx index of register to read (0-3) + * + * @return Returns the stored value. + */ +uint32_t SNVS_ReadGP(uint8_t idx); + +/*! + * @brief Write a GP register. + * + * @param idx index of register to write (0-3) + * @param val value to write + * + * This function is called write to one of the four LPGPR[0-3]. Note that + * SECO and SCFW may use some of these so only a limited number may be available + * for cusotmer use. See the [Porting Guide](@ref PORT_SNVS). + */ +void SNVS_WriteGP(uint8_t idx, uint32_t val); + +/*! + * @brief Manage security violation and tamper. + * + * @param id index of register(s) to access + * @param access read or write + * @param data0 value 0 to read or write + * @param data1 value 1 to read or write + * @param data2 value 2 to read or write + * @param data3 value 3 to read or write + * @param data4 value 4 to read or write + * @param size number of value to access + * + * Set dataX to NULL if not used. + * + * This function is called to read/write security violation and + * tamper registers. See the SECO API Reference Guide for more info. + */ +void SNVS_SecVio(uint8_t id, uint8_t access, uint32_t *data0, + uint32_t *data1, uint32_t *data2, uint32_t *data3, uint32_t *data4, + uint8_t size); + +/*! + * @brief Manage security violation and tamper of DGO. + * + * @param id index of register to access + * @param access read or write + * @param data value to read or write + * + * This function is called to read/write security violation and + * tamper DGO registers. See the SECO API Reference Guide for more info. + */ +void SNVS_SecVioDgo(uint8_t id, uint8_t access, uint32_t *data); + +#ifdef SIMU +/*! + * @brief Simulation function to increment time. + * + * @param secs seconds to increment + */ +void SNVS_IncTime(uint32_t secs); +#endif + +/* Externs */ + +/*! SNVS error return */ +extern sc_err_t snvs_err; + +/** @} */ + +#endif /* DRV_SNVS_H */ + +/** @} */ + diff --git a/platform/drivers/snvs/v2/Makefile b/platform/drivers/snvs/v2/Makefile new file mode 100755 index 0000000..3735cae --- /dev/null +++ b/platform/drivers/snvs/v2/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/snvs/v2/fsl_snvs.o + +DIRS += $(OUT)/drivers/snvs/v2 + diff --git a/platform/drivers/stc/Makefile b/platform/drivers/stc/Makefile new file mode 100755 index 0000000..c20428a --- /dev/null +++ b/platform/drivers/stc/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/stc/fsl_stc.o + +DIRS += $(OUT)/drivers/stc + diff --git a/platform/drivers/stc/fsl_stc.h b/platform/drivers/stc/fsl_stc.h new file mode 100755 index 0000000..a9b0f3d --- /dev/null +++ b/platform/drivers/stc/fsl_stc.h @@ -0,0 +1,121 @@ +/* + * Copyright 2017-2019 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef FSL_STC_H +#define FSL_STC_H + +#include "fsl_common.h" + +/*! + * @addtogroup stc_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/** @{ */ +/*! @brief STC driver version 2.2.1. */ +#define FSL_STC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/** @} */ + +/*! @brief STC interleave mode. */ +typedef enum +{ + kSTC_Interleave4K = 0x0U, /*!< 4K interleave */ + kSTC_Interleave8K = 0x1U, /*!< 8K interleave */ + kSTC_Interleave16K = 0x2U, /*!< 16K interleave */ + kSTC_InterleaveNone = 0x3U, /*!< No interleave */ +} stc_interleave_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Set STC interleave. + */ +void STC_RIL_SetInterleave(STC_Type *base, stc_interleave_mode_t interleave); + +/*! + * @brief Set STC RCAT. + */ +void STC_RCAT_SetCategorization(STC_Type *base, uint8_t cat, uint32_t mask, + uint32_t compare); + +/*! + * @brief Set STC RCAT. + */ +void STC_RCAT_SetStartStopTDM(STC_Type *base, uint8_t cat, uint8_t tdm, + uint32_t start, uint32_t stop); + +/*! + * @brief Set STC RCAT. + */ +uint32_t STC_RCAT_GetHPR(const STC_Type *base, uint8_t cat); + +/*! + * @brief Set STC RCAT. + */ +void STC_RCAT_SetHPR(STC_Type *base, uint8_t cat, uint8_t hpr_qos_offset); + +/*! + * @brief Set STC panic QOS. + */ +void STC_QOS_Panic(STC_Type *base, uint8_t cat, uint8_t qos); + +/*! + * @brief Set STC UD disable. + */ +void STC_UD_DisableAll(STC_Type *base); + +/*! + * @brief Set STC UD enable threshold 1. + */ +void STC_UD_EnableThreshold1(STC_Type *base, uint8_t cat, uint8_t threshold, uint8_t qos); + +/*! + * @brief Set STC UD enable threshold 2. + */ +void STC_UD_EnableThreshold2(STC_Type *base, uint8_t cat, uint8_t threshold, uint8_t qos); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_STC_H */ diff --git a/platform/drivers/sysctr/Makefile b/platform/drivers/sysctr/Makefile new file mode 100755 index 0000000..d3e4d0a --- /dev/null +++ b/platform/drivers/sysctr/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/sysctr/fsl_sysctr.o + +DIRS += $(OUT)/drivers/sysctr + diff --git a/platform/drivers/sysctr/fsl_sysctr.h b/platform/drivers/sysctr/fsl_sysctr.h new file mode 100755 index 0000000..ab661f1 --- /dev/null +++ b/platform/drivers/sysctr/fsl_sysctr.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_SYSCTR_H +#define DRV_SYSCTR_H + +/*! + * @addtogroup sysctr_driver + * @{ + */ + +/*! @file */ + +/* Includes */ +#include "fsl_device_registers.h" + +/* Defines */ +#define SYSCTR_CNTCV_MARGIN 50U + +/* SYSCTR counts at a rate of 8 MHz (125 nsec period). Conversions + to/from usec can be calculated using a shift: + + 1 tick = 1/8 usec --> ticks >> 3 = usec + 1 usec = 8 ticks --> usec << 3 = ticks +*/ +#define SYSCTR_TICKS_TO_USEC(ticks) ((ticks) >> 3U) +#define SYSCTR_USEC_TO_TICKS(usec) ((usec) << 3U) +#define SYSCTR_TICKS_TO_USEC64(ticks) (U64(ticks) >> 3ULL) +#define SYSCTR_USEC_TO_TICKS64(usec) (U64(usec) << 3ULL) + +/* Types */ + +/* Externs */ + +/* Functions */ + +/*! + * @name System Counter Functions + * @{ + */ + +/*! + * This function initializes and enables the system counter. + */ +void SYSCTR_Init(void); + +/*! + * This function returns the system counter value as a 64-bit clock + * cycle count. + * + * @return Returns the system counter value. + */ +uint64_t SYSCTR_GetCounter64(void); + +/*! + * This function returns the system counter value as a 32-bit clock + * cycle count. + * + * @return Returns the system counter value. + */ +uint32_t SYSCTR_GetCounter32(void); + +/*! + * This function returns the system counter time in uS. The return + * value is 64 bits. + * + * @return Returns the system counter value in uS. + */ +uint64_t SYSCTR_GetUsec64(void); + +/*! + * This function returns the system counter time in uS. The return + * value is 32 bits. + * + * @return Returns the system counter value in uS. + */ +uint32_t SYSCTR_GetUsec32(void); + +/*! + * This function delays the indicated number of uS. + * + * @param[in] usec number of microseconds to delay + */ +void SYSCTR_TimeDelay(uint32_t usec); + +/*! + * This function configures the frequency mode of the system + * counter. The system counter supports high-frequency (8 MHz) + * and low-frequency (32768 Hz) modes with a variable + * increment to maintain an effective 8 MHz counting rate. + * + * @param[in] bLowFreq flag to indicate low-frequency mode (SC_TRUE = low-frequency operation) + * @param[in] bWaitAck flag to wait for mode change (SC_TRUE = wait for mode change) + */ +void SYSCTR_FreqMode(sc_bool_t bLowFreq, sc_bool_t bWaitAck); + +/*! + * This function waits for a pending frequency mode change + * of the system counter. + * + * @param[in] bLowFreq flag to indicate low-frequency mode (SC_TRUE = low-frequency operation) + */ +void SYSCTR_FreqModeWaitAck(sc_bool_t bLowFreq); + +/*! + * This function configures the system counter compare frame0 + * to generate an IRQ (wake) event after the specified number of + * microseconds. + * + * @param[in] usec number of microseconds until wake event + */ +void SYSCTR_WakeEnable(uint32_t usec); + +/*! + * This function configures the system counter compare frame1 + * to generate an IRQ event after the specified number of + * system counter ticks. + * + * @param[in] usec number of system counter ticks until the event + */ +void SYSCTR_Compare1Enable(uint64_t ticks); + +/*! + * This function clears and disables the system counter compare frame1 + * IRQ event. + */ +void SYSCTR_Compare1Disable(void); + +/** @} */ + +#endif /* DRV_SYSCTR_H */ + +/** @} */ + diff --git a/platform/drivers/systick/Makefile b/platform/drivers/systick/Makefile new file mode 100755 index 0000000..225496d --- /dev/null +++ b/platform/drivers/systick/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/systick/fsl_systick.o + +DIRS += $(OUT)/drivers/systick + diff --git a/platform/drivers/systick/fsl_systick.h b/platform/drivers/systick/fsl_systick.h new file mode 100755 index 0000000..15db5a6 --- /dev/null +++ b/platform/drivers/systick/fsl_systick.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_SYSTICK_H +#define DRV_SYSTICK_H + +/*! + * @addtogroup systick_driver + * @{ + */ + +/*! @file */ + +/* Includes */ +#include "fsl_device_registers.h" +#include "fsl_clock.h" + +/* Defines */ +#define SYSTICK_TICKS_PER_USEC (SC_MCU_STARTUP_FREQ_MHZ) +#define SYSTICK_MAX_TICKS (SysTick_VAL_CURRENT_Msk) +#define SYSTICK_MAX_DELAY_USEC (50U*1000U) // 50 msec + +#if ((SYSTICK_MAX_DELAY_USEC*SYSTICK_TICKS_PER_USEC) > SYSTICK_MAX_TICKS) +#error "SYSTICK_MAX_DELAY_USEC exceeds SYSTICK_MAX_TICKS" +#endif + + +/* Types */ + + +/* Externs */ + + +/* Functions */ + + +/*! + * @name System Timer (SysTick) Functions + * @{ + */ + +void SYSTICK_Init(void); +void SYSTICK_CycleDelay(uint32_t cycles); +void SYSTICK_TimeDelay(uint32_t usec); +void SYSTICK_TimeDelayVar(uint32_t usec, uint32_t ticksPerUsec); +uint32_t SYSTICK_GetCounter32(void); +uint32_t SYSTICK_TickDiff32(uint32_t cntStart, uint32_t cntEnd); +uint32_t SYSTICK_NsecDiff(uint32_t cntStart, uint32_t cntEnd, uint32_t tickPsec); + + +/** @} */ + + +#endif /* DRV_SYSTICK_H */ + +/** @} */ + diff --git a/platform/drivers/v2x/Makefile b/platform/drivers/v2x/Makefile new file mode 100755 index 0000000..68a0737 --- /dev/null +++ b/platform/drivers/v2x/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/v2x/fsl_v2x.o + +DIRS += $(OUT)/drivers/v2x + diff --git a/platform/drivers/v2x/fsl_v2x.h b/platform/drivers/v2x/fsl_v2x.h new file mode 100755 index 0000000..0de8e33 --- /dev/null +++ b/platform/drivers/v2x/fsl_v2x.h @@ -0,0 +1,137 @@ +/* + * Copyright 2019-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_V2X_H +#define DRV_V2X_H + +/*! + * @addtogroup v2x_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +/*! + * @name Macros for version parsing + */ +/** @{ */ +#define V2X_PROD_VER(X) (((X) >> 16) & 0x7FFFUL) +#define V2X_MAJOR_VER(X) (((X) >> 4) & 0xFFFUL) +#define V2X_MINOR_VER(X) ((X) & 0xFUL) +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +/*! + * This function initializes the V2X driver. + * + * Called when DB is powered up. + */ +void V2X_Init(void); + +/*! + * This function deinitializes the V2X driver. + * + * Called before DB is powered down. + */ +void V2X_Deinit(void); + +/** @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used to return the V2X FW build info. + * + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + * @param[out] dirty pointer to return dirty flag + * + * See the SECO API Reference Guide for more info. + */ +void V2X_Version(uint32_t *version, uint32_t *commit, sc_bool_t *dirty); + +/*! + * This function dumps low-level V2X debug info to the SCU debug + * UART. + * + * @param[in] mask bit(0): logs from V2X primary core / bit(1): logs from secondary core + */ +void V2X_DumpDebug(uint32_t log_bitmap); +#define LOG_BITMAP_V2XP 0x1 +#define LOG_BITMAP_V2XS 0x2 + +/** @} */ + +/*! + * @name Miscellaneous Functions + * @{ + */ + +/*! + * This function sends a ping to V2X. + * + * See the V2X API Reference Guide for more info. + */ +void V2X_Ping(void); + +/*! + * @brief V2X MU IRQ handler. + * + * This function is called when the V2X SCU/DEBUG MU asserts an interrupt. + */ +void V2X_MU_IRQHandler(void); + +/** @} */ + +/* Externs */ + +/*! V2X error return */ +extern sc_err_t v2x_err; + +#endif /* DRV_V2X_H */ + +/** @} */ + diff --git a/platform/drivers/wdog32/Makefile b/platform/drivers/wdog32/Makefile new file mode 100755 index 0000000..59e6249 --- /dev/null +++ b/platform/drivers/wdog32/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/wdog32/fsl_wdog32.o + +DIRS += $(OUT)/drivers/wdog32 + diff --git a/platform/drivers/wdog32/fsl_wdog32.h b/platform/drivers/wdog32/fsl_wdog32.h new file mode 100755 index 0000000..1e385a7 --- /dev/null +++ b/platform/drivers/wdog32/fsl_wdog32.h @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_WDOG32_H_ +#define _FSL_WDOG32_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog32 + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Unlock sequence */ +/** @{ */ +#define WDOG_FIRST_WORD_OF_UNLOCK (WDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK ((WDOG_UPDATE_KEY >> 16U) & 0xFFFFU) /*!< Second word of unlock sequence */ +/** @} */ + +/*! @name Refresh sequence */ +/** @{ */ +#define WDOG_FIRST_WORD_OF_REFRESH (WDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH ((WDOG_REFRESH_KEY >> 16U) & 0xFFFFU) /*!< Second word of refresh sequence */ +/** @} */ +/*! @name Driver version */ +/** @{ */ +/*! @brief WDOG32 driver version. */ +#define FSL_WDOG32_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/** @} */ + +/*! @brief Describes WDOG32 clock source. */ +typedef enum _wdog32_clock_source +{ + kWDOG32_ClockSource0 = 0U, /*!< Clock source 0 */ + kWDOG32_ClockSource1 = 1U, /*!< Clock source 1 */ + kWDOG32_ClockSource2 = 2U, /*!< Clock source 2 */ + kWDOG32_ClockSource3 = 3U, /*!< Clock source 3 */ +} wdog32_clock_source_t; + +/*! @brief Describes the selection of the clock prescaler. */ +typedef enum _wdog32_clock_prescaler +{ + kWDOG32_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kWDOG32_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */ +} wdog32_clock_prescaler_t; + +/*! @brief Defines WDOG32 work mode. */ +typedef struct _wdog32_work_mode +{ + bool enableWait; /*!< Enables or disables WDOG32 in wait mode */ + bool enableStop; /*!< Enables or disables WDOG32 in stop mode */ + bool enableDebug; /*!< Enables or disables WDOG32 in debug mode */ +} wdog32_work_mode_t; + +/*! @brief Describes WDOG32 test mode. */ +typedef enum _wdog32_test_mode +{ + kWDOG32_TestModeDisabled = 0U, /*!< Test Mode disabled */ + kWDOG32_UserModeEnabled = 1U, /*!< User Mode enabled */ + kWDOG32_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ + kWDOG32_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ +} wdog32_test_mode_t; + +/*! @brief Describes WDOG32 configuration structure. */ +typedef struct _wdog32_config +{ + bool enableWdog32; /*!< Enables or disables WDOG32 */ + wdog32_clock_source_t clockSource; /*!< Clock source select */ + wdog32_clock_prescaler_t prescaler; /*!< Clock prescaler value */ + wdog32_work_mode_t workMode; /*!< Configures WDOG32 work mode in debug stop and wait mode */ + wdog32_test_mode_t testMode; /*!< Configures WDOG32 test mode */ + bool enableUpdate; /*!< Update write-once register enable */ + bool enableInterrupt; /*!< Enables or disables WDOG32 interrupt */ + bool enableWindowMode; /*!< Enables or disables WDOG32 window mode */ + uint16_t windowValue; /*!< Window value */ + uint16_t timeoutValue; /*!< Timeout value */ +} wdog32_config_t; + +/*! + * @brief WDOG32 interrupt configuration structure. + * + * This structure contains the settings for all of the WDOG32 interrupt configurations. + */ +enum _wdog32_interrupt_enable_t +{ + kWDOG32_InterruptEnable = WDOG_CS_INT_MASK, /*!< Interrupt is generated before forcing a reset */ +}; + +/*! + * @brief WDOG32 status flags. + * + * This structure contains the WDOG32 status flags for use in the WDOG32 functions. + */ +enum _wdog32_status_flags_t +{ + kWDOG32_RunningFlag = WDOG_CS_EN_MASK, /*!< Running flag, set when WDOG32 is enabled */ + kWDOG32_InterruptFlag = WDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG32 Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the WDOG32 configuration structure. + * + * This function initializes the WDOG32 configuration structure to default values. The default + * values are: + * @code + * wdog32Config->enableWdog32 = true; + * wdog32Config->clockSource = kWDOG32_ClockSource1; + * wdog32Config->prescaler = kWDOG32_ClockPrescalerDivide1; + * wdog32Config->workMode.enableWait = true; + * wdog32Config->workMode.enableStop = false; + * wdog32Config->workMode.enableDebug = false; + * wdog32Config->testMode = kWDOG32_TestModeDisabled; + * wdog32Config->enableUpdate = true; + * wdog32Config->enableInterrupt = false; + * wdog32Config->enableWindowMode = false; + * wdog32Config->windowValue = 0U; + * wdog32Config->timeoutValue = 0xFFFFU; + * @endcode + * + * @param config Pointer to the WDOG32 configuration structure. + * @see wdog32_config_t + */ +void WDOG32_GetDefaultConfig(wdog32_config_t *config); + +/*! + * @brief Initializes the WDOG32 module. + * + * This function initializes the WDOG32. + * To reconfigure the WDOG32 without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * Example: + * @code + * wdog32_config_t config; + * WDOG32_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * WDOG32_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG32 peripheral base address. + * @param config The configuration of the WDOG32. + */ +#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT +void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config); +#else +AT_QUICKACCESS_SECTION_CODE(void WDOG32_Init(WDOG_Type *base, const wdog32_config_t *config)); +#endif + +/*! + * @brief De-initializes the WDOG32 module. + * + * This function shuts down the WDOG32. + * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. + * + * @param base WDOG32 peripheral base address. + */ +void WDOG32_Deinit(WDOG_Type *base); + +/** @} */ + +/*! + * @name WDOG32 functional Operation + * @{ + */ + +/*! + * @brief Enables the WDOG32 module. + * + * This function writes a value into the WDOG_CS register to enable the WDOG32. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base WDOG32 peripheral base address. + */ +static inline void WDOG32_Enable(WDOG_Type *base) +{ + base->CS |= WDOG_CS_EN_MASK; +} + +/*! + * @brief Disables the WDOG32 module. + * + * This function writes a value into the WDOG_CS register to disable the WDOG32. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base WDOG32 peripheral base address + */ +static inline void WDOG32_Disable(WDOG_Type *base) +{ + base->CS &= ~WDOG_CS_EN_MASK; +} + +/*! + * @brief Enables the WDOG32 interrupt. + * + * This function writes a value into the WDOG_CS register to enable the WDOG32 interrupt. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base WDOG32 peripheral base address. + * @param mask The interrupts to enable. + * The parameter can be a combination of the following source if defined: + * @arg kWDOG32_InterruptEnable + */ +static inline void WDOG32_EnableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->CS |= mask; +} + +/*! + * @brief Disables the WDOG32 interrupt. + * + * This function writes a value into the WDOG_CS register to disable the WDOG32 interrupt. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base WDOG32 peripheral base address. + * @param mask The interrupts to disabled. + * The parameter can be a combination of the following source if defined: + * @arg kWDOG32_InterruptEnable + */ +static inline void WDOG32_DisableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->CS &= ~mask; +} + +/*! + * @brief Gets the WDOG32 all status flags. + * + * This function gets all status flags. + * + * Example to get the running flag: + * @code + * uint32_t status; + * status = WDOG32_GetStatusFlags(wdog_base) & kWDOG32_RunningFlag; + * @endcode + * @param base WDOG32 peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false). @see _wdog32_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +static inline uint32_t WDOG32_GetStatusFlags(WDOG_Type *base) +{ + return (base->CS & (WDOG_CS_EN_MASK | WDOG_CS_FLG_MASK)); +} + +/*! + * @brief Clears the WDOG32 flag. + * + * This function clears the WDOG32 status flag. + * + * Example to clear an interrupt flag: + * @code + * WDOG32_ClearStatusFlags(wdog_base,kWDOG32_InterruptFlag); + * @endcode + * @param base WDOG32 peripheral base address. + * @param mask The status flags to clear. + * The parameter can be any combination of the following values: + * @arg kWDOG32_InterruptFlag + */ + +#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT +void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask); +#else +AT_QUICKACCESS_SECTION_CODE(void WDOG32_ClearStatusFlags(WDOG_Type *base, uint32_t mask)); +#endif + +/*! + * @brief Sets the WDOG32 timeout value. + * + * This function writes a timeout value into the WDOG_TOVAL register. + * The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base WDOG32 peripheral base address + * @param timeoutCount WDOG32 timeout value, count of WDOG32 clock ticks. + */ +static inline void WDOG32_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->TOVAL = timeoutCount; +} + +/*! + * @brief Sets the WDOG32 window value. + * + * This function writes a window value into the WDOG_WIN register. + * The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base WDOG32 peripheral base address. + * @param windowValue WDOG32 window value. + */ +static inline void WDOG32_SetWindowValue(WDOG_Type *base, uint16_t windowValue) +{ + base->WIN = windowValue; +} + +/*! + * @brief Unlocks the WDOG32 register written. + * + * This function unlocks the WDOG32 register written. + * + * Before starting the unlock sequence and following the configuration, disable the global interrupts. + * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. + * After the configuration finishes, re-enable the global interrupts. + * + * @param base WDOG32 peripheral base address + */ +static inline void WDOG32_Unlock(WDOG_Type *base) +{ + if (0U != ((base->CS) & WDOG_CS_CMD32EN_MASK)) + { + base->CNT = WDOG_UPDATE_KEY; + } + else + { + base->CNT = WDOG_FIRST_WORD_OF_UNLOCK; + base->CNT = WDOG_SECOND_WORD_OF_UNLOCK; + } +#ifdef WDOG_CS_ULK_MASK + /* Waited until for registers to be unlocked. */ + while (0U == ((base->CS) & WDOG_CS_ULK_MASK)) + { + ; + } +#endif /* WDOG_CS_ULK_MASK */ +} + +/*! + * @brief Refreshes the WDOG32 timer. + * + * This function feeds the WDOG32. + * This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG32 peripheral base address + */ +static inline void WDOG32_Refresh(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + if (0U != ((base->CS) & WDOG_CS_CMD32EN_MASK)) + { + base->CNT = WDOG_REFRESH_KEY; + } + else + { + base->CNT = WDOG_FIRST_WORD_OF_REFRESH; + base->CNT = WDOG_SECOND_WORD_OF_REFRESH; + } + EnableGlobalIRQ(primaskValue); +} + +/*! + * @brief Gets the WDOG32 counter value. + * + * This function gets the WDOG32 counter value. + * + * @param base WDOG32 peripheral base address. + * @return Current WDOG32 counter value. + */ +static inline uint16_t WDOG32_GetCounterValue(WDOG_Type *base) +{ + return (uint16_t)base->CNT; +} + +/** @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG32_H_ */ diff --git a/platform/drivers/xrdc2/Makefile b/platform/drivers/xrdc2/Makefile new file mode 100755 index 0000000..a89e9d5 --- /dev/null +++ b/platform/drivers/xrdc2/Makefile @@ -0,0 +1,5 @@ + +OBJS += $(OUT)/drivers/xrdc2/fsl_xrdc2.o + +DIRS += $(OUT)/drivers/xrdc2 + diff --git a/platform/drivers/xrdc2/fsl_xrdc2.h b/platform/drivers/xrdc2/fsl_xrdc2.h new file mode 100755 index 0000000..dfc878e --- /dev/null +++ b/platform/drivers/xrdc2/fsl_xrdc2.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017-2020 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DRV_XRDC2_H +#define DRV_XRDC2_H + +/*! + * @addtogroup xrdc2_driver + * @{ + */ + +/*! @file */ + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +#ifndef DEBUG + #define XRDC_PAC_CHECK(X, Y) NOP +#else + #define XRDC_PAC_CHECK(X, Y) XRDC_PacCheck((X), (Y)) +#endif + +#define XRDC_BASE_ADDR(X) ((XRDC2_Type*) (((sc_saddr_t) DSC_BASE_ADDR(X)) \ + + 0x10000U)) + +#define XRDC_MAX_DOMAINS 16U + +#define XRDC_MAX_PAC 8U +#define XRDC_MAX_PAC_SLOTS 256U +#define XRDC_MAX_MSC 128U +#define XRDC_MAX_MDAC 32U +#define XRDC_MAX_MDAC_SLOTS 32U +#define XRDC_MAX_MRC 32U +#define XRDC_MAX_MRC_SLOTS 32U + +#define XRDC_IDX_W 16U +#define XRDC_DID_W 4U +#define XRDC_SID_W 16U +#define XRDC_MATCH_W 16U +#define XRDC_DET_W 1U +#define XRDC_RMSG_W 4U +#define XRDC_NUM_W 8U + +/* Types */ + +typedef uint8_t xrdc_info_t; +typedef uint16_t xrdc_idx_t; +typedef uint8_t xrdc_did_t; +typedef uint16_t xrdc_match_t; +typedef uint8_t xrdc_det_t; +typedef uint8_t xrdc_rmsg_t; +typedef uint8_t xrdc_perm_t; + +/*! + * This type is used to store a XRDC SID value. + */ +typedef union +{ + uint16_t U; + struct + { + uint16_t SID : 6; + uint16_t CID : 4; + uint16_t RESERVED0 : 6; + } B; +} xrdc_sid_t; + +/*! + * This type is used to store info about a PAC. + */ +typedef struct +{ + uint32_t slot_en[XRDC_MAX_PAC_SLOTS/32]; //!< Slot enables + dsc_pdom_t pd : DSC_PDOM_W; //!< Power domain + sc_bool_t present : SC_BOOL_W; //!< Present +} xrdc_pac_info_t; + +/* XRDC Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +void XRDC_Init(sc_dsc_t dsc); +sc_bool_t XRDC_Config(sc_dsc_t dsc, sc_bool_t mst_enable, + sc_bool_t chk_enable); +void XRDC_GetConfig(sc_dsc_t dsc, sc_bool_t *mst_enable, + sc_bool_t *chk_enable); +void XRDC_Status(sc_dsc_t dsc, xrdc_did_t *did, xrdc_info_t *hrl, + xrdc_info_t *gclo); + +/** @} */ + +/*! + * @name MSC Functions + * @{ + */ + +void XRDC_GetMsc(sc_dsc_t dsc, xrdc_idx_t idx, sc_bool_t *valid, + sc_bool_t *lock, xrdc_perm_t *perms); +void XRDC_SetMsc(sc_dsc_t dsc, xrdc_idx_t idx, sc_bool_t valid, sc_bool_t lock, + const xrdc_perm_t *perms); +void XRDC_SetMultiMsc(sc_dsc_t dsc, xrdc_idx_t start, xrdc_idx_t num, + sc_bool_t valid, sc_bool_t lock, const xrdc_perm_t *perms); + +/** @} */ + +/*! + * @name MDAC Functions + * @{ + */ + +void XRDC_GetMda(sc_dsc_t dsc, xrdc_idx_t idx, sc_bool_t *valid, sc_bool_t *lock, + sc_rm_spa_t *sa, sc_rm_spa_t *pa, xrdc_did_t *did, xrdc_sid_t *sid, + xrdc_match_t *match, xrdc_match_t *mask, sc_bool_t has_match, + const uint32_t *cache); +void XRDC_SetMda(sc_dsc_t dsc, xrdc_idx_t idx, sc_bool_t valid, sc_bool_t lock, + sc_rm_spa_t sa, sc_rm_spa_t pa, xrdc_did_t did, xrdc_sid_t sid, + xrdc_match_t match, xrdc_match_t mask, sc_bool_t has_match, + uint32_t *cache); + +/** @} */ + +/*! + * @name PAC Functions + * @{ + */ + +void XRDC_GetPdac(sc_dsc_t dsc, xrdc_idx_t idx, sc_bool_t *valid, + sc_bool_t *lock, xrdc_perm_t *perms); +void XRDC_SetPdac(sc_dsc_t dsc, xrdc_idx_t idx, sc_bool_t valid, + sc_bool_t lock, const xrdc_perm_t *perms, sc_bool_t no_update); +void XRDC_SetMultiPdac(sc_dsc_t dsc, xrdc_idx_t start, xrdc_idx_t num, + sc_bool_t valid, sc_bool_t lock, const xrdc_perm_t *perms, + sc_bool_t no_update); + +/** @} */ + +/*! + * @name MRC Functions + * @{ + */ + +void XRDC_GetMrc(sc_dsc_t dsc, xrdc_idx_t idx, sc_faddr_t *start, + sc_faddr_t *end, sc_bool_t *valid, sc_bool_t *lock, xrdc_perm_t *perms, + xrdc_det_t *det, xrdc_rmsg_t *rmsg, const uint32_t *cache); +void XRDC_SetMrc(sc_dsc_t dsc, xrdc_idx_t idx, sc_faddr_t start, + sc_faddr_t end, sc_bool_t valid, sc_bool_t lock, const xrdc_perm_t *perms, + xrdc_det_t det, xrdc_rmsg_t rmsg, uint32_t *cache); +void XRDC_InvalidateMrc(sc_dsc_t dsc, xrdc_idx_t idx, + xrdc_idx_t regions, uint32_t *cache); +sc_bool_t XRDC_FindMrc(sc_dsc_t dsc, xrdc_idx_t *idx, sc_faddr_t start, + sc_faddr_t end, xrdc_idx_t regions, uint32_t *cache); +sc_bool_t XRDC_UnusedMrc(sc_dsc_t dsc, xrdc_idx_t *idx, + xrdc_idx_t regions, uint32_t *cache); + +/** @} */ + +/*! + * @name Debug Functions + * @{ + */ + +#ifdef DEBUG +void XRDC_PacCheck(xrdc_idx_t num, const xrdc_pac_info_t *info); +#endif + +/** @} */ + +#endif /* DRV_XRDC2_H */ + +/** @} */ + diff --git a/platform/main/Makefile b/platform/main/Makefile new file mode 100755 index 0000000..99e841d --- /dev/null +++ b/platform/main/Makefile @@ -0,0 +1,30 @@ + +objs_main := main.o main_common.o boot.o + +ifeq ($(HW), SIMU) + objs_main += main_simu.o +endif + +ifndef NO_IPC + objs_main += rpc.o ipc_srv.o + + ifeq ($(HW), REAL) + objs_main += ipc.o + else + objs_main += ipc_simu.o + endif +endif + +ifeq ($(M),1) + objs_main += monitor.o +endif + +ifeq ($(EM),1) + objs_main += monitor.o +endif + +OBJS += \ + $(foreach object,$(objs_main),$(OUT)/main/$(object)) + +DIRS += $(OUT)/main + diff --git a/platform/main/board.h b/platform/main/board.h new file mode 100755 index 0000000..a1b9d82 --- /dev/null +++ b/platform/main/board.h @@ -0,0 +1,743 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the board API. + * + * @addtogroup BRD_SVC BRD: Board Interface + * + * Module for the Board interface. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_BOARD_API_H +#define SC_BOARD_API_H + +/* Defines */ + +#define BOARD_PARM_RTN_NOT_USED 0U /*!< Feature not used */ +#define BOARD_PARM_RTN_USED 1U /*!< Feature used */ + +#define BOARD_PARM_RTN_EXTERNAL 2U /*!< Return value for BOARD_PARM_PCIE_PLL */ +#define BOARD_PARM_RTN_INTERNAL 3U /*!< Return value for BOARD_PARM_PCIE_PLL */ +#define BOARD_PARM_RTN_INTERNAL_DPLL 4U /*!< Return value for BOARD_PARM_PCIE_PLL (DXL only) */ + +#define BOARD_PARM_RTN_DPLL_SS_0_5 5U /*!< 0.5% spread of PCIE DPLL frequency. */ +#define BOARD_PARM_RTN_DPLL_SS_1 10U /*!< 1% spread of PCIE DPLL frequency. */ +#define BOARD_PARM_RTN_DPLL_SS_1_5 15U /*!< 1.5% spread of PCIE DPLL frequency. */ +#define BOARD_PARM_RTN_DPLL_SS_2 20U /*!< 2% spread of PCIE DPLL frequency. */ + +#define BOARD_PARM_RTN_VDD_MEMC_NOM 0U /*!< MEMC Nominal */ +#define BOARD_PARM_RTN_VDD_MEMC_OD 1U /*!< MEMC Overdrive */ + +#define BOARD_PARM_KS1_RETENTION_DISABLE 0U /*!< Disable retention during KS1 */ +#define BOARD_PARM_KS1_RETENTION_ENABLE 1U /*!< Enable retention during KS1 */ + +#define BOARD_PARM_KS1_ONOFF_WAKE_DISABLE 0U /*!< Disable ONOFF wakeup during KS1 */ +#define BOARD_PARM_KS1_ONOFF_WAKE_ENABLE 1U /*!< Enable ONOFF wakeup during KS1 */ + +#define BOARD_PARM_KS1_WDOG_WAKE_ENABLE 0U /*!< Enable SC WDOG service during KS1 (required for ON_OFF wakeup on some devices) */ +#define BOARD_PARM_KS1_WDOG_WAKE_DISABLE 1U /*!< Disable SC WDOG service during KS1 (SC WDOG disabled during KS1) */ + +/*--------------------------------------------------------------------------*/ +/* Board PLL spread spectrum fspread in part per thousand */ +/* Supported values - 0.4% (4), 1.0% (10), 1.4% (14), 2.0% (20) */ +/*--------------------------------------------------------------------------*/ +#define BOARD_PARM_SSC_N_0P4 4U /*!< Return 0.4% fspread for PLL spread spectrum */ +#define BOARD_PARM_SSC_N_1P0 10U /*!< Return 1.0% fspread for PLL spread spectrum */ +#define BOARD_PARM_SSC_N_1P4 14U /*!< Return 1.4% fspread for PLL spread spectrum */ +#define BOARD_PARM_SSC_N_2P0 20U /*!< Return 2.0% fspread for PLL spread spectrum */ + +/* Types */ + +/*! + * Board config parameter types. + */ +typedef enum +{ + BOARD_PARM_PCIE_PLL = 0, /*!< PCIe PLL internal or external */ + BOARD_PARM_KS1_RESUME_USEC = 1, /*!< Supply ramp delay in usec for KS1 exit */ + BOARD_PARM_KS1_RETENTION = 2, /*!< Controls if retention is applied during KS1 */ + BOARD_PARM_KS1_ONOFF_WAKE = 3, /*!< Controls if ONOFF button can wake from KS1 */ + BOARD_PARM_REBOOT_TIME = 4, /*!< Partition reboot timeout in mS */ + BOARD_PARM_DC0_PLL0_SSC = 5, /*!< DC0 PLL0 spread spectrum config */ + BOARD_PARM_DC0_PLL1_SSC = 6, /*!< DC0 PLL1 spread spectrum config */ + BOARD_PARM_DC1_PLL0_SSC = 7, /*!< DC1 PLL0 spread spectrum config */ + BOARD_PARM_DC1_PLL1_SSC = 8, /*!< DC1 PLL1 spread spectrum config */ + BOARD_PARM_ISI_PIX_FREQ = 9, /*!< ISI pixel clock frequency override */ + BOARD_PARM_VDD_MEMC = 10, /*!< VDD_MEMC voltage, valid only for DXL */ + BOARD_PARM_KS1_WDOG_WAKE = 11, /*!< Controls if SC WDOG configuration during KS1 */ + BOARD_PARM_PCIE_DPLL_SS = 12 /*!< Spread Spectrum SPREAD value for PCIE DPLL (DXL ONLY) */ +} board_parm_t; + +/*! + * Board fault types. + */ +typedef enum +{ + BOARD_BFAULT_COMMON = 0, /*!< Common fault handler */ + BOARD_BFAULT_CPU = 1, /*!< Cortex-M ECC or lockup error */ + BOARD_BFAULT_EXIT = 2, /*!< SCFW exit */ + BOARD_BFAULT_DDR_RET = 3, /*!< DDR retention request without configuration */ + BOARD_BFAULT_REBOOT = 4, /*!< Undetermined partition reboot failure */ + BOARD_BFAULT_BAD_CONTAINER = 5, /*!< Bad boot container, invalid partitions/images */ + BOARD_BFAULT_BRD_FAIL = 6, /*!< Board failure - RM or PMIC, etc. */ + BOARD_BFAULT_TEST_FAIL = 7, /*!< Unit test failure, exit */ + BOARD_BFAULT_DDR_INIT_FAIL = 8 /*!< board_init_ddr() returned an error */ +} sc_bfault_t; + +/*! + * Board reboot timeout actions. + */ +typedef enum +{ + BOARD_REBOOT_TO_NONE = 0, /*!< Reboot timeout does nothing */ + BOARD_REBOOT_TO_FORCE = 1, /*!< Reboot timeout forces reboot continue */ + BOARD_REBOOT_TO_FAULT = 2 /*!< Reboot timeout causes board fault */ +} board_reboot_to_t; + +/*! + * Board config parameter returns. + */ +typedef uint32_t board_parm_rtn_t; + +/*! + * Board reset event types for CPUs. + */ +typedef enum +{ + BOARD_CPU_RESET_SELF = 0, /*!< Self requested reset */ + BOARD_CPU_RESET_WDOG = 1, /*!< Watchdog reset */ + BOARD_CPU_RESET_LOCKUP = 2, /*!< Lockup reset */ + BOARD_CPU_RESET_MEM_ERR = 3 /*!< Memory error reset */ +} board_cpu_rst_ev_t; + +/*! + * DDR actions (power state transitions, etc.) + */ +typedef enum +{ + BOARD_DDR_COLD_INIT = 0, /*!< Init DDR from POR */ + BOARD_DDR_PERIODIC = 1, /*!< Run periodic training */ + BOARD_DDR_SR_DRC_ON_ENTER = 2, /*!< Enter self-refresh (leave DRC on) */ + BOARD_DDR_SR_DRC_ON_EXIT = 3, /*!< Exit self-refresh (DRC was on) */ + BOARD_DDR_SR_DRC_OFF_ENTER = 4, /*!< Enter self-refresh (turn off DRC) */ + BOARD_DDR_SR_DRC_OFF_EXIT = 5, /*!< Exit self-refresh (DRC was off) */ + BOARD_DDR_PERIODIC_HALT = 6, /*!< Halt periodic training */ + BOARD_DDR_PERIODIC_RESTART = 7, /*!< Restart periodic training */ + BOARD_DDR_DERATE_PERIODIC = 8, /*!< Run periodic derate */ + BOARD_DDR0_VREF = 9, /*!< Run VREF training for DRC 0 */ + BOARD_DDR1_VREF = 10 /*!< Run VREF training for DRC 1 */ +} board_ddr_action_t; + +/* Macros */ + +/*! + * @name Macros for DCD processing + */ +/** @{ */ +#define DATA4(A, V) *((volatile uint32_t*)(A)) = U32(V) +#define SET_BIT4(A, V) *((volatile uint32_t*)(A)) |= U32(V) +#define CLR_BIT4(A, V) *((volatile uint32_t*)(A)) &= ~(U32(V)) +#define CHECK_BITS_SET4(A, M) while((*((volatile uint32_t*)(A)) \ + & U32(M)) != ((uint32_t)(M))){} +#define CHECK_BITS_CLR4(A, M) while((*((volatile uint32_t*)(A)) \ + & U32(M)) != U32(0U)){} +#define CHECK_ANY_BIT_SET4(A, M) while((*((volatile uint32_t*)(A)) \ + & U32(M)) == U32(0U)){} +#define CHECK_ANY_BIT_CLR4(A, M) while((*((volatile uint32_t*)(A)) \ + & U32(M)) == U32(M)){} +/** @} */ + +/*! + * Macro for debug of board calls + */ +#define BRD_ERR(X) /* Call function */ \ + err = (X); \ + /* Check error returned */ \ + if (err != SC_ERR_NONE) \ + { \ + /* Print line number */ \ + board_print(3, "error @ line %d: %d\n", \ + __LINE__, err); \ + /* Call board function to handle */ \ + board_fault(SC_FALSE, \ + BOARD_BFAULT_BRD_FAIL, SC_PT); \ + } + +#if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + /*! + * Macro for naming partitions + */ + #define PARTITION_NAME(PT, NAME) \ + rm_part_names[PT] = NAME +#else + /*! + * Macro for naming partitions + */ + #define PARTITION_NAME(PT, NAME) \ + NOP +#endif + +/* Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +/*! + * This function initalizes the board. + * + * @param[in] phase boot phase + * + * There are seven phases to board initialization. The first phase is system + * init (\a phase = BOOT_PHASE_SYS_INIT). This happens before any HW access is + * possible. The second phase is the API phase (\a phase = BOOT_PHASE_API_INIT) + * and initializes all of the board interface data structures. The third phase + * (\a phase = BOOT_PHASE_HW_INIT) is the HW phase and this initializes + * the board hardware. The fourth phase (\a phase = BOOT_PHASE_EARLY_INIT) + * is just before starting early CPU. The fifth phase (\a phase = + * BOOT_PHASE_LATE_INIT) is just before starting the remaining CPUs. + * The sixth phase (\a phase = BOOT_PHASE_FINAL_INIT) is the final boot + * phase and is used to wrap up any needed init. A test phase (\a phase = + * BOOT_PHASE_TEST_INIT) is called only when an SCFW image is built with + * unit tests and is called just before any tests are run. + */ +void board_init(boot_phase_t phase); + +/*! + * This function returns the debug UART info. + * + * @param[in] inst UART instance + * @param[in] baud UART baud rate + * + * @return Pointer to the debug UART type. + */ +LPUART_Type *board_get_debug_uart(uint8_t *inst, uint32_t *baud); + +/*! + * This function initalizes the debug UART. + * + * @param[in] early_phase flag indicating phase + */ +void board_config_debug_uart(sc_bool_t early_phase); + +/*! + * This function powers off the debug UART. + * + * Only called when rebooting a partition. Only needs to power + * down the UART if it isn't the dedicated SCU UART. + * board_get_debug_uart() will be called again after the reboot + * completes. + */ +void board_disable_debug_uart(void); + +/*! + * This function configures SCU resources. + * + * @param[in] pt_sc SCU partition + * + * By default, the SCFW keeps most of the resources found in the SCU + * subsystem. It also keeps the SCU/PMIC pads required for the main + * code to function. Any additional resources or pads required for + * the board code to run should be kept here. This is done by marking + * them as not movable. + */ +void board_config_sc(sc_rm_pt_t pt_sc); + +/*! + * This function returns board configuration info. + * + * @param[in] parm parameter to return + * + * This function is used to return board configuration info. Parameters + * define if various how various SoC connections are made at the + * board-level. For example, the external PCIe clock input. + * + * Note this can be called at any time in the boot process. If a return + * value is based on run-time detection (for example reading a GPIO) + * great care must be take to insure the return value is correct and + * that infrastructure is powered to allow this. + * + * See example code (board.c) for parameter/returns options. + * + * @return Returns the paramter value. + */ +board_parm_rtn_t board_parameter(board_parm_t parm); + +/*! + * This function returns resource availability info. + * + * @param[in] rsrc resource to check + * + * This function is used to return board configuration info. It reports + * if resources are functional on this board. For example, which DDR + * controllers are used. + * + * See example code (board.c) for more details. + * + * @return Returns SC_TRUE if available. + */ +sc_bool_t board_rsrc_avail(sc_rsrc_t rsrc); + +/*! + * This function initalizes DDR. + * + * @param[in] early phase of init + * @param[in] ddr_initialized True if ROM initialized the DDR + * + * This function may be called twice. The early parameter is SC_TRUE when + * called prior to MCU start and SC_FALSE when called after. This + * allows the implementation to decide when DDR init needs to be + * done. + * + * Note the first call will not occur unless SC_BD_FLAGS_EARLY_CPU_START + * is set in bd_flags of the boot container. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t board_init_ddr(sc_bool_t early, sc_bool_t ddr_initialized); + +/*! + * This function cinfigures the DDR. + * + * @param[in] rom_caller is ROM the caller? + * @param[in] action perform this action on DDR + * + * @return Returns SC_ERR_NONE if successful. + * + * This function may be called from the ROM (\a rom_caller = SC_TRUE). In + * this case, the SCFW startup has not yet run and it is not valid to call + * most SCFW function calls. ANA_WRITE() and SYSCTR_TimeDelay() + * are the only two functions that have are safe to call. + */ +sc_err_t board_ddr_config(bool rom_caller, board_ddr_action_t action); + +/*! + * This function allows the board file to do SCFW configuration. + * + * @param[in] early phase of init + * @param[in] pt_boot boot partition + * + * This function may be called twice. The early parameter is SC_TRUE when + * called prior to MCU start and SC_FALSE when called after. This allows + * the implementation to decide when to do configuration processing. + * + * Note the first call will not occur unless SC_BD_FLAGS_EARLY_CPU_START + * is set in bd_flags of the boot container. + * + * Typical actions here include creating a resource partition for an MCU, + * powering up a board component, or configuring a shared clock. + */ +void board_system_config(sc_bool_t early, sc_rm_pt_t pt_boot); + +/*! + * This function returns SC_TRUE for early CPUs. + * + * @param[in] cpu CPU + * + * This function should return SC_TRUE if the CPU in question may + * be started early. This early start is before power on of later + * CPU subsystems. It would normally return SC_TRUE for MCU cores that + * need to run early. Only SC_R_MCU_0_PID0 and SC_R_MCU_1_PID0 can + * return SC_TRUE. + * + * Note CPUs will only get started early if SC_BD_FLAGS_EARLY_CPU_START + * is set in bd_flags of the boot container. + * + * @return Returns SC_TRUE if CPU should start early. + */ +sc_bool_t board_early_cpu(sc_rsrc_t cpu); + +/*! + * Function to override QoS configuration. + * + * @param[in] ss subsystem with QoS controls + */ +void board_qos_config(sc_sub_t ss); + +/** @} */ + +/*! + * @name Power Functions + * @{ + */ + +/*! + * This function transitions the power state for an external board- + * level supply which goes to the i.MX8. + * + * @param[in] ss subsystem using supply + * @param[in] pd power domain + * @param[in] from_mode power mode transitioning from + * @param[in] to_mode power mode transitioning to + * + * This function is used to transition a board power supply that is + * used by the SoC. It allows mapping of subsystem power domains + * to board supplies. + * + * Note that the base code will enable/disable isolators after + * changing the state of internal power domains. External supplies + * sometimes supply a domain connected via an isolator to a domain + * passed here. In this case, this function needs to also control the + * connected domain's supply. For example, when LVDS SS PD (PD1) is + * powered toggled, the external supply for the LVDS PHY must be + * toggled here. MIPI and CSI SS PD are similar. + */ +void board_set_power_mode(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); + +/*! + * This function sets the voltage for a PMIC controlled SS. + * + * @param[in] ss subsystem + * @param[in] new_volt voltage value to be set + * @param[in] old_volt current voltage + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t board_set_voltage(sc_sub_t ss, uint32_t new_volt, uint32_t old_volt); + +/*! + * This function is used to set power supplies of the board when + * entering and exiting low power mode. + * + * @param[in] mode power mode to apply + * + * Note this function is not called by sc_pm_set_sys_power_mode(). + * It is called when the system dynamically transitions power modes + * during run-time execution. It is normally used to manage the + * supply for the memories (MEMC). + */ +void board_lpm(sc_pm_power_mode_t mode); + +/*! + * This function transitions the power state for an external board- + * level supply which goes to a board component. + * + * @param[in] idx board-relative resource index + * @param[in] rsrc_idx unified resource index + * @param[in] from_mode power mode transitioning from + * @param[in] to_mode power mode transitioning to + * + * This function is used to transition a board power supply that is + * used by a board component. It allows mapping of board resources + * (e.g. SC_R_BOARD_R0) to board supplies. + * + * \a idx should be used to identify the resource. It is 0-n and is + * associated with the board reosurces PMIC_0 through BOARD_R7. + * + * \a rsrc_idx is only useful for debug output of a resource name. + */ +void board_trans_resource_power(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, + sc_pm_power_mode_t from_mode,sc_pm_power_mode_t to_mode); + +/*! + * This function resets a board resource. + * + * @param[in] idx board-relative resource index + * @param[in] rsrc_idx unified resource index + * @param[in] pt partition + * + * This function is used to reset resource. If pt equals SC_PT_ALL + * then reset all resources belonging to that partition. Otherwise, + * reset rsrc_idx only. + * + * It is only called when a partition is rebooted or when the + * sc_pm_resource_reset() function is called. Is is usually empty + * unless a resource can't be powered off but can be soft reset. + * + * \a idx should be used to identify the resource. It is 0-n and is + * associated with the board reosurces PMIC_0 through BOARD_R7. + * + * \a rsrc_idx is only useful for debug output of a resource name. + */ +void board_rsrc_reset(sc_rm_idx_t idx, sc_rm_idx_t rsrc_idx, sc_rm_pt_t pt); + +/** @} */ + +/*! + * @name Misc Functions + * @{ + */ + +/*! + * This function is used to set the board power. + * + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid mode + * + * This function is only called by sc_pm_set_sys_power_mode(). + * It is normally used ask the PMIC to power off the board + * completly. + */ +sc_err_t board_power(sc_pm_power_mode_t mode); + +/*! + * This function is used to reset the system. + * + * @param[in] type reset type + * @param[in] reason cause of reset + * @param[in] pt partition causing reset + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid type + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +sc_err_t board_reset(sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_rm_pt_t pt); + +/*! + * This function is called when a CPU encounters a reset + * event. + * + * @param[in] resource CPU resource + * @param[in] reset_event CPU reset event + * @param[in] pt partition of CPU + */ +void board_cpu_reset(sc_rsrc_t resource, board_cpu_rst_ev_t reset_event, + sc_rm_pt_t pt); + +/*! + * This function is called when a partition reboot is requested. It allows + * the port to override the parameters or take other action such as logging + * or reboot the board. + * + * @param[in] pt partition being rebooted + * @param[in,out] type pointer to modify reset type + * @param[in,out] reason pointer to modify reset reason + * @param[in,out] mode pointer to modify power cycle mode + * @param[out] mask pointer to return mask of wait partitions + * + * Code can modify or log the parameters. Can also take another action like + * reset the board. After return from this function, the partition will be + * rebooted. + * + * Type is cold, warm, board. Reason is SW, WDOG, etc. Reboot is accomplished + * by reducing power and reapplying. Mode indicates the power level to reduce + * to (usually off). + * + * If \a mask is non-0 mask, then the reboot will be delayed until all + * partitions indicated in the mask (pt 1 = bit 1, etc.) have called + * sc_pm_reboot_continue() to continue the boot. + */ +void board_reboot_part(sc_rm_pt_t pt, sc_pm_reset_type_t *type, + sc_pm_reset_reason_t *reason, sc_pm_power_mode_t *mode, + uint32_t *mask); + +/*! + * This function is called when a partition reboot is has powered off the + * partition but has not yet powered it back on. It allows the boot parameters + * to be changed. Could also bracket a change done in board_reboot_part(). + * + * @param[in] pt partition being rebooted + * @param[in,out] boot_cpu pointer to modify the boot CPU + * @param[in,out] boot_mu pointer to modify the boot MU + * @param[in,out] boot_dev pointer to modify the boot device + * @param[in,out] boot_addr pointer to modify the boot address + * + */ +void board_reboot_part_cont(sc_rm_pt_t pt, sc_rsrc_t *boot_cpu, + sc_rsrc_t *boot_mu, sc_rsrc_t *boot_dev, sc_faddr_t *boot_addr); + +/*! + * This function is called when a partition reboot times out. + * + * @param[in] pt partition being rebooted + * + * @return Returns the desired action. + */ +board_reboot_to_t board_reboot_timeout(sc_rm_pt_t pt); + +/*! + * This function is called when a SS (other than SCU) reports a + * panic temp alarm. + * + * @param[in] dsc dsc reporting alarm + * + * Note this function would normally request a board reset. + * + * See the Porting Guide for more information. + */ +void board_panic(sc_dsc_t dsc); + +/*! + * This function is called when a fault is detected or the SCFW + * returns from main(). + * + * @param[in] restarted SC_TRUE if called on restart + * @param[in] reason reason for the fault + * @param[in] pt partition causing fault + * + * Note this function would normally request a board reset. For + * debug builds it is common to disable the watchdog and loop. + * + * The \a restarted paramter is SC_TRUE if this error is pending from + * the last restart. + */ +void board_fault(sc_bool_t restarted, sc_bfault_t reason, + sc_rm_pt_t pt); + +/*! + * This function is called when a security violation is reported by + * the SECO or SNVS. + * + * Note this function would normally request a board reset. For + * debug builds it is common to do nothing. + */ +void board_security_violation(void); + +/*! + * This function is used to return the current status of the ON/OFF + * button. + * + * @return Returns the status + */ +sc_bool_t board_get_button_status(void); + +/*! + * This function sets a miscellaneous control value. + * + * @param[in] resource resource + * @param[in] idx board resource index + * @param[in] rsrc_idx unified resource index + * @param[in] ctrl control to write + * @param[in] val value to write + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note this function can be used to set voltages for both SoC + * resources and board resources (e.g. SC_R_BOARD_R0). + */ +sc_err_t board_set_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t val); + +/*! + * This function gets a miscellaneous control value. + * + * @param[in] resource resource + * @param[in] idx board resource index + * @param[in] rsrc_idx unified resource index + * @param[in] ctrl control to read + * @param[out] val pointer to return value + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t board_get_control(sc_rsrc_t resource, sc_rm_idx_t idx, + sc_rm_idx_t rsrc_idx, uint32_t ctrl, uint32_t *val); + +/*! + * This function is called periodically to tick the board. + * + * @param[in] msec number of mS to increment + * + * Can be used to implement customer watchdogs, monitor some + * hardware, etc. + */ +void board_tick(uint16_t msec); + +/*! + * This function is called when sc_misc_board_ioctl() is called. + * + * @param[in] caller_pt handle of caller partition + * @param[in] mu receiving MU via RPC/IPC + * @param[in,out] parm1 pointer to pass parameter 1 + * @param[in,out] parm2 pointer to pass parameter 2 + * @param[in,out] parm3 pointer to pass parameter 3 + * + * Can be used to implement customer watchdogs, monitor some + * hardware, etc. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t board_ioctl(sc_rm_pt_t caller_pt, sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3); + +/*! + * Interrupt handler for the PMIC. + */ +void PMIC_IRQHandler(void); + +/*! + * Interrupt handler for the SNVS button. + */ +void SNVS_Button_IRQHandler(void); + +/** @} */ + +/* Externs */ + +/*! + * External variable for accessing the number of board resources. + */ +extern const sc_rm_idx_t board_num_rsrc; + +/*! + * External variable for accessing the board resource map. + */ +extern const sc_rsrc_map_t board_rsrc_map[BRD_NUM_RSRC_BRD]; + +/*! + * External variable for specing DDR periodic training. + */ +extern const uint32_t board_ddr_period_ms; + +/*! + * External variable for DDR periodic derate. + */ +extern const uint32_t board_ddr_derate_period_ms; + +#endif /* SC_BOARD_API_H */ + +/** \example board.c + * This is an example implementation for the i.MX8QM MEK board. + */ + +/** @} */ + diff --git a/platform/main/boot.h b/platform/main/boot.h new file mode 100755 index 0000000..d3deaaa --- /dev/null +++ b/platform/main/boot.h @@ -0,0 +1,295 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for interaction with the ROM. + */ +/*==========================================================================*/ + +#ifndef SC_BOOT_H +#define SC_BOOT_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +#define SC_BOOT_DATA_BARKER 0xC0FFEE16U +#define SC_BOOT_DATA_VER 0x01U + +#define SC_IMG_TYPE_EXEC 0x03U /* Executable image type */ +#define SC_IMG_TYPE_DATA 0x04U /* Data image type */ +#define SC_IMG_TYPE_DDR_INIT 0x05U /* DDR init image type */ +#define SC_IMG_TYPE_SECO 0x06U /* SECO image type */ +#define SC_IMG_TYPE_PROVSN 0x07U /* Provisioning image type */ +#define SC_IMG_TYPE_DEK 0x08U /* DEK image type */ +#define SC_IMG_TYPE_V2X_PRI_FW 0x0BU /* Primary V2X FW */ +#define SC_IMG_TYPE_V2X_SND_FW 0x0CU /* Secondary V2X FW */ +#define SC_IMG_TYPE_V2X_PATCH 0x0DU /* V2X patch */ +#define SC_IMG_TYPE_V2X_DUMMY 0x0EU /* A dummy image entity in SCU CTNR, provides loading space */ +#define SC_IMG_TYPE_DEBUG 0x10U /* Signed debug enable message */ +#define SC_IMG_TYPE_SECFUSE 0x11U /* Signed secure fuse message */ +#define SC_IMG_TYPE_RETURN 0x12U /* Signed field return message */ +#define SC_IMG_TYPE_PATCH 0x13U /* Signed patch message */ +#define SC_IMG_TYPE_FIPSZERO 0x14U /* FIPS zero message */ +#define SC_IMG_TYPE_ALL 0xFFU /* All images */ + +#define SC_BD_FLAGS_NOT_SECURE 16U +#define SC_BD_FLAGS_NOT_ISOLATED 17U +#define SC_BD_FLAGS_RESTRICTED 18U +#define SC_BD_FLAGS_GRANT 19U +#define SC_BD_FLAGS_NOT_COHERENT 20U +#define SC_BD_FLAGS_ALT_CONFIG 21U +#define SC_BD_FLAGS_EARLY_CPU_START 22U +#define SC_BD_FLAGS_DDRTEST 23U +#define SC_BD_FLAGS_NO_AP 24U +#define SC_BD_FLAGS_ALT_CONFIG2 25U + +/* Types */ + +/*! + * This type is used to indicate boot type. + */ +typedef enum +{ + SC_BT_TYPE_PRIMARY = 1, + SC_BT_TYPE_SECONDARY = 2, + SC_BT_TYPE_RECOVERY = 3, + SC_BT_TYPE_SERIAL = 0xFF +} sc_bt_type_t; + +/*! + * This type is used to indicate boot device. + */ +typedef enum +{ + SC_BT_DEV_TYPE_SD = 1, + SC_BT_DEV_TYPE_MMC = 2, + SC_BT_DEV_TYPE_NAND = 3, + SC_BT_DEV_TYPE_FLEXSPINOR = 4, + SC_BT_DEV_TYPE_SATA_DISK = 7, + SC_BT_DEV_TYPE_USB = 14 +} sc_bt_dev_type_t; + +/*! + * This type is used to store a CPU start request. + */ +typedef struct +{ + sc_faddr_t addr; //!< 64-bit address to boot from + uint16_t cpu; //!< CPU to start + uint16_t mu; //!< MU associated with this CPU + uint8_t part; //!< Partition to start + uint8_t resv[3]; //!< Reserved +} sc_boot_list_t; + +/*! + * This type is used pass data from the ROM to the SCFW. + */ +typedef struct +{ + uint32_t barker; //!< Barker code + uint16_t ver; //!< Version + uint16_t size; //!< Size + uint8_t num; //!< Number images in list + uint8_t resv0[3]; //!< Reserved + uint32_t bd_flags; //!< Boot data flags + sc_boot_list_t img[SC_BOOT_MAX_LIST]; //!< image list + uint32_t resv1[4]; //!< was SCD address +} sc_boot_data_t; + +/*! + * This type is used store handoff header info. + */ +typedef struct +{ + uint16_t barker; //!< Barker code + uint16_t len; //!< Size +} sc_handoff_header_t; + +/*! + * This type is used pass boot device info from the ROM to the SCFW. + */ +typedef struct +{ + sc_bt_type_t bt_type; //!< Boot type + uint8_t instance; //!< Instance number + sc_bt_dev_type_t dev_type; //!< Device type + uint8_t resv2; +} sc_bt_dev_info_t; + +/*! + * This type is used pass extended data from the ROM to the SCFW. + */ +typedef struct +{ + sc_handoff_header_t header; //!< Barker/size info + uint32_t bringup_flags; //!< SS bring up flags + union + { + sc_bt_dev_info_t bt_dev_info; //!< Boot device + uint32_t u; //!< Force 32 bits + }; + uint32_t core_freq; + uint32_t axi_freq; + uint32_t ddr_freq; + uint32_t rom_tick_freq; + uint8_t ver; + uint8_t rsv1[3]; + uint32_t bringup_flags2; //!< SS bring up expansion + uint32_t rsv2; +} sc_boot_data2_t; + +/*! + * This type is used pass passover data from the ROM to the AP. + */ +typedef struct +{ + uint16_t tag; //!< Tag + uint8_t len; //!< Fixed value of 0x20 + uint8_t ver; //!< Version + uint32_t boot_mode; //!< Boot mode + uint32_t card_addr_mode; //!< SD card address mode + uint32_t bad_blks_of_img_set0; //!< NAND bad block count skipped 1 + uint32_t ap_mu_id; //!< AP MU ID + uint32_t bad_blks_of_img_set1; //!< NAND bad block count skipped 1 + uint8_t boot_stage; //!< Boot stage + uint8_t img_set_sel; //!< Image set booted from + uint8_t rsv[2]; //!< Reserved + uint32_t img_set_end; //!< Offset of Image End +} sc_passover_t; + +#ifdef SC_ROM_FUNC_ADDR + /*! + * This type is used make calls to the ROM. + */ + typedef struct + { + uint16_t ver; + uint16_t tag; + uint32_t (*dsc_ai_read)(uint8_t dsc_id, uint8_t src_sel, + uint16_t address); + int32_t (*dsc_ai_write)(uint8_t dsc_id, uint8_t src_sel, + uint16_t address, uint32_t data); + } sc_rom_functions_t; +#endif + +/* Functions */ + +sc_err_t boot_init(sc_bool_t allow); + +/*! + * This function returns flags passed to the SCFW from the ROM. These + * come from the boot container (bd_flags). + * + * @param[out] flag pointer to return raw flag value + * @param[out] not_secure pointer to return secure flag + * @param[out] not_isolated pointer to return isolated flag + * @param[out] restricted pointer to return restricted flag + * @param[out] grant pointer to return grant flag + * @param[out] not_coherent pointer to return coherent flag + * @param[out] alt_config pointer to return alt_config flag + * @param[out] early pointer to return early flag + * @param[out] ddrtest pointer to return ddrtest flag + * @param[out] no_ap pointer to return no_ap flag + * @param[out] alt_config2 pointer to return alt_config 2 flag + * + * For all pointers, NULL will result in no return of that value. + * + * See the [Boot Flags](@ref BOOT_FLAGS) section for definition + * of these flags. + * + * Many of the flags (some inverted) are used to create the + * boot partition by calling sc_rm_partition_alloc(). + */ +void boot_get_data(uint32_t *flag, sc_bool_t *not_secure, + sc_bool_t *not_isolated, sc_bool_t *restricted, sc_bool_t *grant, + sc_bool_t *not_coherent, sc_bool_t *alt_config, sc_bool_t *early, + sc_bool_t *ddrtest, sc_bool_t *no_ap, sc_bool_t *alt_config2); + +sc_err_t boot_get_img_1(uint8_t type, sc_rsrc_t *cpu, sc_faddr_t *addr, + sc_rsrc_t *mu, sc_rm_pt_t *pt, sc_bool_t force_ap); +sc_err_t boot_get_img_n(uint8_t type, sc_rsrc_t *cpu, sc_faddr_t *addr, + sc_rsrc_t *mu, sc_rm_pt_t *pt, sc_bool_t force_ap); +sc_err_t boot_get_bring_up(sc_sub_t ss, sc_bool_t *flag); +sc_err_t boot_get_boot_dev(sc_bt_dev_type_t *dev_type, uint8_t *inst, + sc_bt_type_t *bt_type); +sc_err_t boot_get_container_idx(uint8_t *idx); +uint8_t boot_get_img_num(void); +sc_err_t boot_get_img_start_addr(uint16_t img, sc_faddr_t *addr); + +/*! + * This function checks to see if a partition will be booting. + * + * @param[in] pt partition + * + * @return Returns SC_TRUE if the partition will boot. + */ +sc_bool_t boot_is_booting(sc_rm_pt_t pt); + +/*! + * This function returns the boot device resource associate with + * the specified partition. + * + * @param[in] pt partition + * @param[in] check_pt Boolean to verify if boot device needs + * to be associated with the partition. + * + * @return Returns the boot device. + */ +sc_rsrc_t boot_get_dev(sc_rm_pt_t pt, sc_bool_t check_pt); + +void boot_check_rom_data(void); + +#ifdef FLEXSPI_V2X_ADDR +/*! + * Return info from parsed FlexSPI container headers. + * + * @param[out] v2x_fw_addr pointer to return the V2X FW address + * @param[out] v2x_fw_size pointer to return the V2X FW size + * @param[out] dummy_addr pointer to return the dummy address + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t boot_get_flexspi_v2x_info(sc_saddr_t *v2x_fw_addr, + uint32_t *v2x_fw_size, sc_saddr_t *dummy_addr); +#endif + +#endif /* SC_BOOT_H */ + diff --git a/platform/main/build_info.h b/platform/main/build_info.h new file mode 100644 index 0000000..8303d05 --- /dev/null +++ b/platform/main/build_info.h @@ -0,0 +1,11 @@ +#ifndef BUILD_INFO_H +#define BUILD_INFO_H + +#define SCFW_BRANCH imx_scfw_2020q4 +#define SCFW_BUILD 5126UL +#define SCFW_COMMIT 0x0d54291fUL +#define SCFW_DATE "Dec 17 2020" +#define SCFW_DATE2 Dec_17_2020 +#define SCFW_TIME "03:04:44" + +#endif diff --git a/platform/main/debug.h b/platform/main/debug.h new file mode 100755 index 0000000..fc62ce3 --- /dev/null +++ b/platform/main/debug.h @@ -0,0 +1,359 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the system controller debug functionality. + */ +/*==========================================================================*/ + +#ifndef DEBUG_H +#define DEBUG_H + +/* Includes */ + +/* Debug Switches */ + +/*! This define sets the gobal debug level: +* - 0=Nothing +* - 1=+Banners +* - 2=+Data Dumps +* - 3=+Function entry/exit +* - 4=+Internal inline data +* - 5=All +*/ +#define DEBUG_LEVEL 2 + +#define DEBUG_BOOT +//#define DEBUG_DRV +//#define DEBUG_SS +//#define DEBUG_IRQ +//#define DEBUG_MISC +//#define DEBUG_PAD +//#define DEBUG_PM +//#define DEBUG_RM +//#define DEBUG_TIMER +#define DEBUG_BOARD +#define DEBUG_TEST +//#define DEBUG_DDRC +#define DEBUG_PMIC +//#define DEBUG_SOC +//#define DEBUG_SECO +//#define DEBUG_V2X + +#define DEBUG_RM_DUMP 4 +#define DEBUG_SS_DUMP(args...) ss_print(2, args) +#define DEBUG_SS_DSC_PM(args...) ss_print(2, args) +#define DEBUG_DRV_DSC(args...) drv_print(2, args) +#define DEBUG_DRV_DSC_DUMP(args...) drv_print(4, args) +#define DEBUG_DRV_XRDC2(args...) drv_print(5, args) +#define DEBUG_AI_DUMP(args...) debug_print(2, args) + +#ifndef HAS_TEST + #if 0 + #define DEBUG_RPC + #endif +#endif + +/* SIMU Debug */ + +#ifndef RD + #ifdef SIMU + #undef DEBUG_LEVEL + #define DEBUG_LEVEL 3 + #define DEBUG_BOOT + #define DEBUG_DRV + #define DEBUG_SS + #define DEBUG_IRQ + #define DEBUG_MISC + #define DEBUG_PAD + #define DEBUG_PM + #define DEBUG_RM + #define DEBUG_TIMER + #define DEBUG_BOARD + #define DEBUG_TEST + #undef DEBUG_RM_DUMP + #define DEBUG_RM_DUMP 3 + #undef DEBUG_SS_DUMP + #define DEBUG_SS_DUMP(args...) ss_print(3, args) + #undef DEBUG_SS_DSC_PM + #define DEBUG_SS_DSC_PM(args...) ss_print(2, args) + #undef DEBUG_DRV_DSC + #define DEBUG_DRV_DSC(args...) drv_print(2, args) + #undef DEBUG_DRV_DSC_DUMP + #define DEBUG_DRV_DSC_DUMP(args...) drv_print(3, args) + #undef DEBUG_DRV_XRDC2 + #define DEBUG_DRV_XRDC2(args...) drv_print(5, args) + #undef DEBUG_AI_DUMP + #define DEBUG_AI_DUMP(args...) debug_print(2, args) + #endif +#endif + +#ifdef MONITOR + #define DEBUG_DRV + #define DEBUG_SS + #undef DEBUG_SS_DUMP + #define DEBUG_SS_DUMP(args...) ss_print(0, args) + #undef DEBUG_DRV_DSC_DUMP + #define DEBUG_DRV_DSC_DUMP(args...) drv_print(0, args) + #undef DEBUG_LEVEL + #define DEBUG_LEVEL 1 +#endif + +#ifdef DL + #undef DEBUG_LEVEL + #define DEBUG_LEVEL DL +#endif + +#ifdef TL + #define TL1 TL + #define TL2 TL + #define TL3 3 +#else + #define TL1 1 + #define TL2 2 + #define TL3 3 +#endif + +/* Defines */ + +#ifdef DEBUG + #define debug0_print(...) \ + board_printf(__VA_ARGS__); +#else + #define debug0_print(args...) \ + NOP +#endif + +#if 1 <= DEBUG_LEVEL + #define debug1_print(...) \ + board_printf(__VA_ARGS__); +#else + #define debug1_print(args...) \ + NOP +#endif + +#if 2 <= DEBUG_LEVEL + #define debug2_print(...) \ + board_printf(__VA_ARGS__); +#else + #define debug2_print(args...) \ + NOP +#endif + +#if 3 <= DEBUG_LEVEL + #define debug3_print(...) \ + board_printf(__VA_ARGS__); +#else + #define debug3_print(args...) \ + NOP +#endif + +#if 4 <= DEBUG_LEVEL + #define debug4_print(...) \ + board_printf(__VA_ARGS__); +#else + #define debug4_print(args...) \ + NOP +#endif + +#if 5 <= DEBUG_LEVEL + #define debug5_print(...) \ + board_printf(__VA_ARGS__); +#else + #define debug5_print(args...) \ + NOP +#endif + +#ifdef DEBUG + #define debug_print(dl, args...) \ + debug##dl##_print(args) +#else + #define debug_print(args...) \ + NOP +#endif + +#ifdef DEBUG_BOOT + #define boot_print(dl, args...) \ + debug_print(dl, args) +#else + #define boot_print(args...) \ + NOP +#endif + +#ifdef DEBUG_DRV + #define drv_print(dl, args...) \ + debug_print(dl, args) +#else + #define drv_print(args...) \ + NOP +#endif + +#ifdef DEBUG_SOC + #define soc_print(dl, args...) \ + debug_print(dl, args) +#else + #define soc_print(args...) \ + NOP +#endif + +#ifdef DEBUG_SS + #define ss_print(dl, args...) \ + debug_print(dl, args) +#else + #define ss_print(args...) \ + NOP +#endif + +#ifdef DEBUG_IRQ + #define irq_print(dl, args...) \ + debug_print(dl, args) +#else + #define irq_print(args...) \ + NOP +#endif + +#ifdef DEBUG_MISC + #define misc_print(dl, args...) \ + debug_print(dl, args) +#else + #define misc_print(args...) \ + NOP +#endif + +#ifdef DEBUG_PAD + #define pad_print(dl, args...) \ + debug_print(dl, args) +#else + #define pad_print(args...) \ + NOP +#endif + +#ifdef DEBUG_PM + #define pm_print(dl, args...) \ + debug_print(dl, args) +#else + #define pm_print(args...) \ + NOP +#endif + +#ifdef DEBUG_RM + #define rm_print(dl, args...) \ + debug_print(dl, args) +#else + #define rm_print(args...) \ + NOP +#endif + +#ifdef DEBUG_TIMER + #define timer_print(dl, args...) \ + debug_print(dl, args) +#else + #define timer_print(args...) \ + NOP +#endif + +#ifdef DEBUG_BOARD + #define board_print(dl, args...) \ + debug_print(dl, args) +#else + #define board_print(args...) \ + NOP +#endif + +#ifdef DEBUG_TEST + #define test_print(dl, args...) \ + debug_print(dl, args) +#else + #define test_print(args...) \ + NOP +#endif + +#ifdef DEBUG_RPC + #define rpc_print(dl, args...) \ + debug_print(dl, args) +#else + #define rpc_print(args...) \ + NOP +#endif + +#ifdef DEBUG_DDRC + #define ddrc_print(dl, args...)\ + debug_print(dl, args) +#else + #define ddrc_print(args...) \ + NOP +#endif + +#ifdef DEBUG_PMIC + #define pmic_print(dl, args...)\ + debug_print(dl, args) +#else + #define pmic_print(...) \ + NOP +#endif + +#ifdef DEBUG_SECO + #define seco_print(dl, args...) \ + debug_print(dl, args) +#else + #define seco_print(args...) \ + NOP +#endif + +#ifdef DEBUG_V2X + #define v2x_print(dl, args...) \ + debug_print(dl, args) +#else + #define v2x_print(args...) \ + NOP +#endif + +#define debug_print_pk(dl, args...) \ + if (debug_level >= (dl)) \ + { \ + debug_print(0, args); \ + } + +#define error_print(...) \ + debug_print(0, __VA_ARGS__) + +#define always_print(...) \ + debug_print(0, __VA_ARGS__) + +#endif /* DEBUG_H */ + diff --git a/platform/main/ipc.h b/platform/main/ipc.h new file mode 100755 index 0000000..5a9644f --- /dev/null +++ b/platform/main/ipc.h @@ -0,0 +1,99 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the IPC implementation. + */ +/*==========================================================================*/ + +#ifndef SC_IPC_H +#define SC_IPC_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * This function opens an IPC channel. + * + * @param[out] ipc return pointer for ipc handle + * @param[in] id id of channel to open + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC + * otherwise). + * + * The \a id parameter is implementation specific. Could be an MU + * address, pointer to a driver path, channel index, etc. + */ +sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id); + +/*! + * This function closes an IPC channel. + * + * @param[in] ipc id of channel to close + */ +void sc_ipc_close(sc_ipc_t ipc); + +/*! + * This function reads a message from an IPC channel. + * + * @param[in] ipc id of channel read from + * @param[out] data pointer to message buffer to read + * + * This function will block if no message is available to be read. + */ +void sc_ipc_read(sc_ipc_t ipc, void *data); + +/*! + * This function writes a message to an IPC channel. + * + * @param[in] ipc id of channel to write to + * @param[in] data pointer to message buffer to write + * + * This function will block if the outgoing buffer is full. + */ +void sc_ipc_write(sc_ipc_t ipc, const void *data); + +#endif /* SC_IPC_H */ + diff --git a/platform/main/ipc_srv.h b/platform/main/ipc_srv.h new file mode 100755 index 0000000..c698ec7 --- /dev/null +++ b/platform/main/ipc_srv.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the IPC implementation (SC side). + */ +/*==========================================================================*/ + +#ifndef SC_IPC_SRV_H +#define SC_IPC_SRV_H + +/* Includes */ + +#include "main/main.h" +#include "main/rpc.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +sc_bool_t sc_ipc_pending(MU_Type *base); +sc_err_t sc_ipc_read_async(MU_Type *base, sc_rpc_async_msg_t *asyncMsg); +sc_err_t sc_ipc_write_async(MU_Type *base, sc_rpc_async_msg_t *asyncMsg); +sc_bool_t sc_ipc_handler(MU_Type *base, sc_rpc_async_msg_t *asyncMsg, + sc_rsrc_t mu); +void sc_ipc_reset(MU_Type *loc_mu, MU_Type *rem_mu, + sc_rpc_async_msg_t *asyncMsg); + +#endif /* SC_IPC_SRV_H */ + diff --git a/platform/main/main.h b/platform/main/main.h new file mode 100755 index 0000000..6101002 --- /dev/null +++ b/platform/main/main.h @@ -0,0 +1,427 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the system controller main. Contains defines, macros, + * and types shared by main and test implementations. + */ +/*==========================================================================*/ + +#ifndef SC_MAIN_H +#define SC_MAIN_H + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/ipc.h" +#include "main/rpc.h" +#include "board/board_common.h" +#include "config/config.h" +#include "main/debug.h" +#include "ss/inf/inf.h" + +/* Defines */ + +#define SC_NA 0U +#define SC_SW 0U + +#define SC_NUM_SS_GRP (SC_SS_GRP_LAST + 1U) +#define SC_NUM_RESOURCE (SC_R_LAST) +#define SC_NUM_SUBSYS ((sc_sub_t) (((uint8_t) SC_SUBSYS_LAST) + 1U)) +#define SC_NUM_DSC ((sc_dsc_t) (((uint8_t) SC_DSC_LAST) + 1U)) + +#define SC_MSIZE_W 5U +#define SC_MSLOT_W 2U +#define SC_MSLOT_SHF 30U +#define SC_SSLOT_W 6U +#define SC_SSLOT_SHF 28U +#define SC_SSPROT_W 2U + +#define NOP {} + +#ifndef SIMU + #define ENTER_CS SystemEnterCS() + #define EXIT_CS SystemExitCS() +#else + #define ENTER_CS NOP + #define EXIT_CS NOP +#endif + +#define DONT_TOUCH_RSRC 0U +#define LEAVE_RSRC_ON 1U +#define TURN_RSRC_OFF 2U +#define SET_RSRC_STBY 3U + +#define PLL_VER13 (13U) +#define PLL_VER18 (18U) + + +/*! Macro to get minimum */ +#if !defined(MIN) + #define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) + /*! Macro to get maximum */ + #define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +/*! Macro to get absolute value */ +#define ABS(X) ((X) < 0 ? -(X) : (X)) + +/*! Macro to create bit field */ +#define BIT(X) (U32(1U) << (U32(X) % U32(32U))) + +/*! Macro to return bit position */ +#define BIT_POS(X) (U32(X) % U32(32U)) + +/*! Macro to create bit field */ +#define BIT8(X) (U8(1U) << (U8(X) % U8(8U))) + +/*! Macro to create bit field */ +#define BIT16(X) (U16(1U) << (U16(X) % U16(16U))) + +/*! Macro to create bit field */ +#define BIT32(X) (U32(1U) << (U32(X) % U32(32U))) + +/*! Macro to create bit field */ +#define BIT64(X) (U64(1U) << (U64(X) % U64(64U))) + +/*! Macro to extract from field */ +#define MASK(X) ((U32(1U) << U32(X)) - U32(1U)) + +/*! Macro to extract from bit field */ +#define EX_BIT(X, Y) ((U32(X) >> (U32(Y) % 32U)) & U32(1U)) + +/*! Macro to extract from bool field */ +#define EX_BOOL(X, Y) (U2B32(EX_BIT((X), (Y)))) + +/*! Macro to extract from field */ +#define EX_FIELD(X, Y, Z) (((X) >> (U32(Y) % 32U)) & MASK(Z)) + +/*! Macro to create clear field */ +#define CLR_FIELD(X, Y) (MASK(Y) << (U32(X) % U32(32U))) + +/*! Macro to create field */ +#define INS_FIELD(X, Y, Z) ((U32(Z) & MASK(Y)) << (U32(X) % 32U)) + +/*! Macro to create register index */ +#define REG(X) (U32(X) / U32(32U)) + +/*! Macro to create 8-bit index from register and bit */ +#define REGBIT8(X, Y) ((U8(X) * U8(32U)) + (U8(Y) % 32U)) + +/*! Macro to create 32-bit index from register and bit */ +#define REGBIT(X, Y) ((U32(X) * U32(32U)) + (U32(Y) % 32U)) + +/*! Macro to create 64-bit index from register and bit */ +#define REGBIT64(X, Y) ((U64(X) * U64(32U)) + (U64(Y) % 32U)) + +/*! Macro to get upper 32 bits of a 64-bit value */ +#define UINT64_H(X) (U32((U64(X) >> 32U) & U64(0x0FFFFFFFFU))) + +/*! Macro to get lower 32 bits of a 64-bit value */ +#define UINT64_L(X) (U32(U64(X) & U64(0x0FFFFFFFFU))) + +/*! Macro to get upper 16 bits of a 32-bit value */ +#define UINT32_H(X) (U16((U32(X) >> 16U) & U32(0xFFFFU))) + +/*! Macro to get lower 16 bits of a 32-bit value */ +#define UINT32_L(X) (U16(U32(X) & U32(0xFFFFU))) + +/*! Macro to declare a bit array */ +#define BITARRAY_DEC(X, Y) uint32_t (X)[(((Y) - 1U) / 32U) + 1U] + +/*! Macro to set a bit in a bit array */ +#define BITARRAY_SET(X, Y) (X)[REG(Y)] |= BIT(Y) + +/*! Macro to clear a bit in a bit array */ +#define BITARRAY_CLR(X, Y) (X)[REG(Y)] &= ~BIT(Y) + +/*! Macro to get a bit in a bit array */ +#define BITARRAY_GET(X, Y) ((X)[REG(Y)] & BIT(Y)) + +#define ASRT(X) \ + if (!(X)) \ + { \ + return; \ + } + +#define ASRT_ERR(X,ERROR) \ + if (err == SC_ERR_NONE) \ + { \ + if (!(X)) \ + { \ + err = (ERROR); \ + } \ + } + +#define ASRT_C(X) \ + if (!(X)) \ + { \ + continue; \ + } + +#define FUNC_ERR(X) \ + if (err == SC_ERR_NONE) \ + { \ + err = (X); \ + } + +#ifdef SIMU +#define SIMU_ASRT(X, STR) \ + if (!(X)) \ + { \ + error_print("error: %s\n", STR);\ + board_exit(-1); \ + } +#else + #define SIMU_ASRT(X, STR) \ + NOP +#endif + +#define HALT \ + do \ + { \ + } \ + while(true) + +/*! + * @name Defines for memory sizes + */ +/** @{ */ +#define SC_4KB 0x1000UL /*!< 4KB */ +#define SC_64KB 0x10000UL /*!< 64KB */ +#define SC_128KB 0x20000UL /*!< 128KB */ +#define SC_256KB 0x40000UL /*!< 256KB */ +#define SC_1MB 0x100000UL /*!< 1MB */ +#define SC_16MB 0x1000000UL /*!< 16MB */ +#define SC_64MB 0x4000000UL /*!< 64MB */ +#define SC_256MB 0x10000000UL /*!< 256MB */ +#define SC_512MB 0x20000000UL /*!< 512MB */ +#define SC_1GB 0x40000000UL /*!< 1GB */ +#define SC_1P5GB 0x60000000UL /*!< 1.5GB */ +#define SC_2GB 0x80000000UL /*!< 2GB */ +#define SC_3GB 0xC0000000UL /*!< 3GB */ +#define SC_4GB 0x100000000ULL /*!< 4GB */ +#define SC_6GB 0x180000000ULL /*!< 6GB */ +#define SC_8GB 0x200000000ULL /*!< 8GB */ +#define SC_16GB 0x400000000ULL /*!< 16GB */ +/** @} */ + +/*! + * @name Parameter checking macros + */ +/** @{ */ +#define BOUND_PT(X) ASRT_ERR((X) < SC_RM_NUM_PARTITION, SC_ERR_PARM) +#define BOUND_RSRC(X,I) ASRT_ERR(rm_check_map_ridx((X), &(I)) != SC_FALSE, SC_ERR_PARM) +#define BOUND_RSRC_C(X,I) ASRT_C(rm_check_map_ridx((X), &(I)) != SC_FALSE) +#define BOUND_MR(X) ASRT_ERR((X) < SC_RM_NUM_MEMREG, SC_ERR_PARM) +#define BOUND_PAD(X) ASRT_ERR((X) < SC_NUM_PAD, SC_ERR_PARM) +#define BOUND_SS(X) ASRT_ERR((X) <= SC_SUBSYS_LAST, SC_ERR_PARM) +#define USED_PT(X) ASRT_ERR(rm_is_partition_used(X) != SC_FALSE, SC_ERR_PARM) +#define ANCESTOR(X) ASRT_ERR(rm_check_ancestor(caller_pt, (X)) != SC_FALSE, SC_ERR_NOACCESS) +#define ANCESTOR_C(X) ASRT_C(rm_check_ancestor(caller_pt, (X)) != SC_FALSE) +#define OWNED(X) ASRT_ERR(rm_is_resource_owned(caller_pt, (X)) != SC_FALSE, SC_ERR_NOACCESS) +#define OWNER(X,Y) ASRT_ERR(rm_is_resource_owned((X), (Y)) != SC_FALSE, SC_ERR_NOACCESS) +#define SYSTEM(X) ASRT_ERR(rm_is_sys_access(X) != SC_FALSE, SC_ERR_NOACCESS) +#define NOT_SC_PT(X) ASRT_ERR((X) != SC_PT, SC_ERR_NOACCESS) +#define MASTER(X) ASRT_ERR(rm_is_ridx_master(X) != SC_FALSE, SC_ERR_PARM) +#define MASTER_C(X) ASRT_C(rm_is_ridx_master(X) != SC_FALSE) +#define PERIPHERAL(X) ASRT_ERR(rm_is_ridx_peripheral(X) != SC_FALSE, SC_ERR_PARM) +#define PERIPHERAL_C(X) ASRT_C(rm_is_ridx_peripheral(X) != SC_FALSE) +#define ACCESS_ALLOWED(X,I) ASRT_ERR(rm_is_ridx_access_allowed((X), (I)) != SC_FALSE, SC_ERR_NOACCESS) +#define ACCESS_ALLOWED_C(X,I) ASRT_C(rm_is_ridx_access_allowed((X), (I)) != SC_FALSE) +/** @} */ + +/* Types */ + +/*! + * Boot init phase types. + */ +typedef enum +{ + BOOT_PHASE_SYS_INIT = 6, /*!< Init system (no HW access yet) */ + BOOT_PHASE_API_INIT = 0, /*!< Init API (no HW access yet) */ + BOOT_PHASE_HW_INIT = 1, /*!< Init HW (API can be used) */ + BOOT_PHASE_EARLY_INIT = 4, /*!< Pre-start early CPUs */ + BOOT_PHASE_LATE_INIT = 5, /*!< Pre-start late CPUs */ + BOOT_PHASE_FINAL_INIT = 2, /*!< All done */ + BOOT_PHASE_TEST_INIT = 3 /*!< Init HW required for unit tests */ +} boot_phase_t; + +typedef uint8_t sc_msize_t; +typedef uint8_t sc_mslot_t; +typedef uint8_t sc_sslot_t; + +typedef const char * const strings[]; + +typedef union +{ + int8_t with_sign; + uint8_t no_sign; +} cint8_t; + +typedef union +{ + int16_t with_sign; + uint16_t no_sign; +} cint16_t; + +typedef union +{ + int32_t with_sign; + uint32_t no_sign; +} cint32_t; + +typedef union +{ + int64_t with_sign; + uint64_t no_sign; +} cint64_t; + +/*! + * This type is used to declare constant subsystem information. + */ +typedef struct +{ + uint8_t present : SC_BOOL_W; //!< 1 if SS present + sc_ss_inst_t inst : SC_SS_INST_W; //!< Instance number + sc_sub_t db_ssi : SC_PGP_W; //!< DB SSI this subsystem uses + sc_sub_t parent : SC_SUBSYS_W; //!< Parent SS if this is a sub-SS + sc_rm_idx_t r_ofs : SC_RM_IDX_W; //!< Offset into parent's resources + sc_rm_idx_t r2_ofs : SC_RM_IDX_W; //!< Second offset into parent's resources + sc_dsc_t dsc : SC_DSC_W; //!< Primary DSC this subsystem uses +} sc_ss_info_t; + +/*! + * This type is used to declare constant memmap information. The + * address range is the top-level memory map as seen by the AP cores. + */ +typedef struct +{ + sc_faddr_t start; //!< Start of subsystem address range + sc_faddr_t len; //!< Length of of subsystem address range + uint8_t mem : SC_BOOL_W; //!< Contains memory + uint8_t ss_prot : SC_SSPROT_W; //!< Protection 0=DB, 1=SS, 2=none + sc_msize_t size : SC_MSIZE_W; //!< ZADDR size + sc_mslot_t slot : SC_MSLOT_W; //!< ZADDR slot + sc_sslot_t subslot : SC_SSLOT_W; //!< ZADDR subslot + sc_sub_t ss : SC_SUBSYS_W; //!< Associated subsystem +} sc_memmap_t; + +/*! + * This type is used to declare constant DB information. + */ +typedef struct +{ + sc_rsrc_t rsrc : SC_RSRC_W; //!< DB resource + sc_sub_t ss : SC_SUBSYS_W; //!< DB subsystem + sc_db_connect_t connect; //!< DB connections +} sc_db_list_t; + +/*! + * This type declares all the memory areas that can be used for boot. + */ + typedef struct +{ + sc_faddr_t start; //!< Start of memory address range + sc_faddr_t len; //!< End of memory address range + sc_rsrc_t rsrc : SC_RSRC_W; //!< Resource associated with memory. + sc_sub_t ss : SC_SUBSYS_W; //!< Subsystem associated with resource. +}sc_boot_mem_t; + +/* Functions */ + +void main_banners(void); +sc_err_t main_drv_test(void); +void main_init(void); +sc_err_t main_sc_test(void); +void main_config(sc_rm_pt_t *pt_boot, sc_bool_t *early); +sc_err_t main_ddr(sc_bool_t early); +uint32_t main_dcd(void); +void main_prep_cpu(sc_rsrc_t boot_cpu, sc_rsrc_t boot_mu); +void main_dump(void); +#if defined(DEBUG) && !defined(SIMU) + /*! + * This function configures the specified UART to be used for debug output. + * + * @param[in] base base of the UART to configure + * @param[in] rate rate of the source clock to the UART + * + * Calls board_get_debug_uart() to get the instance number and the baud + * rate. If that returns 0 then will do nothing. Does not configure the pads + * power state, or clock source. Sets SCFW_DBG_READY to 1U. + */ + void main_config_debug_uart(LPUART_Type *base, uint32_t rate); +#endif +void main_pll_debug(void); +sc_err_t main_get_mem_ss(sc_faddr_t start_addr, uint32_t *ss); +#ifdef TEST_BOOTTIME +void test_save_time(uint32_t bootTicksRom, uint32_t bootTicksBanner, + uint32_t bootTicksEarly); +#endif + +/* Externs */ + +extern sc_bool_t rom_loaded; +extern const sc_db_list_t sc_db_info[SC_NUM_DB]; +#ifdef DEBUG + extern const char * const rnames[SC_NUM_RSRC]; + extern const char * const pnames[SC_NUM_PAD]; + extern const char * const snames[SC_SUBSYS_LAST + 1U]; +#endif +extern const sc_ss_info_t sc_ss_info[SC_SUBSYS_LAST + 1U]; +extern const sc_memmap_t sc_memmap[]; +extern const ss_base_info_t * const ss_base_info[SC_SUBSYS_LAST + 1U]; +extern volatile sc_bool_t rpc_debug; +extern sc_rm_idx_t rom_boot_rsrc[SC_NUM_RSRC]; +extern const sc_boot_mem_t rom_boot_addr[]; + +#ifdef DEBUG +char term_emul_getc(void); +void term_emul_putc(char c); +#endif + +#ifdef NO_DEVICE_ACCESS + extern uint32_t temp_fuses[16 * 1024]; +#endif + +#endif /* SC_MAIN_H */ + diff --git a/platform/main/monitor.h b/platform/main/monitor.h new file mode 100755 index 0000000..9fa7429 --- /dev/null +++ b/platform/main/monitor.h @@ -0,0 +1,64 @@ +/* +** ################################################################### +** +** Copyright 2017-2018 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the SCFW debug monitor. + */ +/*==========================================================================*/ + +#ifndef SC_MONITOR_H +#define SC_MONITOR_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +#ifdef MONITOR + void monitor(void); + sc_err_t monitor_update_line_and_dispatch(char *my_string); +#endif + +/* External variables */ + +#endif /* SC_MONITOR_H */ + diff --git a/platform/main/prof.h b/platform/main/prof.h new file mode 100755 index 0000000..b8890bc --- /dev/null +++ b/platform/main/prof.h @@ -0,0 +1,188 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the profiler implementation. + */ +/*==========================================================================*/ + +#ifndef SC_PROF_H +#define SC_PROF_H + +/* Includes */ + +#ifdef SIMU + #include + typedef struct timespec sc_prof_time_t; +#else + #include "drivers/sysctr/fsl_sysctr.h" + #include "drivers/systick/fsl_systick.h" + typedef uint32_t sc_prof_time_t; +#endif + +/*--------------------------------------------------------------------------*/ +/* Time Duration Profiling Macros */ +/*--------------------------------------------------------------------------*/ + +#ifdef SIMU +#define SC_PTIM_DECLARE(context) sc_prof_time_t context ## startTime; \ + sc_prof_time_t context ## endTime; \ + const char *context ## fileName; \ + uint32_t context ## lineNum + +#define SC_PTIM_EXTERN(context) extern sc_prof_time_t context ## startTime; \ + extern sc_prof_time_t context ## endTime; \ + extern const char *context ## fileName; \ + extern uint32_t context ## lineNum +#else +#define SC_PTIM_DECLARE(context) sc_prof_time_t context ## startTime; \ + sc_prof_time_t context ## endTime; \ + sc_prof_time_t context ## HPstartTime; \ + sc_prof_time_t context ## HPendTime; \ + const char *context ## fileName; \ + uint32_t context ## lineNum + +#define SC_PTIM_EXTERN(context) extern sc_prof_time_t context ## startTime; \ + extern sc_prof_time_t context ## endTime; \ + extern sc_prof_time_t context ## HPstartTime; \ + extern sc_prof_time_t context ## HPendTime; \ + extern const char *context ## fileName; \ + extern uint32_t context ## lineNum +#endif // SIMU + + +#define SC_PTIM_SETREF(context, file, line) context ## lineNum = line; \ + context ## fileName = file + +#define SC_PTIM_CLRREF(context) SC_PTIM_SETREF(context, NULL, 0) + +#define SC_PTIM_FILEREF(context) context ## fileName == NULL ? __FILE__ : context ## fileName +#define SC_PTIM_LINEREF(context) context ## fileName == NULL ? __LINE__ : context ## lineNum + +#ifdef SIMU +#define SC_PTIM_GET_TIME(context, timeVar) clock_gettime(CLOCK_PROCESS_CPUTIME_ID, &(context ## timeVar)) +#define SC_PTIM_TIME_DIFF(context) ((uint32_t)((context ## endTime.tv_nsec - context ## startTime.tv_nsec))) +#define SC_PTIM_HP_GET_TIME(context, timeVar) SC_PTIM_GET_TIME(context, timeVar) +#define SC_PTIM_HP_TIME_DIFF(context) SC_PTIM_TIME_DIFF(context) +#else +#define SC_PTIM_GET_TIME(context, timeVar) context ## timeVar = SYSCTR_GetCounter32() +#define SC_PTIM_TIME_DIFF(context) (SYSCTR_TICKS_TO_USEC(context ## endTime - context ## startTime) * 1000) +#define SC_PTIM_HP_GET_TIME(context, timeVar) context ## HP ## timeVar = SysTick->VAL; +#define SC_PTIM_HP_TIME_DIFF(context) SYSTICK_NsecDiff(context ## HP ## startTime, context ## HP ## endTime, 3750) +#endif // SIMU + +#define SC_PTIM_BEGIN(context) SC_PTIM_GET_TIME(context, startTime) +#define SC_PTIM_END(context) SC_PTIM_GET_TIME(context, endTime) +#define SC_PTIM_REPORT(context) debug_print(1, "PROF: time = %u ns (%s:%d)\n", \ + SC_PTIM_TIME_DIFF(context), \ + SC_PTIM_FILEREF(context), \ + SC_PTIM_LINEREF(context)) + +#define SC_PTIM_REPORT_N(context, n) debug_print(1, "PROF: n = %u, time / iter = %u ns (%s:%d)\n", \ + n, \ + SC_PTIM_TIME_DIFF(context) / n, \ + SC_PTIM_FILEREF(context), \ + SC_PTIM_LINEREF(context)) + +#define SC_PTIM_REPORT_GE_THRESH(context, nsec) if (SC_PTIM_TIME_DIFF(context) >= nsec) SC_PTIM_REPORT(context) + +#define SC_PTIM_HP_BEGIN(context) SC_PTIM_HP_GET_TIME(context, startTime) +#define SC_PTIM_HP_END(context) SC_PTIM_HP_GET_TIME(context, endTime) +#define SC_PTIM_HP_REPORT(context) debug_print(1, "PROF: time = %u ns (%s:%d)\n", \ + SC_PTIM_HP_TIME_DIFF(context), \ + SC_PTIM_FILEREF(context), \ + SC_PTIM_LINEREF(context)) + +#define SC_PTIM_HP_REPORT_N(context, n) debug_print(1, "PTIM: n = %u, time / iter = %u ns (%s:%d)\n", \ + n, \ + SC_PTIM_HP_TIME_DIFF(context) / n, \ + SC_PTIM_FILEREF(context), \ + SC_PTIM_LINEREF(context)) + +#define SC_PTIM_HP_REPORT_GE_THRESH(context, nsec) if (SC_PTIM_HP_TIME_DIFF(context) >= nsec) SC_PTIM_HP_REPORT(context) + +/*--------------------------------------------------------------------------*/ +/* Access Count Profiling Macros */ +/*--------------------------------------------------------------------------*/ + +#define SC_PCNT_DECLARE() uint32_t dscCountR; \ + uint32_t dscCountW; \ + uint32_t csrCountR; \ + uint32_t csrCountW; \ + uint32_t xrdcCountR; \ + uint32_t xrdcCountW; + +#define SC_PCNT_EXTERN() extern uint32_t dscCountR; \ + extern uint32_t dscCountW; \ + extern uint32_t csrCountR; \ + extern uint32_t csrCountW; \ + extern uint32_t xrdcCountR; \ + extern uint32_t xrdcCountW; + +#ifdef HAS_TEST_PCNT +#define SC_PCNT_BEGIN() dscCountR = 0; \ + dscCountW = 0; \ + csrCountR = 0; \ + csrCountW = 0; \ + xrdcCountR = 0; \ + xrdcCountW = 0; +#else +#define SC_PCNT_BEGIN() ; +#endif + +#define SC_PCNT_DSC_R(X) dscCountR += (X) +#define SC_PCNT_DSC_W(X) dscCountW += (X) +#define SC_PCNT_DSC_RW(X) dscCountR += (X); \ + dscCountW += (X); +#define SC_PCNT_CSR_R(X) csrCountR += (X) +#define SC_PCNT_CSR_W(X) csrCountW += (X) +#define SC_PCNT_CSR_RW(X) csrCountR += (X); \ + csrCountW += (X); +#define SC_PCNT_XRDC_R(X) xrdcCountR += (X) +#define SC_PCNT_XRDC_W(X) xrdcCountW += (X) + +#ifdef HAS_TEST_PCNT +#define SC_PCNT_REPORT(X) debug_print(1, "%s PCNT(R/W): dsc=%u/%u, csr=%u/%u, xrdc=%u/%u\n", \ + X, dscCountR, dscCountW, csrCountR, csrCountW, xrdcCountR, \ + xrdcCountW) +#else +#define SC_PCNT_REPORT(X) ; +#endif + +#endif /* SC_PROF_H */ + diff --git a/platform/main/rpc.h b/platform/main/rpc.h new file mode 100755 index 0000000..b20f513 --- /dev/null +++ b/platform/main/rpc.h @@ -0,0 +1,212 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the RPC implementation. + */ +/*==========================================================================*/ + +#ifndef SC_RPC_H +#define SC_RPC_H + +/* Includes */ + +#include "main/types.h" +#include "main/ipc.h" + +/* Defines */ + +/*! + * @name SCFW API version + */ +/** @{ */ +#define SCFW_API_VERSION_MAJOR 1U +#define SCFW_API_VERSION_MINOR 26U +/** @} */ + +/*! RPC version */ +#define SC_RPC_VERSION 1U + +/*! + * @name Defines for service types + */ +/** @{ */ +#define SC_RPC_SVC_UNKNOWN 0U +#define SC_RPC_SVC_RETURN 1U +#define SC_RPC_SVC_PM 2U +#define SC_RPC_SVC_RM 3U +#define SC_RPC_SVC_TIMER 5U +#define SC_RPC_SVC_PAD 6U +#define SC_RPC_SVC_MISC 7U +#define SC_RPC_SVC_IRQ 8U +#define SC_RPC_SVC_SECO 9U +#define SC_RPC_SVC_ABORT 10U +/** @} */ + +/* Internal Defines */ + +#define SC_RPC_MAX_MSG 8U + +#define RPC_VER(MESG) ((MESG)->version) +#define RPC_SIZE(MESG) ((MESG)->size) +#define RPC_SVC(MESG) ((MESG)->svc) +#define RPC_FUNC(MESG) ((MESG)->func) +#define RPC_R8(MESG) ((MESG)->func) +#define RPC_I64(MESG, IDX) ((I64(RPC_U32((MESG), (IDX))) << 32ULL) \ + | I64(RPC_U32((MESG), (IDX) + 4U))) +#define RPC_I32(MESG, IDX) ((MESG)->DATA.i32[(IDX) / 4U]) +#define RPC_I16(MESG, IDX) ((MESG)->DATA.i16[(IDX) / 2U]) +#define RPC_I8(MESG, IDX) ((MESG)->DATA.i8[(IDX)]) +#define RPC_U64(MESG, IDX) ((U64(RPC_U32((MESG), (IDX))) << 32ULL) \ + | U64(RPC_U32((MESG), (IDX) + 4U))) +#define RPC_U32(MESG, IDX) ((MESG)->DATA.u32[(IDX) / 4U]) +#define RPC_U16(MESG, IDX) ((MESG)->DATA.u16[(IDX) / 2U]) +#define RPC_U8(MESG, IDX) ((MESG)->DATA.u8[(IDX)]) + +#define SC_RPC_ASYNC_STATE_RD_START 0U +#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U +#define SC_RPC_ASYNC_STATE_RD_DONE 2U +#define SC_RPC_ASYNC_STATE_WR_START 3U +#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U +#define SC_RPC_ASYNC_STATE_WR_DONE 5U + +/* SC -> Client general-purpose MU IRQs */ +#define SC_RPC_MU_GIR_SVC 0x1U +#define SC_RPC_MU_GIR_WAKE 0x2U +#define SC_RPC_MU_GIR_BOOT 0x4U +#define SC_RPC_MU_GIR_DBG 0x8U + +/* Client -> SC general-purpose MU IRQs */ +#define SC_RPC_MU_GIR_RST 0x1U + +#define I8(X) ((int8_t) (X)) +#define I16(X) ((int16_t) (X)) +#define I32(X) ((int32_t) (X)) +#define I64(X) ((int64_t) (X)) +#define U8(X) ((uint8_t) (X)) +#define U16(X) ((uint16_t) (X)) +#define U32(X) ((uint32_t) (X)) +#define U64(X) ((uint64_t) (X)) + +#define PTR_I8(X) ((int8_t *) (X)) +#define PTR_I16(X) ((int16_t *) (X)) +#define PTR_I32(X) ((int32_t *) (X)) +#define PTR_I64(X) ((int64_t *) (X)) +#define PTR_U8(X) ((uint8_t *) (X)) +#define PTR_U16(X) ((uint16_t *) (X)) +#define PTR_U32(X) ((uint32_t *) (X)) +#define PTR_U64(X) ((uint64_t *) (X)) + +#define U2B(X) (((X) != 0U) ? SC_TRUE : SC_FALSE) +#define U2B32(X) (((X) != 0UL) ? SC_TRUE : SC_FALSE) +#define B2U8(X) (((X) != SC_FALSE) ? U8(0x01U) : U8(0x00U)) +#define B2U16(X) (((X) != SC_FALSE) ? U16(0x01U) : U16(0x00U)) +#define B2U32(X) (((X) != SC_FALSE) ? U32(0x01U) : U32(0x00U)) + +/* Types */ + +typedef struct +{ + uint8_t version; + uint8_t size; + uint8_t svc; + uint8_t func; + union + { + int32_t i32[(SC_RPC_MAX_MSG - 1U)]; + int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U]; + int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U]; + uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; + uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U]; + uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U]; + } DATA; +} sc_rpc_msg_t; + +typedef uint8_t sc_rpc_async_state_t; + +typedef struct +{ + sc_rpc_async_state_t state; + uint8_t wordIdx; + sc_rpc_msg_t msg; + uint32_t timeStamp; +} sc_rpc_async_msg_t; + +/* Functions */ + +/*! + * This is an internal function to send an RPC message over an IPC + * channel. It is called by client-side SCFW API function shims. + * + * @param[in] ipc IPC handle + * @param[in,out] msg handle to a message + * @param[in] no_resp response flag + * + * If \a no_resp is SC_FALSE then this function waits for a response + * and returns the result in \a msg. + */ +void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp); + +/*! + * This is an internal function to dispath an RPC call that has + * arrived via IPC over an MU. It is called by server-side SCFW. + * + * @param[in] mu MU message arrived on + * @param[in,out] msg handle to a message + * + * The function result is returned in \a msg. + */ +void sc_rpc_dispatch(sc_rsrc_t mu, sc_rpc_msg_t *msg); + +/*! + * This function translates an RPC message and forwards on to the + * normal RPC API. It is used only by hypervisors. + * + * @param[in] ipc IPC handle + * @param[in,out] msg handle to a message + * + * This function decodes a message, calls macros to translate the + * resources, pads, addresses, partitions, memory regions, etc. and + * then forwards on to the hypervisors SCFW API.Return results are + * translated back abd placed back into the message to be returned + * to the original API. + */ +void sc_rpc_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg); + +#endif /* SC_RPC_H */ + diff --git a/platform/main/scfw.h b/platform/main/scfw.h new file mode 100755 index 0000000..76cdf9c --- /dev/null +++ b/platform/main/scfw.h @@ -0,0 +1,73 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing includes to system headers and porting types. + */ +/*==========================================================================*/ + +#ifndef SC_SCFW_H +#define SC_SCFW_H + +/* Includes */ + +#include +#include +#include +#include +#include +#if defined(DEBUG) || defined(GCOV) + #include +#endif + +/* Types */ + +/*! + * This type is used to declare a handle for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint32_t sc_ipc_t; + +/*! + * This type is used to declare an ID for an IPC communication + * channel. Its meaning is specific to the IPC implementation. + */ +typedef uint32_t sc_ipc_id_t; + +#endif /* SC_SCFW_H */ + diff --git a/platform/main/sched.h b/platform/main/sched.h new file mode 100755 index 0000000..5c79426 --- /dev/null +++ b/platform/main/sched.h @@ -0,0 +1,89 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the SCHED implementation. + */ +/*==========================================================================*/ + +#ifndef SC_SCHED_H +#define SC_SCHED_H + +/* Includes */ + +#include "fsl_device_registers.h" + +/* Defines */ + +#define SC_SCHED_NUM_PRIO_LEV BIT(__NVIC_PRIO_BITS) +#define SC_SCHED_PRIO_WRAP_TO_DEFAULT SC_SCHED_PRIO_NOPREEMPT_LOW + +// Priority grouping (PRIGROUP) configured as follows: +// 1-bit group priority field +// 3-bit subgroup priority field +// +// Note: actual bits of priority fields are MSB of fields as defined +// by __NVIC_PRIO_BITS +// +#define SC_SCHED_PRIGROUP (6U) + +/* Types */ +typedef enum +{ + SC_SCHED_PRIO_PREEMPT_CRITICAL = 0, // Highest premptive + SC_SCHED_PRIO_PREEMPT_VERY_HIGH = 1, + SC_SCHED_PRIO_PREEMPT_HIGH = 2, + SC_SCHED_PRIO_PREEMPT_ABOVE_NORMAL = 3, + SC_SCHED_PRIO_PREEMPT_NORMAL = 4, + SC_SCHED_PRIO_PREEMPT_BELOW_NORMAL = 5, + SC_SCHED_PRIO_PREEMPT_LOW = 6, + SC_SCHED_PRIO_PREEMPT_VERY_LOW = 7, // Lowest premptive + + SC_SCHED_PRIO_NOPREEMPT_CRITICAL = 8, // Highest non-premptive + SC_SCHED_PRIO_NOPREEMPT_VERY_HIGH = 9, + SC_SCHED_PRIO_NOPREEMPT_HIGH = 10, + SC_SCHED_PRIO_NOPREEMPT_ABOVE_NORMAL = 11, + SC_SCHED_PRIO_NOPREEMPT_NORMAL = 12, + SC_SCHED_PRIO_NOPREEMPT_BELOW_NORMAL = 13, + SC_SCHED_PRIO_NOPREEMPT_LOW = 14, + SC_SCHED_PRIO_NOPREEMPT_VERY_LOW = 15, // Lowest non-premptive + +} sc_sched_prio_t; + +#endif /* SC_SCHED_H */ + diff --git a/platform/main/simu.h b/platform/main/simu.h new file mode 100755 index 0000000..a10470b --- /dev/null +++ b/platform/main/simu.h @@ -0,0 +1,72 @@ +/* +** ################################################################### +** +** Copyright 2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the SIMU functions. + */ +/*==========================================================================*/ + +#ifndef SC_SIMU_H +#define SC_SIMU_H + +/* Includes */ + +#include "main/types.h" +#include "main/boot.h" +#include "main/board.h" +#include "main/simu.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +void main_simu_init(int argc, char * const argv[]); +void main_simu_load_fuses(void); +sc_bool_t main_simu_fuses_loaded(void); +const sc_boot_data_t *main_simu_rom_load_bd( + const sc_boot_data_t *boot_data); +const sc_boot_data2_t * main_simu_rom_load_bd2( + const sc_boot_data2_t *boot_data2); +const sc_passover_t * main_simu_rom_load_po( + const sc_passover_t *passover_data); +void main_simu_load_board(void); +board_parm_rtn_t main_board_parameter(board_parm_t parm); + +#endif /* SC_SIMU_H */ + diff --git a/platform/main/soc.h b/platform/main/soc.h new file mode 100755 index 0000000..1e4e779 --- /dev/null +++ b/platform/main/soc.h @@ -0,0 +1,1265 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the SoC API. This abstracts SoC-specific + * functionality such as init, info, analog, power, HPM, and DDR. + * + * @addtogroup SOC SOC: SoC Interface + * + * Module for the SoC Interface. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SOC_API_H +#define SC_SOC_API_H + +/* Includes */ + +#include "main/board.h" + +/*! Macro to configure an STC category */ +#define STC_RCAT_SETCAT(SS, CAT, CATMASK, CMP) \ + STC_RCAT_SetCategorization(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi], \ + CAT, CATMASK, CMP) + +/*! Macro to set an STC TDM */ +#define STC_RCAT_SETSTARTSTOPTDM(SS, CAT, TDM, START, STOP) \ + STC_RCAT_SetStartStopTDM(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi], \ + CAT, TDM, START, STOP) + +/*! Macro to get an STC HPR */ +#define STC_RCAT_GETHPR(SS, CAT) \ + STC_RCAT_GetHPR(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi], CAT) + +/*! Macro to set an STC HPR */ +#define STC_RCAT_SETHPR(SS, CAT, HPR) \ + STC_RCAT_SetHPR(base_ptrs[sc_ss_info[ \ + SC_SUBSYS_##SS].db_ssi], CAT, HPR) + +/*! Macro to set an STC QoS panic */ +#define STC_QOS_PANIC(SS, CAT, QOS) \ + STC_QOS_Panic(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi], \ + CAT, QOS) + +/*! Macro to set an STC threshold */ +#define STC_UD_THRESHOLD1(SS, CAT, TH, QOS) \ + STC_UD_EnableThreshold1(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi], \ + CAT, TH, QOS) + +/*! Macro to set an STC threshold 2 */ +#define STC_UD_THRESHOLD2(SS, CAT, TH, QOS) \ + STC_UD_EnableThreshold2(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi], \ + CAT, TH, QOS) + +/*! Macro to disable an STC underrun detect */ +#define STC_UD_DIS(SS) \ + STC_UD_DisableAll(base_ptrs[ \ + sc_ss_info[SC_SUBSYS_##SS].db_ssi]) + +/* Indicator for system interface resources to manage power + * mode directly (i.e. no save/restore). + */ +#define SOC_SYS_IF_NO_SAVE (SC_PM_PW_MODE_ON + 1U) + +/*! Reset reason SNVS persistant storage register */ +#define SOC_RR 1U + +/*! Macro to check if reset reason is valid */ +#define SOC_RR_CHECK(X) ((((X) >> 24U) & 0xFFUL) == 0xCCUL) + +/*! Macro to set the reset reason */ +#define SOC_RR_INFO(R, P) ((0xCCUL << 24U) | (U32(R) << 8U) | U32(P)) + +/*! Macro to extract the reset reason */ +#define SOC_RR_REASON(X) (((X) >> 8U) & 0xFFUL) + +/*! Macro to extract the resetting partition */ +#define SOC_RR_PT(X) (((X) >> 0U) & 0xFFUL) + +/*! + * @name Defines for patch ID + */ +/** @{ */ +#define SC_PATCH_ID_NONE 0x00U /* Non patch - end marker */ +#define SC_PATCH_ID_SCU 0x55U /* SCU ROM patch */ +#define SC_PATCH_ID_SECO 0x45U /* SECO ROM patch */ +#define SC_PATCH_ID_V2X 0x57U /* V2X primary ROM patch */ +#define SC_PATCH_ID_V2X2 0x59U /* V2X secondary ROM patch */ +#define SC_PATCH_ID_C2XS 0x5AU /* V2X ROM patch SHA value */ +#define SC_PATCH_ID_CTRL 0x5BU /* Patch control */ +#define SC_PATCH_ID_ALL 0xFFU /* All patch IDs */ +/** @} */ + +typedef struct +{ + const uint16_t offset; + const uint16_t len; +} soc_patch_area_list_t; + +typedef struct +{ + uint32_t freq; + uint32_t volt; + uint8_t bias; +} soc_freq_volt_tbl_t; + +typedef struct +{ + uint32_t shader_clk; + uint32_t core_clk; + uint32_t ahb_clk; + uint32_t axi_ssi_clk; +} soc_gpu_clks_opp_t; + +/*! + * Stores CPU power state info + */ +typedef struct +{ + sc_rm_idx_t rm_idx; + sc_pm_power_mode_t req_mode; + sc_bool_t lpm_active; + sc_bool_t rst_req; + sc_bool_t early_wake; + uint8_t wake_idx; + sc_pm_wake_src_t wake_src; + sc_faddr_t resume_addr; +} soc_cpu_state_t; + +/*! + * Stores cluster power state info + */ +typedef struct +{ + sc_rm_idx_t rm_idx; + uint8_t num_cpu; + soc_cpu_state_t *cpu_state; + sc_pm_power_mode_t req_mode; +} soc_cluster_state_t; + +/*! + * Stores multi-cluster power state info + */ +typedef struct +{ + sc_rm_idx_t rm_idx; + soc_cluster_state_t *cluster_state; + sc_pm_power_mode_t req_mode; +} soc_multicluster_state_t; + +/*! + * Stores MCU sleep state info + */ +typedef struct +{ + sc_rm_idx_t wic_rm_idx; + sc_rm_idx_t sc_mu_rm_idx; + sc_bool_t dsm_req; + sc_bool_t dsm_active; + sc_bool_t rst_req; + uint8_t stopm; + uint8_t pstopo; + sc_faddr_t resume_addr; +} soc_mcu_state_t; + +/*! + * Stores auxiliary core power state info + */ +typedef struct +{ + sc_bool_t active; + sc_bool_t fw_loading; + sc_saddr_t fw_addr; + sc_pm_sys_if_t fw_sys_if; +} soc_aux_state_t; + +/*! + * Stores system interface node resource info + */ +typedef struct +{ + sc_rm_idx_t num_rm_idx; /*!< Number of resources in the node */ + const sc_rsrc_t *rsrc; /*!< Resource array for node */ + sc_rm_idx_t *rm_idx; /*!< Resource index array for node */ + sc_pm_power_mode_t *saved_pm; /*!< Saved power mode array for node */ +} soc_sys_if_node_t; + +/*! + * Stores system interface power mode reqest info + */ +typedef struct +{ + sc_pm_power_mode_t hpm; /*!< High-power mode for system interface */ + sc_pm_power_mode_t lpm; /*!< Low-power mode for system interface */ +} soc_sys_if_req_t; + +/*! + * Stores HMP node power mode info + */ +typedef struct +{ + sc_rm_idx_t rm_idx; + soc_sys_if_req_t *sys_if_req; /*!< System interface mode request array */ +} soc_hmp_node_t; + +/*! + * Stores HMP FSPI retention info + */ +typedef struct +{ + sc_pm_power_mode_t pm; /*!< FSPI power mode to restore */ + uint32_t clk_rate; /*!< FSPI clock rate to restore */ +} soc_fspi_ret_info_t; + +/*! + * Stores HMP system power mode info + */ +typedef struct +{ + uint8_t num_hmp; /*!< Number of HMP nodes */ + soc_hmp_node_t *hmp_node; /*!< HMP node array */ + uint8_t num_sys_if; /*!< Number of system interace nodes */ + soc_sys_if_node_t *sys_if_node; /*!< System interface node array */ + sc_bool_t sys_if_mgmt; /*!< System interface managment flag */ + sc_rm_idx_t ap_gic_rm_idx; /*!< AP GIC resource index */ + sc_rm_idx_t ap_irqstr_rm_idx; /*!< AP IRQSTR resource index */ + uint8_t ap_resume_cluster_idx; /*!< AP resume cluster index */ + uint8_t ap_resume_cpu_idx; /*!< AP resume cpu index */ + sc_pm_power_mode_t ocmem_mode; /*!< On-chip memory mode for SoC */ + soc_fspi_ret_info_t fspi_ret_info; /*!< FSPI retention info */ + sc_pm_power_mode_t ddr_mode; /*!< DDR mode for SoC */ + sc_bool_t ddr_active; /*!< DDR active (initialized) boolean */ + sc_bool_t lpm_active; /*!< LPM active boolean */ +} soc_hmp_t; + +/* + * Stores DDR retention region info + */ +typedef struct +{ + const uint32_t addr; /*!< Address of DDR region to be retained */ + const uint32_t size; /*!< Size of DDR region to be retained */ + uint32_t * const buf; /*!< Pointer to SCFW buffer for DDR retention */ +} soc_ddr_ret_region_t; + +/*! + * Stores DDR retention info + */ +typedef struct +{ + const uint32_t num_drc; /*!< Number of DRCs to retain */ + ddrc * const drc_inst; /*!< Buffer for DRC register retention */ + ddr_phy * const drc_phy_inst; /*!< Buffer for DRC PHY register retention */ + const uint32_t num_region; /*!< Number of DDR retention regions */ + const soc_ddr_ret_region_t * const region; /*!< Retention region array */ + uint32_t drc0_clk_rate; /*!< Clock rate to restore after retention */ +#if HAS_SS_DRC_1 + uint32_t drc1_clk_rate; /*!< Clock rate to restore after retention */ +#endif +} soc_ddr_ret_info_t; + + +#ifdef SWI_DQS2DQ_IRQn +/*! + * Stores DQS2DQ synchronization info + */ +typedef struct +{ + const sc_rsrc_t isi_rsrc; /*!< ISI channel used for sync */ + ISI_Type * const isi_regs; /*!< ISI peripheral registers */ + uint32_t timeout_usec; /*!< Sync search timeout */ +} soc_dqs2dq_sync_info_t; +#endif + +/*! + * Stores MSI ring usecount + */ +typedef struct +{ + const sc_rsrc_t rsrc; + uint16_t count; + uint16_t ss_count; +} soc_msi_ring_usecount_t; + +#ifndef NO_DEVICE_ACCESS +// Define to enable self-hosted debug +#if 0 +#define SOC_SELFHOSTED_DEBUG +#endif +#endif + +#ifdef SOC_SELFHOSTED_DEBUG +#define LAR_OFFSET (0xFB0U) +#define LAR_KEY (0xC5ACCE55U) + +#define DBGDTRRX_OFFSET (0x080U) +#define EDITR_OFFSET (0x084U) +#define EDSCR_OFFSET (0x088U) +#define DBGDTRTX_OFFSET (0x08CU) +#define EDPRSR_OFFSET (0x314U) + +#define CTICONTROL_OFFSET (0x000U) +#define CTIAPPPULSE_OFFSET (0x01CU) +#define CTIOUTEN0_OFFSET (0x0A0U) + +#define MSR_OP_CODE(op0, op1, CRn, CRm, op2, Rt) \ + (0xD5000000U | (op0 << 19U) | (op1 << 16U) | \ + (CRn << 12U) | (CRm << 8U) | (op2 << 5U) | (Rt << 0U)) + +#define MRS_OP_CODE(op0, op1, CRn, CRm, op2, Rt) \ + (0xD5200000U | (op0 << 19U) | (op1 << 16U) | \ + (CRn << 12U) | (CRm << 8U) | (op2 << 5U) | (Rt << 0U)) + +#define SYS_OP_CODE(op1, CRn, CRm, op2, Rt) \ + (0xD5000000U | (0x1U << 19U) | (op1 << 16U) | \ + (CRn << 12U) | (CRm << 8U) | (op2 << 5U) | (Rt << 0U)) + +typedef struct +{ + const uint32_t dbg_base; + const uint32_t cti_base; +} soc_dbgapb_cpu_info_t; + +typedef struct +{ + const uint8_t num_way; // Number of ways + const uint16_t num_set; // Number of sets + const uint8_t way_shift; // Shift for way encoding + const uint8_t set_shift; // Shift for set encoding + const uint8_t ofs_shift; // Shift for cache offset encoding + const uint8_t data_ramid; // L1 data RAM identifier + const uint8_t tag_ramid; // L1 tag RAM identifier + const uint32_t CDBGDR0; // Data register 0 + const uint32_t CDBGDR1; // Data register 1 + const uint32_t CDBGxCT; // D-Cache tag read operation + const uint32_t CDBGxCD; // D-Cache data read operation +} soc_dbgapb_cache_info_t; + +typedef struct +{ + const uint8_t num_cpu; // Number of CPUs in cluster + const sc_rsrc_t cpu0_rsrc; // First CPU resource + soc_dbgapb_cache_info_t const *dc_info; // D-cache info + soc_dbgapb_cache_info_t const *ic_info; // I-cache info +} soc_dbgapb_cluster_info_t; + +#endif + +/* External variables */ + +/*! Global variable to hold resetting partition */ +extern sc_rm_pt_t soc_reset_pt; + +/*! Global variable to hold reset reason */ +extern sc_pm_reset_reason_t soc_reset_rsn; + +/* ! Global variable to hold the dco-pc values for table 0 */ +extern uint32_t soc_dpll_tbl_0[]; + +/* ! Global variable to hold the dco-pc values for table 1 */ +extern uint32_t soc_dpll_tbl_1[]; + +/*!Global variable to store the state of clocks during power transition */ +extern sc_bool_t soc_clk_off_trans; + +/*! Global variable to hold the SCU standalone repeater trim. */ +#ifdef OTP_SCU_REG_TRIM +extern uint32_t soc_scu_srut; +#endif + +/*! Global variable to hold the VPU standalone repeater1 trim. */ +#ifdef OTP_VPU_REG0_TRIM +extern uint32_t soc_vpu_srut1; +#endif + +/*! Global variable to hold the VPU standalone repeater2 trim. */ +#ifdef OTP_VPU_REG1_TRIM +extern uint32_t soc_vpu_srut2; +#endif + +#if HAS_SS_GPU_0 || HAS_SS_GPU_1 +/*! Global variable to hold the maximum GPU freq dictated by the fuse. */ +extern uint32_t soc_max_gpu_freq; +#endif + +#if HAS_SS_AP_0 +/*! Global variable to hold the maximum AP0 freq dictated by the fuse. */ +extern uint32_t soc_max_ap0_freq; +#endif + +#if HAS_SS_AP_1 +/*! Global variable to hold the maximum AP1 freq dictated by the fuse. */ +extern uint32_t soc_max_ap1_freq; +#endif + +#if HAS_SS_AP_2 +/*! Global variable to hold the maximum AP2 freq dictated by the fuse. */ +extern uint32_t soc_max_ap2_freq; +#endif + +#if (HAS_SS_GPU_0 || HAS_SS_GPU_1) && !defined(NO_GPU_CLKS) +/*! + * Global variable to hold the GPU clock frequency and voltage for the + * various operating points. + */ +extern soc_gpu_clks_opp_t gpu_clks[NUM_GPU_OPP]; +#endif + +extern soc_hmp_t soc_hmp; +extern soc_sys_if_req_t soc_sys_if_req[SOC_NUM_HMP_NODES][SOC_NUM_SYS_IF]; +extern soc_mcu_state_t soc_mcu_state[SOC_NUM_MCU]; +#if defined(SOC_NUM_AUX) && (SOC_NUM_AUX >= 1) +extern soc_aux_state_t soc_aux_state[SOC_NUM_AUX]; +#endif +extern soc_cluster_state_t soc_cluster_state[SOC_NUM_CLUSTER]; + +#if (SOC_NUM_CLUSTER > 1U) + extern soc_multicluster_state_t soc_multicluster_state; +#endif + +#ifdef SWI_DQS2DQ_IRQn +extern soc_dqs2dq_sync_info_t *soc_dqs2dq_sync_info; +#endif + +#if FSL_FEATURE_PCIE_DPLL_SS +extern uint32_t ss_step; +extern uint32_t ss_stop; +extern uint32_t ss_denom; +#endif + +/*! Global variable to track if boot resources should not be reset. */ +extern sc_bool_t soc_no_reset; + +/* Functions */ + +/*! + * @name Initialization Functions + * @{ + */ + +/*! + * This function initalizes the parts of the SoC. + * + * @param[in] phase flag indicating phase + * + */ +void soc_init_common(boot_phase_t phase); + +/*! + * This function initalizes the SoC specific parts of the chip. + * + * @param[in] phase flag indicating phase + * + */ +void soc_init(boot_phase_t phase); + +/*! + * This function configures SCU resources. + * + * @param[in] pt_sc SCU partition + * @param[in] pt_boot boot partition + */ +void soc_config_sc(sc_rm_pt_t pt_sc, sc_rm_pt_t pt_boot); + +/*! + * This function configures SECO resources. + */ +void soc_config_seco(void); + +/*! + * Configure QoS in the DB when it is powered up. + */ +void soc_qos_config(void); + +#ifdef AUTOCAL +/*! + * Calibrate REFGEN tree. + */ +void soc_autocal_refgen_tree(void); +#endif + +/*! + * This function returns the pointer to fuse availability array. + */ +uint32_t *soc_get_fuse_avail(void); + +/*! + * This function fills in a bit array with info about disabled + * resources. + */ +void soc_init_fused_rsrc(void); + +/*! + * This function configures a subsystem as not available. + * + * @param[in] ss subsystem not available + */ +void soc_ss_notavail(sc_sub_t ss); + +/*! + * This function initalizes the refgen trims from the fuses. + */ +void soc_init_refgen(void); + +/*! + * This function initalize regulator, repeater and osc trims + * from the fuses. + */ +void soc_analog_fuse_init(void); + +#if HAS_SS_GPU_0 || HAS_SS_GPU_1 +/*! + * This function initalizes the maximum GPU core, shader + * and AXI clock based on the fuse. + * + * @param[in] gpu_fuse GPU Frequency fuse + */ +uint32_t soc_gpu_freq_config(uint32_t gpu_fuse); +#endif + +#if defined(HAS_V2X) && HAS_SS_V2X +/*! + * This function enables/disables V2X. + * + * @param[in] enb enable/disable + */ +void soc_v2x_enable(sc_bool_t enb); +#endif + +/** @} */ + +/*! + * @name Info Functions + * @{ + */ + +/*! + * This function saves reset info into persistant storage. + * + * @param[in] reason reason for reset + * @param[in] pt partition that caused reset + * + */ +void soc_set_reset_info(sc_pm_reset_reason_t reason, sc_rm_pt_t pt); + +/*! + * Return reset reason. + */ +sc_pm_reset_reason_t soc_reset_reason(void); + +/*! + * Return partition causing reset. + */ +sc_rm_pt_t soc_reset_part(void); + +/*! + * This function returns if a resource is available. + * + * @param[in] rsrc resource to check + * + * @return Returns SC_TRUE if the resource is available. + */ +sc_bool_t soc_rsrc_avail(sc_rsrc_t rsrc); + +/*! + * This function returns the trim value for a temp sensor. + * + * @param[in] dsc DSC to check + * + * @return Returns trim value. + */ +uint32_t soc_get_temp_trim(sc_dsc_t dsc); + +/*! + * This function returns the offset value for a temp sensor. + * + * @param[in] dsc DSC to check + * + * @return Returns the offset value. + */ +int8_t soc_get_temp_ofs(sc_dsc_t dsc); + +/*! + * This function returns temp interrupt to use. + * + * @param[in] dsc DSC alarm came from + * @param[in] alarm alarm (0=panic, 1=low, 2=high) + * + * @return Returns the interrupt. + */ +uint32_t soc_get_temp_trigger(sc_dsc_t dsc, uint32_t alarm); + +/*! + * This function returns the maximum frequency limited by + * the fuses for the GPU and AP cores + * + * @param[in] dsc_id DSC to check + * + * @return Returns the maximum frequency limited by fuse + */ +uint32_t soc_get_max_freq(sc_dsc_t dsc_id); + +/*! + * This function checks if the frequency is limited by + * fuse. + * + * @param[in] enet_rsrc ethernet resource to check + * + * @return SC_TRUE is frequency is limited + */ +sc_bool_t soc_enet_get_freq_limit(sc_rsrc_t enet_rsrc); + +/*! + * Initialize the maximum frequency of certain resources based + * on fuses. + */ +void soc_get_max_freq_fuse(void); + +/*! + * This function identifies if the given pd has internal + * or external switches. + * + *@param[in] dsc DSC to affect + *@param[in] pd pd to affect + * + * @return Returns SC_TRUE if the pd is internally switched, + * SC_FALSE if externally switched. + */ +sc_bool_t soc_pd_switchable(sc_dsc_t dsc, uint32_t pd); + +/*! + * This function checks if the given power domain of the given + * dsc supports retention. + * + *@param[in] dsc DSC to affect + *@param[in] pd pd to affect + * + * @return Returns SC_TRUE if the pd supports retention + */ +sc_bool_t soc_pd_retention(sc_dsc_t dsc, uint32_t pd); + +/*! + * This function checks if the given subsystem has forward + * body-bias. + * + *@param[in] ss subsystem to affect + * + * @return Returns SC_TRUE if the pd supports forward body-bias + */ +sc_bool_t soc_ss_has_bias(sc_sub_t ss); + +/*! + * This function returns the subsystem AI type, mainly used to + * identify if an SS has temp sensor. + * + * @param[in] ss subsystem to check + * + * @return Type of Analog Interface in the SS + */ +dsc_ai_type_t soc_ss_ai_type(sc_sub_t ss); + +/*! + * Return the type of memory used in the given PD of + * the DSC. + * + *@param[in] dsc DSC to affect + *@param[in] pd pd to affect + * + * @return Type of memory (ESilicon or Normal) used in the SS + */ +uint32_t soc_mem_type(sc_dsc_t dsc, uint32_t pd); + +/*! + * This function returns the uniquely defined memory power plane + * for the given dsc id + * + * @param[in] dsc_id DSC to check + * + * @return memory plane for the dsc_id + */ +uint8_t soc_mem_pwr_plane(sc_dsc_t dsc_id); + +/*! + * This function returns the change state of a resource during reboot. + * + * @param[in] idx idx to check + * + * @return SC_TRUE if not to be reset + */ +sc_bool_t soc_reboot_no_reset(sc_rm_idx_t idx); + +/*! + * Return the DSCMIX clock slice index and type. + * + * @param[out] clk_type DSC clock slice type + * @param[out] idx DSC clock slice index + * @param[out] parent DSC clock slice parent + */ +void soc_dsc_clock_info(dsc_clk_type_t *clk_type, uint32_t *idx, + sc_pm_clk_parent_t *parent); + +/*! + * Return HW limited clock dividers. + * + * @param[in] dsc DSC to affect + * @param[in] clkinfo Pointer to clock whose info is requested + * @param[out] pll_div Pll divided output + * + * @return DSCMIX clock slice divider + */ +uint32_t soc_get_clock_div(sc_dsc_t dsc, const dsc_clk_info_t *clkinfo, uint8_t *pll_div); + +/*! + * Checks if the given clock slice is the DSCMIX slice. + * + * @param[in] clk_info pointer to the clock data structure + * + * @return SC_TRUE if the slice is a DSCMIX slice + */ +sc_bool_t soc_slice_is_dsc(const dsc_clk_info_t *clk_info); + +#ifdef USE_AVPLL_FOR_DC +/*! + * This function returns parameters required to setup the AVPLLs used by + * DC subsystem. + * + * @param[in] pll_rsrc DC PLL resource ID + * @param[out] ai_toggle AI toggle to which the replacement AVPLL + * is connected + * @param[out] ssc_enable SC_TRUE if spread spectrum should be + * enabled for the PLL + * + * @return DSC_ID of the subsystem in which the AVPLLs reside + */ +sc_dsc_t soc_get_dc_avpll_info(sc_rsrc_t pll_rsrc, uint8_t *ai_toggle, + sc_bool_t *ssc_enable); +#endif + +/*! + * This function returns spread spectrum info required to setup the AVPLL + * + * @param[in] dsc dsc to affect + * @param[in] pll_index PLL index to affect + * + * @return Spread spectrum PPM for the PLL + */ +uint8_t soc_get_avpll_ssc_n(sc_dsc_t dsc, uint8_t pll_index); + +/*! + * This function checks if the GPU frequency is HW limited based on fuses. + * + * @return SC_TRUE if the frequency is HW limited + */ +sc_bool_t soc_gpu_freq_hw_limited(void); + +/*! + * Calculate and return the ROM patch checksum. + * + * @param[out] checksum pointer to return checksum + * @param[in] len length of fuse area to sum + */ +void soc_rompatch_checksum(uint32_t *checksum, uint16_t len); + +#ifdef ROM_PATCH_HEADER +/*! + * Return info for the first ROM patch. + * + * @param[in] id ID of patches to find + * @param[out] desc pointer to return patch descriptor + * @param[out] len pointer to return patch length + * @param[out] type pointer to return patch type + * @param[out] checksum pointer to return patch checksum + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NONE patch found, + * - SC_ERR_NOTFOUND if no patch found + */ +sc_err_t soc_patch_info_1(uint8_t id, uint8_t *desc, uint8_t *len, + uint8_t *type, uint32_t *checksum); + +/*! + * Return info for the next ROM patch. + * + * @param[in] id ID of patches to find + * @param[out] desc pointer to return patch descriptor + * @param[out] len pointer to return patch length + * @param[out] type pointer to return patch type + * @param[out] checksum pointer to return patch checksum + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NONE patch found, + * - SC_ERR_NOTFOUND if no additional patch found + */ +sc_err_t soc_patch_info_n(uint8_t id, uint8_t *desc, uint8_t *len, + uint8_t *type, uint32_t *checksum); +#endif + +/** @} */ + +/*! + * @name Analog Functions + * @{ + */ + +/*! + * Enable/Disable anamix in some SS during init and low power mode. + */ +void soc_setup_anamix(sc_bool_t enable); + +/*! + * This function powers up the DSC anamix. + * + * @param[in] dsc DSC to affect + */ +void soc_dsc_powerup_anamix(sc_dsc_t dsc); + +/*! + * This function powers up the DSC phymix. + * + * @param[in] dsc DSC to affect + */ +void soc_dsc_powerup_phymix(sc_dsc_t dsc); + +/*! + * This function powers down the DSC anamix. + * + * @param[in] dsc DSC to affect + */ +void soc_dsc_powerdown_anamix(sc_dsc_t dsc); + +/*! + * This function powers down the DSC phymix. + * + * @param[in] dsc DSC to affect + */ +void soc_dsc_powerdown_phymix(sc_dsc_t dsc); + +/*! + * Setup HSIO repeaters for internal or external PCIE clock + * + * @param[in] internal_clk SC_TRUE if using internal clock + * @param[in] enable SC_TRUE if powering up SS + */ +void soc_setup_hsio_repeater(board_parm_rtn_t internal_clk, sc_bool_t enable); + +/*! + * Setup the Forward body-bias for the given subsystem + * + * @param[in] ss Subsystem to affect + * @param[in] bias_mask IP within SS to enable/disable + * @param[in] enable SC_TRUE if enabling forward body-bias + * @param[in] delay time to wait when disabling forward body-bias + */ +void soc_set_bias(sc_sub_t ss, uint8_t bias_mask, sc_bool_t enable, + uint32_t delay); + +/*! + * Return the DPLL DCO-P trim value + * + * @param[in] dsc Subsystem to affect + * @param[in] pll_index PLL index within the SS + * @param[in] rate PLL lock rate + * + * @return DCO-PC trim value (default if fuse is 0) + */ +uint32_t soc_dpll_dco_pc(sc_dsc_t dsc, uint8_t pll_index, uint32_t rate); + +/*! + * Populate the DPLL DCO-PC values based on fuses + */ +void soc_dpll_populate_tbl(void); + +/** @} */ + +/*! + * @name Power Functions + * @{ + */ + +/*! + * Set the voltage based on the frequency for SS controlled by + * PMIC rail. + * + * @param[in] ss Subsystem to affect + * @param[in] old_freq Freq associated with current voltage + * @param[in] new_freq Freq associated with new voltage + * @param[in] pmic_change SC_TRUE is pmic voltage should be changed + * + * @return SC_ERR_NONE on successful voltage change else error code + */ +sc_err_t soc_set_freq_voltage(sc_sub_t ss, uint32_t old_freq, + uint32_t *new_freq, sc_bool_t pmic_change); + +/*! + * Handle SoC and board level power transitions required to power up + * or down a power domain. + * + * @param[in] ss Subsytem to affect + * @param[in] pd Power domain within the SS transitioning + * @param[in] from_mode Current power mode of the pd + * @param[in] to_mode New power mode of the pd + */ +void soc_trans_pd(sc_sub_t ss, uint8_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); + +/*! + * Check if the Forward body bias is enabled for the cluster, this + * function is only valid for the AP clusters. + * + * @param[in] ss Subsystem to affect + * + * @return SC_TRUE if forward body-bias is enabled. + */ +sc_bool_t soc_bias_enabled(sc_sub_t ss); + + +/*! + * Check if the new PLL rate is below the max freq vd-detect in the SS + * can support. + * + * @param[in] dsc DSC of subsystem to affect + * @param[in] rate New pll rate + * + * @return SC_TRUE if new pll rate is below the max vd-detect frequency + */ +sc_bool_t soc_ss_has_vd_detect(sc_dsc_t dsc, sc_pm_clock_rate_t rate); + +/*! + * Transition internal SOC level bandgap + * + * @param[in] ss Subsystem to affect + * @param[in] rsrc_idx Resource to affect + * @param[in] from_mode Current power mode of the resource + * @param[in] to_mode New power mode of the resource. + */ +void soc_trans_bandgap(sc_sub_t ss, sc_rsrc_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); + +void soc_fabric_force_on(sc_sub_t ss, sc_bool_t enb); +void soc_post_ss_reset(sc_dsc_t dsc, DSC_Type *dsc_base); +void soc_gicr_quiesce(uint8_t cluster_idx, uint32_t cpu_idx); +void soc_pause_ddr_traffic(sc_bool_t pause); +sc_bool_t soc_cluster_link_off(sc_rsrc_t resource, sc_rm_pt_t pt); + +/** @} */ + +/*! + * @name HPM Functions + * @{ + */ + +void soc_init_hmp(boot_phase_t phase); +sc_err_t soc_set_cpu_resume(uint8_t cluster_idx, uint8_t cpu_idx, + sc_bool_t isPrimary, sc_faddr_t resume_addr); +sc_err_t soc_set_mcu_resume(uint8_t mcu_idx,sc_faddr_t resume_addr); +sc_err_t soc_set_multicluster_power_mode(sc_pm_power_mode_t mode); +sc_err_t soc_set_cluster_power_mode(uint8_t cluster_idx, + sc_pm_power_mode_t mode); +sc_err_t soc_set_cpu_power_mode(uint8_t cluster_idx, uint8_t cpu_idx, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); +void soc_set_cpu_rst_mode(uint8_t cluster_idx, uint8_t cpu_idx, + sc_bool_t rst); +void soc_set_mcu_sleep_mode(uint8_t mcu_idx, sc_bool_t dsm, + uint8_t stopm, uint8_t pstopo); +sc_bool_t soc_get_mcu_sleep_mode_active(uint8_t mcu_idx); +void soc_set_mcu_rst_mode(uint8_t mcu_idx, sc_bool_t rst); +sc_err_t soc_req_sys_if_power_mode(uint8_t hmp_idx, sc_pm_sys_if_t sys_if, + sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); +void soc_trans_sys_if_hpm(uint8_t hmp_idx); +void soc_trans_sys_if_lpm(void); +void soc_sync_sys_if_pm(void); +void soc_trans_cpu_power_mode(uint8_t cluster_idx, uint8_t cpu_idx); +void soc_trans_mcu_power_mode(uint8_t mcu_idx); +void soc_prewake_cpu(void); +void soc_wake_cpu(uint8_t cluster_idx, uint8_t cpu_idx); +void soc_wake_mcu(uint8_t mcu_idx); +void soc_wake_lsio_mu(void); +void soc_wake_mcu_mu(uint8_t mcu_idx); +void soc_wake_sys_if_interconnect(void); +sc_pm_power_mode_t soc_get_hmp_sys_power_mode(void); +void soc_dump_hmp_power_state(void); +sc_bool_t soc_can_hmp_enter_lpm(void); +void soc_update_hmp_sys_power_mode(void); +void soc_update_hmp_boot_mem(void); + +/** @} */ + +/*! + * @name Auxiliary Core Functions + * @{ + */ + +#if defined(SOC_NUM_AUX) && (SOC_NUM_AUX >= 1) +/*! + * Get firmware address for auxiliary core + * + * @param[in] aux_idx Auxiliary core index + * @param[out] fw_addr Firmware address + * + * @return SC_ERR_NONE if firmware address could be retrieved. + */ +sc_err_t soc_aux_get_fw_addr(uint8_t aux_idx, sc_saddr_t *fw_addr); + +/*! + * This function enables the system interfaces needed to load an auxiliary + * core firmware image. + * + * @param[in] aux_idx Auxiliary core index + * @param[in] fw_addr Address of FW image + * + * @return SC_ERR_NONE if successful. + */ +sc_err_t soc_aux_enable_fw_load(uint8_t aux_idx, sc_faddr_t fw_addr); + +/*! + * This function disables the system interfaces needed to load an auxiliary + * core firmware image. + * + * @param[in] aux_idx Auxiliary core index + * @param[in] fw_addr Address of FW image + * + * @return SC_ERR_NONE if successful. + */ +sc_err_t soc_aux_disable_fw_load(uint8_t aux_idx); + +/*! + * This function checks if auxiliary core firmware load is in progress. + * + * @param[in] aux_idx Auxiliary core index + * + * @return SC_TRUE if firmware load is in progress. + */ +sc_bool_t soc_aux_check_fw_load(uint8_t aux_idx); + +/*! + * This function retrieves the system interface associated with the + * subsystem that contains the auxiliary core firmware. + * + * @param[in] ss Subsystem containing the firmware + * @param[out] sys_if System interface containing the firmware + * + * @return SC_ERR_NONE if mapping to system interface is found. + */ +sc_err_t soc_aux_get_fw_sys_if(sc_sub_t ss, sc_pm_sys_if_t *sys_if); +#endif + +/** @} */ + +/*! + * @name DDR Functions + * @{ + */ + +/*! + * This function initalizes DDR. + * + * @param[in] early boolean for early init + * + * @return Returns the sc_err_t. + * + */ +sc_err_t soc_init_ddr(sc_bool_t early); + +/*! + * This function places the DDR in SRPD (self-refresh power down) and + * disables DDR clocks. + */ +void soc_self_refresh_power_down_clk_disable_entry(void); + +/*! + * This function enables DDR clocks and exits the DDR from SRPD (self-refresh + * power down). + */ +void soc_refresh_power_down_clk_disable_exit(void); + +/*! + * This function configures parameters for DDR low-power retention (SRPD with + * DRC powered down). + * + * @param[in] ddr_ret_info pointer to retention info struct + */ +void soc_ddr_config_retention(soc_ddr_ret_info_t *ddr_ret_info); + +/*! + * This function places the DDR into low-power retention (SRPD with + * DRC powered down). + */ +void soc_ddr_enter_retention(void); + +/*! + * This function exits the DDR from low-power retention (SRPD with + * DRC powered down). + */ +void soc_ddr_exit_retention(void); + +/*! + * This function initializes LPDDR4 DQS2DQ training. + */ +void soc_ddr_dqs2dq_init(void); + +/*! + * This function does DDR bit deskew training. + */ +void soc_ddr_bit_deskew(void); + +/*! + * This function invokes LPDDR4 DQS2DQ periodic training. + */ +void soc_ddr_dqs2dq_periodic(void); + +#ifdef SWI_DQS2DQ_IRQn +/*! + * This function configures parameters of LPDDR4 DQS2DQ periodic training. + * + * @param[in] dqs2dq_sync_info pointer to DQS2DQ info struct + */ +void soc_ddr_dqs2dq_config(soc_dqs2dq_sync_info_t *dqs2dq_sync_info); + +/*! + * This function sychronizes LPDDR4 DQS2DQ periodic training to + * DDR traffic events (i.e. ISI frame completion). + */ +void soc_ddr_dqs2dq_sync(void); +#endif + +/*! + * This function enables DDR LPCG clock gating. + */ +void soc_drc_lpcg_setup(void); + +/** @} */ + +/*! + * @name Misc Functions + * @{ + */ + +/*! + * This function ticks the temp sensor processing. + * + * @param[in] msec milliseconds that have expired + */ +void soc_temp_sensor_tick(uint16_t msec); + +void soc_setup_msi_slave_ring(sc_sub_t cur_ss, sc_sub_t parent, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); +void soc_msi_ring_workaround(sc_pm_power_mode_t from_mode, + sc_pm_power_mode_t to_mode, soc_msi_ring_usecount_t *msi_slv_ring, + uint32_t num_msi_slaves, MSI_MSTR_Type *msi_reg, sc_sub_t cur_ss); + +#ifdef ERR050601_WORKAROUND +void soc_block_ap_set(sc_rm_pt_t pt, sc_rsrc_t resource); +void soc_block_ap_memreg(sc_rm_mr_t mr, sc_rm_perm_t *perms); +#endif + +/** @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * Dumps registers of single analog module. + * + * @param[in] dsc DSC to dump + * @param[in] tog toggle to dump + * @param[in] ai AI type + */ +void soc_dsc_ai_dumpmodule(sc_dsc_t dsc, uint8_t tog, sc_ai_t ai); + +/*! + * Dumps registers of analog modules in a subsystem. + * + * @param[in] dsc DSC to dump + */ +void soc_dsc_ai_dump(sc_dsc_t dsc); + +/*! + * Allows for muxing out analog clocks and voltage levels. + * + * @param[in] dsc DSC to affect + */ +void soc_anamix_test_out(sc_dsc_t dsc); + +/** @} */ + +#ifdef SOC_SELFHOSTED_DEBUG +soc_dbgapb_cluster_info_t *soc_dbgapb_get_cluster_info(sc_rsrc_t cpu_rsrc); +soc_dbgapb_cluster_info_t *soc_dbgapb_get_indexed_cluster_info(uint8_t idx); +soc_dbgapb_cpu_info_t *soc_dbgapb_get_cpu_info(sc_rsrc_t cpu_rsrc); + +sc_bool_t soc_dbgapb_halt(void); +sc_bool_t soc_dbgapb_get_reg(sc_rsrc_t cpu_rsrc, uint8_t reg_idx, + uint32_t *reg_upper, uint32_t *reg_lower); +sc_bool_t soc_dbgapb_get_L1line(sc_rsrc_t cpu_rsrc, sc_bool_t dcache, + uint8_t way, uint16_t set,uint32_t *tag_upper,uint32_t *tag_lower, + uint32_t line[ ], uint32_t num_words); +#endif + +/*! + * Tune the RC-OSC to the requested frequency + * + * @param[in] dsc DSC in which the RC-OSC resides + * @param[in] freq_mhz frequency to tune (normally 200Mhz) + */ +void soc_rc200_tune(sc_dsc_t dsc, uint32_t freq_mhz); + +/*! + * Retune the 24MHz Osc with the new CL_TUNE value. + * @param[in] cl_tune new capacitor value + */ +void soc_XtalCL_Tune(uint32_t cl_tune); + +#endif /* SC_SOC_API_H */ + +/** @} */ + diff --git a/platform/main/types.h b/platform/main/types.h new file mode 100755 index 0000000..22b59e3 --- /dev/null +++ b/platform/main/types.h @@ -0,0 +1,1047 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing types used across multiple service APIs. + */ +/*==========================================================================*/ + +#ifndef SC_TYPES_H +#define SC_TYPES_H + +/* Includes */ + +#include "main/scfw.h" + +/* Defines */ + +/*! + * @name Defines for chip IDs + */ +/** @{ */ +#define CHIP_ID_QM 0x1U /*!< i.MX8QM */ +#define CHIP_ID_QX 0x2U /*!< i.MX8QX*/ +#define CHIP_ID_DXL 0xEU /*!< i.MX8DXL */ +/** @} */ + +/*! + * @name Defines for common frequencies + */ +/** @{ */ +#define SC_32KHZ 32768U /*!< 32KHz */ +#define SC_1MHZ 1000000U /*!< 1MHz */ +#define SC_10MHZ 10000000U /*!< 10MHz */ +#define SC_16MHZ 16000000U /*!< 16MHz */ +#define SC_20MHZ 20000000U /*!< 20MHz */ +#define SC_25MHZ 25000000U /*!< 25MHz */ +#define SC_27MHZ 27000000U /*!< 27MHz */ +#define SC_40MHZ 40000000U /*!< 40MHz */ +#define SC_45MHZ 45000000U /*!< 45MHz */ +#define SC_50MHZ 50000000U /*!< 50MHz */ +#define SC_60MHZ 60000000U /*!< 60MHz */ +#define SC_66MHZ 66666666U /*!< 66MHz */ +#define SC_74MHZ 74250000U /*!< 74.25MHz */ +#define SC_80MHZ 80000000U /*!< 80MHz */ +#define SC_83MHZ 83333333U /*!< 83MHz */ +#define SC_84MHZ 84375000U /*!< 84.37MHz */ +#define SC_100MHZ 100000000U /*!< 100MHz */ +#define SC_106MHZ 106250000U /*!< 106.25MHz */ +#define SC_114MHZ 114000000U /*!< 114MHz */ +#define SC_125MHZ 125000000U /*!< 125MHz */ +#define SC_128MHZ 128000000U /*!< 128MHz */ +#define SC_133MHZ 133333333U /*!< 133MHz */ +#define SC_135MHZ 135000000U /*!< 135MHz */ +#define SC_150MHZ 150000000U /*!< 150MHz */ +#define SC_160MHZ 160000000U /*!< 160MHz */ +#define SC_166MHZ 166666666U /*!< 166MHz */ +#define SC_175MHZ 175000000U /*!< 175MHz */ +#define SC_180MHZ 180000000U /*!< 180MHz */ +#define SC_200MHZ 200000000U /*!< 200MHz */ +#define SC_212MHZ 212500000U /*!< 212.5MHz */ +#define SC_217MHZ 216666666U /*!< 217MHz */ +#define SC_250MHZ 250000000U /*!< 250MHz */ +#define SC_266MHZ 266666666U /*!< 266MHz */ +#define SC_300MHZ 300000000U /*!< 300MHz */ +#define SC_312MHZ 312500000U /*!< 312.5MHZ */ +#define SC_320MHZ 320000000U /*!< 320MHz */ +#define SC_325MHZ 325000000U /*!< 325MHz */ +#define SC_333MHZ 333333333U /*!< 333MHz */ +#define SC_350MHZ 350000000U /*!< 350MHz */ +#define SC_368MHZ 368500000U /*!< 368.5MHZ */ +#define SC_372MHZ 372000000U /*!< 372MHz */ +#define SC_375MHZ 375000000U /*!< 375MHz */ +#define SC_400MHZ 400000000U /*!< 400MHz */ +#define SC_425MHZ 425000000U /*!< 425MHz */ +#define SC_465MHZ 465000000U /*!< 465MHz */ +#define SC_500MHZ 500000000U /*!< 500MHz */ +#define SC_594MHZ 594000000U /*!< 594MHz */ +#define SC_625MHZ 625000000U /*!< 625MHz */ +#define SC_640MHZ 640000000U /*!< 640MHz */ +#define SC_648MHZ 648000000U /*!< 648MHz */ +#define SC_650MHZ 650000000U /*!< 650MHz */ +#define SC_667MHZ 666666667U /*!< 667MHz */ +#define SC_675MHZ 675000000U /*!< 675MHz */ +#define SC_700MHZ 700000000U /*!< 700MHz */ +#define SC_720MHZ 720000000U /*!< 720MHz */ +#define SC_750MHZ 750000000U /*!< 750MHz */ +#define SC_753MHZ 753000000U /*!< 753MHz */ +#define SC_793MHZ 793000000U /*!< 793MHz */ +#define SC_800MHZ 800000000U /*!< 800MHz */ +#define SC_850MHZ 850000000U /*!< 850MHz */ +#define SC_858MHZ 858000000U /*!< 858MHz */ +#define SC_900MHZ 900000000U /*!< 900MHz */ +#define SC_953MHZ 953000000U /*!< 953MHz */ +#define SC_963MHZ 963000000U /*!< 963MHz */ +#define SC_1000MHZ 1000000000U /*!< 1GHz */ +#define SC_1060MHZ 1060000000U /*!< 1.06GHz */ +#define SC_1068MHZ 1068000000U /*!< 1.068GHz */ +#define SC_1121MHZ 1121000000U /*!< 1.121GHz */ +#define SC_1173MHZ 1173000000U /*!< 1.173GHz */ +#define SC_1188MHZ 1188000000U /*!< 1.188GHz */ +#define SC_1260MHZ 1260000000U /*!< 1.26GHz */ +#define SC_1278MHZ 1278000000U /*!< 1.278GHz */ +#define SC_1280MHZ 1280000000U /*!< 1.28GHz */ +#define SC_1300MHZ 1300000000U /*!< 1.3GHz */ +#define SC_1313MHZ 1313000000U /*!< 1.313GHz */ +#define SC_1345MHZ 1345000000U /*!< 1.345GHz */ +#define SC_1400MHZ 1400000000U /*!< 1.4GHz */ +#define SC_1500MHZ 1500000000U /*!< 1.5GHz */ +#define SC_1600MHZ 1600000000U /*!< 1.6GHz */ +#define SC_1800MHZ 1800000000U /*!< 1.8GHz */ +#define SC_1860MHZ 1860000000U /*!< 1.86GHz */ +#define SC_2000MHZ 2000000000U /*!< 2.0GHz */ +#define SC_2112MHZ 2112000000U /*!< 2.12GHz */ +/** @} */ + +/*! + * @name Defines for 24M related frequencies + */ +/** @{ */ +#define SC_8MHZ 8000000U /*!< 8MHz */ +#define SC_12MHZ 12000000U /*!< 12MHz */ +#define SC_19MHZ 19800000U /*!< 19.8MHz */ +#define SC_24MHZ 24000000U /*!< 24MHz */ +#define SC_48MHZ 48000000U /*!< 48MHz */ +#define SC_120MHZ 120000000U /*!< 120MHz */ +#define SC_132MHZ 132000000U /*!< 132MHz */ +#define SC_144MHZ 144000000U /*!< 144MHz */ +#define SC_192MHZ 192000000U /*!< 192MHz */ +#define SC_210MHZ 210000000U /*!< 210MHz */ +#define SC_211MHZ 211200000U /*!< 211.2MHz */ +#define SC_228MHZ 228000000U /*!< 233MHz */ +#define SC_240MHZ 240000000U /*!< 240MHz */ +#define SC_264MHZ 264000000U /*!< 264MHz */ +#define SC_352MHZ 352000000U /*!< 352MHz */ +#define SC_360MHZ 360000000U /*!< 360MHz */ +#define SC_384MHZ 384000000U /*!< 384MHz */ +#define SC_396MHZ 396000000U /*!< 396MHz */ +#define SC_432MHZ 432000000U /*!< 432MHz */ +#define SC_456MHZ 456000000U /*!< 466MHz */ +#define SC_480MHZ 480000000U /*!< 480MHz */ +#define SC_600MHZ 600000000U /*!< 600MHz */ +#define SC_744MHZ 744000000U /*!< 744MHz */ +#define SC_792MHZ 792000000U /*!< 792MHz */ +#define SC_840MHZ 840000000U /*!< 840MHz */ +#define SC_864MHZ 864000000U /*!< 864MHz */ +#define SC_912MHZ 912000000U /*!< 912MHz */ +#define SC_960MHZ 960000000U /*!< 960MHz */ +#define SC_1056MHZ 1056000000U /*!< 1056MHz */ +#define SC_1104MHZ 1104000000U /*!< 1104MHz */ +#define SC_1200MHZ 1200000000U /*!< 1.2GHz */ +#define SC_1464MHZ 1464000000U /*!< 1.464GHz */ +#define SC_2400MHZ 2400000000U /*!< 2.4GHz */ +#define SC_3000MHZ 3000000000U /*!< 2.4GHz */ + +/** @} */ + +/*! + * @name Defines for A/V related frequencies + */ +/** @{ */ +#define SC_62MHZ 62937500U /*!< 62.9375MHz */ +#define SC_755MHZ 755250000U /*!< 755.25MHz */ +/** @} */ + +/*! + * @name Defines for type widths + */ +/** @{ */ +#define SC_BOOL_W 1U /*!< Width of sc_bool_t */ +#define SC_ERR_W 4U /*!< Width of sc_err_t */ +#define SC_RSRC_W 10U /*!< Width of sc_rsrc_t */ +#define SC_CTRL_W 7U /*!< Width of sc_ctrl_t */ +/** @} */ + +/*! + * @name Defines for sc_bool_t + */ +/** @{ */ +#define SC_FALSE ((sc_bool_t) 0U) /*!< False */ +#define SC_TRUE ((sc_bool_t) 1U) /*!< True */ +/** @} */ + +/*! + * @name Defines for sc_err_t + */ +/** @{ */ +#define SC_ERR_NONE 0U /*!< Success */ +#define SC_ERR_VERSION 1U /*!< Incompatible API version */ +#define SC_ERR_CONFIG 2U /*!< Configuration error */ +#define SC_ERR_PARM 3U /*!< Bad parameter */ +#define SC_ERR_NOACCESS 4U /*!< Permission error (no access) */ +#define SC_ERR_LOCKED 5U /*!< Permission error (locked) */ +#define SC_ERR_UNAVAILABLE 6U /*!< Unavailable (out of resources) */ +#define SC_ERR_NOTFOUND 7U /*!< Not found */ +#define SC_ERR_NOPOWER 8U /*!< No power */ +#define SC_ERR_IPC 9U /*!< Generic IPC error */ +#define SC_ERR_BUSY 10U /*!< Resource is currently busy/active */ +#define SC_ERR_FAIL 11U /*!< General I/O failure */ +#define SC_ERR_LAST 12U +/** @} */ + +/*! + * @name Defines for sc_rsrc_t + */ +/** @{ */ +#define SC_R_AP_0 0U +#define SC_R_AP_0_0 1U +#define SC_R_AP_0_1 2U +#define SC_R_AP_0_2 3U +#define SC_R_AP_0_3 4U +#define SC_R_AP_1 5U +#define SC_R_AP_1_0 6U +#define SC_R_AP_1_1 7U +#define SC_R_AP_1_2 8U +#define SC_R_AP_1_3 9U +#define SC_R_CCI 10U +#define SC_R_DB 11U +#define SC_R_DRC_0 12U +#define SC_R_DRC_1 13U +#define SC_R_GIC_SMMU 14U +#define SC_R_IRQSTR_MCU_0 15U +#define SC_R_IRQSTR_MCU_1 16U +#define SC_R_SMMU_0 17U +#define SC_R_GIC_0 18U +#define SC_R_DC_0_BLIT0 19U +#define SC_R_DC_0_BLIT1 20U +#define SC_R_DC_0_BLIT2 21U +#define SC_R_DC_0_BLIT_OUT 22U +#define SC_R_PERF_0 23U +#define SC_R_USB_1_PHY 24U +#define SC_R_DC_0_WARP 25U +#define SC_R_V2X_MU_0 26U +#define SC_R_V2X_MU_1 27U +#define SC_R_DC_0_VIDEO0 28U +#define SC_R_DC_0_VIDEO1 29U +#define SC_R_DC_0_FRAC0 30U +#define SC_R_V2X_MU_2 31U +#define SC_R_DC_0 32U +#define SC_R_GPU_2_PID0 33U +#define SC_R_DC_0_PLL_0 34U +#define SC_R_DC_0_PLL_1 35U +#define SC_R_DC_1_BLIT0 36U +#define SC_R_DC_1_BLIT1 37U +#define SC_R_DC_1_BLIT2 38U +#define SC_R_DC_1_BLIT_OUT 39U +#define SC_R_V2X_MU_3 40U +#define SC_R_V2X_MU_4 41U +#define SC_R_DC_1_WARP 42U +#define SC_R_STM 43U +#define SC_R_SECVIO 44U +#define SC_R_DC_1_VIDEO0 45U +#define SC_R_DC_1_VIDEO1 46U +#define SC_R_DC_1_FRAC0 47U +#define SC_R_V2X 48U +#define SC_R_DC_1 49U +#define SC_R_UNUSED14 50U +#define SC_R_DC_1_PLL_0 51U +#define SC_R_DC_1_PLL_1 52U +#define SC_R_SPI_0 53U +#define SC_R_SPI_1 54U +#define SC_R_SPI_2 55U +#define SC_R_SPI_3 56U +#define SC_R_UART_0 57U +#define SC_R_UART_1 58U +#define SC_R_UART_2 59U +#define SC_R_UART_3 60U +#define SC_R_UART_4 61U +#define SC_R_EMVSIM_0 62U +#define SC_R_EMVSIM_1 63U +#define SC_R_DMA_0_CH0 64U +#define SC_R_DMA_0_CH1 65U +#define SC_R_DMA_0_CH2 66U +#define SC_R_DMA_0_CH3 67U +#define SC_R_DMA_0_CH4 68U +#define SC_R_DMA_0_CH5 69U +#define SC_R_DMA_0_CH6 70U +#define SC_R_DMA_0_CH7 71U +#define SC_R_DMA_0_CH8 72U +#define SC_R_DMA_0_CH9 73U +#define SC_R_DMA_0_CH10 74U +#define SC_R_DMA_0_CH11 75U +#define SC_R_DMA_0_CH12 76U +#define SC_R_DMA_0_CH13 77U +#define SC_R_DMA_0_CH14 78U +#define SC_R_DMA_0_CH15 79U +#define SC_R_DMA_0_CH16 80U +#define SC_R_DMA_0_CH17 81U +#define SC_R_DMA_0_CH18 82U +#define SC_R_DMA_0_CH19 83U +#define SC_R_DMA_0_CH20 84U +#define SC_R_DMA_0_CH21 85U +#define SC_R_DMA_0_CH22 86U +#define SC_R_DMA_0_CH23 87U +#define SC_R_DMA_0_CH24 88U +#define SC_R_DMA_0_CH25 89U +#define SC_R_DMA_0_CH26 90U +#define SC_R_DMA_0_CH27 91U +#define SC_R_DMA_0_CH28 92U +#define SC_R_DMA_0_CH29 93U +#define SC_R_DMA_0_CH30 94U +#define SC_R_DMA_0_CH31 95U +#define SC_R_I2C_0 96U +#define SC_R_I2C_1 97U +#define SC_R_I2C_2 98U +#define SC_R_I2C_3 99U +#define SC_R_I2C_4 100U +#define SC_R_ADC_0 101U +#define SC_R_ADC_1 102U +#define SC_R_FTM_0 103U +#define SC_R_FTM_1 104U +#define SC_R_CAN_0 105U +#define SC_R_CAN_1 106U +#define SC_R_CAN_2 107U +#define SC_R_DMA_1_CH0 108U +#define SC_R_DMA_1_CH1 109U +#define SC_R_DMA_1_CH2 110U +#define SC_R_DMA_1_CH3 111U +#define SC_R_DMA_1_CH4 112U +#define SC_R_DMA_1_CH5 113U +#define SC_R_DMA_1_CH6 114U +#define SC_R_DMA_1_CH7 115U +#define SC_R_DMA_1_CH8 116U +#define SC_R_DMA_1_CH9 117U +#define SC_R_DMA_1_CH10 118U +#define SC_R_DMA_1_CH11 119U +#define SC_R_DMA_1_CH12 120U +#define SC_R_DMA_1_CH13 121U +#define SC_R_DMA_1_CH14 122U +#define SC_R_DMA_1_CH15 123U +#define SC_R_DMA_1_CH16 124U +#define SC_R_DMA_1_CH17 125U +#define SC_R_DMA_1_CH18 126U +#define SC_R_DMA_1_CH19 127U +#define SC_R_DMA_1_CH20 128U +#define SC_R_DMA_1_CH21 129U +#define SC_R_DMA_1_CH22 130U +#define SC_R_DMA_1_CH23 131U +#define SC_R_DMA_1_CH24 132U +#define SC_R_DMA_1_CH25 133U +#define SC_R_DMA_1_CH26 134U +#define SC_R_DMA_1_CH27 135U +#define SC_R_DMA_1_CH28 136U +#define SC_R_DMA_1_CH29 137U +#define SC_R_DMA_1_CH30 138U +#define SC_R_DMA_1_CH31 139U +#define SC_R_V2X_PID0 140U +#define SC_R_V2X_PID1 141U +#define SC_R_V2X_PID2 142U +#define SC_R_V2X_PID3 143U +#define SC_R_GPU_0_PID0 144U +#define SC_R_GPU_0_PID1 145U +#define SC_R_GPU_0_PID2 146U +#define SC_R_GPU_0_PID3 147U +#define SC_R_GPU_1_PID0 148U +#define SC_R_GPU_1_PID1 149U +#define SC_R_GPU_1_PID2 150U +#define SC_R_GPU_1_PID3 151U +#define SC_R_PCIE_A 152U +#define SC_R_SERDES_0 153U +#define SC_R_MATCH_0 154U +#define SC_R_MATCH_1 155U +#define SC_R_MATCH_2 156U +#define SC_R_MATCH_3 157U +#define SC_R_MATCH_4 158U +#define SC_R_MATCH_5 159U +#define SC_R_MATCH_6 160U +#define SC_R_MATCH_7 161U +#define SC_R_MATCH_8 162U +#define SC_R_MATCH_9 163U +#define SC_R_MATCH_10 164U +#define SC_R_MATCH_11 165U +#define SC_R_MATCH_12 166U +#define SC_R_MATCH_13 167U +#define SC_R_MATCH_14 168U +#define SC_R_PCIE_B 169U +#define SC_R_SATA_0 170U +#define SC_R_SERDES_1 171U +#define SC_R_HSIO_GPIO_0 172U +#define SC_R_MATCH_15 173U +#define SC_R_MATCH_16 174U +#define SC_R_MATCH_17 175U +#define SC_R_MATCH_18 176U +#define SC_R_MATCH_19 177U +#define SC_R_MATCH_20 178U +#define SC_R_MATCH_21 179U +#define SC_R_MATCH_22 180U +#define SC_R_MATCH_23 181U +#define SC_R_MATCH_24 182U +#define SC_R_MATCH_25 183U +#define SC_R_MATCH_26 184U +#define SC_R_MATCH_27 185U +#define SC_R_MATCH_28 186U +#define SC_R_LCD_0 187U +#define SC_R_LCD_0_PWM_0 188U +#define SC_R_LCD_0_I2C_0 189U +#define SC_R_LCD_0_I2C_1 190U +#define SC_R_PWM_0 191U +#define SC_R_PWM_1 192U +#define SC_R_PWM_2 193U +#define SC_R_PWM_3 194U +#define SC_R_PWM_4 195U +#define SC_R_PWM_5 196U +#define SC_R_PWM_6 197U +#define SC_R_PWM_7 198U +#define SC_R_GPIO_0 199U +#define SC_R_GPIO_1 200U +#define SC_R_GPIO_2 201U +#define SC_R_GPIO_3 202U +#define SC_R_GPIO_4 203U +#define SC_R_GPIO_5 204U +#define SC_R_GPIO_6 205U +#define SC_R_GPIO_7 206U +#define SC_R_GPT_0 207U +#define SC_R_GPT_1 208U +#define SC_R_GPT_2 209U +#define SC_R_GPT_3 210U +#define SC_R_GPT_4 211U +#define SC_R_KPP 212U +#define SC_R_MU_0A 213U +#define SC_R_MU_1A 214U +#define SC_R_MU_2A 215U +#define SC_R_MU_3A 216U +#define SC_R_MU_4A 217U +#define SC_R_MU_5A 218U +#define SC_R_MU_6A 219U +#define SC_R_MU_7A 220U +#define SC_R_MU_8A 221U +#define SC_R_MU_9A 222U +#define SC_R_MU_10A 223U +#define SC_R_MU_11A 224U +#define SC_R_MU_12A 225U +#define SC_R_MU_13A 226U +#define SC_R_MU_5B 227U +#define SC_R_MU_6B 228U +#define SC_R_MU_7B 229U +#define SC_R_MU_8B 230U +#define SC_R_MU_9B 231U +#define SC_R_MU_10B 232U +#define SC_R_MU_11B 233U +#define SC_R_MU_12B 234U +#define SC_R_MU_13B 235U +#define SC_R_ROM_0 236U +#define SC_R_FSPI_0 237U +#define SC_R_FSPI_1 238U +#define SC_R_IEE_0 239U +#define SC_R_IEE_0_R0 240U +#define SC_R_IEE_0_R1 241U +#define SC_R_IEE_0_R2 242U +#define SC_R_IEE_0_R3 243U +#define SC_R_IEE_0_R4 244U +#define SC_R_IEE_0_R5 245U +#define SC_R_IEE_0_R6 246U +#define SC_R_IEE_0_R7 247U +#define SC_R_SDHC_0 248U +#define SC_R_SDHC_1 249U +#define SC_R_SDHC_2 250U +#define SC_R_ENET_0 251U +#define SC_R_ENET_1 252U +#define SC_R_MLB_0 253U +#define SC_R_DMA_2_CH0 254U +#define SC_R_DMA_2_CH1 255U +#define SC_R_DMA_2_CH2 256U +#define SC_R_DMA_2_CH3 257U +#define SC_R_DMA_2_CH4 258U +#define SC_R_USB_0 259U +#define SC_R_USB_1 260U +#define SC_R_USB_0_PHY 261U +#define SC_R_USB_2 262U +#define SC_R_USB_2_PHY 263U +#define SC_R_DTCP 264U +#define SC_R_NAND 265U +#define SC_R_LVDS_0 266U +#define SC_R_LVDS_0_PWM_0 267U +#define SC_R_LVDS_0_I2C_0 268U +#define SC_R_LVDS_0_I2C_1 269U +#define SC_R_LVDS_1 270U +#define SC_R_LVDS_1_PWM_0 271U +#define SC_R_LVDS_1_I2C_0 272U +#define SC_R_LVDS_1_I2C_1 273U +#define SC_R_LVDS_2 274U +#define SC_R_LVDS_2_PWM_0 275U +#define SC_R_LVDS_2_I2C_0 276U +#define SC_R_LVDS_2_I2C_1 277U +#define SC_R_MCU_0_PID0 278U +#define SC_R_MCU_0_PID1 279U +#define SC_R_MCU_0_PID2 280U +#define SC_R_MCU_0_PID3 281U +#define SC_R_MCU_0_PID4 282U +#define SC_R_MCU_0_RGPIO 283U +#define SC_R_MCU_0_SEMA42 284U +#define SC_R_MCU_0_TPM 285U +#define SC_R_MCU_0_PIT 286U +#define SC_R_MCU_0_UART 287U +#define SC_R_MCU_0_I2C 288U +#define SC_R_MCU_0_INTMUX 289U +#define SC_R_ENET_0_A0 290U +#define SC_R_ENET_0_A1 291U +#define SC_R_MCU_0_MU_0B 292U +#define SC_R_MCU_0_MU_0A0 293U +#define SC_R_MCU_0_MU_0A1 294U +#define SC_R_MCU_0_MU_0A2 295U +#define SC_R_MCU_0_MU_0A3 296U +#define SC_R_MCU_0_MU_1A 297U +#define SC_R_MCU_1_PID0 298U +#define SC_R_MCU_1_PID1 299U +#define SC_R_MCU_1_PID2 300U +#define SC_R_MCU_1_PID3 301U +#define SC_R_MCU_1_PID4 302U +#define SC_R_MCU_1_RGPIO 303U +#define SC_R_MCU_1_SEMA42 304U +#define SC_R_MCU_1_TPM 305U +#define SC_R_MCU_1_PIT 306U +#define SC_R_MCU_1_UART 307U +#define SC_R_MCU_1_I2C 308U +#define SC_R_MCU_1_INTMUX 309U +#define SC_R_UNUSED17 310U +#define SC_R_UNUSED18 311U +#define SC_R_MCU_1_MU_0B 312U +#define SC_R_MCU_1_MU_0A0 313U +#define SC_R_MCU_1_MU_0A1 314U +#define SC_R_MCU_1_MU_0A2 315U +#define SC_R_MCU_1_MU_0A3 316U +#define SC_R_MCU_1_MU_1A 317U +#define SC_R_SAI_0 318U +#define SC_R_SAI_1 319U +#define SC_R_SAI_2 320U +#define SC_R_IRQSTR_AP_0 321U +#define SC_R_IRQSTR_DSP 322U +#define SC_R_ELCDIF_PLL 323U +#define SC_R_OCRAM 324U +#define SC_R_AUDIO_PLL_0 325U +#define SC_R_PI_0 326U +#define SC_R_PI_0_PWM_0 327U +#define SC_R_PI_0_PWM_1 328U +#define SC_R_PI_0_I2C_0 329U +#define SC_R_PI_0_PLL 330U +#define SC_R_PI_1 331U +#define SC_R_PI_1_PWM_0 332U +#define SC_R_PI_1_PWM_1 333U +#define SC_R_PI_1_I2C_0 334U +#define SC_R_PI_1_PLL 335U +#define SC_R_SC_PID0 336U +#define SC_R_SC_PID1 337U +#define SC_R_SC_PID2 338U +#define SC_R_SC_PID3 339U +#define SC_R_SC_PID4 340U +#define SC_R_SC_SEMA42 341U +#define SC_R_SC_TPM 342U +#define SC_R_SC_PIT 343U +#define SC_R_SC_UART 344U +#define SC_R_SC_I2C 345U +#define SC_R_SC_MU_0B 346U +#define SC_R_SC_MU_0A0 347U +#define SC_R_SC_MU_0A1 348U +#define SC_R_SC_MU_0A2 349U +#define SC_R_SC_MU_0A3 350U +#define SC_R_SC_MU_1A 351U +#define SC_R_SYSCNT_RD 352U +#define SC_R_SYSCNT_CMP 353U +#define SC_R_DEBUG 354U +#define SC_R_SYSTEM 355U +#define SC_R_SNVS 356U +#define SC_R_OTP 357U +#define SC_R_VPU_PID0 358U +#define SC_R_VPU_PID1 359U +#define SC_R_VPU_PID2 360U +#define SC_R_VPU_PID3 361U +#define SC_R_VPU_PID4 362U +#define SC_R_VPU_PID5 363U +#define SC_R_VPU_PID6 364U +#define SC_R_VPU_PID7 365U +#define SC_R_ENET_0_A2 366U +#define SC_R_ENET_1_A0 367U +#define SC_R_ENET_1_A1 368U +#define SC_R_ENET_1_A2 369U +#define SC_R_ENET_1_A3 370U +#define SC_R_ENET_1_A4 371U +#define SC_R_DMA_4_CH0 372U +#define SC_R_DMA_4_CH1 373U +#define SC_R_DMA_4_CH2 374U +#define SC_R_DMA_4_CH3 375U +#define SC_R_DMA_4_CH4 376U +#define SC_R_ISI_0_CH0 377U +#define SC_R_ISI_0_CH1 378U +#define SC_R_ISI_0_CH2 379U +#define SC_R_ISI_0_CH3 380U +#define SC_R_ISI_0_CH4 381U +#define SC_R_ISI_0_CH5 382U +#define SC_R_ISI_0_CH6 383U +#define SC_R_ISI_0_CH7 384U +#define SC_R_MJPEG_0_DEC_S0 385U +#define SC_R_MJPEG_0_DEC_S1 386U +#define SC_R_MJPEG_0_DEC_S2 387U +#define SC_R_MJPEG_0_DEC_S3 388U +#define SC_R_MJPEG_0_ENC_S0 389U +#define SC_R_MJPEG_0_ENC_S1 390U +#define SC_R_MJPEG_0_ENC_S2 391U +#define SC_R_MJPEG_0_ENC_S3 392U +#define SC_R_MIPI_0 393U +#define SC_R_MIPI_0_PWM_0 394U +#define SC_R_MIPI_0_I2C_0 395U +#define SC_R_MIPI_0_I2C_1 396U +#define SC_R_MIPI_1 397U +#define SC_R_MIPI_1_PWM_0 398U +#define SC_R_MIPI_1_I2C_0 399U +#define SC_R_MIPI_1_I2C_1 400U +#define SC_R_CSI_0 401U +#define SC_R_CSI_0_PWM_0 402U +#define SC_R_CSI_0_I2C_0 403U +#define SC_R_CSI_1 404U +#define SC_R_CSI_1_PWM_0 405U +#define SC_R_CSI_1_I2C_0 406U +#define SC_R_HDMI 407U +#define SC_R_HDMI_I2S 408U +#define SC_R_HDMI_I2C_0 409U +#define SC_R_HDMI_PLL_0 410U +#define SC_R_HDMI_RX 411U +#define SC_R_HDMI_RX_BYPASS 412U +#define SC_R_HDMI_RX_I2C_0 413U +#define SC_R_ASRC_0 414U +#define SC_R_ESAI_0 415U +#define SC_R_SPDIF_0 416U +#define SC_R_SPDIF_1 417U +#define SC_R_SAI_3 418U +#define SC_R_SAI_4 419U +#define SC_R_SAI_5 420U +#define SC_R_GPT_5 421U +#define SC_R_GPT_6 422U +#define SC_R_GPT_7 423U +#define SC_R_GPT_8 424U +#define SC_R_GPT_9 425U +#define SC_R_GPT_10 426U +#define SC_R_DMA_2_CH5 427U +#define SC_R_DMA_2_CH6 428U +#define SC_R_DMA_2_CH7 429U +#define SC_R_DMA_2_CH8 430U +#define SC_R_DMA_2_CH9 431U +#define SC_R_DMA_2_CH10 432U +#define SC_R_DMA_2_CH11 433U +#define SC_R_DMA_2_CH12 434U +#define SC_R_DMA_2_CH13 435U +#define SC_R_DMA_2_CH14 436U +#define SC_R_DMA_2_CH15 437U +#define SC_R_DMA_2_CH16 438U +#define SC_R_DMA_2_CH17 439U +#define SC_R_DMA_2_CH18 440U +#define SC_R_DMA_2_CH19 441U +#define SC_R_DMA_2_CH20 442U +#define SC_R_DMA_2_CH21 443U +#define SC_R_DMA_2_CH22 444U +#define SC_R_DMA_2_CH23 445U +#define SC_R_DMA_2_CH24 446U +#define SC_R_DMA_2_CH25 447U +#define SC_R_DMA_2_CH26 448U +#define SC_R_DMA_2_CH27 449U +#define SC_R_DMA_2_CH28 450U +#define SC_R_DMA_2_CH29 451U +#define SC_R_DMA_2_CH30 452U +#define SC_R_DMA_2_CH31 453U +#define SC_R_ASRC_1 454U +#define SC_R_ESAI_1 455U +#define SC_R_SAI_6 456U +#define SC_R_SAI_7 457U +#define SC_R_AMIX 458U +#define SC_R_MQS_0 459U +#define SC_R_DMA_3_CH0 460U +#define SC_R_DMA_3_CH1 461U +#define SC_R_DMA_3_CH2 462U +#define SC_R_DMA_3_CH3 463U +#define SC_R_DMA_3_CH4 464U +#define SC_R_DMA_3_CH5 465U +#define SC_R_DMA_3_CH6 466U +#define SC_R_DMA_3_CH7 467U +#define SC_R_DMA_3_CH8 468U +#define SC_R_DMA_3_CH9 469U +#define SC_R_DMA_3_CH10 470U +#define SC_R_DMA_3_CH11 471U +#define SC_R_DMA_3_CH12 472U +#define SC_R_DMA_3_CH13 473U +#define SC_R_DMA_3_CH14 474U +#define SC_R_DMA_3_CH15 475U +#define SC_R_DMA_3_CH16 476U +#define SC_R_DMA_3_CH17 477U +#define SC_R_DMA_3_CH18 478U +#define SC_R_DMA_3_CH19 479U +#define SC_R_DMA_3_CH20 480U +#define SC_R_DMA_3_CH21 481U +#define SC_R_DMA_3_CH22 482U +#define SC_R_DMA_3_CH23 483U +#define SC_R_DMA_3_CH24 484U +#define SC_R_DMA_3_CH25 485U +#define SC_R_DMA_3_CH26 486U +#define SC_R_DMA_3_CH27 487U +#define SC_R_DMA_3_CH28 488U +#define SC_R_DMA_3_CH29 489U +#define SC_R_DMA_3_CH30 490U +#define SC_R_DMA_3_CH31 491U +#define SC_R_AUDIO_PLL_1 492U +#define SC_R_AUDIO_CLK_0 493U +#define SC_R_AUDIO_CLK_1 494U +#define SC_R_MCLK_OUT_0 495U +#define SC_R_MCLK_OUT_1 496U +#define SC_R_PMIC_0 497U +#define SC_R_PMIC_1 498U +#define SC_R_SECO 499U +#define SC_R_CAAM_JR1 500U +#define SC_R_CAAM_JR2 501U +#define SC_R_CAAM_JR3 502U +#define SC_R_SECO_MU_2 503U +#define SC_R_SECO_MU_3 504U +#define SC_R_SECO_MU_4 505U +#define SC_R_HDMI_RX_PWM_0 506U +#define SC_R_AP_2 507U +#define SC_R_AP_2_0 508U +#define SC_R_AP_2_1 509U +#define SC_R_AP_2_2 510U +#define SC_R_AP_2_3 511U +#define SC_R_DSP 512U +#define SC_R_DSP_RAM 513U +#define SC_R_CAAM_JR1_OUT 514U +#define SC_R_CAAM_JR2_OUT 515U +#define SC_R_CAAM_JR3_OUT 516U +#define SC_R_VPU_DEC_0 517U +#define SC_R_VPU_ENC_0 518U +#define SC_R_CAAM_JR0 519U +#define SC_R_CAAM_JR0_OUT 520U +#define SC_R_PMIC_2 521U +#define SC_R_DBLOGIC 522U +#define SC_R_HDMI_PLL_1 523U +#define SC_R_BOARD_R0 524U +#define SC_R_BOARD_R1 525U +#define SC_R_BOARD_R2 526U +#define SC_R_BOARD_R3 527U +#define SC_R_BOARD_R4 528U +#define SC_R_BOARD_R5 529U +#define SC_R_BOARD_R6 530U +#define SC_R_BOARD_R7 531U +#define SC_R_MJPEG_0_DEC_MP 532U +#define SC_R_MJPEG_0_ENC_MP 533U +#define SC_R_VPU_TS_0 534U +#define SC_R_VPU_MU_0 535U +#define SC_R_VPU_MU_1 536U +#define SC_R_VPU_MU_2 537U +#define SC_R_VPU_MU_3 538U +#define SC_R_VPU_ENC_1 539U +#define SC_R_VPU 540U +#define SC_R_DMA_5_CH0 541U +#define SC_R_DMA_5_CH1 542U +#define SC_R_DMA_5_CH2 543U +#define SC_R_DMA_5_CH3 544U +#define SC_R_ATTESTATION 545U +#define SC_R_LAST 546U +#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /*!< All resources */ +/** @} */ + +/*! + * @name Compatibility defines for sc_rsrc_t + */ +/** @{ */ +#define SC_R_A35 SC_R_AP_2 +#define SC_R_A35_0 SC_R_AP_2_0 +#define SC_R_A35_1 SC_R_AP_2_1 +#define SC_R_A35_2 SC_R_AP_2_2 +#define SC_R_A35_3 SC_R_AP_2_3 +#define SC_R_A53 SC_R_AP_0 +#define SC_R_A53_0 SC_R_AP_0_0 +#define SC_R_A53_1 SC_R_AP_0_1 +#define SC_R_A53_2 SC_R_AP_0_2 +#define SC_R_A53_3 SC_R_AP_0_3 +#define SC_R_A72 SC_R_AP_1 +#define SC_R_A72_0 SC_R_AP_1_0 +#define SC_R_A72_1 SC_R_AP_1_1 +#define SC_R_A72_2 SC_R_AP_1_2 +#define SC_R_A72_3 SC_R_AP_1_3 +#define SC_R_GIC SC_R_GIC_0 +#define SC_R_HSIO_GPIO SC_R_HSIO_GPIO_0 +#define SC_R_IEE SC_R_IEE_0 +#define SC_R_IEE_R0 SC_R_IEE_0_R0 +#define SC_R_IEE_R1 SC_R_IEE_0_R1 +#define SC_R_IEE_R2 SC_R_IEE_0_R2 +#define SC_R_IEE_R3 SC_R_IEE_0_R3 +#define SC_R_IEE_R4 SC_R_IEE_0_R4 +#define SC_R_IEE_R5 SC_R_IEE_0_R5 +#define SC_R_IEE_R6 SC_R_IEE_0_R6 +#define SC_R_IEE_R7 SC_R_IEE_0_R7 +#define SC_R_IRQSTR_M4_0 SC_R_IRQSTR_MCU_0 +#define SC_R_IRQSTR_M4_1 SC_R_IRQSTR_MCU_1 +#define SC_R_IRQSTR_SCU2 SC_R_IRQSTR_AP_0 +#define SC_R_ISI_CH0 SC_R_ISI_0_CH0 +#define SC_R_ISI_CH1 SC_R_ISI_0_CH1 +#define SC_R_ISI_CH2 SC_R_ISI_0_CH2 +#define SC_R_ISI_CH3 SC_R_ISI_0_CH3 +#define SC_R_ISI_CH4 SC_R_ISI_0_CH4 +#define SC_R_ISI_CH5 SC_R_ISI_0_CH5 +#define SC_R_ISI_CH6 SC_R_ISI_0_CH6 +#define SC_R_ISI_CH7 SC_R_ISI_0_CH7 +#define SC_R_M4_0_I2C SC_R_MCU_0_I2C +#define SC_R_M4_0_INTMUX SC_R_MCU_0_INTMUX +#define SC_R_M4_0_MU_0A0 SC_R_MCU_0_MU_0A0 +#define SC_R_M4_0_MU_0A1 SC_R_MCU_0_MU_0A1 +#define SC_R_M4_0_MU_0A2 SC_R_MCU_0_MU_0A2 +#define SC_R_M4_0_MU_0A3 SC_R_MCU_0_MU_0A3 +#define SC_R_M4_0_MU_0B SC_R_MCU_0_MU_0B +#define SC_R_M4_0_MU_1A SC_R_MCU_0_MU_1A +#define SC_R_M4_0_PID0 SC_R_MCU_0_PID0 +#define SC_R_M4_0_PID1 SC_R_MCU_0_PID1 +#define SC_R_M4_0_PID2 SC_R_MCU_0_PID2 +#define SC_R_M4_0_PID3 SC_R_MCU_0_PID3 +#define SC_R_M4_0_PID4 SC_R_MCU_0_PID4 +#define SC_R_M4_0_PIT SC_R_MCU_0_PIT +#define SC_R_M4_0_RGPIO SC_R_MCU_0_RGPIO +#define SC_R_M4_0_SEMA42 SC_R_MCU_0_SEMA42 +#define SC_R_M4_0_TPM SC_R_MCU_0_TPM +#define SC_R_M4_0_UART SC_R_MCU_0_UART +#define SC_R_M4_1_I2C SC_R_MCU_1_I2C +#define SC_R_M4_1_INTMUX SC_R_MCU_1_INTMUX +#define SC_R_M4_1_MU_0A0 SC_R_MCU_1_MU_0A0 +#define SC_R_M4_1_MU_0A1 SC_R_MCU_1_MU_0A1 +#define SC_R_M4_1_MU_0A2 SC_R_MCU_1_MU_0A2 +#define SC_R_M4_1_MU_0A3 SC_R_MCU_1_MU_0A3 +#define SC_R_M4_1_MU_0B SC_R_MCU_1_MU_0B +#define SC_R_M4_1_MU_1A SC_R_MCU_1_MU_1A +#define SC_R_M4_1_PID0 SC_R_MCU_1_PID0 +#define SC_R_M4_1_PID1 SC_R_MCU_1_PID1 +#define SC_R_M4_1_PID2 SC_R_MCU_1_PID2 +#define SC_R_M4_1_PID3 SC_R_MCU_1_PID3 +#define SC_R_M4_1_PID4 SC_R_MCU_1_PID4 +#define SC_R_M4_1_PIT SC_R_MCU_1_PIT +#define SC_R_M4_1_RGPIO SC_R_MCU_1_RGPIO +#define SC_R_M4_1_SEMA42 SC_R_MCU_1_SEMA42 +#define SC_R_M4_1_TPM SC_R_MCU_1_TPM +#define SC_R_M4_1_UART SC_R_MCU_1_UART +#define SC_R_MJPEG_DEC_MP SC_R_MJPEG_0_DEC_MP +#define SC_R_MJPEG_DEC_S0 SC_R_MJPEG_0_DEC_S0 +#define SC_R_MJPEG_DEC_S1 SC_R_MJPEG_0_DEC_S1 +#define SC_R_MJPEG_DEC_S2 SC_R_MJPEG_0_DEC_S2 +#define SC_R_MJPEG_DEC_S3 SC_R_MJPEG_0_DEC_S3 +#define SC_R_MJPEG_ENC_MP SC_R_MJPEG_0_ENC_MP +#define SC_R_MJPEG_ENC_S0 SC_R_MJPEG_0_ENC_S0 +#define SC_R_MJPEG_ENC_S1 SC_R_MJPEG_0_ENC_S1 +#define SC_R_MJPEG_ENC_S2 SC_R_MJPEG_0_ENC_S2 +#define SC_R_MJPEG_ENC_S3 SC_R_MJPEG_0_ENC_S3 +#define SC_R_PERF SC_R_PERF_0 +#define SC_R_SMMU SC_R_SMMU_0 +/** @} */ + +/*! + * Define for ATF/Linux. Not used by SCFW. Not a valid parameter + * for any SCFW API calls! + */ +#define SC_R_NONE 0xFFF0U + +/* NOTE - please add by replacing some of the UNUSED from above! */ + +/*! + * Defines for sc_ctrl_t + */ +#define SC_C_TEMP 0U +#define SC_C_TEMP_HI 1U +#define SC_C_TEMP_LOW 2U +#define SC_C_PXL_LINK_MST1_ADDR 3U +#define SC_C_PXL_LINK_MST2_ADDR 4U +#define SC_C_PXL_LINK_MST_ENB 5U +#define SC_C_PXL_LINK_MST1_ENB 6U +#define SC_C_PXL_LINK_MST2_ENB 7U +#define SC_C_PXL_LINK_SLV1_ADDR 8U +#define SC_C_PXL_LINK_SLV2_ADDR 9U +#define SC_C_PXL_LINK_MST_VLD 10U +#define SC_C_PXL_LINK_MST1_VLD 11U +#define SC_C_PXL_LINK_MST2_VLD 12U +#define SC_C_SINGLE_MODE 13U +#define SC_C_ID 14U +#define SC_C_PXL_CLK_POLARITY 15U +#define SC_C_LINESTATE 16U +#define SC_C_PCIE_G_RST 17U +#define SC_C_PCIE_BUTTON_RST 18U +#define SC_C_PCIE_PERST 19U +#define SC_C_PHY_RESET 20U +#define SC_C_PXL_LINK_RATE_CORRECTION 21U +#define SC_C_PANIC 22U +#define SC_C_PRIORITY_GROUP 23U +#define SC_C_TXCLK 24U +#define SC_C_CLKDIV 25U +#define SC_C_DISABLE_50 26U +#define SC_C_DISABLE_125 27U +#define SC_C_SEL_125 28U +#define SC_C_MODE 29U +#define SC_C_SYNC_CTRL0 30U +#define SC_C_KACHUNK_CNT 31U +#define SC_C_KACHUNK_SEL 32U +#define SC_C_SYNC_CTRL1 33U +#define SC_C_DPI_RESET 34U +#define SC_C_MIPI_RESET 35U +#define SC_C_DUAL_MODE 36U +#define SC_C_VOLTAGE 37U +#define SC_C_PXL_LINK_SEL 38U +#define SC_C_OFS_SEL 39U +#define SC_C_OFS_AUDIO 40U +#define SC_C_OFS_PERIPH 41U +#define SC_C_OFS_IRQ 42U +#define SC_C_RST0 43U +#define SC_C_RST1 44U +#define SC_C_SEL0 45U +#define SC_C_CALIB0 46U +#define SC_C_CALIB1 47U +#define SC_C_CALIB2 48U +#define SC_C_IPG_DEBUG 49U +#define SC_C_IPG_DOZE 50U +#define SC_C_IPG_WAIT 51U +#define SC_C_IPG_STOP 52U +#define SC_C_IPG_STOP_MODE 53U +#define SC_C_IPG_STOP_ACK 54U +#define SC_C_SYNC_CTRL 55U +#define SC_C_OFS_AUDIO_ALT 56U +#define SC_C_DSP_BYP 57U +#define SC_C_CLK_GEN_EN 58U +#define SC_C_INTF_SEL 59U +#define SC_C_RXC_DLY 60U +#define SC_C_TIMER_SEL 61U +#define SC_C_MISC0 62U +#define SC_C_MISC1 63U +#define SC_C_MISC2 64U +#define SC_C_MISC3 65U +#define SC_C_LAST 66U + +/*! + * Define for used to specify all pads + */ +#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /*!< All pads */ + +/* Types */ + +/*! + * This type is used to store a boolean. + */ +typedef uint8_t sc_bool_t; + +/*! + * This type is used to store a system (full-size) address. + */ +typedef uint64_t sc_faddr_t; + +/*! + * This type is used to indicate error response for most functions. + */ +typedef uint8_t sc_err_t; + +/*! + * This type is used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ +typedef uint16_t sc_rsrc_t; + +/*! + * This type is used to indicate a control. + */ +typedef uint32_t sc_ctrl_t; + +/*! + * This type is used to indicate a pad. Valid values are SoC specific. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +typedef uint16_t sc_pad_t; + +#ifdef DOXYGEN + /* Extra documentation of standard types */ + + /*! + * Type used to declare an 8-bit integer. + */ + typedef __INT8_TYPE__ int8_t; + + /*! + * Type used to declare a 16-bit integer. + */ + typedef __INT16_TYPE__ int16_t; + + /*! + * Type used to declare a 32-bit integer. + */ + typedef __INT32_TYPE__ int32_t; + + /*! + * Type used to declare a 64-bit integer. + */ + typedef __INT64_TYPE__ int64_t; + + /*! + * Type used to declare an 8-bit unsigned integer. + */ + typedef __UINT8_TYPE__ uint8_t; + + /*! + * Type used to declare a 16-bit unsigned integer. + */ + typedef __UINT16_TYPE__ uint16_t; + + /*! + * Type used to declare a 32-bit unsigned integer. + */ + typedef __UINT32_TYPE__ uint32_t; + + /*! + * Type used to declare a 64-bit unsigned integer. + */ + typedef __UINT64_TYPE__ uint64_t; +#endif + +#endif /* SC_TYPES_H */ + diff --git a/platform/soc/MX8DXL/Makefile b/platform/soc/MX8DXL/Makefile new file mode 100755 index 0000000..da097a7 --- /dev/null +++ b/platform/soc/MX8DXL/Makefile @@ -0,0 +1,7 @@ + +OBJS += $(OUT)/soc/MX8DXL/soc.o +OBJS += $(OUT)/soc/common/soc_common.o + +DIRS += $(OUT)/soc/MX8DXL +DIRS += $(OUT)/soc/common + diff --git a/platform/soc/MX8QM/Makefile b/platform/soc/MX8QM/Makefile new file mode 100755 index 0000000..3e8695d --- /dev/null +++ b/platform/soc/MX8QM/Makefile @@ -0,0 +1,7 @@ + +OBJS += $(OUT)/soc/MX8QM/soc.o +OBJS += $(OUT)/soc/common/soc_common.o + +DIRS += $(OUT)/soc/MX8QM +DIRS += $(OUT)/soc/common + diff --git a/platform/soc/MX8QX/Makefile b/platform/soc/MX8QX/Makefile new file mode 100755 index 0000000..7f837d9 --- /dev/null +++ b/platform/soc/MX8QX/Makefile @@ -0,0 +1,7 @@ + +OBJS += $(OUT)/soc/MX8QX/soc.o +OBJS += $(OUT)/soc/common/soc_common.o + +DIRS += $(OUT)/soc/MX8QX +DIRS += $(OUT)/soc/common + diff --git a/platform/ss/a35/v1/Makefile b/platform/ss/a35/v1/Makefile new file mode 100755 index 0000000..65a49d3 --- /dev/null +++ b/platform/ss/a35/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/a35/v1/ss.o + +CONFIGH += $(SRC)/ss/a35/v1/config.h $(SRC)/ss/a35/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/a35/v1/resource.txt + +CLK_MD += $(SRC)/ss/a35/v1/clock.txt + +CTRL_MD += $(SRC)/ss/a35/v1/control.txt + +DIRS += $(OUT)/ss/a35/v1 + diff --git a/platform/ss/a35/v1/dsc.h b/platform/ss/a35/v1/dsc.h new file mode 100755 index 0000000..b4e8e36 --- /dev/null +++ b/platform/ss/a35/v1/dsc.h @@ -0,0 +1,214 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup A35_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A35_DSC_H +#define SC_SS_A35_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_CORE0_POR REGBIT(0, 2) +#define RST_CORE1_POR REGBIT(0, 3) +#define RST_CORE2_POR REGBIT(0, 4) +#define RST_CORE3_POR REGBIT(0, 5) +#define RST_DEBUG REGBIT(0, 6) +#define RST_BIST REGBIT(0, 7) + +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_RESET_VECTOR REGBIT(0, 17) +#define GPR_L2_REQ REGBIT(0, 20) +#define GPR_L2_FLUSH_REQ REGBIT(0, 21) +#define GPR_L2_RST_INV_DISABLE REGBIT(0, 22) +#define GPR_DBG_L1_RST_DIS REGBIT(0, 23) +#define GPR_EDBG_RQ0 REGBIT(0, 24) +#define GPR_EDBG_RQ1 REGBIT(0, 25) +#define GPR_EDBG_RQ2 REGBIT(0, 26) +#define GPR_EDBG_RQ3 REGBIT(0, 27) +#define GPR_CLUSTERIDAFF1_0 REGBIT(0, 28) +#define GPR_CLUSTERIDAFF1_1 REGBIT(0, 29) +#define GPR_ADBGIC_PWRDNREQN REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_EVENTO_RESET REGBIT(1, 4) +#define GPR_NEON_REQ0 REGBIT(1, 8) +#define GPR_NEON_REQ1 REGBIT(1, 9) +#define GPR_NEON_REQ2 REGBIT(1, 10) +#define GPR_NEON_REQ3 REGBIT(1, 11) +#define GPR_CPUQ_REQ0 REGBIT(1, 12) +#define GPR_CPUQ_REQ1 REGBIT(1, 13) +#define GPR_CPUQ_REQ2 REGBIT(1, 14) +#define GPR_CPUQ_REQ3 REGBIT(1, 15) +#define GPR_RST_CORE0 REGBIT(1, 16) +#define GPR_RST_CORE1 REGBIT(1, 17) +#define GPR_RST_CORE2 REGBIT(1, 18) +#define GPR_RST_CORE3 REGBIT(1, 19) +#define GPR_DBG_PWRD_UP0 REGBIT(1, 20) +#define GPR_DBG_PWRD_UP1 REGBIT(1, 21) +#define GPR_DBG_PWRD_UP2 REGBIT(1, 22) +#define GPR_DBG_PWRD_UP3 REGBIT(1, 23) +#define GPR_EVENTI REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_L2_ACTIVE_A35 REGBIT(0, 24) +#define GPS_L2_DENY_A35 REGBIT(0, 25) +#define GPS_L2_ACCEPT_B_A35 REGBIT(0, 26) +#define GPS_L2_FLUSHDONE_A35 REGBIT(0, 27) +#define GPS_ADBGIC_PWRDNACKN REGBIT(0, 28) +#define GPS_EVENTO REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_CPUQ_DENY0 REGBIT(1, 0) +#define GPS_CPUQ_DENY1 REGBIT(1, 1) +#define GPS_CPUQ_DENY2 REGBIT(1, 2) +#define GPS_CPUQ_DENY3 REGBIT(1, 3) +#define GPS_CPUQ_ACCEPT_B0 REGBIT(1, 4) +#define GPS_CPUQ_ACCEPT_B1 REGBIT(1, 5) +#define GPS_CPUQ_ACCEPT_B2 REGBIT(1, 6) +#define GPS_CPUQ_ACCEPT_B3 REGBIT(1, 7) +#define GPS_NEON_ACTIVE0 REGBIT(1, 8) +#define GPS_NEON_ACTIVE1 REGBIT(1, 9) +#define GPS_NEON_ACTIVE2 REGBIT(1, 10) +#define GPS_NEON_ACTIVE3 REGBIT(1, 11) +#define GPS_NEON_DENY0 REGBIT(1, 12) +#define GPS_NEON_DENY1 REGBIT(1, 13) +#define GPS_NEON_DENY2 REGBIT(1, 14) +#define GPS_NEON_DENY3 REGBIT(1, 15) +#define GPS_NEON_ACCEPT0_B REGBIT(1, 16) +#define GPS_NEON_ACCEPT1_B REGBIT(1, 17) +#define GPS_NEON_ACCEPT2_B REGBIT(1, 18) +#define GPS_NEON_ACCEPT3_B REGBIT(1, 19) +#define GPS_CPUQ_ACTIVE0 REGBIT(1, 20) +#define GPS_CPUQ_ACTIVE1 REGBIT(1, 21) +#define GPS_CPUQ_ACTIVE2 REGBIT(1, 22) +#define GPS_CPUQ_ACTIVE3 REGBIT(1, 23) +#define GPS_STANDBYWFI0 REGBIT(1, 24) +#define GPS_STANDBYWFI1 REGBIT(1, 25) +#define GPS_STANDBYWFI2 REGBIT(1, 26) +#define GPS_STANDBYWFI3 REGBIT(1, 27) +#define GPS_STANDBYWFE0 REGBIT(1, 28) +#define GPS_STANDBYWFE1 REGBIT(1, 29) +#define GPS_STANDBYWFE2 REGBIT(1, 30) +#define GPS_STANDBYWFE3 REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 2 Bit Definitions + */ +/** @{ */ +#define GPS_DBG_RST_REQ0 REGBIT(2, 0) +#define GPS_DBG_RST_REQ1 REGBIT(2, 1) +#define GPS_DBG_RST_REQ2 REGBIT(2, 2) +#define GPS_DBG_RST_REQ3 REGBIT(2, 3) +#define GPS_DBG_NOPWRDWN0 REGBIT(2, 4) +#define GPS_DBG_NOPWRDWN1 REGBIT(2, 5) +#define GPS_DBG_NOPWRDWN2 REGBIT(2, 6) +#define GPS_DBG_NOPWRDWN3 REGBIT(2, 7) +#define GPS_DBG_PWR_UP_REQ0 REGBIT(2, 8) +#define GPS_DBG_PWR_UP_REQ1 REGBIT(2, 9) +#define GPS_DBG_PWR_UP_REQ2 REGBIT(2, 10) +#define GPS_DBG_PWR_UP_REQ3 REGBIT(2, 11) +#define GPS_DBG_ACK0 REGBIT(2, 12) +#define GPS_DBG_ACK1 REGBIT(2, 13) +#define GPS_DBG_ACK2 REGBIT(2, 14) +#define GPS_DBG_ACK3 REGBIT(2, 15) +#define GPS_WARM_RESET_REQ0 REGBIT(2, 16) +#define GPS_WARM_RESET_REQ1 REGBIT(2, 17) +#define GPS_WARM_RESET_REQ2 REGBIT(2, 18) +#define GPS_WARM_RESET_REQ3 REGBIT(2, 19) +#define GPS_STANDBYWFIL2_A35 REGBIT(2, 20) +#define GPS_CACTIVES_A35_GIC REGBIT(2, 21) +#define GPS_CACTIVEM_A35_GIC REGBIT(2, 22) +#define GPS_SMPEN0 REGBIT(2, 24) +#define GPS_SMPEN1 REGBIT(2, 25) +#define GPS_SMPEN2 REGBIT(2, 26) +#define GPS_SMPEN3 REGBIT(2, 27) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_EVENTO REGBIT64(1, 0) +#define IRQ_CLREXMONACK REGBIT64(1, 1) +#define IRQ_L2_FLUSHDONE REGBIT64(1, 2) +#define IRQ_L2_DENY REGBIT64(1, 7) +#define IRQ_L2_ACCEPT_B REGBIT64(1, 8) +#define IRQ_STANDBYWFI REGBIT64(1, 9) +#define IRQ_STANDBYWFIL2 REGBIT64(1, 13) +#define IRQ_DBG_ACK REGBIT64(1, 14) +#define IRQ_CA35_COMM_IRQ_B REGBIT64(1, 15) +#define IRQ_DBG_RST_REQ REGBIT64(1, 16) +#define IRQ_DBG_PWR_UP_REQ REGBIT64(1, 17) +#define IRQ_PWR_DN_ACKN_TO_GIC_SLV REGBIT64(1, 18) +#define IRQ_WARMRESETREQ REGBIT64(1, 20) + +/** @} */ + +#endif /* SC_SS_A35_DSC_H */ + +/** @} */ diff --git a/platform/ss/a35/v1/ss.h b/platform/ss/a35/v1/ss.h new file mode 100755 index 0000000..d32661b --- /dev/null +++ b/platform/ss/a35/v1/ss.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the A35 subsystem API. + * + * @addtogroup A35_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A35_SS_H +#define SC_SS_A35_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(a35) + +/* Functions */ + +SS_FUNC_PROTO_A35 + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_a35[]; + +#endif /* SC_SS_A35_SS_H */ + +/** @} */ + diff --git a/platform/ss/a35/v2/Makefile b/platform/ss/a35/v2/Makefile new file mode 100755 index 0000000..da971d8 --- /dev/null +++ b/platform/ss/a35/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/a35/v2/ss.o + +CONFIGH += $(SRC)/ss/a35/v2/config.h $(SRC)/ss/a35/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/a35/v2/resource.txt + +CLK_MD += $(SRC)/ss/a35/v2/clock.txt + +CTRL_MD += $(SRC)/ss/a35/v2/control.txt + +DIRS += $(OUT)/ss/a35/v2 + diff --git a/platform/ss/a35/v2/dsc.h b/platform/ss/a35/v2/dsc.h new file mode 100755 index 0000000..193b672 --- /dev/null +++ b/platform/ss/a35/v2/dsc.h @@ -0,0 +1,174 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup A35_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A35_DSC_H +#define SC_SS_A35_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_CORE0_POR REGBIT(0, 2) +#define RST_CORE1_POR REGBIT(0, 3) +#define RST_DEBUG REGBIT(0, 6) +#define RST_BIST REGBIT(0, 7) + +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_RESET_VECTOR REGBIT(0, 17) +#define GPR_L2_REQ REGBIT(0, 20) +#define GPR_L2_FLUSH_REQ REGBIT(0, 21) +#define GPR_L2_RST_INV_DISABLE REGBIT(0, 22) +#define GPR_DBG_L1_RST_DIS REGBIT(0, 23) +#define GPR_EDBG_RQ0 REGBIT(0, 24) +#define GPR_EDBG_RQ1 REGBIT(0, 25) +#define GPR_CLUSTERIDAFF1_0 REGBIT(0, 28) +#define GPR_CLUSTERIDAFF1_1 REGBIT(0, 29) +#define GPR_ADBGIC_PWRDNREQN REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_EVENTO_RESET REGBIT(1, 4) +#define GPR_NEON_REQ0 REGBIT(1, 8) +#define GPR_NEON_REQ1 REGBIT(1, 9) +#define GPR_CPUQ_REQ0 REGBIT(1, 12) +#define GPR_CPUQ_REQ1 REGBIT(1, 13) +#define GPR_RST_CORE0 REGBIT(1, 16) +#define GPR_RST_CORE1 REGBIT(1, 17) +#define GPR_DBG_PWRD_UP0 REGBIT(1, 20) +#define GPR_DBG_PWRD_UP1 REGBIT(1, 21) +#define GPR_EVENTI REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_L2_ACTIVE_A35 REGBIT(0, 24) +#define GPS_L2_DENY_A35 REGBIT(0, 25) +#define GPS_L2_ACCEPT_B_A35 REGBIT(0, 26) +#define GPS_L2_FLUSHDONE_A35 REGBIT(0, 27) +#define GPS_ADBGIC_PWRDNACKN REGBIT(0, 28) +#define GPS_EVENTO REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_CPUQ_DENY0 REGBIT(1, 0) +#define GPS_CPUQ_DENY1 REGBIT(1, 1) +#define GPS_CPUQ_ACCEPT_B0 REGBIT(1, 4) +#define GPS_CPUQ_ACCEPT_B1 REGBIT(1, 5) +#define GPS_NEON_ACTIVE0 REGBIT(1, 8) +#define GPS_NEON_ACTIVE1 REGBIT(1, 9) +#define GPS_NEON_DENY0 REGBIT(1, 12) +#define GPS_NEON_DENY1 REGBIT(1, 13) +#define GPS_NEON_ACCEPT0_B REGBIT(1, 16) +#define GPS_NEON_ACCEPT1_B REGBIT(1, 17) +#define GPS_CPUQ_ACTIVE0 REGBIT(1, 20) +#define GPS_CPUQ_ACTIVE1 REGBIT(1, 21) +#define GPS_STANDBYWFI0 REGBIT(1, 24) +#define GPS_STANDBYWFI1 REGBIT(1, 25) +#define GPS_STANDBYWFE0 REGBIT(1, 28) +#define GPS_STANDBYWFE1 REGBIT(1, 29) +/** @} */ + +/*! + * @name GPR Status 2 Bit Definitions + */ +/** @{ */ +#define GPS_DBG_RST_REQ0 REGBIT(2, 0) +#define GPS_DBG_RST_REQ1 REGBIT(2, 1) +#define GPS_DBG_NOPWRDWN0 REGBIT(2, 4) +#define GPS_DBG_NOPWRDWN1 REGBIT(2, 5) +#define GPS_DBG_PWR_UP_REQ0 REGBIT(2, 8) +#define GPS_DBG_PWR_UP_REQ1 REGBIT(2, 9) +#define GPS_DBG_ACK0 REGBIT(2, 12) +#define GPS_DBG_ACK1 REGBIT(2, 13) +#define GPS_WARM_RESET_REQ0 REGBIT(2, 16) +#define GPS_WARM_RESET_REQ1 REGBIT(2, 17) +#define GPS_STANDBYWFIL2_A35 REGBIT(2, 20) +#define GPS_CACTIVES_A35_GIC REGBIT(2, 21) +#define GPS_CACTIVEM_A35_GIC REGBIT(2, 22) +#define GPS_SMPEN0 REGBIT(2, 24) +#define GPS_SMPEN1 REGBIT(2, 25) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_EVENTO REGBIT64(1, 0) +#define IRQ_CLREXMONACK REGBIT64(1, 1) +#define IRQ_L2_FLUSHDONE REGBIT64(1, 2) +#define IRQ_L2_DENY REGBIT64(1, 7) +#define IRQ_L2_ACCEPT_B REGBIT64(1, 8) +#define IRQ_STANDBYWFI REGBIT64(1, 9) +#define IRQ_STANDBYWFIL2 REGBIT64(1, 13) +#define IRQ_DBG_ACK REGBIT64(1, 14) +#define IRQ_CA35_COMM_IRQ_B REGBIT64(1, 15) +#define IRQ_DBG_RST_REQ REGBIT64(1, 16) +#define IRQ_DBG_PWR_UP_REQ REGBIT64(1, 17) +#define IRQ_PWR_DN_ACKN_TO_GIC_SLV REGBIT64(1, 18) +#define IRQ_WARMRESETREQ REGBIT64(1, 20) + +/** @} */ + +#endif /* SC_SS_A35_DSC_H */ + +/** @} */ diff --git a/platform/ss/a35/v2/ss.h b/platform/ss/a35/v2/ss.h new file mode 100755 index 0000000..71c4a5b --- /dev/null +++ b/platform/ss/a35/v2/ss.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2018-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the A35 subsystem API. + * + * @addtogroup A35_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A35_SS_H +#define SC_SS_A35_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(a35) + +/* Functions */ + +SS_FUNC_PROTO_A35 + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_a35[]; + +#endif /* SC_SS_A35_SS_H */ + +/** @} */ + diff --git a/platform/ss/a53/v1/Makefile b/platform/ss/a53/v1/Makefile new file mode 100755 index 0000000..b00b64d --- /dev/null +++ b/platform/ss/a53/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/a53/v1/ss.o + +CONFIGH += $(SRC)/ss/a53/v1/config.h $(SRC)/ss/a53/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/a53/v1/resource.txt + +CLK_MD += $(SRC)/ss/a53/v1/clock.txt + +CTRL_MD += $(SRC)/ss/a53/v1/control.txt + +DIRS += $(OUT)/ss/a53/v1 + diff --git a/platform/ss/a53/v1/config.h b/platform/ss/a53/v1/config.h new file mode 100644 index 0000000..2a638a1 --- /dev/null +++ b/platform/ss/a53/v1/config.h @@ -0,0 +1,147 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the A53 subsystem. + * + * @addtogroup A53_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_A53_CONFIG_H +#define SC_SS_A53_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_A53 5U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_A53 \ + void ss_init_a53(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_set_cpu_power_mode_a53(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_power_mode_t mode, sc_pm_wake_src_t \ + wake_src); \ + sc_err_t ss_set_cpu_resume_a53(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); \ + sc_err_t ss_req_sys_if_power_mode_a53(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, \ + sc_pm_power_mode_t lpm); \ + sc_err_t ss_set_clock_rate_a53(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_cpu_start_a53(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); \ + void ss_rdc_set_master_a53(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + void ss_updown_a53(sc_sub_t ss, sc_bool_t up); \ + void ss_prepost_power_mode_a53(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + void ss_link_enable_a53(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_adb_enable_a53(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + void ss_adb_wait_a53(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_A53 \ + { \ + ss_init_a53, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_a53, \ + ss_set_cpu_resume_a53, \ + ss_req_sys_if_power_mode_a53, \ + ss_set_clock_rate_a53, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_a53, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_a53, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_a53, \ + ss_prepost_power_mode_a53, \ + ss_iso_disable_base, \ + ss_link_enable_a53, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_a53, \ + ss_adb_wait_a53, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_A53_0 \ + "A53_0", \ + "A53_1", \ + "A53_2", \ + "A53_3", \ + "A53", \ + +#endif + +#endif /* SC_SS_A53_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/a53/v1/dsc.h b/platform/ss/a53/v1/dsc.h new file mode 100755 index 0000000..9ea0cf9 --- /dev/null +++ b/platform/ss/a53/v1/dsc.h @@ -0,0 +1,218 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup A53_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A53_DSC_H +#define SC_SS_A53_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_CORE0_POR REGBIT(0, 2) +#define RST_CORE1_POR REGBIT(0, 3) +#define RST_CORE2_POR REGBIT(0, 4) +#define RST_CORE3_POR REGBIT(0, 5) +#define RST_DEBUG REGBIT(0, 6) +#define RST_BIST REGBIT(0, 7) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_BROADCAST_INNER REGBIT(0, 16) +#define GPR_RESET_VECTOR REGBIT(0, 17) +#define GPR_L2_REQ REGBIT(0, 20) +#define GPR_L2_FLUSH_REQ REGBIT(0, 21) +#define GPR_L2_RST_INV_DISABLE REGBIT(0, 22) +#define GPR_DBG_L1_RST_DIS REGBIT(0, 23) +#define GPR_EDBG_RQ0 REGBIT(0, 24) +#define GPR_EDBG_RQ1 REGBIT(0, 25) +#define GPR_EDBG_RQ2 REGBIT(0, 26) +#define GPR_EDBG_RQ3 REGBIT(0, 27) +#define GPR_CLUSTERIDAFF1_0 REGBIT(0, 28) +#define GPR_CLUSTERIDAFF1_1 REGBIT(0, 29) +#define GPR_SYSBARDENABLE REGBIT(0, 30) +#define GPR_ADBGIC_PWRDNREQN REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_ACINACTM REGBIT(1, 1) +#define GPR_EVENTO_RESET REGBIT(1, 4) +#define GPR_NEON_REQ0 REGBIT(1, 8) +#define GPR_NEON_REQ1 REGBIT(1, 9) +#define GPR_NEON_REQ2 REGBIT(1, 10) +#define GPR_NEON_REQ3 REGBIT(1, 11) +#define GPR_CPUQ_REQ0 REGBIT(1, 12) +#define GPR_CPUQ_REQ1 REGBIT(1, 13) +#define GPR_CPUQ_REQ2 REGBIT(1, 14) +#define GPR_CPUQ_REQ3 REGBIT(1, 15) +#define GPR_RST_CORE0 REGBIT(1, 16) +#define GPR_RST_CORE1 REGBIT(1, 17) +#define GPR_RST_CORE2 REGBIT(1, 18) +#define GPR_RST_CORE3 REGBIT(1, 19) +#define GPR_DBG_PWRD_UP0 REGBIT(1, 20) +#define GPR_DBG_PWRD_UP1 REGBIT(1, 21) +#define GPR_DBG_PWRD_UP2 REGBIT(1, 22) +#define GPR_DBG_PWRD_UP3 REGBIT(1, 23) +#define GPR_EVENTI REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_L2_ACTIVE_A53 REGBIT(0, 24) +#define GPS_L2_DENY_A53 REGBIT(0, 25) +#define GPS_L2_ACCEPT_B_A53 REGBIT(0, 26) +#define GPS_L2_FLUSHDONE_A53 REGBIT(0, 27) +#define GPS_ADBGIC_PWRDNACKN REGBIT(0, 28) +#define GPS_EVENTO REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_CPUQ_DENY0 REGBIT(1, 0) +#define GPS_CPUQ_DENY1 REGBIT(1, 1) +#define GPS_CPUQ_DENY2 REGBIT(1, 2) +#define GPS_CPUQ_DENY3 REGBIT(1, 3) +#define GPS_CPUQ_ACCEPT_B0 REGBIT(1, 4) +#define GPS_CPUQ_ACCEPT_B1 REGBIT(1, 5) +#define GPS_CPUQ_ACCEPT_B2 REGBIT(1, 6) +#define GPS_CPUQ_ACCEPT_B3 REGBIT(1, 7) +#define GPS_NEON_ACTIVE0 REGBIT(1, 8) +#define GPS_NEON_ACTIVE1 REGBIT(1, 9) +#define GPS_NEON_ACTIVE2 REGBIT(1, 10) +#define GPS_NEON_ACTIVE3 REGBIT(1, 11) +#define GPS_NEON_DENY0 REGBIT(1, 12) +#define GPS_NEON_DENY1 REGBIT(1, 13) +#define GPS_NEON_DENY2 REGBIT(1, 14) +#define GPS_NEON_DENY3 REGBIT(1, 15) +#define GPS_NEON_ACCEPT0_B REGBIT(1, 16) +#define GPS_NEON_ACCEPT1_B REGBIT(1, 17) +#define GPS_NEON_ACCEPT2_B REGBIT(1, 18) +#define GPS_NEON_ACCEPT3_B REGBIT(1, 19) +#define GPS_CPUQ_ACTIVE0 REGBIT(1, 20) +#define GPS_CPUQ_ACTIVE1 REGBIT(1, 21) +#define GPS_CPUQ_ACTIVE2 REGBIT(1, 22) +#define GPS_CPUQ_ACTIVE3 REGBIT(1, 23) +#define GPS_STANDBYWFI0 REGBIT(1, 24) +#define GPS_STANDBYWFI1 REGBIT(1, 25) +#define GPS_STANDBYWFI2 REGBIT(1, 26) +#define GPS_STANDBYWFI3 REGBIT(1, 27) +#define GPS_STANDBYWFE0 REGBIT(1, 28) +#define GPS_STANDBYWFE1 REGBIT(1, 29) +#define GPS_STANDBYWFE2 REGBIT(1, 30) +#define GPS_STANDBYWFE3 REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 2 Bit Definitions + */ +/** @{ */ +#define GPS_DBG_RST_REQ0 REGBIT(2, 0) +#define GPS_DBG_RST_REQ1 REGBIT(2, 1) +#define GPS_DBG_RST_REQ2 REGBIT(2, 2) +#define GPS_DBG_RST_REQ3 REGBIT(2, 3) +#define GPS_DBG_NOPWRDWN0 REGBIT(2, 4) +#define GPS_DBG_NOPWRDWN1 REGBIT(2, 5) +#define GPS_DBG_NOPWRDWN2 REGBIT(2, 6) +#define GPS_DBG_NOPWRDWN3 REGBIT(2, 7) +#define GPS_DBG_PWR_UP_REQ0 REGBIT(2, 8) +#define GPS_DBG_PWR_UP_REQ1 REGBIT(2, 9) +#define GPS_DBG_PWR_UP_REQ2 REGBIT(2, 10) +#define GPS_DBG_PWR_UP_REQ3 REGBIT(2, 11) +#define GPS_DBG_ACK0 REGBIT(2, 12) +#define GPS_DBG_ACK1 REGBIT(2, 13) +#define GPS_DBG_ACK2 REGBIT(2, 14) +#define GPS_DBG_ACK3 REGBIT(2, 15) +#define GPS_WARM_RESET_REQ0 REGBIT(2, 16) +#define GPS_WARM_RESET_REQ1 REGBIT(2, 17) +#define GPS_WARM_RESET_REQ2 REGBIT(2, 18) +#define GPS_WARM_RESET_REQ3 REGBIT(2, 19) +#define GPS_STANDBYWFIL2_A53 REGBIT(2, 20) +#define GPS_CACTIVES_A53_GIC REGBIT(2, 21) +#define GPS_CACTIVEM_A53_GIC REGBIT(2, 22) +#define GPS_SMPEN0 REGBIT(2, 24) +#define GPS_SMPEN1 REGBIT(2, 25) +#define GPS_SMPEN2 REGBIT(2, 26) +#define GPS_SMPEN3 REGBIT(2, 27) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_EVENTO REGBIT64(1, 0) +#define IRQ_CLREXMONACK REGBIT64(1, 1) +#define IRQ_L2_FLUSHDONE REGBIT64(1, 2) +#define IRQ_NEON_DENY REGBIT64(1, 3) +#define IRQ_NEON_ACCEPT_B REGBIT64(1, 4) +#define IRQ_CPUQ_DENY REGBIT64(1, 5) +#define IRQ_CPUQ_ACCEPT_B REGBIT64(1, 6) +#define IRQ_L2_DENY REGBIT64(1, 7) +#define IRQ_L2_ACCEPT_B REGBIT64(1, 8) +#define IRQ_STANDBYWFI REGBIT64(1, 9) +#define IRQ_STANDBYWFIL2 REGBIT64(1, 13) +#define IRQ_DBG_ACK REGBIT64(1, 14) +#define IRQ_CA53_COMM_IRQ_B REGBIT64(1, 15) +#define IRQ_DBG_RST_REQ REGBIT64(1, 16) +#define IRQ_DBG_PWR_UP_REQ REGBIT64(1, 17) +#define IRQ_PWR_DN_ACKN_TO_GIC_SLV REGBIT64(1, 18) +/** @} */ + +#endif /* SC_SS_A53_DSC_H */ + +/** @} */ diff --git a/platform/ss/a53/v1/rsrc.h b/platform/ss/a53/v1/rsrc.h new file mode 100644 index 0000000..a23475c --- /dev/null +++ b/platform/ss/a53/v1/rsrc.h @@ -0,0 +1,66 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the A53 subsystem. + * + * @addtogroup A53_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_A53_RSRC_H +#define SC_SS_A53_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_A53_0 0U +#define SS_R_A53_1 1U +#define SS_R_A53_2 2U +#define SS_R_A53_3 3U +#define SS_R_A53 4U +/** @} */ + +#endif /* SC_SS_A53_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/a53/v1/ss.h b/platform/ss/a53/v1/ss.h new file mode 100755 index 0000000..3a48346 --- /dev/null +++ b/platform/ss/a53/v1/ss.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the A53 subsystem API. + * + * @addtogroup A53_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A53_SS_H +#define SC_SS_A53_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(a53) + +/* Functions */ + +SS_FUNC_PROTO_A53 + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_a53[]; + +#endif /* SC_SS_A53_SS_H */ + +/** @} */ + diff --git a/platform/ss/a72/v1/Makefile b/platform/ss/a72/v1/Makefile new file mode 100755 index 0000000..0e5efcf --- /dev/null +++ b/platform/ss/a72/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/a72/v1/ss.o + +CONFIGH += $(SRC)/ss/a72/v1/config.h $(SRC)/ss/a72/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/a72/v1/resource.txt + +CLK_MD += $(SRC)/ss/a72/v1/clock.txt + +CTRL_MD += $(SRC)/ss/a72/v1/control.txt + +DIRS += $(OUT)/ss/a72/v1 + diff --git a/platform/ss/a72/v1/config.h b/platform/ss/a72/v1/config.h new file mode 100644 index 0000000..bb6613e --- /dev/null +++ b/platform/ss/a72/v1/config.h @@ -0,0 +1,145 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the A72 subsystem. + * + * @addtogroup A72_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_A72_CONFIG_H +#define SC_SS_A72_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_A72 3U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_A72 \ + void ss_init_a72(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_set_cpu_power_mode_a72(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_power_mode_t mode, sc_pm_wake_src_t \ + wake_src); \ + sc_err_t ss_set_cpu_resume_a72(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); \ + sc_err_t ss_req_sys_if_power_mode_a72(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, \ + sc_pm_power_mode_t lpm); \ + sc_err_t ss_set_clock_rate_a72(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_cpu_start_a72(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); \ + void ss_rdc_set_master_a72(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + void ss_updown_a72(sc_sub_t ss, sc_bool_t up); \ + void ss_prepost_power_mode_a72(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + void ss_link_enable_a72(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_adb_enable_a72(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + void ss_adb_wait_a72(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_A72 \ + { \ + ss_init_a72, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_a72, \ + ss_set_cpu_resume_a72, \ + ss_req_sys_if_power_mode_a72, \ + ss_set_clock_rate_a72, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_a72, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_a72, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_a72, \ + ss_prepost_power_mode_a72, \ + ss_iso_disable_base, \ + ss_link_enable_a72, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_a72, \ + ss_adb_wait_a72, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_A72_0 \ + "A72_0", \ + "A72_1", \ + "A72", \ + +#endif + +#endif /* SC_SS_A72_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/a72/v1/dsc.h b/platform/ss/a72/v1/dsc.h new file mode 100755 index 0000000..300093d --- /dev/null +++ b/platform/ss/a72/v1/dsc.h @@ -0,0 +1,172 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup A72_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A72_DSC_H +#define SC_SS_A72_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_CORE0_POR REGBIT(0, 2) +#define RST_CORE1_POR REGBIT(0, 3) +#define RST_DEBUG REGBIT(0, 6) + +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_BROADCAST_INNER REGBIT(0, 16) +#define GPR_RESET_VECTOR REGBIT(0, 17) +#define GPR_L2_REQ REGBIT(0, 20) +#define GPR_L2_FLUSH_REQ REGBIT(0, 21) +#define GPR_L2_RST_INV_DISABLE REGBIT(0, 22) +#define GPR_DBG_L1_RST_DIS REGBIT(0, 23) +#define GPR_EDBG_RQ0 REGBIT(0, 24) +#define GPR_EDBG_RQ1 REGBIT(0, 25) +#define GPR_CLUSTERIDAFF1_0 REGBIT(0, 28) +#define GPR_CLUSTERIDAFF1_1 REGBIT(0, 29) +#define GPR_SYSBARDENABLE REGBIT(0, 30) +#define GPR_ADBGIC_PWRDNREQN REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @} */ +#define GPR_ADB_PWRDNREQN REGBIT(1, 32) +#define GPR_ACINACTM REGBIT(1, 33) +#define GPR_EVENTO_RESET REGBIT(1, 36) +#define GPR_CPUQ_REQ0 REGBIT(1, 44) +#define GPR_CPUQ_REQ1 REGBIT(1, 45) +#define GPR_RST_CORE0 REGBIT(1, 48) +#define GPR_RST_CORE1 REGBIT(1, 49) +#define GPR_DBG_PWRD_UP0 REGBIT(1, 52) +#define GPR_DBG_PWRD_UP1 REGBIT(1, 53) +#define GPR_EVENTI REGBIT(1, 63) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_L2_ACTIVE_A72 REGBIT(0, 24) +#define GPS_L2_DENY_A72 REGBIT(0, 25) +#define GPS_L2_ACCEPT_B_A72 REGBIT(0, 26) +#define GPS_L2_FLUSHDONE_A72 REGBIT(0, 27) +#define GPS_ADBGIC_PWRDNACKN REGBIT(0, 28) +#define GPS_ADBACE_PWRDNACKN REGBIT(0, 29) +#define GPS_EVENTO REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_CPUQ_DENY0 REGBIT(1, 32) +#define GPS_CPUQ_DENY1 REGBIT(1, 33) +#define GPS_CPUQ_ACCEPT_B0 REGBIT(1, 36) +#define GPS_CPUQ_ACCEPT_B1 REGBIT(1, 37) +#define GPS_CPUQ_ACTIVE0 REGBIT(1, 52) +#define GPS_CPUQ_ACTIVE1 REGBIT(1, 53) +#define GPS_STANDBYWFI0 REGBIT(1, 56) +#define GPS_STANDBYWFI1 REGBIT(1, 57) +#define GPS_STANDBYWFE0 REGBIT(1, 60) +#define GPS_STANDBYWFE1 REGBIT(1, 61) +/** @} */ + +/*! + * @name GPR Status 2 Bit Definitions + */ +/** @{ */ +#define GPS_DBG_RST_REQ0 REGBIT(2, 64) +#define GPS_DBG_RST_REQ1 REGBIT(2, 65) +#define GPS_DBG_NOPWRDWN0 REGBIT(2, 68) +#define GPS_DBG_NOPWRDWN1 REGBIT(2, 69) +#define GPS_DBG_PWR_UP_REQ0 REGBIT(2, 72) +#define GPS_DBG_PWR_UP_REQ1 REGBIT(2, 73) +#define GPS_DBG_ACK0 REGBIT(2, 76) +#define GPS_DBG_ACK1 REGBIT(2, 77) +#define GPS_WARM_RESET_REQ0 REGBIT(2, 80) +#define GPS_WARM_RESET_REQ1 REGBIT(2, 81) +#define GPS_STANDBYWFIL2_A72 REGBIT(2, 84) +#define GPS_CACTIVES_A72_GIC REGBIT(2, 85) +#define GPS_CACTIVEM_A72_GIC REGBIT(2, 86) +#define GPS_CACTIVES_ACE REGBIT(2, 87) +#define GPS_SMPEN0 REGBIT(2, 88) +#define GPS_SMPEN1 REGBIT(2, 89) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_EVENTO REGBIT64(1, 0) +#define IRQ_CLREXMONACK REGBIT64(1, 1) +#define IRQ_L2_FLUSHDONE REGBIT64(1, 2) +#define IRQ_CPUQ_DENY REGBIT64(1, 5) +#define IRQ_CPUQ_ACCEPT_B REGBIT64(1, 6) +#define IRQ_L2_DENY REGBIT64(1, 7) +#define IRQ_L2_ACCEPT_B REGBIT64(1, 8) +#define IRQ_STANDBYWFI REGBIT64(1, 9) +#define IRQ_STANDBYWFIL2 REGBIT64(1, 13) +#define IRQ_DBG_ACK REGBIT64(1, 14) +#define IRQ_CA72_COMM_IRQ_B REGBIT64(1, 15) +#define IRQ_DBG_RST_REQ REGBIT64(1, 16) +#define IRQ_DBG_PWR_UP_REQ REGBIT64(1, 17) +#define IRQ_PWR_DN_ACKN_TO_GIC_SLV REGBIT64(1, 18) +#define IRQ_ADBACE_PWRDNACKN REGBIT64(1, 19) +/** @} */ + +#endif /* SC_SS_A72_DSC_H */ + +/** @} */ diff --git a/platform/ss/a72/v1/rsrc.h b/platform/ss/a72/v1/rsrc.h new file mode 100644 index 0000000..d39be4b --- /dev/null +++ b/platform/ss/a72/v1/rsrc.h @@ -0,0 +1,64 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the A72 subsystem. + * + * @addtogroup A72_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_A72_RSRC_H +#define SC_SS_A72_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_A72_0 0U +#define SS_R_A72_1 1U +#define SS_R_A72 2U +/** @} */ + +#endif /* SC_SS_A72_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/a72/v1/ss.h b/platform/ss/a72/v1/ss.h new file mode 100755 index 0000000..1e47dd3 --- /dev/null +++ b/platform/ss/a72/v1/ss.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the A72 subsystem API. + * + * @addtogroup A72_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_A72_SS_H +#define SC_SS_A72_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(a72) + +/* Functions */ + +SS_FUNC_PROTO_A72 + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_a72[]; + +#endif /* SC_SS_A72_SS_H */ + +/** @} */ + diff --git a/platform/ss/adma/v2/Makefile b/platform/ss/adma/v2/Makefile new file mode 100755 index 0000000..aecb3e9 --- /dev/null +++ b/platform/ss/adma/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/adma/v2/ss.o + +CONFIGH += $(SRC)/ss/adma/v2/config.h $(SRC)/ss/adma/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/adma/v2/resource.txt + +CLK_MD += $(SRC)/ss/adma/v2/clock.txt + +CTRL_MD += $(SRC)/ss/adma/v2/control.txt + +DIRS += $(OUT)/ss/adma/v2 + diff --git a/platform/ss/adma/v2/dsc.h b/platform/ss/adma/v2/dsc.h new file mode 100755 index 0000000..205bba4 --- /dev/null +++ b/platform/ss/adma/v2/dsc.h @@ -0,0 +1,385 @@ +/* +** ################################################################### +** +** Copyright 2018-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup ADMA_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_ADMA_DSC_H +#define SC_SS_ADMA_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_SS_DSP REGBIT(0, 2) +#define RST_SS_DSP_CORE REGBIT(0, 3) +#define RST_SS_DSP_DEBUG REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_OBS_SEL0 REGBIT(0, 8) +#define GPR_OBS_SEL1 REGBIT(0, 9) +#define GPR_OBS_SEL2 REGBIT(0, 10) +#define GPR_OBS_SEL3 REGBIT(0, 11) +#define GPR_SYS_OFFSET_AUD_ALT REGBIT(0, 16) +#define GPR_ADB_GIC_PWRDNREQN REGBIT(0, 24) +#define GPR_ADB_DSP_PWRDNREQN0 REGBIT(0, 25) +#define GPR_ADB_DSP_PWRDNREQN1 REGBIT(0, 26) +#define GPR_DSP_CACHE_SEL REGBIT(0, 27) +#define GPR_DSP_CACHEABLE REGBIT(0, 28) +#define GPR_LCDIF_CACHEABLE REGBIT(0, 29) +#define GPR_AUDIO_EDMA_CACHEABLE REGBIT(0, 30) +#define GPR_PERIPH_EDMA_CACHEABLE REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_DMA_CLOCK_RATIO0 REGBIT(1, 32) +#define GPR_DMA_CLOCK_RATIO1 REGBIT(1, 33) +#define GPR_DMA_CLOCK_RATIO_ENB REGBIT(1, 34) +#define GPR_DSP_DMA_BYPASS REGBIT(1, 35) +#define GPR_DMA01_DSP_BYPASS REGBIT(1, 36) +#define GPR_DMA23_DSP_BYPASS REGBIT(1, 37) +#define GPR_PIXEL_RATE_CORR REGBIT(1, 38) +#define GPR_SYS_OFFSET_SEL REGBIT(1, 39) +#define GPR_SYS_OFFSET_AUD REGBIT(1, 40) +#define GPR_SYS_OFFSET_DMA REGBIT(1, 48) +#define GPR_SYS_OFFSET_GIC REGBIT(1, 56) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_ADB_GIC_PWRDNACKN REGBIT(0, 16) +#define GPS_ADB_GIC_CACTIVES REGBIT(0, 17) +#define GPS_ADB_GIC_CACTIVEM REGBIT(0, 18) +#define GPS_ADB_DSP_PWRDNACKN0 REGBIT(0, 25) +#define GPS_ADB_DSP_CACTIVES0 REGBIT(0, 26) +#define GPS_ADB_DSP_CACTIVEM0 REGBIT(0, 27) +#define GPS_ADB_DSP_PWRDNACKN1 REGBIT(0, 29) +#define GPS_ADB_DSP_CACTIVES1 REGBIT(0, 30) +#define GPS_ADB_DSP_CACTIVEM1 REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_OBS_OUT REGBIT(1, 32) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GIC_WAKE00 REGBIT64(1, 0) +#define IRQ_GIC_WAKE01 REGBIT64(1, 1) +#define IRQ_GIC_WAKE02 REGBIT64(1, 2) +#define IRQ_GIC_WAKE03 REGBIT64(1, 3) +#define IRQ_IRQSTR_CTI0 REGBIT64(1, 8) +#define IRQ_IRQSTR_CTI1 REGBIT64(1, 9) +#define IRQ_IRQSTR_CTI2 REGBIT64(1, 10) +#define IRQ_IRQSTR_CTI3 REGBIT64(1, 11) +#define IRQ_IRQSTR_CTI4 REGBIT64(1, 12) +#define IRQ_GIC_ECC_FATAL REGBIT64(1, 13) +#define IRQ_LPI2C0 REGBIT64(1, 15) +#define IRQ_LPI2C1 REGBIT64(1, 16) +#define IRQ_LPI2C2 REGBIT64(1, 17) +#define IRQ_LPI2C3 REGBIT64(1, 18) +#define IRQ_LPSPI0 REGBIT64(1, 19) +#define IRQ_LPSPI1 REGBIT64(1, 20) +#define IRQ_LPSPI2 REGBIT64(1, 21) +#define IRQ_LPSPI3 REGBIT64(1, 22) +#define IRQ_LPUART0 REGBIT64(1, 23) +#define IRQ_LPUART1 REGBIT64(1, 24) +#define IRQ_LPUART2 REGBIT64(1, 25) +#define IRQ_LPUART3 REGBIT64(1, 26) +#define IRQ_ADC0 REGBIT64(1, 27) +/** @} */ + +/*! + * @name CSR2 0x00 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_EXPSTATE REGBIT(0x0, 0) +/** @} */ + +/*! + * @name CSR2 0x01 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_IMPWIRE REGBIT(0x1, 0) +/** @} */ + +/*! + * @name CSR2 0x02 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_PRID REGBIT(0x2, 0) +/** @} */ + +/*! + * @name CSR2 0x30 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_OCDHALTONRESET REGBIT(0x3, 0) +#define CSR2_DSP_RUNSTALL REGBIT(0x3, 1) +#define CSR2_DSP_STATVECTORSEL REGBIT(0x3, 2) +/** @} */ + +/*! + * @name CSR2 0x40 Bit Definitions + */ +/** @{ */ +/** @} */ + +/*! + * @name CSR3 0x00 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA2_IPG_DEBUG REGBIT(0x0, 0) +#define CSR3_EDMA3_IPG_DEBUG REGBIT(0x0, 1) +#define CSR3_SPI0_IPG_DEBUG REGBIT(0x0, 3) +#define CSR3_SPI1_IPG_DEBUG REGBIT(0x0, 4) +#define CSR3_SPI2_IPG_DEBUG REGBIT(0x0, 5) +#define CSR3_SPI3_IPG_DEBUG REGBIT(0x0, 6) +#define CSR3_I2C0_IPG_DEBUG REGBIT(0x0, 17) +#define CSR3_I2C1_IPG_DEBUG REGBIT(0x0, 18) +#define CSR3_I2C2_IPG_DEBUG REGBIT(0x0, 19) +#define CSR3_I2C3_IPG_DEBUG REGBIT(0x0, 20) +#define CSR3_FTM0_IPG_DEBUG REGBIT(0x0, 26) +#define CSR3_FTM1_IPG_DEBUG REGBIT(0x0, 27) +#define CSR3_CAN0_IPG_DEBUG REGBIT(0x0, 29) +#define CSR3_CAN1_IPG_DEBUG REGBIT(0x0, 30) +#define CSR3_CAN2_IPG_DEBUG REGBIT(0x0, 31) +/** @} */ + +/*! + * @name CSR3 0x10 Bit Definitions + */ +/** @{ */ +#define CSR3_SPI0_IPG_DOZE REGBIT(0x1, 3) +#define CSR3_SPI1_IPG_DOZE REGBIT(0x1, 4) +#define CSR3_SPI2_IPG_DOZE REGBIT(0x1, 5) +#define CSR3_SPI3_IPG_DOZE REGBIT(0x1, 6) +#define CSR3_UART0_IPG_DOZE REGBIT(0x1, 8) +#define CSR3_UART1_IPG_DOZE REGBIT(0x1, 9) +#define CSR3_UART2_IPG_DOZE REGBIT(0x1, 10) +#define CSR3_UART3_IPG_DOZE REGBIT(0x1, 11) +#define CSR3_I2C0_IPG_DOZE REGBIT(0x1, 17) +#define CSR3_I2C1_IPG_DOZE REGBIT(0x1, 18) +#define CSR3_I2C2_IPG_DOZE REGBIT(0x1, 19) +#define CSR3_I2C3_IPG_DOZE REGBIT(0x1, 20) +#define CSR3_ADC0_IPG_DOZE REGBIT(0x1, 23) +#define CSR3_CAN0_IPG_DOZE REGBIT(0x1, 29) +#define CSR3_CAN1_IPG_DOZE REGBIT(0x1, 30) +#define CSR3_CAN2_IPG_DOZE REGBIT(0x1, 31) +/** @} */ + +/*! + * @name CSR3 0x20 Bit Definitions + */ +/** @{ */ +#define CSR3_SPI0_IPG_STOP_MODE REGBIT(0x2, 3) +#define CSR3_SPI1_IPG_STOP_MODE REGBIT(0x2, 4) +#define CSR3_SPI2_IPG_STOP_MODE REGBIT(0x2, 5) +#define CSR3_SPI3_IPG_STOP_MODE REGBIT(0x2, 6) +#define CSR3_UART0_IPG_STOP_MODE REGBIT(0x2, 8) +#define CSR3_UART1_IPG_STOP_MODE REGBIT(0x2, 9) +#define CSR3_UART2_IPG_STOP_MODE REGBIT(0x2, 10) +#define CSR3_UART3_IPG_STOP_MODE REGBIT(0x2, 11) +#define CSR3_I2C0_IPG_STOP_MODE REGBIT(0x2, 17) +#define CSR3_I2C1_IPG_STOP_MODE REGBIT(0x2, 18) +#define CSR3_I2C2_IPG_STOP_MODE REGBIT(0x2, 19) +#define CSR3_I2C3_IPG_STOP_MODE REGBIT(0x2, 20) +/** @} */ + +/*! + * @name CSR3 0x30 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA2_IPG_STOP REGBIT(0x3, 0) +#define CSR3_EDMA3_IPG_STOP REGBIT(0x3, 1) +#define CSR3_SPI0_IPG_STOP REGBIT(0x3, 3) +#define CSR3_SPI1_IPG_STOP REGBIT(0x3, 4) +#define CSR3_SPI2_IPG_STOP REGBIT(0x3, 5) +#define CSR3_SPI3_IPG_STOP REGBIT(0x3, 6) +#define CSR3_UART0_IPG_STOP REGBIT(0x3, 8) +#define CSR3_UART1_IPG_STOP REGBIT(0x3, 9) +#define CSR3_UART2_IPG_STOP REGBIT(0x3, 10) +#define CSR3_UART3_IPG_STOP REGBIT(0x3, 11) +#define CSR3_I2C0_IPG_STOP REGBIT(0x3, 17) +#define CSR3_I2C1_IPG_STOP REGBIT(0x3, 18) +#define CSR3_I2C2_IPG_STOP REGBIT(0x3, 19) +#define CSR3_I2C3_IPG_STOP REGBIT(0x3, 20) +#define CSR3_ADC0_IPG_STOP REGBIT(0x3, 23) +#define CSR3_CAN0_IPG_STOP REGBIT(0x3, 29) +#define CSR3_CAN1_IPG_STOP REGBIT(0x3, 30) +#define CSR3_CAN2_IPG_STOP REGBIT(0x3, 31) +/** @} */ + +/*! + * @name CSR3 0x40 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA2_IPG_STOP_ACK REGBIT(0x4, 0) +#define CSR3_EDMA3_IPG_STOP_ACK REGBIT(0x4, 1) +#define CSR3_SPI0_IPG_STOP_ACK REGBIT(0x4, 3) +#define CSR3_SPI1_IPG_STOP_ACK REGBIT(0x4, 4) +#define CSR3_SPI2_IPG_STOP_ACK REGBIT(0x4, 5) +#define CSR3_SPI3_IPG_STOP_ACK REGBIT(0x4, 6) +#define CSR3_UART0_IPG_STOP_ACK REGBIT(0x4, 8) +#define CSR3_UART1_IPG_STOP_ACK REGBIT(0x4, 9) +#define CSR3_UART2_IPG_STOP_ACK REGBIT(0x4, 10) +#define CSR3_UART3_IPG_STOP_ACK REGBIT(0x4, 11) +#define CSR3_I2C0_IPG_STOP_ACK REGBIT(0x4, 17) +#define CSR3_I2C1_IPG_STOP_ACK REGBIT(0x4, 18) +#define CSR3_I2C2_IPG_STOP_ACK REGBIT(0x4, 19) +#define CSR3_I2C3_IPG_STOP_ACK REGBIT(0x4, 20) +#define CSR3_ADC0_IPG_STOP_ACK REGBIT(0x4, 23) +#define CSR3_CAN0_IPG_STOP_ACK REGBIT(0x4, 29) +#define CSR3_CAN1_IPG_STOP_ACK REGBIT(0x4, 30) +#define CSR3_CAN2_IPG_STOP_ACK REGBIT(0x4, 31) +/** @} */ + +/*! + * @name CSR3 0x80 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_DEBUG REGBIT(0x8, 0) +#define CSR3_EDMA1_IPG_DEBUG REGBIT(0x8, 1) +#define CSR3_GPT0_IPG_DEBUG REGBIT(0x8, 2) +#define CSR3_GPT1_IPG_DEBUG REGBIT(0x8, 3) +#define CSR3_GPT2_IPG_DEBUG REGBIT(0x8, 4) +#define CSR3_GPT3_IPG_DEBUG REGBIT(0x8, 5) +#define CSR3_GPT4_IPG_DEBUG REGBIT(0x8, 6) +#define CSR3_GPT5_IPG_DEBUG REGBIT(0x8, 7) +#define CSR3_SAI0_IPG_DEBUG REGBIT(0x8, 8) +#define CSR3_SAI1_IPG_DEBUG REGBIT(0x8, 9) +#define CSR3_SAI2_IPG_DEBUG REGBIT(0x8, 10) +#define CSR3_SAI3_IPG_DEBUG REGBIT(0x8, 11) +#define CSR3_SAI4_IPG_DEBUG REGBIT(0x8, 12) +#define CSR3_SAI5_IPG_DEBUG REGBIT(0x8, 13) +#define CSR3_PWM_IPG_DEBUG REGBIT(0x8, 16) +/** @} */ + +/*! + * @name CSR3 0x90 Bit Definitions + */ +/** @{ */ +#define CSR3_GPT0_IPG_DOZE REGBIT(0x9, 2) +#define CSR3_GPT1_IPG_DOZE REGBIT(0x9, 3) +#define CSR3_GPT2_IPG_DOZE REGBIT(0x9, 4) +#define CSR3_GPT3_IPG_DOZE REGBIT(0x9, 5) +#define CSR3_GPT4_IPG_DOZE REGBIT(0x9, 6) +#define CSR3_GPT5_IPG_DOZE REGBIT(0x9, 7) +#define CSR3_PWM_IPG_DOZE REGBIT(0x9, 16) +/** @} */ + +/*! + * @name CSR3 0xA0 Bit Definitions + */ +/** @{ */ +#define CSR3_GPT0_IPG_WAIT REGBIT(0xA, 2) +#define CSR3_GPT1_IPG_WAIT REGBIT(0xA, 3) +#define CSR3_GPT2_IPG_WAIT REGBIT(0xA, 4) +#define CSR3_GPT3_IPG_WAIT REGBIT(0xA, 5) +#define CSR3_GPT4_IPG_WAIT REGBIT(0xA, 6) +#define CSR3_GPT5_IPG_WAIT REGBIT(0xA, 7) +#define CSR3_SAI0_IPG_STOP_MODE REGBIT(0xA, 8) +#define CSR3_SAI1_IPG_STOP_MODE REGBIT(0xA, 9) +#define CSR3_SAI2_IPG_STOP_MODE REGBIT(0xA, 10) +#define CSR3_SAI3_IPG_STOP_MODE REGBIT(0xA, 11) +#define CSR3_SAI4_IPG_STOP_MODE REGBIT(0xA, 12) +#define CSR3_SAI5_IPG_STOP_MODE REGBIT(0xA, 13) +#define CSR3_PWM_IPG_WAIT REGBIT(0xA, 16) +/** @} */ + +/*! + * @name CSR3 0xB0 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP REGBIT(0xB, 0) +#define CSR3_EDMA1_IPG_STOP REGBIT(0xB, 1) +#define CSR3_GPT0_IPG_STOP REGBIT(0xB, 2) +#define CSR3_GPT1_IPG_STOP REGBIT(0xB, 3) +#define CSR3_GPT2_IPG_STOP REGBIT(0xB, 4) +#define CSR3_GPT3_IPG_STOP REGBIT(0xB, 5) +#define CSR3_GPT4_IPG_STOP REGBIT(0xB, 6) +#define CSR3_GPT5_IPG_STOP REGBIT(0xB, 7) +#define CSR3_SAI0_IPG_STOP REGBIT(0xB, 8) +#define CSR3_SAI1_IPG_STOP REGBIT(0xB, 9) +#define CSR3_SAI2_IPG_STOP REGBIT(0xB, 10) +#define CSR3_SAI3_IPG_STOP REGBIT(0xB, 11) +#define CSR3_SAI4_IPG_STOP REGBIT(0xB, 12) +#define CSR3_SAI5_IPG_STOP REGBIT(0xB, 13) +#define CSR3_PWM_IPG_STOP REGBIT(0xB, 16) +/** @} */ + +/*! + * @name CSR3 0xC0 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP_ACK REGBIT(0xC, 0) +#define CSR3_EDMA1_IPG_STOP_ACK REGBIT(0xC, 1) +#define CSR3_SAI0_IPG_STOP_ACK REGBIT(0xC, 8) +#define CSR3_SAI1_IPG_STOP_ACK REGBIT(0xC, 9) +#define CSR3_SAI2_IPG_STOP_ACK REGBIT(0xC, 10) +#define CSR3_SAI3_IPG_STOP_ACK REGBIT(0xC, 11) +#define CSR3_SAI4_IPG_STOP_ACK REGBIT(0xC, 12) +#define CSR3_SAI5_IPG_STOP_ACK REGBIT(0xC, 13) +/** @} */ + +#endif /* SC_SS_ADMA_DSC_H */ + +/** @} */ + diff --git a/platform/ss/adma/v2/ss.h b/platform/ss/adma/v2/ss.h new file mode 100755 index 0000000..50ee2fc --- /dev/null +++ b/platform/ss/adma/v2/ss.h @@ -0,0 +1,66 @@ +/* +** ################################################################### +** +** Copyright 2018-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the ADMA subsystem API. + * + * @addtogroup ADMA_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_ADMA_SS_H +#define SC_SS_ADMA_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(adma) + +/* Functions */ + +SS_FUNC_PROTO_ADMA + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_adma[]; + +#endif /* SC_SS_ADMA_SS_H */ + +/** @} */ + diff --git a/platform/ss/adma/v3/Makefile b/platform/ss/adma/v3/Makefile new file mode 100755 index 0000000..eb305b8 --- /dev/null +++ b/platform/ss/adma/v3/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/adma/v3/ss.o + +CONFIGH += $(SRC)/ss/adma/v3/config.h $(SRC)/ss/adma/v3/rsrc.h + +RSRC_MD += $(SRC)/ss/adma/v3/resource.txt + +CLK_MD += $(SRC)/ss/adma/v3/clock.txt + +CTRL_MD += $(SRC)/ss/adma/v3/control.txt + +DIRS += $(OUT)/ss/adma/v3 + diff --git a/platform/ss/adma/v3/dsc.h b/platform/ss/adma/v3/dsc.h new file mode 100755 index 0000000..9b5548e --- /dev/null +++ b/platform/ss/adma/v3/dsc.h @@ -0,0 +1,387 @@ +/* +** ################################################################### +** +** Copyright 2018-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup ADMA_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_ADMA_DSC_H +#define SC_SS_ADMA_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_SS_DSP REGBIT(0, 2) +#define RST_SS_DSP_CORE REGBIT(0, 3) +#define RST_SS_DSP_DEBUG REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_OBS_SEL0 REGBIT(0, 8) +#define GPR_OBS_SEL1 REGBIT(0, 9) +#define GPR_OBS_SEL2 REGBIT(0, 10) +#define GPR_OBS_SEL3 REGBIT(0, 11) +#define GPR_ADB_GIC_PWRDNREQN REGBIT(0, 24) +#define GPR_ADB_DSP_PWRDNREQN0 REGBIT(0, 25) +#define GPR_ADB_DSP_PWRDNREQN1 REGBIT(0, 26) +#define GPR_LCDIF_CACHEABLE REGBIT(0, 29) +#define GPR_AUDIO_EDMA_CACHEABLE REGBIT(0, 30) +#define GPR_PERIPH_EDMA_CACHEABLE REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_DMA_CLOCK_RATIO0 REGBIT(1, 32) +#define GPR_DMA_CLOCK_RATIO1 REGBIT(1, 33) +#define GPR_DMA_CLOCK_RATIO_ENB REGBIT(1, 34) +#define GPR_DSP_DMA_BYPASS REGBIT(1, 35) +#define GPR_DMA01_DSP_BYPASS REGBIT(1, 36) +#define GPR_DMA23_DSP_BYPASS REGBIT(1, 37) +#define GPR_PIXEL_RATE_CORR REGBIT(1, 38) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_ADB_GIC_PWRDNACKN REGBIT(0, 16) +#define GPS_ADB_GIC_CACTIVES REGBIT(0, 17) +#define GPS_ADB_GIC_CACTIVEM REGBIT(0, 18) +#define GPS_ADB_DSP_PWRDNACKN0 REGBIT(0, 25) +#define GPS_ADB_DSP_CACTIVES0 REGBIT(0, 26) +#define GPS_ADB_DSP_CACTIVEM0 REGBIT(0, 27) +#define GPS_ADB_DSP_PWRDNACKN1 REGBIT(0, 29) +#define GPS_ADB_DSP_CACTIVES1 REGBIT(0, 30) +#define GPS_ADB_DSP_CACTIVEM1 REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_OBS_OUT REGBIT(1, 32) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GIC_WAKE00 REGBIT64(1, 0) +#define IRQ_GIC_WAKE01 REGBIT64(1, 1) +#define IRQ_GIC_WAKE02 REGBIT64(1, 2) +#define IRQ_GIC_WAKE03 REGBIT64(1, 3) +#define IRQ_IRQSTR_CTI0 REGBIT64(1, 8) +#define IRQ_IRQSTR_CTI1 REGBIT64(1, 9) +#define IRQ_IRQSTR_CTI2 REGBIT64(1, 10) +#define IRQ_IRQSTR_CTI3 REGBIT64(1, 11) +#define IRQ_IRQSTR_CTI4 REGBIT64(1, 12) +#define IRQ_GIC_ECC_FATAL REGBIT64(1, 13) +#define IRQ_LPI2C0 REGBIT64(1, 15) +#define IRQ_LPI2C1 REGBIT64(1, 16) +#define IRQ_LPI2C2 REGBIT64(1, 17) +#define IRQ_LPI2C3 REGBIT64(1, 18) +#define IRQ_LPSPI0 REGBIT64(1, 19) +#define IRQ_LPSPI1 REGBIT64(1, 20) +#define IRQ_LPSPI2 REGBIT64(1, 21) +#define IRQ_LPSPI3 REGBIT64(1, 22) +#define IRQ_LPUART0 REGBIT64(1, 23) +#define IRQ_LPUART1 REGBIT64(1, 24) +#define IRQ_LPUART2 REGBIT64(1, 25) +#define IRQ_LPUART3 REGBIT64(1, 26) +#define IRQ_ADC0 REGBIT64(1, 27) +/** @} */ + +/*! + * @name CSR2 0x00 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_EXPSTATE REGBIT(0x0, 0) +/** @} */ + +/*! + * @name CSR2 0x01 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_IMPWIRE REGBIT(0x1, 0) +/** @} */ + +/*! + * @name CSR2 0x02 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_PRID REGBIT(0x2, 0) +/** @} */ + +/*! + * @name CSR2 0x30 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_OCDHALTONRESET REGBIT(0x3, 0) +#define CSR2_DSP_RUNSTALL REGBIT(0x3, 1) +#define CSR2_DSP_STATVECTORSEL REGBIT(0x3, 2) +/** @} */ + +/*! + * @name CSR2 0x40 Bit Definitions + */ +/** @{ */ +/** @} */ + +/*! + * @name CSR3 0x00 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA2_IPG_DEBUG REGBIT(0x0, 0) +#define CSR3_EDMA3_IPG_DEBUG REGBIT(0x0, 1) +#define CSR3_SPI0_IPG_DEBUG REGBIT(0x0, 3) +#define CSR3_SPI1_IPG_DEBUG REGBIT(0x0, 4) +#define CSR3_SPI2_IPG_DEBUG REGBIT(0x0, 5) +#define CSR3_SPI3_IPG_DEBUG REGBIT(0x0, 6) +#define CSR3_I2C0_IPG_DEBUG REGBIT(0x0, 17) +#define CSR3_I2C1_IPG_DEBUG REGBIT(0x0, 18) +#define CSR3_I2C2_IPG_DEBUG REGBIT(0x0, 19) +#define CSR3_I2C3_IPG_DEBUG REGBIT(0x0, 20) +#define CSR3_FTM0_IPG_DEBUG REGBIT(0x0, 26) +#define CSR3_FTM1_IPG_DEBUG REGBIT(0x0, 27) +#define CSR3_CAN0_IPG_DEBUG REGBIT(0x0, 29) +#define CSR3_CAN1_IPG_DEBUG REGBIT(0x0, 30) +#define CSR3_CAN2_IPG_DEBUG REGBIT(0x0, 31) +/** @} */ + +/*! + * @name CSR3 0x10 Bit Definitions + */ +/** @{ */ +#define CSR3_SPI0_IPG_DOZE REGBIT(0x1, 3) +#define CSR3_SPI1_IPG_DOZE REGBIT(0x1, 4) +#define CSR3_SPI2_IPG_DOZE REGBIT(0x1, 5) +#define CSR3_SPI3_IPG_DOZE REGBIT(0x1, 6) +#define CSR3_UART0_IPG_DOZE REGBIT(0x1, 8) +#define CSR3_UART1_IPG_DOZE REGBIT(0x1, 9) +#define CSR3_UART2_IPG_DOZE REGBIT(0x1, 10) +#define CSR3_UART3_IPG_DOZE REGBIT(0x1, 11) +#define CSR3_I2C0_IPG_DOZE REGBIT(0x1, 17) +#define CSR3_I2C1_IPG_DOZE REGBIT(0x1, 18) +#define CSR3_I2C2_IPG_DOZE REGBIT(0x1, 19) +#define CSR3_I2C3_IPG_DOZE REGBIT(0x1, 20) +#define CSR3_ADC0_IPG_DOZE REGBIT(0x1, 23) +#define CSR3_CAN0_IPG_DOZE REGBIT(0x1, 29) +#define CSR3_CAN1_IPG_DOZE REGBIT(0x1, 30) +#define CSR3_CAN2_IPG_DOZE REGBIT(0x1, 31) +/** @} */ + +/*! + * @name CSR3 0x20 Bit Definitions + */ +/** @{ */ +#define CSR3_SPI0_IPG_STOP_MODE REGBIT(0x2, 3) +#define CSR3_SPI1_IPG_STOP_MODE REGBIT(0x2, 4) +#define CSR3_SPI2_IPG_STOP_MODE REGBIT(0x2, 5) +#define CSR3_SPI3_IPG_STOP_MODE REGBIT(0x2, 6) +#define CSR3_UART0_IPG_STOP_MODE REGBIT(0x2, 8) +#define CSR3_UART1_IPG_STOP_MODE REGBIT(0x2, 9) +#define CSR3_UART2_IPG_STOP_MODE REGBIT(0x2, 10) +#define CSR3_UART3_IPG_STOP_MODE REGBIT(0x2, 11) +#define CSR3_I2C0_IPG_STOP_MODE REGBIT(0x2, 17) +#define CSR3_I2C1_IPG_STOP_MODE REGBIT(0x2, 18) +#define CSR3_I2C2_IPG_STOP_MODE REGBIT(0x2, 19) +#define CSR3_I2C3_IPG_STOP_MODE REGBIT(0x2, 20) +/** @} */ + +/*! + * @name CSR3 0x30 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA2_IPG_STOP REGBIT(0x3, 0) +#define CSR3_EDMA3_IPG_STOP REGBIT(0x3, 1) +#define CSR3_SPI0_IPG_STOP REGBIT(0x3, 3) +#define CSR3_SPI1_IPG_STOP REGBIT(0x3, 4) +#define CSR3_SPI2_IPG_STOP REGBIT(0x3, 5) +#define CSR3_SPI3_IPG_STOP REGBIT(0x3, 6) +#define CSR3_UART0_IPG_STOP REGBIT(0x3, 8) +#define CSR3_UART1_IPG_STOP REGBIT(0x3, 9) +#define CSR3_UART2_IPG_STOP REGBIT(0x3, 10) +#define CSR3_UART3_IPG_STOP REGBIT(0x3, 11) +#define CSR3_I2C0_IPG_STOP REGBIT(0x3, 17) +#define CSR3_I2C1_IPG_STOP REGBIT(0x3, 18) +#define CSR3_I2C2_IPG_STOP REGBIT(0x3, 19) +#define CSR3_I2C3_IPG_STOP REGBIT(0x3, 20) +#define CSR3_ADC0_IPG_STOP REGBIT(0x3, 23) +#define CSR3_CAN0_IPG_STOP REGBIT(0x3, 29) +#define CSR3_CAN1_IPG_STOP REGBIT(0x3, 30) +#define CSR3_CAN2_IPG_STOP REGBIT(0x3, 31) +/** @} */ + +/*! + * @name CSR3 0x40 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA2_IPG_STOP_ACK REGBIT(0x4, 0) +#define CSR3_EDMA3_IPG_STOP_ACK REGBIT(0x4, 1) +#define CSR3_SPI0_IPG_STOP_ACK REGBIT(0x4, 3) +#define CSR3_SPI1_IPG_STOP_ACK REGBIT(0x4, 4) +#define CSR3_SPI2_IPG_STOP_ACK REGBIT(0x4, 5) +#define CSR3_SPI3_IPG_STOP_ACK REGBIT(0x4, 6) +#define CSR3_UART0_IPG_STOP_ACK REGBIT(0x4, 8) +#define CSR3_UART1_IPG_STOP_ACK REGBIT(0x4, 9) +#define CSR3_UART2_IPG_STOP_ACK REGBIT(0x4, 10) +#define CSR3_UART3_IPG_STOP_ACK REGBIT(0x4, 11) +#define CSR3_I2C0_IPG_STOP_ACK REGBIT(0x4, 17) +#define CSR3_I2C1_IPG_STOP_ACK REGBIT(0x4, 18) +#define CSR3_I2C2_IPG_STOP_ACK REGBIT(0x4, 19) +#define CSR3_I2C3_IPG_STOP_ACK REGBIT(0x4, 20) +#define CSR3_ADC0_IPG_STOP_ACK REGBIT(0x4, 23) +#define CSR3_CAN0_IPG_STOP_ACK REGBIT(0x4, 29) +#define CSR3_CAN1_IPG_STOP_ACK REGBIT(0x4, 30) +#define CSR3_CAN2_IPG_STOP_ACK REGBIT(0x4, 31) +/** @} */ + +/*! + * @name CSR3 0x80 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_DEBUG REGBIT(0x8, 0) +#define CSR3_EDMA1_IPG_DEBUG REGBIT(0x8, 1) +#define CSR3_GPT0_IPG_DEBUG REGBIT(0x8, 2) +#define CSR3_GPT1_IPG_DEBUG REGBIT(0x8, 3) +#define CSR3_GPT2_IPG_DEBUG REGBIT(0x8, 4) +#define CSR3_GPT3_IPG_DEBUG REGBIT(0x8, 5) +#define CSR3_GPT4_IPG_DEBUG REGBIT(0x8, 6) +#define CSR3_GPT5_IPG_DEBUG REGBIT(0x8, 7) +#define CSR3_SAI0_IPG_DEBUG REGBIT(0x8, 8) +#define CSR3_SAI1_IPG_DEBUG REGBIT(0x8, 9) +#define CSR3_SAI2_IPG_DEBUG REGBIT(0x8, 10) +#define CSR3_SAI3_IPG_DEBUG REGBIT(0x8, 11) +#define CSR3_SAI4_IPG_DEBUG REGBIT(0x8, 12) +#define CSR3_SAI5_IPG_DEBUG REGBIT(0x8, 13) +#define CSR3_PWM_IPG_DEBUG REGBIT(0x8, 16) +/** @} */ + +/*! + * @name CSR3 0x90 Bit Definitions + */ +/** @{ */ +#define CSR3_GPT0_IPG_DOZE REGBIT(0x9, 2) +#define CSR3_GPT1_IPG_DOZE REGBIT(0x9, 3) +#define CSR3_GPT2_IPG_DOZE REGBIT(0x9, 4) +#define CSR3_GPT3_IPG_DOZE REGBIT(0x9, 5) +#define CSR3_GPT4_IPG_DOZE REGBIT(0x9, 6) +#define CSR3_GPT5_IPG_DOZE REGBIT(0x9, 7) +#define CSR3_PWM_IPG_DOZE REGBIT(0x9, 16) +/** @} */ + +/*! + * @name CSR3 0xA0 Bit Definitions + */ +/** @{ */ +#define CSR3_GPT0_IPG_WAIT REGBIT(0xA, 2) +#define CSR3_GPT1_IPG_WAIT REGBIT(0xA, 3) +#define CSR3_GPT2_IPG_WAIT REGBIT(0xA, 4) +#define CSR3_GPT3_IPG_WAIT REGBIT(0xA, 5) +#define CSR3_GPT4_IPG_WAIT REGBIT(0xA, 6) +#define CSR3_GPT5_IPG_WAIT REGBIT(0xA, 7) +#define CSR3_SAI0_IPG_STOP_MODE REGBIT(0xA, 8) +#define CSR3_SAI1_IPG_STOP_MODE REGBIT(0xA, 9) +#define CSR3_SAI2_IPG_STOP_MODE REGBIT(0xA, 10) +#define CSR3_SAI3_IPG_STOP_MODE REGBIT(0xA, 11) +#define CSR3_SAI4_IPG_STOP_MODE REGBIT(0xA, 12) +#define CSR3_SAI5_IPG_STOP_MODE REGBIT(0xA, 13) +#define CSR3_PWM_IPG_WAIT REGBIT(0xA, 16) +/** @} */ + +/*! + * @name CSR3 0xB0 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP REGBIT(0xB, 0) +#define CSR3_EDMA1_IPG_STOP REGBIT(0xB, 1) +#define CSR3_GPT0_IPG_STOP REGBIT(0xB, 2) +#define CSR3_GPT1_IPG_STOP REGBIT(0xB, 3) +#define CSR3_GPT2_IPG_STOP REGBIT(0xB, 4) +#define CSR3_GPT3_IPG_STOP REGBIT(0xB, 5) +#define CSR3_GPT4_IPG_STOP REGBIT(0xB, 6) +#define CSR3_GPT5_IPG_STOP REGBIT(0xB, 7) +#define CSR3_SAI0_IPG_STOP REGBIT(0xB, 8) +#define CSR3_SAI1_IPG_STOP REGBIT(0xB, 9) +#define CSR3_SAI2_IPG_STOP REGBIT(0xB, 10) +#define CSR3_SAI3_IPG_STOP REGBIT(0xB, 11) +#define CSR3_SAI4_IPG_STOP REGBIT(0xB, 12) +#define CSR3_SAI5_IPG_STOP REGBIT(0xB, 13) +#define CSR3_PWM_IPG_STOP REGBIT(0xB, 16) +/** @} */ + +/*! + * @name CSR3 0xC0 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP_ACK REGBIT(0xC, 0) +#define CSR3_EDMA1_IPG_STOP_ACK REGBIT(0xC, 1) +#define CSR3_SAI0_IPG_STOP_ACK REGBIT(0xC, 8) +#define CSR3_SAI1_IPG_STOP_ACK REGBIT(0xC, 9) +#define CSR3_SAI2_IPG_STOP_ACK REGBIT(0xC, 10) +#define CSR3_SAI3_IPG_STOP_ACK REGBIT(0xC, 11) +#define CSR3_SAI4_IPG_STOP_ACK REGBIT(0xC, 12) +#define CSR3_SAI5_IPG_STOP_ACK REGBIT(0xC, 13) +/** @} */ + +#if (defined(FSL_FEATURE_DSC_HAS_PER_RESET) && FSL_FEATURE_DSC_HAS_PER_RESET) +/*! + * @name ECSR 0x00 Reset Bit Definitions + */ +/** @{ */ +#define CSR_GIC_RESET REGBIT(0x0, 0) +/** @} */ +#endif + +#endif /* SC_SS_ADMA_DSC_H */ + +/** @} */ + diff --git a/platform/ss/adma/v3/ss.h b/platform/ss/adma/v3/ss.h new file mode 100755 index 0000000..50ee2fc --- /dev/null +++ b/platform/ss/adma/v3/ss.h @@ -0,0 +1,66 @@ +/* +** ################################################################### +** +** Copyright 2018-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the ADMA subsystem API. + * + * @addtogroup ADMA_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_ADMA_SS_H +#define SC_SS_ADMA_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(adma) + +/* Functions */ + +SS_FUNC_PROTO_ADMA + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_adma[]; + +#endif /* SC_SS_ADMA_SS_H */ + +/** @} */ + diff --git a/platform/ss/audio/v1/Makefile b/platform/ss/audio/v1/Makefile new file mode 100755 index 0000000..737d8f0 --- /dev/null +++ b/platform/ss/audio/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/audio/v1/ss.o + +CONFIGH += $(SRC)/ss/audio/v1/config.h $(SRC)/ss/audio/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/audio/v1/resource.txt + +CLK_MD += $(SRC)/ss/audio/v1/clock.txt + +CTRL_MD += $(SRC)/ss/audio/v1/control.txt + +DIRS += $(OUT)/ss/audio/v1 + diff --git a/platform/ss/audio/v1/config.h b/platform/ss/audio/v1/config.h new file mode 100644 index 0000000..08c82c3 --- /dev/null +++ b/platform/ss/audio/v1/config.h @@ -0,0 +1,214 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the AUDIO subsystem. + * + * @addtogroup AUDIO_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_AUDIO_CONFIG_H +#define SC_SS_AUDIO_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_AUDIO 92U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_AUDIO \ + sc_err_t ss_set_control_audio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + void ss_updown_audio(sc_sub_t ss, sc_bool_t up); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_AUDIO \ + { \ + ss_init_base, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_audio, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_audio, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_AUDIO_0 \ + "ASRC_0", \ + "ESAI_0", \ + "SPDIF_0", \ + "SPDIF_1", \ + "SAI_0", \ + "SAI_1", \ + "SAI_2", \ + "SAI_3", \ + "SAI_4", \ + "SAI_5", \ + "GPT_5", \ + "GPT_6", \ + "GPT_7", \ + "GPT_8", \ + "GPT_9", \ + "GPT_10", \ + "DMA_2_CH0", \ + "DMA_2_CH1", \ + "DMA_2_CH2", \ + "DMA_2_CH3", \ + "DMA_2_CH4", \ + "DMA_2_CH5", \ + "DMA_2_CH6", \ + "DMA_2_CH7", \ + "DMA_2_CH8", \ + "DMA_2_CH9", \ + "DMA_2_CH10", \ + "DMA_2_CH11", \ + "DMA_2_CH12", \ + "DMA_2_CH13", \ + "DMA_2_CH14", \ + "DMA_2_CH15", \ + "DMA_2_CH16", \ + "DMA_2_CH17", \ + "DMA_2_CH18", \ + "DMA_2_CH19", \ + "DMA_2_CH20", \ + "DMA_2_CH21", \ + "DMA_2_CH22", \ + "DMA_2_CH23", \ + "DMA_2_CH24", \ + "DMA_2_CH25", \ + "DMA_2_CH26", \ + "DMA_2_CH27", \ + "DMA_2_CH28", \ + "DMA_2_CH29", \ + "DMA_2_CH30", \ + "DMA_2_CH31", \ + "ASRC_1", \ + "ESAI_1", \ + "SAI_6", \ + "SAI_7", \ + "AMIX", \ + "MQS_0", \ + "DMA_3_CH0", \ + "DMA_3_CH1", \ + "DMA_3_CH2", \ + "DMA_3_CH3", \ + "DMA_3_CH4", \ + "DMA_3_CH5", \ + "DMA_3_CH6", \ + "DMA_3_CH7", \ + "DMA_3_CH8", \ + "DMA_3_CH9", \ + "DMA_3_CH10", \ + "DMA_3_CH11", \ + "DMA_3_CH12", \ + "DMA_3_CH13", \ + "DMA_3_CH14", \ + "DMA_3_CH15", \ + "DMA_3_CH16", \ + "DMA_3_CH17", \ + "DMA_3_CH18", \ + "DMA_3_CH19", \ + "DMA_3_CH20", \ + "DMA_3_CH21", \ + "DMA_3_CH22", \ + "DMA_3_CH23", \ + "DMA_3_CH24", \ + "DMA_3_CH25", \ + "DMA_3_CH26", \ + "DMA_3_CH27", \ + "DMA_3_CH28", \ + "DMA_3_CH29", \ + "DMA_3_CH30", \ + "DMA_3_CH31", \ + "AUDIO_PLL_0", \ + "AUDIO_PLL_1", \ + "AUDIO_CLK_0", \ + "AUDIO_CLK_1", \ + "MCLK_OUT_0", \ + "MCLK_OUT_1", \ + +#endif + +#endif /* SC_SS_AUDIO_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/audio/v1/dsc.h b/platform/ss/audio/v1/dsc.h new file mode 100755 index 0000000..2963661 --- /dev/null +++ b/platform/ss/audio/v1/dsc.h @@ -0,0 +1,103 @@ +/* +** ################################################################### +** +** Copyright (c) 2016-2019 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup AUDIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_AUDIO_DSC_H +#define SC_SS_AUDIO_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_EDMA_IPDA_CHICKEN_OUT0 REGBIT(1, 32) +#define GPR_EDMA_IPDA_CHICKEN_OUT1 REGBIT(1, 33) +#define GPR_EDMA_IPDA_CHICKEN_OUT2 REGBIT(1, 34) +#define GPR_EDMA_IPDA_CHICKEN_OUT3 REGBIT(1, 35) +#define GPR_EDMA_IPDA_CHICKEN_OUT4 REGBIT(1, 36) +#define GPR_EDMA_IPDA_CHICKEN_OUT5 REGBIT(1, 37) +#define GPR_EDMA_IPDA_CHICKEN_OUT6 REGBIT(1, 38) +#define GPR_EDMA_IPDA_CHICKEN_OUT7 REGBIT(1, 39) +#define GPR_EDMA_IPDA_CHICKEN_OUT8 REGBIT(1, 40) +#define GPR_EDMA_IPDA_CHICKEN_OUT9 REGBIT(1, 41) +#define GPR_EDMA_IPDA_CHICKEN_OUT10 REGBIT(1, 42) +#define GPR_EDMA_IPDA_CHICKEN_OUT11 REGBIT(1, 43) +#define GPR_EDMA_IPDA_CHICKEN_OUT12 REGBIT(1, 44) +#define GPR_EDMA_IPDA_CHICKEN_OUT13 REGBIT(1, 45) +#define GPR_EDMA_IPDA_CHICKEN_OUT14 REGBIT(1, 46) +#define GPR_EDMA_IPDA_CHICKEN_OUT15 REGBIT(1, 47) +#define GPR_EDMA_IPDA_CHICKEN_OUT16 REGBIT(1, 48) +#define GPR_EDMA_IPDA_CHICKEN_OUT17 REGBIT(1, 49) +#define GPR_EDMA_IPDA_CHICKEN_OUT18 REGBIT(1, 50) +#define GPR_EDMA_IPDA_CHICKEN_OUT19 REGBIT(1, 51) +#define GPR_EDMA_IPDA_CHICKEN_OUT20 REGBIT(1, 52) +#define GPR_EDMA_IPDA_CHICKEN_OUT21 REGBIT(1, 53) +#define GPR_EDMA_IPDA_CHICKEN_OUT22 REGBIT(1, 54) +#define GPR_EDMA_IPDA_CHICKEN_OUT23 REGBIT(1, 55) +#define GPR_EDMA_IPDA_CHICKEN_OUT24 REGBIT(1, 56) +#define GPR_EDMA_IPDA_CHICKEN_OUT25 REGBIT(1, 57) +#define GPR_EDMA_IPDA_CHICKEN_OUT26 REGBIT(1, 58) +#define GPR_EDMA_IPDA_CHICKEN_OUT27 REGBIT(1, 59) +#define GPR_EDMA_IPDA_CHICKEN_OUT28 REGBIT(1, 60) +#define GPR_EDMA_IPDA_CHICKEN_OUT29 REGBIT(1, 61) +#define GPR_EDMA_IPDA_CHICKEN_OUT30 REGBIT(1, 62) +#define GPR_EDMA_IPDA_CHICKEN_OUT31 REGBIT(1, 63) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_DMA0_IPG_STOP_ACK REGBIT(1, 0) +#define GPS_DMA1_IPG_STOP_ACK REGBIT(1, 1) +/** @} */ + +#endif /* SC_SS_AUDIO_DSC_H */ + +/** @} */ + diff --git a/platform/ss/audio/v1/rsrc.h b/platform/ss/audio/v1/rsrc.h new file mode 100644 index 0000000..29ed836 --- /dev/null +++ b/platform/ss/audio/v1/rsrc.h @@ -0,0 +1,153 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the AUDIO subsystem. + * + * @addtogroup AUDIO_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_AUDIO_RSRC_H +#define SC_SS_AUDIO_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_ASRC_0 0U +#define SS_R_ESAI_0 1U +#define SS_R_SPDIF_0 2U +#define SS_R_SPDIF_1 3U +#define SS_R_SAI_0 4U +#define SS_R_SAI_1 5U +#define SS_R_SAI_2 6U +#define SS_R_SAI_3 7U +#define SS_R_SAI_4 8U +#define SS_R_SAI_5 9U +#define SS_R_GPT_5 10U +#define SS_R_GPT_6 11U +#define SS_R_GPT_7 12U +#define SS_R_GPT_8 13U +#define SS_R_GPT_9 14U +#define SS_R_GPT_10 15U +#define SS_R_DMA_2_CH0 16U +#define SS_R_DMA_2_CH1 17U +#define SS_R_DMA_2_CH2 18U +#define SS_R_DMA_2_CH3 19U +#define SS_R_DMA_2_CH4 20U +#define SS_R_DMA_2_CH5 21U +#define SS_R_DMA_2_CH6 22U +#define SS_R_DMA_2_CH7 23U +#define SS_R_DMA_2_CH8 24U +#define SS_R_DMA_2_CH9 25U +#define SS_R_DMA_2_CH10 26U +#define SS_R_DMA_2_CH11 27U +#define SS_R_DMA_2_CH12 28U +#define SS_R_DMA_2_CH13 29U +#define SS_R_DMA_2_CH14 30U +#define SS_R_DMA_2_CH15 31U +#define SS_R_DMA_2_CH16 32U +#define SS_R_DMA_2_CH17 33U +#define SS_R_DMA_2_CH18 34U +#define SS_R_DMA_2_CH19 35U +#define SS_R_DMA_2_CH20 36U +#define SS_R_DMA_2_CH21 37U +#define SS_R_DMA_2_CH22 38U +#define SS_R_DMA_2_CH23 39U +#define SS_R_DMA_2_CH24 40U +#define SS_R_DMA_2_CH25 41U +#define SS_R_DMA_2_CH26 42U +#define SS_R_DMA_2_CH27 43U +#define SS_R_DMA_2_CH28 44U +#define SS_R_DMA_2_CH29 45U +#define SS_R_DMA_2_CH30 46U +#define SS_R_DMA_2_CH31 47U +#define SS_R_ASRC_1 48U +#define SS_R_ESAI_1 49U +#define SS_R_SAI_6 50U +#define SS_R_SAI_7 51U +#define SS_R_AMIX 52U +#define SS_R_MQS_0 53U +#define SS_R_DMA_3_CH0 54U +#define SS_R_DMA_3_CH1 55U +#define SS_R_DMA_3_CH2 56U +#define SS_R_DMA_3_CH3 57U +#define SS_R_DMA_3_CH4 58U +#define SS_R_DMA_3_CH5 59U +#define SS_R_DMA_3_CH6 60U +#define SS_R_DMA_3_CH7 61U +#define SS_R_DMA_3_CH8 62U +#define SS_R_DMA_3_CH9 63U +#define SS_R_DMA_3_CH10 64U +#define SS_R_DMA_3_CH11 65U +#define SS_R_DMA_3_CH12 66U +#define SS_R_DMA_3_CH13 67U +#define SS_R_DMA_3_CH14 68U +#define SS_R_DMA_3_CH15 69U +#define SS_R_DMA_3_CH16 70U +#define SS_R_DMA_3_CH17 71U +#define SS_R_DMA_3_CH18 72U +#define SS_R_DMA_3_CH19 73U +#define SS_R_DMA_3_CH20 74U +#define SS_R_DMA_3_CH21 75U +#define SS_R_DMA_3_CH22 76U +#define SS_R_DMA_3_CH23 77U +#define SS_R_DMA_3_CH24 78U +#define SS_R_DMA_3_CH25 79U +#define SS_R_DMA_3_CH26 80U +#define SS_R_DMA_3_CH27 81U +#define SS_R_DMA_3_CH28 82U +#define SS_R_DMA_3_CH29 83U +#define SS_R_DMA_3_CH30 84U +#define SS_R_DMA_3_CH31 85U +#define SS_R_AUDIO_PLL_0 86U +#define SS_R_AUDIO_PLL_1 87U +#define SS_R_AUDIO_CLK_0 88U +#define SS_R_AUDIO_CLK_1 89U +#define SS_R_MCLK_OUT_0 90U +#define SS_R_MCLK_OUT_1 91U +/** @} */ + +#endif /* SC_SS_AUDIO_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/audio/v1/ss.h b/platform/ss/audio/v1/ss.h new file mode 100755 index 0000000..7807300 --- /dev/null +++ b/platform/ss/audio/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the AUDIO subsystem API. + * + * @addtogroup AUDIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_AUDIO_SS_H +#define SC_SS_AUDIO_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(audio) + +/* Functions */ + +SS_FUNC_PROTO_AUDIO + +#endif /* SC_SS_AUDIO_SS_H */ + +/** @} */ + diff --git a/platform/ss/base/v1/Makefile b/platform/ss/base/v1/Makefile new file mode 100755 index 0000000..b533599 --- /dev/null +++ b/platform/ss/base/v1/Makefile @@ -0,0 +1,9 @@ + +OBJS += $(OUT)/ss/base/v1/ss.o $(OUT)/ss/base/ss_common.o + +CONFIGH += $(SRC)/ss/base/v1/config.h + +DIRS += $(OUT)/ss/base/v1 + +DOX_ADD_COMMON += $(SRC)/ss/base/ss_common.c + diff --git a/platform/ss/base/v1/config.h b/platform/ss/base/v1/config.h new file mode 100644 index 0000000..029be6d --- /dev/null +++ b/platform/ss/base/v1/config.h @@ -0,0 +1,193 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the BASE subsystem. + * + * @addtogroup BASE_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_BASE_CONFIG_H +#define SC_SS_BASE_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_BASE 0 + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_BASE \ + void ss_init_base(sc_sub_t ss, sc_bool_t api_phase); \ + void ss_trans_power_mode_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + sc_err_t ss_rsrc_reset_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_rm_pt_t pt, sc_bool_t pre); \ + sc_err_t ss_set_cpu_power_mode_base(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_power_mode_t mode, sc_pm_wake_src_t \ + wake_src); \ + sc_err_t ss_set_cpu_resume_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); \ + sc_err_t ss_req_sys_if_power_mode_base(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, \ + sc_pm_power_mode_t lpm); \ + sc_err_t ss_set_clock_rate_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_get_clock_rate_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_clock_enable_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); \ + sc_err_t ss_force_clock_enable_base(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable); \ + sc_err_t ss_set_clock_parent_base(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t \ + new_parent); \ + sc_err_t ss_get_clock_parent_base(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); \ + sc_bool_t ss_is_rsrc_accessible_base(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx); \ + void ss_mu_irq_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t rsrc_idx, \ + uint32_t mask); \ + sc_err_t ss_cpu_start_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); \ + void ss_rdc_enable_base(sc_sub_t ss, sc_bool_t master); \ + void ss_rdc_set_master_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + void ss_rdc_set_peripheral_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, const sc_rm_perm_t \ + *perms, sc_bool_t no_update); \ + sc_err_t ss_rdc_set_memory_base(sc_sub_t ss, sc_faddr_t start, \ + sc_faddr_t end, sc_bool_t valid, const sc_rm_perm_t *perms, \ + sc_rm_det_t det, sc_rm_rmsg_t rmsg, sc_faddr_t new_start, \ + sc_faddr_t new_end); \ + sc_err_t ss_set_control_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + sc_err_t ss_get_control_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t *val); \ + sc_err_t ss_irq_enable_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t mask, sc_bool_t enable); \ + sc_err_t ss_irq_status_base(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t *status); \ + void ss_irq_trigger_base(sc_sub_t ss, sc_irq_group_t group, uint32_t \ + irq, sc_rm_pt_t pt); \ + void ss_dump_base(sc_sub_t ss, sc_bool_t xrdc, sc_bool_t dsc, sc_bool_t \ + clk); \ + void ss_do_mem_repair_base(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t \ + enable); \ + void ss_updown_base(sc_sub_t ss, sc_bool_t up); \ + void ss_prepost_power_mode_base(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + void ss_iso_disable_base(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_link_enable_base(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_ssi_power_base(sc_sub_t ss, sc_bool_t enable); \ + void ss_ssi_bhole_mode_base(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_pause_mode_base(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_wait_idle_base(sc_sub_t ss, sc_sub_t remote, uint8_t port); \ + void ss_adb_enable_base(sc_sub_t ss, sc_sub_t remote, sc_bool_t \ + enable); \ + void ss_adb_wait_base(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + void ss_prepost_clock_mode_base(sc_sub_t ss, ss_clock_t clk, \ + ss_prepost_t type, sc_pm_clk_mode_t from_mode, sc_pm_clk_mode_t \ + to_mode); \ + sc_bool_t ss_rdc_is_did_vld_base(sc_sub_t ss, const sc_rm_perm_t \ + *perms); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_BASE \ + { \ + ss_init_base, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + +#endif + +#endif /* SC_SS_BASE_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/base/v1/dsc.h b/platform/ss/base/v1/dsc.h new file mode 100755 index 0000000..ea369fb --- /dev/null +++ b/platform/ss/base/v1/dsc.h @@ -0,0 +1,142 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the generic DSC header info defined by the standards + * doc. + * + * @addtogroup BASE_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_BASE_DSC_H +#define SC_SS_BASE_DSC_H + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_DSCMIX REGBIT(0, 0) +#define RST_SS REGBIT(0, 1) +#define RST_SS_PD2 REGBIT(0, 2) +#define RST_SS_PD3 REGBIT(0, 3) +#define RST_SS_PD4 REGBIT(0, 4) +#define RST_SS_PD5 REGBIT(0, 5) +#define RST_SS_PD6 REGBIT(0, 6) +#define RST_SS_MEM_REPAIR REGBIT(0, 7) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SSI0_PM REGBIT(0, 0) +#define GPR_SSI0_BHM REGBIT(0, 1) +#define GPR_SSI0_ISO_CONTROL REGBIT(0, 2) +#define GPR_SSI0_POWER_CONTROL REGBIT(0, 3) +#define GPR_SSI1_PM REGBIT(0, 4) +#define GPR_SSI1_BHM REGBIT(0, 5) +#define GPR_SSI1_ISO_CONTROL REGBIT(0, 6) +#define GPR_SSI1_POWER_CONTROL REGBIT(0, 7) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_SSI0_SI REGBIT(0, 0) +#define GPS_SSI0_RI REGBIT(0, 1) +#define GPS_SSI1_SI REGBIT(0, 2) +#define GPS_SSI1_RI REGBIT(0, 3) +#define GPS_SSI0_PM_DATA_PEND REGBIT(0, 4) +#define GPS_SSI1_PM_DATA_PEND REGBIT(0, 5) +/** @} */ + +/*! + * @name DSC IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_TEMP_PANIC REGBIT64(0, 0) +#define IRQ_TEMP_LOW REGBIT64(0, 1) +#define IRQ_TEMP_HIGH REGBIT64(0, 2) +#define IRQ_MSI_ERR REGBIT64(0, 3) +#define IRQ_MSI_OVFL REGBIT64(0, 4) +#define IRQ_MSI_AHB_OVFL REGBIT64(0, 5) +#define IRQ_BIST REGBIT64(0, 6) +#define IRQ_PWRCTRL_PFET_LF_ACK REGBIT64(0, 16) +#define IRQ_PWRCTRL_PFET_HF_ACK REGBIT64(0, 24) +/** @} */ + +/*! + * @name AI Toggle Mask Definitions + */ +/** @{ */ +#define AI_ANA_PLL0 REGBIT(0, 0) +#define AI_ANA_PLL1 REGBIT(0, 1) +#define AI_ANA_PLL2 REGBIT(0, 2) +#define AI_ANA_OSC24M REGBIT(0, 3) +#define AI_ANA_RC200OSC REGBIT(0, 4) +#define AI_ANA_VDROP_PROCMON REGBIT(0, 5) +#define AI_ANA_TEMP_SENSE REGBIT(0, 6) +#define AI_ANA_LVDS_TRANSCEIVER REGBIT(0, 7) +#define AI_ANA_NEG_CHARGE_PUMP REGBIT(0, 8) +#define AI_ANA_WELL_LEVEL_SOURCE REGBIT(0, 9) +#define AI_ANA_BANDGAP_REFERENCE REGBIT(0, 10) +#define AI_ANA_VA_REF_GEN REGBIT(0, 11) +#define AI_ANA_DIFF_CLOCK_REPEATER REGBIT(0, 12) +#define AI_ANA_DIFF_ROOT_CLK_BUFFER REGBIT(0, 13) +#define AI_ANA_DIFF_CLOCK_TERM REGBIT(0, 14) +#define AI_PHY_PHY_LDO REGBIT(0, 17) +#define AI_PHY_LVDS_TRANSCEIVER REGBIT(0, 18) +#define AI_PHY_BANDGAP_REFERENCE REGBIT(0, 19) +#define AI_PHY_VA_REF_GEN REGBIT(0, 20) +#define AI_PHY_DIFF_CLOCK_REPEATER REGBIT(0, 21) +#define AI_PHY_DIFF_ROOT_CLK_BUF0 REGBIT(0, 22) +#define AI_PHY_DIFF_ROOT_CLK_BUF1 REGBIT(0, 23) +#define AI_PHY_DIFF_ROOT_CLK_BUF2 REGBIT(0, 24) +#define AI_PHY_DIFF_CLOCK_TERM0 REGBIT(0, 25) +#define AI_PHY_DIFF_CLOCK_TERM1 REGBIT(0, 26) +#define AI_PHY_DIFF_CLOCK_TERM2 REGBIT(0, 27) +#define AI_PHY_DIFF_CLOCK_TERM3 REGBIT(0, 28) +/** @} */ + +#endif /* SC_SS_BASE_DSC_H */ + +/** @} */ + diff --git a/platform/ss/base/v1/ss.h b/platform/ss/base/v1/ss.h new file mode 100755 index 0000000..3881517 --- /dev/null +++ b/platform/ss/base/v1/ss.h @@ -0,0 +1,204 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the base subsystem API. + * + * @addtogroup BASE_SS BASE: Base Subsystem + * + * Module for Base subsystem access. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_BASE_H +#define SC_SS_BASE_H + +/* Includes */ + +#include "main/types.h" +#include "ss/inf/inf.h" +#include "svc/pm/svc.h" +#include "drivers/xrdc2/fsl_xrdc2.h" +#include "main/sched.h" + +/* Defines */ + +#define PD_DSC 0U +#define PD_SS 1U + +#define CLKOFFTRANS() ((from_mode <= SC_PM_PW_MODE_STBY) && (to_mode <= SC_PM_PW_MODE_STBY)) +#define CLK2OFF() ((from_mode > SC_PM_PW_MODE_STBY) && (to_mode <= SC_PM_PW_MODE_STBY)) +#define CLK2ON() ((from_mode <= SC_PM_PW_MODE_STBY) && (to_mode > SC_PM_PW_MODE_STBY)) +#define PWR2OFF() (to_mode == SC_PM_PW_MODE_OFF) +#define HSCLK() ((from_mode <= SC_PM_PW_MODE_LP) && (to_mode > SC_PM_PW_MODE_LP)) +#define LSCLK() ((from_mode > SC_PM_PW_MODE_LP) && (to_mode == SC_PM_PW_MODE_LP)) +#define PWR2ON() (from_mode == SC_PM_PW_MODE_OFF) +#define RUN2CLKOFF() ((from_mode > SC_PM_PW_MODE_STBY) && (to_mode == SC_PM_PW_MODE_STBY)) + +#define SS_RESET_NONE 0x7FFFU +#define SS_RESET_LINK 0x8000U + +/* Types */ + +/*! + * This type is used store static constant info on the signals for + * a P-channel interface. + */ +typedef struct +{ + uint8_t pstate; + uint8_t pstate_width; + uint8_t preq; + uint8_t paccept; + uint8_t pdeny; + uint8_t pactive; + uint8_t pactive_width; +} ss_pchannel_t; + +/*! + * This type is used store static constant info on the signals for + * a Q-channel interface. + */ +typedef struct +{ + uint8_t qreqn; + uint8_t qacceptn; + uint8_t qdeny; + uint8_t qactive; +} ss_qchannel_t; + +typedef uint16_t ss_reset_list_t; + +/* Functions */ + +SS_FUNC_PROTO_BASE + +#if (defined(FSL_FEATURE_DSC_HAS_PER_RESET) && FSL_FEATURE_DSC_HAS_PER_RESET) +void ss_reset_resource(ECSR_Reset_Type *csr_base, sc_sub_t ss, ss_idx_t ss_idx, + const ss_reset_list_t *reset_list, sc_bool_t old_sequence); +void ss_setup_reset_clk(sc_sub_t ss, ss_idx_t ss_idx, sc_pm_clk_t clk, + sc_bool_t enable); +void ss_setup_reset_plls(sc_sub_t ss, sc_bool_t enable); +#endif +void ss_init_boot_base(sc_sub_t ss, ss_idx_t ss_idx, sc_pm_power_mode_t to_mode); +sc_bool_t ss_is_powered(sc_sub_t ss); +void ss_set_rsrc_clks(sc_sub_t ss, ss_idx_t ss_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); +void ss_trans_pd(sc_sub_t ss, dsc_pdom_t pd, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); +uint8_t ss_pchannel_get_activity(sc_dsc_t dsc, const ss_pchannel_t channel); +uint8_t ss_pchannel_set_state(sc_dsc_t dsc, const ss_pchannel_t channel, + uint8_t new_state); +sc_bool_t ss_qchannel_set_state(sc_dsc_t dsc, const ss_qchannel_t channel, + sc_bool_t new_state); +void ss_ssi_link(sc_sub_t local, sc_sub_t remote, uint8_t local_port, + uint8_t remote_port, sc_bool_t enable); +void ss_ssi_po_link(sc_sub_t local, sc_sub_t remote, uint8_t port, + sc_bool_t enable); +void ss_adb_link(sc_sub_t local, sc_sub_t remote, sc_bool_t enable); +void ss_adb_enb(sc_sub_t ss, uint32_t adb, sc_bool_t enable); +void ss_adb_x2_enb(sc_sub_t ss, uint32_t adb1, uint32_t adb2, sc_bool_t enable); +void ss_adb_wt(sc_sub_t ss, uint32_t adb, sc_bool_t enable); +void ss_adb_x2_wt(sc_sub_t ss, uint32_t adb1, uint32_t adb2, sc_bool_t enable); +sc_err_t ss_check_pll_rate(sc_sub_t ss, ss_clock_t clk_index, + const sc_pm_clock_rate_t *rate, sc_bool_t rom_boot); +void ss_config_pll_rate(sc_sub_t ss, ss_clock_t clk_index, + sc_pm_clock_rate_t *rate, sc_bool_t rom_boot); +sc_err_t ss_config_clk_rate(sc_sub_t ss, ss_clock_t clk_index, + sc_pm_clock_rate_t *rate, sc_bool_t rom_boot); +void ss_config_pll_mode(sc_sub_t ss, ss_clock_t clk_index, + sc_pm_clk_mode_t mode, sc_bool_t rom_boot); +sc_err_t ss_config_clk_mode(sc_sub_t ss, ss_clock_t clk_index, + sc_pm_clk_mode_t mode, sc_bool_t rom_boot); +sc_err_t ss_ap_reset_vector(sc_faddr_t addr, uint32_t cpu, sc_bool_t *vector); +void ss_populate_boot_dev_info(ss_idx_t ss_idx, sc_sub_t ss, + sc_bool_t fix_pll_rate); +sc_err_t ss_get_clk_rate_by_index(sc_sub_t ss, ss_clock_t clk_index, + sc_pm_clock_rate_t *rate); +sc_pm_clk_parent_t ss_get_parent_index(sc_sub_t ss, ss_clock_t clk_index); +void ss_set_parent_by_index(sc_sub_t ss, ss_clock_t clk_index, + sc_pm_clk_parent_t new_parent_index); +sc_err_t ss_refactor_clks(sc_sub_t ss, ss_idx_t ss_idx, sc_pm_clk_t clk, + const sc_pm_clock_rate_t *cur_rate, sc_pm_clock_rate_t *rate); +void ss_active_bias_domains(sc_sub_t ss, uint8_t *active_mask, uint8_t *idle_mask); +void ss_config_max_core_freq(sc_sub_t ss, ss_clock_t pll_index, ss_clock_t cpu_clk_index, + dsc_clk_type_t pll_type, sc_pm_clock_rate_t max_rate); +void ss_trans_power_mode_noxrdc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); + +#ifdef XRDC_SUPPORT + void ss_rdc_enable_check(void); + void ss_rdc_power_down(sc_sub_t ss, dsc_pdom_t pd); + void ss_rdc_set_custom_master(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, sc_rm_spa_t pa, + sc_rm_did_t did, sc_rm_sid_t sid, xrdc_match_t match, + xrdc_match_t mask, uint8_t cid); + void ss_rdc_set_custom_mda(sc_sub_t ss, sc_rm_idx_t xrdc_master_idx, + sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, sc_rm_spa_t pa, sc_rm_did_t did, + sc_rm_sid_t sid, xrdc_match_t match, xrdc_match_t mask, uint8_t cid); +#endif /* XRDC_SUPPORT */ +void ss_dsc_irq_handler_base(sc_dsc_t dsc, + const ss_dsc_l2irq_handler *ss_dsc_l2irq_handlers, + const ss_dsc_l2irq_handler *ss_l2irq_handlers); +sc_bool_t ss_dsc_handler_default(sc_dsc_t dsc, uint32_t irqIndex); + +/* Debug Functions */ + +#if defined(DEBUG) || defined(GCOV) + void ss_dump_header_base(sc_sub_t ss); + void ss_dump_master_counts_base(sc_sub_t ss); + void ss_dump_xrdc_base(sc_sub_t ss, sc_dsc_t dsc, + const ss_base_info_t *base); + void ss_dump_clocks(sc_sub_t ss); +#endif + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_dsc_l2irq_handlers_base[]; +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_base[]; +extern sc_bool_t xrdc_enable; +extern sc_bool_t base_noflushl2; +extern sc_bool_t base_nopoweroff; +extern sc_bool_t base_gic_noblock; + +#endif /* SC_SS_BASE_H */ + +/** @} */ + diff --git a/platform/ss/cci/v1/Makefile b/platform/ss/cci/v1/Makefile new file mode 100755 index 0000000..e2cc168 --- /dev/null +++ b/platform/ss/cci/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/cci/v1/ss.o + +CONFIGH += $(SRC)/ss/cci/v1/config.h $(SRC)/ss/cci/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/cci/v1/resource.txt + +CLK_MD += $(SRC)/ss/cci/v1/clock.txt + +CTRL_MD += $(SRC)/ss/cci/v1/control.txt + +DIRS += $(OUT)/ss/cci/v1 + diff --git a/platform/ss/cci/v1/config.h b/platform/ss/cci/v1/config.h new file mode 100644 index 0000000..7128cb2 --- /dev/null +++ b/platform/ss/cci/v1/config.h @@ -0,0 +1,134 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the CCI subsystem. + * + * @addtogroup CCI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_CCI_CONFIG_H +#define SC_SS_CCI_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_CCI 1U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_CCI \ + sc_err_t ss_set_cpu_power_mode_cci(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_power_mode_t mode, sc_pm_wake_src_t \ + wake_src); \ + void ss_prepost_power_mode_cci(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + void ss_link_enable_cci(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_ssi_bhole_mode_cci(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_pause_mode_cci(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_wait_idle_cci(sc_sub_t ss, sc_sub_t remote, uint8_t port); \ + sc_bool_t ss_rdc_is_did_vld_cci(sc_sub_t ss, const sc_rm_perm_t \ + *perms); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_CCI \ + { \ + ss_init_base, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_cci, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_cci, \ + ss_iso_disable_base, \ + ss_link_enable_cci, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_cci, \ + ss_ssi_pause_mode_cci, \ + ss_ssi_wait_idle_cci, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_cci, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_CCI_0 \ + "CCI", \ + +#endif + +#endif /* SC_SS_CCI_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/cci/v1/dsc.h b/platform/ss/cci/v1/dsc.h new file mode 100755 index 0000000..0e30158 --- /dev/null +++ b/platform/ss/cci/v1/dsc.h @@ -0,0 +1,85 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup CCI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CCI_DSC_H +#define SC_SS_CCI_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_ECOREVNUM REGBIT(1, 16) +#define GPR_CCI_CSYSREQ REGBIT(1, 24) +#define GPR_CCI_HYST_CTRL REGBIT(1, 30) +#define GPR_CCI_AUTO_GATE REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_CSYSACK_CCI REGBIT(0, 28) +#define GPS_CACTIVE_CCI REGBIT(0, 29) +#define GPS_CACTIVEM2_CCI REGBIT(0, 30) +#define GPS_CACTIVE_A72_ADB REGBIT(0, 31) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_CACTIVE REGBIT64(1, 0) +#define IRQ_CACTIVEM REGBIT64(1, 1) +/** @} */ + +#endif /* SC_SS_CCI_DSC_H */ + +/** @} */ + diff --git a/platform/ss/cci/v1/rsrc.h b/platform/ss/cci/v1/rsrc.h new file mode 100644 index 0000000..63484a2 --- /dev/null +++ b/platform/ss/cci/v1/rsrc.h @@ -0,0 +1,62 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the CCI subsystem. + * + * @addtogroup CCI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_CCI_RSRC_H +#define SC_SS_CCI_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_CCI 0U +/** @} */ + +#endif /* SC_SS_CCI_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/cci/v1/ss.h b/platform/ss/cci/v1/ss.h new file mode 100755 index 0000000..83f08d9 --- /dev/null +++ b/platform/ss/cci/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the CCI subsystem API. + * + * @addtogroup CCI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CCI_SS_H +#define SC_SS_CCI_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(cci) + +/* Functions */ + +SS_FUNC_PROTO_CCI + +#endif /* SC_SS_CCI_SS_H */ + +/** @} */ + diff --git a/platform/ss/conn/v1/Makefile b/platform/ss/conn/v1/Makefile new file mode 100755 index 0000000..0fec512 --- /dev/null +++ b/platform/ss/conn/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/conn/v1/ss.o + +CONFIGH += $(SRC)/ss/conn/v1/config.h $(SRC)/ss/conn/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/conn/v1/resource.txt + +CLK_MD += $(SRC)/ss/conn/v1/clock.txt + +CTRL_MD += $(SRC)/ss/conn/v1/control.txt + +DIRS += $(OUT)/ss/conn/v1 + diff --git a/platform/ss/conn/v1/config.h b/platform/ss/conn/v1/config.h new file mode 100644 index 0000000..a404c29 --- /dev/null +++ b/platform/ss/conn/v1/config.h @@ -0,0 +1,143 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the CONN subsystem. + * + * @addtogroup CONN_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_CONN_CONFIG_H +#define SC_SS_CONN_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_CONN 16U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_CONN \ + void ss_init_conn(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_set_control_conn(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + void ss_updown_conn(sc_sub_t ss, sc_bool_t up); \ + void ss_prepost_power_mode_conn(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + void ss_iso_disable_conn(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_CONN \ + { \ + ss_init_conn, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_conn, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_conn, \ + ss_prepost_power_mode_conn, \ + ss_iso_disable_conn, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_CONN_0 \ + "SDHC_0", \ + "SDHC_1", \ + "SDHC_2", \ + "ENET_0", \ + "ENET_1", \ + "DMA_4_CH0", \ + "DMA_4_CH1", \ + "DMA_4_CH2", \ + "DMA_4_CH3", \ + "DMA_4_CH4", \ + "USB_0", \ + "USB_1", \ + "USB_0_PHY", \ + "USB_2", \ + "USB_2_PHY", \ + "NAND", \ + +#endif + +#endif /* SC_SS_CONN_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/conn/v1/dsc.h b/platform/ss/conn/v1/dsc.h new file mode 100755 index 0000000..54cbba6 --- /dev/null +++ b/platform/ss/conn/v1/dsc.h @@ -0,0 +1,142 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup CONN_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CONN_DSC_H +#define SC_SS_CONN_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_USB2 REGBIT(0, 2) +#define RST_USB3_AON REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_OBS_SEL0 REGBIT(0, 8) +#define GPR_OBS_SEL1 REGBIT(0, 9) +#define GPR_ENET_CTRL0 REGBIT(0, 16) +#define GPR_ENET_CTRL1 REGBIT(0, 17) +#define GPR_ISO_USB3_NONSS REGBIT(0, 18) +#define GPR_ISO_USB3_SS REGBIT(0, 19) +#define GPR_ISO_USB2 REGBIT(0, 20) +#define GPR_PL301_CACHE_DIS REGBIT(0, 21) +#define GPR_PL301_M12_ID_FILTER REGBIT(0, 22) +#define GPR_PL301_FORCE_CACHEABLE REGBIT(0, 23) +#define GPR_ENET1_MUX REGBIT(0, 24) +#define GPR_ENET2_MUX REGBIT(0, 25) +#define GPR_ENET1_IPG_STOP REGBIT(0, 26) +#define GPR_ENET2_IPG_STOP REGBIT(0, 27) +#define GPR_ENET1_TX_CLK_SEL REGBIT(0, 28) +#define GPR_ENET2_TX_CLK_SEL REGBIT(0, 29) +#define GPR_USB2PHY_IPG_CLK_ACTIVE REGBIT(0, 30) +#define GPR_USB2PHY_XTAL_VLD REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_ENET1_CLKDIV_SEL REGBIT(1, 33) +#define GPR_ENET2_CLKDIV_SEL REGBIT(1, 34) +#define GPR_USB_PHY_TRIM REGBIT(1, 35) +#define GPR_DIS REGBIT(1, 57) +#define GPR_ENET1_50_DISABLE REGBIT(1, 58) +#define GPR_ENET1_125_DISABLE REGBIT(1, 59) +#define GPR_ENET2_50_DISABLE REGBIT(1, 60) +#define GPR_ENET2_125_DISABLE REGBIT(1, 61) +#define GPR_ENET1_125_SEL REGBIT(1, 62) +#define GPR_ENET2_125_SEL REGBIT(1, 63) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_ENET1_IPG_STOP_ACK REGBIT(0, 6) +#define GPS_ENET2_IPG_STOP_ACK REGBIT(0, 7) +/** @} */ + +/*! + * @name IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_ENET1_BUF1 REGBIT(1, 3) +#define IRQ_ENET1_BUF2 REGBIT(1, 4) +#define IRQ_ENET1 REGBIT(1, 5) +#define IRQ_ENET1_TIME REGBIT(1, 6) +#define IRQ_ENET2_BUF1 REGBIT(1, 7) +#define IRQ_ENET2_BUF2 REGBIT(1, 8) +#define IRQ_ENET2 REGBIT(1, 9) +#define IRQ_ENET2_TIME REGBIT(1, 10) +#define IRQ_DTCP REGBIT(1, 11) +#define IRQ_USBOH_OTG REGBIT(1, 14) +#define IRQ_USBOH_HSIC REGBIT(1, 15) +#define IRQ_USBOH_PHY REGBIT(1, 16) +#define IRQ_USBOH_WAKE REGBIT(1, 17) +#define IRQ_NAND_BCH REGBIT(1, 18) +#define IRQ_NAND_GPMI REGBIT(1, 19) +#define IRQ_DMA_CH0 REGBIT(1, 20) +#define IRQ_DMA_CH1 REGBIT(1, 21) +#define IRQ_DMA_CH2 REGBIT(1, 22) +#define IRQ_DMA_CH3 REGBIT(1, 23) +#define IRQ_DMA_CH4 REGBIT(1, 24) +#define IRQ_DMA_ERR REGBIT(1, 25) +#define IRQ_USB3 REGBIT(1, 26) +#define IRQ_NAND_DMA REGBIT(1, 27) +/** @} */ + +#endif /* SC_SS_CONN_DSC_H */ + +/** @} */ + diff --git a/platform/ss/conn/v1/rsrc.h b/platform/ss/conn/v1/rsrc.h new file mode 100644 index 0000000..5905d82 --- /dev/null +++ b/platform/ss/conn/v1/rsrc.h @@ -0,0 +1,77 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the CONN subsystem. + * + * @addtogroup CONN_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_CONN_RSRC_H +#define SC_SS_CONN_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_SDHC_0 0U +#define SS_R_SDHC_1 1U +#define SS_R_SDHC_2 2U +#define SS_R_ENET_0 3U +#define SS_R_ENET_1 4U +#define SS_R_DMA_4_CH0 5U +#define SS_R_DMA_4_CH1 6U +#define SS_R_DMA_4_CH2 7U +#define SS_R_DMA_4_CH3 8U +#define SS_R_DMA_4_CH4 9U +#define SS_R_USB_0 10U +#define SS_R_USB_1 11U +#define SS_R_USB_0_PHY 12U +#define SS_R_USB_2 13U +#define SS_R_USB_2_PHY 14U +#define SS_R_NAND 15U +/** @} */ + +#endif /* SC_SS_CONN_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/conn/v1/ss.h b/platform/ss/conn/v1/ss.h new file mode 100755 index 0000000..7ed2685 --- /dev/null +++ b/platform/ss/conn/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the CONN subsystem API. + * + * @addtogroup CONN_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CONN_SS_H +#define SC_SS_CONN_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(conn) + +/* Functions */ + +SS_FUNC_PROTO_CONN + +#endif /* SC_SS_CONN_SS_H */ + +/** @} */ + diff --git a/platform/ss/conn/v2/Makefile b/platform/ss/conn/v2/Makefile new file mode 100755 index 0000000..2cc2d49 --- /dev/null +++ b/platform/ss/conn/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/conn/v2/ss.o + +CONFIGH += $(SRC)/ss/conn/v2/config.h $(SRC)/ss/conn/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/conn/v2/resource.txt + +CLK_MD += $(SRC)/ss/conn/v2/clock.txt + +CTRL_MD += $(SRC)/ss/conn/v2/control.txt + +DIRS += $(OUT)/ss/conn/v2 + diff --git a/platform/ss/conn/v2/dsc.h b/platform/ss/conn/v2/dsc.h new file mode 100755 index 0000000..185bb27 --- /dev/null +++ b/platform/ss/conn/v2/dsc.h @@ -0,0 +1,145 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup CONN_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CONN_DSC_H +#define SC_SS_CONN_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_USB2 REGBIT(0, 2) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_OBS_SEL0 REGBIT(0, 8) +#define GPR_OBS_SEL1 REGBIT(0, 9) +#define GPR_ENET_QOS_DIS_CRC_CHK REGBIT(0, 10) +#define GPR_ENET_QOS_CLK_GEN_EN REGBIT(0, 11) +#define GPR_ENET_QOS_INTF_SEL REGBIT(0, 12) +#define GPR_ENET_RXC_DELAY REGBIT(0, 16) +#define GPR_ENET_EC0_DIS REGBIT(0, 18) +#define GPR_ISO_USB_OTG1 REGBIT(0, 19) +#define GPR_ISO_USB_OTG2 REGBIT(0, 20) +#define GPR_PL301_CACHE_DIS REGBIT(0, 21) +#define GPR_PL301_M12_ID_FILTER REGBIT(0, 22) +#define GPR_PL301_FORCE_CACHEABLE REGBIT(0, 23) +#define GPR_ENET1_MUX REGBIT(0, 24) +#define GPR_ENET2_MUX REGBIT(0, 25) +#define GPR_ENET1_IPG_STOP REGBIT(0, 26) +#define GPR_ENET1_TX_CLK_SEL REGBIT(0, 28) +#define GPR_USB2PHY_IPG_CLK_ACTIVE REGBIT(0, 30) +#define GPR_USB2PHY_XTAL_VLD REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_ENET1_CLKDIV_SEL REGBIT(1, 33) +#define GPR_USB_PHY_TRIM REGBIT(1, 35) +#define GPR_DIS REGBIT(1, 57) +#define GPR_ENET1_50_DISABLE REGBIT(1, 58) +#define GPR_ENET1_125_DISABLE REGBIT(1, 59) +#define GPR_ENET2_50_DISABLE REGBIT(1, 60) +#define GPR_ENET2_125_DISABLE REGBIT(1, 61) +#define GPR_ENET1_125_SEL REGBIT(1, 62) +#define GPR_ENET2_125_SEL REGBIT(1, 63) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_ENET1_IPG_STOP_ACK REGBIT(0, 6) +/** @} */ + +/*! + * @name IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_ENET1_BUF1 REGBIT(1, 3) +#define IRQ_ENET1_BUF2 REGBIT(1, 4) +#define IRQ_ENET1 REGBIT(1, 5) +#define IRQ_ENET1_TIME REGBIT(1, 6) +#define IRQ_ENET2_PMT REGBIT(1, 7) +#define IRQ_ENET2 REGBIT(1, 8) +#define IRQ_USBOH_OTG REGBIT(1, 14) +#define IRQ_USBOH_OTG2 REGBIT(1, 15) +#define IRQ_USBOH_PHY REGBIT(1, 16) +#define IRQ_USBOH_WAKE REGBIT(1, 17) +#define IRQ_NAND_BCH REGBIT(1, 18) +#define IRQ_NAND_GPMI REGBIT(1, 19) +#define IRQ_NAND_DMA REGBIT(1, 27) +/** @} */ + +#if (defined(FSL_FEATURE_DSC_HAS_PER_RESET) && FSL_FEATURE_DSC_HAS_PER_RESET) +/*! + * @name ECSR 0x00 Reset Bit Definitions + */ +/** @{ */ +#define CSR_SDHC1_RESET REGBIT8(0x0, 0) +#define CSR_SDHC2_RESET REGBIT8(0x0, 1) +#define CSR_SDHC3_RESET REGBIT8(0x0, 2) +#define CSR_ENET1_RESET REGBIT8(0x0, 3) +#define CSR_ENET2_RESET REGBIT8(0x0, 4) +#define CSR_USB_RESET REGBIT8(0x0, 5) +#define CSR_USB_PHY1_RESET REGBIT8(0x0, 6) +#define CSR_USB_PHY2_RESET REGBIT8(0x0, 7) +#define CSR_NAND_RESET REGBIT8(0x0, 8) +/** @} */ +#endif + +#endif /* SC_SS_CONN_DSC_H */ + +/** @} */ + diff --git a/platform/ss/conn/v2/ss.h b/platform/ss/conn/v2/ss.h new file mode 100755 index 0000000..8bdbc6d --- /dev/null +++ b/platform/ss/conn/v2/ss.h @@ -0,0 +1,62 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the CONN subsystem API. + * + * @addtogroup CONN_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CONN_SS_H +#define SC_SS_CONN_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(conn) + +/* Functions */ + +SS_FUNC_PROTO_CONN + +#endif /* SC_SS_CONN_SS_H */ + +/** @} */ + diff --git a/platform/ss/csi/v1/Makefile b/platform/ss/csi/v1/Makefile new file mode 100755 index 0000000..f8c2750 --- /dev/null +++ b/platform/ss/csi/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/csi/v1/ss.o + +CONFIGH += $(SRC)/ss/csi/v1/config.h $(SRC)/ss/csi/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/csi/v1/resource.txt + +CLK_MD += $(SRC)/ss/csi/v1/clock.txt + +CTRL_MD += $(SRC)/ss/csi/v1/control.txt + +DIRS += $(OUT)/ss/csi/v1 + diff --git a/platform/ss/csi/v1/config.h b/platform/ss/csi/v1/config.h new file mode 100644 index 0000000..cb23634 --- /dev/null +++ b/platform/ss/csi/v1/config.h @@ -0,0 +1,134 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the CSI subsystem. + * + * @addtogroup CSI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_CSI_CONFIG_H +#define SC_SS_CSI_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_CSI 3U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_CSI \ + void ss_init_csi(sc_sub_t ss, sc_bool_t api_phase); \ + void ss_trans_power_mode_csi(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_CSI \ + { \ + ss_init_csi, \ + ss_trans_power_mode_csi, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_CSI_0 \ + "CSI_0", \ + "CSI_0_PWM_0", \ + "CSI_0_I2C_0", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_CSI_1 \ + "CSI_1", \ + "CSI_1_PWM_0", \ + "CSI_1_I2C_0", \ + +#endif + +#endif /* SC_SS_CSI_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/csi/v1/dsc.h b/platform/ss/csi/v1/dsc.h new file mode 100755 index 0000000..9137f06 --- /dev/null +++ b/platform/ss/csi/v1/dsc.h @@ -0,0 +1,102 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup CSI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CSI_DSC_H +#define SC_SS_CSI_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_MIPI REGBIT(0, 2) +#define RST_BUS REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 0) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 1) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 2) +#define GPR_PWM0_IPG_STOP REGBIT(0, 3) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 4) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 5) +#define GPR_I2C0_IPG_STOP REGBIT(0, 6) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 7) +#define GPR_PHY_ISO REGBIT(0, 16) +#define GPR_DISPLAY_CTRL_LINK_SLV REGBIT(0, 25) +#define GPR_RX_RCAL REGBIT(0, 26) +#define GPR_RXLPRP0 REGBIT(0, 28) +#define GPR_RXLPRP1 REGBIT(0, 29) +#define GPR_RXCDRP0 REGBIT(0, 30) +#define GPR_RXCDRP1 REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 0) +#define GPS_LANES_STOPPED REGBIT(0, 1) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO REGBIT64(1, 0) +#define IRQ_LPI2C0 REGBIT64(1, 1) +/** @} */ + +#endif /* SC_SS_CSI_DSC_H */ + +/** @} */ + diff --git a/platform/ss/csi/v1/rsrc.h b/platform/ss/csi/v1/rsrc.h new file mode 100644 index 0000000..1bbc5a6 --- /dev/null +++ b/platform/ss/csi/v1/rsrc.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the CSI subsystem. + * + * @addtogroup CSI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_CSI_RSRC_H +#define SC_SS_CSI_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_CSI_0 0U +#define SS_R_CSI_0_PWM_0 1U +#define SS_R_CSI_0_I2C_0 2U +#define SS_R_CSI_1 0U +#define SS_R_CSI_1_PWM_0 1U +#define SS_R_CSI_1_I2C_0 2U +/** @} */ + +#endif /* SC_SS_CSI_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/csi/v1/ss.h b/platform/ss/csi/v1/ss.h new file mode 100755 index 0000000..b13c092 --- /dev/null +++ b/platform/ss/csi/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the CSI subsystem API. + * + * @addtogroup CSI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_CSI_SS_H +#define SC_SS_CSI_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(csi) + +/* Functions */ + +SS_FUNC_PROTO_CSI + +#endif /* SC_SS_CSI_SS_H */ + +/** @} */ + diff --git a/platform/ss/db/v1/Makefile b/platform/ss/db/v1/Makefile new file mode 100755 index 0000000..1482515 --- /dev/null +++ b/platform/ss/db/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/db/v1/ss.o + +CONFIGH += $(SRC)/ss/db/v1/config.h $(SRC)/ss/db/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/db/v1/resource.txt + +CLK_MD += $(SRC)/ss/db/v1/clock.txt + +CTRL_MD += $(SRC)/ss/db/v1/control.txt + +DIRS += $(OUT)/ss/db/v1 + diff --git a/platform/ss/db/v1/config.h b/platform/ss/db/v1/config.h new file mode 100644 index 0000000..e7e56bc --- /dev/null +++ b/platform/ss/db/v1/config.h @@ -0,0 +1,136 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the DB subsystem. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_DB_CONFIG_H +#define SC_SS_DB_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_DB 1U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_DB \ + void ss_rdc_enable_db(sc_sub_t ss, sc_bool_t master); \ + sc_err_t ss_rdc_set_memory_db(sc_sub_t ss, sc_faddr_t start, sc_faddr_t \ + end, sc_bool_t valid, const sc_rm_perm_t *perms, sc_rm_det_t det, \ + sc_rm_rmsg_t rmsg, sc_faddr_t new_start, sc_faddr_t new_end); \ + void ss_updown_db(sc_sub_t ss, sc_bool_t up); \ + void ss_prepost_power_mode_db(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + void ss_link_enable_db(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_ssi_bhole_mode_db(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_pause_mode_db(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_wait_idle_db(sc_sub_t ss, sc_sub_t remote, uint8_t port); \ + void ss_adb_enable_db(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + void ss_adb_wait_db(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_DB \ + { \ + ss_init_base, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_db, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_db, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_db, \ + ss_prepost_power_mode_db, \ + ss_iso_disable_base, \ + ss_link_enable_db, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_db, \ + ss_ssi_pause_mode_db, \ + ss_ssi_wait_idle_db, \ + ss_adb_enable_db, \ + ss_adb_wait_db, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DB_0 \ + "DB", \ + +#endif + +#endif /* SC_SS_DB_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/db/v1/dsc.h b/platform/ss/db/v1/dsc.h new file mode 100755 index 0000000..7155f24 --- /dev/null +++ b/platform/ss/db/v1/dsc.h @@ -0,0 +1,198 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DB_DSC_H +#define SC_SS_DB_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SSI2_PM REGBIT(0, 8) +#define GPR_SSI2_BHM REGBIT(0, 9) +#define GPR_SSI3_PM REGBIT(0, 10) +#define GPR_SSI3_BHM REGBIT(0, 11) +#define GPR_SSI4_PM REGBIT(0, 12) +#define GPR_SSI4_BHM REGBIT(0, 13) +#define GPR_SSI5_PM REGBIT(0, 14) +#define GPR_SSI5_BHM REGBIT(0, 15) +#define GPR_SSI6_PM REGBIT(0, 16) +#define GPR_SSI6_BHM REGBIT(0, 17) +#define GPR_SSI7_PM REGBIT(0, 18) +#define GPR_SSI7_BHM REGBIT(0, 19) +#define GPR_SSI8_PM REGBIT(0, 20) +#define GPR_SSI8_BHM REGBIT(0, 21) +#define GPR_SSI9_PM REGBIT(0, 22) +#define GPR_SSI9_BHM REGBIT(0, 23) +#define GPR_SSI10_PM REGBIT(0, 24) +#define GPR_SSI10_BHM REGBIT(0, 25) +#define GPR_SSI11_PM REGBIT(0, 26) +#define GPR_SSI11_BHM REGBIT(0, 27) +#define GPR_SSI12_PM REGBIT(0, 28) +#define GPR_SSI12_BHM REGBIT(0, 29) +#define GPR_SSI13_PM REGBIT(0, 30) +#define GPR_SSI13_BHM REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_SSI14_PM REGBIT(1, 0) +#define GPR_SSI14_BHM REGBIT(1, 1) +#define GPR_SSI15_PM REGBIT(1, 2) +#define GPR_SSI15_BHM REGBIT(1, 3) +#define GPR_SSI_DRC0_PM0 REGBIT(1, 4) +#define GPR_SSI_DRC0_PM1 REGBIT(1, 5) +#define GPR_SSI_DRC0_BHM0 REGBIT(1, 6) +#define GPR_SSI_DRC0_BHM1 REGBIT(1, 7) +#define GPR_SSI_DRC1_PM0 REGBIT(1, 8) +#define GPR_SSI_DRC1_PM1 REGBIT(1, 9) +#define GPR_SSI_DRC1_BHM0 REGBIT(1, 10) +#define GPR_SSI_DRC1_BHM1 REGBIT(1, 11) +#define GPR_SSI0_TCU_PM0 REGBIT(1, 12) +#define GPR_SSI0_TCU_PM1 REGBIT(1, 13) +#define GPR_SSI0_TCU_PM2 REGBIT(1, 14) +#define GPR_SSI0_TCU_PM3 REGBIT(1, 15) +#define GPR_SSI1_TCU_PM0 REGBIT(1, 16) +#define GPR_SSI1_TCU_PM1 REGBIT(1, 17) +#define GPR_SSI1_TCU_PM2 REGBIT(1, 18) +#define GPR_SSI1_TCU_PM3 REGBIT(1, 19) +#define GPR_SSI2_TCU_PM0 REGBIT(1, 20) +#define GPR_SSI2_TCU_PM1 REGBIT(1, 21) +#define GPR_SSI2_TCU_PM2 REGBIT(1, 22) +#define GPR_SSI2_TCU_PM3 REGBIT(1, 23) +#define GPR_SSI3_TCU_PM0 REGBIT(1, 24) +#define GPR_SSI3_TCU_PM1 REGBIT(1, 25) +#define GPR_SSI3_TCU_PM2 REGBIT(1, 26) +#define GPR_SSI3_TCU_PM3 REGBIT(1, 27) +#define GPR_ADB_PWRDNREQN REGBIT(1, 28) +#define GPR_TBU_PD_QREQN REGBIT(1, 29) +#define GPR_QEN REGBIT(1, 30) +#define GPR_SSI_IDLE_STRAP REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_SSI2_SI REGBIT(0, 4) +#define GPS_SSI2_RI REGBIT(0, 5) +#define GPS_SSI3_SI REGBIT(0, 6) +#define GPS_SSI3_RI REGBIT(0, 7) +#define GPS_SSI4_SI REGBIT(0, 8) +#define GPS_SSI4_RI REGBIT(0, 9) +#define GPS_SSI5_SI REGBIT(0, 10) +#define GPS_SSI5_RI REGBIT(0, 11) +#define GPS_SSI6_SI REGBIT(0, 12) +#define GPS_SSI6_RI REGBIT(0, 13) +#define GPS_SSI7_SI REGBIT(0, 14) +#define GPS_SSI7_RI REGBIT(0, 15) +#define GPS_SSI8_SI REGBIT(0, 16) +#define GPS_SSI8_RI REGBIT(0, 17) +#define GPS_SSI9_SI REGBIT(0, 18) +#define GPS_SSI9_RI REGBIT(0, 19) +#define GPS_SSI10_SI REGBIT(0, 20) +#define GPS_SSI10_RI REGBIT(0, 21) +#define GPS_SSI11_SI REGBIT(0, 22) +#define GPS_SSI11_RI REGBIT(0, 23) +#define GPS_SSI12_SI REGBIT(0, 24) +#define GPS_SSI12_RI REGBIT(0, 25) +#define GPS_SSI13_SI REGBIT(0, 26) +#define GPS_SSI13_RI REGBIT(0, 27) +#define GPS_SSI14_SI REGBIT(0, 28) +#define GPS_SSI14_RI REGBIT(0, 29) +#define GPS_SSI15_SI REGBIT(0, 30) +#define GPS_SSI15_RI REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_SSI_DRC0_SI REGBIT(1, 0) +#define GPS_SSI_DRC0_RI REGBIT(1, 1) +#define GPS_SSI_DRC1_SI REGBIT(1, 2) +#define GPS_SSI_DRC1_RI REGBIT(1, 3) +#define GPS_ADB_PWRDNACKN REGBIT(1, 4) +#define GPS_TBU_PD_QACCEPTN REGBIT(1, 5) +#define GPS_CACTIVE_PG0 REGBIT(1, 6) +#define GPS_CACTIVE_PG1 REGBIT(1, 7) +#define GPS_CACTIVE_PG2 REGBIT(1, 8) +#define GPS_CACTIVE_PG3 REGBIT(1, 9) +#define GPS_CACTIVE_BN REGBIT(1, 10) +#undef GPS_SSI0_PM_DATA_PEND +#define GPS_SSI0_PM_DATA_PEND REGBIT(1, 11) +#undef GPS_SSI1_PM_DATA_PEND +#define GPS_SSI1_PM_DATA_PEND REGBIT(1, 12) +#define GPS_SSI2_PM_DATA_PEND REGBIT(1, 13) +#define GPS_SSI3_PM_DATA_PEND REGBIT(1, 14) +#define GPS_SSI4_PM_DATA_PEND REGBIT(1, 15) +#define GPS_SSI5_PM_DATA_PEND REGBIT(1, 16) +#define GPS_SSI6_PM_DATA_PEND REGBIT(1, 17) +#define GPS_SSI7_PM_DATA_PEND REGBIT(1, 18) +#define GPS_SSI8_PM_DATA_PEND REGBIT(1, 19) +#define GPS_SSI9_PM_DATA_PEND REGBIT(1, 20) +#define GPS_SSI10_PM_DATA_PEND REGBIT(1, 21) +#define GPS_SSI11_PM_DATA_PEND REGBIT(1, 22) +#define GPS_SSI12_PM_DATA_PEND REGBIT(1, 23) +#define GPS_SSI13_PM_DATA_PEND REGBIT(1, 24) +#define GPS_SSI14_PM_DATA_PEND REGBIT(1, 25) +#define GPS_SSI15_PM_DATA_PEND REGBIT(1, 26) +#define GPS_SSI_DRC0_PM_DATA_PEND0 REGBIT(1, 27) +#define GPS_SSI_DRC0_PM_DATA_PEND1 REGBIT(1, 28) +#define GPS_SSI_DRC1_PM_DATA_PEND0 REGBIT(1, 29) +#define GPS_SSI_DRC1_PM_DATA_PEND1 REGBIT(1, 30) +/** @} */ + +#endif /* SC_SS_DB_DSC_H */ + +/** @} */ + diff --git a/platform/ss/db/v1/rsrc.h b/platform/ss/db/v1/rsrc.h new file mode 100644 index 0000000..4c1036c --- /dev/null +++ b/platform/ss/db/v1/rsrc.h @@ -0,0 +1,62 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the DB subsystem. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_DB_RSRC_H +#define SC_SS_DB_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_DB 0U +/** @} */ + +#endif /* SC_SS_DB_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/db/v1/ss.h b/platform/ss/db/v1/ss.h new file mode 100755 index 0000000..a370fa8 --- /dev/null +++ b/platform/ss/db/v1/ss.h @@ -0,0 +1,65 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DB subsystem API. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DB_SS_H +#define SC_SS_DB_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(db) + +/* Functions */ + +SS_FUNC_PROTO_DB + +void ss_auto_clock_gate_db(sc_bool_t enable); + +#endif /* SC_SS_DB_SS_H */ + +/** @} */ + diff --git a/platform/ss/db/v2/Makefile b/platform/ss/db/v2/Makefile new file mode 100755 index 0000000..91c09fc --- /dev/null +++ b/platform/ss/db/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/db/v2/ss.o + +CONFIGH += $(SRC)/ss/db/v2/config.h $(SRC)/ss/db/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/db/v2/resource.txt + +CLK_MD += $(SRC)/ss/db/v2/clock.txt + +CTRL_MD += $(SRC)/ss/db/v2/control.txt + +DIRS += $(OUT)/ss/db/v2 + diff --git a/platform/ss/db/v2/dsc.h b/platform/ss/db/v2/dsc.h new file mode 100755 index 0000000..aff36b3 --- /dev/null +++ b/platform/ss/db/v2/dsc.h @@ -0,0 +1,150 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DB_DSC_H +#define SC_SS_DB_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SSI2_PM REGBIT(0, 8) +#define GPR_SSI2_BHM REGBIT(0, 9) +#define GPR_SSI3_PM REGBIT(0, 10) +#define GPR_SSI3_BHM REGBIT(0, 11) +#define GPR_SSI4_PM REGBIT(0, 12) +#define GPR_SSI4_BHM REGBIT(0, 13) +#define GPR_SSI5_PM REGBIT(0, 14) +#define GPR_SSI5_BHM REGBIT(0, 15) +#define GPR_SSI6_PM REGBIT(0, 16) +#define GPR_SSI6_BHM REGBIT(0, 17) +#define GPR_SSI7_PM REGBIT(0, 18) +#define GPR_SSI7_BHM REGBIT(0, 19) +#define GPR_SSI8_PM REGBIT(0, 20) +#define GPR_SSI8_BHM REGBIT(0, 21) +#define GPR_SSI9_PM REGBIT(0, 22) +#define GPR_SSI9_BHM REGBIT(0, 23) +#define GPR_SSI10_PM REGBIT(0, 24) +#define GPR_SSI10_BHM REGBIT(0, 25) +#define GPR_SSI11_PM REGBIT(0, 26) +#define GPR_SSI11_BHM REGBIT(0, 27) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_SSI_DRC0_PM0 REGBIT(1, 4) +#define GPR_SSI_DRC0_PM1 REGBIT(1, 5) +#define GPR_SSI_DRC0_BHM0 REGBIT(1, 6) +#define GPR_SSI_DRC0_BHM1 REGBIT(1, 7) +#define GPR_ADB_PWRDNREQN REGBIT(1, 28) +#define GPR_SSI_IDLE_STRAP REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_SSI2_SI REGBIT(0, 4) +#define GPS_SSI2_RI REGBIT(0, 5) +#define GPS_SSI3_SI REGBIT(0, 6) +#define GPS_SSI3_RI REGBIT(0, 7) +#define GPS_SSI4_SI REGBIT(0, 8) +#define GPS_SSI4_RI REGBIT(0, 9) +#define GPS_SSI5_SI REGBIT(0, 10) +#define GPS_SSI5_RI REGBIT(0, 11) +#define GPS_SSI6_SI REGBIT(0, 12) +#define GPS_SSI6_RI REGBIT(0, 13) +#define GPS_SSI7_SI REGBIT(0, 14) +#define GPS_SSI7_RI REGBIT(0, 15) +#define GPS_SSI8_SI REGBIT(0, 16) +#define GPS_SSI8_RI REGBIT(0, 17) +#define GPS_SSI9_SI REGBIT(0, 18) +#define GPS_SSI9_RI REGBIT(0, 19) +#define GPS_SSI10_SI REGBIT(0, 20) +#define GPS_SSI10_RI REGBIT(0, 21) +#define GPS_SSI11_SI REGBIT(0, 22) +#define GPS_SSI11_RI REGBIT(0, 23) +/** @} */ + +/*! + * @name GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_SSI_DRC0_SI REGBIT(1, 0) +#define GPS_SSI_DRC0_RI REGBIT(1, 1) +#define GPS_ADB_PWRDNACKN REGBIT(1, 4) +#define GPS_CACTIVE_PG0 REGBIT(1, 6) +#define GPS_CACTIVE_PG1 REGBIT(1, 7) +#define GPS_CACTIVE_PG2 REGBIT(1, 8) +#define GPS_CACTIVE_BN REGBIT(1, 10) +#undef GPS_SSI0_PM_DATA_PEND +#define GPS_SSI0_PM_DATA_PEND REGBIT(1, 11) +#undef GPS_SSI1_PM_DATA_PEND +#define GPS_SSI1_PM_DATA_PEND REGBIT(1, 12) +#define GPS_SSI2_PM_DATA_PEND REGBIT(1, 13) +#define GPS_SSI3_PM_DATA_PEND REGBIT(1, 14) +#define GPS_SSI4_PM_DATA_PEND REGBIT(1, 15) +#define GPS_SSI5_PM_DATA_PEND REGBIT(1, 16) +#define GPS_SSI6_PM_DATA_PEND REGBIT(1, 17) +#define GPS_SSI7_PM_DATA_PEND REGBIT(1, 18) +#define GPS_SSI8_PM_DATA_PEND REGBIT(1, 19) +#define GPS_SSI9_PM_DATA_PEND REGBIT(1, 20) +#define GPS_SSI10_PM_DATA_PEND REGBIT(1, 21) +#define GPS_SSI11_PM_DATA_PEND REGBIT(1, 22) +#define GPS_SSI_DRC0_PM_DATA_PEND0 REGBIT(1, 27) +#define GPS_SSI_DRC0_PM_DATA_PEND1 REGBIT(1, 28) +/** @} */ + +#endif /* SC_SS_DB_DSC_H */ + +/** @} */ + diff --git a/platform/ss/db/v2/ss.h b/platform/ss/db/v2/ss.h new file mode 100755 index 0000000..a370fa8 --- /dev/null +++ b/platform/ss/db/v2/ss.h @@ -0,0 +1,65 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DB subsystem API. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DB_SS_H +#define SC_SS_DB_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(db) + +/* Functions */ + +SS_FUNC_PROTO_DB + +void ss_auto_clock_gate_db(sc_bool_t enable); + +#endif /* SC_SS_DB_SS_H */ + +/** @} */ + diff --git a/platform/ss/db/v4/Makefile b/platform/ss/db/v4/Makefile new file mode 100755 index 0000000..5b71f82 --- /dev/null +++ b/platform/ss/db/v4/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/db/v4/ss.o + +CONFIGH += $(SRC)/ss/db/v4/config.h $(SRC)/ss/db/v4/rsrc.h + +RSRC_MD += $(SRC)/ss/db/v4/resource.txt + +CLK_MD += $(SRC)/ss/db/v4/clock.txt + +CTRL_MD += $(SRC)/ss/db/v4/control.txt + +DIRS += $(OUT)/ss/db/v4 + diff --git a/platform/ss/db/v4/dsc.h b/platform/ss/db/v4/dsc.h new file mode 100755 index 0000000..75b7be8 --- /dev/null +++ b/platform/ss/db/v4/dsc.h @@ -0,0 +1,127 @@ +/* +** ################################################################### +** +** Copyright (c) 2019-2020 Freescale Semiconductor, Inc. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DB_DSC_H +#define SC_SS_DB_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_V2X REGBIT(0, 2) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SSI2_PM REGBIT(0, 8) +#define GPR_SSI2_BHM REGBIT(0, 9) +#define GPR_SSI3_PM REGBIT(0, 10) +#define GPR_SSI3_BHM REGBIT(0, 11) +#define GPR_SSI4_PM REGBIT(0, 12) +#define GPR_SSI4_BHM REGBIT(0, 13) +#define GPR_SSI5_PM REGBIT(0, 14) +#define GPR_SSI5_BHM REGBIT(0, 15) +#define GPR_SSI6_PM REGBIT(0, 16) +#define GPR_SSI6_BHM REGBIT(0, 17) +#define GPR_V2XDB_ADB_PWRDNREQN REGBIT(0, 18) +#define GPR_DBV2X_ADB_PWRDNREQN REGBIT(0, 19) +#define GPR_SSI_DRC0_PM0 REGBIT(0, 20) +#define GPR_SSI_DRC0_PM1 REGBIT(0, 21) +#define GPR_SSI_DRC0_BHM0 REGBIT(0, 22) +#define GPR_SSI_DRC0_BHM1 REGBIT(0, 23) +#define GPR_V2X_CLOCK_RUN REGBIT(0, 30) +#define GPR_SSI_IDLE_STRAP REGBIT(0, 31) + +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_SSI2_SI REGBIT(0, 4) +#define GPS_SSI2_RI REGBIT(0, 5) +#define GPS_SSI3_SI REGBIT(0, 6) +#define GPS_SSI3_RI REGBIT(0, 7) +#define GPS_SSI4_SI REGBIT(0, 8) +#define GPS_SSI4_RI REGBIT(0, 9) +#define GPS_SSI5_SI REGBIT(0, 10) +#define GPS_SSI5_RI REGBIT(0, 11) +#define GPS_SSI6_SI REGBIT(0, 12) +#define GPS_SSI6_RI REGBIT(0, 13) +#define GPR_V2XDB_ADB_PWRDNACKN REGBIT(0, 14) +#define GPR_DBV2X_ADB_PWRDNACKN REGBIT(0, 15) +#define GPS_SSI_DRC0_SI REGBIT(0, 16) +#define GPS_SSI_DRC0_RI REGBIT(0, 17) +#undef GPS_SSI0_PM_DATA_PEND +#define GPS_SSI0_PM_DATA_PEND REGBIT(0, 20) +#undef GPS_SSI1_PM_DATA_PEND +#define GPS_SSI1_PM_DATA_PEND REGBIT(0, 21) +#define GPS_SSI2_PM_DATA_PEND REGBIT(0, 22) +#define GPS_SSI3_PM_DATA_PEND REGBIT(0, 23) +#define GPS_SSI4_PM_DATA_PEND REGBIT(0, 24) +#define GPS_SSI5_PM_DATA_PEND REGBIT(0, 25) +#define GPS_SSI6_PM_DATA_PEND REGBIT(0, 26) +#define GPS_SSI_DRC0_PM_DATA_PEND0 REGBIT(0, 28) +#define GPS_SSI_DRC0_PM_DATA_PEND1 REGBIT(0, 29) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_SERIOUS_ERR REGBIT64(1, 0) +#define IRQ_V2X_MU REGBIT64(1, 1) +/** @} */ + +#endif /* SC_SS_DB_DSC_H */ + +/** @} */ + diff --git a/platform/ss/db/v4/ss.h b/platform/ss/db/v4/ss.h new file mode 100755 index 0000000..ee54f79 --- /dev/null +++ b/platform/ss/db/v4/ss.h @@ -0,0 +1,83 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DB subsystem API. + * + * @addtogroup DB_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DB_SS_H +#define SC_SS_DB_SS_H + +#include "ss/inf/inf.h" + +/* Types */ + +typedef enum +{ + SS_V2X_AUTH_IP, + SS_V2X_AUTH_PASS, + SS_V2X_AUTH_FAIL +} ss_v2x_state_t; + +/* Externs */ + +SS_BASE_INFO_PROTO(db) + +/* Functions */ + +SS_FUNC_PROTO_DB + +void ss_auto_clock_gate_db(sc_bool_t enable); +void ss_v2x_enable(void); +void ss_v2x_set_state(ss_v2x_state_t state); +ss_v2x_state_t ss_v2x_get_state(void); +sc_bool_t ss_v2x_clock_run(sc_bool_t enable); +void ss_v2x_auth_finish(void); + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_db[]; + +#endif /* SC_SS_DB_SS_H */ + +/** @} */ + diff --git a/platform/ss/dblogic/v1/Makefile b/platform/ss/dblogic/v1/Makefile new file mode 100755 index 0000000..4dde1af --- /dev/null +++ b/platform/ss/dblogic/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/dblogic/v1/ss.o + +CONFIGH += $(SRC)/ss/dblogic/v1/config.h $(SRC)/ss/dblogic/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/dblogic/v1/resource.txt + +CLK_MD += $(SRC)/ss/dblogic/v1/clock.txt + +CTRL_MD += $(SRC)/ss/dblogic/v1/control.txt + +DIRS += $(OUT)/ss/dblogic/v1 + diff --git a/platform/ss/dblogic/v1/config.h b/platform/ss/dblogic/v1/config.h new file mode 100644 index 0000000..e589935 --- /dev/null +++ b/platform/ss/dblogic/v1/config.h @@ -0,0 +1,142 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the DBLOGIC subsystem. + * + * @addtogroup DBLOGIC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_DBLOGIC_CONFIG_H +#define SC_SS_DBLOGIC_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_DBLOGIC 9U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_DBLOGIC \ + void ss_prepost_power_mode_dblogic(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + void ss_link_enable_dblogic(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t \ + enable); \ + void ss_ssi_power_dblogic(sc_sub_t ss, sc_bool_t enable); \ + void ss_ssi_pause_mode_dblogic(sc_sub_t ss, sc_sub_t remote, uint8_t \ + port, sc_bool_t enable); \ + void ss_ssi_wait_idle_dblogic(sc_sub_t ss, sc_sub_t remote, uint8_t \ + port); \ + void ss_adb_enable_dblogic(sc_sub_t ss, sc_sub_t remote, sc_bool_t \ + enable); \ + void ss_adb_wait_dblogic(sc_sub_t ss, sc_sub_t remote, sc_bool_t \ + enable); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_DBLOGIC \ + { \ + ss_init_base, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_dblogic, \ + ss_iso_disable_base, \ + ss_link_enable_dblogic, \ + ss_ssi_power_dblogic, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_dblogic, \ + ss_ssi_wait_idle_dblogic, \ + ss_adb_enable_dblogic, \ + ss_adb_wait_dblogic, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DBLOGIC_0 \ + "DBLOGIC", \ + "GIC_SMMU", \ + "IRQSTR_M4_0", \ + "IRQSTR_M4_1", \ + "SMMU", \ + "GIC", \ + "IRQSTR_SCU2", \ + "IRQSTR_DSP", \ + "STM", \ + +#endif + +#endif /* SC_SS_DBLOGIC_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/dblogic/v1/dsc.h b/platform/ss/dblogic/v1/dsc.h new file mode 100755 index 0000000..8f545df --- /dev/null +++ b/platform/ss/dblogic/v1/dsc.h @@ -0,0 +1,117 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DBLOGIC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DBLOGIC_DSC_H +#define SC_SS_DBLOGIC_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SSI0_TBU_PM (0xFUL << 4) +#define GPR_SSI1_TBU_PM (0xFUL << 8) +#define GPR_SSI2_TBU_PM (0xFUL << 12) +#define GPR_SSI3_TBU_PM (0xFUL << 16) +#define GPR_ADB_PWRDNREQN0 REGBIT(0, 26) +#define GPR_STM_NSGUAREN_B REGBIT(0, 27) +#define GPR_ADB_PWRDNREQN1 REGBIT(0, 28) +#define GPR_SSI_IDLE_STRAP REGBIT(0, 29) +#define GPR_TCU_QREQN REGBIT(0, 30) +#define GPR_TCU_SPF_BYPASS REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#undef GPS_SSI0_PM_DATA_PEND +#define GPS_SSI0_PM_DATA_PEND REGBIT(0, 3) +#define GPS_SSI0_TBU_IDLE REGBIT(0, 4) +#define GPS_SSI0_TBU_PM_DATA_PEND REGBIT(0, 5) +#define GPS_SSI1_TBU_IDLE REGBIT(0, 6) +#define GPS_SSI1_TBU_PM_DATA_PEND REGBIT(0, 7) +#define GPS_SSI2_TBU_IDLE REGBIT(0, 8) +#define GPS_SSI2_TBU_PM_DATA_PEND REGBIT(0, 9) +#define GPS_SSI3_TBU_IDLE REGBIT(0, 10) +#define GPS_SSI3_TBU_PM_DATA_PEND REGBIT(0, 11) +#define GPS_STM_QACCEPTN REGBIT(0, 12) +#define GPS_STM_QDENY REGBIT(0, 13) +#define GPS_ADB_PWRDNACKN0 REGBIT(0, 24) +#define GPS_ADB_PWRDNACKN1 REGBIT(0, 25) +#define GPS_ADB_CACTIVE_S0 REGBIT(0, 26) +#define GPS_ADB_CACTIVE_S1 REGBIT(0, 27) +#define GPS_ADB_CACTIVE_M0 REGBIT(0, 28) +#define GPS_ADB_CACTIVE_M1 REGBIT(0, 29) +#define GPS_AWAKEUP_PTW REGBIT(0, 31) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GIC_WAKE00 REGBIT64(1, 0) +#define IRQ_GIC_WAKE01 REGBIT64(1, 1) +#define IRQ_GIC_WAKE02 REGBIT64(1, 2) +#define IRQ_GIC_WAKE03 REGBIT64(1, 3) +#define IRQ_GIC_WAKE10 REGBIT64(1, 4) +#define IRQ_GIC_WAKE11 REGBIT64(1, 5) +#define IRQ_IRQSTR_CTI0 REGBIT64(1, 8) +#define IRQ_IRQSTR_CTI1 REGBIT64(1, 9) +#define IRQ_IRQSTR_CTI2 REGBIT64(1, 10) +#define IRQ_IRQSTR_CTI3 REGBIT64(1, 11) +#define IRQ_IRQSTR_CTI4 REGBIT64(1, 12) +#define IRQ_GIC_ECC_FATAL REGBIT64(1, 13) +#define IRQ_GIC_AXI_ERR REGBIT64(1, 14) +/** @} */ + +#endif /* SC_SS_DBLOGIC_DSC_H */ + +/** @} */ + diff --git a/platform/ss/dblogic/v1/rsrc.h b/platform/ss/dblogic/v1/rsrc.h new file mode 100644 index 0000000..d119673 --- /dev/null +++ b/platform/ss/dblogic/v1/rsrc.h @@ -0,0 +1,70 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the DBLOGIC subsystem. + * + * @addtogroup DBLOGIC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_DBLOGIC_RSRC_H +#define SC_SS_DBLOGIC_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_DBLOGIC 0U +#define SS_R_GIC_SMMU 1U +#define SS_R_IRQSTR_M4_0 2U +#define SS_R_IRQSTR_M4_1 3U +#define SS_R_SMMU 4U +#define SS_R_GIC 5U +#define SS_R_IRQSTR_SCU2 6U +#define SS_R_IRQSTR_DSP 7U +#define SS_R_STM 8U +/** @} */ + +#endif /* SC_SS_DBLOGIC_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/dblogic/v1/ss.h b/platform/ss/dblogic/v1/ss.h new file mode 100755 index 0000000..2e2fae7 --- /dev/null +++ b/platform/ss/dblogic/v1/ss.h @@ -0,0 +1,69 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DBLOGIC subsystem API. + * + * @addtogroup DBLOGIC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DBLOGIC_SS_H +#define SC_SS_DBLOGIC_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(dblogic) + +/* Functions */ + +SS_FUNC_PROTO_DBLOGIC + +void smmu0_spf_bypass(sc_bool_t enable); + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_dblogic[]; + +#endif /* SC_SS_DBLOGIC_SS_H */ + +/** @} */ + diff --git a/platform/ss/dc/v1/Makefile b/platform/ss/dc/v1/Makefile new file mode 100755 index 0000000..94d600a --- /dev/null +++ b/platform/ss/dc/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/dc/v1/ss.o + +CONFIGH += $(SRC)/ss/dc/v1/config.h $(SRC)/ss/dc/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/dc/v1/resource.txt + +CLK_MD += $(SRC)/ss/dc/v1/clock.txt + +CTRL_MD += $(SRC)/ss/dc/v1/control.txt + +DIRS += $(OUT)/ss/dc/v1 + diff --git a/platform/ss/dc/v1/config.h b/platform/ss/dc/v1/config.h new file mode 100644 index 0000000..799d8b5 --- /dev/null +++ b/platform/ss/dc/v1/config.h @@ -0,0 +1,164 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the DC subsystem. + * + * @addtogroup DC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_DC_CONFIG_H +#define SC_SS_DC_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_DC 11U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_DC \ + void ss_trans_power_mode_dc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + sc_err_t ss_set_clock_rate_dc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_clock_enable_dc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); \ + sc_err_t ss_set_clock_parent_dc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t new_parent); \ + sc_err_t ss_get_clock_parent_dc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); \ + void ss_rdc_set_master_dc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + void ss_dump_dc(sc_sub_t ss, sc_bool_t xrdc, sc_bool_t dsc, sc_bool_t \ + clk); \ + void ss_prepost_clock_mode_dc(sc_sub_t ss, ss_clock_t clk, ss_prepost_t \ + type, sc_pm_clk_mode_t from_mode, sc_pm_clk_mode_t to_mode); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_DC \ + { \ + ss_init_base, \ + ss_trans_power_mode_dc, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_dc, \ + ss_get_clock_rate_base, \ + ss_clock_enable_dc, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_dc, \ + ss_get_clock_parent_dc, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_dc, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_dc, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_dc, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DC_0 \ + "DC_0", \ + "DC_0_BLIT_OUT", \ + "DC_0_BLIT2", \ + "DC_0_BLIT1", \ + "DC_0_BLIT0", \ + "DC_0_FRAC0", \ + "DC_0_VIDEO0", \ + "DC_0_VIDEO1", \ + "DC_0_WARP", \ + "DC_0_PLL_0", \ + "DC_0_PLL_1", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DC_1 \ + "DC_1", \ + "DC_1_BLIT_OUT", \ + "DC_1_BLIT2", \ + "DC_1_BLIT1", \ + "DC_1_BLIT0", \ + "DC_1_FRAC0", \ + "DC_1_VIDEO0", \ + "DC_1_VIDEO1", \ + "DC_1_WARP", \ + "DC_1_PLL_0", \ + "DC_1_PLL_1", \ + +#endif + +#endif /* SC_SS_DC_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/dc/v1/dsc.h b/platform/ss/dc/v1/dsc.h new file mode 100755 index 0000000..31486c8 --- /dev/null +++ b/platform/ss/dc/v1/dsc.h @@ -0,0 +1,122 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DC_DSC_H +#define SC_SS_DC_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_DSP0 REGBIT(0, 2) +#define RST_DSP1 REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_OBS_SEL0 REGBIT(0, 8) +#define GPR_OBS_SEL1 REGBIT(0, 9) +#define GPR_OBS_SEL2 REGBIT(0, 10) +#define GPR_PXL_LINK_MST1_ADDR REGBIT(0, 24) +#define GPR_PXL_LINK_MST2_ADDR REGBIT(0, 26) +#define GPR_IRIS_MVP_PANIC REGBIT(0, 28) +#define GPR_PXL_LINK_MST1_ENB REGBIT(0, 30) +#define GPR_PXL_LINK_MST2_ENB REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_DC_SYNC_MODE REGBIT(1, 32) +#define GPR_PXL_LINK_MST1_VLD REGBIT(1, 33) +#define GPR_PXL_LINK_MST2_VLD REGBIT(1, 34) +#define GPR_DIV_LINK_CLK_BY_2 REGBIT(1, 35) +#define GPR_KACHUNK_FRAC0 REGBIT(1, 36) +#define GPR_KACHUNK_VID0 REGBIT(1, 37) +#define GPR_KACHUNK_VID1 REGBIT(1, 38) +#define GPR_KACHUNK_WRAP0 REGBIT(1, 39) +#define GPR_PL_SYNC_CTRL0 REGBIT(1, 40) +#define GPR_PL_SYNC_CTRL1 REGBIT(1, 41) +#define GPR_PRG0_SEL REGBIT(1, 42) +#define GPR_PL_DSP0_CLK REGBIT(1, 43) +#define GPR_PL_DSP1_CLK REGBIT(1, 44) +#define GPR_KACHUNK_CNT_NUM0 REGBIT(1, 48) +#define GPR_KACHUNK_CNT_NUM1 REGBIT(1, 49) +#define GPR_KACHUNK_CNT_NUM2 REGBIT(1, 50) +#define GPR_KACHUNK_CNT_NUM3 REGBIT(1, 51) +#define GPR_KACHUNK_CNT_NUM4 REGBIT(1, 52) +#define GPR_KACHUNK_CNT_NUM5 REGBIT(1, 53) +#define GPR_KACHUNK_CNT_NUM6 REGBIT(1, 54) +#define GPR_KACHUNK_CNT_NUM7 REGBIT(1, 55) +#define GPR_KACHUNK_CNT_NUM8 REGBIT(1, 56) +#define GPR_KACHUNK_CNT_NUM9 REGBIT(1, 57) +#define GPR_KACHUNK_CNT_NUM10 REGBIT(1, 58) +#define GPR_KACHUNK_CNT_NUM11 REGBIT(1, 59) +#define GPR_KACHUNK_CNT_NUM12 REGBIT(1, 60) +#define GPR_KACHUNK_CNT_NUM13 REGBIT(1, 61) +#define GPR_KACHUNK_CNT_NUM14 REGBIT(1, 62) +#define GPR_KACHUNK_CNT_NUM15 REGBIT(1, 63) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_GPRCTRL16 REGBIT(0, 16) +#define GPS_GPRCTRL17 REGBIT(0, 17) +/** @} */ + +#endif /* SC_SS_DC_DSC_H */ + +/** @} */ + diff --git a/platform/ss/dc/v1/rsrc.h b/platform/ss/dc/v1/rsrc.h new file mode 100644 index 0000000..e4d2f06 --- /dev/null +++ b/platform/ss/dc/v1/rsrc.h @@ -0,0 +1,83 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the DC subsystem. + * + * @addtogroup DC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_DC_RSRC_H +#define SC_SS_DC_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_DC_0 0U +#define SS_R_DC_0_BLIT_OUT 1U +#define SS_R_DC_0_BLIT2 2U +#define SS_R_DC_0_BLIT1 3U +#define SS_R_DC_0_BLIT0 4U +#define SS_R_DC_0_FRAC0 5U +#define SS_R_DC_0_VIDEO0 6U +#define SS_R_DC_0_VIDEO1 7U +#define SS_R_DC_0_WARP 8U +#define SS_R_DC_0_PLL_0 9U +#define SS_R_DC_0_PLL_1 10U +#define SS_R_DC_1 0U +#define SS_R_DC_1_BLIT_OUT 1U +#define SS_R_DC_1_BLIT2 2U +#define SS_R_DC_1_BLIT1 3U +#define SS_R_DC_1_BLIT0 4U +#define SS_R_DC_1_FRAC0 5U +#define SS_R_DC_1_VIDEO0 6U +#define SS_R_DC_1_VIDEO1 7U +#define SS_R_DC_1_WARP 8U +#define SS_R_DC_1_PLL_0 9U +#define SS_R_DC_1_PLL_1 10U +/** @} */ + +#endif /* SC_SS_DC_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/dc/v1/ss.h b/platform/ss/dc/v1/ss.h new file mode 100755 index 0000000..db9a14c --- /dev/null +++ b/platform/ss/dc/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DC subsystem API. + * + * @addtogroup DC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DC_SS_H +#define SC_SS_DC_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(dc) + +/* Functions */ + +SS_FUNC_PROTO_DC + +#endif /* SC_SS_DC_SS_H */ + +/** @} */ + diff --git a/platform/ss/dma/v1/Makefile b/platform/ss/dma/v1/Makefile new file mode 100755 index 0000000..9a81403 --- /dev/null +++ b/platform/ss/dma/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/dma/v1/ss.o + +CONFIGH += $(SRC)/ss/dma/v1/config.h $(SRC)/ss/dma/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/dma/v1/resource.txt + +CLK_MD += $(SRC)/ss/dma/v1/clock.txt + +CTRL_MD += $(SRC)/ss/dma/v1/control.txt + +DIRS += $(OUT)/ss/dma/v1 + diff --git a/platform/ss/dma/v1/config.h b/platform/ss/dma/v1/config.h new file mode 100644 index 0000000..f84a551 --- /dev/null +++ b/platform/ss/dma/v1/config.h @@ -0,0 +1,212 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the DMA subsystem. + * + * @addtogroup DMA_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_DMA_CONFIG_H +#define SC_SS_DMA_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_DMA 87U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_DMA \ + void ss_trans_power_mode_dma(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + sc_err_t ss_set_control_dma(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + void ss_updown_dma(sc_sub_t ss, sc_bool_t up); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_DMA \ + { \ + ss_init_base, \ + ss_trans_power_mode_dma, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_dma, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_dma, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DMA_0 \ + "SPI_0", \ + "SPI_1", \ + "SPI_2", \ + "SPI_3", \ + "UART_0", \ + "UART_1", \ + "UART_2", \ + "UART_3", \ + "UART_4", \ + "EMVSIM_0", \ + "EMVSIM_1", \ + "DMA_0_CH0", \ + "DMA_0_CH1", \ + "DMA_0_CH2", \ + "DMA_0_CH3", \ + "DMA_0_CH4", \ + "DMA_0_CH5", \ + "DMA_0_CH6", \ + "DMA_0_CH7", \ + "DMA_0_CH8", \ + "DMA_0_CH9", \ + "DMA_0_CH10", \ + "DMA_0_CH11", \ + "DMA_0_CH12", \ + "DMA_0_CH13", \ + "DMA_0_CH14", \ + "DMA_0_CH15", \ + "DMA_0_CH16", \ + "DMA_0_CH17", \ + "DMA_0_CH18", \ + "DMA_0_CH19", \ + "DMA_0_CH20", \ + "DMA_0_CH21", \ + "DMA_0_CH22", \ + "DMA_0_CH23", \ + "DMA_0_CH24", \ + "DMA_0_CH25", \ + "DMA_0_CH26", \ + "DMA_0_CH27", \ + "DMA_0_CH28", \ + "DMA_0_CH29", \ + "DMA_0_CH30", \ + "DMA_0_CH31", \ + "I2C_0", \ + "I2C_1", \ + "I2C_2", \ + "I2C_3", \ + "I2C_4", \ + "ADC_0", \ + "ADC_1", \ + "FTM_0", \ + "FTM_1", \ + "CAN_0", \ + "CAN_1", \ + "CAN_2", \ + "DMA_1_CH0", \ + "DMA_1_CH1", \ + "DMA_1_CH2", \ + "DMA_1_CH3", \ + "DMA_1_CH4", \ + "DMA_1_CH5", \ + "DMA_1_CH6", \ + "DMA_1_CH7", \ + "DMA_1_CH8", \ + "DMA_1_CH9", \ + "DMA_1_CH10", \ + "DMA_1_CH11", \ + "DMA_1_CH12", \ + "DMA_1_CH13", \ + "DMA_1_CH14", \ + "DMA_1_CH15", \ + "DMA_1_CH16", \ + "DMA_1_CH17", \ + "DMA_1_CH18", \ + "DMA_1_CH19", \ + "DMA_1_CH20", \ + "DMA_1_CH21", \ + "DMA_1_CH22", \ + "DMA_1_CH23", \ + "DMA_1_CH24", \ + "DMA_1_CH25", \ + "DMA_1_CH26", \ + "DMA_1_CH27", \ + "DMA_1_CH28", \ + "DMA_1_CH29", \ + "DMA_1_CH30", \ + "DMA_1_CH31", \ + +#endif + +#endif /* SC_SS_DMA_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/dma/v1/dsc.h b/platform/ss/dma/v1/dsc.h new file mode 100755 index 0000000..e1ed076 --- /dev/null +++ b/platform/ss/dma/v1/dsc.h @@ -0,0 +1,246 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DMA_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DMA_DSC_H +#define SC_SS_DMA_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_OBS_SEL0 REGBIT(0, 8) +#define GPR_OBS_SEL1 REGBIT(0, 9) +#define GPR_OBS_SEL2 REGBIT(0, 10) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_EMVSIM0 REGBIT64(1, 0) +#define IRQ_EMVSIM1 REGBIT64(1, 1) +#define IRQ_LPI2C0 REGBIT64(1, 2) +#define IRQ_LPI2C1 REGBIT64(1, 3) +#define IRQ_LPI2C2 REGBIT64(1, 4) +#define IRQ_LPI2C3 REGBIT64(1, 5) +#define IRQ_LPI2C4 REGBIT64(1, 6) +#define IRQ_LPSPI0 REGBIT64(1, 7) +#define IRQ_LPSPI1 REGBIT64(1, 8) +#define IRQ_LPSPI2 REGBIT64(1, 9) +#define IRQ_LPSPI3 REGBIT64(1, 10) +#define IRQ_LPUART0 REGBIT64(1, 11) +#define IRQ_LPUART1 REGBIT64(1, 12) +#define IRQ_LPUART2 REGBIT64(1, 13) +#define IRQ_LPUART3 REGBIT64(1, 14) +#define IRQ_LPUART4 REGBIT64(1, 15) +#define IRQ_ADC0 REGBIT64(1, 16) +#define IRQ_ADC1 REGBIT64(1, 17) +/** @} */ + +/*! + * @name CSR3 0x00 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_DEBUG REGBIT(0x0, 0) +#define CSR3_EDMA1_IPG_DEBUG REGBIT(0x0, 1) +#define CSR3_SPI0_IPG_DEBUG REGBIT(0x0, 3) +#define CSR3_SPI1_IPG_DEBUG REGBIT(0x0, 4) +#define CSR3_SPI2_IPG_DEBUG REGBIT(0x0, 5) +#define CSR3_SPI3_IPG_DEBUG REGBIT(0x0, 6) +#define CSR3_UART0_IPG_DEBUG REGBIT(0x0, 8) +#define CSR3_UART1_IPG_DEBUG REGBIT(0x0, 9) +#define CSR3_UART2_IPG_DEBUG REGBIT(0x0, 10) +#define CSR3_UART3_IPG_DEBUG REGBIT(0x0, 11) +#define CSR3_UART4_IPG_DEBUG REGBIT(0x0, 12) +#define CSR3_SIM0_IPG_DEBUG REGBIT(0x0, 14) +#define CSR3_SIM1_IPG_DEBUG REGBIT(0x0, 15) +#define CSR3_I2C0_IPG_DEBUG REGBIT(0x0, 17) +#define CSR3_I2C1_IPG_DEBUG REGBIT(0x0, 18) +#define CSR3_I2C2_IPG_DEBUG REGBIT(0x0, 19) +#define CSR3_I2C3_IPG_DEBUG REGBIT(0x0, 20) +#define CSR3_I2C4_IPG_DEBUG REGBIT(0x0, 21) +#define CSR3_ADC0_IPG_DEBUG REGBIT(0x0, 23) +#define CSR3_ADC1_IPG_DEBUG REGBIT(0x0, 24) +#define CSR3_FTM0_IPG_DEBUG REGBIT(0x0, 26) +#define CSR3_FTM1_IPG_DEBUG REGBIT(0x0, 27) +#define CSR3_CAN0_IPG_DEBUG REGBIT(0x0, 29) +#define CSR3_CAN1_IPG_DEBUG REGBIT(0x0, 30) +#define CSR3_CAN2_IPG_DEBUG REGBIT(0x0, 31) +/** @} */ + +/*! + * @name CSR3 0x10 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_DOZE REGBIT(0x1, 0) +#define CSR3_EDMA1_IPG_DOZE REGBIT(0x1, 1) +#define CSR3_SPI0_IPG_DOZE REGBIT(0x1, 3) +#define CSR3_SPI1_IPG_DOZE REGBIT(0x1, 4) +#define CSR3_SPI2_IPG_DOZE REGBIT(0x1, 5) +#define CSR3_SPI3_IPG_DOZE REGBIT(0x1, 6) +#define CSR3_UART0_IPG_DOZE REGBIT(0x1, 8) +#define CSR3_UART1_IPG_DOZE REGBIT(0x1, 9) +#define CSR3_UART2_IPG_DOZE REGBIT(0x1, 10) +#define CSR3_UART3_IPG_DOZE REGBIT(0x1, 11) +#define CSR3_UART4_IPG_DOZE REGBIT(0x1, 12) +#define CSR3_SIM0_IPG_DOZE REGBIT(0x1, 14) +#define CSR3_SIM1_IPG_DOZE REGBIT(0x1, 15) +#define CSR3_I2C0_IPG_DOZE REGBIT(0x1, 17) +#define CSR3_I2C1_IPG_DOZE REGBIT(0x1, 18) +#define CSR3_I2C2_IPG_DOZE REGBIT(0x1, 19) +#define CSR3_I2C3_IPG_DOZE REGBIT(0x1, 20) +#define CSR3_I2C4_IPG_DOZE REGBIT(0x1, 21) +#define CSR3_ADC0_IPG_DOZE REGBIT(0x1, 23) +#define CSR3_ADC1_IPG_DOZE REGBIT(0x1, 24) +#define CSR3_FTM0_IPG_DOZE REGBIT(0x1, 26) +#define CSR3_FTM1_IPG_DOZE REGBIT(0x1, 27) +#define CSR3_CAN0_IPG_DOZE REGBIT(0x1, 29) +#define CSR3_CAN1_IPG_DOZE REGBIT(0x1, 30) +#define CSR3_CAN2_IPG_DOZE REGBIT(0x1, 31) +/** @} */ + +/*! + * @name CSR3 0x20 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP_MODE REGBIT(0x2, 0) +#define CSR3_EDMA1_IPG_STOP_MODE REGBIT(0x2, 1) +#define CSR3_SPI0_IPG_STOP_MODE REGBIT(0x2, 3) +#define CSR3_SPI1_IPG_STOP_MODE REGBIT(0x2, 4) +#define CSR3_SPI2_IPG_STOP_MODE REGBIT(0x2, 5) +#define CSR3_SPI3_IPG_STOP_MODE REGBIT(0x2, 6) +#define CSR3_UART0_IPG_STOP_MODE REGBIT(0x2, 8) +#define CSR3_UART1_IPG_STOP_MODE REGBIT(0x2, 9) +#define CSR3_UART2_IPG_STOP_MODE REGBIT(0x2, 10) +#define CSR3_UART3_IPG_STOP_MODE REGBIT(0x2, 11) +#define CSR3_UART4_IPG_STOP_MODE REGBIT(0x2, 12) +#define CSR3_SIM0_IPG_STOP_MODE REGBIT(0x2, 14) +#define CSR3_SIM1_IPG_STOP_MODE REGBIT(0x2, 15) +#define CSR3_I2C0_IPG_STOP_MODE REGBIT(0x2, 17) +#define CSR3_I2C1_IPG_STOP_MODE REGBIT(0x2, 18) +#define CSR3_I2C2_IPG_STOP_MODE REGBIT(0x2, 19) +#define CSR3_I2C3_IPG_STOP_MODE REGBIT(0x2, 20) +#define CSR3_I2C4_IPG_STOP_MODE REGBIT(0x2, 21) +#define CSR3_ADC0_IPG_STOP_MODE REGBIT(0x2, 23) +#define CSR3_ADC1_IPG_STOP_MODE REGBIT(0x2, 24) +#define CSR3_FTM0_IPG_STOP_MODE REGBIT(0x2, 26) +#define CSR3_FTM1_IPG_STOP_MODE REGBIT(0x2, 27) +#define CSR3_CAN0_IPG_STOP_MODE REGBIT(0x2, 29) +#define CSR3_CAN1_IPG_STOP_MODE REGBIT(0x2, 30) +#define CSR3_CAN2_IPG_STOP_MODE REGBIT(0x2, 31) +/** @} */ + +/*! + * @name CSR3 0x30 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP REGBIT(0x3, 0) +#define CSR3_EDMA1_IPG_STOP REGBIT(0x3, 1) +#define CSR3_SPI0_IPG_STOP REGBIT(0x3, 3) +#define CSR3_SPI1_IPG_STOP REGBIT(0x3, 4) +#define CSR3_SPI2_IPG_STOP REGBIT(0x3, 5) +#define CSR3_SPI3_IPG_STOP REGBIT(0x3, 6) +#define CSR3_UART0_IPG_STOP REGBIT(0x3, 8) +#define CSR3_UART1_IPG_STOP REGBIT(0x3, 9) +#define CSR3_UART2_IPG_STOP REGBIT(0x3, 10) +#define CSR3_UART3_IPG_STOP REGBIT(0x3, 11) +#define CSR3_UART4_IPG_STOP REGBIT(0x3, 12) +#define CSR3_SIM0_IPG_STOP REGBIT(0x3, 14) +#define CSR3_SIM1_IPG_STOP REGBIT(0x3, 15) +#define CSR3_I2C0_IPG_STOP REGBIT(0x3, 17) +#define CSR3_I2C1_IPG_STOP REGBIT(0x3, 18) +#define CSR3_I2C2_IPG_STOP REGBIT(0x3, 19) +#define CSR3_I2C3_IPG_STOP REGBIT(0x3, 20) +#define CSR3_I2C4_IPG_STOP REGBIT(0x3, 21) +#define CSR3_ADC0_IPG_STOP REGBIT(0x3, 23) +#define CSR3_ADC1_IPG_STOP REGBIT(0x3, 24) +#define CSR3_FTM0_IPG_STOP REGBIT(0x3, 26) +#define CSR3_FTM1_IPG_STOP REGBIT(0x3, 27) +#define CSR3_CAN0_IPG_STOP REGBIT(0x3, 29) +#define CSR3_CAN1_IPG_STOP REGBIT(0x3, 30) +#define CSR3_CAN2_IPG_STOP REGBIT(0x3, 31) + +/** @} */ + +/*! + * @name CSR3 0x40 Bit Definitions + */ +/** @{ */ +#define CSR3_EDMA0_IPG_STOP_ACK REGBIT(0x4, 0) +#define CSR3_EDMA1_IPG_STOP_ACK REGBIT(0x4, 1) +#define CSR3_SPI0_IPG_STOP_ACK REGBIT(0x4, 3) +#define CSR3_SPI1_IPG_STOP_ACK REGBIT(0x4, 4) +#define CSR3_SPI2_IPG_STOP_ACK REGBIT(0x4, 5) +#define CSR3_SPI3_IPG_STOP_ACK REGBIT(0x4, 6) +#define CSR3_UART0_IPG_STOP_ACK REGBIT(0x4, 8) +#define CSR3_UART1_IPG_STOP_ACK REGBIT(0x4, 9) +#define CSR3_UART2_IPG_STOP_ACK REGBIT(0x4, 10) +#define CSR3_UART3_IPG_STOP_ACK REGBIT(0x4, 11) +#define CSR3_UART4_IPG_STOP_ACK REGBIT(0x4, 12) +#define CSR3_SIM0_IPG_STOP_ACK REGBIT(0x4, 14) +#define CSR3_SIM1_IPG_STOP_ACK REGBIT(0x4, 15) +#define CSR3_I2C0_IPG_STOP_ACK REGBIT(0x4, 17) +#define CSR3_I2C1_IPG_STOP_ACK REGBIT(0x4, 18) +#define CSR3_I2C2_IPG_STOP_ACK REGBIT(0x4, 19) +#define CSR3_I2C3_IPG_STOP_ACK REGBIT(0x4, 20) +#define CSR3_I2C4_IPG_STOP_ACK REGBIT(0x4, 21) +#define CSR3_ADC0_IPG_STOP_ACK REGBIT(0x4, 23) +#define CSR3_ADC1_IPG_STOP_ACK REGBIT(0x4, 24) +#define CSR3_FTM0_IPG_STOP_ACK REGBIT(0x4, 26) +#define CSR3_FTM1_IPG_STOP_ACK REGBIT(0x4, 27) +#define CSR3_CAN0_IPG_STOP_ACK REGBIT(0x4, 29) +#define CSR3_CAN1_IPG_STOP_ACK REGBIT(0x4, 30) +#define CSR3_CAN2_IPG_STOP_ACK REGBIT(0x4, 31) +/** @} */ + +#endif /* SC_SS_DMA_DSC_H */ + +/** @} */ + diff --git a/platform/ss/dma/v1/rsrc.h b/platform/ss/dma/v1/rsrc.h new file mode 100644 index 0000000..d5a7e22 --- /dev/null +++ b/platform/ss/dma/v1/rsrc.h @@ -0,0 +1,148 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the DMA subsystem. + * + * @addtogroup DMA_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_DMA_RSRC_H +#define SC_SS_DMA_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_SPI_0 0U +#define SS_R_SPI_1 1U +#define SS_R_SPI_2 2U +#define SS_R_SPI_3 3U +#define SS_R_UART_0 4U +#define SS_R_UART_1 5U +#define SS_R_UART_2 6U +#define SS_R_UART_3 7U +#define SS_R_UART_4 8U +#define SS_R_EMVSIM_0 9U +#define SS_R_EMVSIM_1 10U +#define SS_R_DMA_0_CH0 11U +#define SS_R_DMA_0_CH1 12U +#define SS_R_DMA_0_CH2 13U +#define SS_R_DMA_0_CH3 14U +#define SS_R_DMA_0_CH4 15U +#define SS_R_DMA_0_CH5 16U +#define SS_R_DMA_0_CH6 17U +#define SS_R_DMA_0_CH7 18U +#define SS_R_DMA_0_CH8 19U +#define SS_R_DMA_0_CH9 20U +#define SS_R_DMA_0_CH10 21U +#define SS_R_DMA_0_CH11 22U +#define SS_R_DMA_0_CH12 23U +#define SS_R_DMA_0_CH13 24U +#define SS_R_DMA_0_CH14 25U +#define SS_R_DMA_0_CH15 26U +#define SS_R_DMA_0_CH16 27U +#define SS_R_DMA_0_CH17 28U +#define SS_R_DMA_0_CH18 29U +#define SS_R_DMA_0_CH19 30U +#define SS_R_DMA_0_CH20 31U +#define SS_R_DMA_0_CH21 32U +#define SS_R_DMA_0_CH22 33U +#define SS_R_DMA_0_CH23 34U +#define SS_R_DMA_0_CH24 35U +#define SS_R_DMA_0_CH25 36U +#define SS_R_DMA_0_CH26 37U +#define SS_R_DMA_0_CH27 38U +#define SS_R_DMA_0_CH28 39U +#define SS_R_DMA_0_CH29 40U +#define SS_R_DMA_0_CH30 41U +#define SS_R_DMA_0_CH31 42U +#define SS_R_I2C_0 43U +#define SS_R_I2C_1 44U +#define SS_R_I2C_2 45U +#define SS_R_I2C_3 46U +#define SS_R_I2C_4 47U +#define SS_R_ADC_0 48U +#define SS_R_ADC_1 49U +#define SS_R_FTM_0 50U +#define SS_R_FTM_1 51U +#define SS_R_CAN_0 52U +#define SS_R_CAN_1 53U +#define SS_R_CAN_2 54U +#define SS_R_DMA_1_CH0 55U +#define SS_R_DMA_1_CH1 56U +#define SS_R_DMA_1_CH2 57U +#define SS_R_DMA_1_CH3 58U +#define SS_R_DMA_1_CH4 59U +#define SS_R_DMA_1_CH5 60U +#define SS_R_DMA_1_CH6 61U +#define SS_R_DMA_1_CH7 62U +#define SS_R_DMA_1_CH8 63U +#define SS_R_DMA_1_CH9 64U +#define SS_R_DMA_1_CH10 65U +#define SS_R_DMA_1_CH11 66U +#define SS_R_DMA_1_CH12 67U +#define SS_R_DMA_1_CH13 68U +#define SS_R_DMA_1_CH14 69U +#define SS_R_DMA_1_CH15 70U +#define SS_R_DMA_1_CH16 71U +#define SS_R_DMA_1_CH17 72U +#define SS_R_DMA_1_CH18 73U +#define SS_R_DMA_1_CH19 74U +#define SS_R_DMA_1_CH20 75U +#define SS_R_DMA_1_CH21 76U +#define SS_R_DMA_1_CH22 77U +#define SS_R_DMA_1_CH23 78U +#define SS_R_DMA_1_CH24 79U +#define SS_R_DMA_1_CH25 80U +#define SS_R_DMA_1_CH26 81U +#define SS_R_DMA_1_CH27 82U +#define SS_R_DMA_1_CH28 83U +#define SS_R_DMA_1_CH29 84U +#define SS_R_DMA_1_CH30 85U +#define SS_R_DMA_1_CH31 86U +/** @} */ + +#endif /* SC_SS_DMA_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/dma/v1/ss.h b/platform/ss/dma/v1/ss.h new file mode 100755 index 0000000..bc56e97 --- /dev/null +++ b/platform/ss/dma/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DMA subsystem API. + * + * @addtogroup DMA_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DMA_SS_H +#define SC_SS_DMA_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(dma) + +/* Functions */ + +SS_FUNC_PROTO_DMA + +#endif /* SC_SS_DMA_SS_H */ + +/** @} */ + diff --git a/platform/ss/drc/v1/Makefile b/platform/ss/drc/v1/Makefile new file mode 100755 index 0000000..fd088d8 --- /dev/null +++ b/platform/ss/drc/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/drc/v1/ss.o + +CONFIGH += $(SRC)/ss/drc/v1/config.h $(SRC)/ss/drc/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/drc/v1/resource.txt + +CLK_MD += $(SRC)/ss/drc/v1/clock.txt + +CTRL_MD += $(SRC)/ss/drc/v1/control.txt + +DIRS += $(OUT)/ss/drc/v1 + diff --git a/platform/ss/drc/v1/config.h b/platform/ss/drc/v1/config.h new file mode 100644 index 0000000..dbb5599 --- /dev/null +++ b/platform/ss/drc/v1/config.h @@ -0,0 +1,134 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the DRC subsystem. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_DRC_CONFIG_H +#define SC_SS_DRC_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_DRC 1U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_DRC \ + void ss_init_drc(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_set_clock_rate_drc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_set_control_drc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + void ss_prepost_power_mode_drc(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_DRC \ + { \ + ss_init_drc, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_drc, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_drc, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_drc, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DRC_0 \ + "DRC_0", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_DRC_1 \ + "DRC_1", \ + +#endif + +#endif /* SC_SS_DRC_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/drc/v1/dsc.h b/platform/ss/drc/v1/dsc.h new file mode 100755 index 0000000..958931d --- /dev/null +++ b/platform/ss/drc/v1/dsc.h @@ -0,0 +1,107 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DRC_DSC_H +#define SC_SS_DRC_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_DDR_CRESETN REGBIT(0, 2) +#define RST_PHY_RSTN REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PRF1_AXI_ID REGBIT(0, 4) +#define GPR_SSI_IDLE_STRAP_DRC REGBIT(0, 9) +#define GPR_QCHAN_QEN REGBIT(0, 10) +#define GPR_PRF1_AXI_ID_MASK REGBIT(0, 11) +#define GPR_PRF2_AXI_ID REGBIT(0, 16) +#define GPR_PHY_MODE_0 REGBIT(0, 22) +#define GPR_PHY_MODE_1 REGBIT(0, 23) +#define GPR_RET_EN_I REGBIT(0, 27) +#define GPR_EXT_EN_I REGBIT(0, 28) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_PRF2_AXI_ID_MASK REGBIT(1, 16) +#define GPR_PRF3_AXI_ID REGBIT(1, 21) +#define GPR_PRF3_AXI_ID_MASK REGBIT(1, 26) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_DFI_INIT_COMP REGBIT(0, 17) +#define GPS_CSYSACK_0 REGBIT(0, 19) +#define GPS_CSYSACK_DDRC REGBIT(0, 21) +#define GPS_PHY_BYP_MODE REGBIT(0, 22) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_CSYSACK_0 REGBIT64(1, 0) +#define IRQ_CSYSACK_DDRC REGBIT64(1, 1) +/** @} */ + +#endif /* SC_SS_DRC_DSC_H */ + +/** @} */ + diff --git a/platform/ss/drc/v1/rsrc.h b/platform/ss/drc/v1/rsrc.h new file mode 100644 index 0000000..b90a81e --- /dev/null +++ b/platform/ss/drc/v1/rsrc.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the DRC subsystem. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_DRC_RSRC_H +#define SC_SS_DRC_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_DRC_0 0U +#define SS_R_DRC_1 0U +/** @} */ + +#endif /* SC_SS_DRC_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/drc/v1/ss.h b/platform/ss/drc/v1/ss.h new file mode 100755 index 0000000..a6f7094 --- /dev/null +++ b/platform/ss/drc/v1/ss.h @@ -0,0 +1,66 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DRC subsystem API. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DRC_SS_H +#define SC_SS_DRC_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(drc) + +/* Functions */ + +SS_FUNC_PROTO_DRC + +void ss_drc_enable(sc_sub_t ss, sc_bool_t enable); +uint32_t ss_drc_get_config(sc_sub_t ss); + +#endif /* SC_SS_DRC_SS_H */ + +/** @} */ + diff --git a/platform/ss/drc/v2/Makefile b/platform/ss/drc/v2/Makefile new file mode 100755 index 0000000..da6f45d --- /dev/null +++ b/platform/ss/drc/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/drc/v2/ss.o + +CONFIGH += $(SRC)/ss/drc/v2/config.h $(SRC)/ss/drc/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/drc/v2/resource.txt + +CLK_MD += $(SRC)/ss/drc/v2/clock.txt + +CTRL_MD += $(SRC)/ss/drc/v2/control.txt + +DIRS += $(OUT)/ss/drc/v2 + diff --git a/platform/ss/drc/v2/dsc.h b/platform/ss/drc/v2/dsc.h new file mode 100755 index 0000000..ebb7bd9 --- /dev/null +++ b/platform/ss/drc/v2/dsc.h @@ -0,0 +1,109 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DRC_DSC_H +#define SC_SS_DRC_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_DDR_CRESETN REGBIT(0, 2) +#define RST_PHY_RSTN REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PRF1_AXI_ID REGBIT(0, 4) +#define GPR_SSI_IDLE_STRAP_DRC REGBIT(0, 9) +#define GPR_QCHAN_QEN REGBIT(0, 10) +#define GPR_PRF1_AXI_ID_MASK REGBIT(0, 11) +#define GPR_PRF2_AXI_ID REGBIT(0, 16) +#define GPR_PHY_MODE_0 REGBIT(0, 22) +#define GPR_PHY_MODE_1 REGBIT(0, 23) +#define GPR_RET_EN_I REGBIT(0, 27) +#define GPR_EXT_EN_I REGBIT(0, 28) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_SBR_START_MASK REGBIT(1, 0) +#define GPR_SBR_RANGE_MASK REGBIT(1, 8) +#define GPR_PRF2_AXI_ID_MASK REGBIT(1, 16) +#define GPR_PRF3_AXI_ID REGBIT(1, 21) +#define GPR_PRF3_AXI_ID_MASK REGBIT(1, 26) +#define GPR_ANAMIX_SPARE0 REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_CSYSACK_0 REGBIT(0, 19) +#define GPS_CSYSACK_DDRC REGBIT(0, 21) +#define GPS_PHY_BYP_MODE REGBIT(0, 22) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_CSYSACK_0 REGBIT64(1, 0) +#define IRQ_CSYSACK_DDRC REGBIT64(1, 1) +/** @} */ + +#endif /* SC_SS_DRC_DSC_H */ + +/** @} */ + diff --git a/platform/ss/drc/v2/ss.h b/platform/ss/drc/v2/ss.h new file mode 100755 index 0000000..a6f7094 --- /dev/null +++ b/platform/ss/drc/v2/ss.h @@ -0,0 +1,66 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DRC subsystem API. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DRC_SS_H +#define SC_SS_DRC_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(drc) + +/* Functions */ + +SS_FUNC_PROTO_DRC + +void ss_drc_enable(sc_sub_t ss, sc_bool_t enable); +uint32_t ss_drc_get_config(sc_sub_t ss); + +#endif /* SC_SS_DRC_SS_H */ + +/** @} */ + diff --git a/platform/ss/drc/v3/Makefile b/platform/ss/drc/v3/Makefile new file mode 100755 index 0000000..0d60e89 --- /dev/null +++ b/platform/ss/drc/v3/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/drc/v3/ss.o + +CONFIGH += $(SRC)/ss/drc/v3/config.h $(SRC)/ss/drc/v3/rsrc.h + +RSRC_MD += $(SRC)/ss/drc/v3/resource.txt + +CLK_MD += $(SRC)/ss/drc/v3/clock.txt + +CTRL_MD += $(SRC)/ss/drc/v3/control.txt + +DIRS += $(OUT)/ss/drc/v3 + diff --git a/platform/ss/drc/v3/dsc.h b/platform/ss/drc/v3/dsc.h new file mode 100755 index 0000000..ebb7bd9 --- /dev/null +++ b/platform/ss/drc/v3/dsc.h @@ -0,0 +1,109 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DRC_DSC_H +#define SC_SS_DRC_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_DDR_CRESETN REGBIT(0, 2) +#define RST_PHY_RSTN REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PRF1_AXI_ID REGBIT(0, 4) +#define GPR_SSI_IDLE_STRAP_DRC REGBIT(0, 9) +#define GPR_QCHAN_QEN REGBIT(0, 10) +#define GPR_PRF1_AXI_ID_MASK REGBIT(0, 11) +#define GPR_PRF2_AXI_ID REGBIT(0, 16) +#define GPR_PHY_MODE_0 REGBIT(0, 22) +#define GPR_PHY_MODE_1 REGBIT(0, 23) +#define GPR_RET_EN_I REGBIT(0, 27) +#define GPR_EXT_EN_I REGBIT(0, 28) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_SBR_START_MASK REGBIT(1, 0) +#define GPR_SBR_RANGE_MASK REGBIT(1, 8) +#define GPR_PRF2_AXI_ID_MASK REGBIT(1, 16) +#define GPR_PRF3_AXI_ID REGBIT(1, 21) +#define GPR_PRF3_AXI_ID_MASK REGBIT(1, 26) +#define GPR_ANAMIX_SPARE0 REGBIT(1, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_CSYSACK_0 REGBIT(0, 19) +#define GPS_CSYSACK_DDRC REGBIT(0, 21) +#define GPS_PHY_BYP_MODE REGBIT(0, 22) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_CSYSACK_0 REGBIT64(1, 0) +#define IRQ_CSYSACK_DDRC REGBIT64(1, 1) +/** @} */ + +#endif /* SC_SS_DRC_DSC_H */ + +/** @} */ + diff --git a/platform/ss/drc/v3/ss.h b/platform/ss/drc/v3/ss.h new file mode 100755 index 0000000..e965648 --- /dev/null +++ b/platform/ss/drc/v3/ss.h @@ -0,0 +1,65 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the DRC subsystem API. + * + * @addtogroup DRC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_DRC_SS_H +#define SC_SS_DRC_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(drc) + +/* Functions */ + +SS_FUNC_PROTO_DRC + +void ss_drc_enable(sc_sub_t ss, sc_bool_t enable); +uint32_t ss_drc_get_config(sc_sub_t ss); + +#endif /* SC_SS_DRC_SS_H */ + +/** @} */ + diff --git a/platform/ss/gpu/v1/Makefile b/platform/ss/gpu/v1/Makefile new file mode 100755 index 0000000..b12ce29 --- /dev/null +++ b/platform/ss/gpu/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/gpu/v1/ss.o + +CONFIGH += $(SRC)/ss/gpu/v1/config.h $(SRC)/ss/gpu/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/gpu/v1/resource.txt + +CLK_MD += $(SRC)/ss/gpu/v1/clock.txt + +CTRL_MD += $(SRC)/ss/gpu/v1/control.txt + +DIRS += $(OUT)/ss/gpu/v1 + diff --git a/platform/ss/gpu/v1/config.h b/platform/ss/gpu/v1/config.h new file mode 100644 index 0000000..b424487 --- /dev/null +++ b/platform/ss/gpu/v1/config.h @@ -0,0 +1,138 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the GPU subsystem. + * + * @addtogroup GPU_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_GPU_CONFIG_H +#define SC_SS_GPU_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_GPU 4U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_GPU \ + void ss_init_gpu(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_set_clock_rate_gpu(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + void ss_prepost_power_mode_gpu(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_GPU \ + { \ + ss_init_gpu, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_gpu, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_gpu, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_GPU_0 \ + "GPU_0_PID0", \ + "GPU_0_PID1", \ + "GPU_0_PID2", \ + "GPU_0_PID3", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_GPU_1 \ + "GPU_1_PID0", \ + "GPU_1_PID1", \ + "GPU_1_PID2", \ + "GPU_1_PID3", \ + +#endif + +#endif /* SC_SS_GPU_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/gpu/v1/dsc.h b/platform/ss/gpu/v1/dsc.h new file mode 100755 index 0000000..1fee76e --- /dev/null +++ b/platform/ss/gpu/v1/dsc.h @@ -0,0 +1,73 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup GPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_GPU_DSC_H +#define SC_SS_GPU_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_ID REGBIT(0, 4) +#define GPR_SINGLE_MODE REGBIT(0, 8) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_CLOCK_WAKE_GLITCH REGBIT(0, 2) +#define GPS_PM_DATA_PEND REGBIT(0, 4) +/** @} */ + +#endif /* SC_SS_GPU_DSC_H */ + +/** @} */ + diff --git a/platform/ss/gpu/v1/rsrc.h b/platform/ss/gpu/v1/rsrc.h new file mode 100644 index 0000000..97bd53e --- /dev/null +++ b/platform/ss/gpu/v1/rsrc.h @@ -0,0 +1,69 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the GPU subsystem. + * + * @addtogroup GPU_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_GPU_RSRC_H +#define SC_SS_GPU_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_GPU_0_PID0 0U +#define SS_R_GPU_0_PID1 1U +#define SS_R_GPU_0_PID2 2U +#define SS_R_GPU_0_PID3 3U +#define SS_R_GPU_1_PID0 0U +#define SS_R_GPU_1_PID1 1U +#define SS_R_GPU_1_PID2 2U +#define SS_R_GPU_1_PID3 3U +/** @} */ + +#endif /* SC_SS_GPU_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/gpu/v1/ss.h b/platform/ss/gpu/v1/ss.h new file mode 100755 index 0000000..be6421c --- /dev/null +++ b/platform/ss/gpu/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the GPU subsystem API. + * + * @addtogroup GPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_GPU_SS_H +#define SC_SS_GPU_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(gpu) + +/* Functions */ + +SS_FUNC_PROTO_GPU + +#endif /* SC_SS_GPU_SS_H */ + +/** @} */ + diff --git a/platform/ss/gpu/v2/Makefile b/platform/ss/gpu/v2/Makefile new file mode 100755 index 0000000..dea666c --- /dev/null +++ b/platform/ss/gpu/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/gpu/v2/ss.o + +CONFIGH += $(SRC)/ss/gpu/v2/config.h $(SRC)/ss/gpu/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/gpu/v2/resource.txt + +CLK_MD += $(SRC)/ss/gpu/v2/clock.txt + +CTRL_MD += $(SRC)/ss/gpu/v2/control.txt + +DIRS += $(OUT)/ss/gpu/v2 + diff --git a/platform/ss/gpu/v2/dsc.h b/platform/ss/gpu/v2/dsc.h new file mode 100755 index 0000000..1641c3e --- /dev/null +++ b/platform/ss/gpu/v2/dsc.h @@ -0,0 +1,71 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup GPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_GPU_DSC_H +#define SC_SS_GPU_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_ID REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_CLOCK_WAKE_GLITCH REGBIT(0, 2) +/** @} */ + +#endif /* SC_SS_GPU_DSC_H */ + +/** @} */ + diff --git a/platform/ss/gpu/v2/ss.h b/platform/ss/gpu/v2/ss.h new file mode 100755 index 0000000..be6421c --- /dev/null +++ b/platform/ss/gpu/v2/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the GPU subsystem API. + * + * @addtogroup GPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_GPU_SS_H +#define SC_SS_GPU_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(gpu) + +/* Functions */ + +SS_FUNC_PROTO_GPU + +#endif /* SC_SS_GPU_SS_H */ + +/** @} */ + diff --git a/platform/ss/hdmi/v1/Makefile b/platform/ss/hdmi/v1/Makefile new file mode 100755 index 0000000..23ee868 --- /dev/null +++ b/platform/ss/hdmi/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/hdmi/v1/ss.o + +CONFIGH += $(SRC)/ss/hdmi/v1/config.h $(SRC)/ss/hdmi/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/hdmi/v1/resource.txt + +CLK_MD += $(SRC)/ss/hdmi/v1/clock.txt + +CTRL_MD += $(SRC)/ss/hdmi/v1/control.txt + +DIRS += $(OUT)/ss/hdmi/v1 + diff --git a/platform/ss/hdmi/v1/config.h b/platform/ss/hdmi/v1/config.h new file mode 100644 index 0000000..6802bc9 --- /dev/null +++ b/platform/ss/hdmi/v1/config.h @@ -0,0 +1,139 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the HDMI subsystem. + * + * @addtogroup HDMI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_HDMI_CONFIG_H +#define SC_SS_HDMI_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_HDMI 5U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_HDMI \ + void ss_trans_power_mode_hdmi(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + sc_err_t ss_set_clock_rate_hdmi(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_set_clock_parent_hdmi(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t \ + new_parent); \ + sc_err_t ss_set_control_hdmi(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + sc_err_t ss_get_control_hdmi(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t *val); \ + void ss_prepost_power_mode_hdmi(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_HDMI \ + { \ + ss_init_base, \ + ss_trans_power_mode_hdmi, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_hdmi, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_hdmi, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_hdmi, \ + ss_get_control_hdmi, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_hdmi, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_HDMI_0 \ + "HDMI", \ + "HDMI_I2S", \ + "HDMI_I2C_0", \ + "HDMI_PLL_0", \ + "HDMI_PLL_1", \ + +#endif + +#endif /* SC_SS_HDMI_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/hdmi/v1/dsc.h b/platform/ss/hdmi/v1/dsc.h new file mode 100755 index 0000000..cbd7981 --- /dev/null +++ b/platform/ss/hdmi/v1/dsc.h @@ -0,0 +1,104 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup HDMI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HDMI_DSC_H +#define SC_SS_HDMI_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_PHY REGBIT(0, 2) +#define RST_HPD_FILTER REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 8) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 9) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 10) +#define GPR_PWM0_IPG_STOP REGBIT(0, 11) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 12) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 13) +#define GPR_I2C0_IPG_STOP REGBIT(0, 14) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 15) +#define GPR_PHY_ISO_ENABLE REGBIT(0, 17) +#define GPR_PLL_REF_CLK_SELECT REGBIT(0, 18) +#define GPR_PD_PAD REGBIT(0, 24) +#define GPR_LNK_BID6 REGBIT(0, 25) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 4) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO0 REGBIT64(1, 0) +#define IRQ_GPIO1 REGBIT64(1, 1) +#define IRQ_GPIO2 REGBIT64(1, 2) +#define IRQ_GPIO3 REGBIT64(1, 3) +#define IRQ_GPIO4 REGBIT64(1, 4) +#define IRQ_GPIO5 REGBIT64(1, 5) +#define IRQ_GPIO6 REGBIT64(1, 6) +#define IRQ_GPIO7 REGBIT64(1, 7) +/** @} */ + +#endif /* SC_SS_HDMI_DSC_H */ + +/** @} */ + diff --git a/platform/ss/hdmi/v1/rsrc.h b/platform/ss/hdmi/v1/rsrc.h new file mode 100644 index 0000000..dad387d --- /dev/null +++ b/platform/ss/hdmi/v1/rsrc.h @@ -0,0 +1,66 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the HDMI subsystem. + * + * @addtogroup HDMI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_HDMI_RSRC_H +#define SC_SS_HDMI_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_HDMI 0U +#define SS_R_HDMI_I2S 1U +#define SS_R_HDMI_I2C_0 2U +#define SS_R_HDMI_PLL_0 3U +#define SS_R_HDMI_PLL_1 4U +/** @} */ + +#endif /* SC_SS_HDMI_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/hdmi/v1/ss.h b/platform/ss/hdmi/v1/ss.h new file mode 100755 index 0000000..e5f1473 --- /dev/null +++ b/platform/ss/hdmi/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the HDMI subsystem API. + * + * @addtogroup HDMI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HDMI_SS_H +#define SC_SS_HDMI_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(hdmi) + +/* Functions */ + +SS_FUNC_PROTO_HDMI + +#endif /* SC_SS_HDMI_SS_H */ + +/** @} */ + diff --git a/platform/ss/hdmi_rx/v1/Makefile b/platform/ss/hdmi_rx/v1/Makefile new file mode 100755 index 0000000..43d2d73 --- /dev/null +++ b/platform/ss/hdmi_rx/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/hdmi_rx/v1/ss.o + +CONFIGH += $(SRC)/ss/hdmi_rx/v1/config.h $(SRC)/ss/hdmi_rx/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/hdmi_rx/v1/resource.txt + +CLK_MD += $(SRC)/ss/hdmi_rx/v1/clock.txt + +CTRL_MD += $(SRC)/ss/hdmi_rx/v1/control.txt + +DIRS += $(OUT)/ss/hdmi_rx/v1 + diff --git a/platform/ss/hdmi_rx/v1/config.h b/platform/ss/hdmi_rx/v1/config.h new file mode 100644 index 0000000..b51a52c --- /dev/null +++ b/platform/ss/hdmi_rx/v1/config.h @@ -0,0 +1,129 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the HDMI_RX subsystem. + * + * @addtogroup HDMI_RX_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_HDMI_RX_CONFIG_H +#define SC_SS_HDMI_RX_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_HDMI_RX 4U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_HDMI_RX \ + void ss_trans_power_mode_hdmi_rx(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_power_mode_t from_mode, \ + sc_pm_power_mode_t to_mode); \ + void ss_prepost_power_mode_hdmi_rx(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_HDMI_RX \ + { \ + ss_init_base, \ + ss_trans_power_mode_hdmi_rx, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_hdmi_rx, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_HDMI_RX_0 \ + "HDMI_RX", \ + "HDMI_RX_BYPASS", \ + "HDMI_RX_I2C_0", \ + "HDMI_RX_PWM_0", \ + +#endif + +#endif /* SC_SS_HDMI_RX_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/hdmi_rx/v1/dsc.h b/platform/ss/hdmi_rx/v1/dsc.h new file mode 100755 index 0000000..076d666 --- /dev/null +++ b/platform/ss/hdmi_rx/v1/dsc.h @@ -0,0 +1,87 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup HDMI_RX_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HDMI_RX_DSC_H +#define SC_SS_HDMI_RX_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_PHY REGBIT(0, 2) +#define RST_HPD_FILTER REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 8) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 9) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 10) +#define GPR_PWM0_IPG_STOP REGBIT(0, 11) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 12) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 13) +#define GPR_I2C0_IPG_STOP REGBIT(0, 14) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 15) +#define GPR_HDP_PHY_ISO REGBIT(0, 16) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 4) +/** @} */ + +#endif /* SC_SS_HDMI_RX_DSC_H */ + +/** @} */ + diff --git a/platform/ss/hdmi_rx/v1/rsrc.h b/platform/ss/hdmi_rx/v1/rsrc.h new file mode 100644 index 0000000..432963e --- /dev/null +++ b/platform/ss/hdmi_rx/v1/rsrc.h @@ -0,0 +1,65 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the HDMI_RX subsystem. + * + * @addtogroup HDMI_RX_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_HDMI_RX_RSRC_H +#define SC_SS_HDMI_RX_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_HDMI_RX 0U +#define SS_R_HDMI_RX_BYPASS 1U +#define SS_R_HDMI_RX_I2C_0 2U +#define SS_R_HDMI_RX_PWM_0 3U +/** @} */ + +#endif /* SC_SS_HDMI_RX_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/hdmi_rx/v1/ss.h b/platform/ss/hdmi_rx/v1/ss.h new file mode 100755 index 0000000..33dc1dc --- /dev/null +++ b/platform/ss/hdmi_rx/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the HDMI_RX subsystem API. + * + * @addtogroup HDMI_RX_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HDMI_RX_SS_H +#define SC_SS_HDMI_RX_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(hdmi_rx) + +/* Functions */ + +SS_FUNC_PROTO_HDMI_RX + +#endif /* SC_SS_HDMI_RX_SS_H */ + +/** @} */ + diff --git a/platform/ss/hsio/v1/Makefile b/platform/ss/hsio/v1/Makefile new file mode 100755 index 0000000..af2f54d --- /dev/null +++ b/platform/ss/hsio/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/hsio/v1/ss.o + +CONFIGH += $(SRC)/ss/hsio/v1/config.h $(SRC)/ss/hsio/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/hsio/v1/resource.txt + +CLK_MD += $(SRC)/ss/hsio/v1/clock.txt + +CTRL_MD += $(SRC)/ss/hsio/v1/control.txt + +DIRS += $(OUT)/ss/hsio/v1 + diff --git a/platform/ss/hsio/v1/config.h b/platform/ss/hsio/v1/config.h new file mode 100644 index 0000000..4d0f7d8 --- /dev/null +++ b/platform/ss/hsio/v1/config.h @@ -0,0 +1,164 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the HSIO subsystem. + * + * @addtogroup HSIO_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_HSIO_CONFIG_H +#define SC_SS_HSIO_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_HSIO 35U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_HSIO \ + void ss_init_hsio(sc_sub_t ss, sc_bool_t api_phase); \ + void ss_rdc_enable_hsio(sc_sub_t ss, sc_bool_t master); \ + void ss_rdc_set_master_hsio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + sc_err_t ss_set_control_hsio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + void ss_prepost_power_mode_hsio(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_HSIO \ + { \ + ss_init_hsio, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_hsio, \ + ss_rdc_set_master_hsio, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_hsio, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_hsio, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_HSIO_0 \ + "PCIE_A", \ + "PCIE_B", \ + "SATA_0", \ + "SERDES_0", \ + "SERDES_1", \ + "HSIO_GPIO", \ + "MATCH_0", \ + "MATCH_1", \ + "MATCH_2", \ + "MATCH_3", \ + "MATCH_4", \ + "MATCH_5", \ + "MATCH_6", \ + "MATCH_7", \ + "MATCH_8", \ + "MATCH_9", \ + "MATCH_10", \ + "MATCH_11", \ + "MATCH_12", \ + "MATCH_13", \ + "MATCH_14", \ + "MATCH_15", \ + "MATCH_16", \ + "MATCH_17", \ + "MATCH_18", \ + "MATCH_19", \ + "MATCH_20", \ + "MATCH_21", \ + "MATCH_22", \ + "MATCH_23", \ + "MATCH_24", \ + "MATCH_25", \ + "MATCH_26", \ + "MATCH_27", \ + "MATCH_28", \ + +#endif + +#endif /* SC_SS_HSIO_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/hsio/v1/dsc.h b/platform/ss/hsio/v1/dsc.h new file mode 100755 index 0000000..26e281f --- /dev/null +++ b/platform/ss/hsio/v1/dsc.h @@ -0,0 +1,95 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup HSIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HSIO_DSC_H +#define SC_SS_HSIO_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_SS_PCIE_A REGBIT(0, 2) +#define RST_SS_PCIE_B REGBIT(0, 3) +#define RST_SS_SATA REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_DBG_SEL0 REGBIT(0, 8) +#define GPR_DBG_SEL1 REGBIT(0, 9) +#define GPR_DBG_SEL2 REGBIT(0, 10) +#define GPR_DBG_SEL3 REGBIT(0, 11) +#define GPR_DBG_SEL4 REGBIT(0, 12) +#define GPR_DBG_SEL5 REGBIT(0, 13) +#define GPR_DBG_SATA_SEL0 REGBIT(0, 14) +#define GPR_DBG_SATA_SEL1 REGBIT(0, 15) +#define GPR_DBG_SATA_SEL2 REGBIT(0, 16) +#define GPR_ISO_EN_PHY_LDO REGBIT(0, 17) +#define GPR_ISO_POWER_GOOD REGBIT(0, 18) +#define GPR_ISO_EN_HPLL_IOB REGBIT(0, 19) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_PCIE_A REGBIT64(1, 0) +#define IRQ_PCIE_B REGBIT64(1, 1) +#define IRQ_GPIO_0_2 REGBIT64(1, 2) +#define IRQ_GPIO_3_5 REGBIT64(1, 3) +#define IRQ_SATA_0 REGBIT64(1, 4) +/** @} */ + +#endif /* SC_SS_HSIO_DSC_H */ + +/** @} */ + diff --git a/platform/ss/hsio/v1/rsrc.h b/platform/ss/hsio/v1/rsrc.h new file mode 100644 index 0000000..a815738 --- /dev/null +++ b/platform/ss/hsio/v1/rsrc.h @@ -0,0 +1,96 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the HSIO subsystem. + * + * @addtogroup HSIO_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_HSIO_RSRC_H +#define SC_SS_HSIO_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_PCIE_A 0U +#define SS_R_PCIE_B 1U +#define SS_R_SATA_0 2U +#define SS_R_SERDES_0 3U +#define SS_R_SERDES_1 4U +#define SS_R_HSIO_GPIO 5U +#define SS_R_MATCH_0 6U +#define SS_R_MATCH_1 7U +#define SS_R_MATCH_2 8U +#define SS_R_MATCH_3 9U +#define SS_R_MATCH_4 10U +#define SS_R_MATCH_5 11U +#define SS_R_MATCH_6 12U +#define SS_R_MATCH_7 13U +#define SS_R_MATCH_8 14U +#define SS_R_MATCH_9 15U +#define SS_R_MATCH_10 16U +#define SS_R_MATCH_11 17U +#define SS_R_MATCH_12 18U +#define SS_R_MATCH_13 19U +#define SS_R_MATCH_14 20U +#define SS_R_MATCH_15 21U +#define SS_R_MATCH_16 22U +#define SS_R_MATCH_17 23U +#define SS_R_MATCH_18 24U +#define SS_R_MATCH_19 25U +#define SS_R_MATCH_20 26U +#define SS_R_MATCH_21 27U +#define SS_R_MATCH_22 28U +#define SS_R_MATCH_23 29U +#define SS_R_MATCH_24 30U +#define SS_R_MATCH_25 31U +#define SS_R_MATCH_26 32U +#define SS_R_MATCH_27 33U +#define SS_R_MATCH_28 34U +/** @} */ + +#endif /* SC_SS_HSIO_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/hsio/v1/ss.h b/platform/ss/hsio/v1/ss.h new file mode 100755 index 0000000..afdb840 --- /dev/null +++ b/platform/ss/hsio/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the HSIO subsystem API. + * + * @addtogroup HSIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HSIO_SS_H +#define SC_SS_HSIO_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(hsio) + +/* Functions */ + +SS_FUNC_PROTO_HSIO + +#endif /* SC_SS_HSIO_SS_H */ + +/** @} */ + diff --git a/platform/ss/hsio/v2/Makefile b/platform/ss/hsio/v2/Makefile new file mode 100755 index 0000000..aeb569b --- /dev/null +++ b/platform/ss/hsio/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/hsio/v2/ss.o + +CONFIGH += $(SRC)/ss/hsio/v2/config.h $(SRC)/ss/hsio/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/hsio/v2/resource.txt + +CLK_MD += $(SRC)/ss/hsio/v2/clock.txt + +CTRL_MD += $(SRC)/ss/hsio/v2/control.txt + +DIRS += $(OUT)/ss/hsio/v2 + diff --git a/platform/ss/hsio/v2/dsc.h b/platform/ss/hsio/v2/dsc.h new file mode 100755 index 0000000..960e8aa --- /dev/null +++ b/platform/ss/hsio/v2/dsc.h @@ -0,0 +1,93 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup HSIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HSIO_DSC_H +#define SC_SS_HSIO_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_SS_PCIE_A REGBIT(0, 2) +#define RST_SS_PCIE_B REGBIT(0, 3) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_DBG_SEL0 REGBIT(0, 8) +#define GPR_DBG_SEL1 REGBIT(0, 9) +#define GPR_DBG_SEL2 REGBIT(0, 10) +#define GPR_DBG_SEL3 REGBIT(0, 11) +#define GPR_DBG_SEL4 REGBIT(0, 12) +#define GPR_DBG_SEL5 REGBIT(0, 13) +#define GPR_ISO_EN_PHY_LDO REGBIT(0, 17) +#define GPR_ISO_POWER_GOOD REGBIT(0, 18) +#define GPR_ISO_EN_HPLL_IOB REGBIT(0, 19) +#define GPR_PIPE_RATE_DSC0 REGBIT(0, 29) +#define GPR_PIPE_RATE_DSC1 REGBIT(0, 30) +#define GPR_PIPE_RATE_OVR REGBIT(0, 31) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_PCIE_A REGBIT64(1, 1) +#define IRQ_GPIO_0_2 REGBIT64(1, 2) +#define IRQ_GPIO_3_5 REGBIT64(1, 3) +#define IRQ_DMA REGBIT64(1, 7) +/** @} */ + +#endif /* SC_SS_HSIO_DSC_H */ + +/** @} */ + diff --git a/platform/ss/hsio/v2/ss.h b/platform/ss/hsio/v2/ss.h new file mode 100755 index 0000000..afdb840 --- /dev/null +++ b/platform/ss/hsio/v2/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the HSIO subsystem API. + * + * @addtogroup HSIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_HSIO_SS_H +#define SC_SS_HSIO_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(hsio) + +/* Functions */ + +SS_FUNC_PROTO_HSIO + +#endif /* SC_SS_HSIO_SS_H */ + +/** @} */ + diff --git a/platform/ss/img/v1/Makefile b/platform/ss/img/v1/Makefile new file mode 100755 index 0000000..0eccf03 --- /dev/null +++ b/platform/ss/img/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/img/v1/ss.o + +CONFIGH += $(SRC)/ss/img/v1/config.h $(SRC)/ss/img/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/img/v1/resource.txt + +CLK_MD += $(SRC)/ss/img/v1/clock.txt + +CTRL_MD += $(SRC)/ss/img/v1/control.txt + +DIRS += $(OUT)/ss/img/v1 + diff --git a/platform/ss/img/v1/config.h b/platform/ss/img/v1/config.h new file mode 100644 index 0000000..4c891ba --- /dev/null +++ b/platform/ss/img/v1/config.h @@ -0,0 +1,143 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the IMG subsystem. + * + * @addtogroup IMG_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_IMG_CONFIG_H +#define SC_SS_IMG_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_IMG 18U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_IMG \ + void ss_trans_power_mode_img(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + void ss_prepost_power_mode_img(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_IMG \ + { \ + ss_init_base, \ + ss_trans_power_mode_img, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_img, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_IMG_0 \ + "ISI_CH0", \ + "ISI_CH1", \ + "ISI_CH2", \ + "ISI_CH3", \ + "ISI_CH4", \ + "ISI_CH5", \ + "ISI_CH6", \ + "ISI_CH7", \ + "MJPEG_DEC_MP", \ + "MJPEG_DEC_S0", \ + "MJPEG_DEC_S1", \ + "MJPEG_DEC_S2", \ + "MJPEG_DEC_S3", \ + "MJPEG_ENC_MP", \ + "MJPEG_ENC_S0", \ + "MJPEG_ENC_S1", \ + "MJPEG_ENC_S2", \ + "MJPEG_ENC_S3", \ + +#endif + +#endif /* SC_SS_IMG_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/img/v1/dsc.h b/platform/ss/img/v1/dsc.h new file mode 100755 index 0000000..1d0b84a --- /dev/null +++ b/platform/ss/img/v1/dsc.h @@ -0,0 +1,64 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup IMG_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_IMG_DSC_H +#define SC_SS_IMG_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_SS_ISI REGBIT(0, 2) +/** @} */ + +#endif /* SC_SS_IMG_DSC_H */ + +/** @} */ + diff --git a/platform/ss/img/v1/rsrc.h b/platform/ss/img/v1/rsrc.h new file mode 100644 index 0000000..ccee3c8 --- /dev/null +++ b/platform/ss/img/v1/rsrc.h @@ -0,0 +1,79 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the IMG subsystem. + * + * @addtogroup IMG_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_IMG_RSRC_H +#define SC_SS_IMG_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_ISI_CH0 0U +#define SS_R_ISI_CH1 1U +#define SS_R_ISI_CH2 2U +#define SS_R_ISI_CH3 3U +#define SS_R_ISI_CH4 4U +#define SS_R_ISI_CH5 5U +#define SS_R_ISI_CH6 6U +#define SS_R_ISI_CH7 7U +#define SS_R_MJPEG_DEC_MP 8U +#define SS_R_MJPEG_DEC_S0 9U +#define SS_R_MJPEG_DEC_S1 10U +#define SS_R_MJPEG_DEC_S2 11U +#define SS_R_MJPEG_DEC_S3 12U +#define SS_R_MJPEG_ENC_MP 13U +#define SS_R_MJPEG_ENC_S0 14U +#define SS_R_MJPEG_ENC_S1 15U +#define SS_R_MJPEG_ENC_S2 16U +#define SS_R_MJPEG_ENC_S3 17U +/** @} */ + +#endif /* SC_SS_IMG_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/img/v1/ss.h b/platform/ss/img/v1/ss.h new file mode 100755 index 0000000..67921b9 --- /dev/null +++ b/platform/ss/img/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the IMG subsystem API. + * + * @addtogroup IMG_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_IMG_SS_H +#define SC_SS_IMG_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(img) + +/* Functions */ + +SS_FUNC_PROTO_IMG + +#endif /* SC_SS_IMG_SS_H */ + +/** @} */ + diff --git a/platform/ss/inf/Makefile b/platform/ss/inf/Makefile new file mode 100755 index 0000000..ae33184 --- /dev/null +++ b/platform/ss/inf/Makefile @@ -0,0 +1,6 @@ + +OBJS += $(OUT)/ss/inf/inf.o + +INFH += $(SRC)/ss/inf/inf_ss.h + +DIRS += $(OUT)/ss/inf diff --git a/platform/ss/inf/inf.h b/platform/ss/inf/inf.h new file mode 100755 index 0000000..f0ff4c6 --- /dev/null +++ b/platform/ss/inf/inf.h @@ -0,0 +1,1078 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Common functions for interfacing with the subsystems. + * + * @addtogroup INF_SS INF: Subsystem Interface + * + * @brief Module for common subsystem access. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_INF_H +#define SC_SS_INF_H + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/svc.h" +#include "svc/pm/svc.h" +#include "svc/irq/svc.h" +#include "drivers/dsc/fsl_dsc.h" +#include "drivers/xrdc2/fsl_xrdc2.h" + +/* Defines */ + +#define SS_CLK_W 6U //!< Width of ss_clock_t +#define SS_PLL_W 2U //!< Width of ss_pll_t +#define SS_IO_W 4U //!< Width of ss_io_type_t +#define SS_XEXP_W 8U //!< Width of ss_xexp_idx_t +#define SS_FIELD_POS_W 16U //!< Width of I/O field position +#define SS_FIELD_WID_W 6U //!< Width of I/O field width +#define SS_CID_W 4U //!< Width of CPU ID +#define SS_IDX_W 8U //!< Width of SS index +#define SS_NUM_SSI_W 2U //!< Width of num SSIs + +#define SS_MAX_CLK 35U //!< Max number of clocks per subsystem +#define SS_MAX_PLL 3U //!< Max number of PLLs per subsystem + +#define SS_MAX_PM_CLKS 5U + +/*! Define to indicate invalid power domains and clocks */ +#define NV ((uint8_t) UINT8_MAX) + +/*! Define to fill in a sc_rsrc_map_t variable */ +#define RSRC(R, I, X) \ +{ \ + .resource = U16(SC_R_##R), \ + .inst = U8(I), \ + .ss_idx = U8(X) \ +} + +#define SS_I1 0x8001U + +#define XNFO_DL {0U, 0U} + +#ifdef DISABLE_LPCG_AT_PD_PUP +#define LPCG_INFO \ + .num_lpcg = SS_NUM_LPCG, \ + .lpcg_info = SS_LPCG_ADDR_INFO +#else +#define LPCG_INFO +#endif + +#ifdef XRDC_SUPPORT + /*! Define to fill in a ss_base_info_t variable (with XRDC) */ + #define BASE_INFO(XEXP_INFO, MDAC_INFO, PAC_INFO, MSC_INFO, MRC_INFO, CTRL_INFO) \ + .num_rsrc = SS_NUM_RSRC, \ + .num_srsrc = SS_NUM_SRSRC, \ + .num_prsrc = SS_NUM_PRSRC, \ + .num_prsrc2 = SS_NUM_PRSRC2, \ + .rsrc = ss_rsrc_info, \ + .rsrc_map = rsrc_map, \ + .num_pd = SS_NUM_PD, \ + .pd_info = ss_pd_info, \ + .pd_reboot_info = SS_PD_REBOOT_INFO,\ + .num_ctrl = SS_NUM_CTRL, \ + .ctrl_info = (CTRL_INFO), \ + .dsc_aon_reset_mask = SS_AON_RESET, \ + .irq_enb = SS_IRQ_ENB, \ + .pd_dsc = SS_PD_DSC, \ + .pd_ssi = SS_PD_SSI, \ + .num_clks = SS_NUM_CLK, \ + .clk_info = ss_clk_info, \ + .ss_iso_info = ss_iso_info, \ + .num_pll = SS_NUM_PLL, \ + .mu_irq = SS_MU_IRQ, \ + .dscmix = SS_DSCMIX, \ + .ai_type = SS_AI_TYPE, \ + .ss_phy_iso = SS_PHY_ISO, \ + .ss_num_ssi = SS_NUM_SSI, \ + .mtr_clk_idx = MTR_CLK_IDX, \ + .pd_mgr = SS_PD_MGR, \ + .xexp_info = (XEXP_INFO), \ + .num_mdac = SS_NUM_MDAC, \ + .mdac_info = (MDAC_INFO), \ + .mdac_match = SS_MDAC_MATCH, \ + .mdac_cache = SS_MDAC_CACHE, \ + .num_pac = SS_NUM_PAC, \ + .pac_info = (PAC_INFO), \ + .num_msc = SS_NUM_MSC, \ + .msc_info = (MSC_INFO), \ + .num_mrc = SS_NUM_MRC, \ + .mrc_info = (MRC_INFO), \ + .mrc_mask = SS_MRC_MASK, \ + .mrc_cache = SS_MRC_CACHE, \ + LPCG_INFO +#else + /*! Define to fill in a ss_base_info_t variable (without XRDC) */ + #define BASE_INFO(XEXP_INFO, MDAC_INFO, PAC_INFO, MSC_INFO, MRC_INFO, CTRL_INFO) \ + .num_rsrc = SS_NUM_RSRC, \ + .num_srsrc = SS_NUM_SRSRC, \ + .num_prsrc = SS_NUM_PRSRC, \ + .num_prsrc2 = SS_NUM_PRSRC2, \ + .rsrc = ss_rsrc_info, \ + .rsrc_map = rsrc_map, \ + .num_pd = SS_NUM_PD, \ + .pd_info = ss_pd_info, \ + .pd_reboot_info = SS_PD_REBOOT_INFO,\ + .num_ctrl = SS_NUM_CTRL, \ + .ctrl_info = (CTRL_INFO), \ + .dsc_aon_reset_mask = SS_AON_RESET, \ + .irq_enb = SS_IRQ_ENB, \ + .pd_dsc = SS_PD_DSC, \ + .pd_ssi = SS_PD_SSI, \ + .num_clks = SS_NUM_CLK, \ + .clk_info = ss_clk_info, \ + .ss_iso_info = ss_iso_info, \ + .num_pll = SS_NUM_PLL, \ + .mu_irq = SS_MU_IRQ, \ + .dscmix = SS_DSCMIX, \ + .ai_type = SS_AI_TYPE, \ + .ss_phy_iso = SS_PHY_ISO, \ + .ss_num_ssi = SS_NUM_SSI, \ + .mtr_clk_idx = MTR_CLK_IDX, \ + LPCG_INFO +#endif /* XRDC_SUPPORT */ + +#ifdef XRDC_SUPPORT + /*! Define to fill in a ss_rsrc_info_t variable (with XRDC) */ + #define RNFO(PWD, C1 ,C2 ,C3 ,C4, C5, M, P, X, MI, PI, MATCHF, MASKF) \ + { \ + .master = U2B(M), \ + .peripheral = U2B(P), \ + .pd = U8(PWD), \ + .clk = {U8(C1), U8(C2), U8(C3), U8(C4), U8(C5)}, \ + .xexp_idx = U8(X), \ + .xrdc_master_idx = U16(MI), \ + .xrdc_peripheral_idx = U16(PI), \ + .xrdc_mda_match = U16(MATCHF), \ + .xrdc_mda_mask = U16(MASKF) \ + } +#else + /*! Define to fill in a ss_rsrc_info_t variable (without XRDC) */ + #define RNFO(PWD, C1 ,C2 ,C3 ,C4, C5, M, P, X, MI, PI, MATCHF, MASKF) \ + { \ + .master = U2B(M), \ + .peripheral = U2B(P), \ + .pd = U8(PWD), \ + .clk = {U8(C1), U8(C2), U8(C3), U8(C4), U8(C5)} \ + } +#endif /* XRDC_SUPPORT */ + +/*! Define to fill in a ss_xexp_info_t variable */ +#define XNFO(S, N) \ +{ \ + .start = U16(S), \ + .num = U8(N), \ +} + +/*! Define to fill in a ss_ctrl_info_t variable */ +#define TNFO(R, C, IO, B, W) \ +{ \ + .ss_idx = U8(SS_R_##R), \ + .ctrl = U8(SC_C_##C), \ + .io = (SS_IO_##IO), \ + .bit = U16(B), \ + .width = U8(W) \ +} + +/*! Define to fill in a ss_mrc_info_t variable */ +#define MNFO(P, ST, EN, AJ, M, I, SL, PWD, SB, C) \ +{ \ + .present = U2B(P), \ + .start = U64(ST), \ + .end = U64(EN), \ + .adjust = U64(AJ), \ + .mrc = U16(M), \ + .idx = U16(I), \ + .num_slots = U16(SL), \ + .pd = U8(PWD), \ + .sub = U8(SB), \ + .cache = (uint32_t*) (C) \ +} + +/* Types */ + +/*! + * This type is used to indicate pre- or post-amble function calls. + */ +typedef enum +{ + SS_PREAMBLE, //!< Preamble function call + SS_POSTAMBLE //!< Postamble function call +} ss_prepost_t; + +/*! + * This type is used to indicate type of DSC I/O. + */ +typedef enum +{ + SS_IO_GPR_CTRL, //!< GPR Control + SS_IO_GPR_STAT, //!< GPR Status + SS_IO_CSR, //!< CSR + SS_IO_CSR2, //!< CSR2 + SS_IO_CSR3, //!< CSR3 + SS_IO_AI_RW, //!< Analog Interface (RW) + SS_IO_AI_RO, //!< Analog Interface (RO) + SS_IO_RST_CTRL, //!< Reset control + SS_IO_BRD_CTRL, //!< Board control + SS_IO_SW_CTRL //!< Software control +} ss_io_type_t; + +/*! Type for a ss resource index */ +typedef uint8_t ss_idx_t; + +/*! Type for a resource index */ +typedef sc_rm_idx_t ss_ridx_t; + +/*! Type for a clock index */ +typedef uint8_t ss_clock_t; + +/*! Type for a PLL index */ +typedef uint8_t ss_pll_t; + +/*! Type for an XRDC expansion info index */ +typedef uint8_t ss_xexp_idx_t; + +/*! + * This type is used to store static constant info about the PACs in a + * subsystem. + */ +typedef xrdc_pac_info_t ss_pac_info_t; + +/*! + * This type is used store static constant info to map resources + * to the containing subsystem. + */ +typedef struct +{ + sc_rsrc_t resource : SC_RSRC_W; + ss_idx_t ss_idx : SS_IDX_W; + sc_ss_inst_t inst : SC_SS_INST_W; +} sc_rsrc_map_t; + +/*! + * This type is used store static constant info about resources in a + * subsystem. A pointer to this structure can be found in the + * ss_base_info_t type. + */ +typedef struct +{ + #ifdef XRDC_SUPPORT + sc_rm_idx_t xrdc_master_idx : SC_RM_IDX_W; //!< XRDC MDAC MDA index + sc_rm_idx_t xrdc_peripheral_idx : SC_RM_IDX_W; //!< XRDC PAC PDAC index + sc_rm_match_t xrdc_mda_match : SC_RM_MATCH_W;//!< XRDC MDAC match + sc_rm_match_t xrdc_mda_mask : SC_RM_MATCH_W;//!< XRDC MDAC mask + ss_xexp_idx_t xexp_idx : SS_XEXP_W; //!< XRDC expansion index + #endif /* XRDC_SUPPORT */ + ss_clock_t clk[SS_MAX_PM_CLKS]; //!< Clocks + dsc_pdom_t pd : DSC_PDOM_W; //!< Power domain + sc_bool_t master : SC_BOOL_W; //!< Master flag + sc_bool_t peripheral : SC_BOOL_W; //!< Slave flag +} ss_rsrc_info_t; + +/*! + * This type is used store static constant info about controls in a + * subsystem. A pointer to this structure can be found in the + * ss_base_info_t type. + */ +typedef struct +{ + uint16_t bit : SS_FIELD_POS_W; //!< Field position + ss_idx_t ss_idx : SS_IDX_W; //!< SS resource index + uint8_t width : SS_FIELD_WID_W; //!< Field width + sc_ctrl_t ctrl : SC_CTRL_W; //!< Control + ss_io_type_t io : SS_IO_W; //!< I/O type +} ss_ctrl_info_t; + +#ifdef DISABLE_LPCG_AT_PD_PUP +typedef struct +{ + volatile uint32_t * lpcg_addr; //!< LPCG offset + xrdc_idx_t pac_idx; + uint8_t num_cont_addr; + dsc_pdom_t pd; +} ss_lpcg_info_t; +#endif + +/*! + * This type is used to store static constant info about the power domains + * in the subsystem. + */ +typedef struct +{ + uint32_t reset_mask; //!< Resets associated with the PD +} ss_pd_info_t; + +/*! + * This type is used to store static constant info about resources to + * keep assigned to the SCU or associated with another resource. + */ +typedef struct +{ + xrdc_idx_t start; //!< Start slot + uint8_t num; //!< Number of slots +} ss_xexp_info_t; + +/*! + * This type is used to store static constant info about the MDACs in a + * subsystem. + */ +typedef struct +{ + xrdc_idx_t num_slots : XRDC_NUM_W; //!< Number of slots + dsc_pdom_t pd : DSC_PDOM_W; //!< Power domain + uint8_t cid : SS_CID_W; //!< CPU ID + sc_bool_t present : SC_BOOL_W; //!< Present + uint32_t *cache; //!< Cache pointer +} ss_mdac_info_t; + +/*! + * This type is used to store static constant info about the MSCs in a + * subsystem. + */ +typedef struct +{ + dsc_pdom_t pd : DSC_PDOM_W; //!< Power domain + sc_bool_t present : SC_BOOL_W; //!< Present +} ss_msc_info_t; + +/*! + * This type is used to store static constant info about the MRCs in a + * subsystem. Start->end address range indicates memory space covered + * by an MRC. + */ +typedef struct +{ + sc_faddr_t start; //!< Start address + sc_faddr_t end; //!< End address + sc_faddr_t adjust; //!< Sub/mask for this MRC + uint32_t *cache; //!< Cache pointer + xrdc_idx_t mrc : XRDC_NUM_W; //!< MRC index + xrdc_idx_t idx : XRDC_NUM_W; //!< index of first entry + xrdc_idx_t num_slots : XRDC_NUM_W; //!< Number of slots + dsc_pdom_t pd : DSC_PDOM_W; //!< Power domain + dsc_pdom_t sub : SC_BOOL_W; //!< Adjust by subtraction + sc_bool_t present : SC_BOOL_W; //!< Present +} ss_mrc_info_t; + +/*! + * This type is used to store static constant info about a subsystem. An + * array for all subsytems is declared in inf.c called ss_base_info. From + * this array info for subsystems inc. resources, XRDC components, power + * domains, etc. can be accessed. + */ +typedef struct +{ + uint64_t irq_enb; //!< Initial DSC IRQ enables + #ifdef XRDC_SUPPORT + const sc_faddr_t mrc_mask; //!< Range of MRCs in subsystem + #endif /* XRDC_SUPPORT */ + const ss_rsrc_info_t *rsrc; //!< Pointer to resource info + const sc_rsrc_map_t *rsrc_map; //!< Pointer to resource map + const ss_pd_info_t *pd_info; //!< Pointer to power domain info + const ss_pd_info_t *pd_reboot_info; //!< Pointer to power domain info + const ss_ctrl_info_t *ctrl_info; //!< Pointer to control info + const dsc_clk_info_t *clk_info; //!< Pointer to clock info + #ifdef DISABLE_LPCG_AT_PD_PUP + const ss_lpcg_info_t *lpcg_info; //!< Pointer to LPCG info + #endif + const uint8_t *ss_iso_info; //!< SS Isolation info + uint32_t dsc_aon_reset_mask; //!< Resets associated with DSC AON + uint32_t ss_phy_iso; //!< Additional ISO control (usually phy) + #ifdef XRDC_SUPPORT + const ss_xexp_info_t *xexp_info; //!< Pointer to xexp info + const ss_mdac_info_t *mdac_info; //!< Pointer to MDAC info + const ss_pac_info_t *pac_info; //!< Pointer to PAC info + const ss_msc_info_t *msc_info; //!< Pointer to MSC info + const ss_mrc_info_t *mrc_info; //!< Pointer to MRC info + uint32_t mdac_match; //!< MDAC match flags + uint16_t mdac_cache; //!< Size of MDAC cache (per inst) + uint16_t mrc_cache; //!< Size of MRC cache (per inst) + #endif /* XRDC_SUPPORT */ + sc_rm_idx_t num_rsrc : SC_RM_IDX_W; //!< Number of resources + sc_rm_idx_t num_srsrc : SC_RM_IDX_W; //!< Number of resources with children + #ifdef XRDC_SUPPORT + xrdc_idx_t num_mdac : XRDC_NUM_W; //!< Number of XRDC MDACs + xrdc_idx_t num_pac : XRDC_NUM_W; //!< Number of XRDC PACs + xrdc_idx_t num_msc : XRDC_NUM_W; //!< Number of XRDC MSCs + xrdc_idx_t num_mrc : XRDC_NUM_W; //!< Number of XRDC MRCs + #endif /* XRDC_SUPPORT */ + sc_rms_idx_t num_prsrc : SC_RMS_IDX_W; //!< Number of resources with parent + sc_rms_idx_t num_prsrc2 : SC_RMS_IDX_W; //!< Number of resources with second parent + #ifdef DISABLE_LPCG_AT_PD_PUP + uint8_t num_lpcg : DSC_NUM_LPCG_W; //!< Number of lpcg in the ss + #endif + ss_clock_t num_clks : SS_CLK_W+1; //!< Number of clocks + sc_ctrl_t num_ctrl : SC_CTRL_W; //!< Number of controls + dsc_pdom_t num_pd : DSC_PDOM_W+1; //!< Number of power domains + dsc_pdom_t pd_dsc : DSC_PDOM_W; //!< Power domain of the gated DSC logic + dsc_pdom_t pd_ssi : DSC_PDOM_W; //!< Power domain of the SSI + #ifdef XRDC_SUPPORT + dsc_pdom_t pd_mgr : DSC_PDOM_W; //!< Power domain of XRDC manager + #endif /* XRDC_SUPPORT */ + ss_pll_t num_pll : SS_PLL_W+1; //!< Number of PLLs + dsc_ai_type_t ai_type : DSC_AI_TYPE_W; //!< Type of AI for this SS + uint8_t ss_num_ssi : SS_NUM_SSI_W; //!< Number of standard SSI + ss_clock_t mtr_clk_idx : SS_CLK_W; //! < Clock index of the MTR clock + sc_bool_t mu_irq : SC_BOOL_W; //!< SS has interrupt trigger MU + sc_bool_t dscmix : SC_BOOL_W; //!< DSCMIX clock present +} ss_base_info_t; + +/*! + * This type is used to store dynamic data about the clocks/PLLs in + * the subsystem. + */ +typedef struct +{ + uint16_t usecount; //!< Count of peripherals using clock + sc_pm_clk_mode_t cur_mode : SC_PM_CLOCK_MODE_W; //!< Current mode of the clock + sc_pm_clk_parent_t parent; //!< Current parent of the clock + union { + uint32_t rate_div; //!< Current rate divider for the clock + uint32_t parent_rate; //!< store rate for parent clocks (pll, byp, xtal) + }; +} ss_clk_data_t; + +/*! + * This type is used to store dynamic data about a subsystem. + */ +typedef struct +{ + ss_clk_data_t clk_data[SS_MAX_CLK]; //!< Clock/PLL data + ss_pll_t num_pll; //!< number of PLLs in the SS + uint16_t usecount[DSC_MAX_PD][SC_PM_PW_MODE_ON];//!< PD use counts + sc_pm_power_mode_t power_mode[DSC_MAX_PD]; //!< Power mode of each power domain + #ifdef XRDC_SUPPORT + uint8_t master_did[SC_RM_NUM_DOMAIN]; //!< Count of masters in each resource domain + #endif /* XRDC_SUPPORT */ +} ss_base_data_t; + +/*! Type for IRQ handler */ +typedef sc_bool_t (*ss_dsc_l2irq_handler)(sc_dsc_t dsc, uint32_t irqIndex); + +/* Include auto generated interface info */ +#include "inf_ss.h" + +/*! + * @name Interface Functions + * @{ + */ + +/*! + * This function initalizes a subsystem. + * + * @param[in] ss subsystem to initialize + * @param[in] api_phase flag indicating phase + * + * There are two phases to subsystem intialization. The fist phase is + * the API phase (\a api_phase = SC_TRUE) and initializes all of the subsystem + * interface data structures. The second phase is the HW phase and this + * initializes the SS hardware. Both are called from main() only. + */ +/* IDL: SS_INIT() */ +void ss_init(sc_sub_t ss, sc_bool_t api_phase); + +/*! + * This function transitions a resource from one power mode to another. + * + * @param[in] rsrc_idx unified resource index + * @param[in] from_mode current resource power mode + * @param[in] to_mode requested new resource power mode + * + * This function will be dispatched to the subsystem containing + * \a rsrc_idx. If required, the subsystem power domains will change + * (dsc, ssi, and that containing \a rsrc_idx). + */ +/* IDL: SS_TRANS_POWER_MODE() */ +void ss_trans_power_mode(ss_ridx_t rsrc_idx, + sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); + +/*! + * This function requests a resource be reset. + * + * @param[in] rsrc_idx unified resource index + * @param[in] pt partition + * @param[in] pre pre-power off reset + * + * If pt equals SC_PT_ALL then reset all resources belonging + * to that partition. Otherwise, reset rsrc_idx only. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: SS_RSRC_RESET() */ +sc_err_t ss_rsrc_reset(ss_ridx_t rsrc_idx, sc_rm_pt_t pt, + sc_bool_t pre); + +/*! + * This function requests the power power mode to be entered + * for some resources under certain circumstances. + * + * @param[in] rsrc_idx unified resource index + * @param[in] mode requested low-power mode + * @param[in] wake_src low-power mode wake source + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This function will be dispatched to the subsystem containing + * \a rsrc_idx. If required, the subsystem power domains will change + * (dsc, ssi, and that containing \a rsrc_idx). + */ +/* IDL: SS_SET_CPU_POWER_MODE() */ +sc_err_t ss_set_cpu_power_mode(ss_ridx_t rsrc_idx, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); + +/*! + * This function sets the resume address of a CPU. + * + * @param[in] rsrc_idx unified resource index of CPU + * @param[in] isPrimary set SC_TRUE if primary wake CPU + * @param[in] addr boot address for CPU + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: SS_SET_CPU_RESUME() */ +sc_err_t ss_set_cpu_resume(ss_ridx_t rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); + +/*! + * This function requests the power mode for system-level interfaces + * including messaging units, interconnect, and memories. + * + * @param[in] rsrc_idx unified resource index + * @param[in] sys_if system-level interface to be configured + * @param[in] hpm high-power mode for the system interface + * @param[in] lpm low-power mode for the system interface + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +/* IDL: SS_REQ_SYS_IF_POWER_MODE() */ +sc_err_t ss_req_sys_if_power_mode(ss_ridx_t rsrc_idx, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); + +/*! + * This function sets a clock rate. + * + * @param[in] rsrc_idx unified resource index + * @param[in] clk clk to set + * @param[in,out] rate pointer to rate to set (Hz) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Will return actual rate that could be achieved in \a rate. + */ +/* IDL: SS_SET_CLOCK_RATE() */ +sc_err_t ss_set_clock_rate(ss_ridx_t rsrc_idx, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); + +/*! + * This function gets a clock rate. + * + * @param[in] rsrc_idx unified resource index + * @param[in] clk clk to get + * @param[out] rate pointer to return rate (Hz) + * + * @return Returns the rate of the clock in Hz. + */ +/* IDL: SS_GET_CLOCK_RATE() */ +sc_err_t ss_get_clock_rate(ss_ridx_t rsrc_idx, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate); + +/*! + * This function enables a clock. + * + * @param[in] rsrc_idx unified resource index + * @param[in] clk clk to enable/disable + * @param[in,out] enable flag indicating state (SC_TRUE = enable) + * @param[in,out] autog flag indicating HW autogate mode + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: SS_CLOCK_ENABLE() */ +sc_err_t ss_clock_enable(ss_ridx_t rsrc_idx, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog); + +/*! + * This function enables a clock. + * + * @param[in] rsrc_idx unified resource index + * @param[in] clk clk to enable/disable + * @param[in,out] enable flag indicating state (SC_TRUE = enable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This function forces the clock to the desired state regardless of + * any other gating input (hardware, etc.). + */ +/* IDL: SS_FORCE_CLOCK_ENABLE() */ +sc_err_t ss_force_clock_enable(ss_ridx_t rsrc_idx, sc_pm_clk_t clk, + sc_bool_t enable); + +/*! + * This function sets the parent of a resource's clock. + * This function should only be called when the clock is disabled. + * + * @param[in] rsrc_idx unified resource index + * @param[in] clk clock to affect + * @param[in] new_parent New parent of the clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * - SC_ERR_BUSY if clock is currently enabled. + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +/* IDL: SS_SET_CLOCK_PARENT() */ +sc_err_t ss_set_clock_parent(ss_ridx_t rsrc_idx, sc_pm_clk_t clk, + sc_pm_clk_parent_t new_parent); + +/*! + * This function gets the parent of a resource's clock. + * + * @param[in] rsrc_idx unified resource index + * @param[in] clk clock to affect + * @param[out] parent pointer to return parent of clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +/* IDL: SS_GET_CLOCK_PARENT() */ +sc_err_t ss_get_clock_parent(ss_ridx_t rsrc_idx, sc_pm_clk_t clk, + sc_pm_clk_parent_t *parent); + +/*! + * This function returns the functional state of a resource. + * + * @param[in] rsrc_idx unified resource index + * + * @return Returns a boolean (SC_TRUE if resource functional). + * + * This checks to see if the power and clocks for a resource + * (inc. required bus clocks) are enabled. + */ +/* IDL: SS_IS_RSRC_ACCESSIBLE() */ +sc_bool_t ss_is_rsrc_accessible(ss_ridx_t rsrc_idx); + +/*! + * This function triggers an interrupt on an MU. + * + * @param[in] rsrc_idx unified resource index of MU + * @param[in] mask MU interrupt to trigger + */ +/* IDL: SS_MU_IRQ() */ +void ss_mu_irq(ss_ridx_t rsrc_idx, uint32_t mask); + +/*! + * This function starts or stops a subsystem CPU. + * + * @param[in] rsrc_idx unified resource index of CPU + * @param[in] enable enable/disable flag (SC_TRUE = enable) + * @param[in] addr boot address for CPU + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: SS_CPU_START() */ +sc_err_t ss_cpu_start(ss_ridx_t rsrc_idx, sc_bool_t enable, sc_faddr_t addr); + +#ifdef XRDC_SUPPORT +/*! + * This function enables the subsystem hardware resource manager. + * + * @param[in] ss subsystem to affect + * @param[in] master master only + */ +/* IDL: SS_RDC_ENABLE() */ +void ss_rdc_enable(sc_sub_t ss, sc_bool_t master); + +/*! + * This function configures a subsystem master. + * + * @param[in] rsrc_idx unified resource index of master + * @param[in] valid valid flag (SC_TRUE = valid) + * @param[in] lock lock flag (SC_TRUE = lock) + * @param[in] sa security attribute + * @param[in] pa privilege attribute + * @param[in] did domain ID + * @param[in] sid StreamID + * @param[in] cid CPU ID + */ +/* IDL: SS_RDC_SET_MASTER() */ +void ss_rdc_set_master(ss_ridx_t rsrc_idx, sc_bool_t valid, sc_bool_t lock, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, + uint8_t cid); + +/*! + * This function configures a subsystem peripheral. + * + * @param[in] rsrc_idx unified resource index of peripheral + * @param[in] valid valid flag (SC_TRUE = valid) + * @param[in] lock lock flag (SC_TRUE = lock) + * @param[in] perms array of permisions + * @param[in] no_update if true, don't update if already valid + */ +/* IDL: SS_RDC_SET_PERIPHERAL() */ +void ss_rdc_set_peripheral(ss_ridx_t rsrc_idx, sc_bool_t valid, sc_bool_t lock, + const sc_rm_perm_t *perms, sc_bool_t no_update); + +/*! + * This function configures a memory region. + * + * @param[in] start 64-bit start address + * @param[in] end 64-bit end address + * @param[in] valid valid flag (SC_TRUE = valid) + * @param[in] perms array of permisions + * @param[in] det detour transaction to IEE + * @param[in] rmsg IEE config + * @param[in] new_start new 64-bit start address + * @param[in] new_end new 64-bit end address + */ +/* IDL: SS_RDC_SET_MEMORY() */ +sc_err_t ss_rdc_set_memory(sc_faddr_t start, sc_faddr_t end, sc_bool_t valid, + const sc_rm_perm_t *perms, sc_rm_det_t det, sc_rm_rmsg_t rmsg, + sc_faddr_t new_start, sc_faddr_t new_end); + +#endif /* XRDC_SUPPORT */ + +/*! + * This function sets a miscellaneous control value. + * + * @param[in] rsrc_idx unified resource index + * @param[in] ctrl control to write + * @param[in] val value to write + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: SS_SET_CONTROL() */ +sc_err_t ss_set_control(ss_ridx_t rsrc_idx, uint32_t ctrl, uint32_t val); + +/*! + * This function gets a miscellaneous control value. + * + * @param[in] rsrc_idx unified resource index + * @param[in] ctrl control to read + * @param[out] val pointer to return value + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: SS_GET_CONTROL() */ +sc_err_t ss_get_control(ss_ridx_t rsrc_idx, uint32_t ctrl, uint32_t *val); + +/*! + * This function enables/disables interrupts. + * + * @param[in] rsrc_idx unified resource index + * @param[in] group group the interrupts are in + * @param[in] mask mask of interrupts to affect + * @param[in] enable state to change interrupts to + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + */ +/* IDL: SS_IRQ_ENABLE() */ +sc_err_t ss_irq_enable(ss_ridx_t rsrc_idx, sc_irq_group_t group, + uint32_t mask, sc_bool_t enable); + +/*! + * This function returns the current interrupt status. Automatically + * clears pending interrupts. + * + * @param[in] rsrc_idx unified resource index + * @param[in] group groups the interrupts are in + * @param[in] status status of interrupts + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + */ +/* IDL: SS_IRQ_STATUS() */ +sc_err_t ss_irq_status(ss_ridx_t rsrc_idx, sc_irq_group_t group, + uint32_t *status); + +/*! + * This function triggers an interrupt. + * + * @param[in] group group the interrupt is in + * @param[in] irq interrupt to trigger + * @param[in] pt partition to trigger + * + * This function results in an interrupt being triggered on all SCFW MUs + * owned by the specified partition that have the interrupt enabled. Use + * SC_PT_ALL to trigger for all partitions. + * + * See the [RPC protocol section](@ref PROTOCOL) for more information. + */ +/* IDL: SS_IRQ_TRIGGER() */ +void ss_irq_trigger(sc_irq_group_t group, uint32_t irq, sc_rm_pt_t pt); + +/*! + * This function dumps the state of a subsystem. + */ +/* IDL: SS_DUMP() */ +void ss_dump(sc_sub_t ss, sc_bool_t xrdc, sc_bool_t dsc, sc_bool_t clk); + +/** @} */ + +/*! + * @name Helper Functions + * @{ + */ + +/*! + * This function runs manual memory repair on a subsystem. + * + * @param[in] ss subsystem to repair + * @param[in] pd power domain to repair + * @param[in] enable reset state of MTR HW + * + * This function does memory repair manually to work around HW issues. + */ +/* IDL: SS_DO_MEM_REPAIR() */ +void ss_do_mem_repair(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); + +/*! + * This function is used to configure SS features after a SS is + * fully powered up (SSI link enabled) or before powering down. + * + * @param[in] ss subsystem transitioning + * @param[in] up SC_TRUE if powered up, SC_FALSE if powering down + * + * This function is used to customize subsystem power transitions. + * It can be used to control the subsystem or wait for subsystem + * status before/after power mode transitions. + */ +/* IDL: SS_UPDOWN() */ +void ss_updown(sc_sub_t ss, sc_bool_t up); + +/*! + * This function is a pre- and post-amble for power domain power + * mode transitions. + * + * @param[in] ss subsystem transitioning + * @param[in] pd power domain transitioning + * @param[in] type type of notification + * @param[in] from_mode current power domain mode + * @param[in] to_mode new power domain mode + * @param[in] rom_boot SC_TRUE if ROM has powered up SS + * + * This function is used to customize subsystem power transitions. + * It can be used to control the subsystem or wait for subsystem + * status before/after power mode transitions. + */ +/* IDL: SS_PREPOST_POWER_MODE() */ +void ss_prepost_power_mode(sc_sub_t ss, dsc_pdom_t pd, + ss_prepost_t type, sc_pm_power_mode_t from_mode, + sc_pm_power_mode_t to_mode, sc_bool_t rom_boot); + +/*! + * This function enables/disables the isolation in a subsystem. + * + * @param[in] ss subsystem to affect + * @param[in] pd power domain to affect + * @param[in] enable flag indicating new state (SC_TRUE = enable) + */ +/* IDL: ss_iso_disable() */ +void ss_iso_disable(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); + +/*! + * This function enables/disables the interfaces in a subsystem. + * + * @param[in] ss subsystem to affect + * @param[in] pd power domain to affect + * @param[in] enable flag indicating new state (SC_TRUE = enable) + */ +/* IDL: ss_link_enable() */ +void ss_link_enable(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); + +/*! + * This function enables/disables a subsystems's SSI ports. + * + * @param[in] ss subsystem to affect + * @param[in] enable flag indicating new state (SC_TRUE = on) + */ +/* IDL: SS_SSI_POWER() */ +void ss_ssi_power(sc_sub_t ss, sc_bool_t enable); + +/*! + * This function enables/disables black hole mode of an SSI. + * + * @param[in] ss subsystem to affect + * @param[in] remote affect SSI to this subsystem + * @param[in] port affect this instance of the SSI + * @param[in] enable flag indicating new state (SC_TRUE = enable) + */ +/* IDL: SS_SSI_BHOLE_MODE() */ +void ss_ssi_bhole_mode(sc_sub_t ss, sc_sub_t remote, uint8_t port, + sc_bool_t enable); + +/*! + * This function enables/disables pause mode of an SSI. + * + * @param[in] ss subsystem to affect + * @param[in] remote affect SSI to this subsystem + * @param[in] port affect this instance of the SSI + * @param[in] enable flag indicating new state (SC_TRUE = enable) + */ +/* IDL: SS_SSI_PAUSE_MODE() */ +void ss_ssi_pause_mode(sc_sub_t ss, sc_sub_t remote, uint8_t port, + sc_bool_t enable); + +/*! + * This function waits for an SSI to become idle. + * + * @param[in] ss subsystem to affect + * @param[in] remote affect SSI to this subsystem + * @param[in] port affect this instance of the SSI + */ +/* IDL: SS_SSI_WAIT_IDLE() */ +void ss_ssi_wait_idle(sc_sub_t ss, sc_sub_t remote, uint8_t port); + +/*! + * This function setups an ADB interface between two ss. + * + * @param[in] ss local subsystem + * @param[in] remote remote subsystem + * @param[in] enable powerup/powerdown the ADB link + */ +/* IDL: SS_ADB_ENABLE() */ +void ss_adb_enable(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); + +/*! + * This function waits for the ADB to be powered up. + * + * @param[in] ss local subsystem + * @param[in] remote remote subsystem + * @param[in] enable powerup/powerdown the ADB link + */ +/* IDL: SS_ADB_WAIT() */ +void ss_adb_wait(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); + +/*! + * This function is a pre- and post-amble for clock mode transitions. + * + * @param[in] ss subsystem transitioning + * @param[in] clk clock transitioning + * @param[in] type type of notification + * @param[in] from_mode current clock mode + * @param[in] to_mode new clock mode + * + * This function is used to customize subsystem clock transitions. + * It can be used to control the subsystem or wait for subsystem + * status before/after clock transitions. + */ +/* IDL: SS_PREPOST_CLOCK_MODE() */ +void ss_prepost_clock_mode(sc_sub_t ss, ss_clock_t clk, ss_prepost_t type, + sc_pm_clk_mode_t from_mode, sc_pm_clk_mode_t to_mode); + +#ifdef XRDC_SUPPORT +/*! + * This function checks if a subsystem generates transactions matching + * domains. + * + * @param[in] ss subsystem to check + * @param[in] perms array of permisions + * + * @return Returns SC_TRUE if the subsystem has masters in domains which + * have access in \a perms. + */ +/* IDL: SS_RDC_IS_DID_VLD() */ +sc_bool_t ss_rdc_is_did_vld(sc_sub_t ss, const sc_rm_perm_t *perms); +#endif /* XRDC_SUPPORT */ + +/*! + * This function returns a system-wide resource from a subsystem + * and subsystem relative resource index. + * + * @param[in] ss subsystem containing resource + * @param[in] ss_idx subsystem index of resource + * + * @return Returns the system-wide resource. + */ +sc_rsrc_t ss_get_resource(sc_sub_t ss, ss_idx_t ss_idx); + +/*! + * This function determines if two memory regions overlap. + * + * @param[in] start1 start address for region 1 + * @param[in] end1 end address for region 1 + * @param[in] start2 start address for region 2 + * @param[in] end2 end address for region 2 + * + * @return Returns SC_TRUE if the memory regions overlap. + */ +sc_bool_t ss_overlap(sc_faddr_t start1, sc_faddr_t end1, sc_faddr_t start2, + sc_faddr_t end2); + +/*! + * This function gets temp sensor availability of a subsystem. + * + * @param[in] rsrc_idx any resource in the subsystem + * + * @return Returns SC_TRUE if the associated subsystem has a temp sensor. + */ +sc_bool_t ss_temp_sensor(ss_ridx_t rsrc_idx); + +/** @} */ + +/* Externs */ + +extern const sc_ss_ep_t sc_ss_ep[SC_SUBSYS_LAST + 1U]; +extern ss_base_data_t sc_ss_data[SC_SUBSYS_LAST + 1U]; + +#endif /* SC_SS_INF_H */ + +/** @} */ + diff --git a/platform/ss/inf/inf_ss.h b/platform/ss/inf/inf_ss.h new file mode 100644 index 0000000..4c69590 --- /dev/null +++ b/platform/ss/inf/inf_ss.h @@ -0,0 +1,276 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Subsystem side functions for interfacing with the subsystems. + * + * @addtogroup INF_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/inf_ss_h.pl */ + +#ifndef SC_SS_INF_SS_H +#define SC_SS_INF_SS_H + +/* Includes */ + +/* Defines */ + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO(X) \ + void ss_init_##X(sc_sub_t ss, sc_bool_t api_phase); \ + void ss_trans_power_mode_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + sc_err_t ss_rsrc_reset_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_rm_pt_t pt, sc_bool_t pre); \ + sc_err_t ss_set_cpu_power_mode_##X(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_power_mode_t mode, sc_pm_wake_src_t \ + wake_src); \ + sc_err_t ss_set_cpu_resume_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); \ + sc_err_t ss_req_sys_if_power_mode_##X(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, \ + sc_pm_power_mode_t lpm); \ + sc_err_t ss_set_clock_rate_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_get_clock_rate_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + sc_err_t ss_clock_enable_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); \ + sc_err_t ss_force_clock_enable_##X(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable); \ + sc_err_t ss_set_clock_parent_##X(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t \ + new_parent); \ + sc_err_t ss_get_clock_parent_##X(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); \ + sc_bool_t ss_is_rsrc_accessible_##X(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx); \ + void ss_mu_irq_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t rsrc_idx, \ + uint32_t mask); \ + sc_err_t ss_cpu_start_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); \ + void ss_rdc_enable_##X(sc_sub_t ss, sc_bool_t master); \ + void ss_rdc_set_master_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + void ss_rdc_set_peripheral_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, const sc_rm_perm_t \ + *perms, sc_bool_t no_update); \ + sc_err_t ss_rdc_set_memory_##X(sc_sub_t ss, sc_faddr_t start, \ + sc_faddr_t end, sc_bool_t valid, const sc_rm_perm_t *perms, \ + sc_rm_det_t det, sc_rm_rmsg_t rmsg, sc_faddr_t new_start, \ + sc_faddr_t new_end); \ + sc_err_t ss_set_control_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t val); \ + sc_err_t ss_get_control_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t *val); \ + sc_err_t ss_irq_enable_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t mask, sc_bool_t enable); \ + sc_err_t ss_irq_status_##X(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t *status); \ + void ss_irq_trigger_##X(sc_sub_t ss, sc_irq_group_t group, uint32_t \ + irq, sc_rm_pt_t pt); \ + void ss_dump_##X(sc_sub_t ss, sc_bool_t xrdc, sc_bool_t dsc, sc_bool_t \ + clk); \ + void ss_do_mem_repair_##X(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t \ + enable); \ + void ss_updown_##X(sc_sub_t ss, sc_bool_t up); \ + void ss_prepost_power_mode_##X(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + void ss_iso_disable_##X(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_link_enable_##X(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t enable); \ + void ss_ssi_power_##X(sc_sub_t ss, sc_bool_t enable); \ + void ss_ssi_bhole_mode_##X(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_pause_mode_##X(sc_sub_t ss, sc_sub_t remote, uint8_t port, \ + sc_bool_t enable); \ + void ss_ssi_wait_idle_##X(sc_sub_t ss, sc_sub_t remote, uint8_t port); \ + void ss_adb_enable_##X(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + void ss_adb_wait_##X(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); \ + void ss_prepost_clock_mode_##X(sc_sub_t ss, ss_clock_t clk, \ + ss_prepost_t type, sc_pm_clk_mode_t from_mode, sc_pm_clk_mode_t \ + to_mode); \ + sc_bool_t ss_rdc_is_did_vld_##X(sc_sub_t ss, const sc_rm_perm_t \ + *perms); \ + + +/*! Define used to make subsystem info external */ +#define SS_BASE_INFO_PROTO(X) extern const ss_base_info_t ss_base_info_##X; + +/* Types */ + +/*! + * @name Type defines for SS entry point pointers + */ +/** @{ */ +typedef void ss_init_t(sc_sub_t ss, sc_bool_t api_phase); +typedef void ss_trans_power_mode_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode); +typedef sc_err_t ss_rsrc_reset_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_rm_pt_t pt, sc_bool_t pre); +typedef sc_err_t ss_set_cpu_power_mode_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_power_mode_t mode, sc_pm_wake_src_t + wake_src); +typedef sc_err_t ss_set_cpu_resume_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); +typedef sc_err_t ss_req_sys_if_power_mode_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, + sc_pm_power_mode_t lpm); +typedef sc_err_t ss_set_clock_rate_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); +typedef sc_err_t ss_get_clock_rate_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); +typedef sc_err_t ss_clock_enable_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); +typedef sc_err_t ss_force_clock_enable_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_bool_t enable); +typedef sc_err_t ss_set_clock_parent_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t new_parent); +typedef sc_err_t ss_get_clock_parent_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); +typedef sc_bool_t ss_is_rsrc_accessible_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx); +typedef void ss_mu_irq_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t rsrc_idx, + uint32_t mask); +typedef sc_err_t ss_cpu_start_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); +typedef void ss_rdc_enable_t(sc_sub_t ss, sc_bool_t master); +typedef void ss_rdc_set_master_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, sc_rm_spa_t + pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); +typedef void ss_rdc_set_peripheral_t(sc_sub_t ss, ss_idx_t ss_idx, + ss_ridx_t rsrc_idx, sc_bool_t valid, sc_bool_t lock, const sc_rm_perm_t + *perms, sc_bool_t no_update); +typedef sc_err_t ss_rdc_set_memory_t(sc_sub_t ss, sc_faddr_t start, + sc_faddr_t end, sc_bool_t valid, const sc_rm_perm_t *perms, sc_rm_det_t + det, sc_rm_rmsg_t rmsg, sc_faddr_t new_start, sc_faddr_t new_end); +typedef sc_err_t ss_set_control_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, uint32_t ctrl, uint32_t val); +typedef sc_err_t ss_get_control_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, uint32_t ctrl, uint32_t *val); +typedef sc_err_t ss_irq_enable_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_irq_group_t group, uint32_t mask, sc_bool_t enable); +typedef sc_err_t ss_irq_status_t(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t + rsrc_idx, sc_irq_group_t group, uint32_t *status); +typedef void ss_irq_trigger_t(sc_sub_t ss, sc_irq_group_t group, uint32_t + irq, sc_rm_pt_t pt); +typedef void ss_dump_t(sc_sub_t ss, sc_bool_t xrdc, sc_bool_t dsc, + sc_bool_t clk); +typedef void ss_do_mem_repair_t(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t + enable); +typedef void ss_updown_t(sc_sub_t ss, sc_bool_t up); +typedef void ss_prepost_power_mode_t(sc_sub_t ss, dsc_pdom_t pd, + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t + to_mode, sc_bool_t rom_boot); +typedef void ss_iso_disable_t(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t + enable); +typedef void ss_link_enable_t(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t + enable); +typedef void ss_ssi_power_t(sc_sub_t ss, sc_bool_t enable); +typedef void ss_ssi_bhole_mode_t(sc_sub_t ss, sc_sub_t remote, uint8_t + port, sc_bool_t enable); +typedef void ss_ssi_pause_mode_t(sc_sub_t ss, sc_sub_t remote, uint8_t + port, sc_bool_t enable); +typedef void ss_ssi_wait_idle_t(sc_sub_t ss, sc_sub_t remote, uint8_t + port); +typedef void ss_adb_enable_t(sc_sub_t ss, sc_sub_t remote, sc_bool_t + enable); +typedef void ss_adb_wait_t(sc_sub_t ss, sc_sub_t remote, sc_bool_t enable); +typedef void ss_prepost_clock_mode_t(sc_sub_t ss, ss_clock_t clk, + ss_prepost_t type, sc_pm_clk_mode_t from_mode, sc_pm_clk_mode_t + to_mode); +typedef sc_bool_t ss_rdc_is_did_vld_t(sc_sub_t ss, const sc_rm_perm_t + *perms); +/** @} */ + +/*! + * This type is used to store static constant function pointers for a + * subsystem. An array for all subsytems is declared in inf.c called + * sc_ss_ep. From this array direct calls can be made to subsystems. + */ +typedef struct +{ + ss_init_t * const ep_ss_init; + ss_trans_power_mode_t * const ep_ss_trans_power_mode; + ss_rsrc_reset_t * const ep_ss_rsrc_reset; + ss_set_cpu_power_mode_t * const ep_ss_set_cpu_power_mode; + ss_set_cpu_resume_t * const ep_ss_set_cpu_resume; + ss_req_sys_if_power_mode_t * const ep_ss_req_sys_if_power_mode; + ss_set_clock_rate_t * const ep_ss_set_clock_rate; + ss_get_clock_rate_t * const ep_ss_get_clock_rate; + ss_clock_enable_t * const ep_ss_clock_enable; + ss_force_clock_enable_t * const ep_ss_force_clock_enable; + ss_set_clock_parent_t * const ep_ss_set_clock_parent; + ss_get_clock_parent_t * const ep_ss_get_clock_parent; + ss_is_rsrc_accessible_t * const ep_ss_is_rsrc_accessible; + ss_mu_irq_t * const ep_ss_mu_irq; + ss_cpu_start_t * const ep_ss_cpu_start; + ss_rdc_enable_t * const ep_ss_rdc_enable; + ss_rdc_set_master_t * const ep_ss_rdc_set_master; + ss_rdc_set_peripheral_t * const ep_ss_rdc_set_peripheral; + ss_rdc_set_memory_t * const ep_ss_rdc_set_memory; + ss_set_control_t * const ep_ss_set_control; + ss_get_control_t * const ep_ss_get_control; + ss_irq_enable_t * const ep_ss_irq_enable; + ss_irq_status_t * const ep_ss_irq_status; + ss_irq_trigger_t * const ep_ss_irq_trigger; + ss_dump_t * const ep_ss_dump; + ss_do_mem_repair_t * const ep_ss_do_mem_repair; + ss_updown_t * const ep_ss_updown; + ss_prepost_power_mode_t * const ep_ss_prepost_power_mode; + ss_iso_disable_t * const ep_ss_iso_disable; + ss_link_enable_t * const ep_ss_link_enable; + ss_ssi_power_t * const ep_ss_ssi_power; + ss_ssi_bhole_mode_t * const ep_ss_ssi_bhole_mode; + ss_ssi_pause_mode_t * const ep_ss_ssi_pause_mode; + ss_ssi_wait_idle_t * const ep_ss_ssi_wait_idle; + ss_adb_enable_t * const ep_ss_adb_enable; + ss_adb_wait_t * const ep_ss_adb_wait; + ss_prepost_clock_mode_t * const ep_ss_prepost_clock_mode; + ss_rdc_is_did_vld_t * const ep_ss_rdc_is_did_vld; +} sc_ss_ep_t; + +#endif /* SC_SS_INF_SS_H */ + +/** @} */ + diff --git a/platform/ss/inf/inf_ss_def.h b/platform/ss/inf/inf_ss_def.h new file mode 100755 index 0000000..c545258 --- /dev/null +++ b/platform/ss/inf/inf_ss_def.h @@ -0,0 +1,160 @@ +/* +** ################################################################### +** +** Copyright 2017-2019 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Default SS interface config. + * + * @addtogroup INF_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_INF_DEF_H +#define SC_SS_INF_DEF_H + +/* Defines */ + +/*! + * @name SS Configuration + */ +/** @{ */ +#ifndef SS_NUM_INST + #define SS_NUM_INST 1U +#endif +#ifndef SS_NUM_SRSRC + #define SS_NUM_SRSRC 0U +#endif +#ifndef SS_NUM_PRSRC + #define SS_NUM_PRSRC 0U + #define SS_NUM_PRSRC2 0U +#else +#ifndef SS_NUM_PRSRC2 + #define SS_NUM_PRSRC2 (SS_NUM_PRSRC) +#endif +#endif +#ifndef SS_NUM_RSRC_MAP + #define SS_NUM_RSRC_MAP (SS_NUM_RSRC * SS_NUM_INST) +#endif +#ifndef SS_NUM_PD + #define SS_NUM_PD 2U +#endif +#ifndef SS_PD_REBOOT_INFO + #define SS_PD_REBOOT_INFO NULL +#endif +#ifndef SS_LPCG_ADDR_INFO + #define SS_LPCG_ADDR_INFO NULL + #define SS_NUM_LPCG 0U +#endif +#ifndef SS_AON_RESET + #define SS_AON_RESET BIT(RST_DSCMIX) +#endif +#ifndef SS_PD_DSC + #define SS_PD_DSC 0U +#endif +#ifndef SS_PD_SSI + #define SS_PD_SSI 1U +#endif +#ifndef SS_NUM_SSI + #define SS_NUM_SSI 1U +#endif +#ifndef SS_IRQ_ENB + #define SS_IRQ_ENB 0U +#endif +#ifndef SS_MU_IRQ + #define SS_MU_IRQ SC_FALSE +#endif +#ifndef SS_AI_TYPE + #define SS_AI_TYPE AI_COMMON +#endif +#ifndef SS_PHY_ISO + #define SS_PHY_ISO 0U +#endif +#ifndef MTR_CLK_IDX + #define MTR_CLK_IDX 0U +#endif +#ifndef SS_DSCMIX + #define SS_DSCMIX SC_TRUE +#endif +/** @} */ + +/*! + * @name XRDC Configuration + */ +/** @{ */ +#ifndef SS_PD_MGR + #define SS_PD_MGR 0U +#endif +#ifndef SS_NUM_MDAC + #define SS_NUM_MDAC 0U +#endif +#ifndef SS_MDAC_MATCH + #define SS_MDAC_MATCH 0x00000000U +#endif +#ifndef SS_MDAC_CACHE + #define SS_MDAC_CACHE 0U +#endif +#ifndef SS_NUM_PAC + #define SS_NUM_PAC 0U +#endif +#ifndef SS_NUM_MSC + #define SS_NUM_MSC 0U +#endif +#ifndef SS_NUM_MRC + #define SS_NUM_MRC 0U +#endif +#ifndef SS_NUM_MRC_SLOTS + #define SS_NUM_MRC_SLOTS 0U +#endif +#ifndef SS_MRC_MASK + #define SS_MRC_MASK 0x000000000U +#endif +#ifndef SS_MRC_CACHE + #define SS_MRC_CACHE 0U +#endif +/** @} */ + +/* Define Checks */ + +#if (SS_NUM_CLK > SS_MAX_CLK) + #error "SS_NUM_CLK > SS_MAX_CLK" +#endif + +#endif /* SC_SS_INF_DEF_H */ + +/** @} */ + + diff --git a/platform/ss/lsio/v2/Makefile b/platform/ss/lsio/v2/Makefile new file mode 100755 index 0000000..b62b4f9 --- /dev/null +++ b/platform/ss/lsio/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/lsio/v2/ss.o + +CONFIGH += $(SRC)/ss/lsio/v2/config.h $(SRC)/ss/lsio/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/lsio/v2/resource.txt + +CLK_MD += $(SRC)/ss/lsio/v2/clock.txt + +CTRL_MD += $(SRC)/ss/lsio/v2/control.txt + +DIRS += $(OUT)/ss/lsio/v2 + diff --git a/platform/ss/lsio/v2/config.h b/platform/ss/lsio/v2/config.h new file mode 100644 index 0000000..d0a49ce --- /dev/null +++ b/platform/ss/lsio/v2/config.h @@ -0,0 +1,190 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the LSIO subsystem. + * + * @addtogroup LSIO_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_LSIO_CONFIG_H +#define SC_SS_LSIO_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_LSIO 57U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_LSIO \ + void ss_init_lsio(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_rsrc_reset_lsio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_rm_pt_t pt, sc_bool_t pre); \ + void ss_mu_irq_lsio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t rsrc_idx, \ + uint32_t mask); \ + sc_err_t ss_irq_enable_lsio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t mask, sc_bool_t enable); \ + sc_err_t ss_irq_status_lsio(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t *status); \ + void ss_irq_trigger_lsio(sc_sub_t ss, sc_irq_group_t group, uint32_t \ + irq, sc_rm_pt_t pt); \ + void ss_prepost_power_mode_lsio(sc_sub_t ss, dsc_pdom_t pd, \ + ss_prepost_t type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode, sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_LSIO \ + { \ + ss_init_lsio, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_lsio, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_lsio, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_lsio, \ + ss_irq_status_lsio, \ + ss_irq_trigger_lsio, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_lsio, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_LSIO_0 \ + "PWM_0", \ + "PWM_1", \ + "PWM_2", \ + "PWM_3", \ + "PWM_4", \ + "PWM_5", \ + "PWM_6", \ + "PWM_7", \ + "GPIO_0", \ + "GPIO_1", \ + "GPIO_2", \ + "GPIO_3", \ + "GPIO_4", \ + "GPIO_5", \ + "GPIO_6", \ + "GPIO_7", \ + "FSPI_0", \ + "FSPI_1", \ + "GPT_0", \ + "GPT_1", \ + "GPT_2", \ + "GPT_3", \ + "GPT_4", \ + "KPP", \ + "MU_0A", \ + "MU_1A", \ + "MU_2A", \ + "MU_3A", \ + "MU_4A", \ + "MU_5A", \ + "MU_6A", \ + "MU_7A", \ + "MU_8A", \ + "MU_9A", \ + "MU_10A", \ + "MU_11A", \ + "MU_12A", \ + "MU_13A", \ + "MU_5B", \ + "MU_6B", \ + "MU_7B", \ + "MU_8B", \ + "MU_9B", \ + "MU_10B", \ + "MU_11B", \ + "MU_12B", \ + "MU_13B", \ + "IEE", \ + "IEE_R0", \ + "IEE_R1", \ + "IEE_R2", \ + "IEE_R3", \ + "IEE_R4", \ + "IEE_R5", \ + "IEE_R6", \ + "IEE_R7", \ + "OCRAM", \ + +#endif + +#endif /* SC_SS_LSIO_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/lsio/v2/dsc.h b/platform/ss/lsio/v2/dsc.h new file mode 100755 index 0000000..ea79dc1 --- /dev/null +++ b/platform/ss/lsio/v2/dsc.h @@ -0,0 +1,346 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup LSIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_LSIO_DSC_H +#define SC_SS_LSIO_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SWAP REGBIT(0, 14) +#define GPR_SWAP_MASK REGBIT(0, 23) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO0 REGBIT64(1, 0) +#define IRQ_GPIO1 REGBIT64(1, 1) +#define IRQ_GPIO2 REGBIT64(1, 2) +#define IRQ_GPIO3 REGBIT64(1, 3) +#define IRQ_GPIO4 REGBIT64(1, 4) +#define IRQ_GPIO5 REGBIT64(1, 5) +#define IRQ_GPIO6 REGBIT64(1, 6) +#define IRQ_GPIO7 REGBIT64(1, 7) +#define IRQ_GPT0 REGBIT64(1, 8) +#define IRQ_GPT1 REGBIT64(1, 9) +#define IRQ_GPT2 REGBIT64(1, 10) +#define IRQ_GPT3 REGBIT64(1, 11) +#define IRQ_GPT4 REGBIT64(1, 12) +#define IRQ_KPP REGBIT64(1, 13) +#define IRQ_PWM0 REGBIT64(1, 14) +#define IRQ_PWM1 REGBIT64(1, 15) +#define IRQ_PWM2 REGBIT64(1, 16) +#define IRQ_PWM3 REGBIT64(1, 17) +#define IRQ_PWM4 REGBIT64(1, 18) +#define IRQ_PWM5 REGBIT64(1, 19) +#define IRQ_PWM6 REGBIT64(1, 20) +#define IRQ_PWM7 REGBIT64(1, 21) +#define IRQ_MU_SIDEB REGBIT64(1, 27) +/** @} */ + +/*! + * @name CSR 0x00 Bit Definitions + */ +/** @{ */ +#define CSR_GPT0_IPG_STOP REGBIT(0x0, 0) +#define CSR_GPT1_IPG_STOP REGBIT(0x0, 1) +#define CSR_GPT2_IPG_STOP REGBIT(0x0, 2) +#define CSR_GPT3_IPG_STOP REGBIT(0x0, 3) +#define CSR_GPT4_IPG_STOP REGBIT(0x0, 4) +#define CSR_PWM0_IPG_STOP REGBIT(0x0, 5) +#define CSR_PWM1_IPG_STOP REGBIT(0x0, 6) +#define CSR_PWM2_IPG_STOP REGBIT(0x0, 7) +#define CSR_PWM3_IPG_STOP REGBIT(0x0, 8) +#define CSR_PWM4_IPG_STOP REGBIT(0x0, 9) +#define CSR_PWM5_IPG_STOP REGBIT(0x0, 10) +#define CSR_PWM6_IPG_STOP REGBIT(0x0, 11) +#define CSR_PWM7_IPG_STOP REGBIT(0x0, 12) +/** @} */ + + +/*! + * @name CSR 0x10 Bit Definitions + */ +/** @{ */ +#define CSR_FSPI0_IPG_STOP REGBIT(0x1, 0) +#define CSR_FSPI1_IPG_STOP REGBIT(0x1, 1) +#define CSR_MU5A_IPG_STOP REGBIT(0x1, 2) +#define CSR_MU6A_IPG_STOP REGBIT(0x1, 3) +#define CSR_MU7A_IPG_STOP REGBIT(0x1, 4) +#define CSR_MU8A_IPG_STOP REGBIT(0x1, 5) +#define CSR_MU9A_IPG_STOP REGBIT(0x1, 6) +#define CSR_MU10A_IPG_STOP REGBIT(0x1, 7) +#define CSR_MU11A_IPG_STOP REGBIT(0x1, 8) +#define CSR_MU12A_IPG_STOP REGBIT(0x1, 9) +#define CSR_MU13A_IPG_STOP REGBIT(0x1, 10) +#define CSR_MU5B_IPG_STOP REGBIT(0x1, 11) +#define CSR_MU6B_IPG_STOP REGBIT(0x1, 12) +#define CSR_MU7B_IPG_STOP REGBIT(0x1, 13) +#define CSR_MU8B_IPG_STOP REGBIT(0x1, 14) +#define CSR_MU9B_IPG_STOP REGBIT(0x1, 15) +#define CSR_MU10B_IPG_STOP REGBIT(0x1, 16) +#define CSR_MU11B_IPG_STOP REGBIT(0x1, 17) +#define CSR_MU12B_IPG_STOP REGBIT(0x1, 18) +#define CSR_MU13B_IPG_STOP REGBIT(0x1, 19) +/** @} */ + +/*! + * @name CSR 0x20 Bit Definitions + */ +/** @{ */ +#define CSR_GPT0_IPG_WAIT REGBIT(0x2, 0) +#define CSR_GPT1_IPG_WAIT REGBIT(0x2, 1) +#define CSR_GPT2_IPG_WAIT REGBIT(0x2, 2) +#define CSR_GPT3_IPG_WAIT REGBIT(0x2, 3) +#define CSR_GPT4_IPG_WAIT REGBIT(0x2, 4) +#define CSR_PWM0_IPG_WAIT REGBIT(0x2, 5) +#define CSR_PWM1_IPG_WAIT REGBIT(0x2, 6) +#define CSR_PWM2_IPG_WAIT REGBIT(0x2, 7) +#define CSR_PWM3_IPG_WAIT REGBIT(0x2, 8) +#define CSR_PWM4_IPG_WAIT REGBIT(0x2, 9) +#define CSR_PWM5_IPG_WAIT REGBIT(0x2, 10) +#define CSR_PWM6_IPG_WAIT REGBIT(0x2, 11) +#define CSR_PWM7_IPG_WAIT REGBIT(0x2, 12) +/** @} */ + +/*! + * @name CSR 0x30 Bit Definitions + */ +/** @{ */ +#define CSR_MU5A_IPG_WAIT REGBIT(0x3, 2) +#define CSR_MU6A_IPG_WAIT REGBIT(0x3, 3) +#define CSR_MU7A_IPG_WAIT REGBIT(0x3, 4) +#define CSR_MU8A_IPG_WAIT REGBIT(0x3, 5) +#define CSR_MU9A_IPG_WAIT REGBIT(0x3, 6) +#define CSR_MU10A_IPG_WAIT REGBIT(0x3, 7) +#define CSR_MU11A_IPG_WAIT REGBIT(0x3, 8) +#define CSR_MU12A_IPG_WAIT REGBIT(0x3, 9) +#define CSR_MU13A_IPG_WAIT REGBIT(0x3, 10) +#define CSR_MU5B_IPG_WAIT REGBIT(0x3, 11) +#define CSR_MU6B_IPG_WAIT REGBIT(0x3, 12) +#define CSR_MU7B_IPG_WAIT REGBIT(0x3, 13) +#define CSR_MU8B_IPG_WAIT REGBIT(0x3, 14) +#define CSR_MU9B_IPG_WAIT REGBIT(0x3, 15) +#define CSR_MU10B_IPG_WAIT REGBIT(0x3, 16) +#define CSR_MU11B_IPG_WAIT REGBIT(0x3, 17) +#define CSR_MU12B_IPG_WAIT REGBIT(0x3, 18) +#define CSR_MU13B_IPG_WAIT REGBIT(0x3, 19) +/** @} */ + +/*! + * @name CSR 0x40 Bit Definitions + */ +/** @{ */ +#define CSR_GPT0_IPG_DOZE REGBIT(0x4, 0) +#define CSR_GPT1_IPG_DOZE REGBIT(0x4, 1) +#define CSR_GPT2_IPG_DOZE REGBIT(0x4, 2) +#define CSR_GPT3_IPG_DOZE REGBIT(0x4, 3) +#define CSR_GPT4_IPG_DOZE REGBIT(0x4, 4) +#define CSR_PWM0_IPG_DOZE REGBIT(0x4, 5) +#define CSR_PWM1_IPG_DOZE REGBIT(0x4, 6) +#define CSR_PWM2_IPG_DOZE REGBIT(0x4, 7) +#define CSR_PWM3_IPG_DOZE REGBIT(0x4, 8) +#define CSR_PWM4_IPG_DOZE REGBIT(0x4, 9) +#define CSR_PWM5_IPG_DOZE REGBIT(0x4, 10) +#define CSR_PWM6_IPG_DOZE REGBIT(0x4, 11) +#define CSR_PWM7_IPG_DOZE REGBIT(0x4, 12) +/** @} */ + +/*! + * @name CSR 0x50 Bit Definitions + */ +/** @{ */ +#define CSR_FSPI0_IPG_DOZE REGBIT(0x5, 0) +#define CSR_FSPI1_IPG_DOZE REGBIT(0x5, 1) +/** @} */ + +/*! + * @name CSR 0x70 Definitions + */ +/** @{ */ +#define CSR_MU5A_IPG_DSM REGBIT(0x7, 2) +#define CSR_MU6A_IPG_DSM REGBIT(0x7, 3) +#define CSR_MU7A_IPG_DSM REGBIT(0x7, 4) +#define CSR_MU8A_IPG_DSM REGBIT(0x7, 5) +#define CSR_MU9A_IPG_DSM REGBIT(0x7, 6) +#define CSR_MU10A_IPG_DSM REGBIT(0x7, 7) +#define CSR_MU11A_IPG_DSM REGBIT(0x7, 8) +#define CSR_MU12A_IPG_DSM REGBIT(0x7, 9) +#define CSR_MU13A_IPG_DSM REGBIT(0x7, 10) +#define CSR_MU5B_IPG_DSM REGBIT(0x7, 11) +#define CSR_MU6B_IPG_DSM REGBIT(0x7, 12) +#define CSR_MU7B_IPG_DSM REGBIT(0x7, 13) +#define CSR_MU8B_IPG_DSM REGBIT(0x7, 14) +#define CSR_MU9B_IPG_DSM REGBIT(0x7, 15) +#define CSR_MU10B_IPG_DSM REGBIT(0x7, 16) +#define CSR_MU11B_IPG_DSM REGBIT(0x7, 17) +#define CSR_MU12B_IPG_DSM REGBIT(0x7, 18) +#define CSR_MU13B_IPG_DSM REGBIT(0x7, 19) +/** @} */ + +/*! + * @name CSR 0x80 Bit Definitions + */ +/** @{ */ +#define CSR_GPT0_IPG_DEBUG REGBIT(0x8, 0) +#define CSR_GPT1_IPG_DEBUG REGBIT(0x8, 1) +#define CSR_GPT2_IPG_DEBUG REGBIT(0x8, 2) +#define CSR_GPT3_IPG_DEBUG REGBIT(0x8, 3) +#define CSR_GPT4_IPG_DEBUG REGBIT(0x8, 4) +#define CSR_PWM0_IPG_DEBUG REGBIT(0x8, 5) +#define CSR_PWM1_IPG_DEBUG REGBIT(0x8, 6) +#define CSR_PWM2_IPG_DEBUG REGBIT(0x8, 7) +#define CSR_PWM3_IPG_DEBUG REGBIT(0x8, 8) +#define CSR_PWM4_IPG_DEBUG REGBIT(0x8, 9) +#define CSR_PWM5_IPG_DEBUG REGBIT(0x8, 10) +#define CSR_PWM6_IPG_DEBUG REGBIT(0x8, 11) +#define CSR_PWM7_IPG_DEBUG REGBIT(0x8, 12) +/** @} */ + +/*! + * @name CSR 0xB0 Bit Definitions + */ +/** @{ */ +#define CSR_FSPI0_IPG_STOP_ACK REGBIT(0xB, 0) +#define CSR_FSPI1_IPG_STOP_ACK REGBIT(0xB, 1) +/** @} */ + +/*! + * @name CSR 0xC0 Bit Definitions + */ +/** @{ */ +#define CSR_GPT0_32K_SYNC REGBIT(0xC, 0) +#define CSR_GPT1_32K_SYNC REGBIT(0xC, 1) +#define CSR_GPT2_32K_SYNC REGBIT(0xC, 2) +#define CSR_GPT3_32K_SYNC REGBIT(0xC, 3) +#define CSR_GPT4_32K_SYNC REGBIT(0xC, 4) +#define CSR_PWM0_32K_SYNC REGBIT(0xC, 5) +#define CSR_PWM1_32K_SYNC REGBIT(0xC, 6) +#define CSR_PWM2_32K_SYNC REGBIT(0xC, 7) +#define CSR_PWM3_32K_SYNC REGBIT(0xC, 8) +#define CSR_PWM4_32K_SYNC REGBIT(0xC, 9) +#define CSR_PWM5_32K_SYNC REGBIT(0xC, 10) +#define CSR_PWM6_32K_SYNC REGBIT(0xC, 11) +#define CSR_PWM7_32K_SYNC REGBIT(0xC, 12) +/** @} */ + +/*! + * @name CSR 0xD0 Bit Definitions + */ +/** @{ */ +#define CSR_OCRAM_RD_ADDR_PIPE REGBIT(0xD, 0) +#define CSR_OCRAM_RD_DATA_WAIT REGBIT(0xD, 1) +#define CSR_OCRAM_WR_ADDR_PIPE REGBIT(0xD, 2) +#define CSR_OCRAM_WR_DATA_PIPE REGBIT(0xD, 3) +/** @} */ + +/*! + * @name CSR 0xE0 Bit Definitions + */ +/** @{ */ +#define CSR_OCRAM_RD_ADDR_PIPE_PEND REGBIT(0xE, 0) +#define CSR_OCRAM_RD_DATA_WAIT_PEND REGBIT(0xE, 1) +#define CSR_OCRAM_WR_ADDR_PIPE_PEND REGBIT(0xE, 2) +#define CSR_OCRAM_WR_DATA_PIPE_PEND REGBIT(0xE, 3) +/** @} */ + +#if (defined(FSL_FEATURE_DSC_HAS_PER_RESET) && FSL_FEATURE_DSC_HAS_PER_RESET) +/*! + * @name ECSR 0x00 Reset Bit Definitions + */ +/** @{ */ +#define CSR_PWM0_RESET REGBIT8(0x0, 0) +#define CSR_PWM1_RESET REGBIT8(0x0, 1) +#define CSR_PWM2_RESET REGBIT8(0x0, 2) +#define CSR_PWM3_RESET REGBIT8(0x0, 3) +#define CSR_PWM4_RESET REGBIT8(0x0, 4) +#define CSR_PWM5_RESET REGBIT8(0x0, 5) +#define CSR_PWM6_RESET REGBIT8(0x0, 6) +#define CSR_PWM7_RESET REGBIT8(0x0, 7) +#define CSR_GPIO0_RESET REGBIT8(0x0, 8) +#define CSR_GPIO1_RESET REGBIT8(0x0, 9) +#define CSR_GPIO2_RESET REGBIT8(0x0, 10) +#define CSR_GPIO3_RESET REGBIT8(0x0, 11) +#define CSR_GPIO4_RESET REGBIT8(0x0, 12) +#define CSR_GPIO5_RESET REGBIT8(0x0, 13) +#define CSR_GPIO6_RESET REGBIT8(0x0, 14) +#define CSR_GPIO7_RESET REGBIT8(0x0, 15) +#define CSR_GPT0_RESET REGBIT8(0x0, 16) +#define CSR_GPT1_RESET REGBIT8(0x0, 17) +#define CSR_GPT2_RESET REGBIT8(0x0, 18) +#define CSR_GPT3_RESET REGBIT8(0x0, 19) +#define CSR_GPT4_RESET REGBIT8(0x0, 20) +/** @} */ + +/*! + * @name ECSR 0x01 Reset Bit Definitions + */ +/** @{ */ +#define CSR_MU5_RESET REGBIT8(0x1, 0) +#define CSR_MU6_RESET REGBIT8(0x1, 1) +#define CSR_MU7_RESET REGBIT8(0x1, 2) +#define CSR_MU8_RESET REGBIT8(0x1, 3) +#define CSR_MU9_RESET REGBIT8(0x1, 4) +#define CSR_MU10_RESET REGBIT8(0x1, 5) +#define CSR_MU11_RESET REGBIT8(0x1, 6) +#define CSR_MU12_RESET REGBIT8(0x1, 7) +#define CSR_MU13_RESET REGBIT8(0x1, 8) +#define CSR_FSPI0_RESET REGBIT8(0x1, 9) +#define CSR_IEE_RESET REGBIT8(0x1, 10) +/** @} */ +#endif + +#endif /* SC_SS_LSIO_DSC_H */ + +/** @} */ + diff --git a/platform/ss/lsio/v2/rsrc.h b/platform/ss/lsio/v2/rsrc.h new file mode 100644 index 0000000..a2851a9 --- /dev/null +++ b/platform/ss/lsio/v2/rsrc.h @@ -0,0 +1,118 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the LSIO subsystem. + * + * @addtogroup LSIO_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_LSIO_RSRC_H +#define SC_SS_LSIO_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_PWM_0 0U +#define SS_R_PWM_1 1U +#define SS_R_PWM_2 2U +#define SS_R_PWM_3 3U +#define SS_R_PWM_4 4U +#define SS_R_PWM_5 5U +#define SS_R_PWM_6 6U +#define SS_R_PWM_7 7U +#define SS_R_GPIO_0 8U +#define SS_R_GPIO_1 9U +#define SS_R_GPIO_2 10U +#define SS_R_GPIO_3 11U +#define SS_R_GPIO_4 12U +#define SS_R_GPIO_5 13U +#define SS_R_GPIO_6 14U +#define SS_R_GPIO_7 15U +#define SS_R_FSPI_0 16U +#define SS_R_FSPI_1 17U +#define SS_R_GPT_0 18U +#define SS_R_GPT_1 19U +#define SS_R_GPT_2 20U +#define SS_R_GPT_3 21U +#define SS_R_GPT_4 22U +#define SS_R_KPP 23U +#define SS_R_MU_0A 24U +#define SS_R_MU_1A 25U +#define SS_R_MU_2A 26U +#define SS_R_MU_3A 27U +#define SS_R_MU_4A 28U +#define SS_R_MU_5A 29U +#define SS_R_MU_6A 30U +#define SS_R_MU_7A 31U +#define SS_R_MU_8A 32U +#define SS_R_MU_9A 33U +#define SS_R_MU_10A 34U +#define SS_R_MU_11A 35U +#define SS_R_MU_12A 36U +#define SS_R_MU_13A 37U +#define SS_R_MU_5B 38U +#define SS_R_MU_6B 39U +#define SS_R_MU_7B 40U +#define SS_R_MU_8B 41U +#define SS_R_MU_9B 42U +#define SS_R_MU_10B 43U +#define SS_R_MU_11B 44U +#define SS_R_MU_12B 45U +#define SS_R_MU_13B 46U +#define SS_R_IEE 47U +#define SS_R_IEE_R0 48U +#define SS_R_IEE_R1 49U +#define SS_R_IEE_R2 50U +#define SS_R_IEE_R3 51U +#define SS_R_IEE_R4 52U +#define SS_R_IEE_R5 53U +#define SS_R_IEE_R6 54U +#define SS_R_IEE_R7 55U +#define SS_R_OCRAM 56U +/** @} */ + +#endif /* SC_SS_LSIO_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/lsio/v2/ss.h b/platform/ss/lsio/v2/ss.h new file mode 100755 index 0000000..3976742 --- /dev/null +++ b/platform/ss/lsio/v2/ss.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the LSIO subsystem API. + * + * @addtogroup LSIO_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_LSIO_SS_H +#define SC_SS_LSIO_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(lsio) + +/* Functions */ + +SS_FUNC_PROTO_LSIO + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_lsio[]; + +#endif /* SC_SS_LSIO_SS_H */ + +/** @} */ + diff --git a/platform/ss/lvds/v1/Makefile b/platform/ss/lvds/v1/Makefile new file mode 100755 index 0000000..6e82aea --- /dev/null +++ b/platform/ss/lvds/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/lvds/v1/ss.o + +CONFIGH += $(SRC)/ss/lvds/v1/config.h $(SRC)/ss/lvds/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/lvds/v1/resource.txt + +CLK_MD += $(SRC)/ss/lvds/v1/clock.txt + +CTRL_MD += $(SRC)/ss/lvds/v1/control.txt + +DIRS += $(OUT)/ss/lvds/v1 + diff --git a/platform/ss/lvds/v1/config.h b/platform/ss/lvds/v1/config.h new file mode 100644 index 0000000..08b20f3 --- /dev/null +++ b/platform/ss/lvds/v1/config.h @@ -0,0 +1,133 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the LVDS subsystem. + * + * @addtogroup LVDS_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_LVDS_CONFIG_H +#define SC_SS_LVDS_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_LVDS 3U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_LVDS \ + void ss_trans_power_mode_lvds(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_LVDS \ + { \ + ss_init_base, \ + ss_trans_power_mode_lvds, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_LVDS_0 \ + "LVDS_0", \ + "LVDS_0_PWM_0", \ + "LVDS_0_I2C_0", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_LVDS_1 \ + "LVDS_1", \ + "LVDS_1_PWM_0", \ + "LVDS_1_I2C_0", \ + +#endif + +#endif /* SC_SS_LVDS_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/lvds/v1/dsc.h b/platform/ss/lvds/v1/dsc.h new file mode 100755 index 0000000..265c266 --- /dev/null +++ b/platform/ss/lvds/v1/dsc.h @@ -0,0 +1,98 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup LVDS_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_LVDS_DSC_H +#define SC_SS_LVDS_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 10) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 11) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 12) +#define GPR_PWM0_IPG_STOP REGBIT(0, 13) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 14) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 15) +#define GPR_I2C0_IPG_STOP REGBIT(0, 16) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 17) +#define GPR_I2C1_IPG_DEBUG REGBIT(0, 18) +#define GPR_I2C1_IPG_DOZE REGBIT(0, 19) +#define GPR_I2C1_IPG_STOP REGBIT(0, 20) +#define GPR_I2C1_IPG_STOP_MODE REGBIT(0, 21) +#define GPR_PXL_LINK_RATE_CORRECT REGBIT(0, 22) +#define GPR_CKIL_SYNC_REQ REGBIT(0, 23) +#define GPR_PHY_ISO REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 4) +#define GPS_I2C1_STOP_ACK REGBIT(0, 5) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO0 REGBIT64(1, 0) +#define IRQ_GPIO1 REGBIT64(1, 1) +#define IRQ_GPIO2 REGBIT64(1, 2) +#define IRQ_GPIO3 REGBIT64(1, 3) +#define IRQ_LPI2C0_HREQ REGBIT64(1, 4) +#define IRQ_LPI2C1_HREQ REGBIT64(1, 5) +#define IRQ_WAKE_CTI REGBIT64(1, 6) +/** @} */ + +#endif /* SC_SS_LVDS_DSC_H */ + +/** @} */ diff --git a/platform/ss/lvds/v1/rsrc.h b/platform/ss/lvds/v1/rsrc.h new file mode 100644 index 0000000..a725716 --- /dev/null +++ b/platform/ss/lvds/v1/rsrc.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the LVDS subsystem. + * + * @addtogroup LVDS_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_LVDS_RSRC_H +#define SC_SS_LVDS_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_LVDS_0 0U +#define SS_R_LVDS_0_PWM_0 1U +#define SS_R_LVDS_0_I2C_0 2U +#define SS_R_LVDS_1 0U +#define SS_R_LVDS_1_PWM_0 1U +#define SS_R_LVDS_1_I2C_0 2U +/** @} */ + +#endif /* SC_SS_LVDS_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/lvds/v1/ss.h b/platform/ss/lvds/v1/ss.h new file mode 100755 index 0000000..805563a --- /dev/null +++ b/platform/ss/lvds/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the LVDS subsystem API. + * + * @addtogroup LVDS_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_LVDS_SS_H +#define SC_SS_LVDS_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(lvds) + +/* Functions */ + +SS_FUNC_PROTO_LVDS + +#endif /* SC_SS_LVDS_SS_H */ + +/** @} */ + diff --git a/platform/ss/m4/v1/Makefile b/platform/ss/m4/v1/Makefile new file mode 100755 index 0000000..48a551d --- /dev/null +++ b/platform/ss/m4/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/m4/v1/ss.o + +CONFIGH += $(SRC)/ss/m4/v1/config.h $(SRC)/ss/m4/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/m4/v1/resource.txt + +CLK_MD += $(SRC)/ss/m4/v1/clock.txt + +CTRL_MD += $(SRC)/ss/m4/v1/control.txt + +DIRS += $(OUT)/ss/m4/v1 + diff --git a/platform/ss/m4/v1/config.h b/platform/ss/m4/v1/config.h new file mode 100644 index 0000000..4ae7233 --- /dev/null +++ b/platform/ss/m4/v1/config.h @@ -0,0 +1,186 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the M4 subsystem. + * + * @addtogroup M4_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_M4_CONFIG_H +#define SC_SS_M4_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_M4 18U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_M4 \ + void ss_init_m4(sc_sub_t ss, sc_bool_t api_phase); \ + sc_err_t ss_rsrc_reset_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_rm_pt_t pt, sc_bool_t pre); \ + sc_err_t ss_set_cpu_resume_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t isPrimary, sc_faddr_t addr); \ + sc_err_t ss_req_sys_if_power_mode_m4(sc_sub_t ss, ss_idx_t ss_idx, \ + ss_ridx_t rsrc_idx, sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, \ + sc_pm_power_mode_t lpm); \ + sc_err_t ss_set_clock_rate_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); \ + void ss_mu_irq_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t rsrc_idx, \ + uint32_t mask); \ + sc_err_t ss_cpu_start_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); \ + void ss_rdc_set_master_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + sc_err_t ss_irq_enable_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t mask, sc_bool_t enable); \ + sc_err_t ss_irq_status_m4(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_irq_group_t group, uint32_t *status); \ + void ss_irq_trigger_m4(sc_sub_t ss, sc_irq_group_t group, uint32_t irq, \ + sc_rm_pt_t pt); \ + void ss_prepost_power_mode_m4(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_M4 \ + { \ + ss_init_m4, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_m4, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_m4, \ + ss_req_sys_if_power_mode_m4, \ + ss_set_clock_rate_m4, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_m4, \ + ss_cpu_start_m4, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_m4, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_m4, \ + ss_irq_status_m4, \ + ss_irq_trigger_m4, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_m4, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_M4_0 \ + "M4_0_PID0", \ + "M4_0_PID1", \ + "M4_0_PID2", \ + "M4_0_PID3", \ + "M4_0_PID4", \ + "M4_0_RGPIO", \ + "M4_0_SEMA42", \ + "M4_0_TPM", \ + "M4_0_PIT", \ + "M4_0_UART", \ + "M4_0_I2C", \ + "M4_0_INTMUX", \ + "M4_0_MU_0B", \ + "M4_0_MU_0A0", \ + "M4_0_MU_0A1", \ + "M4_0_MU_0A2", \ + "M4_0_MU_0A3", \ + "M4_0_MU_1A", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_M4_1 \ + "M4_1_PID0", \ + "M4_1_PID1", \ + "M4_1_PID2", \ + "M4_1_PID3", \ + "M4_1_PID4", \ + "M4_1_RGPIO", \ + "M4_1_SEMA42", \ + "M4_1_TPM", \ + "M4_1_PIT", \ + "M4_1_UART", \ + "M4_1_I2C", \ + "M4_1_INTMUX", \ + "M4_1_MU_0B", \ + "M4_1_MU_0A0", \ + "M4_1_MU_0A1", \ + "M4_1_MU_0A2", \ + "M4_1_MU_0A3", \ + "M4_1_MU_1A", \ + +#endif + +#endif /* SC_SS_M4_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/m4/v1/dsc.h b/platform/ss/m4/v1/dsc.h new file mode 100755 index 0000000..18aa5f9 --- /dev/null +++ b/platform/ss/m4/v1/dsc.h @@ -0,0 +1,133 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup M4_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_M4_DSC_H +#define SC_SS_M4_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_SS_POR REGBIT(0, 2) +#define RST_CORE REGBIT(0, 3) +#define RST_DEBUG REGBIT(0, 4) +/** @} */ + +/*! + * @name SS GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_CM4_HCLK_MUX_SEL REGBIT(0, 8) +#define GPR_CM4_HCLK_MUX_IN0 REGBIT(0, 9) +#define GPR_CM4_AXBS_STALL_REQUEST REGBIT(0, 10) +#define GPR_CM4_REF_CLK_GATE REGBIT(0, 11) +#define GPR_CM4_DBG_REQ REGBIT(0, 12) +#define GPR_CM4_TX_EVENT_ENB REGBIT(0, 13) +#define GPR_CM4_HCLK_ENB REGBIT(0, 14) +#define GPR_SIM_BBS_LP_RUN_ACK_3V REGBIT(0, 24) +#define GPR_SIM_BBS_HS_RUN_ACK_3V REGBIT(0, 25) +#define GPR_SIM_SYS_RST_SRSL_WDOG REGBIT(0, 26) +#define GPR_SIM_SYS_RST_SRSH_LOCKUP REGBIT(0, 27) +#define GPR_SIM_SYS_RST_SRSH_SW REGBIT(0, 28) +#define GPR_SIM_SYS_RST_SRSH_UECC REGBIT(0, 29) +#define GPR_SIM_RCM_VLLS_DETECT REGBIT(0, 30) +#define GPR_SLEEP_HOLD_REQ REGBIT(0, 31) +/** @} */ + +/*! + * @name SS GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_DBGPWRUPREQ REGBIT(1, 45) +#define GPR_SYSPWRUPREQ REGBIT(1, 46) +#define GPR_LPI2C1_IPG_STOP REGBIT(1, 50) +#define GPR_LPI2C1_IPG_STOP_MODE REGBIT(1, 51) +#define GPR_WDOG1_IPG_STOP REGBIT(1, 53) +#define GPR_TPM1_IPG_STOP REGBIT(1, 57) +#define GPR_LPUART1_IPG_STOP REGBIT(1, 59) +#define GPR_LPUART1_IPG_STOP_MODE REGBIT(1, 60) +/** @} */ + +/*! + * @name SS GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_LP_STOP_MODE_LOWV_BBS0 REGBIT(0, 24) +#define GPS_LP_STOP_MODE_LOWV_BBS1 REGBIT(0, 25) +#define GPS_LP_STOP_MODE_LOWV_BBS2 REGBIT(0, 26) +#define GPS_LP_STOP_OPTION_BBS0 REGBIT(0, 28) +#define GPS_LP_STOP_OPTION_BBS1 REGBIT(0, 29) +#define GPS_CPU_SLEEP_DEEP_HOLD_ACK REGBIT(0, 31) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_CM4_CPU_SLEEPING REGBIT64(1, 4) +#define IRQ_CM4_CPU_SLEEP_DEEP REGBIT64(1, 5) +#define IRQ_CM4_AXBS_STALL_ACK REGBIT64(1, 6) +#define IRQ_CM4_CPU_SYS_RESET_REQ REGBIT64(1, 7) +#define IRQ_WDOG1_WDG_RSTO REGBIT64(1, 8) +#define IRQ_CM4_CPU_LOCKUP REGBIT64(1, 9) +#define IRQ_AWIC_REQ REGBIT64(1, 10) +#define IRQ_CM4_UECC_ERR REGBIT64(1, 11) +#define IRQ_BBS_SIM_BBS_LP_RUN_REQ REGBIT64(1, 12) +#define IRQ_BBS_SIM_BBS_HS_RUN_REQ REGBIT64(1, 13) +#define IRQ_LPI2C1_IPG_STOP_ACK REGBIT64(1, 20) +#define IRQ_LPUART1_IPG_STOP_ACK REGBIT64(1, 21) +#define IRQ_INTMUX_INT_OUT_ASYNC REGBIT64(1, 24) +#define IRQ_MU_SIDEB REGBIT64(1, 27) +/** @} */ + +#endif /* SC_SS_M4_DSC_H */ + +/** @} */ + diff --git a/platform/ss/m4/v1/rsrc.h b/platform/ss/m4/v1/rsrc.h new file mode 100644 index 0000000..d943978 --- /dev/null +++ b/platform/ss/m4/v1/rsrc.h @@ -0,0 +1,97 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the M4 subsystem. + * + * @addtogroup M4_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_M4_RSRC_H +#define SC_SS_M4_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_M4_0_PID0 0U +#define SS_R_M4_0_PID1 1U +#define SS_R_M4_0_PID2 2U +#define SS_R_M4_0_PID3 3U +#define SS_R_M4_0_PID4 4U +#define SS_R_M4_0_RGPIO 5U +#define SS_R_M4_0_SEMA42 6U +#define SS_R_M4_0_TPM 7U +#define SS_R_M4_0_PIT 8U +#define SS_R_M4_0_UART 9U +#define SS_R_M4_0_I2C 10U +#define SS_R_M4_0_INTMUX 11U +#define SS_R_M4_0_MU_0B 12U +#define SS_R_M4_0_MU_0A0 13U +#define SS_R_M4_0_MU_0A1 14U +#define SS_R_M4_0_MU_0A2 15U +#define SS_R_M4_0_MU_0A3 16U +#define SS_R_M4_0_MU_1A 17U +#define SS_R_M4_1_PID0 0U +#define SS_R_M4_1_PID1 1U +#define SS_R_M4_1_PID2 2U +#define SS_R_M4_1_PID3 3U +#define SS_R_M4_1_PID4 4U +#define SS_R_M4_1_RGPIO 5U +#define SS_R_M4_1_SEMA42 6U +#define SS_R_M4_1_TPM 7U +#define SS_R_M4_1_PIT 8U +#define SS_R_M4_1_UART 9U +#define SS_R_M4_1_I2C 10U +#define SS_R_M4_1_INTMUX 11U +#define SS_R_M4_1_MU_0B 12U +#define SS_R_M4_1_MU_0A0 13U +#define SS_R_M4_1_MU_0A1 14U +#define SS_R_M4_1_MU_0A2 15U +#define SS_R_M4_1_MU_0A3 16U +#define SS_R_M4_1_MU_1A 17U +/** @} */ + +#endif /* SC_SS_M4_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/m4/v1/ss.h b/platform/ss/m4/v1/ss.h new file mode 100755 index 0000000..80d3781 --- /dev/null +++ b/platform/ss/m4/v1/ss.h @@ -0,0 +1,67 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the M4 subsystem API. + * + * @addtogroup M4_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_M4_SS_H +#define SC_SS_M4_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(m4) + +/* Functions */ + +SS_FUNC_PROTO_M4 + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_mcu[]; + +#endif /* SC_SS_M4_SS_H */ + +/** @} */ + diff --git a/platform/ss/mipi/v1/Makefile b/platform/ss/mipi/v1/Makefile new file mode 100755 index 0000000..1f0f8d3 --- /dev/null +++ b/platform/ss/mipi/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/mipi/v1/ss.o + +CONFIGH += $(SRC)/ss/mipi/v1/config.h $(SRC)/ss/mipi/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/mipi/v1/resource.txt + +CLK_MD += $(SRC)/ss/mipi/v1/clock.txt + +CTRL_MD += $(SRC)/ss/mipi/v1/control.txt + +DIRS += $(OUT)/ss/mipi/v1 + diff --git a/platform/ss/mipi/v1/config.h b/platform/ss/mipi/v1/config.h new file mode 100644 index 0000000..ecde9a0 --- /dev/null +++ b/platform/ss/mipi/v1/config.h @@ -0,0 +1,136 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the MIPI subsystem. + * + * @addtogroup MIPI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_MIPI_CONFIG_H +#define SC_SS_MIPI_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_MIPI 4U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_MIPI \ + void ss_init_mipi(sc_sub_t ss, sc_bool_t api_phase); \ + void ss_trans_power_mode_mipi(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t \ + to_mode); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_MIPI \ + { \ + ss_init_mipi, \ + ss_trans_power_mode_mipi, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_base, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_MIPI_0 \ + "MIPI_0", \ + "MIPI_0_PWM_0", \ + "MIPI_0_I2C_0", \ + "MIPI_0_I2C_1", \ + + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_MIPI_1 \ + "MIPI_1", \ + "MIPI_1_PWM_0", \ + "MIPI_1_I2C_0", \ + "MIPI_1_I2C_1", \ + +#endif + +#endif /* SC_SS_MIPI_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/mipi/v1/dsc.h b/platform/ss/mipi/v1/dsc.h new file mode 100755 index 0000000..aade67c --- /dev/null +++ b/platform/ss/mipi/v1/dsc.h @@ -0,0 +1,119 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup MIPI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_MIPI_DSC_H +#define SC_SS_MIPI_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_MIPI_BYTE REGBIT(0, 2) +#define RST_MIPI_DPI REGBIT(0, 3) +#define RST_MIPI_ESC REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ + +#define GPR_D3_0_TM REGBIT(0, 0) +#define GPR_CLK_0_TM REGBIT(0, 1) +#define GPR_CLK_1_TM REGBIT(0, 2) +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 3) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 4) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 5) +#define GPR_PWM0_IPG_STOP REGBIT(0, 6) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 7) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 8) +#define GPR_I2C0_IPG_STOP REGBIT(0, 9) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 10) +#define GPR_I2C1_IPG_DEBUG REGBIT(0, 11) +#define GPR_I2C1_IPG_DOZE REGBIT(0, 12) +#define GPR_I2C1_IPG_STOP REGBIT(0, 13) +#define GPR_I2C1_IPG_STOP_MODE REGBIT(0, 14) +#define GPR_CLK_2_TM REGBIT(0, 15) +#define GPR_PHY_ISO REGBIT(0, 16) +#define GPR_D3_1_TM REGBIT(0, 17) +#define GPR_D3_2_TM REGBIT(0, 18) +#define GPR_D2_TM REGBIT(0, 19) +#define GPR_D1_0_TM REGBIT(0, 22) +#define GPR_D1_1_TM REGBIT(0, 23) +#define GPR_TX_RCAL REGBIT(0, 26) +#define GPR_D1_2_TM REGBIT(0, 28) +#define GPR_D0_TM REGBIT(0, 29) + +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 0) +#define GPS_I2C1_STOP_ACK REGBIT(0, 1) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO_0 REGBIT64(1, 0) +#define IRQ_GPIO_1 REGBIT64(1, 1) +#define IRQ_GPIO_2 REGBIT64(1, 2) +#define IRQ_GPIO_3 REGBIT64(1, 3) +#define IRQ_LPI2C0_HREQ REGBIT64(1, 4) +#define IRQ_LPI2C1_HREQ REGBIT64(1, 5) +#define IRQ_WAKE_CTI REGBIT64(1, 6) +/** @} */ + +#endif /* SC_SS_MIPI_DSC_H */ + +/** @} */ diff --git a/platform/ss/mipi/v1/rsrc.h b/platform/ss/mipi/v1/rsrc.h new file mode 100644 index 0000000..c55047e --- /dev/null +++ b/platform/ss/mipi/v1/rsrc.h @@ -0,0 +1,69 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the MIPI subsystem. + * + * @addtogroup MIPI_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_MIPI_RSRC_H +#define SC_SS_MIPI_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_MIPI_0 0U +#define SS_R_MIPI_0_PWM_0 1U +#define SS_R_MIPI_0_I2C_0 2U +#define SS_R_MIPI_0_I2C_1 3U +#define SS_R_MIPI_1 0U +#define SS_R_MIPI_1_PWM_0 1U +#define SS_R_MIPI_1_I2C_0 2U +#define SS_R_MIPI_1_I2C_1 3U +/** @} */ + +#endif /* SC_SS_MIPI_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/mipi/v1/ss.h b/platform/ss/mipi/v1/ss.h new file mode 100755 index 0000000..66f4217 --- /dev/null +++ b/platform/ss/mipi/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the MIPI subsystem API. + * + * @addtogroup MIPI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_MIPI_SS_H +#define SC_SS_MIPI_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(mipi) + +/* Functions */ + +SS_FUNC_PROTO_MIPI + +#endif /* SC_SS_MIPI_SS_H */ + +/** @} */ + diff --git a/platform/ss/mipi/v2/Makefile b/platform/ss/mipi/v2/Makefile new file mode 100755 index 0000000..6707cda --- /dev/null +++ b/platform/ss/mipi/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/mipi/v2/ss.o + +CONFIGH += $(SRC)/ss/mipi/v2/config.h $(SRC)/ss/mipi/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/mipi/v2/resource.txt + +CLK_MD += $(SRC)/ss/mipi/v2/clock.txt + +CTRL_MD += $(SRC)/ss/mipi/v2/control.txt + +DIRS += $(OUT)/ss/mipi/v2 + diff --git a/platform/ss/mipi/v2/dsc.h b/platform/ss/mipi/v2/dsc.h new file mode 100755 index 0000000..cc9334a --- /dev/null +++ b/platform/ss/mipi/v2/dsc.h @@ -0,0 +1,123 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup MIPI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_MIPI_DSC_H +#define SC_SS_MIPI_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_MIPI_BYTE REGBIT(0, 2) +#define RST_MIPI_DPI REGBIT(0, 3) +#define RST_MIPI_ESC REGBIT(0, 4) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 10) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 11) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 12) +#define GPR_PWM0_IPG_STOP REGBIT(0, 13) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 14) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 15) +#define GPR_I2C0_IPG_STOP REGBIT(0, 16) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 17) +#define GPR_I2C1_IPG_DEBUG REGBIT(0, 18) +#define GPR_I2C1_IPG_DOZE REGBIT(0, 19) +#define GPR_I2C1_IPG_STOP REGBIT(0, 20) +#define GPR_I2C1_IPG_STOP_MODE REGBIT(0, 21) +#define GPR_PXL_LINK_RATE_CORRECT REGBIT(0, 22) +#define GPR_CKIL_SYNC_REQ REGBIT(0, 23) +#define GPR_MIPI_DSI_CTRL_MODE REGBIT(0, 24) +#define GPR_CTRL_LINK_SLV1_ADDR REGBIT(0, 25) +#define GPR_MIPI_DSI_CTRL_MODE8 REGBIT(0, 28) +#define GPR_PXL_LINK_SELECT REGBIT(0, 29) +#define GPR_MIPI_DSI_CTRL_TX_RCAL REGBIT(0, 30) +/** @} */ + +/*! + * @name GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_PHY_ISO REGBIT(1, 33) +#define GPR_D0_TM REGBIT(1, 34) +#define GPR_D1_TM REGBIT(1, 37) +#define GPR_D2_TM REGBIT(1, 40) +#define GPR_D3_TM REGBIT(1, 43) +#define GPR_CLK_TM REGBIT(1, 46) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 8) +#define GPS_I2C1_STOP_ACK REGBIT(0, 9) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO_0_4 REGBIT64(1, 0) +#define IRQ_GPIO_1_5 REGBIT64(1, 1) +#define IRQ_GPIO_2_6 REGBIT64(1, 2) +#define IRQ_GPIO_3_7 REGBIT64(1, 3) +#define IRQ_LPI2C0_HREQ REGBIT64(1, 4) +#define IRQ_LPI2C1_HREQ REGBIT64(1, 5) +#define IRQ_WAKE_CTI REGBIT64(1, 6) +/** @} */ + +#endif /* SC_SS_MIPI_DSC_H */ + +/** @} */ diff --git a/platform/ss/mipi/v2/ss.h b/platform/ss/mipi/v2/ss.h new file mode 100755 index 0000000..0c59669 --- /dev/null +++ b/platform/ss/mipi/v2/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the MIPI/LVDS subsystem API. + * + * @addtogroup MIPI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_MIPI_SS_H +#define SC_SS_MIPI_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(mipi) + +/* Functions */ + +SS_FUNC_PROTO_MIPI + +#endif /* SC_SS_MIPI_SS_H */ + +/** @} */ + diff --git a/platform/ss/pi/v1/Makefile b/platform/ss/pi/v1/Makefile new file mode 100755 index 0000000..43578db --- /dev/null +++ b/platform/ss/pi/v1/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/pi/v1/ss.o + +CONFIGH += $(SRC)/ss/pi/v1/config.h $(SRC)/ss/pi/v1/rsrc.h + +RSRC_MD += $(SRC)/ss/pi/v1/resource.txt + +CLK_MD += $(SRC)/ss/pi/v1/clock.txt + +CTRL_MD += $(SRC)/ss/pi/v1/control.txt + +DIRS += $(OUT)/ss/pi/v1 + diff --git a/platform/ss/pi/v1/dsc.h b/platform/ss/pi/v1/dsc.h new file mode 100755 index 0000000..a1b5708 --- /dev/null +++ b/platform/ss/pi/v1/dsc.h @@ -0,0 +1,92 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup PI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_PI_DSC_H +#define SC_SS_PI_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_PWM0_IPG_DEBUG REGBIT(0, 10) +#define GPR_PWM0_IPG_DOZE REGBIT(0, 11) +#define GPR_PWM0_IPG_WAIT REGBIT(0, 12) +#define GPR_PWM0_IPG_STOP REGBIT(0, 13) +#define GPR_I2C0_IPG_DEBUG REGBIT(0, 14) +#define GPR_I2C0_IPG_DOZE REGBIT(0, 15) +#define GPR_I2C0_IPG_STOP REGBIT(0, 16) +#define GPR_I2C0_IPG_STOP_MODE REGBIT(0, 17) +#define GPR_CKIL_SYNC_REQ REGBIT(0, 23) +#define GPR_CTRL_LINK_SLV1_ADDR REGBIT(0, 25) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_I2C0_STOP_ACK REGBIT(0, 4) +/** @} */ + +/*! + * @name IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_GPIO0_4 REGBIT(1, 0) +#define IRQ_GPIO1_5 REGBIT(1, 1) +#define IRQ_GPIO2_6 REGBIT(1, 2) +#define IRQ_GPIO3_7 REGBIT(1, 3) +#define IRQ_LPI2C_HREQ REGBIT(1, 4) +#define IRQ_IRQSTR_CTI0 REGBIT(1, 6) +/** @} */ + +#endif /* SC_SS_PI_DSC_H */ + +/** @} */ + diff --git a/platform/ss/pi/v1/ss.h b/platform/ss/pi/v1/ss.h new file mode 100755 index 0000000..ac59eb3 --- /dev/null +++ b/platform/ss/pi/v1/ss.h @@ -0,0 +1,63 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the PI subsystem API. + * + * @addtogroup PI_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_PI_SS_H +#define SC_SS_PI_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(pi) + +/* Functions */ + +SS_FUNC_PROTO_PI + +#endif /* SC_SS_PI_SS_H */ + +/** @} */ + diff --git a/platform/ss/sc/v2/Makefile b/platform/ss/sc/v2/Makefile new file mode 100755 index 0000000..3180b02 --- /dev/null +++ b/platform/ss/sc/v2/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/sc/v2/ss.o + +CONFIGH += $(SRC)/ss/sc/v2/config.h $(SRC)/ss/sc/v2/rsrc.h + +RSRC_MD += $(SRC)/ss/sc/v2/resource.txt + +CLK_MD += $(SRC)/ss/sc/v2/clock.txt + +CTRL_MD += $(SRC)/ss/sc/v2/control.txt + +DIRS += $(OUT)/ss/sc/v2 + diff --git a/platform/ss/sc/v2/config.h b/platform/ss/sc/v2/config.h new file mode 100644 index 0000000..c7749c4 --- /dev/null +++ b/platform/ss/sc/v2/config.h @@ -0,0 +1,165 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the SC subsystem. + * + * @addtogroup SC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_SC_CONFIG_H +#define SC_SS_SC_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_SC 33U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_SC \ + void ss_init_sc(sc_sub_t ss, sc_bool_t api_phase); \ + void ss_rdc_enable_sc(sc_sub_t ss, sc_bool_t master); \ + void ss_rdc_set_master_sc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, sc_rm_spa_t sa, \ + sc_rm_spa_t pa, sc_rm_did_t did, sc_rm_sid_t sid, uint8_t cid); \ + void ss_rdc_set_peripheral_sc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t valid, sc_bool_t lock, const sc_rm_perm_t \ + *perms, sc_bool_t no_update); \ + sc_err_t ss_get_control_sc(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, uint32_t ctrl, uint32_t *val); \ + void ss_prepost_power_mode_sc(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_SC \ + { \ + ss_init_sc, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_base, \ + ss_rdc_enable_sc, \ + ss_rdc_set_master_sc, \ + ss_rdc_set_peripheral_sc, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_sc, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_base, \ + ss_updown_base, \ + ss_prepost_power_mode_sc, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_SC_0 \ + "SC_PID0", \ + "SC_PID1", \ + "SC_PID2", \ + "SC_PID3", \ + "SC_PID4", \ + "SC_SEMA42", \ + "SC_TPM", \ + "SC_PIT", \ + "SC_UART", \ + "SC_I2C", \ + "SC_MU_0B", \ + "SC_MU_0A0", \ + "SC_MU_0A1", \ + "SC_MU_0A2", \ + "SC_MU_0A3", \ + "SC_MU_1A", \ + "SYSCNT_RD", \ + "SYSCNT_CMP", \ + "DEBUG", \ + "SYSTEM", \ + "SECO", \ + "CAAM_JR1", \ + "CAAM_JR1_OUT", \ + "CAAM_JR2", \ + "CAAM_JR2_OUT", \ + "CAAM_JR3", \ + "CAAM_JR3_OUT", \ + "SECO_MU_2", \ + "SECO_MU_3", \ + "SECO_MU_4", \ + "OTP", \ + "ATTESTATION", \ + "SECVIO", \ + +#endif + +#endif /* SC_SS_SC_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/sc/v2/dsc.h b/platform/ss/sc/v2/dsc.h new file mode 100755 index 0000000..7b8a59c --- /dev/null +++ b/platform/ss/sc/v2/dsc.h @@ -0,0 +1,214 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup SC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_SC_DSC_H +#define SC_SS_SC_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name SS GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_CM4_HCLK_MUX_SEL REGBIT(0, 8) +#define GPR_CM4_PANIC_MODE_SEL REGBIT(0, 9) +#define GPR_CM4_AXBS_STALL_REQUEST REGBIT(0, 10) +#define GPR_ROSC_STOP_EN_AON REGBIT(0, 11) +#define GPR_CM4_DBG_REQ REGBIT(0, 12) +#define GPR_CM4_TX_EVENT_ENB REGBIT(0, 13) +#define GPR_CM4_HCLK_ENB REGBIT(0, 14) +#define GPR_CXCTI0 REGBIT(0, 15) +#define GPR_CSYSREQ_DBLOG REGBIT(0, 16) +#define GPR_CSYSREQ_SCU REGBIT(0, 17) +#define GPR_CSYSREQ_CM4_0 REGBIT(0, 18) +#define GPR_CSYSREQ_CM4_1 REGBIT(0, 19) +#define GPR_CSYSREQ_A53 REGBIT(0, 20) +#define GPR_CSYSREQ_A72 REGBIT(0, 21) +#define GPR_CSYSREQ_VPU REGBIT(0, 22) +#define GPR_SIM_BBS_LP_RUN_ACK_3V REGBIT(0, 24) +#define GPR_SIM_BBS_HS_RUN_ACK_3V REGBIT(0, 25) +#define GPR_SIM_SYS_RST_SRSL_WDOG REGBIT(0, 26) +#define GPR_SIM_SYS_RST_SRSH_LOCKUP REGBIT(0, 27) +#define GPR_SIM_SYS_RST_SRSH_SW REGBIT(0, 28) +#define GPR_SIM_SYS_RST_SRSH_UECC REGBIT(0, 29) +#define GPR_SIM_RCM_VLLS_DETECT REGBIT(0, 30) +#define GPR_SLEEP_HOLD_REQ REGBIT(0, 31) +/** @} */ + +/*! + * @name SS GPR Control 1 Bit Definitions + */ +/** @{ */ +#define GPR_CPWRUPACK1 REGBIT(1, 33) +#define GPR_CPWRUPACK2 REGBIT(1, 34) +#define GPR_CPWRUPACK3 REGBIT(1, 35) +#define GPR_CPWRUPACK4 REGBIT(1, 36) +#define GPR_CPWRUPACK5 REGBIT(1, 37) +#define GPR_CPWRUPACK6 REGBIT(1, 38) +#define GPR_CPWRUPACK7 REGBIT(1, 39) +#define GPR_CPWRUPACK8 REGBIT(1, 40) +#define GPR_CPWRUPACK9 REGBIT(1, 41) +#define GPR_CPWRUPACK10 REGBIT(1, 42) +#define GPR_CPWRUPACK11 REGBIT(1, 43) +#define GPR_CPWRUPACK12 REGBIT(1, 44) +#define GPR_CDBGPWRUPACK REGBIT(1, 45) +#define GPR_CSYSPWRUPACK REGBIT(1, 46) +#define GPR_CDBGRSTACK REGBIT(1, 47) +#define GPR_SEC_SLEEP_HOLD_REQ REGBIT(1, 48) +#define GPR_SEC_AXBS_STALL_REQ REGBIT(1, 49) +#define GPR_LPI2C1_IPG_STOP REGBIT(1, 50) +#define GPR_LPI2C1_IPG_STOP_MODE REGBIT(1, 51) +#define GPR_WDOG1_IPG_STOP REGBIT(1, 53) +#define GPR_CAAM_CLK_EN REGBIT(1, 54) +#define GPR_CAAM_IPG_STOP REGBIT(1, 55) +#define GPR_SNVS_IPG_STOP REGBIT(1, 56) +#define GPR_TPM1_IPG_STOP REGBIT(1, 57) +#define GPR_EWR_CONFIG REGBIT(1, 58) +#define GPR_LPUART1_IPG_STOP REGBIT(1, 59) +#define GPR_LPUART1_IPG_STOP_MODE REGBIT(1, 60) +#define GPR_CLEAR_WRITE_ERR REGBIT(1, 61) +#define GPR_IOMUX_ISO_EN0 REGBIT(1, 62) +#define GPR_IOMUX_ISO_EN1 REGBIT(1, 63) +/** @} */ + +/*! + * @name SS GPR Control 2 Bit Definitions + */ +/** @{ */ +#define GPR_TL_ISO_EN_B REGBIT(2, 64) +#define GPR_TL_SW_LF_EN REGBIT(2, 65) +#define GPR_TL_SW_HF_EN REGBIT(2, 66) +#define GPR_ADM_LP_INHIBIT REGBIT(2, 67) +#define GPR_SNVS_HP_RTCCLK REGBIT(2, 68) +#define GPR_EWR_ENABLE REGBIT(2, 69) +#define GPR_UNCORR_ECC_FIX0 REGBIT(2, 70) +#define GPR_UNCORR_ECC_FIX1 REGBIT(2, 71) +#define GPR_UNCORR_ECC_FIX2 REGBIT(2, 72) +#define GPR_UNCORR_ECC_FIX3 REGBIT(2, 73) +#define GPR_UNCORR_ECC_FIX4 REGBIT(2, 74) +#define GPR_UNCORR_ECC_FIX5 REGBIT(2, 75) +#define GPR_PLL_FREQ_COUNTER REGBIT(2, 76) +/** @} */ + +/*! + * @name SS GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_BOOT_MODE0 REGBIT(0, 16) +#define GPS_BOOT_MODE1 REGBIT(0, 17) +#define GPS_BOOT_MODE2 REGBIT(0, 18) +#define GPS_BOOT_MODE3 REGBIT(0, 19) +#define GPS_BOOT_MODE4 REGBIT(0, 20) +#define GPS_BOOT_MODE5 REGBIT(0, 21) +#define GPS_BOOT_MODE6 REGBIT(0, 22) +#define GPS_BOOT_MODE7 REGBIT(0, 23) +#define GPS_LP_STOP_MODE_LOWV_BBS0 REGBIT(0, 24) +#define GPS_LP_STOP_MODE_LOWV_BBS1 REGBIT(0, 25) +#define GPS_LP_STOP_MODE_LOWV_BBS2 REGBIT(0, 26) +#define GPS_LP_STOP_OPTION_BBS0 REGBIT(0, 28) +#define GPS_LP_STOP_OPTION_BBS1 REGBIT(0, 29) +/** @} */ + +/*! + * @name SS GPR Status 1 Bit Definitions + */ +/** @{ */ +#define GPS_CPWRUPREQ1 REGBIT(1, 1) +#define GPS_CPWRUPREQ2 REGBIT(1, 2) +#define GPS_CPWRUPREQ3 REGBIT(1, 3) +#define GPS_CPWRUPREQ4 REGBIT(1, 4) +#define GPS_CPWRUPREQ5 REGBIT(1, 5) +#define GPS_CPWRUPREQ6 REGBIT(1, 6) +#define GPS_CPWRUPREQ7 REGBIT(1, 7) +#define GPS_CPWRUPREQ8 REGBIT(1, 8) +#define GPS_CPWRUPREQ9 REGBIT(1, 9) +#define GPS_CDBGPWRUPREQ REGBIT(1, 13) +#define GPS_CSYSPWRUPREQ REGBIT(1, 14) +#define GPS_CDBGRSTREQ REGBIT(1, 15) +#define GPS_SEC_SLEEP_HOLD_ACK REGBIT(1, 16) +#define GPS_ADM_LPM_INHIBIT REGBIT(1, 17) +#define GPS_ADM_CAAM_CG_INHIBIT REGBIT(1, 18) +/** @} */ + +/*! + * @name SS GPR Status 2 Bit Definitions + */ +/** @{ */ +#define GPS_JTAG_ID REGBIT(2, 0) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_CM4_CPU_SLEEPING REGBIT64(1, 4) +#define IRQ_CM4_CPU_SLEEP_DEEP REGBIT64(1, 5) +#define IRQ_CM4_AXBS_STALL_ACK REGBIT64(1, 6) +#define IRQ_CM4_CPU_SYS_RESET_REQ REGBIT64(1, 7) +#define IRQ_WDOG1_WDG_RSTO REGBIT64(1, 8) +#define IRQ_CM4_CPU_LOCKUP REGBIT64(1, 9) +#define IRQ_AWIC_REQ REGBIT64(1, 10) +#define IRQ_CM4_UECC_ERR REGBIT64(1, 11) +#define IRQ_BBS_SIM_BBS_LP_RUN_REQ REGBIT64(1, 12) +#define IRQ_BBS_SIM_BBS_HS_RUN_REQ REGBIT64(1, 13) +#define IRQ_CM0_CPU_SLEEP_DEEP REGBIT64(1, 15) +#define IRQ_CM0_CPU_RESET_REQ REGBIT64(1, 16) +#define IRQ_CM0_WDOG1_WDG_RSTO REGBIT64(1, 17) +#define IRQ_CM0_CPU_LOCKUP REGBIT64(1, 18) +#define IRQ_CM0_UECC_ERR REGBIT64(1, 19) +#define IRQ_LPI2C1_IPG_STOP_ACK REGBIT64(1, 20) +#define IRQ_LPUART1_IPG_STOP_ACK REGBIT64(1, 21) +#define IRQ_CAAM_IPG_STOP_ACK REGBIT64(1, 22) +#define IRQ_INTMUX_INT_OUT_ASYNC REGBIT64(1, 24) +#define IRQ_MU_SIDEB REGBIT64(1, 27) +/** @} */ + +#endif /* SC_SS_SC_DSC_H */ + +/** @} */ + diff --git a/platform/ss/sc/v2/rsrc.h b/platform/ss/sc/v2/rsrc.h new file mode 100644 index 0000000..d2f70c2 --- /dev/null +++ b/platform/ss/sc/v2/rsrc.h @@ -0,0 +1,94 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the SC subsystem. + * + * @addtogroup SC_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_SC_RSRC_H +#define SC_SS_SC_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_SC_PID0 0U +#define SS_R_SC_PID1 1U +#define SS_R_SC_PID2 2U +#define SS_R_SC_PID3 3U +#define SS_R_SC_PID4 4U +#define SS_R_SC_SEMA42 5U +#define SS_R_SC_TPM 6U +#define SS_R_SC_PIT 7U +#define SS_R_SC_UART 8U +#define SS_R_SC_I2C 9U +#define SS_R_SC_MU_0B 10U +#define SS_R_SC_MU_0A0 11U +#define SS_R_SC_MU_0A1 12U +#define SS_R_SC_MU_0A2 13U +#define SS_R_SC_MU_0A3 14U +#define SS_R_SC_MU_1A 15U +#define SS_R_SYSCNT_RD 16U +#define SS_R_SYSCNT_CMP 17U +#define SS_R_DEBUG 18U +#define SS_R_SYSTEM 19U +#define SS_R_SECO 20U +#define SS_R_CAAM_JR1 21U +#define SS_R_CAAM_JR1_OUT 22U +#define SS_R_CAAM_JR2 23U +#define SS_R_CAAM_JR2_OUT 24U +#define SS_R_CAAM_JR3 25U +#define SS_R_CAAM_JR3_OUT 26U +#define SS_R_SECO_MU_2 27U +#define SS_R_SECO_MU_3 28U +#define SS_R_SECO_MU_4 29U +#define SS_R_OTP 30U +#define SS_R_ATTESTATION 31U +#define SS_R_SECVIO 32U +/** @} */ + +#endif /* SC_SS_SC_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/sc/v2/ss.h b/platform/ss/sc/v2/ss.h new file mode 100755 index 0000000..f67877b --- /dev/null +++ b/platform/ss/sc/v2/ss.h @@ -0,0 +1,71 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the SC subsystem API. + * + * @addtogroup SC_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_SC_SS_H +#define SC_SS_SC_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(sc) + +/* Functions */ + +SS_FUNC_PROTO_SC + +void ss_timestamp_enable_sc(sc_sub_t remote, sc_bool_t enable); +void ss_pause_ddr_traffic_sc(sc_bool_t pause); +void ss_osc24trim_setup_sc(sc_pm_power_mode_t mode); + +/* External variables */ + +extern const ss_dsc_l2irq_handler ss_l2irq_handlers_sc[]; + +#endif /* SC_SS_SC_SS_H */ + +/** @} */ + diff --git a/platform/ss/vpu/v3/Makefile b/platform/ss/vpu/v3/Makefile new file mode 100755 index 0000000..764664c --- /dev/null +++ b/platform/ss/vpu/v3/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/vpu/v3/ss.o + +CONFIGH += $(SRC)/ss/vpu/v3/config.h $(SRC)/ss/vpu/v3/rsrc.h + +RSRC_MD += $(SRC)/ss/vpu/v3/resource.txt + +CLK_MD += $(SRC)/ss/vpu/v3/clock.txt + +CTRL_MD += $(SRC)/ss/vpu/v3/control.txt + +DIRS += $(OUT)/ss/vpu/v3 + diff --git a/platform/ss/vpu/v3/config.h b/platform/ss/vpu/v3/config.h new file mode 100644 index 0000000..03e1fdd --- /dev/null +++ b/platform/ss/vpu/v3/config.h @@ -0,0 +1,145 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the entry points and debug resource strings + * for the VPU subsystem. + * + * @addtogroup VPU_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/config_ss_h.pl */ + +#ifndef SC_SS_VPU_CONFIG_H +#define SC_SS_VPU_CONFIG_H + +/*! + * This define defines the number of resources. + */ +#define SS_NUM_RSRC_VPU 19U + +/*! Define used to create subsystem function prototypes */ +#define SS_FUNC_PROTO_VPU \ + sc_err_t ss_cpu_start_vpu(sc_sub_t ss, ss_idx_t ss_idx, ss_ridx_t \ + rsrc_idx, sc_bool_t enable, sc_faddr_t addr); \ + void ss_do_mem_repair_vpu(sc_sub_t ss, dsc_pdom_t pd, sc_bool_t \ + enable); \ + void ss_prepost_power_mode_vpu(sc_sub_t ss, dsc_pdom_t pd, ss_prepost_t \ + type, sc_pm_power_mode_t from_mode, sc_pm_power_mode_t to_mode, \ + sc_bool_t rom_boot); \ + + +/*! + * This define is used to override the default SS function entry points. + * If this isn't defined, then the SS uses functions in base. + */ +#define SS_EP_INIT_VPU \ + { \ + ss_init_base, \ + ss_trans_power_mode_base, \ + ss_rsrc_reset_base, \ + ss_set_cpu_power_mode_base, \ + ss_set_cpu_resume_base, \ + ss_req_sys_if_power_mode_base, \ + ss_set_clock_rate_base, \ + ss_get_clock_rate_base, \ + ss_clock_enable_base, \ + ss_force_clock_enable_base, \ + ss_set_clock_parent_base, \ + ss_get_clock_parent_base, \ + ss_is_rsrc_accessible_base, \ + ss_mu_irq_base, \ + ss_cpu_start_vpu, \ + ss_rdc_enable_base, \ + ss_rdc_set_master_base, \ + ss_rdc_set_peripheral_base, \ + ss_rdc_set_memory_base, \ + ss_set_control_base, \ + ss_get_control_base, \ + ss_irq_enable_base, \ + ss_irq_status_base, \ + ss_irq_trigger_base, \ + ss_dump_base, \ + ss_do_mem_repair_vpu, \ + ss_updown_base, \ + ss_prepost_power_mode_vpu, \ + ss_iso_disable_base, \ + ss_link_enable_base, \ + ss_ssi_power_base, \ + ss_ssi_bhole_mode_base, \ + ss_ssi_pause_mode_base, \ + ss_ssi_wait_idle_base, \ + ss_adb_enable_base, \ + ss_adb_wait_base, \ + ss_prepost_clock_mode_base, \ + ss_rdc_is_did_vld_base, \ + } + +#ifdef DEBUG + /*! + * This define is used to name resources for debug output. + */ + #define RNAME_INIT_VPU_0 \ + "VPU", \ + "VPU_PID0", \ + "VPU_PID1", \ + "VPU_PID2", \ + "VPU_PID3", \ + "VPU_PID4", \ + "VPU_PID5", \ + "VPU_PID6", \ + "VPU_PID7", \ + "VPU_DEC_0", \ + "VPU_ENC_0", \ + "VPU_ENC_1", \ + "VPU_TS_0", \ + "VPU_MU_0", \ + "VPU_MU_1", \ + "VPU_MU_2", \ + "VPU_MU_3", \ + "DSP", \ + "DSP_RAM", \ + +#endif + +#endif /* SC_SS_VPU_CONFIG_H */ + +/** @} */ + diff --git a/platform/ss/vpu/v3/dsc.h b/platform/ss/vpu/v3/dsc.h new file mode 100755 index 0000000..1059d63 --- /dev/null +++ b/platform/ss/vpu/v3/dsc.h @@ -0,0 +1,143 @@ +/* +** ################################################################### +** +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup VPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_VPU_DSC_H +#define SC_SS_VPU_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_MED_CORE_ENC REGBIT(0, 2) +#define RST_SS_DSP REGBIT(0, 3) +#define RST_MED_CORE_DEC REGBIT(0, 4) +#define RST_SS_DSP_CORE REGBIT(0, 5) +#define RST_SS_DSP_DEBUG REGBIT(0, 6) +#define RST_MED_CORE_BISR REGBIT(0, 7) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SYS_OFFSET_IRQ REGBIT(0, 8) +#define GPR_SYS_OFFSET_AUD REGBIT(0, 16) +#define GPR_SYS_OFFSET_SEL REGBIT(0, 24) +#define GPR_ADB_DSP_PWRDNREQN0 REGBIT(0, 25) +#define GPR_ADB_DSP_PWRDNREQN1 REGBIT(0, 26) +#define GPR_DSP_CACHE_SEL REGBIT(0, 27) +#define GPR_DSP_CACHEABLE REGBIT(0, 28) +#define GPR_DSP_DMA_BYPASS REGBIT(0, 29) +#define GPR_ARCACHE REGBIT(0, 30) +#define GPR_AWCACHE REGBIT(0, 31) +/** @} */ + +/*! + * @name GPR Status 0 Bit Definitions + */ +/** @{ */ +#define GPS_DSP_DEBUGSTATUS REGBIT(0, 16) +#define GPS_ADB_DSP_PWRDNACKN0 REGBIT(0, 25) +#define GPS_ADB_DSP_CACTIVES0 REGBIT(0, 26) +#define GPS_ADB_DSP_CACTIVEM0 REGBIT(0, 27) +#define GPS_ADB_DSP_PWRDNACKN1 REGBIT(0, 29) +#define GPS_ADB_DSP_CACTIVES1 REGBIT(0, 30) +#define GPS_ADB_DSP_CACTIVEM1 REGBIT(0, 31) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_AVE_IRQ0 REGBIT64(1, 0) +#define IRQ_AVE_IRQ1 REGBIT64(1, 1) +#define IRQ_MSD_IRQ REGBIT64(1, 2) +#define IRQ_IRQSTR REGBIT64(1, 7) +/** @} */ + +/*! + * @name CSR2 0x00 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_EXPSTATE REGBIT(0x0, 0) +/** @} */ + +/*! + * @name CSR2 0x01 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_IMPWIRE REGBIT(0x1, 0) +/** @} */ + +/*! + * @name CSR2 0x02 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_PRID REGBIT(0x2, 0) +/** @} */ + +/*! + * @name CSR2 0x30 Bit Definitions + */ +/** @{ */ +#define CSR2_DSP_OCDHALTONRESET REGBIT(0x3, 0) +#define CSR2_DSP_RUNSTALL REGBIT(0x3, 1) +#define CSR2_DSP_STATVECTORSEL REGBIT(0x3, 2) +/** @} */ + +/*! + * @name CSR2 0x04 Bit Definitions + */ +/** @{ */ +/** @} */ + +#endif /* SC_SS_VPU_DSC_H */ + +/** @} */ + diff --git a/platform/ss/vpu/v3/rsrc.h b/platform/ss/vpu/v3/rsrc.h new file mode 100644 index 0000000..d0a20ae --- /dev/null +++ b/platform/ss/vpu/v3/rsrc.h @@ -0,0 +1,80 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing local resource defines for the VPU subsystem. + * + * @addtogroup VPU_SS + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rsrc_ss_h.pl */ + +#ifndef SC_SS_VPU_RSRC_H +#define SC_SS_VPU_RSRC_H + +/*! + * @name Defines for local SS resource indexes + */ +/** @{ */ +#define SS_R_VPU 0U +#define SS_R_VPU_PID0 1U +#define SS_R_VPU_PID1 2U +#define SS_R_VPU_PID2 3U +#define SS_R_VPU_PID3 4U +#define SS_R_VPU_PID4 5U +#define SS_R_VPU_PID5 6U +#define SS_R_VPU_PID6 7U +#define SS_R_VPU_PID7 8U +#define SS_R_VPU_DEC_0 9U +#define SS_R_VPU_ENC_0 10U +#define SS_R_VPU_ENC_1 11U +#define SS_R_VPU_TS_0 12U +#define SS_R_VPU_MU_0 13U +#define SS_R_VPU_MU_1 14U +#define SS_R_VPU_MU_2 15U +#define SS_R_VPU_MU_3 16U +#define SS_R_DSP 17U +#define SS_R_DSP_RAM 18U +/** @} */ + +#endif /* SC_SS_VPU_RSRC_H */ + +/** @} */ + diff --git a/platform/ss/vpu/v3/ss.h b/platform/ss/vpu/v3/ss.h new file mode 100755 index 0000000..147eff9 --- /dev/null +++ b/platform/ss/vpu/v3/ss.h @@ -0,0 +1,62 @@ +/* +** ################################################################### +** +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the VPU subsystem API. + * + * @addtogroup VPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_VPU_SS_H +#define SC_SS_VPU_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(vpu) + +/* Functions */ + +SS_FUNC_PROTO_VPU + +#endif /* SC_SS_VPU_SS_H */ + +/** @} */ + diff --git a/platform/ss/vpu/v4/Makefile b/platform/ss/vpu/v4/Makefile new file mode 100755 index 0000000..222e6ad --- /dev/null +++ b/platform/ss/vpu/v4/Makefile @@ -0,0 +1,13 @@ + +OBJS += $(OUT)/ss/vpu/v4/ss.o + +CONFIGH += $(SRC)/ss/vpu/v4/config.h $(SRC)/ss/vpu/v4/rsrc.h + +RSRC_MD += $(SRC)/ss/vpu/v4/resource.txt + +CLK_MD += $(SRC)/ss/vpu/v4/clock.txt + +CTRL_MD += $(SRC)/ss/vpu/v4/control.txt + +DIRS += $(OUT)/ss/vpu/v4 + diff --git a/platform/ss/vpu/v4/dsc.h b/platform/ss/vpu/v4/dsc.h new file mode 100755 index 0000000..9e4bed8 --- /dev/null +++ b/platform/ss/vpu/v4/dsc.h @@ -0,0 +1,87 @@ +/* +** ################################################################### +** +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing the subsystem specific DSC header info. + * + * @addtogroup VPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_VPU_DSC_H +#define SC_SS_VPU_DSC_H + +/* Includes */ + +#include "ss/base/v1/dsc.h" + +/*! + * @name Reset Bit Definitions + */ +/** @{ */ +#define RST_MED_CORE_ENC REGBIT(0, 2) +#define RST_MED_CORE_DEC REGBIT(0, 3) +#define RST_MED_CORE_BISR REGBIT(0, 7) +/** @} */ + +/*! + * @name GPR Control 0 Bit Definitions + */ +/** @{ */ +#define GPR_SEC_ENB REGBIT(0, 24) +#define GPR_DEC_CLK REGBIT(0, 25) +#define GPR_ENC_CLK REGBIT(0, 26) +#define GPR_ARCACHE REGBIT(0, 27) +#define GPR_AWCACHE REGBIT(0, 28) +/** @} */ + +/*! + * @name SS IRQ Mask Definitions + */ +/** @{ */ +#define IRQ_AVE_IRQ REGBIT64(1, 0) +#define IRQ_AVE_FIQ REGBIT64(1, 1) +#define IRQ_MSD_IRQ REGBIT64(1, 2) +#define IRQ_MSD_FIQ REGBIT64(1, 3) +#define IRQ_MSD_SIF REGBIT64(1, 4) +/** @} */ + +#endif /* SC_SS_VPU_DSC_H */ + +/** @} */ + diff --git a/platform/ss/vpu/v4/ss.h b/platform/ss/vpu/v4/ss.h new file mode 100755 index 0000000..147eff9 --- /dev/null +++ b/platform/ss/vpu/v4/ss.h @@ -0,0 +1,62 @@ +/* +** ################################################################### +** +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file containing the VPU subsystem API. + * + * @addtogroup VPU_SS + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SS_VPU_SS_H +#define SC_SS_VPU_SS_H + +#include "ss/inf/inf.h" + +/* Externs */ + +SS_BASE_INFO_PROTO(vpu) + +/* Functions */ + +SS_FUNC_PROTO_VPU + +#endif /* SC_SS_VPU_SS_H */ + +/** @} */ + diff --git a/platform/svc/irq/Makefile b/platform/svc/irq/Makefile new file mode 100755 index 0000000..ac04a8e --- /dev/null +++ b/platform/svc/irq/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/irq/svc.o + +RPCS += $(OUT)/svc/irq/rpc_srv.o + +RPCL += $(OUT)/svc/irq/rpc_clnt.o + +RPCH += $(SRC)/svc/irq/rpc.h + +RPCC += $(SRC)/svc/irq/rpc_srv.c \ + $(SRC)/svc/irq/rpc_clnt.c \ + $(SRC)/svc/irq/rpc_xlate.c + +RPCHDR += $(SRC)/svc/irq/rpc_header.h + +DIRS += $(OUT)/svc/irq + diff --git a/platform/svc/irq/api.h b/platform/svc/irq/api.h new file mode 100755 index 0000000..96983eb --- /dev/null +++ b/platform/svc/irq/api.h @@ -0,0 +1,211 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/irq/api.h + * + * Header file containing the public API for the System Controller (SC) + * Interrupt (IRQ) function. + * + * @addtogroup IRQ_SVC IRQ: Interrupt Service + * + * @brief Module for the Interrupt (IRQ) service. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_IRQ_API_H +#define SC_IRQ_API_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +#define SC_IRQ_NUM_GROUP 9U /*!< Number of groups */ + +/*! + * @name Defines for sc_irq_group_t + */ +/** @{ */ +#define SC_IRQ_GROUP_TEMP 0U /*!< Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /*!< Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /*!< RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /*!< Wakeup interrupts */ +#define SC_IRQ_GROUP_SYSCTR 4U /*!< System counter interrupts */ +#define SC_IRQ_GROUP_REBOOTED 5U /*!< Partition reboot complete */ +#define SC_IRQ_GROUP_REBOOT 6U /*!< Partition reboot starting */ +#define SC_IRQ_GROUP_OFFED 7U /*!< Partition off complete */ +#define SC_IRQ_GROUP_OFF 8U /*!< Partition off starting */ +/** @} */ + +/*! + * @name Defines for sc_irq_temp_t + */ +/** @{ */ +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /*!< Temp high alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /*!< CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /*!< CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /*!< GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /*!< GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /*!< DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /*!< VPU temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /*!< PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /*!< PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1UL << 10U) /*!< Temp low alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /*!< CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /*!< CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /*!< GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /*!< GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /*!< DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /*!< DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /*!< VPU temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /*!< PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /*!< PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /*!< PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /*!< PMIC2 temp alarm interrupt */ +/** @} */ + +/*! + * @name Defines for sc_irq_wdog_t + */ +/** @{ */ +#define SC_IRQ_WDOG (1U << 0U) /*!< Watchdog interrupt */ +/** @} */ + +/*! + * @name Defines for sc_irq_rtc_t + */ +/** @{ */ +#define SC_IRQ_RTC (1U << 0U) /*!< RTC interrupt */ +/** @} */ + +/*! + * @name Defines for sc_irq_wake_t + */ +/** @{ */ +#define SC_IRQ_BUTTON (1U << 0U) /*!< Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /*!< Pad wakeup */ +#define SC_IRQ_USR1 (1U << 2U) /*!< User defined 1 */ +#define SC_IRQ_USR2 (1U << 3U) /*!< User defined 2 */ +#define SC_IRQ_BC_PAD (1U << 4U) /*!< Pad wakeup (broadcast to all partitions) */ +#define SC_IRQ_SW_WAKE (1U << 5U) /*!< Software requested wake */ +#define SC_IRQ_SECVIO (1U << 6U) /*!< Security violation */ +/** @} */ + +/*! + * @name Defines for sc_irq_sysctr_t + */ +/** @{ */ +#define SC_IRQ_SYSCTR (1U << 0U) /*!< SYSCTR interrupt */ +/** @} */ + +/* Types */ + +/*! + * This type is used to declare an interrupt group. + */ +typedef uint8_t sc_irq_group_t; + +/*! + * This type is used to declare a bit mask of temp interrupts. + */ +typedef uint8_t sc_irq_temp_t; + +/*! + * This type is used to declare a bit mask of watchdog interrupts. + */ +typedef uint8_t sc_irq_wdog_t; + +/*! + * This type is used to declare a bit mask of RTC interrupts. + */ +typedef uint8_t sc_irq_rtc_t; + +/*! + * This type is used to declare a bit mask of wakeup interrupts. + */ +typedef uint8_t sc_irq_wake_t; + +/* Functions */ + +/*! + * This function enables/disables interrupts. If pending interrupts + * are unmasked, an interrupt will be triggered. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group group the interrupts are in + * @param[in] mask mask of interrupts to affect + * @param[in] enable state to change interrupts to + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + */ +/* IDL: E8 ENABLE(UI16 resource, UI8 group, UI32 mask, IB enable) #1 */ +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); + +/*! + * This function returns the current interrupt status (regardless if + * masked). Automatically clears pending interrupts. + * + * @param[in] ipc IPC handle + * @param[in] resource MU channel + * @param[in] group groups the interrupts are in + * @param[in] status status of interrupts + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if group invalid + * + * The returned \a status may show interrupts pending that are + * currently masked. + */ +/* IDL: E8 STATUS(UI16 resource, UI8 group, UO32 status) #2 */ +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status); + +#endif /* SC_IRQ_API_H */ + +/** @} */ + diff --git a/platform/svc/irq/rpc.h b/platform/svc/irq/rpc.h new file mode 100644 index 0000000..857b1ba --- /dev/null +++ b/platform/svc/irq/rpc.h @@ -0,0 +1,81 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the IRQ RPC implementation. + * + * @addtogroup IRQ_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_IRQ_RPC_H +#define SC_IRQ_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC IRQ function calls + */ +/** @{ */ +#define IRQ_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define IRQ_FUNC_ENABLE 1U /*!< Index for sc_irq_enable() RPC call */ +#define IRQ_FUNC_STATUS 2U /*!< Index for sc_irq_status() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming IRQ RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void irq_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_IRQ_RPC_H */ + +/** @} */ + diff --git a/platform/svc/irq/rpc_clnt.c b/platform/svc/irq/rpc_clnt.c new file mode 100644 index 0000000..ce35f58 --- /dev/null +++ b/platform/svc/irq/rpc_clnt.c @@ -0,0 +1,127 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the IRQ service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup IRQ_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "svc/irq/api.h" +#include "../../main/rpc.h" +#include "svc/irq/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 ENABLE(UI16 resource, UI8 group, UI32 mask, IB enable) #1 */ +sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, + uint32_t mask, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ); + RPC_FUNC(&msg) = U8(IRQ_FUNC_ENABLE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(mask); + RPC_U16(&msg, 4U) = U16(resource); + RPC_U8(&msg, 6U) = U8(group); + RPC_U8(&msg, 7U) = B2U8(enable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 STATUS(UI16 resource, UI8 group, UO32 status) #2 */ +sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource, sc_irq_group_t group, + uint32_t *status) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_IRQ); + RPC_FUNC(&msg) = U8(IRQ_FUNC_STATUS); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(group); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (status != NULL) + { + *status = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/** @} */ + diff --git a/platform/svc/irq/rpc_srv.c b/platform/svc/irq/rpc_srv.c new file mode 100644 index 0000000..ed6be85 --- /dev/null +++ b/platform/svc/irq/rpc_srv.c @@ -0,0 +1,147 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the IRQ service. + * + * @addtogroup IRQ_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/irq/svc.h" +#include "svc/irq/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void irq_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case IRQ_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch enable() */ + case IRQ_FUNC_ENABLE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 4U)); + sc_irq_group_t group = ((sc_irq_group_t) RPC_U8(msg, 6U)); + uint32_t mask = ((uint32_t) RPC_U32(msg, 0U)); + sc_bool_t enable = U2B(RPC_U8(msg, 7U)); + + /* Call function */ + err = irq_enable(caller_pt, resource, group, mask, enable); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch status() */ + case IRQ_FUNC_STATUS : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_irq_group_t group = ((sc_irq_group_t) RPC_U8(msg, 2U)); + uint32_t status = ((uint32_t) 0U); + + /* Call function */ + err = irq_status(caller_pt, resource, group, &status); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(status); + RPC_SIZE(msg) = 2U; + break; + } + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=irq, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=irq, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/irq/svc.c b/platform/svc/irq/svc.c new file mode 100755 index 0000000..8334902 --- /dev/null +++ b/platform/svc/irq/svc.c @@ -0,0 +1,140 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/irq/svc.c + * + * File containing the implementation of the System Controller (SC) + * Interrupt (IRQ) function. + * + * @addtogroup IRQ_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "svc/irq/svc.h" +#include "ss/inf/inf.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* Local Variables */ + +/*--------------------------------------------------------------------------*/ +/* Enable/disable interrupts */ +/*--------------------------------------------------------------------------*/ +sc_err_t irq_enable(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + ASRT_ERR(group < SC_IRQ_NUM_GROUP, SC_ERR_PARM); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + uint32_t new_mask = mask; + + /* Convert partition-based IRQs */ + if ((group == SC_IRQ_GROUP_WDOG) + || (group == SC_IRQ_GROUP_RTC) + || (group == SC_IRQ_GROUP_SYSCTR)) + { + new_mask = BIT(caller_pt); + } + + /* Enable/disable interrupt */ + err = ss_irq_enable(idx, group, new_mask, enable); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get and clear interrupt status */ +/*--------------------------------------------------------------------------*/ +sc_err_t irq_status(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + ASRT_ERR(group < SC_IRQ_NUM_GROUP, SC_ERR_PARM); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + /* Get and clear interrupt status */ + if (err == SC_ERR_NONE) + { + err = ss_irq_status(idx, group, status); + + /* Convert partition-based IRQs */ + if (err == SC_ERR_NONE) + { + if ((*status != 0U) + && ((group == SC_IRQ_GROUP_WDOG) + || (group == SC_IRQ_GROUP_RTC) + || (group == SC_IRQ_GROUP_SYSCTR))) + { + *status = BIT(0); + } + } + } + + return err; +} + +/*==========================================================================*/ + +/** @} */ + diff --git a/platform/svc/irq/svc.h b/platform/svc/irq/svc.h new file mode 100755 index 0000000..e039b1b --- /dev/null +++ b/platform/svc/irq/svc.h @@ -0,0 +1,81 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/irq/svc.h + * + * Header file containing the API for the System Controller (SC) Interrupt + * (IRQ) function. + * + * @addtogroup IRQ_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_IRQ_SVC_H +#define SC_IRQ_SVC_H + +/* Includes */ + +#include "svc/irq/api.h" +#include "svc/rm/svc.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * Internal SC function to enable/disable interrupts. + * + * @see sc_irq_set_control(). + */ +sc_err_t irq_enable(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t mask, sc_bool_t enable); + +/*! + * Internal SC function to get and clear interrupt status. + * + * @see sc_irq_get_control(). + */ +sc_err_t irq_status(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_irq_group_t group, uint32_t *status); + +#endif /* SC_IRQ_SVC_H */ + +/** @} */ + diff --git a/platform/svc/misc/Makefile b/platform/svc/misc/Makefile new file mode 100755 index 0000000..7a7cb31 --- /dev/null +++ b/platform/svc/misc/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/misc/svc.o + +RPCS += $(OUT)/svc/misc/rpc_srv.o + +RPCL += $(OUT)/svc/misc/rpc_clnt.o + +RPCH += $(SRC)/svc/misc/rpc.h + +RPCC += $(SRC)/svc/misc/rpc_srv.c \ + $(SRC)/svc/misc/rpc_clnt.c \ + $(SRC)/svc/misc/rpc_xlate.c + +RPCHDR += $(SRC)/svc/misc/rpc_header.h + +DIRS += $(OUT)/svc/misc + diff --git a/platform/svc/misc/api.h b/platform/svc/misc/api.h new file mode 100755 index 0000000..cc4d40d --- /dev/null +++ b/platform/svc/misc/api.h @@ -0,0 +1,518 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/misc/api.h + * + * Header file containing the public API for the System Controller (SC) + * Miscellaneous (MISC) function. + * + * @addtogroup MISC_SVC MISC: Miscellaneous Service + * + * @brief Module for the Miscellaneous (MISC) service. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_MISC_API_H +#define SC_MISC_API_H + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/** @{ */ +#define SC_MISC_DMA_GRP_W 5U /*!< Width of sc_misc_dma_group_t */ +/** @} */ + +/*! Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U + +/*! + * @name Defines for sc_misc_boot_status_t + */ +/** @{ */ +#define SC_MISC_BOOT_STATUS_SUCCESS 0U /*!< Success */ +#define SC_MISC_BOOT_STATUS_SECURITY 1U /*!< Security violation */ +/** @} */ + +/*! + * @name Defines for sc_misc_temp_t + */ +/** @{ */ +#define SC_MISC_TEMP 0U /*!< Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /*!< Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /*!< Temp low alarm */ +/** @} */ + +/*! + * @name Defines for sc_misc_bt_t + */ +/** @{ */ +#define SC_MISC_BT_PRIMARY 0U /*!< Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /*!< Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /*!< Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /*!< Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /*!< Serial boot */ +/** @} */ + +/* Types */ + +/*! + * This type is used to store a DMA channel priority group. + */ +typedef uint8_t sc_misc_dma_group_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_boot_status_t; + +/*! + * This type is used report boot status. + */ +typedef uint8_t sc_misc_temp_t; + +/*! + * This type is used report the boot type. + */ +typedef uint8_t sc_misc_bt_t; + +/* Functions */ + +/*! + * @name Control Functions + * @{ + */ + +/*! + * This function sets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to change + * @param[in] val value to apply to the control + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +/* IDL: E8 SET_CONTROL(UI16 resource, UI32 ctrl, UI32 val) #1 */ +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val); + +/*! + * This function gets a miscellaneous control value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[in] ctrl control to get + * @param[out] val pointer to return the control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner + * + * Refer to the [Control List](@ref CONTROLS) for valid control values. + */ +/* IDL: E8 GET_CONTROL(UI16 resource, UI32 ctrl, UO32 val) #2 */ +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val); + +/** @} */ + +/*! + * @name DMA Functions + * @{ + */ + +/*! + * This function configures the max DMA channel priority group for a + * partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a max + * @param[in] max max priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent + * of the affected partition + * + * Valid \a max range is 0-31 with 0 being the lowest and 31 the highest. + * Default is the max priority group for the parent partition of \a pt. + */ +/* IDL: E8 SET_MAX_DMA_GROUP(UI8 pt, UI8 max) #4 */ +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max); + +/*! + * This function configures the priority group for a DMA channel. + * + * @param[in] ipc IPC handle + * @param[in] resource DMA channel resource + * @param[in] group priority group (0-31) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the DMA channel + * + * Valid \a group range is 0-31 with 0 being the lowest and 31 the highest. + * The max value of \a group is limited by the partition max set using + * sc_misc_set_max_dma_group(). + */ +/* IDL: E8 SET_DMA_GROUP(UI16 resource, UI8 group) #5 */ +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group); + +/** @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used output a debug character from the SCU UART. + * + * @param[in] ipc IPC handle + * @param[in] ch character to output + */ +/* IDL: R0 DEBUG_OUT(UI8 ch) #10 */ +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch); + +/*! + * This function starts/stops emulation waveform capture. + * + * @param[in] ipc IPC handle + * @param[in] enable flag to enable/disable capture + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_UNAVAILABLE if not running on emulation + */ +/* IDL: E8 WAVEFORM_CAPTURE(IB enable) #6 */ +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable); + +/*! + * This function is used to return the SCFW build info. + * + * @param[in] ipc IPC handle + * @param[out] build pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +/* IDL: R0 BUILD_INFO(UO32 build, UO32 commit) #15 */ +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, + uint32_t *commit); + +/*! + * This function is used to return the SCFW API versions. + * + * @param[in] ipc IPC handle + * @param[out] cl_maj pointer to return major part of client version + * @param[out] cl_min pointer to return minor part of client version + * @param[out] sv_maj pointer to return major part of SCFW version + * @param[out] sv_min pointer to return minor part of SCFW version + * + * Client version is the version of the API ported to and used by the caller. + * SCFW version is the version of the SCFW binary running on the CPU. + * + * Note a major version difference indicates a break in compatibility. + */ +/* IDL: R0 API_VER(UO16 cl_maj, UO16 cl_min, UO16 sv_maj, UO16 sv_min) #35 */ +void sc_misc_api_ver(sc_ipc_t ipc, uint16_t *cl_maj, + uint16_t *cl_min, uint16_t *sv_maj, uint16_t *sv_min); + +/*! + * This function is used to return the device's unique ID. + * + * @param[in] ipc IPC handle + * @param[out] id_l pointer to return lower 32-bit of ID [31:0] + * @param[out] id_h pointer to return upper 32-bits of ID [63:32] + */ +/* IDL: R0 UNIQUE_ID(UO32 id_l, UO32 id_h) #19 */ +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, + uint32_t *id_h); + +/** @} */ + +/*! + * @name Other Functions + * @{ + */ + +/*! + * This function configures the ARI match value for PCIe/SATA resources. + * + * @param[in] ipc IPC handle + * @param[in] resource match resource + * @param[in] resource_mst PCIe/SATA master to match + * @param[in] ari ARI to match + * @param[in] enable enable match or not + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the owner or parent + * of the owner of the resource and translation + * + * For PCIe, the ARI is the 16-bit value that includes the bus number, + * device number, and function number. For SATA, this value includes the + * FISType and PM_Port. + */ +/* IDL: E8 SET_ARI(UI16 resource, UI16 resource_mst, UI16 ari, IB enable) #3 */ +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable); + +/*! + * This function reports boot status. + * + * @param[in] ipc IPC handle + * @param[in] status boot status + * + * This is used by SW partitions to report status of boot. This is + * normally used to report a boot failure. + */ +/* IDL: RN BOOT_STATUS(UI8 status) #7 */ +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); + +/*! + * This function tells the SCFW that a CPU is done booting. + * + * @param[in] ipc IPC handle + * @param[in] cpu CPU that is done booting + * + * This is called by early booting CPUs to report they are done with + * initialization. After starting early CPUs, the SCFW halts the + * booting process until they are done. During this time, early + * CPUs can call the SCFW with lower latency as the SCFW is idle. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the CPU owner + */ +/* IDL: E8 BOOT_DONE(UI16 cpu) #14 */ +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu); + +/*! + * This function reads a given fuse word index. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[out] val fuse read value + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if read operation failed + * - SC_ERR_LOCKED if read operation is locked + */ +/* IDL: E8 OTP_FUSE_READ(UI32 word, UO32 val) #11 */ +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val); + +/*! + * This function writes a given fuse word index. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] word fuse word index + * @param[in] val fuse write value + * + * The command is passed as is to SECO. SECO uses part of the + * \a word parameter to indicate if the fuse should be locked + * after programming. See the "Write common fuse" section of + * the SECO API Reference Guide for more info. + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * - SC_ERR_NOACCESS if write operation failed + * - SC_ERR_LOCKED if write operation is locked + */ +/* IDL: E8 OTP_FUSE_WRITE(UI32 word, UI32 val) #17 */ +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val); + +/*! + * This function sets a temp sensor alarm. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp alarm to set + * @param[in] celsius whole part of temp to set + * @param[in] tenths fractional part of temp to set + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * This function will enable the alarm interrupt if the temp requested is + * not the min/max temp. This enable automatically clears when the alarm + * occurs and this function has to be called again to re-enable. + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + * - SC_ERR_NOACCESS if caller does not own the resource + * - SC_ERR_NOPOWER if power domain of resource not powered + */ +/* IDL: E8 SET_TEMP(UI16 resource, UI8 temp, I16 celsius, I8 tenths) #12 */ +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); + +/*! + * This function gets a temp sensor value. + * + * @param[in] ipc IPC handle + * @param[in] resource resource with sensor + * @param[in] temp value to get (sensor or alarm) + * @param[out] celsius whole part of temp to get + * @param[out] tenths fractional part of temp to get + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if parameters invalid + * - SC_ERR_BUSY if temp not ready yet (time delay after power on) + * - SC_ERR_NOPOWER if power domain of resource not powered + */ +/* IDL: E8 GET_TEMP(UI16 resource, UI8 temp, O16 celsius, O8 tenths) #13 */ +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths); + +/*! + * This function returns the boot device. + * + * @param[in] ipc IPC handle + * @param[out] dev pointer to return boot device + */ +/* IDL: R0 GET_BOOT_DEV(UO16 dev) #16 */ +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev); + +/*! + * This function returns the boot type. + * + * @param[in] ipc IPC handle + * @param[out] type pointer to return boot type + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors code: + * - SC_ERR_UNAVAILABLE if type not passed by ROM + */ +/* IDL: E8 GET_BOOT_TYPE(UO8 type) #33 */ +sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type); + +/*! + * This function returns the boot container index. + * + * @param[in] ipc IPC handle + * @param[out] idx pointer to return index + * + * Return \a idx = 1 for first container, 2 for second. + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors code: + * - SC_ERR_UNAVAILABLE if index not passed by ROM + */ +/* IDL: E8 GET_BOOT_CONTAINER(UO8 idx) #36 */ +sc_err_t sc_misc_get_boot_container(sc_ipc_t ipc, uint8_t *idx); + +/*! + * This function returns the current status of the ON/OFF button. + * + * @param[in] ipc IPC handle + * @param[out] status pointer to return button status + */ +/* IDL: R0 GET_BUTTON_STATUS(OB status) #18 */ +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); + +/*! + * This function returns the ROM patch checksum. + * + * @param[in] ipc IPC handle + * @param[out] checksum pointer to return checksum + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +/* IDL: E8 ROMPATCH_CHECKSUM(UO32 checksum) #26 */ +sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum); + +/*! + * This function calls the board IOCTL function. + * + * @param[in] ipc IPC handle + * @param[in,out] parm1 pointer to pass parameter 1 + * @param[in,out] parm2 pointer to pass parameter 2 + * @param[in,out] parm3 pointer to pass parameter 3 + * + * @return Returns and error code (SC_ERR_NONE = success). + */ +/* IDL: E8 BOARD_IOCTL(UIO32 parm1, UIO32 parm2, UIO32 parm3) #34 */ +sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3); + +/** @} */ + +#endif /* SC_MISC_API_H */ + +/** @} */ + diff --git a/platform/svc/misc/rpc.h b/platform/svc/misc/rpc.h new file mode 100644 index 0000000..ccdc688 --- /dev/null +++ b/platform/svc/misc/rpc.h @@ -0,0 +1,101 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the MISC RPC implementation. + * + * @addtogroup MISC_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_MISC_RPC_H +#define SC_MISC_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC MISC function calls + */ +/** @{ */ +#define MISC_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define MISC_FUNC_SET_CONTROL 1U /*!< Index for sc_misc_set_control() RPC call */ +#define MISC_FUNC_GET_CONTROL 2U /*!< Index for sc_misc_get_control() RPC call */ +#define MISC_FUNC_SET_MAX_DMA_GROUP 4U /*!< Index for sc_misc_set_max_dma_group() RPC call */ +#define MISC_FUNC_SET_DMA_GROUP 5U /*!< Index for sc_misc_set_dma_group() RPC call */ +#define MISC_FUNC_DEBUG_OUT 10U /*!< Index for sc_misc_debug_out() RPC call */ +#define MISC_FUNC_WAVEFORM_CAPTURE 6U /*!< Index for sc_misc_waveform_capture() RPC call */ +#define MISC_FUNC_BUILD_INFO 15U /*!< Index for sc_misc_build_info() RPC call */ +#define MISC_FUNC_API_VER 35U /*!< Index for sc_misc_api_ver() RPC call */ +#define MISC_FUNC_UNIQUE_ID 19U /*!< Index for sc_misc_unique_id() RPC call */ +#define MISC_FUNC_SET_ARI 3U /*!< Index for sc_misc_set_ari() RPC call */ +#define MISC_FUNC_BOOT_STATUS 7U /*!< Index for sc_misc_boot_status() RPC call */ +#define MISC_FUNC_BOOT_DONE 14U /*!< Index for sc_misc_boot_done() RPC call */ +#define MISC_FUNC_OTP_FUSE_READ 11U /*!< Index for sc_misc_otp_fuse_read() RPC call */ +#define MISC_FUNC_OTP_FUSE_WRITE 17U /*!< Index for sc_misc_otp_fuse_write() RPC call */ +#define MISC_FUNC_SET_TEMP 12U /*!< Index for sc_misc_set_temp() RPC call */ +#define MISC_FUNC_GET_TEMP 13U /*!< Index for sc_misc_get_temp() RPC call */ +#define MISC_FUNC_GET_BOOT_DEV 16U /*!< Index for sc_misc_get_boot_dev() RPC call */ +#define MISC_FUNC_GET_BOOT_TYPE 33U /*!< Index for sc_misc_get_boot_type() RPC call */ +#define MISC_FUNC_GET_BOOT_CONTAINER 36U /*!< Index for sc_misc_get_boot_container() RPC call */ +#define MISC_FUNC_GET_BUTTON_STATUS 18U /*!< Index for sc_misc_get_button_status() RPC call */ +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U /*!< Index for sc_misc_rompatch_checksum() RPC call */ +#define MISC_FUNC_BOARD_IOCTL 34U /*!< Index for sc_misc_board_ioctl() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming MISC RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void misc_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_MISC_RPC_H */ + +/** @} */ + diff --git a/platform/svc/misc/rpc_clnt.c b/platform/svc/misc/rpc_clnt.c new file mode 100644 index 0000000..e455a91 --- /dev/null +++ b/platform/svc/misc/rpc_clnt.c @@ -0,0 +1,661 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the MISC service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup MISC_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "svc/misc/api.h" +#include "../../main/rpc.h" +#include "svc/misc/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 SET_CONTROL(UI16 resource, UI32 ctrl, UI32 val) #1 */ +sc_err_t sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, + uint32_t val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_CONTROL); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U32(&msg, 4U) = U32(val); + RPC_U16(&msg, 8U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_CONTROL(UI16 resource, UI32 ctrl, UO32 val) #2 */ +sc_err_t sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, + uint32_t *val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_CONTROL); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U16(&msg, 4U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (val != NULL) + { + *val = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_MAX_DMA_GROUP(UI8 pt, UI8 max) #4 */ +sc_err_t sc_misc_set_max_dma_group(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_misc_dma_group_t max) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_MAX_DMA_GROUP); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(max); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_DMA_GROUP(UI16 resource, UI8 group) #5 */ +sc_err_t sc_misc_set_dma_group(sc_ipc_t ipc, sc_rsrc_t resource, + sc_misc_dma_group_t group) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_DMA_GROUP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(group); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: R0 DEBUG_OUT(UI8 ch) #10 */ +void sc_misc_debug_out(sc_ipc_t ipc, uint8_t ch) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_DEBUG_OUT); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(ch); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); +} + +/* IDL: E8 WAVEFORM_CAPTURE(IB enable) #6 */ +sc_err_t sc_misc_waveform_capture(sc_ipc_t ipc, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_WAVEFORM_CAPTURE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = B2U8(enable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: R0 BUILD_INFO(UO32 build, UO32 commit) #15 */ +void sc_misc_build_info(sc_ipc_t ipc, uint32_t *build, uint32_t *commit) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BUILD_INFO); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out receive message */ + if (build != NULL) + { + *build = (uint32_t) RPC_U32(&msg, 0U); + } + if (commit != NULL) + { + *commit = (uint32_t) RPC_U32(&msg, 4U); + } +} + +/* IDL: R0 API_VER(UO16 cl_maj, UO16 cl_min, UO16 sv_maj, UO16 sv_min) #35 */ +void sc_misc_api_ver(sc_ipc_t ipc, uint16_t *cl_maj, uint16_t *cl_min, + uint16_t *sv_maj, uint16_t *sv_min) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_API_VER); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out receive message */ + if (cl_maj != NULL) + { + *cl_maj = (uint16_t) SCFW_API_VERSION_MAJOR; + } + if (cl_min != NULL) + { + *cl_min = (uint16_t) SCFW_API_VERSION_MINOR; + } + if (sv_maj != NULL) + { + *sv_maj = (uint16_t) RPC_U16(&msg, 4U); + } + if (sv_min != NULL) + { + *sv_min = (uint16_t) RPC_U16(&msg, 6U); + } +} + +/* IDL: R0 UNIQUE_ID(UO32 id_l, UO32 id_h) #19 */ +void sc_misc_unique_id(sc_ipc_t ipc, uint32_t *id_l, uint32_t *id_h) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_UNIQUE_ID); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out receive message */ + if (id_l != NULL) + { + *id_l = (uint32_t) RPC_U32(&msg, 0U); + } + if (id_h != NULL) + { + *id_h = (uint32_t) RPC_U32(&msg, 4U); + } +} + +/* IDL: E8 SET_ARI(UI16 resource, UI16 resource_mst, UI16 ari, IB enable) #3 */ +sc_err_t sc_misc_set_ari(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_ARI); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U16(&msg, 2U) = U16(resource_mst); + RPC_U16(&msg, 4U) = U16(ari); + RPC_U8(&msg, 6U) = B2U8(enable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RN BOOT_STATUS(UI8 status) #7 */ +void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_STATUS); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(status); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_TRUE); +} + +/* IDL: E8 BOOT_DONE(UI16 cpu) #14 */ +sc_err_t sc_misc_boot_done(sc_ipc_t ipc, sc_rsrc_t cpu) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BOOT_DONE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(cpu); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 OTP_FUSE_READ(UI32 word, UO32 val) #11 */ +sc_err_t sc_misc_otp_fuse_read(sc_ipc_t ipc, uint32_t word, uint32_t *val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_READ); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(word); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (val != NULL) + { + *val = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 OTP_FUSE_WRITE(UI32 word, UI32 val) #17 */ +sc_err_t sc_misc_otp_fuse_write(sc_ipc_t ipc, uint32_t word, uint32_t val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_OTP_FUSE_WRITE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(word); + RPC_U32(&msg, 4U) = U32(val); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_TEMP(UI16 resource, UI8 temp, I16 celsius, I8 tenths) #12 */ +sc_err_t sc_misc_set_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + int16_t celsius, int8_t tenths) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_SET_TEMP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_I16(&msg, 2U) = I16(celsius); + RPC_U8(&msg, 4U) = U8(temp); + RPC_I8(&msg, 5U) = I8(tenths); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_TEMP(UI16 resource, UI8 temp, O16 celsius, O8 tenths) #13 */ +sc_err_t sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, + int16_t *celsius, int8_t *tenths) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_TEMP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(temp); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (celsius != NULL) + { + *celsius = (int16_t) RPC_I16(&msg, 0U); + } + if (tenths != NULL) + { + *tenths = (int8_t) RPC_I8(&msg, 2U); + } + + /* Return result */ + return err; +} + +/* IDL: R0 GET_BOOT_DEV(UO16 dev) #16 */ +void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *dev) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_DEV); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out receive message */ + if (dev != NULL) + { + *dev = (sc_rsrc_t) RPC_U16(&msg, 0U); + } +} + +/* IDL: E8 GET_BOOT_TYPE(UO8 type) #33 */ +sc_err_t sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_TYPE); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (type != NULL) + { + *type = (sc_misc_bt_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 GET_BOOT_CONTAINER(UO8 idx) #36 */ +sc_err_t sc_misc_get_boot_container(sc_ipc_t ipc, uint8_t *idx) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BOOT_CONTAINER); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (idx != NULL) + { + *idx = (uint8_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: R0 GET_BUTTON_STATUS(OB status) #18 */ +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_GET_BUTTON_STATUS); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out receive message */ + if (status != NULL) + { + *status = (sc_bool_t) U2B(RPC_U8(&msg, 0U)); + } +} + +/* IDL: E8 ROMPATCH_CHECKSUM(UO32 checksum) #26 */ +sc_err_t sc_misc_rompatch_checksum(sc_ipc_t ipc, uint32_t *checksum) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_ROMPATCH_CHECKSUM); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (checksum != NULL) + { + *checksum = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 BOARD_IOCTL(UIO32 parm1, UIO32 parm2, UIO32 parm3) #34 */ +sc_err_t sc_misc_board_ioctl(sc_ipc_t ipc, uint32_t *parm1, uint32_t *parm2, + uint32_t *parm3) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = U8(MISC_FUNC_BOARD_IOCTL); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(*parm1); + RPC_U32(&msg, 4U) = U32(*parm2); + RPC_U32(&msg, 8U) = U32(*parm3); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + *parm1 = (uint32_t) RPC_U32(&msg, 0U); + *parm2 = (uint32_t) RPC_U32(&msg, 4U); + *parm3 = (uint32_t) RPC_U32(&msg, 8U); + + /* Return result */ + return err; +} + +/** @} */ + diff --git a/platform/svc/misc/rpc_srv.c b/platform/svc/misc/rpc_srv.c new file mode 100644 index 0000000..baa08b7 --- /dev/null +++ b/platform/svc/misc/rpc_srv.c @@ -0,0 +1,486 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the MISC service. + * + * @addtogroup MISC_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/misc/svc.h" +#include "svc/misc/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void misc_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case MISC_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch set_control() */ + case MISC_FUNC_SET_CONTROL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_ctrl_t ctrl = ((sc_ctrl_t) RPC_U32(msg, 0U)); + uint32_t val = ((uint32_t) RPC_U32(msg, 4U)); + + /* Call function */ + err = misc_set_control(caller_pt, resource, ctrl, val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_control() */ + case MISC_FUNC_GET_CONTROL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 4U)); + sc_ctrl_t ctrl = ((sc_ctrl_t) RPC_U32(msg, 0U)); + uint32_t val = ((uint32_t) 0U); + + /* Call function */ + err = misc_get_control(caller_pt, resource, ctrl, &val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(val); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_max_dma_group() */ + case MISC_FUNC_SET_MAX_DMA_GROUP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_misc_dma_group_t max = ((sc_misc_dma_group_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = misc_set_max_dma_group(caller_pt, pt, max); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_dma_group() */ + case MISC_FUNC_SET_DMA_GROUP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_misc_dma_group_t group = ((sc_misc_dma_group_t) RPC_U8(msg, 2U)); + + /* Call function */ + err = misc_set_dma_group(caller_pt, resource, group); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch debug_out() */ + case MISC_FUNC_DEBUG_OUT : + { + /* Declare return and parameters */ + uint8_t ch = ((uint8_t) RPC_U8(msg, 0U)); + + /* Call function */ + misc_debug_out(caller_pt, ch); + + /* Copy in return parameters */ + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch waveform_capture() */ + case MISC_FUNC_WAVEFORM_CAPTURE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_bool_t enable = U2B(RPC_U8(msg, 0U)); + + /* Call function */ + err = misc_waveform_capture(caller_pt, enable); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch build_info() */ + case MISC_FUNC_BUILD_INFO : + { + /* Declare return and parameters */ + uint32_t build = ((uint32_t) 0U); + uint32_t commit = ((uint32_t) 0U); + + /* Call function */ + misc_build_info(caller_pt, &build, &commit); + + /* Copy in return parameters */ + RPC_U32(msg, 0U) = U32(build); + RPC_U32(msg, 4U) = U32(commit); + RPC_SIZE(msg) = 3U; + break; + } + /* Dispatch api_ver() */ + case MISC_FUNC_API_VER : + { + /* Declare return and parameters */ + uint16_t cl_maj = ((uint16_t) 0U); + uint16_t cl_min = ((uint16_t) 0U); + uint16_t sv_maj = ((uint16_t) 0U); + uint16_t sv_min = ((uint16_t) 0U); + + /* Call function */ + misc_api_ver(caller_pt, &cl_maj, &cl_min, &sv_maj, &sv_min); + + /* Copy in return parameters */ + RPC_U16(msg, 0U) = U16(cl_maj); + RPC_U16(msg, 2U) = U16(cl_min); + RPC_U16(msg, 4U) = U16(sv_maj); + RPC_U16(msg, 6U) = U16(sv_min); + RPC_SIZE(msg) = 3U; + break; + } + /* Dispatch unique_id() */ + case MISC_FUNC_UNIQUE_ID : + { + /* Declare return and parameters */ + uint32_t id_l = ((uint32_t) 0U); + uint32_t id_h = ((uint32_t) 0U); + + /* Call function */ + misc_unique_id(caller_pt, &id_l, &id_h); + + /* Copy in return parameters */ + RPC_U32(msg, 0U) = U32(id_l); + RPC_U32(msg, 4U) = U32(id_h); + RPC_SIZE(msg) = 3U; + break; + } + /* Dispatch set_ari() */ + case MISC_FUNC_SET_ARI : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rsrc_t resource_mst = ((sc_rsrc_t) RPC_U16(msg, 2U)); + uint16_t ari = ((uint16_t) RPC_U16(msg, 4U)); + sc_bool_t enable = U2B(RPC_U8(msg, 6U)); + + /* Call function */ + err = misc_set_ari(caller_pt, resource, resource_mst, ari, + enable); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch boot_status() */ + case MISC_FUNC_BOOT_STATUS : + { + /* Declare return and parameters */ + sc_misc_boot_status_t status = ((sc_misc_boot_status_t) RPC_U8(msg, 0U)); + + /* Call function */ + misc_boot_status(caller_pt, status); + + /* Copy in return parameters */ + RPC_SIZE(msg) = 0U; + break; + } + /* Dispatch boot_done() */ + case MISC_FUNC_BOOT_DONE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t cpu = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + err = misc_boot_done(caller_pt, cpu); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch otp_fuse_read() */ + case MISC_FUNC_OTP_FUSE_READ : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t word = ((uint32_t) RPC_U32(msg, 0U)); + uint32_t val = ((uint32_t) 0U); + + /* Call function */ + err = misc_otp_fuse_read(caller_pt, word, &val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(val); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch otp_fuse_write() */ + case MISC_FUNC_OTP_FUSE_WRITE : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t word = ((uint32_t) RPC_U32(msg, 0U)); + uint32_t val = ((uint32_t) RPC_U32(msg, 4U)); + + /* Call function */ + err = misc_otp_fuse_write(caller_pt, word, val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_temp() */ + case MISC_FUNC_SET_TEMP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_misc_temp_t temp = ((sc_misc_temp_t) RPC_U8(msg, 4U)); + int16_t celsius = ((int16_t) RPC_I16(msg, 2U)); + int8_t tenths = ((int8_t) RPC_I8(msg, 5U)); + + /* Call function */ + err = misc_set_temp(caller_pt, resource, temp, celsius, tenths); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_temp() */ + case MISC_FUNC_GET_TEMP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_misc_temp_t temp = ((sc_misc_temp_t) RPC_U8(msg, 2U)); + int16_t celsius = ((int16_t) 0U); + int8_t tenths = ((int8_t) 0U); + + /* Call function */ + err = misc_get_temp(caller_pt, resource, temp, &celsius, + &tenths); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_I16(msg, 0U) = I16(celsius); + RPC_I8(msg, 2U) = I8(tenths); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch get_boot_dev() */ + case MISC_FUNC_GET_BOOT_DEV : + { + /* Declare return and parameters */ + sc_rsrc_t dev = ((sc_rsrc_t) 0U); + + /* Call function */ + misc_get_boot_dev(caller_pt, &dev); + + /* Copy in return parameters */ + RPC_U16(msg, 0U) = U16(dev); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch get_boot_type() */ + case MISC_FUNC_GET_BOOT_TYPE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_misc_bt_t type = ((sc_misc_bt_t) 0U); + + /* Call function */ + err = misc_get_boot_type(caller_pt, &type); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(type); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch get_boot_container() */ + case MISC_FUNC_GET_BOOT_CONTAINER : + { + /* Declare return and parameters */ + sc_err_t result; + uint8_t idx = ((uint8_t) 0U); + + /* Call function */ + err = misc_get_boot_container(caller_pt, &idx); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(idx); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch get_button_status() */ + case MISC_FUNC_GET_BUTTON_STATUS : + { + /* Declare return and parameters */ + sc_bool_t status = SC_FALSE; + + /* Call function */ + misc_get_button_status(caller_pt, &status); + + /* Copy in return parameters */ + RPC_U8(msg, 0U) = B2U8(status); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch rompatch_checksum() */ + case MISC_FUNC_ROMPATCH_CHECKSUM : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t checksum = ((uint32_t) 0U); + + /* Call function */ + err = misc_rompatch_checksum(caller_pt, &checksum); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(checksum); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch board_ioctl() */ + case MISC_FUNC_BOARD_IOCTL : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t parm1 = ((uint32_t) RPC_U32(msg, 0U)); + uint32_t parm2 = ((uint32_t) RPC_U32(msg, 4U)); + uint32_t parm3 = ((uint32_t) RPC_U32(msg, 8U)); + + /* Call function */ + err = misc_board_ioctl(mu, &parm1, &parm2, &parm3); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(parm1); + RPC_U32(msg, 4U) = U32(parm2); + RPC_U32(msg, 8U) = U32(parm3); + RPC_SIZE(msg) = 4U; + break; + } + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=misc, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=misc, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/misc/svc.c b/platform/svc/misc/svc.c new file mode 100755 index 0000000..0e087ed --- /dev/null +++ b/platform/svc/misc/svc.c @@ -0,0 +1,776 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/misc/svc.c + * + * File containing the implementation of the System Controller (SC) + * Miscellaneous (MISC) function. + * + * @addtogroup MISC_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "main/build_info.h" +#include "svc/misc/svc.h" +#include "svc/rm/svc.h" +#include "ss/inf/inf.h" +#include "drivers/analog/fsl_analog.h" +#include "drivers/otp/fsl_otp.h" + +/* Local Defines */ + +/*! Number of CPU waits */ +#define NUM_WAIT_CPU 2 + +/* Local Types */ + +/*! + * This type is used to store dynamic info needed to track partition + * specific data for the watchdog service. + */ +typedef struct +{ + sc_misc_dma_group_t max_dma_group : SC_MISC_DMA_GRP_W; +} misc_part_data_t; + +/* Local Functions */ + +/* Local Variables */ + +/*! State of CPU waits */ +static volatile sc_bool_t cpu_wait[NUM_WAIT_CPU]; + +/*! + * @name Local Variables (not initialized) + * + * @{ + */ +static misc_part_data_t misc_part_data[SC_RM_NUM_PARTITION]; +/** @} */ + +/*--------------------------------------------------------------------------*/ +/* Init the power management service */ +/*--------------------------------------------------------------------------*/ +void misc_init(sc_bool_t api_phase) +{ + if (api_phase != SC_FALSE) + { + sc_rm_pt_t pt; + + /* Init partition data */ + for (pt = 0; pt < SC_RM_NUM_PARTITION; pt++) + { + misc_part_data[pt].max_dma_group = SC_MISC_DMA_GRP_MAX; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set a miscellaneous control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_set_control(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_sub_t ss; + ss_idx_t ss_idx; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check parameters */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + + if (ss > SC_SUBSYS_LAST) + { + /* Handle board */ + err = board_set_control(resource, ss_idx, idx, ctrl, val); + } + else + { + /* Set control value */ + err = ss_set_control(idx, ctrl, val); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get a miscellaneous control value */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_get_control(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_sub_t ss; + ss_idx_t ss_idx; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + + if (ss > SC_SUBSYS_LAST) + { + /* Handle board */ + err = board_get_control(resource, ss_idx, idx, ctrl, val); + } + else + { + /* Get control value */ + err = ss_get_control(idx, ctrl, val); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the ARI translation for PCIe/SATA resources */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_set_ari(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_rm_idx_t midx = 0; + sc_sub_t ss; + ss_idx_t ss_idx; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_RSRC(resource_mst, midx); + + /* Check parameters */ + ACCESS_ALLOWED(caller_pt, idx); + ACCESS_ALLOWED(caller_pt, midx); + + if (err == SC_ERR_NONE) + { + uint32_t val; + + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(midx, &ss, &ss_idx); + + /* Set using the control interface */ + val = U32(ari); + if (enable != SC_FALSE) + { + val |= BIT(31); + } + + err = ss_set_control(idx, ss_idx, val); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the max DMA channel priority group for a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_set_max_dma_group(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_misc_dma_group_t max) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + ASRT_ERR(rm_is_partition_used(pt), SC_ERR_PARM); + ASRT_ERR(max <= misc_part_data[caller_pt].max_dma_group, SC_ERR_PARM); + ASRT_ERR(rm_is_parent(caller_pt, pt), SC_ERR_NOACCESS); + + if (err == SC_ERR_NONE) + { + /* Set max */ + misc_part_data[pt].max_dma_group = max; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure priority group for a DMA channel */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_set_dma_group(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_misc_dma_group_t group) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check parameters */ + ACCESS_ALLOWED(caller_pt, idx); + ASRT_ERR(group <= misc_part_data[caller_pt].max_dma_group, SC_ERR_PARM); + + if (err == SC_ERR_NONE) + { + /* Set using the control interface */ + err = ss_set_control(idx, SC_C_PRIORITY_GROUP, group); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Start/stop emulation waveform capture */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_waveform_capture(sc_rm_pt_t caller_pt, sc_bool_t enable) +{ + #if defined(EMUL) && !defined(SIMU) + if (enable != SC_FALSE) + { + SystemEventTrigger(SC_ENV_TRIG_DUMP); + } + else + { + SystemEventTrigger(SC_ENV_TRIG_KILL); + } + + return SC_ERR_NONE; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Report boot status */ +/*--------------------------------------------------------------------------*/ +void misc_boot_status(sc_rm_pt_t caller_pt, sc_misc_boot_status_t status) +{ + sc_err_t err = SC_ERR_NONE; + + misc_print(3, "misc_boot_status(%d, %d)\n", caller_pt, status); + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + switch (status) + { + /* Success */ + case SC_MISC_BOOT_STATUS_SUCCESS : + { + misc_print(4, " boot success from %d\n", caller_pt); + pm_set_booted(caller_pt, SC_TRUE); + break; + } + /* Security issue (bad authentication) */ + case SC_MISC_BOOT_STATUS_SECURITY: + { + error_print(" boot security violation from %d\n", caller_pt); + pm_set_booted(caller_pt, SC_FALSE); + break; + } + /* Unknown */ + default : + { + misc_print(4, " unknown boot reason from %d\n", caller_pt); + pm_set_booted(caller_pt, SC_FALSE); + break; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Exit early boot */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_boot_done(sc_rm_pt_t caller_pt, sc_rsrc_t cpu) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx; + + misc_print(3, "misc_boot_done(%d, %d)\n", caller_pt, cpu); + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(cpu, idx); + + /* Check parameters */ + ASRT_ERR(rm_is_ridx_owned(caller_pt, idx), SC_ERR_NOACCESS); + + if (err == SC_ERR_NONE) + { + /* Calculate CPU index */ + if (cpu == SC_R_MCU_0_PID0) + { + cpu_wait[0U] = SC_TRUE; + } + else if (cpu == SC_R_MCU_1_PID0) + { + cpu_wait[1U] = SC_TRUE; + } + else + { + err = SC_ERR_PARM; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Wait for CPU boot to be done */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_boot_done_wait(sc_rsrc_t cpu) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx; + + misc_print(3, "misc_boot_done_wait(%d)\n", cpu); + + /* Calculate CPU index */ + if (cpu == SC_R_MCU_0_PID0) + { + idx = 0U; + } + else if (cpu == SC_R_MCU_1_PID0) + { + idx = 1U; + } + else + { + err = SC_ERR_PARM; + } + + if (err == SC_ERR_NONE) + { + /* Wait for CPU to finish */ + while (cpu_wait[idx] == SC_FALSE) + { + ; /* Intentional empty while */ + } + + /* Clear flag */ + cpu_wait[idx]= SC_FALSE; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Output a debug character */ +/*--------------------------------------------------------------------------*/ +void misc_debug_out(sc_rm_pt_t caller_pt, uint8_t ch) +{ + always_print("%c", ch); +} + +/*--------------------------------------------------------------------------*/ +/* OTP MISC read fuse */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_otp_fuse_read(sc_rm_pt_t caller_pt, uint32_t word, + uint32_t *val) +{ + #ifndef NO_DEVICE_ACCESS + return (OTP_Get_Fuse(word, val)); + #else + return SC_ERR_NONE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* OTP MISC write fuse */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_otp_fuse_write(sc_rm_pt_t caller_pt, uint32_t word, + uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check access permissions */ + SYSTEM(caller_pt); + + if (err == SC_ERR_NONE) + { + #ifndef NO_DEVICE_ACCESS + err = OTP_Write(OTP, word, &val); + #endif + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Return temp sensor availabilty */ +/*--------------------------------------------------------------------------*/ +sc_bool_t misc_has_temp(sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0; + sc_sub_t ss; + ss_idx_t ss_idx; + uint32_t val; + + /* Bounds check */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + + if (ss > SC_SUBSYS_LAST) + { + /* Handle board */ + rtn = (board_get_control(resource, ss_idx, idx, SC_C_TEMP, &val) + == SC_ERR_NONE); + } + else + { + /* Call subsystem interface */ + rtn = ss_temp_sensor(idx); + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Set a temp sensor alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_set_temp(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + uint32_t val = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check parameters */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + /* Convert temp */ + if ((resource == SC_R_PMIC_0) || (resource == SC_R_PMIC_1) + || (resource == SC_R_PMIC_2)) + { + val = U32(celsius); + } + else + { + sc_sub_t ss = 0; + ss_idx_t ss_idx = 0; + + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + ANA_Temp2Val(sc_ss_info[ss].dsc, celsius, tenths, &val); + } + + /* Set temp */ + switch (temp) + { + case SC_MISC_TEMP : + err = misc_set_control(caller_pt, resource, SC_C_TEMP, + val); + break; + case SC_MISC_TEMP_HIGH : + err = misc_set_control(caller_pt, resource, SC_C_TEMP_HI, + val); + break; + case SC_MISC_TEMP_LOW : + err = misc_set_control(caller_pt, resource, SC_C_TEMP_LOW, + val); + break; + default : + err = SC_ERR_PARM; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get a temp sensor value */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_get_temp(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + uint32_t val; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Get temp */ + if (err == SC_ERR_NONE) + { + switch (temp) + { + /* Sensor temp */ + case SC_MISC_TEMP : + err = misc_get_control(caller_pt, resource, SC_C_TEMP, + &val); + break; + /* High temp alarm */ + case SC_MISC_TEMP_HIGH : + err = misc_get_control(caller_pt, resource, SC_C_TEMP_HI, + &val); + break; + /* Low temp alarm */ + case SC_MISC_TEMP_LOW : + err = misc_get_control(caller_pt, resource, SC_C_TEMP_LOW, + &val); + break; + /* Bad control */ + default : + err = SC_ERR_PARM; + break; + } + } + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Convert temp */ + if ((resource == SC_R_PMIC_0) || (resource == SC_R_PMIC_1) + || (resource == SC_R_PMIC_2)) + { + *celsius = I16(val); + *tenths = 0; + } + else + { + sc_sub_t ss = 0; + ss_idx_t ss_idx = 0; + + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + ANA_Val2Temp(sc_ss_info[ss].dsc, val, celsius, tenths); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Return SCFW build info */ +/*--------------------------------------------------------------------------*/ +void misc_build_info(sc_rm_pt_t caller_pt, uint32_t *build, + uint32_t *commit) +{ + /* Return info */ + *build = SCFW_BUILD; + *commit = SCFW_COMMIT; +} + +/*--------------------------------------------------------------------------*/ +/* Return unique ID */ +/*--------------------------------------------------------------------------*/ +void misc_unique_id(sc_rm_pt_t caller_pt, uint32_t *id_l, + uint32_t *id_h) +{ + *id_l = OTP_UNIQUE_ID_L; + *id_h = OTP_UNIQUE_ID_H; +} + +/*--------------------------------------------------------------------------*/ +/* Return boot device */ +/*--------------------------------------------------------------------------*/ +void misc_get_boot_dev(sc_rm_pt_t caller_pt, sc_rsrc_t *dev) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + *dev = boot_get_dev(caller_pt, SC_FALSE); + } +} + +/*--------------------------------------------------------------------------*/ +/* Return boot type */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_get_boot_type(sc_rm_pt_t caller_pt, sc_misc_bt_t *type) +{ + sc_err_t err; + sc_bt_dev_type_t dev_type; + uint8_t inst; + sc_bt_type_t bt_type; + + /* Get boot device */ + err = boot_get_boot_dev(&dev_type, &inst, &bt_type); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Translate ROM type */ + switch (bt_type) + { + case SC_BT_TYPE_PRIMARY : + *type = SC_MISC_BT_PRIMARY; + break; + case SC_BT_TYPE_RECOVERY: + *type = SC_MISC_BT_RECOVERY; + break; + case SC_BT_TYPE_SECONDARY: + *type = SC_MISC_BT_SECONDARY; + break; + case SC_BT_TYPE_SERIAL: + *type = SC_MISC_BT_SERIAL; + break; + /* Not found */ + default : + err = SC_ERR_UNAVAILABLE; + break; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Return the boot container index */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_get_boot_container(sc_rm_pt_t caller_pt, uint8_t *idx) +{ + return boot_get_container_idx(idx); +} + +/*--------------------------------------------------------------------------*/ +/* Return the current status of the ON/OFF button */ +/*--------------------------------------------------------------------------*/ +void misc_get_button_status(sc_rm_pt_t caller_pt, sc_bool_t *status) +{ + *status = board_get_button_status(); +} + +/*--------------------------------------------------------------------------*/ +/* Return the ROM patch checksum */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_rompatch_checksum(sc_rm_pt_t caller_pt, uint32_t *checksum) +{ + soc_rompatch_checksum(checksum, OTP_ROM_PATCH_SIZE + + OTP_V2X_PATCH_SIZE); + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Call board IOCTL */ +/*--------------------------------------------------------------------------*/ +sc_err_t misc_board_ioctl(sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_pt_t caller_pt; + + err = rm_get_resource_owner(SC_PT, mu, &caller_pt); + + if (err == SC_ERR_NONE) + { + err = board_ioctl(caller_pt, mu, parm1, parm2, parm3); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Return API version info */ +/*--------------------------------------------------------------------------*/ +void misc_api_ver(sc_rm_pt_t caller_pt, uint16_t *cl_maj, + uint16_t *cl_min, uint16_t *sv_maj, uint16_t *sv_min) +{ + *cl_maj = 0U; + *cl_min = 0U; + *sv_maj = SCFW_API_VERSION_MAJOR; + *sv_min = SCFW_API_VERSION_MINOR; +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Dump MISC state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) && defined(DEBUG_MISC) + void misc_dump(sc_rm_pt_t pt) + { + sc_err_t err = SC_ERR_NONE; + + USED_PT(pt); + + if ((debug != SC_FALSE) && (err == SC_ERR_NONE)) + { + /* Dump data */ + misc_print(2, " Partition: %u\n", pt); + misc_print(2, " Max DMA priority group: %u\n", + misc_part_data[pt].max_dma_group); + } + } +#endif + +/** @} */ + diff --git a/platform/svc/misc/svc.h b/platform/svc/misc/svc.h new file mode 100755 index 0000000..50bca96 --- /dev/null +++ b/platform/svc/misc/svc.h @@ -0,0 +1,288 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/misc/svc.h + * + * Header file containing the API for the System Controller (SC) + * Miscellaneous (MISC) function. + * + * @addtogroup MISC_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_MISC_SVC_H +#define SC_MISC_SVC_H + +/* Includes */ + +#include "svc/misc/api.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * @name Internal Functions + * @{ + */ + +/*! + * Internal SC function to initializes the MISC service. + * + * @param[in] api_phase init phase + * + * Initializes the API if /a api_phase = SC_TRUE, otherwise initializes the HW + * managed by the MISC service. API must be initialized before anything else is + * done with the service. + */ +void misc_init(sc_bool_t api_phase); + +/*! + * Internal SC function to set a miscellaneous control value. + * + * @see sc_misc_set_control(). + */ +sc_err_t misc_set_control(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t val); + +/*! + * Internal SC function to get a miscellaneous control value. + * + * @see sc_misc_get_control(). + */ +sc_err_t misc_get_control(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_ctrl_t ctrl, uint32_t *val); + +/*! + * Internal SC function to configure the ARI translation for + * PCIe/SATA resources. + * + * @see sc_misc_set_ari(). + */ +sc_err_t misc_set_ari(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rsrc_t resource_mst, uint16_t ari, sc_bool_t enable); + +/*! + * Internal SC function to configure max DMA channel priority + * group for a partition. + * + * @see sc_misc_set_max_dma_group(). + */ +sc_err_t misc_set_max_dma_group(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_misc_dma_group_t max); + +/*! + * Internal SC function to configure the priority group for a + * DMA channel. + * + * @see sc_misc_set_dma_group(). + */ +sc_err_t misc_set_dma_group(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_misc_dma_group_t group); + +/*! + * Internal SC function to report boot status. + * + * @see sc_misc_boot_status(). + */ +void misc_boot_status(sc_rm_pt_t caller_pt, sc_misc_boot_status_t status); + +/*! + * Internal SC function to report a CPU has finished initialization. + * + * @see sc_misc_boot_done(). + */ +sc_err_t misc_boot_done(sc_rm_pt_t caller_pt, sc_rsrc_t cpu); + +/*! + * Internal SC function to wait for a CPU to be done booting. + * + * @param[in] cpu CPU to wait for + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t misc_boot_done_wait(sc_rsrc_t cpu); + +/*! + * Internal SC function to start/stop emulation waveform capture. + * + * @see sc_misc_waveform_capture(). + */ +sc_err_t misc_waveform_capture(sc_rm_pt_t caller_pt, sc_bool_t enable); + +/*! + * Internal SC function to output a debug charcter. + * + * @see sc_misc_debug_out(). + */ +void misc_debug_out(sc_rm_pt_t caller_pt, uint8_t ch); + +/*! + * Internal SC function to read otp fuse word + * + * @see sc_misc_otp_fuse_read(). + */ +sc_err_t misc_otp_fuse_read(sc_rm_pt_t caller_pt, + uint32_t word, uint32_t *val); + +/*! + * Internal SC function to write otp fuse word + * + * @see sc_misc_otp_fuse_write(). + */ +sc_err_t misc_otp_fuse_write(sc_rm_pt_t caller_pt, + uint32_t word, uint32_t val); + +/*! + * This function reports if a resource has a temp sensor. + * + * @param[in] resource resource to querry + * + * @return Returns SC_TRUE if the subsystem containing + * /a resource has a temp sensor. + */ +sc_bool_t misc_has_temp(sc_rsrc_t resource); + +/*! + * Internal SC function to set a temp sensor alarm + * + * @see sc_misc_set_temp(). + */ +sc_err_t misc_set_temp(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t celsius, int8_t tenths); + +/*! + * Internal SC function to get a temp sensor value + * + * @see sc_misc_get_temp(). + */ +sc_err_t misc_get_temp(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_misc_temp_t temp, int16_t *celsius, int8_t *tenths); + +/*! + * Internal SC function to return SCFW build info + * + * @see sc_misc_build_info(). + */ +void misc_build_info(sc_rm_pt_t caller_pt, uint32_t *build, + uint32_t *commit); + +/*! + * Internal SC function to return the device unique ID + * + * @see sc_misc_unique_id(). + */ +void misc_unique_id(sc_rm_pt_t caller_pt, uint32_t *id_l, + uint32_t *id_h); + +/*! + * Internal SC function to return the boot device + * + * @see sc_misc_get_boot_dev(). + */ +void misc_get_boot_dev(sc_rm_pt_t caller_pt, sc_rsrc_t *dev); + +/*! + * Internal SC function to return the boot type + * + * @see sc_misc_get_boot_type(). + */ +sc_err_t misc_get_boot_type(sc_rm_pt_t caller_pt, sc_misc_bt_t *type); + +/*! + * Internal SC function to return the boot container index + * + * @see sc_misc_get_boot_containere(). + */ +sc_err_t misc_get_boot_container(sc_rm_pt_t caller_pt, uint8_t *idx); + +/*! + * Internal SC function to return the current status of the ON/OFF button + * + * @see sc_misc_get_button_status(). + */ +void misc_get_button_status(sc_rm_pt_t caller_pt, sc_bool_t *status); + +/*! + * Internal SC function to return the ROM patch checksum + * + * @see sc_misc_rompatch_checksum(). + */ +sc_err_t misc_rompatch_checksum(sc_rm_pt_t caller_pt, uint32_t *checksum); + +/*! + * Internal SC function to call board IOCTL + * + * @see sc_misc_board_ioctl(). + */ +sc_err_t misc_board_ioctl(sc_rsrc_t mu, uint32_t *parm1, + uint32_t *parm2, uint32_t *parm3); + +/*! + * Internal SC function to return API version info + * + * @see sc_misc_api_ver(). + */ +void misc_api_ver(sc_rm_pt_t caller_pt, uint16_t *cl_maj, + uint16_t *cl_min, uint16_t *sv_maj, uint16_t *sv_min); + +/** @} */ + +#if defined(DEBUG) && defined(DEBUG_MISC) + /*! + * @name Debug Functions + * @{ + */ + + /*! + * Internal SC function to dump the internal state of the MISC service. + * + * @param[in] pt partition to dump + */ + void misc_dump(sc_rm_pt_t pt); + + /** @} */ +#endif + + +#endif /* SC_MISC_SVC_H */ + +/** @} */ + diff --git a/platform/svc/pad/Makefile b/platform/svc/pad/Makefile new file mode 100755 index 0000000..bc6affe --- /dev/null +++ b/platform/svc/pad/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/pad/svc.o + +RPCS += $(OUT)/svc/pad/rpc_srv.o + +RPCL += $(OUT)/svc/pad/rpc_clnt.o + +RPCH += $(SRC)/svc/pad/rpc.h + +RPCC += $(SRC)/svc/pad/rpc_srv.c \ + $(SRC)/svc/pad/rpc_clnt.c \ + $(SRC)/svc/pad/rpc_xlate.c + +RPCHDR += $(SRC)/svc/pad/rpc_header.h + +DIRS += $(OUT)/svc/pad + diff --git a/platform/svc/pad/api.h b/platform/svc/pad/api.h new file mode 100755 index 0000000..344da2b --- /dev/null +++ b/platform/svc/pad/api.h @@ -0,0 +1,640 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/pad/api.h + * + * Header file containing the public API for the System Controller (SC) + * Pad Control (PAD) function. + * + * @addtogroup PAD_SVC PAD: Pad Service + * + * @brief Module for the Pad Control (PAD) service. + * + * @details + * + * Pad configuration is managed by SC firmware. The pad configuration + * features supported by the SC firmware include: + * + * - Configuring the mux, input/output connection, and low-power isolation + mode. + * - Configuring the technology-specific pad setting such as drive strength, + * pullup/pulldown, etc. + * - Configuring compensation for pad groups with dual voltage capability. + * + * Pad functions fall into one of three categories. Generic functions are + * common to all SoCs and all process technologies. SoC functions are raw + * low-level functions. Technology-specific functions are specific to the + * process technology. + * + * The list of pads is SoC specific. Refer to the SoC [Pad List](@ref PADS) + * for valid pad values. Note that all pads exist on a die but may or + * may not be brought out by the specific package. Mapping of pads to + * package pins/balls is documented in the associated Data Sheet. Some pads + * may not be brought out because the part (die+package) is defeatured and + * some pads may connect to the substrate in the package. + * + * Some pads (SC_P_COMP_*) that can be specified are not individual pads + * but are in fact pad groups. These groups have additional configuration + * that can be done using the sc_pad_set_gp_28fdsoi_comp() function. More + * info on these can be found in the associated Reference Manual. + * + * Pads are managed as a resource by the Resource Manager (RM). They have + * assigned owners and only the owners can configure the pads. Some of the + * pads are reserved for use by the SCFW itself and this can be overridden + * with the implementation of board_config_sc(). Additionally, pads may + * be assigned to various other partitions via the implementation of + * board_system_config(). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * @includedoc pad/details.dox + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_PAD_API_H +#define SC_PAD_API_H + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/** @{ */ +#define SC_PAD_MUX_W 3U /*!< Width of mux parameter */ +/** @} */ + +/*! + * @name Defines for sc_pad_config_t + */ +/** @{ */ +#define SC_PAD_CONFIG_NORMAL 0U /*!< Normal */ +#define SC_PAD_CONFIG_OD 1U /*!< Open Drain */ +#define SC_PAD_CONFIG_OD_IN 2U /*!< Open Drain and input */ +#define SC_PAD_CONFIG_OUT_IN 3U /*!< Output and input */ +/** @} */ + +/*! + * @name Defines for sc_pad_iso_t + */ +/** @{ */ +#define SC_PAD_ISO_OFF 0U /*!< ISO latch is transparent */ +#define SC_PAD_ISO_EARLY 1U /*!< Follow EARLY_ISO */ +#define SC_PAD_ISO_LATE 2U /*!< Follow LATE_ISO */ +#define SC_PAD_ISO_ON 3U /*!< ISO latched data is held */ +/** @} */ + +/*! + * @name Defines for sc_pad_wakeup_t + */ +/** @{ */ +#define SC_PAD_WAKEUP_OFF 0U /*!< Off */ +#define SC_PAD_WAKEUP_CLEAR 1U /*!< Clears pending flag */ +#define SC_PAD_WAKEUP_LOW_LVL 4U /*!< Low level */ +#define SC_PAD_WAKEUP_FALL_EDGE 5U /*!< Falling edge */ +#define SC_PAD_WAKEUP_RISE_EDGE 6U /*!< Rising edge */ +#define SC_PAD_WAKEUP_HIGH_LVL 7U /*!< High-level */ +/** @} */ + +/*! + * @name Defines for sc_pad_28fdsoi_dse_t + */ +/** @{ */ +#define SC_PAD_28FDSOI_DSE_18V_1MA 0U /*!< Drive strength of 1mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_2MA 1U /*!< Drive strength of 2mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_4MA 2U /*!< Drive strength of 4mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_6MA 3U /*!< Drive strength of 6mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_8MA 4U /*!< Drive strength of 8mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_10MA 5U /*!< Drive strength of 10mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_12MA 6U /*!< Drive strength of 12mA for 1.8v */ +#define SC_PAD_28FDSOI_DSE_18V_HS 7U /*!< High-speed drive strength for 1.8v */ +#define SC_PAD_28FDSOI_DSE_33V_2MA 0U /*!< Drive strength of 2mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_4MA 1U /*!< Drive strength of 4mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_8MA 2U /*!< Drive strength of 8mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_33V_12MA 3U /*!< Drive strength of 12mA for 3.3v */ +#define SC_PAD_28FDSOI_DSE_DV_HIGH 0U /*!< High drive strength for dual volt */ +#define SC_PAD_28FDSOI_DSE_DV_LOW 1U /*!< Low drive strength for dual volt */ +/** @} */ + +/*! + * @name Defines for sc_pad_28fdsoi_ps_t + */ +/** @{ */ +#define SC_PAD_28FDSOI_PS_KEEPER 0U /*!< Bus-keeper (only valid for 1.8v) */ +#define SC_PAD_28FDSOI_PS_PU 1U /*!< Pull-up */ +#define SC_PAD_28FDSOI_PS_PD 2U /*!< Pull-down */ +#define SC_PAD_28FDSOI_PS_NONE 3U /*!< No pull (disabled) */ +/** @} */ + +/*! + * @name Defines for sc_pad_28fdsoi_pus_t + */ +/** @{ */ +#define SC_PAD_28FDSOI_PUS_30K_PD 0U /*!< 30K pull-down */ +#define SC_PAD_28FDSOI_PUS_100K_PU 1U /*!< 100K pull-up */ +#define SC_PAD_28FDSOI_PUS_3K_PU 2U /*!< 3K pull-up */ +#define SC_PAD_28FDSOI_PUS_30K_PU 3U /*!< 30K pull-up */ +/** @} */ + +/* Types */ + +/*! + * This type is used to declare a pad config. It determines how the + * output data is driven, pull-up is controlled, and input signal is + * connected. Normal and OD are typical and only connect the input + * when the output is not driven. The IN options are less common and + * force an input connection even when driving the output. + */ +typedef uint8_t sc_pad_config_t; + +/*! + * This type is used to declare a pad low-power isolation config. + * ISO_LATE is the most common setting. ISO_EARLY is only used when + * an output pad is directly determined by another input pad. The + * other two are only used when SW wants to directly control isolation. + */ +typedef uint8_t sc_pad_iso_t; + +/*! + * This type is used to declare a wakeup mode of a pad. + */ +typedef uint8_t sc_pad_wakeup_t; + +/*! + * This type is used to declare a drive strength. Note it is specific + * to 28FDSOI. Also note that valid values depend on the pad type. + */ +typedef uint8_t sc_pad_28fdsoi_dse_t; + +/*! + * This type is used to declare a pull select. Note it is specific + * to 28FDSOI. + */ +typedef uint8_t sc_pad_28fdsoi_ps_t; + +/*! + * This type is used to declare a pull-up select. Note it is specific + * to 28FDSOI HSIC pads. + */ +typedef uint8_t sc_pad_28fdsoi_pus_t; + +/* Functions */ + +/*! + * @name Generic Functions + * @{ + */ + +/*! + * This function configures the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET_MUX(UI16 pad, UI8 mux, UI8 config, UI8 iso) #1 */ +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso); + +/*! + * This function gets the mux settings for a pad. This includes + * the signal mux, pad config, and low-power isolation mode. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_MUX(UI16 pad, UO8 mux, UO8 config, UO8 iso) #6 */ +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso); + +/*! + * This function configures the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] ctrl control value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET_GP(UI16 pad, UI32 ctrl) #2 */ +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl); + +/*! + * This function gets the general purpose pad control. This + * is technology dependent and includes things like drive strength, + * slew rate, pull up/down, etc. Refer to the SoC Reference Manual + * for bit field details. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] ctrl pointer to return control value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_GP(UI16 pad, UO32 ctrl) #7 */ +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl); + +/*! + * This function configures the wakeup mode of the pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] wakeup wakeup to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET_WAKEUP(UI16 pad, UI8 wakeup) #4 */ +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets the wakeup mode of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] wakeup pointer to return wakeup + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_WAKEUP(UI16 pad, UO8 wakeup) #9 */ +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_wakeup_t *wakeup); + +/*! + * This function configures a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * @param[in] ctrl control value + * @param[in] wakeup wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note muxing two input pads to the same IP functional signal will + * result in undefined behavior. + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET_ALL(UI16 pad, UI8 mux, UI8 config, UI8 iso, UI32 ctrl, UI8 wakeup) #5 */ +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup); + +/*! + * This function gets a pad's config. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] mux pointer to return mux setting + * @param[out] config pointer to return pad config + * @param[out] iso pointer to return low-power isolation mode + * @param[out] ctrl pointer to return control value + * @param[out] wakeup pointer to return wakeup to set + * + * @see sc_pad_set_mux(). + * @see sc_pad_set_gp(). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_ALL(UI16 pad, UO8 mux, UO8 config, UO8 iso, UO32 ctrl, UO8 wakeup) #10 */ +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup); + +/** @} */ + +/*! + * @name SoC Specific Functions + * @{ + */ + +/*! + * This function configures the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] val value to set + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET(UI16 pad, UI32 val) #15 */ +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val); + +/*! + * This function gets the settings for a pad. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] val pointer to return setting + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET(UI16 pad, UO32 val) #16 */ +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); + +/*! + * This function writes a configuration register. This setting is SoC + * specific. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] val value to set + * + * Use to configure various HSIC and NAND congiruation settings. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 CONFIG(UI16 pad, UI32 val) #17 */ +sc_err_t sc_pad_config(sc_ipc_t ipc, sc_pad_t pad, uint32_t val); + +/** @} */ + +/*! + * @name 28FDSIO Technology Specific Functions + * @{ + */ + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] ps pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_NOTFOUND if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET_GP_28FDSOI(UI16 pad, UI8 dse, UI8 ps) #11 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] ps pointer to return pull select + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_NOTFOUND if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_GP_28FDSOI(UI16 pad, UO8 dse, UO8 ps) #12 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps); + +/*! + * This function configures the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] dse drive strength + * @param[in] hys hysteresis + * @param[in] pus pull-up select + * @param[in] pke pull keeper enable + * @param[in] pue pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_NOTFOUND if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 SET_GP_28FDSOI_HSIC(UI16 pad, UI8 dse, IB hys, UI8 pus, IB pke, IB pue) #3 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue); + +/*! + * This function gets the pad control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] dse pointer to return drive strength + * @param[out] hys pointer to return hysteresis + * @param[out] pus pointer to return pull-up select + * @param[out] pke pointer to return pull keeper enable + * @param[out] pue pointer to return pull-up enable + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_NOTFOUND if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_GP_28FDSOI_HSIC(UI16 pad, UO8 dse, OB hys, UO8 pus, OB pke, OB pue) #8 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue); + +/*! + * This function configures the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to configure + * @param[in] compen compensation/freeze mode + * @param[in] fastfrz fast freeze + * @param[in] rasrcp compensation code for PMOS + * @param[in] rasrcn compensation code for NMOS + * @param[in] nasrc_sel NASRC read select + * @param[in] psw_ovr 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_NOTFOUND if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + * + * Note \a psw_ovr is only applicable to pads supporting 2.5 volt + * operation (e.g. some Ethernet pads). + */ +/* IDL: E8 SET_GP_28FDSOI_COMP(UI16 pad, UI8 compen, IB fastfrz, UI8 rasrcp, UI8 rasrcn, IB nasrc_sel, IB psw_ovr) #13 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); + +/*! + * This function gets the compensation control specific to 28FDSOI. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to query + * @param[out] compen pointer to return compensation/freeze mode + * @param[out] fastfrz pointer to return fast freeze + * @param[out] rasrcp pointer to return compensation code for PMOS + * @param[out] rasrcn pointer to return compensation code for NMOS + * @param[out] nasrc_sel pointer to return NASRC read select + * @param[out] compok pointer to return compensation status + * @param[out] nasrc pointer to return NASRCP/NASRCN + * @param[out] psw_ovr pointer to return the 2.5v override + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner, + * - SC_ERR_NOTFOUND if process not applicable + * + * Refer to the SoC [Pad List](@ref PADS) for valid pad values. + */ +/* IDL: E8 GET_GP_28FDSOI_COMP(UI16 pad, UO8 compen, OB fastfrz, UO8 rasrcp, UO8 rasrcn, OB nasrc_sel, OB compok, UO8 nasrc, OB psw_ovr) #14 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr); + +/** @} */ + +#endif /* SC_PAD_API_H */ + +/** @} */ + diff --git a/platform/svc/pad/rpc.h b/platform/svc/pad/rpc.h new file mode 100644 index 0000000..4105fd6 --- /dev/null +++ b/platform/svc/pad/rpc.h @@ -0,0 +1,96 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the PAD RPC implementation. + * + * @addtogroup PAD_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_PAD_RPC_H +#define SC_PAD_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC PAD function calls + */ +/** @{ */ +#define PAD_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define PAD_FUNC_SET_MUX 1U /*!< Index for sc_pad_set_mux() RPC call */ +#define PAD_FUNC_GET_MUX 6U /*!< Index for sc_pad_get_mux() RPC call */ +#define PAD_FUNC_SET_GP 2U /*!< Index for sc_pad_set_gp() RPC call */ +#define PAD_FUNC_GET_GP 7U /*!< Index for sc_pad_get_gp() RPC call */ +#define PAD_FUNC_SET_WAKEUP 4U /*!< Index for sc_pad_set_wakeup() RPC call */ +#define PAD_FUNC_GET_WAKEUP 9U /*!< Index for sc_pad_get_wakeup() RPC call */ +#define PAD_FUNC_SET_ALL 5U /*!< Index for sc_pad_set_all() RPC call */ +#define PAD_FUNC_GET_ALL 10U /*!< Index for sc_pad_get_all() RPC call */ +#define PAD_FUNC_SET 15U /*!< Index for sc_pad_set() RPC call */ +#define PAD_FUNC_GET 16U /*!< Index for sc_pad_get() RPC call */ +#define PAD_FUNC_CONFIG 17U /*!< Index for sc_pad_config() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI 11U /*!< Index for sc_pad_set_gp_28fdsoi() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI 12U /*!< Index for sc_pad_get_gp_28fdsoi() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI_HSIC 3U /*!< Index for sc_pad_set_gp_28fdsoi_hsic() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI_HSIC 8U /*!< Index for sc_pad_get_gp_28fdsoi_hsic() RPC call */ +#define PAD_FUNC_SET_GP_28FDSOI_COMP 13U /*!< Index for sc_pad_set_gp_28fdsoi_comp() RPC call */ +#define PAD_FUNC_GET_GP_28FDSOI_COMP 14U /*!< Index for sc_pad_get_gp_28fdsoi_comp() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming PAD RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void pad_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_PAD_RPC_H */ + +/** @} */ + diff --git a/platform/svc/pad/rpc_clnt.c b/platform/svc/pad/rpc_clnt.c new file mode 100644 index 0000000..0d645b5 --- /dev/null +++ b/platform/svc/pad/rpc_clnt.c @@ -0,0 +1,651 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the PAD service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup PAD_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "svc/pad/api.h" +#include "../../main/rpc.h" +#include "svc/pad/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 SET_MUX(UI16 pad, UI8 mux, UI8 config, UI8 iso) #1 */ +sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_MUX); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(mux); + RPC_U8(&msg, 3U) = U8(config); + RPC_U8(&msg, 4U) = U8(iso); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_MUX(UI16 pad, UO8 mux, UO8 config, UO8 iso) #6 */ +sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_MUX); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mux != NULL) + { + *mux = (uint8_t) RPC_U8(&msg, 0U); + } + if (config != NULL) + { + *config = (sc_pad_config_t) RPC_U8(&msg, 1U); + } + if (iso != NULL) + { + *iso = (sc_pad_iso_t) RPC_U8(&msg, 2U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_GP(UI16 pad, UI32 ctrl) #2 */ +sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t ctrl) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U16(&msg, 4U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_GP(UI16 pad, UO32 ctrl) #7 */ +sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pad_t pad, uint32_t *ctrl) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (ctrl != NULL) + { + *ctrl = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_WAKEUP(UI16 pad, UI8 wakeup) #4 */ +sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t wakeup) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_WAKEUP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(wakeup); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_WAKEUP(UI16 pad, UO8 wakeup) #9 */ +sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pad_t pad, sc_pad_wakeup_t *wakeup) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_WAKEUP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (wakeup != NULL) + { + *wakeup = (sc_pad_wakeup_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_ALL(UI16 pad, UI8 mux, UI8 config, UI8 iso, UI32 ctrl, UI8 wakeup) #5 */ +sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_ALL); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(ctrl); + RPC_U16(&msg, 4U) = U16(pad); + RPC_U8(&msg, 6U) = U8(mux); + RPC_U8(&msg, 7U) = U8(config); + RPC_U8(&msg, 8U) = U8(iso); + RPC_U8(&msg, 9U) = U8(wakeup); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_ALL(UI16 pad, UO8 mux, UO8 config, UO8 iso, UO32 ctrl, UO8 wakeup) #10 */ +sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_ALL); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (ctrl != NULL) + { + *ctrl = (uint32_t) RPC_U32(&msg, 0U); + } + if (mux != NULL) + { + *mux = (uint8_t) RPC_U8(&msg, 4U); + } + if (config != NULL) + { + *config = (sc_pad_config_t) RPC_U8(&msg, 5U); + } + if (iso != NULL) + { + *iso = (sc_pad_iso_t) RPC_U8(&msg, 6U); + } + if (wakeup != NULL) + { + *wakeup = (sc_pad_wakeup_t) RPC_U8(&msg, 7U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET(UI16 pad, UI32 val) #15 */ +sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, uint32_t val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(val); + RPC_U16(&msg, 4U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET(UI16 pad, UO32 val) #16 */ +sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (val != NULL) + { + *val = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 CONFIG(UI16 pad, UI32 val) #17 */ +sc_err_t sc_pad_config(sc_ipc_t ipc, sc_pad_t pad, uint32_t val) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_CONFIG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(val); + RPC_U16(&msg, 4U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_GP_28FDSOI(UI16 pad, UI8 dse, UI8 ps) #11 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(dse); + RPC_U8(&msg, 3U) = U8(ps); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_GP_28FDSOI(UI16 pad, UO8 dse, UO8 ps) #12 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (dse != NULL) + { + *dse = (sc_pad_28fdsoi_dse_t) RPC_U8(&msg, 0U); + } + if (ps != NULL) + { + *ps = (sc_pad_28fdsoi_ps_t) RPC_U8(&msg, 1U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_GP_28FDSOI_HSIC(UI16 pad, UI8 dse, IB hys, UI8 pus, IB pke, IB pue) #3 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_set_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hys, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_HSIC); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(dse); + RPC_U8(&msg, 3U) = U8(pus); + RPC_U8(&msg, 4U) = B2U8(hys); + RPC_U8(&msg, 5U) = B2U8(pke); + RPC_U8(&msg, 6U) = B2U8(pue); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_GP_28FDSOI_HSIC(UI16 pad, UO8 dse, OB hys, UO8 pus, OB pke, OB pue) #8 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_get_gp_28fdsoi_hsic(sc_ipc_t ipc, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hys, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_HSIC); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (dse != NULL) + { + *dse = (sc_pad_28fdsoi_dse_t) RPC_U8(&msg, 0U); + } + if (pus != NULL) + { + *pus = (sc_pad_28fdsoi_pus_t) RPC_U8(&msg, 1U); + } + if (hys != NULL) + { + *hys = (sc_bool_t) U2B(RPC_U8(&msg, 2U)); + } + if (pke != NULL) + { + *pke = (sc_bool_t) U2B(RPC_U8(&msg, 3U)); + } + if (pue != NULL) + { + *pue = (sc_bool_t) U2B(RPC_U8(&msg, 4U)); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_GP_28FDSOI_COMP(UI16 pad, UI8 compen, IB fastfrz, UI8 rasrcp, UI8 rasrcn, IB nasrc_sel, IB psw_ovr) #13 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, uint8_t compen, + sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, sc_bool_t nasrc_sel, + sc_bool_t psw_ovr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_SET_GP_28FDSOI_COMP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(compen); + RPC_U8(&msg, 3U) = U8(rasrcp); + RPC_U8(&msg, 4U) = U8(rasrcn); + RPC_U8(&msg, 5U) = B2U8(fastfrz); + RPC_U8(&msg, 6U) = B2U8(nasrc_sel); + RPC_U8(&msg, 7U) = B2U8(psw_ovr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_GP_28FDSOI_COMP(UI16 pad, UO8 compen, OB fastfrz, UO8 rasrcp, UO8 rasrcn, OB nasrc_sel, OB compok, UO8 nasrc, OB psw_ovr) #14 ^API_HAS_28FDSOI */ +sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pad_t pad, uint8_t *compen, + sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, sc_bool_t *nasrc_sel, + sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PAD); + RPC_FUNC(&msg) = U8(PAD_FUNC_GET_GP_28FDSOI_COMP); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (compen != NULL) + { + *compen = (uint8_t) RPC_U8(&msg, 0U); + } + if (rasrcp != NULL) + { + *rasrcp = (uint8_t) RPC_U8(&msg, 1U); + } + if (rasrcn != NULL) + { + *rasrcn = (uint8_t) RPC_U8(&msg, 2U); + } + if (nasrc != NULL) + { + *nasrc = (uint8_t) RPC_U8(&msg, 3U); + } + if (fastfrz != NULL) + { + *fastfrz = (sc_bool_t) U2B(RPC_U8(&msg, 4U)); + } + if (nasrc_sel != NULL) + { + *nasrc_sel = (sc_bool_t) U2B(RPC_U8(&msg, 5U)); + } + if (compok != NULL) + { + *compok = (sc_bool_t) U2B(RPC_U8(&msg, 6U)); + } + if (psw_ovr != NULL) + { + *psw_ovr = (sc_bool_t) U2B(RPC_U8(&msg, 7U)); + } + + /* Return result */ + return err; +} + +/** @} */ + diff --git a/platform/svc/pad/rpc_srv.c b/platform/svc/pad/rpc_srv.c new file mode 100644 index 0000000..27aa4a8 --- /dev/null +++ b/platform/svc/pad/rpc_srv.c @@ -0,0 +1,476 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the PAD service. + * + * @addtogroup PAD_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/pad/svc.h" +#include "svc/pad/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void pad_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case PAD_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch set_mux() */ + case PAD_FUNC_SET_MUX : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint8_t mux = ((uint8_t) RPC_U8(msg, 2U)); + sc_pad_config_t config = ((sc_pad_config_t) RPC_U8(msg, 3U)); + sc_pad_iso_t iso = ((sc_pad_iso_t) RPC_U8(msg, 4U)); + + /* Call function */ + err = pad_set_mux(caller_pt, pad, mux, config, iso); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_mux() */ + case PAD_FUNC_GET_MUX : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint8_t mux = ((uint8_t) 0U); + sc_pad_config_t config = ((sc_pad_config_t) 0U); + sc_pad_iso_t iso = ((sc_pad_iso_t) 0U); + + /* Call function */ + err = pad_get_mux(caller_pt, pad, &mux, &config, &iso); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mux); + RPC_U8(msg, 1U) = U8(config); + RPC_U8(msg, 2U) = U8(iso); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_gp() */ + case PAD_FUNC_SET_GP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 4U)); + uint32_t ctrl = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = pad_set_gp(caller_pt, pad, ctrl); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_gp() */ + case PAD_FUNC_GET_GP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint32_t ctrl = ((uint32_t) 0U); + + /* Call function */ + err = pad_get_gp(caller_pt, pad, &ctrl); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(ctrl); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_wakeup() */ + case PAD_FUNC_SET_WAKEUP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_wakeup_t wakeup = ((sc_pad_wakeup_t) RPC_U8(msg, 2U)); + + /* Call function */ + err = pad_set_wakeup(caller_pt, pad, wakeup); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_wakeup() */ + case PAD_FUNC_GET_WAKEUP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_wakeup_t wakeup = ((sc_pad_wakeup_t) 0U); + + /* Call function */ + err = pad_get_wakeup(caller_pt, pad, &wakeup); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(wakeup); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_all() */ + case PAD_FUNC_SET_ALL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 4U)); + uint8_t mux = ((uint8_t) RPC_U8(msg, 6U)); + sc_pad_config_t config = ((sc_pad_config_t) RPC_U8(msg, 7U)); + sc_pad_iso_t iso = ((sc_pad_iso_t) RPC_U8(msg, 8U)); + uint32_t ctrl = ((uint32_t) RPC_U32(msg, 0U)); + sc_pad_wakeup_t wakeup = ((sc_pad_wakeup_t) RPC_U8(msg, 9U)); + + /* Call function */ + err = pad_set_all(caller_pt, pad, mux, config, iso, ctrl, + wakeup); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_all() */ + case PAD_FUNC_GET_ALL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint8_t mux = ((uint8_t) 0U); + sc_pad_config_t config = ((sc_pad_config_t) 0U); + sc_pad_iso_t iso = ((sc_pad_iso_t) 0U); + uint32_t ctrl = ((uint32_t) 0U); + sc_pad_wakeup_t wakeup = ((sc_pad_wakeup_t) 0U); + + /* Call function */ + err = pad_get_all(caller_pt, pad, &mux, &config, &iso, &ctrl, + &wakeup); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 4U) = U8(mux); + RPC_U8(msg, 5U) = U8(config); + RPC_U8(msg, 6U) = U8(iso); + RPC_U32(msg, 0U) = U32(ctrl); + RPC_U8(msg, 7U) = U8(wakeup); + RPC_SIZE(msg) = 3U; + break; + } + /* Dispatch set() */ + case PAD_FUNC_SET : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 4U)); + uint32_t val = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = pad_set(caller_pt, pad, val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get() */ + case PAD_FUNC_GET : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint32_t val = ((uint32_t) 0U); + + /* Call function */ + err = pad_get(caller_pt, pad, &val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(val); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch config() */ + case PAD_FUNC_CONFIG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 4U)); + uint32_t val = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = pad_config(caller_pt, pad, val); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } +#ifdef API_HAS_28FDSOI + /* Dispatch set_gp_28fdsoi() */ + case PAD_FUNC_SET_GP_28FDSOI : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_28fdsoi_dse_t dse = ((sc_pad_28fdsoi_dse_t) RPC_U8(msg, 2U)); + sc_pad_28fdsoi_ps_t ps = ((sc_pad_28fdsoi_ps_t) RPC_U8(msg, 3U)); + + /* Call function */ + err = pad_set_gp_28fdsoi(caller_pt, pad, dse, ps); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } +#endif +#ifdef API_HAS_28FDSOI + /* Dispatch get_gp_28fdsoi() */ + case PAD_FUNC_GET_GP_28FDSOI : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_28fdsoi_dse_t dse = ((sc_pad_28fdsoi_dse_t) 0U); + sc_pad_28fdsoi_ps_t ps = ((sc_pad_28fdsoi_ps_t) 0U); + + /* Call function */ + err = pad_get_gp_28fdsoi(caller_pt, pad, &dse, &ps); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(dse); + RPC_U8(msg, 1U) = U8(ps); + RPC_SIZE(msg) = 2U; + break; + } +#endif +#ifdef API_HAS_28FDSOI + /* Dispatch set_gp_28fdsoi_hsic() */ + case PAD_FUNC_SET_GP_28FDSOI_HSIC : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_28fdsoi_dse_t dse = ((sc_pad_28fdsoi_dse_t) RPC_U8(msg, 2U)); + sc_bool_t hys = U2B(RPC_U8(msg, 4U)); + sc_pad_28fdsoi_pus_t pus = ((sc_pad_28fdsoi_pus_t) RPC_U8(msg, 3U)); + sc_bool_t pke = U2B(RPC_U8(msg, 5U)); + sc_bool_t pue = U2B(RPC_U8(msg, 6U)); + + /* Call function */ + err = pad_set_gp_28fdsoi_hsic(caller_pt, pad, dse, hys, pus, pke, + pue); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } +#endif +#ifdef API_HAS_28FDSOI + /* Dispatch get_gp_28fdsoi_hsic() */ + case PAD_FUNC_GET_GP_28FDSOI_HSIC : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_28fdsoi_dse_t dse = ((sc_pad_28fdsoi_dse_t) 0U); + sc_bool_t hys = SC_FALSE; + sc_pad_28fdsoi_pus_t pus = ((sc_pad_28fdsoi_pus_t) 0U); + sc_bool_t pke = SC_FALSE; + sc_bool_t pue = SC_FALSE; + + /* Call function */ + err = pad_get_gp_28fdsoi_hsic(caller_pt, pad, &dse, &hys, &pus, + &pke, &pue); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(dse); + RPC_U8(msg, 2U) = B2U8(hys); + RPC_U8(msg, 1U) = U8(pus); + RPC_U8(msg, 3U) = B2U8(pke); + RPC_U8(msg, 4U) = B2U8(pue); + RPC_SIZE(msg) = 3U; + break; + } +#endif +#ifdef API_HAS_28FDSOI + /* Dispatch set_gp_28fdsoi_comp() */ + case PAD_FUNC_SET_GP_28FDSOI_COMP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint8_t compen = ((uint8_t) RPC_U8(msg, 2U)); + sc_bool_t fastfrz = U2B(RPC_U8(msg, 5U)); + uint8_t rasrcp = ((uint8_t) RPC_U8(msg, 3U)); + uint8_t rasrcn = ((uint8_t) RPC_U8(msg, 4U)); + sc_bool_t nasrc_sel = U2B(RPC_U8(msg, 6U)); + sc_bool_t psw_ovr = U2B(RPC_U8(msg, 7U)); + + /* Call function */ + err = pad_set_gp_28fdsoi_comp(caller_pt, pad, compen, fastfrz, + rasrcp, rasrcn, nasrc_sel, psw_ovr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } +#endif +#ifdef API_HAS_28FDSOI + /* Dispatch get_gp_28fdsoi_comp() */ + case PAD_FUNC_GET_GP_28FDSOI_COMP : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + uint8_t compen = ((uint8_t) 0U); + sc_bool_t fastfrz = SC_FALSE; + uint8_t rasrcp = ((uint8_t) 0U); + uint8_t rasrcn = ((uint8_t) 0U); + sc_bool_t nasrc_sel = SC_FALSE; + sc_bool_t compok = SC_FALSE; + uint8_t nasrc = ((uint8_t) 0U); + sc_bool_t psw_ovr = SC_FALSE; + + /* Call function */ + err = pad_get_gp_28fdsoi_comp(caller_pt, pad, &compen, &fastfrz, + &rasrcp, &rasrcn, &nasrc_sel, &compok, &nasrc, &psw_ovr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(compen); + RPC_U8(msg, 4U) = B2U8(fastfrz); + RPC_U8(msg, 1U) = U8(rasrcp); + RPC_U8(msg, 2U) = U8(rasrcn); + RPC_U8(msg, 5U) = B2U8(nasrc_sel); + RPC_U8(msg, 6U) = B2U8(compok); + RPC_U8(msg, 3U) = U8(nasrc); + RPC_U8(msg, 7U) = B2U8(psw_ovr); + RPC_SIZE(msg) = 3U; + break; + } +#endif + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=pad, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=pad, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/pad/svc.c b/platform/svc/pad/svc.c new file mode 100755 index 0000000..fd02ed1 --- /dev/null +++ b/platform/svc/pad/svc.c @@ -0,0 +1,878 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/pad/svc.c + * + * File containing the implementation of the System Controller (SC) Pad + * Control (PAD) function. + * + * @addtogroup PAD_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "main/soc.h" +#include "main/boot.h" +#include "svc/pad/svc.h" +#include "svc/rm/svc.h" +#include "ss/inf/inf.h" +#include "drivers/pad/fsl_pad.h" +#include "pad_priority.h" + +/* Local Defines */ + +/*! Define to fill in a pad_priority_info_t variable */ +#define PNFO(PAD, PAD_MUX, PAD_RSRC) \ +{ \ + .pad = SC_P_##PAD, \ + .mux = (PAD_MUX), \ + .resource = SC_R_##PAD_RSRC \ +} + +/*! + * @name Parameter checking macros + */ +/** @{ */ +#define PAD_OWNED(X) ASRT_ERR(rm_is_pad_owned(caller_pt, (X)) != SC_FALSE, SC_ERR_NOACCESS) +#define PAD_OWNED_C(X) ASRT_C(rm_is_pad_owned(caller_pt, (X)) != SC_FALSE) +#define MUX_OKAY(X,Y) ASRT_ERR(pad_mux_okay(caller_pt, (X), (Y)) != SC_FALSE, SC_ERR_NOACCESS) +#define MUX_OKAY_C(X,Y) ASRT_C(pad_mux_okay(caller_pt, (X), (Y)) != SC_FALSE) +/** @} */ + +/* Local Types */ + +/*! + * This type is used store static constant info about resources in a + * subsystem. A pointer to this structure can be found in the + * ss_base_info_t type. + */ +typedef struct +{ + sc_pad_t pad : SC_PAD_W; //!< Pad + uint8_t mux : SC_PAD_MUX_W; //!< Mux + sc_rsrc_t resource : SC_RSRC_W; //!< Resource +} pad_priority_info_t; + +/* Local Functions */ + +static sc_bool_t pad_mux_okay(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t mux); + +/* Local Variables */ + +/*! + * Constant array to hold pad mapping info. + */ +static const uint16_t pad_map[SC_NUM_PAD] = +{ + SC_SVC_PAD_INIT +}; + +/*--------------------------------------------------------------------------*/ +/* Init the pad service */ +/*--------------------------------------------------------------------------*/ +void pad_init(sc_bool_t api_phase) +{ + static const pad_priority_info_t pad_init_info[] = + { + SC_PAD_INIT_INIT + }; + + if (api_phase == SC_FALSE) + { + sc_rsrc_t boot_dev; + const pad_priority_info_t *p = pad_init_info; + + /* Get boot device */ + boot_dev = boot_get_dev(SC_PT, SC_FALSE); + + /* Loop through pad priority */ + while ((p->pad != 0U) || (p->mux != 0U) || (p->resource != 0U)) + { + /* Unused for boot? */ + if (p->resource != boot_dev) + { + uint8_t mux = 0U; + sc_pad_config_t config = SC_PAD_CONFIG_NORMAL; + sc_pad_iso_t iso = SC_PAD_ISO_OFF; + + /* Get current state */ + if (pad_get_mux(SC_PT, p->pad, &mux, &config, &iso) == SC_ERR_NONE) + { + /* Check if not already configured by ROM */ + if (mux == 0U) + { + pad_force_mux(p->pad, p->mux, + SC_PAD_CONFIG_NORMAL, SC_PAD_ISO_OFF); + } + } + } + + p++; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the pad */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + uint8_t mux; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Extract the mux setting */ + mux = PAD_ExtractMux(val); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + MUX_OKAY(pad, mux); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + PAD_OWNED_C(p); + MUX_OKAY_C(p, mux); + } + + /* Configure */ + PAD_Set(U32(pad_map[p]) << 4U, val); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the pad mux */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_mux(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(config <= SC_PAD_CONFIG_OUT_IN, SC_ERR_PARM); + ASRT_ERR(iso <= SC_PAD_ISO_ON, SC_ERR_PARM); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + MUX_OKAY(pad, mux); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + PAD_OWNED_C(p); + MUX_OKAY_C(p, mux); + } + + /* Configure mux */ + PAD_SetMux(U32(pad_map[p]) << 4U, mux, config, iso); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Force the pad mux */ +/*--------------------------------------------------------------------------*/ +void pad_force_mux(sc_pad_t pad, uint8_t mux, sc_pad_config_t config, + sc_pad_iso_t iso) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check parameters */ + BOUND_PAD(pad); + + if (err == SC_ERR_NONE) + { + /* Configure mux */ + PAD_SetMux(U32(pad_map[pad]) << 4U, mux, config, iso); + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the pad control */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_gp(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t ctrl) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + PAD_OWNED(pad); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + PAD_OWNED_C(p); + } + + /* Configure GP */ + PAD_SetGP(U32(pad_map[p]) << 4U, ctrl); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the pad wakeup control */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_wakeup(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_wakeup_t wakeup) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(wakeup <= SC_PAD_WAKEUP_HIGH_LVL, SC_ERR_PARM); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + PAD_OWNED_C(p); + } + + /* Configure wakeup */ + PAD_SetWakeup(U32(pad_map[p]) << 4U, wakeup); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the pad config */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_all(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(config <= SC_PAD_CONFIG_OUT_IN, SC_ERR_PARM); + ASRT_ERR(iso <= SC_PAD_ISO_ON, SC_ERR_PARM); + ASRT_ERR(wakeup <= SC_PAD_WAKEUP_HIGH_LVL, SC_ERR_PARM); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + MUX_OKAY(pad, mux); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + PAD_OWNED_C(p); + MUX_OKAY_C(p, mux); + } + + /* Configure all */ + PAD_SetAll(U32(pad_map[p]) << 4U, mux, config, iso, ctrl, + wakeup); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t *val) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure mux */ + PAD_Get(U32(pad_map[pad]) << 4U, val); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad mux */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_mux(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Get mux */ + PAD_GetMux(U32(pad_map[pad]) << 4U, mux, config, iso); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad control */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_gp(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t *ctrl) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Get GP */ + PAD_GetGP(U32(pad_map[pad]) << 4U, ctrl); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad wakeup control */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_wakeup(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_wakeup_t *wakeup) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Get mux */ + PAD_GetWakeup(U32(pad_map[pad]) << 4U, wakeup); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad config */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_all(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure all */ + PAD_GetAll(U32(pad_map[pad]) << 4U, mux, config, iso, ctrl, + wakeup); + } + + return err; +} + +#ifdef API_HAS_28FDSOI +/*--------------------------------------------------------------------------*/ +/* Set the pad control specific to 28FDSOI */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_gp_28fdsoi(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(dse <= SC_PAD_28FDSOI_DSE_18V_HS, SC_ERR_PARM); + ASRT_ERR(ps <= SC_PAD_28FDSOI_PS_NONE, SC_ERR_PARM); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + PAD_OWNED_C(p); + } + + /* Configure GP */ + PAD_SetGP28Fdsoi(U32(pad_map[p]) << 4U, dse, ps); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad control specific to 28FDSOI */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_gp_28fdsoi(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + /* Configure GP */ + if (err == SC_ERR_NONE) + { + PAD_GetGP28Fdsoi(U32(pad_map[pad]) << 4U, dse, ps); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the pad control specific to 28FDSOI HSIC */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_gp_28fdsoi_hsic(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hyp, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(dse <= SC_PAD_28FDSOI_DSE_18V_HS, SC_ERR_PARM); + ASRT_ERR(pus <= SC_PAD_28FDSOI_PUS_30K_PU, SC_ERR_PARM); + + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure GP */ + PAD_SetGP28FdsoiHsic(U32(pad_map[pad]) << 4U, dse, hyp, + pus, pke, pue); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad control specific to 28FDSOI HSIC */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_gp_28fdsoi_hsic(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hyp, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure GP */ + PAD_GetGP28FdsoiHsic(U32(pad_map[pad]) << 4U, dse, hyp, pus, pke, + pue); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the compensation control specific to 28FDSOI */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_set_gp_28fdsoi_comp(sc_rm_pt_t caller_pt, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure GP */ + PAD_SetGP28FdsoiComp(U32(pad_map[pad]) << 4U, compen, fastfrz, + rasrcp, rasrcn, nasrc_sel, psw_ovr); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the pad compensation specific to 28FDSOI */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_get_gp_28fdsoi_comp(sc_rm_pt_t caller_pt, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, + sc_bool_t *psw_ovr) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure GP */ + PAD_GetGP28FdsoiComp(U32(pad_map[pad]) << 4U, compen, fastfrz, + rasrcp, rasrcn, nasrc_sel, compok, nasrc, psw_ovr); + } + + return err; +} +#endif + +/*--------------------------------------------------------------------------*/ +/* Set a config value */ +/*--------------------------------------------------------------------------*/ +sc_err_t pad_config(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t val) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + BOUND_PAD(pad); + + /* Check ownership */ + PAD_OWNED(pad); + + if (err == SC_ERR_NONE) + { + /* Configure */ + PAD_Set(U32(pad_map[pad]) << 4U, val); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Map pad irq and index to pad resource */ +/*--------------------------------------------------------------------------*/ +sc_pad_t pad_map_irq(uint8_t irq, uint8_t idx) +{ + /*! + * Constant array to hold pad grouping info. + */ + static const sc_pad_t pad_irq[SC_NUM_PAD_IRQS] = + { + SC_SVC_PAD_IRQ_INIT + }; + + /* Init pad */ + sc_pad_t pad = SC_NUM_PAD; + + /* Calculate pad from pending IRQ */ + if (irq < SC_NUM_PAD_IRQS) + { + pad = pad_irq[irq] + idx; + } + + return pad; +} + +/*--------------------------------------------------------------------------*/ +/* Dump PAD state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) && defined(DEBUG_PAD) + void pad_dump(sc_rm_pt_t pt) + { + } +#endif + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Get priority conflict info */ +/*--------------------------------------------------------------------------*/ +static sc_bool_t pad_mux_okay(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t mux) +{ + static const pad_priority_info_t pad_priority[SC_NUM_PAD_PRIORITY + 1] = + { + SC_PAD_PRIORITY_INIT + }; + static const pad_priority_info_t * const p = pad_priority; + int16_t top = SC_NUM_PAD_PRIORITY - 1; + uint32_t search = (U32(pad) << 16U) | U32(mux); + sc_bool_t rtn = SC_TRUE; + + /* Skip check for SCFW */ + if (caller_pt != SC_PT) + { + int16_t bottom = 0; + + /* Perform binary search */ + while (bottom <= top) + { + int16_t mid; + uint32_t item; + + /* Next middle to check */ + mid = bottom + ((top - bottom) / 2); + + /* Generate item */ + item = (U32(p[mid].pad) << 16U) | U32(p[mid].mux); + + if (item < search) + { + /* Next search section */ + bottom = mid + 1; + } + else if (item > search) + { + /* Next search section */ + top = mid - 1; + } + else + { + /* Found so return it */ + rtn = rm_is_resource_access_allowed(caller_pt, p[mid].resource); + + break; + } + } + } + + return rtn; +} + +/** @} */ + diff --git a/platform/svc/pad/svc.h b/platform/svc/pad/svc.h new file mode 100755 index 0000000..a6dc011 --- /dev/null +++ b/platform/svc/pad/svc.h @@ -0,0 +1,263 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/pad/svc.h + * + * Header file containing the API for the System Controller (SC) Pad + * Control (PAD) function. + * + * @addtogroup PAD_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_PAD_SVC_H +#define SC_PAD_SVC_H + +/* Includes */ + +#include "svc/pad/api.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * @name Internal Functions + * @{ + */ + +/*! + * Internal SC function to initializes the PAD service. + * + * @param[in] api_phase init phase + * + * Initializes the API if /a api_phase = SC_TRUE, otherwise initializes the HW + * managed by the PAD service. API must be initialized before anything else is + * done with the service. + */ +void pad_init(sc_bool_t api_phase); + +/*! + * Internal SC function to set the pad value. + * + * @see sc_pad_set(). + */ +sc_err_t pad_set(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t val); + +/*! + * Internal SC function to set the pad mux. + * + * @see sc_pad_set_mux(). + */ +sc_err_t pad_set_mux(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso); + +/* + * This internal function configures the mux settings for a pad. This + * includes the signal mux, pad config, and low-power isolation mode. + * + * @param[in] pad pad to configure + * @param[in] mux mux setting + * @param[in] config pad config + * @param[in] iso low-power isolation mode + * + * No error returned. Just fails silently. + */ +void pad_force_mux(sc_pad_t pad, uint8_t mux, sc_pad_config_t config, + sc_pad_iso_t iso); + +/*! + * Internal SC function to set the pad control. + * + * @see sc_pad_set_gp(). + */ +sc_err_t pad_set_gp(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t ctrl); + +/*! + * Internal SC function to set the pad wakeup control. + * + * @see sc_pad_set_wakeup(). + */ +sc_err_t pad_set_wakeup(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_wakeup_t wakeup); + +/*! + * Internal SC function to configure a pad. + * + * @see sc_pad_set_all(). + */ +sc_err_t pad_set_all(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t mux, + sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl, + sc_pad_wakeup_t wakeup); + +/*! + * Internal SC function to get the pad value. + * + * @see sc_pad_get(). + */ +sc_err_t pad_get(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t *val); + +/*! + * Internal SC function to get the pad mux. + * + * @see sc_pad_get_mux(). + */ +sc_err_t pad_get_mux(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso); + +/*! + * Internal SC function to get the pad control. + * + * @see sc_pad_get_gp(). + */ +sc_err_t pad_get_gp(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t *ctrl); + +/*! + * Internal SC function to get the pad wakeup control. + * + * @see sc_pad_get_wakeup(). + */ +sc_err_t pad_get_wakeup(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_wakeup_t *wakeup); + +/*! + * Internal SC function to get a pad's configuration. + * + * @see sc_pad_get_all(). + */ +sc_err_t pad_get_all(sc_rm_pt_t caller_pt, sc_pad_t pad, uint8_t *mux, + sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl, + sc_pad_wakeup_t *wakeup); + +#ifdef API_HAS_28FDSOI +/*! + * Internal SC function to set the pad control specific to 28FDSOI. + * + * @see sc_pad_set_gp_28fdsoi(). + */ +sc_err_t pad_set_gp_28fdsoi(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps); + +/*! + * Internal SC function to get the pad control specific to 28FDSOI. + * + * @see sc_pad_get_gp_28fdsoi(). + */ +sc_err_t pad_get_gp_28fdsoi(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps); + +/*! + * Internal SC function to set the pad control specific to 28FDSOI. + * + * @see sc_pad_set_gp_28fdsoi_hsic(). + */ +sc_err_t pad_set_gp_28fdsoi_hsic(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t dse, sc_bool_t hyp, sc_pad_28fdsoi_pus_t pus, + sc_bool_t pke, sc_bool_t pue); + +/*! + * Internal SC function to get the pad control specific to 28FDSOI. + * + * @see sc_pad_get_gp_28fdsoi_hsic(). + */ +sc_err_t pad_get_gp_28fdsoi_hsic(sc_rm_pt_t caller_pt, sc_pad_t pad, + sc_pad_28fdsoi_dse_t *dse, sc_bool_t *hyp, sc_pad_28fdsoi_pus_t *pus, + sc_bool_t *pke, sc_bool_t *pue); + +/*! + * Internal SC function to set the pad compensation specific to 28FDSOI. + * + * @see sc_pad_set_gp_28fdsoi_comp(). + */ +sc_err_t pad_set_gp_28fdsoi_comp(sc_rm_pt_t caller_pt, sc_pad_t pad, + uint8_t compen, sc_bool_t fastfrz, uint8_t rasrcp, uint8_t rasrcn, + sc_bool_t nasrc_sel, sc_bool_t psw_ovr); + +/*! + * Internal SC function to get the compensation control specific to 28FDSOI. + * + * @see sc_pad_get_gp_28fdsoi_comp(). + */ +sc_err_t pad_get_gp_28fdsoi_comp(sc_rm_pt_t caller_pt, sc_pad_t pad, + uint8_t *compen, sc_bool_t *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn, + sc_bool_t *nasrc_sel, sc_bool_t *compok, uint8_t *nasrc, sc_bool_t *psw_ovr); +#endif + +/*! + * Internal SC function to set a config value. + * + * @see sc_pad_config(). + */ +sc_err_t pad_config(sc_rm_pt_t caller_pt, sc_pad_t pad, uint32_t val); + +/*! + * Internal function to map pad irq and index to pad resource. + * + * @param[in] irq irq of pad + * @param[out] idx index within irq + * + * @return Returns the pad mapping. + * + * If invalid irq or idx then return is >= SC_NUM_PAD. + */ +sc_pad_t pad_map_irq(uint8_t irq, uint8_t idx); + +/** @} */ + +#if defined(DEBUG) && defined(DEBUG_PAD) + /*! + * @name Debug Functions + * @{ + */ + + /*! + * Internal SC function to dump the internal state of the PAD service. + * + * @param[in] pt partition to dump + */ + void pad_dump(sc_rm_pt_t pt); + + /** @} */ +#endif + +#endif /* SC_PAD_SVC_H */ + +/** @} */ + diff --git a/platform/svc/pm/Makefile b/platform/svc/pm/Makefile new file mode 100755 index 0000000..b31b54a --- /dev/null +++ b/platform/svc/pm/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/pm/svc.o + +RPCS += $(OUT)/svc/pm/rpc_srv.o + +RPCL += $(OUT)/svc/pm/rpc_clnt.o + +RPCH += $(SRC)/svc/pm/rpc.h + +RPCC += $(SRC)/svc/pm/rpc_srv.c \ + $(SRC)/svc/pm/rpc_clnt.c \ + $(SRC)/svc/pm/rpc_xlate.c + +RPCHDR += $(SRC)/svc/pm/rpc_header.h + +DIRS += $(OUT)/svc/pm + diff --git a/platform/svc/pm/api.h b/platform/svc/pm/api.h new file mode 100755 index 0000000..8f4630b --- /dev/null +++ b/platform/svc/pm/api.h @@ -0,0 +1,947 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/pm/api.h + * + * Header file containing the public API for the System Controller (SC) + * Power Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * @addtogroup PM_SVC PM: Power Management Service + * + * @brief Module for the Power Management (PM) service. + * + * @includedoc pm/details.dox + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_PM_API_H +#define SC_PM_API_H + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/** @{ */ +#define SC_PM_POWER_MODE_W 2U /*!< Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /*!< Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /*!< Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /*!< Width of sc_pm_reset_reason_t */ +/** @} */ + +/*! + * @name Defines for clock indexes (sc_pm_clk_t) + */ +/** @{ */ +/** @} */ + +/*! + * @name Defines for ALL parameters + */ +/** @{ */ +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /*!< All clocks */ +/** @} */ + +/*! + * @name Defines for sc_pm_power_mode_t + */ +/** @{ */ +#define SC_PM_PW_MODE_OFF 0U /*!< Power off */ +#define SC_PM_PW_MODE_STBY 1U /*!< Power in standby */ +#define SC_PM_PW_MODE_LP 2U /*!< Power in low-power */ +#define SC_PM_PW_MODE_ON 3U /*!< Power on */ +/** @} */ + +/*! + * @name Defines for sc_pm_clk_t + */ +/** @{ */ +#define SC_PM_CLK_SLV_BUS 0U /*!< Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1U /*!< Master bus clock */ +#define SC_PM_CLK_PER 2U /*!< Peripheral clock */ +#define SC_PM_CLK_PHY 3U /*!< Phy clock */ +#define SC_PM_CLK_MISC 4U /*!< Misc clock */ +#define SC_PM_CLK_MISC0 0U /*!< Misc 0 clock */ +#define SC_PM_CLK_MISC1 1U /*!< Misc 1 clock */ +#define SC_PM_CLK_MISC2 2U /*!< Misc 2 clock */ +#define SC_PM_CLK_MISC3 3U /*!< Misc 3 clock */ +#define SC_PM_CLK_MISC4 4U /*!< Misc 4 clock */ +#define SC_PM_CLK_CPU 2U /*!< CPU clock */ +#define SC_PM_CLK_PLL 4U /*!< PLL */ +#define SC_PM_CLK_BYPASS 4U /*!< Bypass clock */ +/** @} */ + +/*! + * @name Defines for sc_pm_clk_parent_t + */ +/** @{ */ +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL */ +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ +/** @} */ + +/*! + * @name Defines for sc_pm_reset_type_t + */ +/** @{ */ +#define SC_PM_RESET_TYPE_COLD 0U /*!< Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /*!< Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /*!< Board reset */ +/** @} */ + +/*! + * @name Defines for sc_pm_reset_reason_t + */ +/** @{ */ +#define SC_PM_RESET_REASON_POR 0U /*!< Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /*!< JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /*!< Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /*!< Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /*!< SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /*!< SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /*!< Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /*!< MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /*!< ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /*!< SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /*!< SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /*!< SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /*!< SCFW fault reset */ +#define SC_PM_RESET_REASON_V2X_DEBUG 13U /*!< V2X debug switch */ +/** @} */ + +/*! + * @name Defines for sc_pm_sys_if_t + */ +/** @{ */ +#define SC_PM_SYS_IF_INTERCONNECT 0U /*!< System interconnect */ +#define SC_PM_SYS_IF_MU 1U /*!< AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /*!< On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /*!< DDR memory */ +/** @} */ + +/*! + * @name Defines for sc_pm_wake_src_t + */ +/** @{ */ +#define SC_PM_WAKE_SRC_NONE 0U /*!< No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /*!< Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /*!< Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /*!< Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /*!< Wakeup from GIC to wake CPU */ +/** @} */ + +/* Types */ + +/*! + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ +typedef uint8_t sc_pm_power_mode_t; + +/*! + * This type is used to declare a clock. + */ +typedef uint8_t sc_pm_clk_t; + +/*! + * This type is used to declare the clock parent. + */ +typedef uint8_t sc_pm_clk_parent_t; + +/*! + * This type is used to declare clock rates. + */ +typedef uint32_t sc_pm_clock_rate_t; + +/*! + * This type is used to declare a desired reset type. + */ +typedef uint8_t sc_pm_reset_type_t; + +/*! + * This type is used to declare a reason for a reset. + */ +typedef uint8_t sc_pm_reset_reason_t; + +/*! + * This type is used to specify a system-level interface to be power managed. + */ +typedef uint8_t sc_pm_sys_if_t; + +/*! + * This type is used to specify a wake source for CPU resources. + */ +typedef uint8_t sc_pm_wake_src_t; + +/* Functions */ + +/*! + * @name Power Functions + * @{ + */ + +/*! + * This function sets the system power mode. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid mode, + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * + * @see sc_pm_set_sys_power_mode(). + */ +/* IDL: E8 SET_SYS_POWER_MODE(UI8 mode) #19 */ +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode); + +/*! + * This function sets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or mode != SC_PM_PW_MODE_OFF, + * - SC_ERR_NOACCESS if caller's partition is not the owner or + * parent of \a pt + * + * This function can only be used to turn off a partition by calling + * with mode equal to SC_PM_PW_MODE_OFF. After turning off, the partition + * can be booted with sc_pm_reboot_partition() or sc_pm_boot(). It cannot + * be used to turn off the calling partition as the MU could not return + * the an error response. + * + * For dynamic power management of a partition, use + * sc_pm_req_low_power_mode(), sc_pm_req_cpu_low_power_mode(), + * and sc_pm_req_sys_if_power_mode() with a WFI for controlled power + * state transitions. + */ +/* IDL: E8 SET_PARTITION_POWER_MODE(UI8 pt, UI8 mode) #1 */ +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode); + +/*! + * This function turns off the calling partition. + * + * @param[in] ipc IPC handle + * + * This function can only be used to turn off the calling partition. + * After turning off, the partition can only be booted by the parent + * with sc_pm_reboot_partition() or sc_pm_boot(). + */ +/* IDL: RN PARTITION_POWER_OFF() #30 */ +void sc_pm_partition_power_off(sc_ipc_t ipc); + +/*! + * This function gets the power mode of a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +/* IDL: E8 GET_SYS_POWER_MODE(UI8 pt, UO8 mode) #2 */ +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode); + +/*! + * This function sends a wake interrupt to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to wake + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * An SC_IRQ_SW_WAKE interrupt is sent to all MUs owned by the + * partition that have this interrupt enabled. The CPU using an + * MU will exit a low-power state to service the MU interrupt. + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +/* IDL: E8 PARTITION_WAKE(UI8 pt) #28 */ +sc_err_t sc_pm_partition_wake(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function sets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or mode, + * - SC_ERR_PARM if resource is the MU used to make the call, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner + * + * Resources must be at SC_PM_PW_MODE_LP mode or higher to access them, + * otherwise the master will get a bus error or hang. + * + * Note some resources are still not accessible even when powered up if bus + * transactions go through a fabric not powered up. Examples of this are + * resources in display and capture subsystems which require the display + * controller or the imaging subsystem to be powered up first. + * + * Note that resources are grouped into power domains by the underlying + * hardware. If any resource in the domain is on, the entire power domain + * will be on. Other power domains required to access the resource will + * also be turned on. Bus clocks required to access the peripheral will be + * turned on. Refer to the SoC RM for more info on power domains and access + * infrastructure (bus fabrics, clock domains, etc.). + * + * When the resource transitions to the SC_PM_PW_MODE_OFF, all of the settings, + * including clock rate, will be lost; immaterial of the state of other + * resources in the same power domain. + */ +/* IDL: E8 SET_RESOURCE_POWER_MODE(UI16 resource, UI8 mode) #3 */ +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * This function sets the power mode for all the resources owned + * by a child partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of child partition + * @param[in] mode power mode to apply + * @param[in] exclude resource to exclude + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or mode, + * - SC_ERR_NOACCESS if caller's partition is not the parent + * (with grant) of \a pt + * + * This functions loops through all the resources owned by \a pt + * and sets the power mode to \a mode. It will skip setting + * \a exclude (SC_R_LAST to skip none). + * + * This function can only be called by the parent. It is used to + * implement some aspects of virtualization. + */ +/* IDL: E8 SET_RESOURCE_POWER_MODE_ALL(UI8 pt, UI8 mode, UI16 exclude) #22 */ +sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude); + +/*! + * This function gets the power mode of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[out] mode pointer to return power mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. The value + * returned does not reflect the power mode of the partition. + */ +/* IDL: E8 GET_RESOURCE_POWER_MODE(UI16 resource, UO8 mode) #4 */ +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode); + +/*! + * This function specifies the low power mode some of the resources + * can enter based on their state. This API is only valid for the + * following resources : SC_R_AP_x, SC_R_AP_x_y, SC_R_CCI. For all + * other resources it will return SC_ERR_PARAM. This function will + * set the low power mode the cores, cluster and cluster associated + * resources will enter when all the cores in a given cluster execute + * WFI. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +/* IDL: E8 REQ_LOW_POWER_MODE(UI16 resource, UI8 mode) #16 */ +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * This function requests low-power mode entry for CPU/cluster + * resources. This API is only valid for the following resources: + * SC_R_AP_x, SC_R_AP_x_y, SC_R_CCI. For all other resources it will + * return SC_ERR_PARAM. For individual core resources, the specified + * power mode and wake source will be applied after the core has entered + * WFI. For cluster resources, the specified power mode is + * applied after all cores in the cluster have entered low-power mode. + * For multicluster resources, the specified power mode is applied + * after all clusters have reached low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * @param[in] wake_src wake source for low-power exit + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +/* IDL: E8 REQ_CPU_LOW_POWER_MODE(UI16 resource, UI8 mode, UI8 wake_src) #20 */ +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); + +/*! + * This function is used to set the resume address of a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +/* IDL: E8 SET_CPU_RESUME_ADDR(UI16 resource, UI64 address) #17 */ +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address); + +/*! + * This function is used to set parameters for CPU resume from + * low-power mode. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] isPrimary set SC_TRUE if primary wake CPU + * @param[in] address 64-bit resume address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +/* IDL: E8 SET_CPU_RESUME(UI16 resource, IB isPrimary, UI64 address) #21 */ +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address); + +/*! + * This function requests the power mode configuration for system-level + * interfaces including messaging units, interconnect, and memories. This + * API is only valid for the following resources : SC_R_AP_x, and + * SC_R_MCU_x_PID_y. For all other resources, it will return SC_ERR_PARAM. + * The requested power mode will be captured and applied to system-level + * resources as system conditions allow. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] sys_if system-level interface to be configured + * @param[in] hpm high-power mode for the system interface + * @param[in] lpm low-power mode for the system interface + * + * @return Returns an error code (SC_ERR_NONE = success). + * + */ +/* IDL: E8 REQ_SYS_IF_POWER_MODE(UI16 resource, UI8 sys_if, UI8 hpm, UI8 lpm) #18 */ +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); + +/** @} */ + +/*! + * @name Clock/PLL Functions + * @{ + */ + +/*! + * This function sets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[in,out] rate pointer to rate + * + * This function returns the actual clock rate of the hardware. This rate + * may be different from the requested clock rate. It is guaranteed to be + * <= the requested rate. If no such rate can be obtained due to hardware + * limitations then it will return SC_ERR_PARM. See the Clocking section + * of the SoC RM to understand the limitations of any specific clock. + * Limitations may be due to clock rate of parent, parent options, max + * integer divider range, etc. The monitor 'dump rsrc_clks' command can + * be used to better understand the limitations. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock/PLL, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource, + * - SC_ERR_LOCKED if rate locked (usually because shared clock/PLL) + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +/* IDL: E8 SET_CLOCK_RATE(UI16 resource, UI8 clk, UIO32 rate) #5 */ +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function gets the rate of a resource's clock/PLL. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock/PLL to affect + * @param[out] rate pointer to return rate + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource, clock/PLL, or rate, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock/PLL not applicable to this resource + * + * This function returns the actual clock rate of the hardware. This rate + * may be different from the original requested clock rate if the resource + * is set to a low power mode. + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock/PLL values. + */ +/* IDL: E8 GET_CLOCK_RATE(UI16 resource, UI8 clk, UO32 rate) #6 */ +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * This function enables/disables a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] enable enable if SC_TRUE; otherwise disabled + * @param[in] autog HW auto clock gating + * + * If \a resource is SC_R_ALL then all resources owned will be affected. + * No error will be returned. + * + * If \a clk is SC_PM_CLK_ALL, then an error will be returned if any + * of the available clocks returns an error. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent (with grant) of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * - SC_ERR_NOPOWER if resource not powered + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +/* IDL: E8 CLOCK_ENABLE(UI16 resource, UI8 clk, IB enable, IB autog) #7 */ +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); + +/*! + * This function sets the parent of a resource's clock. + * This function should only be called when the clock is disabled. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] parent New parent of the clock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent (with grant) of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * - SC_ERR_BUSY if clock is currently enabled. + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +/* IDL: E8 SET_CLOCK_PARENT(UI16 resource, UI8 clk, UI8 parent) #14 */ +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); + +/*! + * This function gets the parent of a resource's clock. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[out] parent pointer to return parent of clock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or clock, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner + * or parent of the owner, + * - SC_ERR_UNAVAILABLE if clock not applicable to this resource + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +/* IDL: E8 GET_CLOCK_PARENT(UI16 resource, UI8 clk, UO8 parent) #15 */ +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); + +/** @} */ + +/*! + * @name Reset Functions + * @{ + */ + +/*! + * This function is used to reset the system. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid type, + * - SC_ERR_NOACCESS if caller cannot access SC_R_SYSTEM + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. + */ +/* IDL: E8 RESET(UI8 type) #13 */ +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function gets a caller's reset reason. + * + * @param[in] ipc IPC handle + * @param[out] reason pointer to return the reset reason + * + * This function returns the reason a partition was reset. If the reason + * is POR, then the system reset reason will be returned. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the original reason will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 RESET_REASON(UO8 reason) #10 */ +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); + +/*! + * This function gets the partition that caused a reset. + * + * @param[in] ipc IPC handle + * @param[out] pt pointer to return the resetting partition + * + * If the reset reason obtained via sc_pm_reset_reason() is POR then the + * result from this function will be 0. Some SECO causes of reset will + * also return 0. + * + * Note depending on the connection of the WDOG_OUT signal and the OTP + * programming of the PMIC, some resets may trigger a system POR + * and the partition info will be lost. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 GET_RESET_PART(UO8 pt) #26 */ +sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function is used to boot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to boot + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered + * @param[in] resource_dev ID of the boot device that must be powered + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition, resource, or addr, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * partition to boot + * + * This must be used to boot a partition. Only a partition booted this + * way can be rebooted using the watchdog, sc_pm_boot() or + * sc_pm_reboot_partition(). + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +/* IDL: E8 BOOT(UI8 pt, UI16 resource_cpu, UI64 boot_addr, UI16 resource_mu, UI16 resource_dev) #8 */ +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to change the boot parameters for a partition. + * + * @param[in] ipc IPC handle + * @param[in] resource_cpu ID of the CPU resource to start + * @param[in] boot_addr 64-bit boot address + * @param[in] resource_mu ID of the MU that must be powered (0=none) + * @param[in] resource_dev ID of the boot device that must be powered (0=none) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource, or addr + * + * This function can be used to change the boot parameters for a partition. + * This can be useful if a partitions reboots differently from the initial + * boot done via sc_pm_boot() or via ROM. + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +/* IDL: E8 SET_BOOT_PARM(UI16 resource_cpu, UI64 boot_addr, UI16 resource_mu, UI16 resource_dev) #27 */ +sc_err_t sc_pm_set_boot_parm(sc_ipc_t ipc, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * This function is used to reboot the caller's partition. + * + * @param[in] ipc IPC handle + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * does nothing. + * + * If this function returns, then the reset did not occur due to an + * invalid parameter. A partition also cannot reboot if it is not + * isolated See sc_rm_partition_alloc(). + */ +/* IDL: RN REBOOT(UI8 type) #9 */ +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); + +/*! + * This function is used to reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to reboot + * @param[in] type reset type + * + * If \a type is SC_PM_RESET_TYPE_COLD, then most peripherals owned by + * the calling partition will be reset if possible. SC state (partitions, + * power, clocks, etc.) is reset. The boot SW of the booting CPU must be + * able to handle peripherals that that are not reset. + * + * If \a type is SC_PM_RESET_TYPE_WARM or SC_PM_RESET_TYPE_BOARD, then + * returns SC_ERR_PARM as these are not supported. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Normally the caller needs to be the parent of the partition being + * rebooted. This is not a requirement if the caller has access rights + * to the SC_R_SYSTEM resource. In other words, having access rights to + * SC_R_SYSTEM overrides the requirement to be the parent. Having access + * rights to SC_R_SYSTEM is not required if the caller is the parent of + * \a pt. + * + * Return errors: + * - SC_ERR_PARM if invalid partition or type + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * (see exception above) + * - SC_ERR_NOACCESS if \a pt is not isolated (see sc_rm_partition_alloc()) + * + * Most peripherals owned by the partition will be reset if + * possible. SC state (partitions, power, clocks, etc.) is reset. The + * boot SW of the booting CPU must be able to handle peripherals that + * that are not reset. + * + * If board_reboot_part() returns a non-0 mask, then the reboot will + * be delayed until all partitions indicated in the mask have called + * sc_pm_reboot_continue() to continue the boot. + */ +/* IDL: E8 REBOOT_PARTITION(UI8 pt, UI8 type) #12 */ +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type); + +/*! + * This function is used to continue the reboot a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to continue + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition + */ +/* IDL: E8 REBOOT_CONTINUE(UI8 pt) #25 */ +sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function is used to start/stop a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] enable start if SC_TRUE; otherwise stop + * @param[in] address 64-bit boot address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or address, + * - SC_ERR_NOACCESS if caller's partition is not the parent of the + * resource (CPU) owner + * + * This function is usually used to start a secondary CPU in the + * same partition as the caller. It is not used to start the first + * CPU in a dedicated partition. That would be started by calling + * sc_pm_boot(). + * + * A CPU started with sc_pm_cpu_start() will not restart as a result + * of a watchdog event or calling sc_pm_reboot() or sc_pm_reboot_partition(). + * Those will reboot that partition which will start the CPU started with + * sc_pm_boot(). + * + * Note the address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +/* IDL: E8 CPU_START(UI16 resource, IB enable, UI64 address) #11 */ +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address); + +/*! + * This function is used to reset a CPU. + * + * @param[in] ipc IPC handle + * @param[in] resource ID of the CPU resource + * @param[in] address 64-bit boot address + * + * This function does not return anything as the calling core may have been + * reset. It can still fail if the resource or address is invalid. It can also + * fail if the caller's partition is not the owner of the CPU, not the parent + * of the CPU resource owner, or has access to SC_R_SYSTEM. Will also fail if + * the resource is not powered on. No indication of failure is returned. + * + * Note this just resets the CPU. None of the peripherals or bus fabric used by + * the CPU is reset. State configured in the SCFW is not reset. The SW running + * on the core has to understand and deal with this. + * + * The address is limited by the hardware implementation. See the + * [CPU Start Address](@ref BOOT_ADDR) section in the Porting Guide. + */ +/* IDL: RN CPU_RESET(UI16 resource, UI64 address) #23 */ +void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address); + +/*! + * This function is used to reset a peripheral. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to reset + * + * This function will reset a resource. Most resources cannot be reset unless + * the SoC design specifically allows it. In the case on MUs, the IPC/RPC + * protocol is also reset. Note a caller cannot reset an MU that this API + * call is sent on. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource, + * - SC_ERR_PARM if resource is the MU used to make the call, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * (with grant) of the owner, + * - SC_ERR_BUSY if the resource cannot be reset due to power state of buses, + * - SC_ERR_UNAVAILABLE if the resource cannot be reset due to hardware limitations + */ +/* IDL: E8 RESOURCE_RESET(UI16 resource) #29 */ +sc_err_t sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function returns a bool indicating if a partition was started. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to check + * + * @return Returns a bool (SC_TRUE = started). + * + * Note this indicates if a partition was started. It does not indicate if a + * partition is currently running or in a low power state. + */ +/* IDL: RB IS_PARTITION_STARTED(UI8 pt) #24 */ +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); + +/** @} */ + +#endif /* SC_PM_API_H */ + +/** @} */ + diff --git a/platform/svc/pm/rpc.h b/platform/svc/pm/rpc.h new file mode 100644 index 0000000..33948fd --- /dev/null +++ b/platform/svc/pm/rpc.h @@ -0,0 +1,109 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the PM RPC implementation. + * + * @addtogroup PM_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_PM_RPC_H +#define SC_PM_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC PM function calls + */ +/** @{ */ +#define PM_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define PM_FUNC_SET_SYS_POWER_MODE 19U /*!< Index for sc_pm_set_sys_power_mode() RPC call */ +#define PM_FUNC_SET_PARTITION_POWER_MODE 1U /*!< Index for sc_pm_set_partition_power_mode() RPC call */ +#define PM_FUNC_PARTITION_POWER_OFF 30U /*!< Index for sc_pm_partition_power_off() RPC call */ +#define PM_FUNC_GET_SYS_POWER_MODE 2U /*!< Index for sc_pm_get_sys_power_mode() RPC call */ +#define PM_FUNC_PARTITION_WAKE 28U /*!< Index for sc_pm_partition_wake() RPC call */ +#define PM_FUNC_SET_RESOURCE_POWER_MODE 3U /*!< Index for sc_pm_set_resource_power_mode() RPC call */ +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U /*!< Index for sc_pm_set_resource_power_mode_all() RPC call */ +#define PM_FUNC_GET_RESOURCE_POWER_MODE 4U /*!< Index for sc_pm_get_resource_power_mode() RPC call */ +#define PM_FUNC_REQ_LOW_POWER_MODE 16U /*!< Index for sc_pm_req_low_power_mode() RPC call */ +#define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U /*!< Index for sc_pm_req_cpu_low_power_mode() RPC call */ +#define PM_FUNC_SET_CPU_RESUME_ADDR 17U /*!< Index for sc_pm_set_cpu_resume_addr() RPC call */ +#define PM_FUNC_SET_CPU_RESUME 21U /*!< Index for sc_pm_set_cpu_resume() RPC call */ +#define PM_FUNC_REQ_SYS_IF_POWER_MODE 18U /*!< Index for sc_pm_req_sys_if_power_mode() RPC call */ +#define PM_FUNC_SET_CLOCK_RATE 5U /*!< Index for sc_pm_set_clock_rate() RPC call */ +#define PM_FUNC_GET_CLOCK_RATE 6U /*!< Index for sc_pm_get_clock_rate() RPC call */ +#define PM_FUNC_CLOCK_ENABLE 7U /*!< Index for sc_pm_clock_enable() RPC call */ +#define PM_FUNC_SET_CLOCK_PARENT 14U /*!< Index for sc_pm_set_clock_parent() RPC call */ +#define PM_FUNC_GET_CLOCK_PARENT 15U /*!< Index for sc_pm_get_clock_parent() RPC call */ +#define PM_FUNC_RESET 13U /*!< Index for sc_pm_reset() RPC call */ +#define PM_FUNC_RESET_REASON 10U /*!< Index for sc_pm_reset_reason() RPC call */ +#define PM_FUNC_GET_RESET_PART 26U /*!< Index for sc_pm_get_reset_part() RPC call */ +#define PM_FUNC_BOOT 8U /*!< Index for sc_pm_boot() RPC call */ +#define PM_FUNC_SET_BOOT_PARM 27U /*!< Index for sc_pm_set_boot_parm() RPC call */ +#define PM_FUNC_REBOOT 9U /*!< Index for sc_pm_reboot() RPC call */ +#define PM_FUNC_REBOOT_PARTITION 12U /*!< Index for sc_pm_reboot_partition() RPC call */ +#define PM_FUNC_REBOOT_CONTINUE 25U /*!< Index for sc_pm_reboot_continue() RPC call */ +#define PM_FUNC_CPU_START 11U /*!< Index for sc_pm_cpu_start() RPC call */ +#define PM_FUNC_CPU_RESET 23U /*!< Index for sc_pm_cpu_reset() RPC call */ +#define PM_FUNC_RESOURCE_RESET 29U /*!< Index for sc_pm_resource_reset() RPC call */ +#define PM_FUNC_IS_PARTITION_STARTED 24U /*!< Index for sc_pm_is_partition_started() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming PM RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void pm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_PM_RPC_H */ + +/** @} */ + diff --git a/platform/svc/pm/rpc_clnt.c b/platform/svc/pm/rpc_clnt.c new file mode 100644 index 0000000..79799aa --- /dev/null +++ b/platform/svc/pm/rpc_clnt.c @@ -0,0 +1,882 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the PM service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup PM_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "svc/pm/api.h" +#include "../../main/rpc.h" +#include "svc/pm/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 SET_SYS_POWER_MODE(UI8 mode) #19 */ +sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_SYS_POWER_MODE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_PARTITION_POWER_MODE(UI8 pt, UI8 mode) #1 */ +sc_err_t sc_pm_set_partition_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_PARTITION_POWER_MODE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RN PARTITION_POWER_OFF() #30 */ +void sc_pm_partition_power_off(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_PARTITION_POWER_OFF); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_TRUE); +} + +/* IDL: E8 GET_SYS_POWER_MODE(UI8 pt, UO8 mode) #2 */ +sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_SYS_POWER_MODE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mode != NULL) + { + *mode = (sc_pm_power_mode_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 PARTITION_WAKE(UI8 pt) #28 */ +sc_err_t sc_pm_partition_wake(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_PARTITION_WAKE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RESOURCE_POWER_MODE(UI16 resource, UI8 mode) #3 */ +sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RESOURCE_POWER_MODE_ALL(UI8 pt, UI8 mode, UI16 exclude) #22 */ +sc_err_t sc_pm_set_resource_power_mode_all(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_power_mode_t mode, sc_rsrc_t exclude) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_RESOURCE_POWER_MODE_ALL); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(exclude); + RPC_U8(&msg, 2U) = U8(pt); + RPC_U8(&msg, 3U) = U8(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_RESOURCE_POWER_MODE(UI16 resource, UO8 mode) #4 */ +sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESOURCE_POWER_MODE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mode != NULL) + { + *mode = (sc_pm_power_mode_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 REQ_LOW_POWER_MODE(UI16 resource, UI8 mode) #16 */ +sc_err_t sc_pm_req_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REQ_LOW_POWER_MODE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 REQ_CPU_LOW_POWER_MODE(UI16 resource, UI8 mode, UI8 wake_src) #20 */ +sc_err_t sc_pm_req_cpu_low_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REQ_CPU_LOW_POWER_MODE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(mode); + RPC_U8(&msg, 3U) = U8(wake_src); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_CPU_RESUME_ADDR(UI16 resource, UI64 address) #17 */ +sc_err_t sc_pm_set_cpu_resume_addr(sc_ipc_t ipc, sc_rsrc_t resource, + sc_faddr_t address) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME_ADDR); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_CPU_RESUME(UI16 resource, IB isPrimary, UI64 address) #21 */ +sc_err_t sc_pm_set_cpu_resume(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CPU_RESUME); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + RPC_U8(&msg, 10U) = B2U8(isPrimary); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 REQ_SYS_IF_POWER_MODE(UI16 resource, UI8 sys_if, UI8 hpm, UI8 lpm) #18 */ +sc_err_t sc_pm_req_sys_if_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REQ_SYS_IF_POWER_MODE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(sys_if); + RPC_U8(&msg, 3U) = U8(hpm); + RPC_U8(&msg, 4U) = U8(lpm); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_CLOCK_RATE(UI16 resource, UI8 clk, UIO32 rate) #5 */ +sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_RATE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(*rate); + RPC_U16(&msg, 4U) = U16(resource); + RPC_U8(&msg, 6U) = U8(clk); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + *rate = (sc_pm_clock_rate_t) RPC_U32(&msg, 0U); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_CLOCK_RATE(UI16 resource, UI8 clk, UO32 rate) #6 */ +sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_pm_clock_rate_t *rate) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_RATE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (rate != NULL) + { + *rate = (sc_pm_clock_rate_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 CLOCK_ENABLE(UI16 resource, UI8 clk, IB enable, IB autog) #7 */ +sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable, sc_bool_t autog) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_CLOCK_ENABLE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + RPC_U8(&msg, 3U) = B2U8(enable); + RPC_U8(&msg, 4U) = B2U8(autog); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_CLOCK_PARENT(UI16 resource, UI8 clk, UI8 parent) #14 */ +sc_err_t sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_CLOCK_PARENT); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + RPC_U8(&msg, 3U) = U8(parent); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_CLOCK_PARENT(UI16 resource, UI8 clk, UO8 parent) #15 */ +sc_err_t sc_pm_get_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_CLOCK_PARENT); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(clk); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (parent != NULL) + { + *parent = (sc_pm_clk_parent_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 RESET(UI8 type) #13 */ +sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_RESET); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(type); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 RESET_REASON(UO8 reason) #10 */ +sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_RESET_REASON); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (reason != NULL) + { + *reason = (sc_pm_reset_reason_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 GET_RESET_PART(UO8 pt) #26 */ +sc_err_t sc_pm_get_reset_part(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_GET_RESET_PART); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (pt != NULL) + { + *pt = (sc_rm_pt_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 BOOT(UI8 pt, UI16 resource_cpu, UI64 boot_addr, UI16 resource_mu, UI16 resource_dev) #8 */ +sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource_cpu, + sc_faddr_t boot_addr, sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 5U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_BOOT); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(boot_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(boot_addr); + RPC_U16(&msg, 8U) = U16(resource_cpu); + RPC_U16(&msg, 10U) = U16(resource_mu); + RPC_U16(&msg, 12U) = U16(resource_dev); + RPC_U8(&msg, 14U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_BOOT_PARM(UI16 resource_cpu, UI64 boot_addr, UI16 resource_mu, UI16 resource_dev) #27 */ +sc_err_t sc_pm_set_boot_parm(sc_ipc_t ipc, sc_rsrc_t resource_cpu, + sc_faddr_t boot_addr, sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 5U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_SET_BOOT_PARM); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(boot_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(boot_addr); + RPC_U16(&msg, 8U) = U16(resource_cpu); + RPC_U16(&msg, 10U) = U16(resource_mu); + RPC_U16(&msg, 12U) = U16(resource_dev); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RN REBOOT(UI8 type) #9 */ +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(type); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_TRUE); +} + +/* IDL: E8 REBOOT_PARTITION(UI8 pt, UI8 type) #12 */ +sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_pm_reset_type_t type) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_PARTITION); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(type); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 REBOOT_CONTINUE(UI8 pt) #25 */ +sc_err_t sc_pm_reboot_continue(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_REBOOT_CONTINUE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 CPU_START(UI16 resource, IB enable, UI64 address) #11 */ +sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, + sc_faddr_t address) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_CPU_START); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + RPC_U8(&msg, 10U) = B2U8(enable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RN CPU_RESET(UI16 resource, UI64 address) #23 */ +void sc_pm_cpu_reset(sc_ipc_t ipc, sc_rsrc_t resource, sc_faddr_t address) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_CPU_RESET); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(address >> 32ULL); + RPC_U32(&msg, 4U) = U32(address); + RPC_U16(&msg, 8U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_TRUE); +} + +/* IDL: E8 RESOURCE_RESET(UI16 resource) #29 */ +sc_err_t sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_RESOURCE_RESET); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RB IS_PARTITION_STARTED(UI8 pt) #24 */ +sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = U8(PM_FUNC_IS_PARTITION_STARTED); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_bool_t) U2B(RPC_R8(&msg)); + + /* Return result */ + return result; +} + +/** @} */ + diff --git a/platform/svc/pm/rpc_srv.c b/platform/svc/pm/rpc_srv.c new file mode 100644 index 0000000..a59589c --- /dev/null +++ b/platform/svc/pm/rpc_srv.c @@ -0,0 +1,628 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the PM service. + * + * @addtogroup PM_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/pm/svc.h" +#include "svc/pm/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void pm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case PM_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch set_sys_power_mode() */ + case PM_FUNC_SET_SYS_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = pm_set_sys_power_mode(caller_pt, mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_partition_power_mode() */ + case PM_FUNC_SET_PARTITION_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = pm_set_partition_power_mode(caller_pt, pt, mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch partition_power_off() */ + case PM_FUNC_PARTITION_POWER_OFF : + { + /* Declare return and parameters */ + + /* Call function */ + pm_partition_power_off(caller_pt); + + /* Copy in return parameters */ + RPC_SIZE(msg) = 0U; + break; + } + /* Dispatch get_sys_power_mode() */ + case PM_FUNC_GET_SYS_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) 0U); + + /* Call function */ + err = pm_get_sys_power_mode(caller_pt, pt, &mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mode); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch partition_wake() */ + case PM_FUNC_PARTITION_WAKE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = pm_partition_wake(caller_pt, pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_resource_power_mode() */ + case PM_FUNC_SET_RESOURCE_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) RPC_U8(msg, 2U)); + + /* Call function */ + err = pm_set_resource_power_mode(mu, resource, mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_resource_power_mode_all() */ + case PM_FUNC_SET_RESOURCE_POWER_MODE_ALL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 2U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) RPC_U8(msg, 3U)); + sc_rsrc_t exclude = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + err = pm_set_resource_power_mode_all(caller_pt, pt, mode, + exclude); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_resource_power_mode() */ + case PM_FUNC_GET_RESOURCE_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) 0U); + + /* Call function */ + err = pm_get_resource_power_mode(caller_pt, resource, &mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mode); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch req_low_power_mode() */ + case PM_FUNC_REQ_LOW_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) RPC_U8(msg, 2U)); + + /* Call function */ + err = pm_req_low_power_mode(caller_pt, resource, mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch req_cpu_low_power_mode() */ + case PM_FUNC_REQ_CPU_LOW_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_power_mode_t mode = ((sc_pm_power_mode_t) RPC_U8(msg, 2U)); + sc_pm_wake_src_t wake_src = ((sc_pm_wake_src_t) RPC_U8(msg, 3U)); + + /* Call function */ + err = pm_req_cpu_low_power_mode(caller_pt, resource, mode, + wake_src); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_cpu_resume_addr() */ + case PM_FUNC_SET_CPU_RESUME_ADDR : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_faddr_t address = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = pm_set_cpu_resume_addr(caller_pt, resource, address); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_cpu_resume() */ + case PM_FUNC_SET_CPU_RESUME : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_bool_t isPrimary = U2B(RPC_U8(msg, 10U)); + sc_faddr_t address = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = pm_set_cpu_resume(caller_pt, resource, isPrimary, + address); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch req_sys_if_power_mode() */ + case PM_FUNC_REQ_SYS_IF_POWER_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_sys_if_t sys_if = ((sc_pm_sys_if_t) RPC_U8(msg, 2U)); + sc_pm_power_mode_t hpm = ((sc_pm_power_mode_t) RPC_U8(msg, 3U)); + sc_pm_power_mode_t lpm = ((sc_pm_power_mode_t) RPC_U8(msg, 4U)); + + /* Call function */ + err = pm_req_sys_if_power_mode(caller_pt, resource, sys_if, hpm, + lpm); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_clock_rate() */ + case PM_FUNC_SET_CLOCK_RATE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 4U)); + sc_pm_clk_t clk = ((sc_pm_clk_t) RPC_U8(msg, 6U)); + sc_pm_clock_rate_t rate = ((sc_pm_clock_rate_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = pm_set_clock_rate(caller_pt, resource, clk, &rate); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(rate); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch get_clock_rate() */ + case PM_FUNC_GET_CLOCK_RATE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_clk_t clk = ((sc_pm_clk_t) RPC_U8(msg, 2U)); + sc_pm_clock_rate_t rate = ((sc_pm_clock_rate_t) 0U); + + /* Call function */ + err = pm_get_clock_rate(caller_pt, resource, clk, &rate); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(rate); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch clock_enable() */ + case PM_FUNC_CLOCK_ENABLE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_clk_t clk = ((sc_pm_clk_t) RPC_U8(msg, 2U)); + sc_bool_t enable = U2B(RPC_U8(msg, 3U)); + sc_bool_t autog = U2B(RPC_U8(msg, 4U)); + + /* Call function */ + err = pm_clock_enable(caller_pt, resource, clk, enable, autog); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_clock_parent() */ + case PM_FUNC_SET_CLOCK_PARENT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_clk_t clk = ((sc_pm_clk_t) RPC_U8(msg, 2U)); + sc_pm_clk_parent_t parent = ((sc_pm_clk_parent_t) RPC_U8(msg, 3U)); + + /* Call function */ + err = pm_set_clock_parent(caller_pt, resource, clk, parent); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_clock_parent() */ + case PM_FUNC_GET_CLOCK_PARENT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_pm_clk_t clk = ((sc_pm_clk_t) RPC_U8(msg, 2U)); + sc_pm_clk_parent_t parent = ((sc_pm_clk_parent_t) 0U); + + /* Call function */ + err = pm_get_clock_parent(caller_pt, resource, clk, &parent); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(parent); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch reset() */ + case PM_FUNC_RESET : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pm_reset_type_t type = ((sc_pm_reset_type_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = pm_reset(caller_pt, type); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch reset_reason() */ + case PM_FUNC_RESET_REASON : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pm_reset_reason_t reason = ((sc_pm_reset_reason_t) 0U); + + /* Call function */ + err = pm_reset_reason(caller_pt, &reason); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(reason); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch get_reset_part() */ + case PM_FUNC_GET_RESET_PART : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) 0U); + + /* Call function */ + err = pm_get_reset_part(caller_pt, &pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(pt); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch boot() */ + case PM_FUNC_BOOT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 14U)); + sc_rsrc_t resource_cpu = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_faddr_t boot_addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_rsrc_t resource_mu = ((sc_rsrc_t) RPC_U16(msg, 10U)); + sc_rsrc_t resource_dev = ((sc_rsrc_t) RPC_U16(msg, 12U)); + + /* Call function */ + err = pm_boot(caller_pt, pt, resource_cpu, boot_addr, + resource_mu, resource_dev); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_boot_parm() */ + case PM_FUNC_SET_BOOT_PARM : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource_cpu = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_faddr_t boot_addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_rsrc_t resource_mu = ((sc_rsrc_t) RPC_U16(msg, 10U)); + sc_rsrc_t resource_dev = ((sc_rsrc_t) RPC_U16(msg, 12U)); + + /* Call function */ + err = pm_set_boot_parm(caller_pt, resource_cpu, boot_addr, + resource_mu, resource_dev); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch reboot() */ + case PM_FUNC_REBOOT : + { + /* Declare return and parameters */ + sc_pm_reset_type_t type = ((sc_pm_reset_type_t) RPC_U8(msg, 0U)); + + /* Call function */ + pm_reboot(caller_pt, type); + + /* Copy in return parameters */ + RPC_SIZE(msg) = 0U; + break; + } + /* Dispatch reboot_partition() */ + case PM_FUNC_REBOOT_PARTITION : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_pm_reset_type_t type = ((sc_pm_reset_type_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = pm_reboot_partition(caller_pt, pt, type); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch reboot_continue() */ + case PM_FUNC_REBOOT_CONTINUE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = pm_reboot_continue(caller_pt, pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch cpu_start() */ + case PM_FUNC_CPU_START : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_bool_t enable = U2B(RPC_U8(msg, 10U)); + sc_faddr_t address = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = pm_cpu_start(caller_pt, resource, enable, address); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch cpu_reset() */ + case PM_FUNC_CPU_RESET : + { + /* Declare return and parameters */ + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 8U)); + sc_faddr_t address = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + pm_cpu_reset(caller_pt, resource, address); + + /* Copy in return parameters */ + RPC_SIZE(msg) = 0U; + break; + } + /* Dispatch resource_reset() */ + case PM_FUNC_RESOURCE_RESET : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + err = pm_resource_reset(mu, resource); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch is_partition_started() */ + case PM_FUNC_IS_PARTITION_STARTED : + { + /* Declare return and parameters */ + sc_bool_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + + /* Call function */ + result = pm_is_partition_started(caller_pt, pt); + + /* Copy in return parameters */ + RPC_R8(msg) = B2U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=pm, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=pm, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/pm/svc.c b/platform/svc/pm/svc.c new file mode 100755 index 0000000..276f6d5 --- /dev/null +++ b/platform/svc/pm/svc.c @@ -0,0 +1,1920 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/pm/svc.c + * + * File containing the implementation of the System Controller (SC) Power + * Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * @addtogroup PM_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "main/boot.h" +#include "main/soc.h" +#include "svc/pm/svc.h" +#include "svc/rm/svc.h" +#include "svc/timer/svc.h" +#include "ss/inf/inf.h" +#include "ss_ver.h" +#if SS_VER_BASE == 1 +#include "ss/base/v1/ss.h" +#endif +#include "drivers/sysctr/fsl_sysctr.h" + +/* Local Defines */ + +/*! + * @name Parameter checking macros + */ +/** @{ */ +#define BOUND_MODE(X) ASRT_ERR((X) <= SC_PM_PW_MODE_ON, SC_ERR_PARM) +#define BOUND_CLK(X) ASRT_ERR((X) < SS_MAX_PM_CLKS, SC_ERR_PARM) +/** @} */ + +/*! + * @name Patition power flags + */ +/** @{ */ +#define PM_PART_INIT BIT32(0U) +#define PM_PART_FINAL BIT32(1U) +#define PM_PART_REBOOT BIT32(2U) +/** @} */ + +/* Local Types */ + +/*! + * This type is used to store dynamic info needed to track partition + * specific data for the power management service. + */ +typedef struct +{ + sc_faddr_t boot_addr; + uint32_t reboot_mask; + sc_rsrc_t boot_cpu : SC_RSRC_W; + sc_rsrc_t boot_mu : SC_RSRC_W; + sc_rsrc_t boot_dev : SC_RSRC_W; + sc_rm_pt_t reason_pt : SC_RM_PARTITION_W; + sc_pm_reset_reason_t reason : SC_PM_RESET_REASON_W; + sc_pm_power_mode_t mode : SC_PM_CLOCK_MODE_W; + sc_pm_reset_type_t type : SC_PM_RESET_TYPE_W; + sc_pm_power_mode_t sys_mode : SC_PM_POWER_MODE_W; + sc_bool_t booted : SC_BOOL_W; +} pm_part_data_t; + +/*! + * This type is used to store dynamic info needed to track resource + * specific data for the power management service. + */ +typedef struct +{ + sc_pm_power_mode_t rsrc_mode : SC_PM_POWER_MODE_W; + sc_pm_power_mode_t user_mode : SC_PM_POWER_MODE_W; +} pm_rsrc_data_t; + +/* Local Functions */ + +static void ss_cpu_stop_all(sc_rm_pt_t pt); +static sc_err_t pm_reboot_cont(sc_rm_pt_t pt); +static sc_err_t pm_part_off(sc_rm_pt_t pt, uint32_t flags); + +/* Local Variables */ + +/*! + * @name Local Variables + * + * @{ + */ +static pm_part_data_t pm_part_data[SC_RM_NUM_PARTITION]; +static pm_rsrc_data_t pm_rsrc_data[SC_NUM_RSRC]; +/** @} */ + +/*--------------------------------------------------------------------------*/ +/* Init the power management service */ +/*--------------------------------------------------------------------------*/ +void pm_init(sc_bool_t api_phase) +{ + if (api_phase != SC_FALSE) + { + sc_rm_pt_t pt; + + /* Init partition data */ + for (pt = 0U; pt < SC_RM_NUM_PARTITION; pt++) + { + pm_part_data[pt].sys_mode = SC_PM_PW_MODE_ON; + pm_part_data[pt].boot_cpu = SC_NUM_RESOURCE; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Initialize a new partition */ +/*--------------------------------------------------------------------------*/ +void pm_init_part(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + /* Update partition power mode */ + pm_part_data[pt].sys_mode = SC_PM_PW_MODE_ON; + pm_part_data[pt].reboot_mask = 0U; +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for a resource index */ +/*--------------------------------------------------------------------------*/ +void pm_init_rsrc_power_mode(sc_rsrc_t rsrc, sc_pm_power_mode_t mode) +{ + sc_rm_idx_t idx= 0U; + + if (rm_check_map_ridx(rsrc, &idx) != SC_FALSE) + { + sc_sub_t ss; + sc_ss_idx_t ss_idx; + + pm_rsrc_data[idx].rsrc_mode = SC_PM_PW_MODE_ON; + + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + ss_init_boot_base(ss, ss_idx, SC_PM_PW_MODE_ON); + } +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for the system */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_sys_power_mode(sc_rm_pt_t caller_pt, sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_MODE(mode); + + /* Check permissions */ + SYSTEM(caller_pt); + + /* Set power mode */ + if (err == SC_ERR_NONE) + { + err = board_power(mode); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Init partition to off */ +/*--------------------------------------------------------------------------*/ +void pm_init_partition_power_off(sc_rm_pt_t pt) +{ + pm_part_data[pt].sys_mode = SC_PM_PW_MODE_OFF; +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_partition_power_mode(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + ASRT_ERR(mode == SC_PM_PW_MODE_OFF, SC_ERR_PARM) + + /* Check parameters */ + USED_PT(pt); + ASRT_ERR(caller_pt != pt, SC_ERR_PARM) + + /* Check ownership */ + if (rm_get_control_partition(pt) != caller_pt) + { + ANCESTOR(pt); + } + + if (err == SC_ERR_NONE) + { + /* Power off partition */ + err = pm_part_off(pt, PM_PART_INIT | PM_PART_FINAL); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for calling partition */ +/*--------------------------------------------------------------------------*/ +void pm_partition_power_off(sc_rm_pt_t caller_pt) +{ + /* Power off partition */ + (void) pm_part_off(caller_pt, PM_PART_INIT | PM_PART_FINAL); +} + +/*--------------------------------------------------------------------------*/ +/* Update power mode for a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_update_partition_power_mode(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + BOUND_MODE(mode); + + /* Check parameters */ + USED_PT(pt); + ASRT_ERR((pt != SC_PT) || (mode != SC_PM_PW_MODE_OFF), SC_ERR_PARM); + + /* Check ownership */ + ANCESTOR(pt); + + if (err == SC_ERR_NONE) + { + sc_rm_idx_t idx = 0U; + + /* Save partition system power mode */ + pm_part_data[pt].sys_mode = mode; + + /* Update all resources */ + for (idx = SC_NUM_RSRC - 1U; idx > 0U; idx--) + { + pm_update_ridx(idx); + } + pm_update_ridx(0U); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Send wake interrupt to a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_partition_wake(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Send interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_WAKE, SC_IRQ_SW_WAKE, pt); + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get power mode for a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_get_sys_power_mode(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + USED_PT(pt); + + if (err == SC_ERR_NONE) + { + /* Return partition power mode */ + *mode = pm_part_data[pt].sys_mode; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update the power state of a resource */ +/*--------------------------------------------------------------------------*/ +void pm_update_ridx(sc_rm_idx_t idx) +{ + sc_rm_pt_t pt = 0U; + sc_pm_power_mode_t to_mode; + + /* Get resource info */ + rm_get_ridx_owner(idx, &pt); + + /* Determine new resource power mode. New mode is the mimumum + * of the user-specified power mode of the resource and the + * power mode of the partition owning the resource. + */ + to_mode = MIN(pm_rsrc_data[idx].user_mode, pm_part_data[pt].sys_mode); + + /* Resource power mode changed? */ + if (to_mode != pm_rsrc_data[idx].rsrc_mode) + { + sc_bool_t no_reset = SC_FALSE; + + /* Reset resource */ + if (to_mode == SC_PM_PW_MODE_OFF) + { + /* Will return a SC_TRUE if resource is in + * use and power mode should remain unchanged + */ + no_reset = soc_reboot_no_reset(idx); + } + + if (no_reset == SC_FALSE) + { + sc_pm_power_mode_t from_mode; + + /* Block access via HW? */ + (void) rm_ridx_block(idx, to_mode < SC_PM_PW_MODE_LP); + (void) rm_update_peripheral(idx); + + /* Call SS to transition resource power mode */ + from_mode = pm_rsrc_data[idx].rsrc_mode; + + /* + * Certain power state transitions require clocks so we may need to + * do two steps to acheive it. + */ + if (CLKOFFTRANS()) + { + soc_clk_off_trans = SC_TRUE; + ss_trans_power_mode(idx, from_mode, SC_PM_PW_MODE_LP); + ss_trans_power_mode(idx, SC_PM_PW_MODE_LP, to_mode); + } + else + { + soc_clk_off_trans = SC_FALSE; + ss_trans_power_mode(idx, from_mode, to_mode); + } + + /* Save new resource power mode */ + pm_rsrc_data[idx].rsrc_mode = to_mode; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for a resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_resource_power_mode(sc_rsrc_t mu, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_err_t err; + sc_rm_pt_t caller_pt = SC_PT; + + /* Get calling partition */ + err = rm_get_resource_owner(SC_PT, mu, &caller_pt); + + /* Check to insure not disabling MU we are calling on */ + ASRT_ERR((mu != resource) || (mode > SC_PM_PW_MODE_STBY), SC_ERR_PARM); + + /* Error? */ + if (err == SC_ERR_NONE) + { + err = pm_set_resource_power_mode_pt(caller_pt, resource, mode); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for a resource via pt */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_resource_power_mode_pt(sc_rm_pt_t caller_pt, + sc_rsrc_t resource, sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + sc_rsrc_t r0, rN; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_MODE(mode); + + /* Is one or all resources? */ + if (resource == SC_R_ALL) + { + /* Set range to cover all resources */ + r0 = 0U; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + sc_pm_power_mode_t from_mode; + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + /* Check ownership */ + if (caller_pt != SC_PT) + { + ACCESS_ALLOWED(caller_pt, idx); + } + + /* Set range to cover only the specified resource */ + r0 = resource; + rN = resource; + + from_mode = pm_rsrc_data[idx].rsrc_mode; + if ((from_mode == SC_PM_PW_MODE_OFF) && (mode == SC_PM_PW_MODE_STBY)) + { + err = SC_ERR_PARM; + } + } + + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = r0; r <= rN; r++) + { + if (resource == SC_R_ALL) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + + /* Check ownership */ + ACCESS_ALLOWED_C(caller_pt, idx); + } + pm_set_rsrc_power_mode(idx, mode); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for all resources in a child partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_resource_power_mode_all(sc_rm_pt_t caller_pt, + sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + BOUND_MODE(mode); + + /* Check parameters */ + USED_PT(pt); + + /* Check access */ + ASRT_ERR(rm_is_parent(caller_pt, pt) != SC_FALSE, + SC_ERR_NOACCESS); + + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = 0U; r <= (SC_NUM_RESOURCE - 1U); r++) + { + sc_rm_idx_t idx = 0U; + sc_rm_pt_t owner = 0U; + + /* Exclude? */ + ASRT_C(r != exclude); + + /* Get resoure index */ + BOUND_RSRC_C(r, idx); + + /* Correct partition? */ + rm_get_ridx_owner(idx, &owner); + if (owner != pt) + { + continue; + } + pm_set_rsrc_power_mode(idx, mode); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set power mode for a resource index */ +/*--------------------------------------------------------------------------*/ +void pm_set_rsrc_power_mode(sc_rm_idx_t idx, sc_pm_power_mode_t mode) +{ + /* Check availability */ + if (rm_is_ridx_avail(idx) != SC_FALSE) + { + sc_pm_power_mode_t from_mode; + + from_mode = pm_rsrc_data[idx].rsrc_mode; + + if ((from_mode != SC_PM_PW_MODE_OFF) + || (mode != SC_PM_PW_MODE_STBY)) + { + /* Save user-specified resource power mode */ + pm_rsrc_data[idx].user_mode = mode; + + /* Update resource */ + pm_update_ridx(idx); + + /* Reflect mode achieved during update */ + pm_rsrc_data[idx].user_mode = pm_rsrc_data[idx].rsrc_mode; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Update power mode for a resource index */ +/*--------------------------------------------------------------------------*/ +void pm_set_active_rsrc_power_mode(sc_rm_idx_t idx, sc_pm_power_mode_t mode) +{ + /* Check availability */ + if (rm_is_ridx_avail(idx) != SC_FALSE) + { + sc_pm_power_mode_t from_mode; + + from_mode = pm_rsrc_data[idx].rsrc_mode; + + if ((from_mode != SC_PM_PW_MODE_OFF) + || (mode != SC_PM_PW_MODE_STBY)) + { + sc_rm_pt_t pt = 0U; + sc_pm_power_mode_t sys_mode; + + /* Save user-specified resource power mode */ + pm_rsrc_data[idx].user_mode = mode; + + /* Save partition state */ + rm_get_ridx_owner(idx, &pt); + sys_mode = pm_part_data[pt].sys_mode; + pm_part_data[pt].sys_mode = SC_PM_PW_MODE_ON; + + /* Update resource */ + pm_update_ridx(idx); + + /* Restore partition state */ + pm_part_data[pt].sys_mode = sys_mode; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Force power mode for a resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_force_resource_power_mode(sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_RSRC(resource, idx); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + sc_pm_power_mode_t from_mode; + + from_mode = pm_rsrc_data[idx].rsrc_mode; + + if ((from_mode == SC_PM_PW_MODE_OFF) && (mode == SC_PM_PW_MODE_STBY)) + { + err = SC_ERR_PARM; + } + else + { + /* Update resource power mode */ + pm_set_rsrc_power_mode(idx, mode); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Force power mode for a resource (no return) */ +/*--------------------------------------------------------------------------*/ +void pm_force_resource_power_mode_v(sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + sc_pm_power_mode_t from_mode; + + from_mode = pm_rsrc_data[idx].rsrc_mode; + + if ((from_mode != SC_PM_PW_MODE_OFF) || (mode != SC_PM_PW_MODE_STBY)) + { + /* Save user-specified resource power mode */ + pm_rsrc_data[idx].user_mode = mode; + + /* Update resource */ + pm_update_ridx(idx); + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Get power mode for a resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_get_resource_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_power_mode_t *mode) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + /* Return resource power mode */ + *mode = pm_rsrc_data[idx].user_mode; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get power mode for a resource index */ +/*--------------------------------------------------------------------------*/ +void pm_get_rsrc_power_mode(sc_rm_idx_t idx, sc_pm_power_mode_t *mode) +{ + /* Check availability */ + if (rm_is_ridx_avail(idx) == SC_FALSE) + { + *mode = SC_PM_PW_MODE_OFF; + } + else + { + *mode = pm_rsrc_data[idx].user_mode; + } +} + +/*--------------------------------------------------------------------------*/ +/* Get active power mode for a resource index */ +/*--------------------------------------------------------------------------*/ +void pm_get_active_rsrc_power_mode(sc_rm_idx_t idx, sc_pm_power_mode_t *mode) +{ + /* Check availability */ + if (rm_is_ridx_avail(idx) == SC_FALSE) + { + *mode = SC_PM_PW_MODE_OFF; + } + else + { + *mode = pm_rsrc_data[idx].rsrc_mode; + } +} + +/*--------------------------------------------------------------------------*/ +/* Request low power mode for a resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_req_low_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx= 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_MODE(mode); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + /* Set CPU power mode */ + err = ss_set_cpu_power_mode(idx, mode, SC_PM_WAKE_SRC_GIC); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Request low power mode for a CPU resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_req_cpu_low_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx= 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_MODE(mode); + ASRT_ERR(wake_src <= SC_PM_WAKE_SRC_GIC, SC_ERR_PARM); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Set CPU power mode */ + err = ss_set_cpu_power_mode(idx, mode, wake_src); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the resume address of a CPU */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_cpu_resume_addr(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_faddr_t address) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_pt_t owner_pt = 0U; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check ownership */ + if (err == SC_ERR_NONE) + { + rm_get_ridx_owner(idx, &owner_pt); + ASRT_ERR(rm_is_parent(caller_pt, owner_pt) || (caller_pt == owner_pt), + SC_ERR_NOACCESS); + } + + /* Set the resume address of the CPU */ + if (err == SC_ERR_NONE) + { + err = ss_set_cpu_resume(idx, SC_FALSE, address); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the resume parameters of a CPU */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_cpu_resume(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_pt_t owner_pt = 0U; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check ownership */ + if (err == SC_ERR_NONE) + { + rm_get_ridx_owner(idx, &owner_pt); + ASRT_ERR(rm_is_parent(caller_pt, owner_pt) || (caller_pt == owner_pt), + SC_ERR_NOACCESS); + } + + /* Set the resume address of the CPU */ + if (err == SC_ERR_NONE) + { + err = ss_set_cpu_resume(idx, isPrimary, address); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Request power mode for system-level interfaces including messaging */ +/* units, interconnect, and memories. */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_req_sys_if_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + ASRT_ERR(sys_if <= SC_PM_SYS_IF_DDR, SC_ERR_PARM); + ASRT_ERR((hpm <= SC_PM_PW_MODE_ON) && + (lpm <= SC_PM_PW_MODE_ON) && + (lpm <= hpm), SC_ERR_PARM); + + /* Check ownership */ + OWNED(resource); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Set interface power mode */ + err = ss_req_sys_if_power_mode(idx, sys_if, hpm, lpm); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get functional state of a resource */ +/*--------------------------------------------------------------------------*/ +sc_bool_t pm_is_resource_accessible(sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_RSRC(resource, idx); + + /* Call SS to inquire about the resource */ + if (err == SC_ERR_NONE) + { + rtn = ss_is_rsrc_accessible(idx); + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Set rate for a resource's clock (0 = gated) */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_clock_rate(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_CLK(clk); + ASRT_ERR(*rate != 0U, SC_ERR_PARM); + + /* Check ownership */ + ASRT_ERR((caller_pt == SC_PT) || rm_is_ridx_access_allowed(caller_pt, + idx), SC_ERR_NOACCESS); + + /* Call SS to set clock rate */ + if (err == SC_ERR_NONE) + { + err = ss_set_clock_rate(idx, clk, rate); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get rate for a resource's clock (0 = gated) */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_get_clock_rate(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_CLK(clk); + + if (err == SC_ERR_NONE) + { + /* Call SS to get clock rates */ + err = ss_get_clock_rate(idx, clk, rate); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Enable/disable for a resource's clock */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_clock_enable(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + sc_rsrc_t r0 = 0U; + sc_rsrc_t rN = 0U; + sc_pm_power_mode_t mode; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check if resource is powered */ + if (err == SC_ERR_NONE) + { + err = pm_get_resource_power_mode(caller_pt, resource, &mode); + } + if (err == SC_ERR_NONE) + { + if (mode == SC_PM_PW_MODE_OFF) + { + err = SC_ERR_NOPOWER; + } + + /* Is one or all resources? */ + if (resource == SC_R_ALL) + { + /* Set range to cover all resources */ + r0 = 0U; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + /* Check parameters */ + BOUND_RSRC(resource, idx); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + /* Set range to cover only the specified resource */ + r0 = resource; + rN = resource; + } + } + + if (err == SC_ERR_NONE) + { + sc_pm_clk_t c0, cN; + + /* Is one or all clock? */ + if (clk == SC_PM_CLK_ALL) + { + /* Set range to cover all clocks */ + c0 = 0U; + cN = SS_MAX_PM_CLKS - 1U; + } + else + { + /* Check parameters */ + BOUND_CLK(clk); + + /* Set range to cover only the specified clock */ + c0 = clk; + cN = clk; + } + + /* Process range of resources */ + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + sc_pm_clk_t c; + + for (r = r0; r <= rN; r++) + { + if (resource == SC_R_ALL) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + + /* Check ownership */ + ACCESS_ALLOWED_C(caller_pt, idx); + } + + /* Process range of clocks */ + for (c = c0; c <= cN; c++) + { + err = ss_clock_enable(idx, c, enable, autog); + if (err == SC_ERR_NONE) + { + continue; + } + + /* For all resources, do not return an error */ + if (resource == SC_R_ALL) + { + err = SC_ERR_NONE; + continue; + } + + /* For all clocks, return err only if available */ + if (clk != SC_PM_CLK_ALL) + { + break; + } + if (err != SC_ERR_UNAVAILABLE) + { + break; + } + } + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Force enable of a resource's clock */ +/*--------------------------------------------------------------------------*/ +void pm_force_clock_enable(sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_RSRC(resource, idx); + BOUND_CLK(clk); + + if (err == SC_ERR_NONE) + { + /* Call SS to set clock mode */ + (void) ss_force_clock_enable(idx, clk, enable); + } +} + +/*--------------------------------------------------------------------------*/ +/* Set Parent of a resource's clock */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_clock_parent(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_CLK(clk); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + /* Call SS to set clock mode */ + err = ss_set_clock_parent(idx, clk, parent); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set Parent of a resource's clock */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_get_clock_parent(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0U; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + BOUND_CLK(clk); + + if (err == SC_ERR_NONE) + { + /* Call SS to set clock mode */ + err = ss_get_clock_parent(idx, clk, parent); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Boot a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_boot(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, sc_rsrc_t resource_cpu, + sc_faddr_t boot_addr, sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t boot_cpu_idx = 0U; + sc_rm_idx_t boot_mu_idx = 0U; + sc_pm_power_mode_t mode = SC_PM_PW_MODE_OFF; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + BOUND_RSRC(resource_cpu, boot_cpu_idx); + BOUND_RSRC(resource_mu, boot_mu_idx); + + /* Check ownership */ + if (rm_get_control_partition(pt) != caller_pt) + { + ANCESTOR(pt); + } + + /* Check CPU and MU ownership */ + OWNER(pt, resource_cpu); + OWNER(pt, resource_mu); + +#ifdef ERR050601_WORKAROUND + /* Block this partition if AP */ + soc_block_ap_set(pt, resource_cpu); +#endif + + /* Power on partition */ + if (err == SC_ERR_NONE) + { + err = pm_update_partition_power_mode(SC_PT, pt, + SC_PM_PW_MODE_ON); + } + + if (err == SC_ERR_NONE) + { + /* Prep CPU */ + main_prep_cpu(resource_cpu, resource_mu); + + /* Check power */ + (void) pm_get_rsrc_power_mode(boot_cpu_idx, &mode); + ASRT_ERR(mode > SC_PM_PW_MODE_STBY, SC_ERR_NOPOWER); + } + + if (err == SC_ERR_NONE) + { + /* Record info */ + pm_part_data[pt].boot_cpu = resource_cpu; + pm_part_data[pt].boot_mu = resource_mu; + pm_part_data[pt].boot_dev = resource_dev; + pm_part_data[pt].boot_addr = boot_addr; + pm_part_data[pt].reason = SC_PM_RESET_REASON_POR; + pm_part_data[pt].reason_pt = SC_PT; + pm_part_data[pt].booted = SC_FALSE; + + /* Set cold boot flag in MU */ + ss_mu_irq(boot_mu_idx, SC_RPC_MU_GIR_BOOT); + + /* Start/stop CPU */ + err = ss_cpu_start(boot_cpu_idx, SC_TRUE, boot_addr); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set partition boot parameters */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_set_boot_parm(sc_rm_pt_t caller_pt, sc_rsrc_t resource_cpu, + sc_faddr_t boot_addr, sc_rsrc_t resource_mu, sc_rsrc_t resource_dev) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check ownership of CPU */ + OWNED(resource_cpu); + + /* Conditionally check ownership of MU */ + if (resource_mu != 0U) + { + OWNED(resource_mu); + } + + /* Conditionally check ownership of boot device */ + if (resource_dev != 0U) + { + OWNED(resource_dev); + } + + if (err == SC_ERR_NONE) + { + /* Record info */ + pm_part_data[caller_pt].boot_cpu = resource_cpu; + pm_part_data[caller_pt].boot_mu = resource_mu; + pm_part_data[caller_pt].boot_dev = resource_dev; + pm_part_data[caller_pt].boot_addr = boot_addr; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get partition boot parameters */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_get_boot_parm(sc_rm_pt_t caller_pt, sc_rsrc_t *resource_cpu, + sc_faddr_t *boot_addr, sc_rsrc_t *resource_mu, sc_rsrc_t *resource_dev) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Return info */ + *resource_cpu = pm_part_data[caller_pt].boot_cpu; + *resource_mu = pm_part_data[caller_pt].boot_mu; + *resource_dev = pm_part_data[caller_pt].boot_dev; + *boot_addr = pm_part_data[caller_pt].boot_addr; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reboot caller's partition */ +/*--------------------------------------------------------------------------*/ +void pm_reboot(sc_rm_pt_t caller_pt, sc_pm_reset_type_t type) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Reboot partition */ + (void) pm_reboot_part(caller_pt, caller_pt, type, + SC_PM_RESET_REASON_SW, SC_PM_PW_MODE_OFF); + } +} + +/*--------------------------------------------------------------------------*/ +/* Get reset reason */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_reset_reason(sc_rm_pt_t caller_pt, sc_pm_reset_reason_t *reason) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Return reason */ + *reason = pm_part_data[caller_pt].reason; + if (*reason == SC_PM_RESET_REASON_POR) + { + *reason = soc_reset_reason(); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get partition causing reset */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_get_reset_part(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Return part */ + *pt = pm_part_data[caller_pt].reason_pt; + if (pm_part_data[caller_pt].reason == SC_PM_RESET_REASON_POR) + { + *pt = soc_reset_part(); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Start/stop a CPU */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_cpu_start(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_bool_t enable, sc_faddr_t address) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_pt_t owner_pt = 0U; + sc_rm_idx_t idx = 0U; + sc_pm_power_mode_t mode = SC_PM_PW_MODE_OFF; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + /* Check ownership */ + rm_get_ridx_owner(idx, &owner_pt); + ASRT_ERR(rm_is_parent(caller_pt, owner_pt) || (caller_pt == owner_pt), + SC_ERR_NOACCESS); + } + + if (err == SC_ERR_NONE) + { + /* Check power */ + pm_get_rsrc_power_mode(idx, &mode); + if (enable) + { + ASRT_ERR(mode > SC_PM_PW_MODE_STBY, SC_ERR_NOPOWER); + } + } + + if (err == SC_ERR_NONE) + { + /* Start/stop CPU */ + err = ss_cpu_start(idx, enable, address); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset a CPU */ +/*--------------------------------------------------------------------------*/ +void pm_cpu_reset(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_faddr_t address) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_pt_t owner_pt = 0U; + sc_rm_idx_t idx = 0U; + sc_pm_power_mode_t mode = SC_PM_PW_MODE_OFF; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + /* Check ownership */ + rm_get_ridx_owner(idx, &owner_pt); + ASRT_ERR(rm_is_parent(caller_pt, owner_pt) || (caller_pt == owner_pt) + || rm_is_sys_access(caller_pt), SC_ERR_NOACCESS); + } + + if (err == SC_ERR_NONE) + { + /* Check power */ + pm_get_rsrc_power_mode(idx, &mode); + ASRT_ERR(mode > SC_PM_PW_MODE_STBY, SC_ERR_NOPOWER); + } + + if (err == SC_ERR_NONE) + { + /* Stop and start CPU */ + (void) ss_cpu_start(idx, SC_FALSE, address); + (void) ss_cpu_start(idx, SC_TRUE, address); + } +} + +/*--------------------------------------------------------------------------*/ +/* Reset a resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_resource_reset(sc_rsrc_t mu, sc_rsrc_t resource) +{ + sc_err_t err; + sc_rm_idx_t idx= 0U; + sc_rm_pt_t caller_pt; + + /* Get calling partition */ + err = rm_get_resource_owner(SC_PT, mu, &caller_pt); + + /* Check to insure not resetting MU we are calling on */ + ASRT_ERR(mu != resource, SC_ERR_PARM); + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check ownership */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + err = ss_rsrc_reset(idx, SC_PT_ALL, SC_FALSE); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reboot a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_reboot_partition(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_reset_type_t type) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + ASRT_ERR(type == SC_PM_RESET_TYPE_COLD, SC_ERR_PARM); + USED_PT(pt); + + /* Check permissions */ + if (rm_get_control_partition(pt) != caller_pt) + { + ASRT_ERR(rm_is_sys_access(caller_pt) || rm_is_parent(caller_pt, pt), + SC_ERR_NOACCESS); + } + + /* Reboot partition */ + if (err == SC_ERR_NONE) + { + err = pm_reboot_part(caller_pt, pt, type, SC_PM_RESET_REASON_SW, + SC_PM_PW_MODE_OFF); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reset system */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_reset(sc_rm_pt_t caller_pt, sc_pm_reset_type_t type) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(type <= SC_PM_RESET_TYPE_BOARD, SC_ERR_PARM); + + /* Check permissions */ + SYSTEM(caller_pt); + + /* Do reset */ + if (err == SC_ERR_NONE) + { + err = board_reset(type, SC_PM_RESET_REASON_SW, caller_pt); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reboot a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_reboot_part(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_pm_power_mode_t mode) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t boot_cpu_idx; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + USED_PT(pt); + + /* Bounds check */ + ASRT_ERR(type == SC_PM_RESET_TYPE_COLD, SC_ERR_PARM); + ASRT_ERR(reason <= SC_PM_RESET_REASON_SCFW_FAULT, SC_ERR_PARM); + + /* Check if booted */ + ASRT_ERR(pm_part_data[pt].boot_cpu < SC_NUM_RESOURCE, SC_ERR_FAIL); + + /* Check partition to reboot is isolated */ + ASRT_ERR(rm_is_partition_isolated(pt) != SC_FALSE, + SC_ERR_NOACCESS); + + /* Get boot CPU index */ + BOUND_RSRC(pm_part_data[pt].boot_cpu, boot_cpu_idx); + + if (err == SC_ERR_NONE) + { + /* Prep partition for power off */ + (void) pm_part_off(pt, PM_PART_INIT | PM_PART_REBOOT); + + /* Notify about reboot */ + ss_irq_trigger(SC_IRQ_GROUP_REBOOT, BIT(pt), + SC_PT_ALL); + + /* Call board to allow change in reset or other action */ + board_reboot_part(pt, &type, &reason, &mode, + &pm_part_data[pt].reboot_mask); + + /* Record info */ + pm_part_data[pt].reason = reason; + pm_part_data[pt].reason_pt = caller_pt; + pm_part_data[pt].type = type; + pm_part_data[pt].mode = mode; + + if (pm_part_data[pt].reboot_mask == 0U) + { + /* Continue the reboot now */ + err = pm_reboot_cont(pt); + } + else + { + uint64_t to = U64(board_parameter(BOARD_PARM_REBOOT_TIME)) + * 1000ULL; + + /* Configure timer for timeout */ + err = timer_set_sysctr_alarm(SC_PT, SYSCTR_GetCounter64() + + SYSCTR_USEC_TO_TICKS64(to)); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Indicate okay to conntinue reboot */ +/*--------------------------------------------------------------------------*/ +sc_err_t pm_reboot_continue(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check parms */ + BOUND_PT(pt); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + pm_part_data[pt].reboot_mask &= ~(BIT32(caller_pt)); + + /* Check reboot mask */ + if (pm_part_data[pt].reboot_mask == 0U) + { + /* Cancel timers */ + (void) timer_cancel_sysctr_alarm(SC_PT); + + /* Continue reboot */ + (void) pm_reboot_cont(pt); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Indicate okay to conntinue reboot */ +/*--------------------------------------------------------------------------*/ +void pm_reboot_continue_all(void) +{ + sc_rm_pt_t p; + + (void) timer_cancel_sysctr_alarm(SC_PT); + + /* Notify users of alarm */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if (pm_part_data[p].reboot_mask != 0U) + { + pm_part_data[p].reboot_mask = 0U; + + switch (board_reboot_timeout(p)) + { + + case BOARD_REBOOT_TO_NONE : + break; + case BOARD_REBOOT_TO_FORCE : + (void) pm_reboot_cont(p); + break; + case BOARD_REBOOT_TO_FAULT : + (void) board_fault(SC_FALSE, BOARD_BFAULT_REBOOT, p); + break; + default : + ; /* Intentional empty default */ + break; + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the boolean indicating that partition has booted */ +/* this is called by AP ROM code via MISC service */ +/*--------------------------------------------------------------------------*/ +void pm_set_booted(sc_rm_pt_t pt, sc_bool_t booted) +{ + pm_part_data[pt].booted = booted; +} + +/*--------------------------------------------------------------------------*/ +/* Get boolean indicating that partition has booted */ +/*--------------------------------------------------------------------------*/ +sc_bool_t pm_get_booted(sc_rm_pt_t pt) +{ + return pm_part_data[pt].booted; +} + +/*--------------------------------------------------------------------------*/ +/* Get boolean indicating that a partition was started */ +/*--------------------------------------------------------------------------*/ +sc_bool_t pm_is_partition_started(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(pt); + + if ((err == SC_ERR_NONE) && (pm_part_data[pt].boot_cpu + < SC_NUM_RESOURCE)) + { + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Dump PM state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) && defined(DEBUG_PM) + void pm_dump(sc_rm_pt_t pt) + { + } +#endif + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Stop all CPUs owned by a partition */ +/*--------------------------------------------------------------------------*/ +static void ss_cpu_stop_all(sc_rm_pt_t pt) +{ + uint8_t cpu = 15U; + + /* List of CPU resources */ + static const sc_rsrc_t cpu_list[15] = + { + /* AP 0 cores */ + SC_R_AP_0_0, + SC_R_AP_0_1, + SC_R_AP_0_2, + SC_R_AP_0_3, + /* AP 1 cores */ + SC_R_AP_1_0, + SC_R_AP_1_1, + /* AP 2 cores */ + SC_R_AP_2_0, + SC_R_AP_2_1, + SC_R_AP_2_2, + SC_R_AP_2_3, + /* MCU cores */ + SC_R_MCU_0_PID0, + SC_R_MCU_1_PID0, + /* Clusters */ + SC_R_AP_0, + SC_R_AP_1, + SC_R_AP_2 + }; + + /* Loop over all CPUs */ + while (cpu > 0U) + { + sc_rm_idx_t idx; + + cpu--; + + /* Check for existance */ + if (rm_check_map_ridx(cpu_list[cpu], &idx) != SC_FALSE) + { + sc_rm_pt_t owner_pt = SC_PT; + + /* Check ownership */ + rm_get_ridx_owner(idx, &owner_pt); + if (owner_pt == pt) + { + if (soc_cluster_link_off(cpu_list[cpu], pt) == SC_FALSE) + { + (void) ss_cpu_start(idx, SC_FALSE, 0ULL); + } + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Reboot a partition */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pm_reboot_cont(sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + sc_rsrc_t boot_cpu = pm_part_data[pt].boot_cpu; + sc_rsrc_t boot_mu = pm_part_data[pt].boot_mu; + sc_rsrc_t boot_dev = pm_part_data[pt].boot_dev; + sc_faddr_t boot_addr = pm_part_data[pt].boot_addr; + + /* Check boot CPU */ + if (rm_check_map_ridx(boot_cpu, NULL) == SC_FALSE) + { + err = SC_ERR_PARM; + } + + if (err == SC_ERR_NONE) + { + /* Allow board file to disable UART */ + board_disable_debug_uart(); + } + + if ((err == SC_ERR_NONE) + && (pm_part_data[pt].type != SC_PM_RESET_TYPE_WARM)) + { + /* Check power state */ + if (pm_part_data[pt].sys_mode != SC_PM_PW_MODE_OFF) + { + base_nopoweroff = SC_TRUE; + + /* Turn off */ + err = pm_part_off(pt, PM_PART_FINAL| PM_PART_REBOOT); + } + + /* Power on partition */ + if (err == SC_ERR_NONE) + { + err = pm_update_partition_power_mode(SC_PT, pt, + SC_PM_PW_MODE_ON); + } + + /* Call board to allow change in boot or other action */ + if (err == SC_ERR_NONE) + { + board_reboot_part_cont(pt, &boot_cpu, &boot_mu, &boot_dev, + &boot_addr); + } + + /* Check for error */ + if (err == SC_ERR_NONE) + { + uint32_t indx; + + /* Power on boot peripherals */ + main_prep_cpu(boot_cpu, boot_mu); + + /* Power on boot memory (FSPI, OCRAM, TCM) */ + if (main_get_mem_ss(boot_addr, &indx) == SC_ERR_NONE) + { + sc_rsrc_t rsrc = rom_boot_addr[indx].rsrc; + + if (rsrc != SC_R_DRC_0) + { + pm_force_resource_power_mode_v( + rom_boot_addr[indx].rsrc, SC_PM_PW_MODE_ON); + } + } + } + + base_nopoweroff = SC_FALSE; + } + + /* Allow board file to re-enable UART */ + board_config_debug_uart(SC_TRUE); + board_config_debug_uart(SC_FALSE); + + if (err == SC_ERR_NONE) + { + sc_rm_idx_t boot_cpu_idx, boot_mu_idx; + + /* Get boot CPU index */ + BOUND_RSRC(boot_cpu, boot_cpu_idx); + + /* Set cold boot flag in MU */ + if (rm_check_map_ridx(boot_mu, &boot_mu_idx) + != SC_FALSE) + { + ss_mu_irq(boot_mu_idx, SC_RPC_MU_GIR_BOOT); + } + + ss_irq_trigger(SC_IRQ_GROUP_REBOOTED, BIT(pt), + SC_PT_ALL); + + /* Restart CPU */ + if (err == SC_ERR_NONE) + { + err = ss_cpu_start(boot_cpu_idx, SC_TRUE, boot_addr); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Power off a partition */ +/*--------------------------------------------------------------------------*/ +static sc_err_t pm_part_off(sc_rm_pt_t pt, uint32_t flags) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check current power state */ + if (pm_part_data[pt].sys_mode != SC_PM_PW_MODE_OFF) + { + /* Power off init phase */ + if ((flags & PM_PART_INIT) != 0U) + { + /* Cancel watchdog */ + timer_halt_wdog(pt); + + /* Cancel alarms */ + (void) timer_cancel_rtc_alarm(pt); + (void) timer_cancel_sysctr_alarm(pt); + + /* Stop all CPUs owned by this partition */ + ss_cpu_stop_all(pt); + + /* Send off notice if not rebooting */ + if ((flags & PM_PART_REBOOT) == 0U) + { + ss_irq_trigger(SC_IRQ_GROUP_OFF, BIT(pt), + SC_PT_ALL);; + } + } + + /* Power off final phase */ + if ((flags & PM_PART_FINAL) != 0U) + { + soc_no_reset = SC_TRUE; + base_noflushl2 = SC_TRUE; + base_gic_noblock = SC_TRUE; + + /* Reset resources that need power on */ + (void) ss_rsrc_reset(0U, pt, SC_TRUE); + + /* Power off */ + err = pm_update_partition_power_mode(SC_PT, pt, + SC_PM_PW_MODE_OFF); + + if (err == SC_ERR_NONE) + { + sc_rm_pt_t p; + + /* Free all child partitions */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if ((rm_is_partition_used(p) != SC_FALSE) + && (rm_is_parent(pt, p) != SC_FALSE)) + { + /* Stop all CPUs */ + ss_cpu_stop_all(p); + + /* Power off partition */ + (void) pm_update_partition_power_mode(SC_PT, + p, SC_PM_PW_MODE_OFF); + + /* Free partition */ + (void) rm_partition_free(SC_PT, p); + } + } + + /* Power off all peripherals */ + (void) pm_set_resource_power_mode_pt(pt, SC_R_ALL, + SC_PM_PW_MODE_OFF); + + /* Reset partition resources still on */ + (void) ss_rsrc_reset(0U, pt, SC_FALSE); + } + + soc_no_reset = SC_FALSE; + base_noflushl2 = SC_FALSE; + base_gic_noblock = SC_FALSE; + + if ((flags & PM_PART_REBOOT) == 0U) + { + /* Unless partition is rebooting, update HMP power state to + * remove requests for HMP nodes powered off. + * + * NOTE: must be done after soc_no_reset set FALSE to avoid + * skip of OCMEM system interfaces + */ + soc_update_hmp_sys_power_mode(); + + /* Send off complete notice if not rebooting */ + ss_irq_trigger(SC_IRQ_GROUP_OFFED, BIT(pt), + SC_PT_ALL);; + } + } + } + + return err; +} + +/** @} */ + diff --git a/platform/svc/pm/svc.h b/platform/svc/pm/svc.h new file mode 100755 index 0000000..7616e14 --- /dev/null +++ b/platform/svc/pm/svc.h @@ -0,0 +1,564 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/pm/svc.h + * + * Header file containing the API for the System Controller (SC) Power + * Management (PM) function. This includes functions for power state + * control, clock control, reset control, and wake-up event control. + * + * @addtogroup PM_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_PM_SVC_H +#define SC_PM_SVC_H + +/* Includes */ + +#include "main/main.h" +#include "svc/pm/api.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * @name Internal Functions + * @{ + */ + +/* + * Internal SC function that sets the boolean indicating that partition has booted. + * + * @param[in] pt handle of partition to set + * @param[in] booted boolean: true indicates that partition has booted + */ +void pm_set_booted(sc_rm_pt_t pt, sc_bool_t booted); + +/* + * Internal SC function that gets boolean indicating that partition has booted. + * + * @param[in] caller_pt handle of partition to check + * + * @return Returns a boolean that indicates if partition has booted + */ +sc_bool_t pm_get_booted(sc_rm_pt_t pt); + +/*! + * Internal SC function to initializes the PM service. + * + * @param[in] api_phase init phase + * + * Initializes the API if /a api_phase = SC_TRUE, otherwise initializes the HW + * managed by the PM service. API must be initialized before anything else is + * done with the service. + */ +void pm_init(sc_bool_t api_phase); + +/*! + * This function initializes a new partition. + * + * @param[in] caller_pt handle of caller partition + * @param[in] pt handle of partition + * + * Note this function should only be called by the resource manager when + * a new partition is allocated. The default power mode is on. + */ +void pm_init_part(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! + * Internal SC function to set the power mode of the system. + * + * @see sc_pm_set_sys_power_mode(). + */ +sc_err_t pm_set_sys_power_mode(sc_rm_pt_t caller_pt, + sc_pm_power_mode_t mode); + +/*! + * This function initializes a partition to off. + * + * @param[in] pt handle of partition + * + * Note this function should only be called immediatly after creating a new + * partition that should be off (default after creating is on). + */ +void pm_init_partition_power_off(sc_rm_pt_t pt); + +/*! + * Internal SC function to set the power mode of a partition. + * + * @see sc_pm_set_partition_power_mode(). + */ +sc_err_t pm_set_partition_power_mode(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to set the power mode of a partition. + * + * @see sc_pm_partition_power_off(). + */ +void pm_partition_power_off(sc_rm_pt_t caller_pt); + +/*! + * Internal function to updates the power mode of a partition. + * + * @param[in] caller_pt handle of partition to update + * @param[in] pt handle of partition + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or mode, + * - SC_ERR_NOACCESS if caller's partition is not the owner or + * parent of \a pt + * + * The power mode of the partitions is a max power any resource will + * be set to. Calling this will result in all resources owned + * by \a pt to have their power changed to the lower of \a mode or the + * individual resource mode set using sc_pm_set_resource_power_mode(). + */ +sc_err_t pm_update_partition_power_mode(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to send wake interrupt to a partition. + * + * @see sc_pm_partition_wake(). + */ +sc_err_t pm_partition_wake(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! + * Internal SC function to get the power mode of a partition. + * + * @see sc_pm_get_sys_power_mode(). + */ +sc_err_t pm_get_sys_power_mode(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_power_mode_t *mode); + +/*! + * Internal SC function to update the power state of a resource. + * + * @param[in] idx unified resource index + * + * Used to update when a partition changes state or resource is moved. + */ +void pm_update_ridx(sc_rm_idx_t idx); + +/*! + * Internal SC function to get the functional state of a resource. + * + * @param[in] resource unified resource index + * + * @return Returns a boolean (SC_TRUE = functional). + * + * Used to see if a resource is ready to be used. + */ +sc_bool_t pm_is_resource_accessible(sc_rsrc_t resource); + +/*! + * Internal SC function to init the power mode of a resource just after ROM boot + */ +void pm_init_rsrc_power_mode(sc_rsrc_t rsrc, sc_pm_power_mode_t mode); + +/*! + * Internal SC function to set the power mode of a resource via MU. + * + * @see sc_pm_set_resource_power_mode(). + */ +sc_err_t pm_set_resource_power_mode(sc_rsrc_t mu, + sc_rsrc_t resource, sc_pm_power_mode_t mode); + +/*! + * Internal function set the power mode of a resource based via pt. + * + * @param[in] pt partition of resource + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * @see sc_pm_set_resource_power_mode(). + */ +sc_err_t pm_set_resource_power_mode_pt(sc_rm_pt_t caller_pt, + sc_rsrc_t resource, sc_pm_power_mode_t mode); + +/*! + * Internal SC function to set power mode for all resources in a child + * partition. + * + * @see sc_pm_set_resource_power_mode_all(). + */ +sc_err_t pm_set_resource_power_mode_all(sc_rm_pt_t caller_pt, + sc_rm_pt_t pt, sc_pm_power_mode_t mode, sc_rsrc_t exclude); + +/*! + * This function sets the power mode of a resource index. + * + * @param[in] idx index of the resource + * @param[in] mode power mode to apply + */ +void pm_set_rsrc_power_mode(sc_rm_idx_t idx, + sc_pm_power_mode_t mode); + +/*! + * This function updates the power mode of a resource index. + * + * @param[in] idx index of the resource + * @param[in] mode power mode to apply + */ +void pm_set_active_rsrc_power_mode(sc_rm_idx_t idx, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to force the power mode of a resource. It + * should only be called by the SC during initial configuration. + * + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid resource or mode + * + * Note only SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON are valid. Other modes + * will return an error. Resources set to SC_PM_PW_MODE_ON will reflect the + * power mode of the partition and will change as that changes. + * + * @see sc_pm_set_partition_power_mode(). + */ +sc_err_t pm_force_resource_power_mode(sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to force the power mode of a resource. It + * should only be called by the SC during initial configuration. + * + * @param[in] resource ID of the resource + * @param[in] mode power mode to apply + * + * @see sc_pm_set_partition_power_mode(). + */ +void pm_force_resource_power_mode_v(sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to get the power mode of a resource. + * + * @see sc_pm_get_resource_power_mode(). + */ +sc_err_t pm_get_resource_power_mode(sc_rm_pt_t caller_pt, + sc_rsrc_t resource, sc_pm_power_mode_t *mode); + +/*! + * This function gets the power mode of a resource index. + * + * @param[in] idx index of the resource + * @param[in] mode power mode to apply + */ +void pm_get_rsrc_power_mode(sc_rm_idx_t idx, + sc_pm_power_mode_t *mode); + +/*! + * This function gets the active power mode of a resource index. + * + * @param[in] idx index of the resource + * @param[in] mode active power mode for the resource + */ +void pm_get_active_rsrc_power_mode(sc_rm_idx_t idx, + sc_pm_power_mode_t *mode); + +/*! + * Internal SC function to request the power mode a resource can enter + * in some low power conditions. + * + * @see sc_pm_req_low_power_mode(). + */ +sc_err_t pm_req_low_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to request low-power mode for a CPU. + * + * @see sc_pm_req_cpu_low_power_mode(). + */ +sc_err_t pm_req_cpu_low_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_power_mode_t mode, sc_pm_wake_src_t wake_src); + +/*! + * Internal SC function to set the resume address of a CPU. + * + * @see sc_pm_set_cpu_resume_addr(). + */ +sc_err_t pm_set_cpu_resume_addr(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_faddr_t address); + +/*! + * Internal SC function to set the resume parameters of a CPU. + * + * @see sc_pm_set_cpu_resume(). + */ +sc_err_t pm_set_cpu_resume(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_bool_t isPrimary, sc_faddr_t address); + +/*! + * Internal SC function to request power mode for system-level interfaces. + * + * @see pm_req_sys_if_power_mode(). + */ +sc_err_t pm_req_sys_if_power_mode(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_sys_if_t sys_if, sc_pm_power_mode_t hpm, sc_pm_power_mode_t lpm); + +/*! + * Internal SC function to set the rate of a resource's clock/PLL. + * + * @see sc_pm_set_clock_rate(). + */ +sc_err_t pm_set_clock_rate(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * Internal SC function to get the rate of a resource's clock/PLL. + * + * @see sc_pm_get_clock_rate(). + */ +sc_err_t pm_get_clock_rate(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clock_rate_t *rate); + +/*! + * Internal SC function to enable/disable a resource's clock. + * + * @see sc_pm_clock_enable(). + */ +sc_err_t pm_clock_enable(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog); + +/*! + * Internal SC function to force a resource's clock to be enabled. + * + * @param[in] resource ID of the resource + * @param[in] clk clock to affect + * @param[in] enable enable if SC_TRUE; otherwise depends on + * state from pm_clock_enable() + * + * Refer to the [Clock List](@ref CLOCKS) for valid clock values. + */ +void pm_force_clock_enable(sc_rsrc_t resource, sc_pm_clk_t clk, + sc_bool_t enable); + +/*! + * Internal SC function to set a clock parent. + * + * @see sc_pm_set_clock_parent(). + */ +sc_err_t pm_set_clock_parent(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t parent); + +/*! + * Internal SC function to get a clock parent. + * + * @see sc_pm_get_clock_parent(). + */ +sc_err_t pm_get_clock_parent(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_pm_clk_t clk, sc_pm_clk_parent_t *parent); + +/*! + * Internal SC function to boot a partition. + * + * @see sc_pm_boot(). + */ +sc_err_t pm_boot(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * Internal SC function to set a partition's boot parameters. + * + * @see sc_pm_set_boot_parm(). + */ +sc_err_t pm_set_boot_parm(sc_rm_pt_t caller_pt, + sc_rsrc_t resource_cpu, sc_faddr_t boot_addr, + sc_rsrc_t resource_mu, sc_rsrc_t resource_dev); + +/*! + * Internal SC function used to get the boot parameters for a partition. + * + * @param[in] caller_pt calling partition + * @param[out] resource_cpu pointer to return the ID of the CPU resource to start + * @param[out] boot_addr pointer to return the 64-bit boot address + * @param[out] resource_mu pointer to return the ID of the MU that must be powered (0=none) + * @param[out] resource_dev pointer to return the ID of the boot device that must be powered (0=none) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid caller_pt + */ +sc_err_t pm_get_boot_parm(sc_rm_pt_t caller_pt, + sc_rsrc_t *resource_cpu, sc_faddr_t *boot_addr, + sc_rsrc_t *resource_mu, sc_rsrc_t *resource_dev); + +/*! + * Internal SC function to reboot the caller's partition. + * + * @see sc_pm_reboot(). + */ +void pm_reboot(sc_rm_pt_t caller_pt, sc_pm_reset_type_t type); + +/*! + * Internal SC function to get the reset reason. + * + * @see sc_pm_reset_reason(). + */ +sc_err_t pm_reset_reason(sc_rm_pt_t caller_pt, + sc_pm_reset_reason_t *reason); + +/*! + * Internal SC function to get the partition that caused a reset. + * + * @see sc_pm_get_reset_part(). + */ +sc_err_t pm_get_reset_part(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt); + +/*! + * Internal SC function to start/stop a CPU. + * + * @see sc_pm_cpu_start(). + */ +sc_err_t pm_cpu_start(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_bool_t enable, sc_faddr_t address); + +/*! + * Internal SC function to reset a CPU. + * + * @see sc_pm_cpu_reset(). + */ +void pm_cpu_reset(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_faddr_t address); + +/*! + * Internal SC function to reset a resource. + * + * @see sc_pm_resource_reset(). + */ + sc_err_t pm_resource_reset(sc_rsrc_t mu, sc_rsrc_t resource); + +/*! + * Internal SC function to reboot a partition. + * + * @see sc_pm_reboot_partition(). + */ +sc_err_t pm_reboot_partition(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_reset_type_t type); + +/*! + * Internal SC function to conntinue reboot. + * + * @see sc_reboot_continue(). + */ +sc_err_t pm_reboot_continue(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! +* Internal SC function to force the conntinue of all reboots. +*/ +void pm_reboot_continue_all(void); + +/*! + * Internal SC function to reset the system. + * + * @see sc_pm_reset(). + */ +sc_err_t pm_reset(sc_rm_pt_t caller_pt, sc_pm_reset_type_t type); + +/*! + * Internal SC function used to reboot a partition. + * + * @param[in] caller_pt calling partition + * @param[in] pt handle of partition to reboot + * @param[in] type reset type + * @param[in] reason reset reason + * @param[in] mode power mode to go down to as part of reboot + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid partition or reason + * + * Most peripherals owned by the partition will be reset if + * possible. SC state (partitions, power, clocks, etc.) is reset. The + * boot SW of the booting CPU must be able to handle peripherals that + * that are not reset. + */ +sc_err_t pm_reboot_part(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pm_reset_type_t type, sc_pm_reset_reason_t reason, + sc_pm_power_mode_t mode); + +/*! + * Internal SC function to get boolean indicating that a partition was + * started. + * + * @see sc_pm_is_partition_started(). + */ +sc_bool_t pm_is_partition_started(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/** @} */ + +#if defined(DEBUG) && defined(DEBUG_PM) + /*! + * @name Debug Functions + * @{ + */ + + /*! + * Internal SC function to dump the internal state of the PM service. + * + * @param[in] pt partition to dump + */ + void pm_dump(sc_rm_pt_t pt); + + /** @} */ +#endif + +#endif /* SC_PM_SVC_H */ + +/** @} */ + diff --git a/platform/svc/rm/Makefile b/platform/svc/rm/Makefile new file mode 100755 index 0000000..1876cc6 --- /dev/null +++ b/platform/svc/rm/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/rm/svc.o + +RPCS += $(OUT)/svc/rm/rpc_srv.o + +RPCL += $(OUT)/svc/rm/rpc_clnt.o + +RPCH += $(SRC)/svc/rm/rpc.h + +RPCC += $(SRC)/svc/rm/rpc_srv.c \ + $(SRC)/svc/rm/rpc_clnt.c \ + $(SRC)/svc/rm/rpc_xlate.c + +RPCHDR += $(SRC)/svc/rm/rpc_header.h + +DIRS += $(OUT)/svc/rm + diff --git a/platform/svc/rm/api.h b/platform/svc/rm/api.h new file mode 100755 index 0000000..1d2e5e4 --- /dev/null +++ b/platform/svc/rm/api.h @@ -0,0 +1,972 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/rm/api.h + * + * Header file containing the public API for the System Controller (SC) + * Resource Management (RM) function. This includes functions for + * partitioning resources, pads, and memory regions. + * + * @addtogroup RM_SVC RM: Resource Management Service + * + * @brief Module for the Resource Management (RM) service. + * + * @includedoc rm/details.dox + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_RM_API_H +#define SC_RM_API_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/** @{ */ +#define SC_RM_PARTITION_W 5U /*!< Width of sc_rm_pt_t */ +#define SC_RM_MEMREG_W 6U /*!< Width of sc_rm_mr_t */ +#define SC_RM_DID_W 4U /*!< Width of sc_rm_did_t */ +#define SC_RM_SID_W 6U /*!< Width of sc_rm_sid_t */ +#define SC_RM_SPA_W 2U /*!< Width of sc_rm_spa_t */ +#define SC_RM_PERM_W 3U /*!< Width of sc_rm_perm_t */ +#define SC_RM_DET_W 1U /*!< Width of sc_rm_det_t */ +#define SC_RM_RMSG_W 4U /*!< Width of sc_rm_rmsg_t */ +/** @} */ + +/*! + * @name Defines for ALL parameters + */ +/** @{ */ +#define SC_RM_PT_ALL ((sc_rm_pt_t) UINT8_MAX) /*!< All partitions */ +#define SC_RM_MR_ALL ((sc_rm_mr_t) UINT8_MAX) /*!< All memory regions */ +/** @} */ + +/*! + * @name Defines for sc_rm_spa_t + */ +/** @{ */ +#define SC_RM_SPA_PASSTHRU 0U /*!< Pass through (attribute driven by master) */ +#define SC_RM_SPA_PASSSID 1U /*!< Pass through and output on SID */ +#define SC_RM_SPA_ASSERT 2U /*!< Assert (force to be secure/privileged) */ +#define SC_RM_SPA_NEGATE 3U /*!< Negate (force to be non-secure/user) */ +/** @} */ + +/*! + * @name Defines for sc_rm_perm_t + */ +/** @{ */ +#define SC_RM_PERM_NONE 0U /*!< No access */ +#define SC_RM_PERM_SEC_R 1U /*!< Secure RO */ +#define SC_RM_PERM_SECPRIV_RW 2U /*!< Secure privilege R/W */ +#define SC_RM_PERM_SEC_RW 3U /*!< Secure R/W */ +#define SC_RM_PERM_NSPRIV_R 4U /*!< Secure R/W, non-secure privilege RO */ +#define SC_RM_PERM_NS_R 5U /*!< Secure R/W, non-secure RO */ +#define SC_RM_PERM_NSPRIV_RW 6U /*!< Secure R/W, non-secure privilege R/W */ +#define SC_RM_PERM_FULL 7U /*!< Full access */ +/** @} */ + +/* Types */ + +/*! + * This type is used to declare a resource partition. + */ +typedef uint8_t sc_rm_pt_t; + +/*! + * This type is used to declare a memory region. + */ +typedef uint8_t sc_rm_mr_t; + +/*! + * This type is used to declare a resource domain ID used by the + * isolation HW. + */ +typedef uint8_t sc_rm_did_t; + +/*! + * This type is used to declare an SMMU StreamID. + */ +typedef uint16_t sc_rm_sid_t; + +/*! + * This type is a used to declare master transaction attributes. + */ +typedef uint8_t sc_rm_spa_t; + +/*! + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ +typedef uint8_t sc_rm_perm_t; + +/*! + * This type is used to indicate memory region transactions should detour + * to the IEE. + */ +typedef uint8_t sc_rm_det_t; + +/*! + * This type is used to assign an RMSG value to a memory region. This value + * is sent to the IEE. + */ +typedef uint8_t sc_rm_rmsg_t; + +/* Functions */ + +/*! + * @name Partition Functions + * @{ + */ + +/*! + * This function requests that the SC create a new resource partition. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for partition; + used for subsequent function + * calls associated with this partition + * @param[in] secure boolean indicating if this partition should be secure; + only valid if caller is secure + * @param[in] isolated boolean indicating if this partition should be HW isolated + * via XRDC; set SC_TRUE if new DID is desired + * @param[in] restricted boolean indicating if this partition should be restricted; + * set SC_TRUE if masters in this partition cannot create new partitions + * @param[in] grant boolean indicating if this partition should always grant + * access and control to the parent + * @param[in] coherent boolean indicating if this partition is coherent; + * set SC_TRUE if only this partition will contain both AP clusters + * and they will be coherent via the CCI + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_ERR_PARM if caller's partition is not secure but a new secure partition is requested, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_UNAVAILABLE if partition table is full (no more allocation space) + * + * Marking as non-secure prevents subsequent functions from configuring masters in this + * partition to assert the secure signal. Basically, if TrustZone SW is used, the Cortex-A + * cores and peripherals the TZ SW will use should be in a secure partition. Almost all + * other partitions (for a non-secure OS or MCU cores) should be in non-secure partitions. + * + * Isolated should be true for almost all partitions. The exception is the non-secure + * partition for a Cortex-A core used to run a non-secure OS. This isn't isolated by + * domain but is instead isolated by the TZ security hardware. + * + * If restricted then the new partition is limited in what functions it can call, + * especially those associated with managing partitions. + * + * The grant option is usually used to isolate a bus master's traffic to specific + * memory without isolating the peripheral interface of the master or the API + * controls of that master. This is only used when creating a sub-partition with + * no CPU. It's useful to separate out a master and the memory it uses. + */ +/* IDL: E8 PARTITION_ALLOC(UO8 pt, IB secure, IB isolated, IB restricted, IB grant, IB coherent) #1 */ +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, sc_bool_t coherent); + +/*! + * This function makes a partition confidential. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition that is granting + * @param[in] retro retroactive + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's not allowed to change \a pt + * - SC_ERR_LOCKED if partition \a pt is locked + * + * Call to make a partition confidential. Confidential means only this + * partition should be able to grant access permissions to this partition. + * + * If retroactive, then all resources owned by other partitions will have + * access rights for this partition removed, even if locked. + */ +/* IDL: E8 SET_CONFIDENTIAL(UI8 pt, IB retro) #31 */ +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro); + +/*! + * This function frees a partition and assigns all resources to the caller. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt out of range or invalid, + * - SC_ERR_NOACCESS if \a pt is the SC partition, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt or caller's partition is locked + * + * All resources, memory regions, and pads are assigned to the caller/parent. + * The partition watchdog is disabled (even if locked). DID is freed. + */ +/* IDL: E8 PARTITION_FREE(UI8 pt) #2 */ +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function returns the DID of a partition. + * + * @param[in] ipc IPC handle + * + * @return Returns the domain ID (DID) of the caller's partition. + * + * The DID is a SoC-specific internal ID used by the HW resource + * protection mechanism. It is only required by clients when using the + * SEMA42 module as the DID is sometimes connected to the master ID. + */ +/* IDL: UR8 GET_DID() #26 */ +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc); + +/*! + * This function forces a partition to use a specific static DID. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to assign \a did + * @param[in] did static DID to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if \a pt or \a did out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if \a pt is locked + * + * Assumes no assigned resources or memory regions yet! The number of static + * DID is fixed by the SC at boot. + */ +/* IDL: E8 PARTITION_STATIC(UI8 pt, UI8 did) #3 */ +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_did_t did); + +/*! + * This function locks a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to lock + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a pt out of range, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt + * + * If a partition is locked it cannot be freed, have resources/pads assigned + * to/from it, memory regions created/assigned, DID changed, or parent changed. + */ +/* IDL: E8 PARTITION_LOCK(UI8 pt) #4 */ +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt); + +/*! + * This function gets the partition handle of the caller. + * + * @param[in] ipc IPC handle + * @param[out] pt return handle for caller's partition + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 GET_PARTITION(UO8 pt) #5 */ +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); + +/*! + * This function sets a new parent for a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition for which parent is to be changed + * @param[in] pt_parent handle of partition to set as parent + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the parent of \a pt, + * - SC_ERR_LOCKED if either partition is locked + */ +/* IDL: E8 SET_PARENT(UI8 pt, UI8 pt_parent) #6 */ +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent); + +/*! + * This function moves all movable resources/pads owned by a source partition + * to a destination partition. It can be used to more quickly set up a new + * partition if a majority of the caller's resources are to be moved to a + * new partition. + * + * @param[in] ipc IPC handle + * @param[in] pt_src handle of partition from which resources should be moved from + * @param[in] pt_dst handle of partition to which resources should be moved to + * @param[in] move_rsrc boolean to indicate if resources should be moved + * @param[in] move_pads boolean to indicate if pads should be moved + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * By default, all resources are movable. This can be changed using the + * sc_rm_set_resource_movable() function. Note all masters defaulted to SMMU + * bypass. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not \a pt_src or the + * parent of \a pt_src, + * - SC_ERR_LOCKED if either partition is locked + */ +/* IDL: E8 MOVE_ALL(UI8 pt_src, UI8 pt_dst, IB move_rsrc, IB move_pads) #7 */ +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads); + +/** @} */ + +/*! + * @name Resource Functions + * @{ + */ + +/*! + * This function assigns ownership of a resource to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition to which resource should be assigned + * @param[in] resource resource to assign + * + * This function assigned a resource to a partition. This partition is then + * the owner. All resources always have an owner (one owner). The owner + * has various rights to make API calls affecting the resource. Ownership + * does not imply access to the peripheral itself (that is based on access + * rights). + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This action resets the resource's master and peripheral attributes. + * Privilege attribute will be PASSTHRU, security attribute will be + * ASSERT if the partition is secure and NEGATE if it is not, and + * masters will defaulted to SMMU bypass. Access permissions will reset + * to SEC_RW for the owning partition only for secure partitions, FULL for + * non-secure. Default is no access by other partitions. + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +/* IDL: E8 ASSIGN_RESOURCE(UI8 pt, UI16 resource) #8 */ +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_rsrc_t resource); + +/*! + * This function flags resources as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] resource_fst first resource for which flag should be set + * @param[in] resource_lst last resource for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if resources are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of resources that will be + * moved using the sc_rm_move_all() function. All resources are movable + * by default so this function is normally used to prevent a set of + * resources from moving. + */ +/* IDL: E8 SET_RESOURCE_MOVABLE(UI16 resource_fst, UI16 resource_lst, IB movable) #9 */ +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable); + +/*! + * This function flags all of a subsystem's resources as movable + * or not. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to use to identify subsystem + * @param[in] movable movable flag (SC_TRUE is movable) + * + * A subsystem is a physical grouping within the chip of related resources; + * this is SoC specific. This function is used to optimize moving resource + * for these groupings, for instance, an MCU core and its associated resources. + * The list of subsystems and associated resources can be found in the + * SoC-specific API document [Resources](@ref RESOURCES) chapter. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if a function argument is out of range + * + * Note \a resource is used to find the associated subsystem. Only + * resources owned by the caller are set. + */ +/* IDL: E8 SET_SUBSYS_RSRC_MOVABLE(UI16 resource, IB movable) #28 */ +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable); + +/*! + * This function sets attributes for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sa security attribute + * @param[in] pa privilege attribute + * @param[in] smmu_bypass SMMU bypass mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of the resource owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * Masters are IP blocks that generate bus transactions. This function configures + * how the isolation HW will define these bus transactions from the specified master. + * Note the security attribute will only be changed if the caller's partition is + * secure. + * + * Note an IP block can be both a master and peripheral (have both a programming model + * and generate bus transactions). + */ +/* IDL: E8 SET_MASTER_ATTRIBUTES(UI16 resource, UI8 sa, UI8 pa, IB smmu_bypass) #10 */ +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass); + +/*! + * This function sets the StreamID for a resource which is a bus master (i.e. + * capable of DMA). + * + * @param[in] ipc IPC handle + * @param[in] resource master resource for which attributes should apply + * @param[in] sid StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function configures the SID attribute associated with all bus transactions + * from this master. Note 0 is not a valid SID as it is reserved to indicate + * bypass. + */ +/* IDL: E8 SET_MASTER_SID(UI16 resource, UI16 sid) #11 */ +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t sid); + +/*! + * This function sets access permissions for a peripheral resource. + * + * @param[in] ipc IPC handle + * @param[in] resource peripheral resource for which permissions should apply + * @param[in] pt handle of partition \a perm should by applied for + * @param[in] perm permissions to apply to \a resource for \a pt + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the resource owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * Peripherals are IP blocks that have a programming model that can be + * accessed. + * + * This function configures how the isolation HW will restrict access to a + * peripheral based on the attributes of a transaction from bus master. It + * also allows the access permissions of SC_R_SYSTEM to be set. + * + * Note an IP block can be both a master and peripheral (have both a programming + * model and generate bus transactions). + */ +/* IDL: E8 SET_PERIPHERAL_PERMISSIONS(UI16 resource, UI8 pt, UI8 perm) #12 */ +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function gets ownership status of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the resource). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +/* IDL: RB IS_RESOURCE_OWNED(UI16 resource) #13 */ +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to get the owner of a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * @param[out] pt pointer to return owning partition + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid + * + * If \a resource is out of range then SC_ERR_PARM is returned. + */ +/* IDL: E8 GET_RESOURCE_OWNER(UI16 resource, UO8 pt) #33 */ +sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/*! + * This function is used to test if a resource is a bus master. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * Masters are IP blocks that generate bus transactions. Note an IP block + * can be both a master and peripheral (have both a programming model + * and generate bus transactions). + * + * @return Returns a boolean (SC_TRUE if the resource is a bus master). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +/* IDL: RB IS_RESOURCE_MASTER(UI16 resource) #14 */ +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to test if a resource is a peripheral. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to check + * + * Peripherals are IP blocks that have a programming model that can be + * accessed. Note an IP block can be both a master and peripheral (have + * both a programming model and generate bus transactions) + * + * @return Returns a boolean (SC_TRUE if the resource is a peripheral). + * + * If \a resource is out of range then SC_FALSE is returned. + */ +/* IDL: RB IS_RESOURCE_PERIPHERAL(UI16 resource) #15 */ +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource); + +/*! + * This function is used to obtain info about a resource. + * + * @param[in] ipc IPC handle + * @param[in] resource resource to inquire about + * @param[out] sid pointer to return StreamID + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a resource is out of range + */ +/* IDL: E8 GET_RESOURCE_INFO(UI16 resource, UO16 sid) #16 */ +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid); + +/** @} */ + +/*! + * @name Memory Region Functions + * @{ + */ + +/*! + * This function requests that the SC create a new memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; + used for subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is misaligned, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function will create a new memory region. The area covered by the + * new region must already exist in a memory region owned by the caller. The + * result will be two memory regions, the new one overlapping the existing + * one. The priority resolution is based on the region index which is hard + * to predict. It could also be different between first creation and reload + * after a resume. Almost always better to use sc_rm_memreg_split() or + * sc_rm_memreg_frag() to create non-overlapping regions. The value of this + * function is mostly for initial region creation by the SCFW itself. + */ +/* IDL: E8 MEMREG_ALLOC(UO8 mr, UI64 addr_start, UI64 addr_end) #17 */ +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function requests that the SC split an existing memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to split + * @param[out] mr_ret return handle for new region; + used for subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if the new memory region is not start/end part of mr, + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_BUSY if the region is coincident with another region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function will take an existing region and split it into two, + * non-overlapping regions. Note the new region must start or end on the + * split region. Permissions will mirror the parent region. + */ +/* IDL: E8 MEMREG_SPLIT(UI8 mr, UO8 mr_ret, UI64 addr_start, UI64 addr_end) #29 */ +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function requests that the SC fragment a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr_ret return handle for new region; + used for subsequent function calls + * associated with this region + * @param[in] addr_start start address of region (physical) + * @param[in] addr_end end address of region (physical) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_LOCKED if caller's partition is locked, + * - SC_ERR_PARM if the new memory region spans multiple existing regions, + * - SC_ERR_NOACCESS if caller's partition does not own the memory containing + * the new region, + * - SC_ERR_BUSY if the region is coincident with another region, + * - SC_ERR_UNAVAILABLE if memory region table is full (no more allocation + * space) + * + * This function finds the memory region containing the address range. + * It then splits it as required and returns the extracted region. The + * result is 2-3 non-overlapping regions, depending on how the new region + * aligns with existing regions. Permissions will mirror the parent region. + */ +/* IDL: E8 MEMREG_FRAG(UO8 mr_ret, UI64 addr_start, UI64 addr_end) #32 */ +sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function frees a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to free + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not a parent of \a mr, + * - SC_ERR_LOCKED if the owning partition of \a mr is locked + */ +/* IDL: E8 MEMREG_FREE(UI8 mr) #18 */ +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * Internal SC function to find a memory region. + * + * @see sc_rm_find_memreg(). + */ +/*! + * This function finds a memory region. + * + * @param[in] ipc IPC handle + * @param[out] mr return handle for region; + used for subsequent function calls + * associated with this region + * @param[in] addr_start start address of region to search for + * @param[in] addr_end end address of region to search for + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOTFOUND if region not found, + * + * Searches only for regions owned by the caller. Finds first + * region containing the range specified. + */ +/* IDL: E8 FIND_MEMREG(UO8 mr, UI64 addr_start, UI64 addr_end) #30 */ +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * This function assigns ownership of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + to which memory region should be assigned + * @param[in] mr handle of memory region to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This function assigns a memory region to a partition. This partition is then + * the owner. All regions always have an owner (one owner). The owner + * has various rights to make API calls affecting the region. Ownership + * does not imply access to the memory itself (that is based on access + * rights). + * + * Note that the process of assigning a partition makes some implicit changes + * to the access permissions. The receiving partition will automatically be + * given SC_RM_PERM_SEC_RW or SC_RM_PERM_FULL rights depending on the security + * state of the receiving partition. + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the \a mr owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +/* IDL: E8 ASSIGN_MEMREG(UI8 pt, UI8 mr) #19 */ +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr); + +/*! + * This function sets access permissions for a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region + for which permissions should apply + * @param[in] pt handle of partition \a perm should by + * applied for + * @param[in] perm permissions to apply to \a mr for \a pt + * + * This operates on the memory region specified. If SC_RM_PT_ALL is specified + * then it operates on all the regions owned by the caller that exist at the + * time of the call. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_LOCKED if the \a pt is confidential and the caller isn't \a pt + * + * This function configures how the HW isolation will restrict access to a + * memory region based on the attributes of a transaction from bus master. + */ +/* IDL: E8 SET_MEMREG_PERMISSIONS(UI8 mr, UI8 pt, UI8 perm) #20 */ +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * This function configures the IEE parameters for a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to check + * @param[in] det 0 = normal, 1 = encrypted + * @param[in] rmsg IEE region (0-7) + * + * Caller must own SC_R_IEE_Rn where n is rmsg. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_LOCKED if the owning partition is locked + * - SC_ERR_NOACCESS if caller's partition is not the region owner or parent + * of the owner + * - SC_ERR_UNAVAILABLE if caller's partition is not the IEE region resource + * owner + */ +/* IDL: E8 SET_MEMREG_IEE(UI8 mr, UI8 det, UI8 rmsg) #34 */ +sc_err_t sc_rm_set_memreg_iee(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_rm_det_t det, sc_rm_rmsg_t rmsg); + +/*! + * This function gets ownership status of a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the + * memory region). + * + * If \a mr is out of range then SC_FALSE is returned. + */ +/* IDL: RB IS_MEMREG_OWNED(UI8 mr) #21 */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); + +/*! + * This function is used to obtain info about a memory region. + * + * @param[in] ipc IPC handle + * @param[in] mr handle of memory region to inquire about + * @param[out] addr_start pointer to return start address + * @param[out] addr_end pointer to return end address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if \a mr is out of range + */ +/* IDL: E8 GET_MEMREG_INFO(UI8 mr, UO64 addr_start, UO64 addr_end) #22 */ +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end); + +/** @} */ + +/*! + * @name Pad Functions + * @{ + */ + +/*! + * This function assigns ownership of a pad to a partition. + * + * @param[in] ipc IPC handle + * @param[in] pt handle of partition + to which pad should be assigned + * @param[in] pad pad to assign + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is restricted, + * - SC_PARM if arguments out of range or invalid, + * - SC_ERR_NOACCESS if caller's partition is not the pad owner or parent + * of the owner, + * - SC_ERR_LOCKED if the owning partition or \a pt is locked + */ +/* IDL: E8 ASSIGN_PAD(UI8 pt, UI16 pad) #23 */ +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); + +/*! + * This function flags pads as movable or not. + * + * @param[in] ipc IPC handle + * @param[in] pad_fst first pad for which flag should be set + * @param[in] pad_lst last pad for which flag should be set + * @param[in] movable movable flag (SC_TRUE is movable) + * + * This function assigned a pad to a partition. This partition is then + * the owner. All pads always have an owner (one owner). The owner + * has various rights to make API calls affecting the pad. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_PARM if pads are out of range, + * - SC_ERR_NOACCESS if caller's partition is not a parent of a pad owner, + * - SC_ERR_LOCKED if the owning partition is locked + * + * This function is used to determine the set of pads that will be + * moved using the sc_rm_move_all() function. All pads are movable + * by default so this function is normally used to prevent a set of + * pads from moving. + */ +/* IDL: E8 SET_PAD_MOVABLE(UI16 pad_fst, UI16 pad_lst, IB movable) #24 */ +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, + sc_pad_t pad_lst, sc_bool_t movable); + +/*! + * This function gets ownership status of a pad. + * + * @param[in] ipc IPC handle + * @param[in] pad pad to check + * + * @return Returns a boolean (SC_TRUE if caller's partition owns the pad). + * + * If \a pad is out of range then SC_FALSE is returned. + */ +/* IDL: RB IS_PAD_OWNED(UI16 pad) #25 */ +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); + +/** @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function dumps the RM state for debug. + * + * @param[in] ipc IPC handle + */ +/* IDL: R0 DUMP() #27 */ +void sc_rm_dump(sc_ipc_t ipc); + +/** @} */ + +#endif /* SC_RM_API_H */ + +/** @} */ + diff --git a/platform/svc/rm/rpc.h b/platform/svc/rm/rpc.h new file mode 100644 index 0000000..e14e988 --- /dev/null +++ b/platform/svc/rm/rpc.h @@ -0,0 +1,113 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the RM RPC implementation. + * + * @addtogroup RM_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_RM_RPC_H +#define SC_RM_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC RM function calls + */ +/** @{ */ +#define RM_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define RM_FUNC_PARTITION_ALLOC 1U /*!< Index for sc_rm_partition_alloc() RPC call */ +#define RM_FUNC_SET_CONFIDENTIAL 31U /*!< Index for sc_rm_set_confidential() RPC call */ +#define RM_FUNC_PARTITION_FREE 2U /*!< Index for sc_rm_partition_free() RPC call */ +#define RM_FUNC_GET_DID 26U /*!< Index for sc_rm_get_did() RPC call */ +#define RM_FUNC_PARTITION_STATIC 3U /*!< Index for sc_rm_partition_static() RPC call */ +#define RM_FUNC_PARTITION_LOCK 4U /*!< Index for sc_rm_partition_lock() RPC call */ +#define RM_FUNC_GET_PARTITION 5U /*!< Index for sc_rm_get_partition() RPC call */ +#define RM_FUNC_SET_PARENT 6U /*!< Index for sc_rm_set_parent() RPC call */ +#define RM_FUNC_MOVE_ALL 7U /*!< Index for sc_rm_move_all() RPC call */ +#define RM_FUNC_ASSIGN_RESOURCE 8U /*!< Index for sc_rm_assign_resource() RPC call */ +#define RM_FUNC_SET_RESOURCE_MOVABLE 9U /*!< Index for sc_rm_set_resource_movable() RPC call */ +#define RM_FUNC_SET_SUBSYS_RSRC_MOVABLE 28U /*!< Index for sc_rm_set_subsys_rsrc_movable() RPC call */ +#define RM_FUNC_SET_MASTER_ATTRIBUTES 10U /*!< Index for sc_rm_set_master_attributes() RPC call */ +#define RM_FUNC_SET_MASTER_SID 11U /*!< Index for sc_rm_set_master_sid() RPC call */ +#define RM_FUNC_SET_PERIPHERAL_PERMISSIONS 12U /*!< Index for sc_rm_set_peripheral_permissions() RPC call */ +#define RM_FUNC_IS_RESOURCE_OWNED 13U /*!< Index for sc_rm_is_resource_owned() RPC call */ +#define RM_FUNC_GET_RESOURCE_OWNER 33U /*!< Index for sc_rm_get_resource_owner() RPC call */ +#define RM_FUNC_IS_RESOURCE_MASTER 14U /*!< Index for sc_rm_is_resource_master() RPC call */ +#define RM_FUNC_IS_RESOURCE_PERIPHERAL 15U /*!< Index for sc_rm_is_resource_peripheral() RPC call */ +#define RM_FUNC_GET_RESOURCE_INFO 16U /*!< Index for sc_rm_get_resource_info() RPC call */ +#define RM_FUNC_MEMREG_ALLOC 17U /*!< Index for sc_rm_memreg_alloc() RPC call */ +#define RM_FUNC_MEMREG_SPLIT 29U /*!< Index for sc_rm_memreg_split() RPC call */ +#define RM_FUNC_MEMREG_FRAG 32U /*!< Index for sc_rm_memreg_frag() RPC call */ +#define RM_FUNC_MEMREG_FREE 18U /*!< Index for sc_rm_memreg_free() RPC call */ +#define RM_FUNC_FIND_MEMREG 30U /*!< Index for sc_rm_find_memreg() RPC call */ +#define RM_FUNC_ASSIGN_MEMREG 19U /*!< Index for sc_rm_assign_memreg() RPC call */ +#define RM_FUNC_SET_MEMREG_PERMISSIONS 20U /*!< Index for sc_rm_set_memreg_permissions() RPC call */ +#define RM_FUNC_SET_MEMREG_IEE 34U /*!< Index for sc_rm_set_memreg_iee() RPC call */ +#define RM_FUNC_IS_MEMREG_OWNED 21U /*!< Index for sc_rm_is_memreg_owned() RPC call */ +#define RM_FUNC_GET_MEMREG_INFO 22U /*!< Index for sc_rm_get_memreg_info() RPC call */ +#define RM_FUNC_ASSIGN_PAD 23U /*!< Index for sc_rm_assign_pad() RPC call */ +#define RM_FUNC_SET_PAD_MOVABLE 24U /*!< Index for sc_rm_set_pad_movable() RPC call */ +#define RM_FUNC_IS_PAD_OWNED 25U /*!< Index for sc_rm_is_pad_owned() RPC call */ +#define RM_FUNC_DUMP 27U /*!< Index for sc_rm_dump() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming RM RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void rm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_RM_RPC_H */ + +/** @} */ + diff --git a/platform/svc/rm/rpc_clnt.c b/platform/svc/rm/rpc_clnt.c new file mode 100644 index 0000000..aedf378 --- /dev/null +++ b/platform/svc/rm/rpc_clnt.c @@ -0,0 +1,1014 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the RM service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup RM_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "../../main/rpc.h" +#include "svc/rm/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 PARTITION_ALLOC(UO8 pt, IB secure, IB isolated, IB restricted, IB grant, IB coherent) #1 */ +sc_err_t sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, + sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, + sc_bool_t coherent) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_ALLOC); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = B2U8(secure); + RPC_U8(&msg, 1U) = B2U8(isolated); + RPC_U8(&msg, 2U) = B2U8(restricted); + RPC_U8(&msg, 3U) = B2U8(grant); + RPC_U8(&msg, 4U) = B2U8(coherent); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (pt != NULL) + { + *pt = (sc_rm_pt_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_CONFIDENTIAL(UI8 pt, IB retro) #31 */ +sc_err_t sc_rm_set_confidential(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t retro) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_CONFIDENTIAL); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = B2U8(retro); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 PARTITION_FREE(UI8 pt) #2 */ +sc_err_t sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_FREE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: UR8 GET_DID() #26 */ +sc_rm_did_t sc_rm_get_did(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + sc_rm_did_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_DID); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_rm_did_t) RPC_R8(&msg); + + /* Return result */ + return result; +} + +/* IDL: E8 PARTITION_STATIC(UI8 pt, UI8 did) #3 */ +sc_err_t sc_rm_partition_static(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_did_t did) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_STATIC); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(did); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 PARTITION_LOCK(UI8 pt) #4 */ +sc_err_t sc_rm_partition_lock(sc_ipc_t ipc, sc_rm_pt_t pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_PARTITION_LOCK); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_PARTITION(UO8 pt) #5 */ +sc_err_t sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_PARTITION); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (pt != NULL) + { + *pt = (sc_rm_pt_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_PARENT(UI8 pt, UI8 pt_parent) #6 */ +sc_err_t sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_PARENT); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(pt_parent); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 MOVE_ALL(UI8 pt_src, UI8 pt_dst, IB move_rsrc, IB move_pads) #7 */ +sc_err_t sc_rm_move_all(sc_ipc_t ipc, sc_rm_pt_t pt_src, sc_rm_pt_t pt_dst, + sc_bool_t move_rsrc, sc_bool_t move_pads) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MOVE_ALL); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt_src); + RPC_U8(&msg, 1U) = U8(pt_dst); + RPC_U8(&msg, 2U) = B2U8(move_rsrc); + RPC_U8(&msg, 3U) = B2U8(move_pads); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 ASSIGN_RESOURCE(UI8 pt, UI16 resource) #8 */ +sc_err_t sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_RESOURCE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RESOURCE_MOVABLE(UI16 resource_fst, UI16 resource_lst, IB movable) #9 */ +sc_err_t sc_rm_set_resource_movable(sc_ipc_t ipc, sc_rsrc_t resource_fst, + sc_rsrc_t resource_lst, sc_bool_t movable) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_RESOURCE_MOVABLE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource_fst); + RPC_U16(&msg, 2U) = U16(resource_lst); + RPC_U8(&msg, 4U) = B2U8(movable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_SUBSYS_RSRC_MOVABLE(UI16 resource, IB movable) #28 */ +sc_err_t sc_rm_set_subsys_rsrc_movable(sc_ipc_t ipc, sc_rsrc_t resource, + sc_bool_t movable) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_SUBSYS_RSRC_MOVABLE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = B2U8(movable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_MASTER_ATTRIBUTES(UI16 resource, UI8 sa, UI8 pa, IB smmu_bypass) #10 */ +sc_err_t sc_rm_set_master_attributes(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_ATTRIBUTES); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(sa); + RPC_U8(&msg, 3U) = U8(pa); + RPC_U8(&msg, 4U) = B2U8(smmu_bypass); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_MASTER_SID(UI16 resource, UI16 sid) #11 */ +sc_err_t sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MASTER_SID); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U16(&msg, 2U) = U16(sid); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_PERIPHERAL_PERMISSIONS(UI16 resource, UI8 pt, UI8 perm) #12 */ +sc_err_t sc_rm_set_peripheral_permissions(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_PERIPHERAL_PERMISSIONS); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + RPC_U8(&msg, 2U) = U8(pt); + RPC_U8(&msg, 3U) = U8(perm); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RB IS_RESOURCE_OWNED(UI16 resource) #13 */ +sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_OWNED); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_bool_t) U2B(RPC_R8(&msg)); + + /* Return result */ + return result; +} + +/* IDL: E8 GET_RESOURCE_OWNER(UI16 resource, UO8 pt) #33 */ +sc_err_t sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_pt_t *pt) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_OWNER); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (pt != NULL) + { + *pt = (sc_rm_pt_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: RB IS_RESOURCE_MASTER(UI16 resource) #14 */ +sc_bool_t sc_rm_is_resource_master(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_MASTER); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_bool_t) U2B(RPC_R8(&msg)); + + /* Return result */ + return result; +} + +/* IDL: RB IS_RESOURCE_PERIPHERAL(UI16 resource) #15 */ +sc_bool_t sc_rm_is_resource_peripheral(sc_ipc_t ipc, sc_rsrc_t resource) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_RESOURCE_PERIPHERAL); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_bool_t) U2B(RPC_R8(&msg)); + + /* Return result */ + return result; +} + +/* IDL: E8 GET_RESOURCE_INFO(UI16 resource, UO16 sid) #16 */ +sc_err_t sc_rm_get_resource_info(sc_ipc_t ipc, sc_rsrc_t resource, + sc_rm_sid_t *sid) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_RESOURCE_INFO); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(resource); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (sid != NULL) + { + *sid = (sc_rm_sid_t) RPC_U16(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 MEMREG_ALLOC(UO8 mr, UI64 addr_start, UI64 addr_end) #17 */ +sc_err_t sc_rm_memreg_alloc(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 5U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_ALLOC); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mr != NULL) + { + *mr = (sc_rm_mr_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 MEMREG_SPLIT(UI8 mr, UO8 mr_ret, UI64 addr_start, UI64 addr_end) #29 */ +sc_err_t sc_rm_memreg_split(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 6U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_SPLIT); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + RPC_U8(&msg, 16U) = U8(mr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mr_ret != NULL) + { + *mr_ret = (sc_rm_mr_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 MEMREG_FRAG(UO8 mr_ret, UI64 addr_start, UI64 addr_end) #32 */ +sc_err_t sc_rm_memreg_frag(sc_ipc_t ipc, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 5U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FRAG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mr_ret != NULL) + { + *mr_ret = (sc_rm_mr_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 MEMREG_FREE(UI8 mr) #18 */ +sc_err_t sc_rm_memreg_free(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_MEMREG_FREE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 FIND_MEMREG(UO8 mr, UI64 addr_start, UI64 addr_end) #30 */ +sc_err_t sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, + sc_faddr_t addr_end) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 5U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_FIND_MEMREG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_start); + RPC_U32(&msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_end); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (mr != NULL) + { + *mr = (sc_rm_mr_t) RPC_U8(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 ASSIGN_MEMREG(UI8 pt, UI8 mr) #19 */ +sc_err_t sc_rm_assign_memreg(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_MEMREG); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(mr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_MEMREG_PERMISSIONS(UI8 mr, UI8 pt, UI8 perm) #20 */ +sc_err_t sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_pt_t pt, + sc_rm_perm_t perm) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MEMREG_PERMISSIONS); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mr); + RPC_U8(&msg, 1U) = U8(pt); + RPC_U8(&msg, 2U) = U8(perm); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_MEMREG_IEE(UI8 mr, UI8 det, UI8 rmsg) #34 */ +sc_err_t sc_rm_set_memreg_iee(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_det_t det, + sc_rm_rmsg_t rmsg) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_MEMREG_IEE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mr); + RPC_U8(&msg, 1U) = U8(det); + RPC_U8(&msg, 2U) = U8(rmsg); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RB IS_MEMREG_OWNED(UI8 mr) #21 */ +sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_MEMREG_OWNED); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_bool_t) U2B(RPC_R8(&msg)); + + /* Return result */ + return result; +} + +/* IDL: E8 GET_MEMREG_INFO(UI8 mr, UO64 addr_start, UO64 addr_end) #22 */ +sc_err_t sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_GET_MEMREG_INFO); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (addr_start != NULL) + { + *addr_start = (sc_faddr_t) RPC_U64(&msg, 0U); + } + if (addr_end != NULL) + { + *addr_end = (sc_faddr_t) RPC_U64(&msg, 8U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 ASSIGN_PAD(UI8 pt, UI16 pad) #23 */ +sc_err_t sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_ASSIGN_PAD); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + RPC_U8(&msg, 2U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_PAD_MOVABLE(UI16 pad_fst, UI16 pad_lst, IB movable) #24 */ +sc_err_t sc_rm_set_pad_movable(sc_ipc_t ipc, sc_pad_t pad_fst, sc_pad_t pad_lst, + sc_bool_t movable) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_SET_PAD_MOVABLE); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad_fst); + RPC_U16(&msg, 2U) = U16(pad_lst); + RPC_U8(&msg, 4U) = B2U8(movable); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: RB IS_PAD_OWNED(UI16 pad) #25 */ +sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) +{ + sc_rpc_msg_t msg; + sc_bool_t result; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_IS_PAD_OWNED); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(pad); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + result = (sc_bool_t) U2B(RPC_R8(&msg)); + + /* Return result */ + return result; +} + +/* IDL: R0 DUMP() #27 */ +void sc_rm_dump(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_RM); + RPC_FUNC(&msg) = U8(RM_FUNC_DUMP); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); +} + +/** @} */ + diff --git a/platform/svc/rm/rpc_srv.c b/platform/svc/rm/rpc_srv.c new file mode 100644 index 0000000..e0668ca --- /dev/null +++ b/platform/svc/rm/rpc_srv.c @@ -0,0 +1,702 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the RM service. + * + * @addtogroup RM_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/rm/svc.h" +#include "svc/rm/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void rm_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case RM_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch partition_alloc() */ + case RM_FUNC_PARTITION_ALLOC : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) 0U); + sc_bool_t secure = U2B(RPC_U8(msg, 0U)); + sc_bool_t isolated = U2B(RPC_U8(msg, 1U)); + sc_bool_t restricted = U2B(RPC_U8(msg, 2U)); + sc_bool_t grant = U2B(RPC_U8(msg, 3U)); + sc_bool_t coherent = U2B(RPC_U8(msg, 4U)); + + /* Call function */ + err = rm_partition_alloc(caller_pt, &pt, secure, isolated, + restricted, grant, coherent); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(pt); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_confidential() */ + case RM_FUNC_SET_CONFIDENTIAL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_bool_t retro = U2B(RPC_U8(msg, 1U)); + + /* Call function */ + err = rm_set_confidential(caller_pt, pt, retro); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch partition_free() */ + case RM_FUNC_PARTITION_FREE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = rm_partition_free(caller_pt, pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_did() */ + case RM_FUNC_GET_DID : + { + /* Declare return and parameters */ + sc_rm_did_t result; + + /* Call function */ + result = rm_get_did(caller_pt); + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch partition_static() */ + case RM_FUNC_PARTITION_STATIC : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_rm_did_t did = ((sc_rm_did_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = rm_partition_static(caller_pt, pt, did); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch partition_lock() */ + case RM_FUNC_PARTITION_LOCK : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = rm_partition_lock(caller_pt, pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_partition() */ + case RM_FUNC_GET_PARTITION : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) 0U); + + /* Call function */ + err = rm_get_partition(caller_pt, &pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(pt); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_parent() */ + case RM_FUNC_SET_PARENT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_rm_pt_t pt_parent = ((sc_rm_pt_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = rm_set_parent(caller_pt, pt, pt_parent); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch move_all() */ + case RM_FUNC_MOVE_ALL : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt_src = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_rm_pt_t pt_dst = ((sc_rm_pt_t) RPC_U8(msg, 1U)); + sc_bool_t move_rsrc = U2B(RPC_U8(msg, 2U)); + sc_bool_t move_pads = U2B(RPC_U8(msg, 3U)); + + /* Call function */ + err = rm_move_all(caller_pt, pt_src, pt_dst, move_rsrc, + move_pads); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch assign_resource() */ + case RM_FUNC_ASSIGN_RESOURCE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 2U)); + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + err = rm_assign_resource(caller_pt, pt, resource); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_resource_movable() */ + case RM_FUNC_SET_RESOURCE_MOVABLE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource_fst = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rsrc_t resource_lst = ((sc_rsrc_t) RPC_U16(msg, 2U)); + sc_bool_t movable = U2B(RPC_U8(msg, 4U)); + + /* Call function */ + err = rm_set_resource_movable(caller_pt, resource_fst, + resource_lst, movable); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_subsys_rsrc_movable() */ + case RM_FUNC_SET_SUBSYS_RSRC_MOVABLE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_bool_t movable = U2B(RPC_U8(msg, 2U)); + + /* Call function */ + err = rm_set_subsys_rsrc_movable(caller_pt, resource, movable); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_master_attributes() */ + case RM_FUNC_SET_MASTER_ATTRIBUTES : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rm_spa_t sa = ((sc_rm_spa_t) RPC_U8(msg, 2U)); + sc_rm_spa_t pa = ((sc_rm_spa_t) RPC_U8(msg, 3U)); + sc_bool_t smmu_bypass = U2B(RPC_U8(msg, 4U)); + + /* Call function */ + err = rm_set_master_attributes(caller_pt, resource, sa, pa, + smmu_bypass); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_master_sid() */ + case RM_FUNC_SET_MASTER_SID : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rm_sid_t sid = ((sc_rm_sid_t) RPC_U16(msg, 2U)); + + /* Call function */ + err = rm_set_master_sid(caller_pt, resource, sid); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_peripheral_permissions() */ + case RM_FUNC_SET_PERIPHERAL_PERMISSIONS : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 2U)); + sc_rm_perm_t perm = ((sc_rm_perm_t) RPC_U8(msg, 3U)); + + /* Call function */ + err = rm_set_peripheral_permissions(caller_pt, resource, pt, + perm); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch is_resource_owned() */ + case RM_FUNC_IS_RESOURCE_OWNED : + { + /* Declare return and parameters */ + sc_bool_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + result = rm_is_resource_owned(caller_pt, resource); + + /* Copy in return parameters */ + RPC_R8(msg) = B2U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_resource_owner() */ + case RM_FUNC_GET_RESOURCE_OWNER : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rm_pt_t pt = ((sc_rm_pt_t) 0U); + + /* Call function */ + err = rm_get_resource_owner(caller_pt, resource, &pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(pt); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch is_resource_master() */ + case RM_FUNC_IS_RESOURCE_MASTER : + { + /* Declare return and parameters */ + sc_bool_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + result = rm_is_resource_master(caller_pt, resource); + + /* Copy in return parameters */ + RPC_R8(msg) = B2U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch is_resource_peripheral() */ + case RM_FUNC_IS_RESOURCE_PERIPHERAL : + { + /* Declare return and parameters */ + sc_bool_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + + /* Call function */ + result = rm_is_resource_peripheral(caller_pt, resource); + + /* Copy in return parameters */ + RPC_R8(msg) = B2U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_resource_info() */ + case RM_FUNC_GET_RESOURCE_INFO : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rsrc_t resource = ((sc_rsrc_t) RPC_U16(msg, 0U)); + sc_rm_sid_t sid = ((sc_rm_sid_t) 0U); + + /* Call function */ + err = rm_get_resource_info(caller_pt, resource, &sid); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U16(msg, 0U) = U16(sid); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch memreg_alloc() */ + case RM_FUNC_MEMREG_ALLOC : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) 0U); + sc_faddr_t addr_start = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_faddr_t addr_end = ((sc_faddr_t) RPC_U64(msg, 8U)); + + /* Call function */ + err = rm_memreg_alloc(caller_pt, &mr, addr_start, addr_end); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mr); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch memreg_split() */ + case RM_FUNC_MEMREG_SPLIT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 16U)); + sc_rm_mr_t mr_ret = ((sc_rm_mr_t) 0U); + sc_faddr_t addr_start = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_faddr_t addr_end = ((sc_faddr_t) RPC_U64(msg, 8U)); + + /* Call function */ + err = rm_memreg_split(caller_pt, mr, &mr_ret, addr_start, + addr_end); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mr_ret); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch memreg_frag() */ + case RM_FUNC_MEMREG_FRAG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr_ret = ((sc_rm_mr_t) 0U); + sc_faddr_t addr_start = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_faddr_t addr_end = ((sc_faddr_t) RPC_U64(msg, 8U)); + + /* Call function */ + err = rm_memreg_frag(caller_pt, &mr_ret, addr_start, addr_end); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mr_ret); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch memreg_free() */ + case RM_FUNC_MEMREG_FREE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 0U)); + + /* Call function */ + err = rm_memreg_free(caller_pt, mr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch find_memreg() */ + case RM_FUNC_FIND_MEMREG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) 0U); + sc_faddr_t addr_start = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_faddr_t addr_end = ((sc_faddr_t) RPC_U64(msg, 8U)); + + /* Call function */ + err = rm_find_memreg(caller_pt, &mr, addr_start, addr_end); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 0U) = U8(mr); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch assign_memreg() */ + case RM_FUNC_ASSIGN_MEMREG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = rm_assign_memreg(caller_pt, pt, mr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_memreg_permissions() */ + case RM_FUNC_SET_MEMREG_PERMISSIONS : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 0U)); + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 1U)); + sc_rm_perm_t perm = ((sc_rm_perm_t) RPC_U8(msg, 2U)); + + /* Call function */ + err = rm_set_memreg_permissions(caller_pt, mr, pt, perm); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_memreg_iee() */ + case RM_FUNC_SET_MEMREG_IEE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 0U)); + sc_rm_det_t det = ((sc_rm_det_t) RPC_U8(msg, 1U)); + sc_rm_rmsg_t rmsg = ((sc_rm_rmsg_t) RPC_U8(msg, 2U)); + + /* Call function */ + err = rm_set_memreg_iee(caller_pt, mr, det, rmsg); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch is_memreg_owned() */ + case RM_FUNC_IS_MEMREG_OWNED : + { + /* Declare return and parameters */ + sc_bool_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 0U)); + + /* Call function */ + result = rm_is_memreg_owned(caller_pt, mr); + + /* Copy in return parameters */ + RPC_R8(msg) = B2U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_memreg_info() */ + case RM_FUNC_GET_MEMREG_INFO : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_mr_t mr = ((sc_rm_mr_t) RPC_U8(msg, 0U)); + sc_faddr_t addr_start = ((sc_faddr_t) 0U); + sc_faddr_t addr_end = ((sc_faddr_t) 0U); + + /* Call function */ + err = rm_get_memreg_info(caller_pt, mr, &addr_start, &addr_end); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(addr_start >> 32ULL); + RPC_U32(msg, 4U) = U32(addr_start); + RPC_U32(msg, 8U) = U32(addr_end >> 32ULL); + RPC_U32(msg, 12U) = U32(addr_end); + RPC_SIZE(msg) = 5U; + break; + } + /* Dispatch assign_pad() */ + case RM_FUNC_ASSIGN_PAD : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 2U)); + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + + /* Call function */ + err = rm_assign_pad(caller_pt, pt, pad); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_pad_movable() */ + case RM_FUNC_SET_PAD_MOVABLE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_pad_t pad_fst = ((sc_pad_t) RPC_U16(msg, 0U)); + sc_pad_t pad_lst = ((sc_pad_t) RPC_U16(msg, 2U)); + sc_bool_t movable = U2B(RPC_U8(msg, 4U)); + + /* Call function */ + err = rm_set_pad_movable(caller_pt, pad_fst, pad_lst, movable); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch is_pad_owned() */ + case RM_FUNC_IS_PAD_OWNED : + { + /* Declare return and parameters */ + sc_bool_t result; + sc_pad_t pad = ((sc_pad_t) RPC_U16(msg, 0U)); + + /* Call function */ + result = rm_is_pad_owned(caller_pt, pad); + + /* Copy in return parameters */ + RPC_R8(msg) = B2U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch dump() */ + case RM_FUNC_DUMP : + { + /* Declare return and parameters */ + + /* Call function */ + rm_dump(caller_pt); + + /* Copy in return parameters */ + RPC_SIZE(msg) = 1U; + break; + } + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=rm, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=rm, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/rm/svc.c b/platform/svc/rm/svc.c new file mode 100755 index 0000000..33b69e0 --- /dev/null +++ b/platform/svc/rm/svc.c @@ -0,0 +1,3718 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/rm/svc.c + * + * File containing the implementation of the System Controller (SC) Resource + * Management (RM) function. This includes functions for partitioning + * resources, pads, and memory regions. + * + * @addtogroup RM_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "main/soc.h" +#include "main/board.h" +#include "svc/rm/svc.h" +#include "svc/pm/svc.h" +#include "svc/timer/svc.h" +#include "ss/inf/inf.h" +#include "ss_ver.h" +#if SS_VER_BASE == 1 +#include "ss/base/v1/ss.h" +#endif +#include "drivers/sysctr/fsl_sysctr.h" + +/* Local Defines */ + +#if 0 + /*! Define to enable RM timing */ + #define PROF_RM +#endif + +/*! Define for MRC alignment */ +#define MRC_ALIGN 0xFFFULL + +/*! + * @name Parameter checking macros + */ +/** @{ */ +#define USED_MR(X) ASRT_ERR(rm_mreg_data[(X)].used != SC_FALSE, SC_ERR_PARM) +#define USED_MR_C(X) ASRT_C(rm_mreg_data[(X)].used != SC_FALSE) +#define NOT_RESTRICTED(X) ASRT_ERR(rm_part_data[(X)].restricted == SC_FALSE, SC_ERR_NOACCESS) +#define NOT_LOCKED(X) ASRT_ERR(rm_part_data[(X)].locked == SC_FALSE, SC_ERR_LOCKED) +#define NOT_LOCKED_C(X) ASRT_C(rm_part_data[(X)].locked == SC_FALSE) +#define PARENT(X) ASRT_ERR(caller_pt == rm_part_data[(X)].parent, SC_ERR_NOACCESS) +/** @} */ + +#ifdef PROF_RM + #define START_TIMER(X) \ + uint32_t (X) = SYSCTR_GetCounter32() +#else + #define START_TIMER(X) NOP +#endif + +#ifdef PROF_RM + #define STOP_TIMER(X) \ + (X) = SYSCTR_GetCounter32() - (X) +#else + #define STOP_TIMER(X) NOP +#endif + +/* Local Types */ + +/*! + * This type is used to store compressed permissions. + */ +typedef uint8_t permz_t; + +/*! + * This type is used to store dynamic info needed to track partition + * specific data for the resource management service. + */ +typedef struct +{ + sc_rm_pt_t parent : SC_RM_PARTITION_W; + sc_rm_pt_t control : SC_RM_PARTITION_W; + sc_rm_did_t did : SC_RM_DID_W; + sc_bool_t used : SC_BOOL_W; + sc_bool_t secure : SC_BOOL_W; + sc_bool_t restricted : SC_BOOL_W; + sc_bool_t isolated : SC_BOOL_W; + sc_bool_t locked : SC_BOOL_W; + sc_bool_t confidential : SC_BOOL_W; + sc_bool_t grant : SC_BOOL_W; + sc_bool_t sys_access : SC_BOOL_W; +} rm_part_data_t; + +/*! + * This type is used to store dynamic info needed to track + * resource state. + */ +typedef struct +{ + permz_t perms[SC_RM_NUM_DOMAIN / 2]; + sc_rm_sid_t sid : SC_RM_SID_W; + sc_ss_idx_t ss_idx : SC_SS_IDX_W; + sc_sub_t ss : SC_SUBSYS_W; + sc_rm_spa_t sa : SC_RM_PERM_W; + sc_rm_spa_t pa : SC_RM_PERM_W; + sc_rm_pt_t owner : SC_RM_PARTITION_W; + sc_bool_t movable : SC_BOOL_W; + sc_bool_t block : SC_BOOL_W; +} rm_rsrc_data_t; + +/*! + * This type is used to store dynamic info needed to track + * pad state. + */ +typedef struct +{ + sc_rm_pt_t owner : SC_RM_PARTITION_W; + sc_bool_t movable : SC_BOOL_W; +} rm_pad_data_t; + +/*! + * This type is used to store dynamic info needed to track + * memory region state. + */ +typedef struct +{ + sc_faddr_t start; + sc_faddr_t end; + sc_rm_mr_t parent : SC_RM_MEMREG_W; + sc_rm_pt_t owner : SC_RM_PARTITION_W; + sc_rm_rmsg_t rmsg : SC_RM_RMSG_W; + sc_rm_det_t det : SC_RM_DET_W; + sc_bool_t used : SC_BOOL_W; + permz_t perms[SC_RM_NUM_DOMAIN / 2]; +} rm_mreg_data_t; + +/* Local Functions */ + +/*! + * @name Private Functions + * @{ + */ +static void clear_perms(permz_t *perms); +static void copy_perms(sc_rm_mr_t mr_src, sc_rm_mr_t mr_dst); +static void set_perms(permz_t *perms, sc_rm_did_t did, + sc_rm_perm_t perm); +static void get_perms(const permz_t *perms, sc_rm_did_t did, + sc_rm_perm_t *perm); +static void update_rdc_resource(sc_rm_idx_t idx, sc_bool_t master, + sc_bool_t peripheral); +static sc_err_t update_rdc_memreg(sc_rm_mr_t mr, sc_faddr_t old_start, + sc_faddr_t old_end, sc_faddr_t new_start, sc_faddr_t new_end); +/** @} */ + +/*! + * @name Local Variables + * + * @{ + */ +static rm_part_data_t rm_part_data[SC_RM_NUM_PARTITION]; +static sc_rm_idx_t rm_rsrc_map_data[SC_NUM_RESOURCE]; +static sc_rm_idx_t rm_ss_map_data[SC_NUM_SUBSYS]; +static rm_rsrc_data_t rm_rsrc_data[SC_NUM_RSRC]; +static rm_pad_data_t rm_pad_data[SC_NUM_PAD]; +static rm_mreg_data_t rm_mreg_data[SC_RM_NUM_MEMREG]; +static sc_rm_mr_t rm_mreg_list[SC_RM_NUM_MEMREG]; +static sc_rm_mr_t rm_mreg_list_count = 0U; +static sc_bool_t did_used[SC_RM_NUM_DOMAIN]; +static sc_rm_pt_t dynamic_pt_first; +static sc_rm_did_t dynamic_did_first; +static sc_bool_t blocking = SC_FALSE; +/** @} */ + +/* Global Variables */ + +/*! Max domain used */ +uint8_t rm_max_did = SC_DID; + +#if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + /*! Partition name pointers */ + const char *rm_part_names[SC_RM_NUM_PARTITION]; +#endif + +/*--------------------------------------------------------------------------*/ +/* Init the resource management service */ +/*--------------------------------------------------------------------------*/ +void rm_init(sc_bool_t api_phase) +{ + if (api_phase != SC_FALSE) + { + sc_sub_t s; + sc_rm_idx_t r; + uint8_t loop; + sc_pad_t n; + + /* Init index mapping info */ + for (r = 0; r < (sc_rm_idx_t) SC_NUM_RESOURCE; r++) + { + rm_rsrc_map_data[r] = SC_NUM_RSRC; + } + + /* Allocate SC DID */ + did_used[SC_DID] = SC_TRUE; + + /* Parition SC_PT allocated to SC */ + rm_part_data[SC_PT].used = SC_TRUE; + #if SC_PT != 0 + rm_part_data[SC_PT].parent = SC_PT; + rm_part_data[SC_PT].control = SC_PT; + #endif + rm_part_data[SC_PT].secure = SC_TRUE; + rm_part_data[SC_PT].isolated = SC_TRUE; + #if SC_DID != 0 + rm_part_data[SC_PT].did = SC_DID; + #endif + rm_part_data[SC_PT].sys_access = SC_FALSE; + + /* All resources owned by SC */ + for (r = 0; r < SC_NUM_RSRC; r++) + { + #if SC_PT != 0 + rm_rsrc_data[r].owner = SC_PT; + #endif + #if SC_BYPASS_SID != 0 + rm_rsrc_data[r].sid = SC_BYPASS_SID; + #endif + rm_rsrc_data[r].sa = SC_SA; + rm_rsrc_data[r].pa = SC_PA; + rm_rsrc_data[r].movable = SC_TRUE; + rm_rsrc_data[r].block = SC_TRUE; + set_perms(rm_rsrc_data[r].perms, SC_DID, SC_RM_PERM_SEC_RW); + } + + /* Fill in SS mapping info */ + r = 0; + for (s = 0; s < SC_NUM_SUBSYS; s++) + { + sc_ss_inst_t inst = sc_ss_info[s].inst; + + rm_ss_map_data[s] = r; + + #ifdef SIMU + if (r >= SC_NUM_RSRC) + { + error_print("error: Rsrc map ovfl: %s\n", + snames[s]); + break; + } + #endif + + for (loop = 0; loop < ss_base_info[s]->num_rsrc; loop++) + { + sc_rm_idx_t idx = (inst * ss_base_info[s]->num_rsrc) + loop; + + /* Check for mapping error */ + #ifdef SIMU + if (rm_rsrc_map_data[ss_base_info[s]->rsrc_map[idx].resource] + != SC_NUM_RSRC) + { + error_print("error: Rsrc map: %s #%d\n", + snames[s], loop); + break; + } + #endif + + /* Fill in resource to index info */ + rm_rsrc_map_data[ss_base_info[s]->rsrc_map[idx].resource] + = r; + + /* Fill in index to ss info */ + rm_rsrc_data[r].ss = s; + rm_rsrc_data[r].ss_idx = loop; + r++; + } + } + + /* Fill in board mapping info */ + for (loop = 0; loop < board_num_rsrc; loop++) + { + #ifdef SIMU + if (r >= SC_NUM_RSRC) + { + error_print("error: Rsrc map ovfl: board\n"); + break; + } + #endif + + /* Check for mapping error */ + #ifdef SIMU + if (rm_rsrc_map_data[board_rsrc_map[loop].resource] + != SC_NUM_RSRC) + { + error_print("error: Rsrc map: BOARD #%d\n", + loop); + } + #endif + + /* Fill in resource to index info */ + rm_rsrc_map_data[board_rsrc_map[loop].resource] + = r; + + /* Fill in index to board info */ + rm_rsrc_data[r].ss = SC_SUBSYS_NA; + rm_rsrc_data[r].ss_idx = loop; + r++; + } + + /* All pads owned by SC */ + for (n = 0; n < SC_NUM_PAD; n++) + { + #if SC_PT != 0 + rm_pad_data[n].owner = SC_PT; + #endif + rm_pad_data[n].movable = SC_TRUE; + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Define number of static partitions */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_reserve_static_pt(sc_rm_pt_t num) +{ + /* Set first dynamic */ + dynamic_pt_first = num; + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Define number of static domains */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_reserve_static_did(sc_rm_did_t num) +{ + SIMU_ASRT(num < SC_RM_NUM_PARTITION, + "bad pt"); + + /* Set first dynamic */ + dynamic_did_first = num; + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Allocate a new resource partition and return a handle */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_partition_alloc(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt, + sc_bool_t secure, sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, + sc_bool_t coherent) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + NOT_LOCKED(caller_pt); + NOT_RESTRICTED(caller_pt); + ASRT_ERR((secure == SC_FALSE) || (rm_part_data[caller_pt].secure != SC_FALSE), + SC_ERR_NOACCESS); + + if (err == SC_ERR_NONE) + { + sc_rm_pt_t p; + + /* Find unallocated partition */ + err = SC_ERR_UNAVAILABLE; + for (p = dynamic_pt_first; p < SC_RM_NUM_PARTITION; p++) + { + if (rm_part_data[p].used == SC_FALSE) + { + /* Init parameters */ + rm_part_data[p].used = SC_TRUE; + rm_part_data[p].parent = caller_pt; + rm_part_data[p].secure = secure; + rm_part_data[p].isolated = isolated; + rm_part_data[p].restricted = restricted; + rm_part_data[p].grant = grant; + rm_part_data[p].locked = SC_FALSE; + rm_part_data[p].sys_access = SC_FALSE; + rm_part_data[p].control = SC_PT; + #if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + rm_part_names[p] = NULL; + #endif + /* Init power and timer state */ + pm_init_part(caller_pt, p); + timer_init_part(caller_pt, p); + + /* Allocate a DID */ + if (isolated != SC_FALSE) + { + /* Coherent? */ + if (coherent != SC_FALSE) + { + /* Use DID 0 if available */ + if (did_used[0] == SC_FALSE) + { + did_used[0] = SC_TRUE; + rm_part_data[p].did = 0; + err = SC_ERR_NONE; + } + } + else + { + sc_rm_did_t d; + + /* Search for an unused DID */ + for (d = dynamic_did_first; d < SC_RM_NUM_DOMAIN; d++) + { + /* Found unused? */ + if (did_used[d] == SC_FALSE) + { + did_used[d] = SC_TRUE; + rm_part_data[p].did = d; + rm_max_did = MAX(rm_max_did, d); + err = SC_ERR_NONE; + + break; + } + } + } + } + else + { + /* Reuse caller DID */ + rm_part_data[p].did = rm_part_data[caller_pt].did; + err = SC_ERR_NONE; + } + + if (err == SC_ERR_NONE) + { + *pt = p; + } + else + { + /* No DID found so unallocate */ + rm_part_data[p].used = SC_FALSE; + } + + break; + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Make partition confidential */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_confidential(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_bool_t retro) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + USED_PT(pt); + NOT_LOCKED(pt); + PARENT(pt); + + if (err == SC_ERR_NONE) + { + /* Mark partition */ + rm_part_data[pt].confidential= SC_TRUE; + + /* Remove permissions */ + if (retro != SC_FALSE) + { + sc_rm_idx_t r; + sc_rm_mr_t m; + + /* Loop through all resources */ + for (r = 0; r < SC_NUM_RSRC; r++) + { + if (rm_rsrc_data[r].owner != pt) + { + set_perms(rm_rsrc_data[r].perms, rm_part_data[pt].did, + SC_RM_PERM_NONE); + } + } + + /* Loop through all memory regions */ + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if (rm_mreg_data[m].owner != pt) + { + set_perms(rm_mreg_data[m].perms, rm_part_data[pt].did, + SC_RM_PERM_NONE); + } + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Free a resource partition and return resources to the parent partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_partition_free(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + USED_PT(pt); + NOT_SC_PT(pt); + + /* Check more parameters if caller not SC */ + if (caller_pt != SC_PT) + { + NOT_LOCKED(caller_pt); + NOT_LOCKED(pt); + NOT_RESTRICTED(caller_pt); + PARENT(pt); + } + + if (err == SC_ERR_NONE) + { + sc_rm_idx_t r; + sc_pad_t n; + sc_rm_mr_t m; + sc_rm_pt_t p; + + /* Call timer service to stop wdog */ + timer_halt_wdog(pt); + + /* Free all child partitions */ + for (p = 0; p < SC_RM_NUM_PARTITION; p++) + { + /* Used and belongs to this partition? */ + if ((rm_part_data[p].used != SC_FALSE) && (rm_part_data[p].parent == pt)) + { + rm_part_data[p].locked = SC_FALSE; + (void) rm_partition_free(rm_part_data[p].parent, p); + } + } + + /* Return all resources to parent */ + for (r = 0; r < SC_NUM_RSRC; r++) + { + /* Is available? */ + if (rm_is_ridx_avail(r) == SC_FALSE) + { + continue; + } + + /* Owned by this partiton? */ + if (rm_rsrc_data[r].owner == pt) + { + /* Return attributes to the default */ + rm_rsrc_data[r].owner = rm_part_data[pt].parent; + pm_update_ridx(r); + rm_rsrc_data[r].pa = SC_RM_SPA_PASSTHRU; + rm_rsrc_data[r].movable = SC_TRUE; + clear_perms(rm_rsrc_data[r].perms); + SIMU_ASRT(rm_rsrc_data[r].owner < SC_RM_NUM_PARTITION, + "bad owner pt"); + if (rm_part_data[rm_rsrc_data[r].owner].secure != SC_FALSE) + { + /* Make secure when returned */ + rm_rsrc_data[r].sa = SC_RM_SPA_ASSERT; + set_perms(rm_rsrc_data[r].perms, + rm_part_data[rm_rsrc_data[r].owner].did, + SC_RM_PERM_SEC_RW); + } + else + { + /* Make not-secure when returned */ + rm_rsrc_data[r].sa = SC_RM_SPA_NEGATE; + set_perms(rm_rsrc_data[r].perms, + rm_part_data[rm_rsrc_data[r].owner].did, + SC_RM_PERM_FULL); + } + + /* Update the resource */ + update_rdc_resource(r, SC_TRUE, SC_TRUE); + } + } + + /* Return all pads to parent */ + for (n = 0; n < SC_NUM_PAD; n++) + { + /* Owned by this partiton? */ + if (rm_pad_data[n].owner == pt) + { + rm_pad_data[n].owner = rm_part_data[pt].parent; + rm_pad_data[n].movable = SC_TRUE; + } + } + + /* Delete child memory regions */ + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + /* Owned by this partiton? */ + if (rm_mreg_data[m].owner == pt) + { + sc_rm_mr_t m_parent = rm_mreg_data[m].parent; + + /* Check parms */ + SIMU_ASRT(m_parent < SC_RM_NUM_PARTITION, + "bad parent pt"); + + if (rm_mreg_data[m].parent == m) + { + continue; + } + + if (rm_mreg_data[m_parent].owner == pt) + { + (void) rm_memreg_free(SC_PT, m); + } + if (rm_mreg_data[m_parent].owner == rm_part_data[pt].parent) + { + (void) rm_memreg_free(SC_PT, m); + } + } + } + + /* Return all remaining memory regions */ + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + /* Owned by this partiton? */ + if (rm_mreg_data[m].owner == pt) + { + (void) rm_assign_memreg(SC_PT, rm_part_data[pt].parent, m); + } + } + + /* Free DID */ + SIMU_ASRT(rm_part_data[pt].did < SC_RM_NUM_DOMAIN, + "bad DID"); + if (rm_part_data[pt].isolated != SC_FALSE) + { + did_used[rm_part_data[pt].did] = SC_FALSE; + } + + /* Free partition */ + rm_part_data[pt].used = SC_FALSE; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get partition of caller */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_get_partition(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + *pt = caller_pt; + + SIMU_ASRT(*pt < SC_RM_NUM_PARTITION, + "bad pt"); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get enable state of a partition */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_partition_used(sc_rm_pt_t pt) +{ + SIMU_ASRT(pt < SC_RM_NUM_PARTITION, + "bad pt"); + + return rm_part_data[pt].used; +} + +/*--------------------------------------------------------------------------*/ +/* Get security state of a partition */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_secure_partition(sc_rm_pt_t caller_pt) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + rtn = rm_part_data[caller_pt].secure; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Get isolation state of a partition */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_partition_isolated(sc_rm_pt_t pt) +{ + SIMU_ASRT(pt < SC_RM_NUM_PARTITION, + "bad pt"); + + return rm_part_data[pt].isolated; +} + +/*--------------------------------------------------------------------------*/ +/* Get system access state of a partition */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_sys_access(sc_rm_pt_t pt) +{ + sc_bool_t rtn; + + /* Check parms */ + SIMU_ASRT(pt < SC_RM_NUM_PARTITION, + "bad pt"); + + /* Is SC? */ + if (pt == SC_PT) + { + rtn = SC_TRUE; + } + /* Own SYSTEM? */ + else if (rm_is_resource_owned(pt, SC_R_SYSTEM) != SC_FALSE) + { + rtn = SC_TRUE; + } + /* Access to SYSTEM? */ + else + { + rtn = rm_part_data[pt].sys_access; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Set partition that can control a partition */ +/*--------------------------------------------------------------------------*/ +void rm_set_control_partition(sc_rm_pt_t pt, sc_rm_pt_t control) +{ + /* Check parms */ + SIMU_ASRT(pt < SC_RM_NUM_PARTITION, + "bad pt"); + SIMU_ASRT(control < SC_RM_NUM_PARTITION, + "bad pt"); + + rm_part_data[pt].control = control; +} + +/*--------------------------------------------------------------------------*/ +/* Get control partition */ +/*--------------------------------------------------------------------------*/ +sc_rm_pt_t rm_get_control_partition(sc_rm_pt_t pt) +{ + return rm_part_data[pt].control; +} + +/*--------------------------------------------------------------------------*/ +/* Get parent of a partition */ +/*--------------------------------------------------------------------------*/ +sc_rm_pt_t rm_get_partition_parent(sc_rm_pt_t pt) +{ + SIMU_ASRT(pt < SC_RM_NUM_PARTITION, + "bad pt"); + + SIMU_ASRT(rm_part_data[pt].parent < SC_RM_NUM_PARTITION, + "bad pt"); + + return rm_part_data[pt].parent; +} + +/*--------------------------------------------------------------------------*/ +/* Get resource domain of caller */ +/*--------------------------------------------------------------------------*/ +sc_rm_did_t rm_get_did(sc_rm_pt_t caller_pt) +{ + sc_rm_did_t did = SC_DID; + + SIMU_ASRT(caller_pt < SC_RM_NUM_PARTITION, + "bad caller_pt"); + + if (caller_pt < SC_RM_NUM_PARTITION) + { + did = rm_part_data[caller_pt].did; + } + + SIMU_ASRT(did < SC_RM_NUM_DOMAIN, + "bad did"); + + return did; +} + +/*--------------------------------------------------------------------------*/ +/* Force a partition onto a static DID (assumes no assigned resources */ +/* or mem regions) */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_partition_static(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rm_did_t did) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + ASRT_ERR(did < dynamic_did_first, SC_ERR_PARM); + + /* Check parameters */ + USED_PT(pt); + NOT_LOCKED(pt); + NOT_RESTRICTED(caller_pt); + + /* Check access rights */ + PARENT(pt); + ASRT_ERR(did_used[did] == SC_FALSE, SC_ERR_UNAVAILABLE); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Check parms */ + SIMU_ASRT(rm_part_data[pt].did < SC_RM_NUM_DOMAIN, + "bad DID"); + + /* Swap DIDs */ + did_used[rm_part_data[pt].did] = SC_FALSE; + rm_part_data[pt].did = did; + rm_max_did = MAX(rm_max_did, did); + did_used[rm_part_data[pt].did] = SC_TRUE; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Lock a partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_partition_lock(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + PARENT(pt); + + if (err == SC_ERR_NONE) + { + /* Lock partition */ + rm_part_data[pt].locked = SC_TRUE; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set new parent for partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_parent(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_pt_t p; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + BOUND_PT(pt_parent); + + /* Check parameters */ + USED_PT(pt); + USED_PT(pt_parent); + NOT_LOCKED(pt); + NOT_LOCKED(pt_parent); + NOT_RESTRICTED(caller_pt); + PARENT(pt); + NOT_SC_PT(pt); + + /* Check for circular relationship */ + p = pt_parent; + while ((err == SC_ERR_NONE) && (p != SC_PT)) + { + if (rm_part_data[p].parent == pt) + { + err = SC_ERR_PARM; + } + + p = rm_part_data[p].parent; + } + + /* Check for error */ + if (err == SC_ERR_NONE) + { + sc_rm_idx_t r; + sc_rm_mr_t m; + + /* Update parent */ + rm_part_data[pt].parent = pt_parent; + + /* Update all resources */ + for (r = 0; r < SC_NUM_RSRC; r++) + { + /* Resource owned by this partition? */ + if (rm_rsrc_data[r].owner == pt) + { + /* Update resource */ + update_rdc_resource(r, SC_FALSE, SC_TRUE); + } + } + + /* Update all memory regions */ + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + /* Mem region owned by this partition? */ + if ((rm_mreg_data[m].used != SC_FALSE) + && (rm_mreg_data[m].owner == pt)) + { + /* Update memory region */ + (void) update_rdc_memreg(m, rm_mreg_data[m].start, + rm_mreg_data[m].end, rm_mreg_data[m].start, + rm_mreg_data[m].end); + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check if caller is the parent of a partition */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_parent(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + if (err == SC_ERR_NONE) + { + /* Check parent */ + rtn = (caller_pt == rm_part_data[pt].parent); + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if caller is an ancestor of owner */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_check_ancestor(sc_rm_pt_t caller_pt, sc_rm_pt_t pt_owner) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt_owner); + + if (err == SC_ERR_NONE) + { + sc_rm_pt_t pt; + + /* SCU always ancestor */ + if (caller_pt == SC_PT) + { + rtn = SC_TRUE; + } + + /* Loop looking for ancestor */ + pt = pt_owner; + while ((rtn == SC_FALSE) && (pt != SC_PT)) + { + if (caller_pt == pt) + { + rtn = SC_TRUE; + } + + pt = rm_part_data[pt].parent; + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Move all resources/pads owned by src partition to dst partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_move_all(sc_rm_pt_t caller_pt, sc_rm_pt_t pt_src, + sc_rm_pt_t pt_dst, sc_bool_t move_rsrc, sc_bool_t move_pads) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt_src); + BOUND_PT(pt_dst); + + /* Check parameters */ + USED_PT(pt_src); + USED_PT(pt_dst); + NOT_LOCKED(pt_src); + NOT_LOCKED(pt_dst); + NOT_RESTRICTED(caller_pt); + ASRT_ERR(pt_src != pt_dst, SC_ERR_PARM); + ANCESTOR(pt_src); + + if (err == SC_ERR_NONE) + { + /* Move all resources from src to dst */ + if (move_rsrc != SC_FALSE) + { + sc_rm_idx_t r; + sc_rm_idx_t jr1 = SC_NUM_RESOURCE, jr3 = SC_NUM_RESOURCE; + + /* Get CAAM indexes */ + rm_check_map_ridx_v(SC_R_CAAM_JR1_OUT, &jr1); + rm_check_map_ridx_v(SC_R_CAAM_JR3_OUT, &jr3); + + /* Loop over all resources */ + for (r = 0; r < SC_NUM_RSRC; r++) + { + /* Check if available */ + if (rm_is_ridx_avail(r) == SC_FALSE) + { + continue; + } + + /* Is movable? */ + if ((rm_rsrc_data[r].movable != SC_FALSE) + && ((rm_rsrc_data[r].owner == pt_src) + || (caller_pt == SC_PT))) + { + /* Only allow JR_OUT resources to be assigned to child */ + if ((r >= jr1) + && (r <= jr3)) + { + ANCESTOR_C(pt_dst); + } + + /* Update owner */ + rm_rsrc_data[r].owner = pt_dst; + pm_update_ridx(r); + + /* Update attributes */ + rm_rsrc_data[r].pa = SC_RM_SPA_PASSTHRU; + clear_perms(rm_rsrc_data[r].perms); + if (rm_part_data[pt_dst].secure != SC_FALSE) + { + /* Secure */ + rm_rsrc_data[r].sa = SC_RM_SPA_ASSERT; + set_perms(rm_rsrc_data[r].perms, + rm_part_data[pt_dst].did, SC_RM_PERM_SEC_RW); + } + else + { + /* Not secure */ + rm_rsrc_data[r].sa = SC_RM_SPA_NEGATE; + set_perms(rm_rsrc_data[r].perms, + rm_part_data[pt_dst].did, SC_RM_PERM_FULL); + } + + /* Update SID */ + rm_rsrc_data[r].sid = SC_BYPASS_SID; + update_rdc_resource(r, SC_TRUE, SC_TRUE); + } + } + + /* Update memory regions that might now be in different MRCs */ + rm_load_memrg(); + } + + /* Move all pads from src to dst */ + if (move_pads != SC_FALSE) + { + sc_pad_t n; + + for (n = 0; n < SC_NUM_PAD; n++) + { + /* Is movable? */ + if ((rm_pad_data[n].movable != SC_FALSE) + && ((rm_pad_data[n].owner == pt_src) + || (caller_pt == SC_PT))) + { + rm_pad_data[n].owner = pt_dst; + } + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Assign a resource to a resource partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_assign_resource(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_rsrc_t r0, rN; + sc_bool_t sync_mem = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + USED_PT(pt); + NOT_LOCKED(caller_pt); + NOT_LOCKED(pt); + NOT_RESTRICTED(caller_pt); + + /* Is one or all resources? */ + if (resource == SC_R_ALL) + { + /* Set range to cover all resources */ + r0 = 0; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + /* Check parameters */ + BOUND_RSRC(resource, idx); + ANCESTOR(rm_rsrc_data[idx].owner); + NOT_LOCKED(rm_rsrc_data[idx].owner); + + /* Only allow JR_OUT resources to be assigned to child */ + if ((resource >= SC_R_CAAM_JR1_OUT) + && (resource <= SC_R_CAAM_JR3_OUT)) + { + ANCESTOR(pt); + } + + /* Set range to cover only the specified resource */ + r0 = resource; + rN = resource; + } + + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = r0; r <= rN; r++) + { + sc_rm_did_t old_did; + + if (resource == SC_R_ALL) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + + /* Check ownership */ + ANCESTOR_C(rm_rsrc_data[idx].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_rsrc_data[idx].owner); + + /* Only allow JR_OUT resources to be assigned to child */ + if ((r >= SC_R_CAAM_JR1_OUT) + && (r <= SC_R_CAAM_JR3_OUT)) + { + ANCESTOR_C(pt); + } + } + + /* Keep old DID */ + SIMU_ASRT(rm_rsrc_data[idx].owner < SC_RM_NUM_PARTITION, + "bad owner"); + old_did = rm_part_data[rm_rsrc_data[idx].owner].did; + + /* Assign resource */ + rm_rsrc_data[idx].owner = pt; + pm_update_ridx(idx); + + /* Default access permissions */ + rm_rsrc_data[idx].pa = SC_RM_SPA_PASSTHRU; + clear_perms(rm_rsrc_data[idx].perms); + if (rm_part_data[pt].secure != SC_FALSE) + { + rm_rsrc_data[idx].sa = SC_RM_SPA_ASSERT; + set_perms(rm_rsrc_data[idx].perms, rm_part_data[pt].did, + SC_RM_PERM_SEC_RW); + } + else + { + rm_rsrc_data[idx].sa = SC_RM_SPA_NEGATE; + set_perms(rm_rsrc_data[idx].perms, rm_part_data[pt].did, + SC_RM_PERM_FULL); + } + rm_rsrc_data[idx].movable = SC_TRUE; + + /* Set SID */ + rm_rsrc_data[idx].sid = SC_BYPASS_SID; + + /* Update resource */ + update_rdc_resource(idx, SC_TRUE, SC_TRUE); + + /* Check if MRC might change */ + if ((rm_is_ridx_master(idx) != SC_FALSE) + && (old_did != rm_part_data[pt].did)) + { + sync_mem = SC_TRUE; + } + } + } + + /* Update memory regions that might now be in different MRCs */ + if ((err == SC_ERR_NONE) && (sync_mem != SC_FALSE)) + { + rm_load_memrg(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Flag resource as movable or not */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_resource_movable(sc_rm_pt_t caller_pt, + sc_rsrc_t resource_fst, sc_rsrc_t resource_lst, sc_bool_t movable) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_rsrc_t r0, rN; + sc_rsrc_t new_resource_fst = resource_fst; + sc_rsrc_t new_resource_lst = resource_lst; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Is one or all resources? */ + if ((new_resource_fst == SC_R_ALL) || (new_resource_lst == SC_R_ALL)) + { + /* Set range to cover all resources */ + r0 = 0; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + if (new_resource_fst > new_resource_lst) + { + sc_rsrc_t temp = new_resource_fst; + new_resource_fst = new_resource_lst; + new_resource_lst = temp; + } + + /* Check parameters */ + if (new_resource_lst >= SC_NUM_RESOURCE) + { + err = SC_ERR_PARM; + } + else if (new_resource_fst > new_resource_lst) + { + err = SC_ERR_PARM; + } + else + { + ; /* Intentional empty else */ + } + + /* Set range to cover only the specified resource */ + r0 = new_resource_fst; + rN = new_resource_lst; + } + + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = r0; r <= rN; r++) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + + /* Check ownership */ + ANCESTOR_C(rm_rsrc_data[idx].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_rsrc_data[idx].owner); + + /* Set flag */ + rm_rsrc_data[idx].movable = movable; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Flag resource group as movable or not */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_subsys_rsrc_movable(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_bool_t movable) +{ + sc_err_t err = SC_ERR_NONE; + sc_sub_t ss; + sc_ss_idx_t ss_idx; + sc_rm_idx_t idx; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + /* Get subsystem */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + + /* Loop through all resources and flag */ + for (idx = 0; idx < SC_NUM_RSRC; idx++) + { + ANCESTOR_C(rm_rsrc_data[idx].owner); + + if (rm_rsrc_data[idx].ss == ss) + { + rm_rsrc_data[idx].movable = movable; + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set attributes for a master resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_master_attributes(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_rsrc_t r0, rN; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + NOT_RESTRICTED(caller_pt); + ASRT_ERR(sa <= SC_RM_SPA_NEGATE, SC_ERR_PARM); + ASRT_ERR(pa <= SC_RM_SPA_NEGATE, SC_ERR_PARM); + + /* Is one or all resources? */ + if (resource == SC_R_ALL) + { + /* Set range to cover all resources */ + r0 = 0; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + /* Check parameters */ + BOUND_RSRC(resource, idx); + MASTER(idx); + ANCESTOR(rm_rsrc_data[idx].owner); + if ((err == SC_ERR_NONE) && (caller_pt != SC_PT) && (caller_pt + == rm_rsrc_data[idx].owner)) + { + err = SC_ERR_NOACCESS; + } + + /* Check permissions */ + NOT_LOCKED(rm_rsrc_data[idx].owner); + + /* Set range to cover only the specified resource */ + r0 = resource; + rN = resource; + } + + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = r0; r <= rN; r++) + { + if (resource == SC_R_ALL) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + MASTER_C(idx); + + /* Check ownership */ + ANCESTOR_C(rm_rsrc_data[idx].owner); + ASRT_C((caller_pt == SC_PT) || (caller_pt != rm_rsrc_data[idx].owner)); + + /* Check permissions */ + NOT_LOCKED_C(rm_rsrc_data[idx].owner); + } + + /* Change attributes */ + if (rm_part_data[caller_pt].secure != SC_FALSE) + { + rm_rsrc_data[idx].sa = sa; + } + rm_rsrc_data[idx].pa = pa; + + if (smmu_bypass != SC_FALSE) + { + rm_rsrc_data[idx].sid = SC_BYPASS_SID; + } + + update_rdc_resource(idx, SC_TRUE, SC_FALSE); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set streamID for a master resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_master_sid(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_sid_t sid) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_rsrc_t r0, rN; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + NOT_RESTRICTED(caller_pt); + ASRT_ERR((sid != 0U) && ((sid & ~SC_RM_SID_MASK) == 0U), SC_ERR_PARM); + + /* Is one or all resources? */ + if (resource == SC_R_ALL) + { + /* Set range to cover all resources */ + r0 = 0; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + /* Check parameters */ + BOUND_RSRC(resource, idx); + MASTER(idx); + ANCESTOR(rm_rsrc_data[idx].owner); + NOT_LOCKED(rm_rsrc_data[idx].owner); + + /* Set range to cover only the specified resource */ + r0 = resource; + rN = resource; + } + + if (err == SC_ERR_NONE) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = r0; r <= rN; r++) + { + if (resource == SC_R_ALL) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + MASTER_C(idx); + + /* Check ownership */ + ANCESTOR_C(rm_rsrc_data[idx].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_rsrc_data[idx].owner); + } + + /* Update resource */ + rm_rsrc_data[idx].sid = sid; + update_rdc_resource(idx, SC_TRUE, SC_FALSE); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update master */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_update_master(sc_rm_idx_t idx) +{ + SIMU_ASRT(idx < SC_NUM_RSRC, "bad rsrc idx") + + update_rdc_resource(idx, SC_TRUE, SC_FALSE); + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Set access permissions for a peripheral resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_peripheral_permissions(sc_rm_pt_t caller_pt, + sc_rsrc_t resource, sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + sc_rsrc_t r0, rN; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + ASRT_ERR((pt < SC_RM_NUM_PARTITION) || (pt == SC_RM_PT_ALL), SC_ERR_PARM); + ASRT_ERR((pt >= SC_RM_NUM_PARTITION) || (rm_part_data[pt].used != SC_FALSE), + SC_ERR_PARM); + ASRT_ERR(perm <= SC_RM_PERM_FULL, SC_ERR_PARM); + + /* Check permissions */ + ASRT_ERR((pt >= SC_RM_NUM_PARTITION) || (rm_part_data[pt].confidential + == SC_FALSE) || (pt == caller_pt), SC_ERR_LOCKED); + + /* Is one or all resources? */ + if (resource == SC_R_ALL) + { + /* Set range to cover all resources */ + r0 = 0; + rN = SC_NUM_RESOURCE - 1U; + } + else + { + /* Check parameters */ + BOUND_RSRC(resource, idx); + + /* Check permissions */ + ANCESTOR(rm_rsrc_data[idx].owner); + NOT_LOCKED(rm_rsrc_data[idx].owner); + + /* Update SYSTEM */ + if ((err == SC_ERR_NONE) && (resource == SC_R_SYSTEM)) + { + sc_bool_t access; + + /* Grant access if permission is not none */ + if (perm == SC_RM_PERM_NONE) + { + access = SC_FALSE; + } + else + { + access = SC_TRUE; + } + + /* Do one or all partitions? */ + if (pt == SC_RM_PT_ALL) + { + sc_rm_pt_t p; + + /* Loop through all partitions */ + for (p = 0; p < SC_RM_NUM_PARTITION; p++) + { + rm_part_data[p].sys_access = access; + } + } + else + { + rm_part_data[pt].sys_access = access; + } + } + else + { + /* Check parameters */ + PERIPHERAL(idx); + } + + /* Set range to cover only the specified resource */ + r0 = resource; + rN = resource; + } + + if ((err == SC_ERR_NONE) && (resource != SC_R_SYSTEM)) + { + sc_rsrc_t r; + + /* Process range of resources */ + for (r = r0; r <= rN; r++) + { + if (resource == SC_R_ALL) + { + /* Check parameters */ + BOUND_RSRC_C(r, idx); + PERIPHERAL_C(idx); + + /* Check ownership */ + ANCESTOR_C(rm_rsrc_data[idx].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_rsrc_data[idx].owner); + } + + /* Do one or all partitions? */ + if (pt == SC_RM_PT_ALL) + { + sc_rm_did_t d; + + /* Loop through all domains */ + for (d = 0; d < SC_RM_NUM_DOMAIN; d++) + { + (void) set_perms(rm_rsrc_data[idx].perms, d, perm); + } + } + else + { + (void) set_perms(rm_rsrc_data[idx].perms, rm_part_data[pt].did, + perm); + } + + (void) update_rdc_resource(idx, SC_FALSE, SC_TRUE); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Update peripheral */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_update_peripheral(sc_rm_idx_t idx) +{ + SIMU_ASRT(idx < SC_NUM_RSRC, "bad rsrc idx") + + update_rdc_resource(idx, SC_FALSE, SC_TRUE); + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Update resoruce */ +/*--------------------------------------------------------------------------*/ +void rm_update_resource(sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + update_rdc_resource(idx, SC_TRUE, SC_TRUE); + } +} + +/*--------------------------------------------------------------------------*/ +/* Get resource subsystem info */ +/*--------------------------------------------------------------------------*/ +void rm_get_ridx_ss_info(sc_rm_idx_t idx, sc_sub_t *ss, + sc_ss_idx_t *ss_idx) +{ + SIMU_ASRT(idx < SC_NUM_RSRC, "bad rsrc idx"); + + *ss = rm_rsrc_data[idx].ss; + *ss_idx = rm_rsrc_data[idx].ss_idx; + + SIMU_ASRT(*ss <= SC_SUBSYS_NA, "bad ss") +} + +/*--------------------------------------------------------------------------*/ +/* Check resource range and return the unified resource index */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_check_map_ridx(sc_rsrc_t resource, sc_rm_idx_t *idx) +{ + sc_bool_t rtn; + + /* Check parameters */ + if (resource >= SC_NUM_RESOURCE) + { + rtn = SC_FALSE; + } + else if (rm_rsrc_map_data[resource] == SC_NUM_RSRC) + { + rtn = SC_FALSE; + } + + /* Check if available */ + else if (soc_rsrc_avail(resource) == SC_FALSE) + { + rtn = SC_FALSE; + } + else + { + /* Return index */ + if (idx != NULL) + { + *idx = rm_rsrc_map_data[resource]; + + SIMU_ASRT(*idx < SC_NUM_RSRC, + "bad rsrc idx"); + + } + rtn = SC_TRUE; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check resource range and return the unified resource index */ +/*--------------------------------------------------------------------------*/ +void rm_check_map_ridx_v(sc_rsrc_t resource, sc_rm_idx_t *idx) +{ + /* Check parameters */ + if ((resource < SC_NUM_RESOURCE) && (rm_rsrc_map_data[resource] + != SC_NUM_RSRC)) + { + /* Return index */ + *idx = rm_rsrc_map_data[resource]; + + SIMU_ASRT(*idx < SC_NUM_RSRC, + "bad rsrc idx"); + } +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource owned */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_resource_owned(sc_rm_pt_t caller_pt, sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + rtn = rm_is_ridx_owned(caller_pt, idx); + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource index owned */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_ridx_owned(sc_rm_pt_t caller_pt, sc_rm_idx_t idx) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + + /* Check availability */ + if (rm_is_ridx_avail(idx) != SC_FALSE) + { + rtn = (rm_rsrc_data[idx].owner == caller_pt); + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource available */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_resource_avail(sc_rsrc_t resource) +{ + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0U; + + if (resource < SC_NUM_RESOURCE) + { + rtn = rm_check_map_ridx(resource, &idx); + } + + /* Check table */ + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Convert resource index to resource */ +/*--------------------------------------------------------------------------*/ +sc_rsrc_t rm_get_resource(sc_rm_idx_t idx) +{ + sc_sub_t ss = 0U; + ss_idx_t ss_idx = 0U; + + SIMU_ASRT(idx < SC_NUM_RSRC, "bad rsrc idx"); + + /* Convert RM index to SS info */ + rm_get_ridx_ss_info(idx, &ss, &ss_idx); + + /* Convert to resource */ + return ss_get_resource(ss, ss_idx); +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource index available */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_ridx_avail(sc_rm_idx_t idx) +{ + /* Check if available */ + return soc_rsrc_avail(rm_get_resource(idx)); +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource access allowed */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_resource_access_allowed(sc_rm_pt_t caller_pt, + sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + rtn = rm_is_ridx_access_allowed(caller_pt, idx); + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource index access allowed */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_ridx_access_allowed(sc_rm_pt_t caller_pt, sc_rm_idx_t idx) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + SIMU_ASRT(rm_rsrc_data[idx].owner < SC_RM_NUM_PARTITION, + "bad owner pt"); + + if (err == SC_ERR_NONE) + { + /* Check if available */ + if (rm_is_ridx_avail(idx) == SC_FALSE) + { + rtn = SC_FALSE; + } + /* Check parent grant */ + else if ((rm_part_data[rm_rsrc_data[idx].owner].grant != SC_FALSE) + && (rm_part_data[rm_rsrc_data[idx].owner].parent == caller_pt)) + { + rtn = SC_TRUE; + } + else + { + rtn = (rm_rsrc_data[idx].owner == caller_pt); + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Return the owner partition for a resource */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_get_resource_owner(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_pt_t *pt) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + rm_get_ridx_owner(idx, pt); + + SIMU_ASRT(*pt < SC_RM_NUM_PARTITION, "bad pt"); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Return the owner partition for a rsrc */ +/*--------------------------------------------------------------------------*/ +void rm_get_ridx_owner(sc_rm_idx_t idx, sc_rm_pt_t *pt) +{ + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + + if (idx < SC_NUM_RSRC) + { + *pt= rm_rsrc_data[idx].owner; + } + else + { + *pt = SC_PT; + } + + SIMU_ASRT(*pt < SC_RM_NUM_PARTITION, "bad pt"); +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource is a master */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_resource_master(sc_rm_pt_t caller_pt, sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + if (rm_is_ridx_owned(caller_pt, idx) != SC_FALSE) + { + rtn = rm_is_ridx_master(idx); + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource is a master */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_ridx_master(sc_rm_idx_t idx) +{ + sc_bool_t rtn; + + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + + /* Check if board */ + if (rm_rsrc_data[idx].ss > SC_SUBSYS_LAST) + { + rtn = SC_FALSE; + } + + /* Check if available */ + else if (rm_is_ridx_avail(idx) == SC_FALSE) + { + rtn = SC_FALSE; + } + else + { + SIMU_ASRT(rm_rsrc_data[idx].ss < SC_NUM_SUBSYS, + "bad ss"); + + rtn = ss_base_info[rm_rsrc_data[idx].ss] + ->rsrc[rm_rsrc_data[idx].ss_idx].master; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource is a peripheral */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_resource_peripheral(sc_rm_pt_t caller_pt, sc_rsrc_t resource) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + sc_rm_idx_t idx = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + BOUND_RSRC(resource, idx); + + if (err == SC_ERR_NONE) + { + if (rm_is_ridx_owned(caller_pt, idx) != SC_FALSE) + { + rtn = rm_is_ridx_peripheral(idx); + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Check if resource is a peripheral */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_ridx_peripheral(sc_rm_idx_t idx) +{ + sc_bool_t rtn; + + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + + /* Check if board */ + if (rm_rsrc_data[idx].ss > SC_SUBSYS_LAST) + { + rtn = SC_FALSE; + } + + /* Check if available */ + else if (rm_is_ridx_avail(idx) == SC_FALSE) + { + rtn = SC_FALSE; + } + else + { + SIMU_ASRT(rm_rsrc_data[idx].ss < SC_NUM_SUBSYS, + "bad ss"); + + rtn = ss_base_info[rm_rsrc_data[idx].ss]-> + rsrc[rm_rsrc_data[idx].ss_idx].peripheral; + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Return resource info */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_get_resource_info(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_sid_t *sid) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx = 0; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_RSRC(resource, idx); + + /* Check parameters */ + ACCESS_ALLOWED(caller_pt, idx); + + if (err == SC_ERR_NONE) + { + /* Return info */ + if (sid != NULL) + { + *sid = rm_rsrc_data[idx].sid; + + /* Check SID */ + SIMU_ASRT((*sid & ~SC_RM_SID_MASK) == 0U, "bad sid"); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set resource block state */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_ridx_block(sc_rm_idx_t idx, sc_bool_t block) +{ + /* Check parms */ + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + + sc_bool_t rtn = rm_rsrc_data[idx].block; + + rm_rsrc_data[idx].block = block; + + /* Update resource */ + update_rdc_resource(idx, SC_FALSE, SC_TRUE); + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Allocate a memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_memreg_alloc(sc_rm_pt_t caller_pt, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_mr_t m, m_found; + sc_bool_t found = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Check parameters */ + if ((addr_start & MRC_ALIGN) != 0ULL) + { + err = SC_ERR_PARM; + } + else if ((addr_end & MRC_ALIGN) != MRC_ALIGN) + { + err = SC_ERR_PARM; + } + else + { + ; /* Intentional empty else */ + } + } + + /* Check permissions */ + NOT_LOCKED(caller_pt); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Check if spanning across multiple existing regions */ + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if ((rm_mreg_data[m].used != SC_FALSE) + && ((addr_start >= rm_mreg_data[m].start) + && (addr_start <= rm_mreg_data[m].end)) + && !((addr_end >= rm_mreg_data[m].start) + && (addr_end <= rm_mreg_data[m].end))) + { + err = SC_ERR_PARM; + } + else if ((rm_mreg_data[m].used != SC_FALSE) + && !((addr_start >= rm_mreg_data[m].start) + && (addr_start <= rm_mreg_data[m].end)) + && ((addr_end >= rm_mreg_data[m].start) + && (addr_end <= rm_mreg_data[m].end))) + { + err = SC_ERR_PARM; + } + else + { + ; /* Intentional empty else */ + } + } + } + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Find parent memory space */ + found = SC_FALSE; + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if ((rm_mreg_data[m].used != SC_FALSE) + && (rm_mreg_data[m].owner == caller_pt) + && (addr_start >= rm_mreg_data[m].start) + && (addr_start <= rm_mreg_data[m].end)) + { + found = SC_TRUE; + m_found = m; + break; + } + } + } + + /* Check if found */ + ASRT_ERR((caller_pt == SC_PT) || (found != SC_FALSE), SC_ERR_NOACCESS); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Find unallocated memory region */ + err = SC_ERR_UNAVAILABLE; + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if (rm_mreg_data[m].used == SC_FALSE) + { + rm_mreg_data[m].used = SC_TRUE; + rm_mreg_data[m].owner = caller_pt; + rm_mreg_data[m].start = addr_start; + rm_mreg_data[m].end = addr_end; + rm_mreg_data[m].det = 0; + rm_mreg_data[m].rmsg = 0; + + /* Found? */ + if (found != SC_FALSE) + { + rm_mreg_data[m].parent = m_found; + copy_perms(m_found, m); + } + else + { + rm_mreg_data[m].parent = m; + + /* Update perms */ + clear_perms(rm_mreg_data[m].perms); + if (rm_part_data[caller_pt].secure != SC_FALSE) + { + /* Secure access by default */ + set_perms(rm_mreg_data[m].perms, + rm_part_data[caller_pt].did, SC_RM_PERM_SEC_RW); + } + else + { + /* Full access by default */ + set_perms(rm_mreg_data[m].perms, + rm_part_data[caller_pt].did, SC_RM_PERM_FULL); + } + } + + /* Update mem region */ + err = update_rdc_memreg(m, rm_mreg_data[m].start, + rm_mreg_data[m].end, rm_mreg_data[m].start, + rm_mreg_data[m].end); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + if (mr != NULL) + { + /* Return memory region index */ + *mr = m; + + /* Update in-order memory list */ + rm_mreg_list[rm_mreg_list_count] = m; + rm_mreg_list_count++; + + /* Check mr */ + SIMU_ASRT(*mr < SC_RM_NUM_MEMREG, + "bad mr"); + } + } + else + { + rm_mreg_data[m].used = SC_FALSE; + } + + break; + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Split a memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_memreg_split(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_err_t err = SC_ERR_NONE; + sc_faddr_t start = 0ULL; + uint32_t num_co = 0U; + sc_rm_mr_t m; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_MR(mr); + + /* Check parameters */ + USED_MR(mr); + + /* Check access rights */ + if ((err == SC_ERR_NONE) && (caller_pt != SC_PT)) + { + NOT_LOCKED(rm_mreg_data[mr].owner); + ANCESTOR(rm_mreg_data[mr].owner); + } + + /* Cannot split coincident region */ + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if ((rm_mreg_data[m].used) + && (rm_mreg_data[m].start == rm_mreg_data[mr].start) + && (rm_mreg_data[m].end == rm_mreg_data[mr].end)) + { + num_co++; + } + } + ASRT_ERR((caller_pt == SC_PT) || (num_co <= 1U), SC_ERR_BUSY); + + /* Check address */ + if (err == SC_ERR_NONE) + { + sc_faddr_t end; + + start = rm_mreg_data[mr].start; + end = rm_mreg_data[mr].end; + if ((addr_start == start) && (addr_end == end)) + { + err = SC_ERR_PARM; + } + else if ((addr_start < start) || (addr_end > end)) + { + err = SC_ERR_PARM; + } + else if ((addr_start != start) && (addr_end != end)) + { + err = SC_ERR_PARM; + } + else + { + ; /* Intentional empty else */ + } + } + + if (err == SC_ERR_NONE) + { + /* Allocate new region (also checks many parameters) */ + if (caller_pt != SC_PT) + { + /* Allocate as caller */ + err = rm_memreg_alloc(caller_pt, mr_ret, addr_start, + addr_end); + } + else + { + /* Allocate as current region owner */ + err = rm_memreg_alloc(rm_mreg_data[mr].owner, mr_ret, + addr_start, addr_end); + } + } + + if (err == SC_ERR_NONE) + { + sc_faddr_t new_start, new_end; + + if (rm_mreg_data[mr].parent == mr) + { + rm_mreg_data[*mr_ret].parent = *mr_ret; + } + else + { + rm_mreg_data[*mr_ret].parent = rm_mreg_data[mr].parent; + } + + /* Copy new */ + new_start = rm_mreg_data[mr].start; + new_end = rm_mreg_data[mr].end; + + /* Split */ + if (addr_start == start) + { + new_start = addr_end + 1ULL; + } + else + { + new_end = addr_start - 1ULL; + } + + /* Update HW */ + err = update_rdc_memreg(mr, rm_mreg_data[mr].start, + rm_mreg_data[mr].end, new_start, new_end); + + /* Update data */ + rm_mreg_data[mr].start = new_start; + rm_mreg_data[mr].end = new_end; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Fragment memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_memreg_frag(sc_rm_pt_t caller_pt, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_mr_t mr; + sc_faddr_t mr_start, mr_end; + + /* Find memory region */ + FUNC_ERR(rm_find_memreg(caller_pt, &mr, addr_start, + addr_end)); + + FUNC_ERR(rm_get_memreg_info(caller_pt, mr, &mr_start, &mr_end)); + + if (err == SC_ERR_NONE) + { + /* Coincident? */ + if ((addr_start == mr_start) && (addr_end == mr_end)) + { + *mr_ret = mr; + } + else + { + /* Front */ + if (addr_start == mr_start) + { + sc_rm_mr_t temp_mr; + + FUNC_ERR(rm_memreg_split(caller_pt, mr, &temp_mr, + addr_end + 1ULL, mr_end)); + + if (err == SC_ERR_NONE) + { + *mr_ret = mr; + } + } + /* End */ + else if (addr_end == mr_end) + { + FUNC_ERR(rm_memreg_split(caller_pt, mr, mr_ret, addr_start, + addr_end)); + } + /* Middle */ + else + { + sc_rm_mr_t temp_mr; + + FUNC_ERR(rm_memreg_split(caller_pt, mr, &temp_mr, + addr_end + 1ULL, mr_end)); + + FUNC_ERR(rm_memreg_split(caller_pt, mr, mr_ret, addr_start, + addr_end)); + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Free a memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_memreg_free(sc_rm_pt_t caller_pt, sc_rm_mr_t mr) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_mr_t m0, mN; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Is one or all regions? */ + if (mr == SC_RM_MR_ALL) + { + /* Set range to cover all regions */ + m0 = 0; + mN = SC_RM_NUM_MEMREG - 1U; + } + else + { + /* Check parameters */ + BOUND_MR(mr); + USED_MR(mr); + if ((err == SC_ERR_NONE) && (caller_pt != SC_PT)) + { + NOT_LOCKED(rm_mreg_data[mr].owner); + ANCESTOR(rm_mreg_data[mr].owner); + } + + /* Set range to cover only the specified region */ + m0 = mr; + mN = mr; + } + + if (err == SC_ERR_NONE) + { + sc_rm_mr_t m; + sc_rm_mr_t mi; + + /* Process range of regions */ + for (m = m0; m <= mN; m++) + { + if (mr != SC_RM_MR_ALL) + { + /* Check parameters */ + USED_MR_C(m); + + if (caller_pt != SC_PT) + { + /* Check ownership */ + ANCESTOR_C(rm_mreg_data[m].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_mreg_data[m].owner); + } + } + + /* Free region */ + rm_mreg_data[m].used = SC_FALSE; + + /* Update RDC */ + (void) update_rdc_memreg(m, rm_mreg_data[m].start, + rm_mreg_data[m].end, rm_mreg_data[m].start, + rm_mreg_data[m].end); + + /* Find entry in memory list */ + for (mi = 0U; mi < rm_mreg_list_count; mi++) + { + if (rm_mreg_list[mi] == m) + { + break; + } + } + + /* Roll entries down in the list */ + while ((mi + 1U) < rm_mreg_list_count) + { + rm_mreg_list[mi] = rm_mreg_list[mi + 1U]; + + mi++; + } + + /* Update the memory list count */ + rm_mreg_list_count--; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Find a memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_find_memreg(sc_rm_pt_t caller_pt, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Loop over regions */ + if (err == SC_ERR_NONE) + { + sc_rm_mr_t m; + + err = SC_ERR_NOTFOUND; + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if (caller_pt != SC_PT) + { + /* Owned? */ + ASRT_C(rm_is_memreg_owned(caller_pt, m) != SC_FALSE); + } + + /* Region containing? */ + if ((addr_start >= rm_mreg_data[m].start) + && (addr_end <= rm_mreg_data[m].end)) + { + *mr = m; + err = SC_ERR_NONE; + + SIMU_ASRT(*mr < SC_RM_NUM_MEMREG, + "bad mr"); + + break; + } + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Assign a memory region to another partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_assign_memreg(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, sc_rm_mr_t mr) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_mr_t m0, mN; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + USED_PT(pt); + NOT_LOCKED(pt); + + /* Is one or all regions? */ + if (mr == SC_RM_MR_ALL) + { + /* Set range to cover all regions */ + m0 = 0; + mN = SC_RM_NUM_MEMREG - 1U; + } + else + { + /* Check parameters */ + BOUND_MR(mr); + USED_MR(mr); + if ((err == SC_ERR_NONE) && (caller_pt != SC_PT)) + { + NOT_LOCKED(rm_mreg_data[mr].owner); + ANCESTOR(rm_mreg_data[mr].owner); + } + + /* Set range to cover only the specified region */ + m0 = mr; + mN = mr; + } + + if (err == SC_ERR_NONE) + { + sc_rm_mr_t m; + + /* Process range of regions */ + for (m = m0; m <= mN; m++) + { + if (mr != SC_RM_MR_ALL) + { + /* Check parameters */ + USED_MR_C(m); + + /* Check ownership */ + ANCESTOR_C(rm_mreg_data[m].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_mreg_data[m].owner); + } + + /* Assign region */ + rm_mreg_data[m].owner = pt; + clear_perms(rm_mreg_data[m].perms); + + if (rm_part_data[pt].secure != SC_FALSE) + { + set_perms(rm_mreg_data[m].perms, rm_part_data[pt].did, + SC_RM_PERM_SEC_RW); + } + else + { + set_perms(rm_mreg_data[m].perms, rm_part_data[pt].did, + SC_RM_PERM_FULL); + } + + /* Update RDC */ + (void) update_rdc_memreg(m, rm_mreg_data[m].start, + rm_mreg_data[m].end, rm_mreg_data[m].start, + rm_mreg_data[m].end); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set access permissions for a memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_memreg_permissions(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_mr_t m0, mN; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + ASRT_ERR((pt < SC_RM_NUM_PARTITION) || (pt == SC_RM_PT_ALL), SC_ERR_PARM); + ASRT_ERR((pt >= SC_RM_NUM_PARTITION) || (rm_part_data[pt].used != SC_FALSE), + SC_ERR_PARM); + + /* Check permissions */ + if ((err == SC_ERR_NONE) && (pt != SC_RM_PT_ALL)) + { + if ((rm_part_data[pt].confidential != SC_FALSE) + && (pt != caller_pt)) + { + err = SC_ERR_LOCKED; + } + } + + /* Is one or all regions? */ + if (mr == SC_RM_MR_ALL) + { + /* Set range to cover all regions */ + m0 = 0; + mN = SC_RM_NUM_MEMREG - 1U; + } + else + { + /* Check parameters */ + BOUND_MR(mr); + USED_MR(mr); + NOT_LOCKED(rm_mreg_data[mr].owner); + ANCESTOR(rm_mreg_data[mr].owner); + + /* Set range to cover only the specified region */ + m0 = mr; + mN = mr; + } + + if (err == SC_ERR_NONE) + { + sc_rm_mr_t m; + + /* Process range of regions */ + for (m = m0; m <= mN; m++) + { + if (mr != SC_RM_MR_ALL) + { + /* Check parameters */ + USED_MR_C(m); + + /* Check ownership */ + ANCESTOR_C(rm_mreg_data[m].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_mreg_data[m].owner); + } + + /* Do one or all partitions? */ + if (pt == SC_RM_PT_ALL) + { + sc_rm_pt_t p; + + /* Loop through all partitions */ + for (p = 0; p < SC_RM_NUM_PARTITION; p++) + { + /* Check access? */ + if ((rm_part_data[p].confidential == SC_FALSE) + || (p == caller_pt)) + { + /* Set permissions */ + set_perms(rm_mreg_data[m].perms, rm_part_data[p].did, + perm); + } + } + } + else + { + set_perms(rm_mreg_data[m].perms, rm_part_data[pt].did, + perm); + } + + /* Update RDC */ + (void) update_rdc_memreg(m, rm_mreg_data[m].start, + rm_mreg_data[m].end, rm_mreg_data[m].start, + rm_mreg_data[m].end); + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set IEE parameters for memory region */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_memreg_iee(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_rm_det_t det, sc_rm_rmsg_t rmsg) +{ + sc_err_t err = SC_ERR_NONE; + sc_rsrc_t resource = U16(SC_R_IEE_R0) + U16(rmsg); + sc_rm_idx_t idx; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_MR(mr); + + /* Check parameters */ + ASRT_ERR(det <= 1U, SC_ERR_PARM); + ASRT_ERR(rmsg <= 7U, SC_ERR_PARM); + BOUND_RSRC(resource, idx); + USED_MR(mr); + + /* Check access rights */ + NOT_LOCKED(rm_mreg_data[mr].owner); + ANCESTOR(rm_mreg_data[mr].owner); + + /* Check for error */ + if (err == SC_ERR_NONE) + { + /* Update data */ + rm_mreg_data[mr].det = det; + rm_mreg_data[mr].rmsg = rmsg; + + /* Update resource */ + (void) update_rdc_memreg(mr, rm_mreg_data[mr].start, + rm_mreg_data[mr].end, rm_mreg_data[mr].start, + rm_mreg_data[mr].end); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check if mememory region owned */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_memreg_owned(sc_rm_pt_t caller_pt, sc_rm_mr_t mr) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_MR(mr); + + if (err == SC_ERR_NONE) + { + /* Check parameters */ + if (rm_mreg_data[mr].used == SC_FALSE) + { + rtn = SC_FALSE; + } + else if (rm_mreg_data[mr].owner == caller_pt) + { + rtn = SC_TRUE; + } + else + { + ; /* Intentional empty else */ + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Return memory region info */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_get_memreg_info(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_MR(mr); + + /* Check parameters */ + USED_MR(mr); + + if (err == SC_ERR_NONE) + { + /* Return info */ + *addr_start = rm_mreg_data[mr].start; + *addr_end = rm_mreg_data[mr].end; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Assign a pad to a resource partition */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_assign_pad(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, sc_pad_t pad) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + /* Check parameters */ + USED_PT(pt); + NOT_LOCKED(pt); + NOT_RESTRICTED(caller_pt); + + /* Is one or all pads? */ + if (pad == SC_P_ALL) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + /* Check parameters */ + BOUND_PAD(pad); + NOT_LOCKED(rm_pad_data[pad].owner); + ANCESTOR(rm_pad_data[pad].owner); + + /* Set range to cover only the specified region */ + p0 = pad; + pN = pad; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + if (pad == SC_P_ALL) + { + /* Check ownership */ + ANCESTOR_C(rm_pad_data[p].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_pad_data[p].owner); + } + + /* Assign pad */ + rm_pad_data[p].owner = pt; + rm_pad_data[p].movable = SC_TRUE; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Flag pad as movable or not */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_set_pad_movable(sc_rm_pt_t caller_pt, sc_pad_t pad_first, + sc_pad_t pad_last, sc_bool_t movable) +{ + sc_err_t err = SC_ERR_NONE; + sc_pad_t p0, pN; + sc_pad_t new_pad_first = pad_first; + sc_pad_t new_pad_last = pad_last; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check permissions */ + NOT_RESTRICTED(caller_pt); + + /* Is one or all pads? */ + if ((new_pad_first == SC_P_ALL) || (new_pad_last == SC_P_ALL)) + { + /* Set range to cover all pads */ + p0 = 0U; + pN = SC_NUM_PAD - 1U; + } + else + { + if (new_pad_first > new_pad_last) + { + sc_pad_t temp = new_pad_first; + new_pad_first = new_pad_last; + new_pad_last = temp; + } + + /* Check parameters */ + BOUND_PAD(new_pad_last); + ASRT_ERR(new_pad_first <= new_pad_last, SC_ERR_PARM); + + /* Set range to cover only the specified region */ + p0 = new_pad_first; + pN = new_pad_last; + } + + if (err == SC_ERR_NONE) + { + sc_pad_t p; + + /* Process range of pads */ + for (p = p0; p <= pN; p++) + { + /* Check ownership */ + ANCESTOR_C(rm_pad_data[p].owner); + + /* Check permissions */ + NOT_LOCKED_C(rm_pad_data[p].owner); + + /* Set flag */ + rm_pad_data[p].movable = movable; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Check if pad owned */ +/*--------------------------------------------------------------------------*/ +sc_bool_t rm_is_pad_owned(sc_rm_pt_t caller_pt, sc_pad_t pad) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t rtn = SC_FALSE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Check parameters */ + if (pad >= SC_NUM_PAD) + { + rtn = SC_FALSE; + } + else if (rm_pad_data[pad].owner == caller_pt) + { + rtn = SC_TRUE; + } + else + { + ; /* Intentional empty else */ + } + } + + return rtn; +} + +/*--------------------------------------------------------------------------*/ +/* Return the owner partition for a pad */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_get_pad_owner(sc_pad_t pad, sc_rm_pt_t *pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check parameters */ + BOUND_PAD(pad); + + if (err == SC_ERR_NONE) + { + *pt = rm_pad_data[pad].owner; + + SIMU_ASRT(*pt < SC_RM_NUM_PARTITION, + "bad pt"); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Create a new resource partition and assign resources */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_partition_create(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt, + sc_bool_t secure, sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent, sc_rsrc_t resource, + const sc_rsrc_t *rsrc_lst, uint32_t rsrc_cnt, + const sc_pad_t *pad_lst, uint32_t pad_cnt, + const sc_rm_mem_list_t *mem_lst, uint32_t mem_cnt) +{ + sc_err_t err = SC_ERR_NONE; + uint32_t idx; + + /* Allocate partition */ + FUNC_ERR(rm_partition_alloc(caller_pt, pt, secure, isolated, + restricted, grant, coherent)); + + /* Mark all resources and pads as not movable */ + FUNC_ERR(rm_set_resource_movable(caller_pt, SC_R_ALL, SC_R_ALL, + SC_FALSE)); + FUNC_ERR(rm_set_pad_movable(caller_pt, SC_P_ALL, SC_P_ALL, + SC_FALSE)); + + /* Mark all subsystem resources as movable */ + if (resource < SC_NUM_RESOURCE) + { + FUNC_ERR(rm_set_subsys_rsrc_movable(caller_pt, resource, + SC_TRUE)); + } + + /* Mark all resources in list as movable */ + idx = 0U; + while (idx < rsrc_cnt) + { + sc_rsrc_t first = rsrc_lst[idx]; + sc_rsrc_t last; + + /* Check for range */ + if ((first & RM_RANGE_MASK) != 0U) + { + first &= ~RM_RANGE_MASK; + idx++; + } + last = rsrc_lst[idx]; + + FUNC_ERR(rm_set_resource_movable(caller_pt, first, last, + SC_TRUE)); + + idx++; + } + + /* Mark all pads in list as movable */ + idx = 0U; + while (idx < pad_cnt) + { + sc_pad_t first = pad_lst[idx]; + sc_pad_t last; + + /* Check for range */ + if ((first & RM_RANGE_MASK) != 0U) + { + first &= ~RM_RANGE_MASK; + idx++; + } + last = pad_lst[idx]; + + FUNC_ERR(rm_set_pad_movable(caller_pt, first, last, + SC_TRUE)); + + idx++; + } + + /* Move everything flagged as movable */ + FUNC_ERR(rm_move_all(caller_pt, caller_pt, *pt, SC_TRUE, SC_TRUE)); + + /* Create and assign all memory in list */ + for (idx = 0U; idx < mem_cnt; idx++) + { + sc_rm_mr_t mr; + + /* Fragment memory */ + FUNC_ERR(rm_memreg_frag(caller_pt, &mr, + mem_lst[idx].addr_start, mem_lst[idx].addr_end)); + + /* Assign to new partition */ + FUNC_ERR(rm_assign_memreg(caller_pt, *pt, mr)); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Enable blocking */ +/*--------------------------------------------------------------------------*/ +void rm_enable_blocking(void) +{ + blocking = SC_TRUE; + + (void) rm_init_subsys(SC_SUBSYS_SC, SC_TRUE); +} + +/*--------------------------------------------------------------------------*/ +/* Reload subsystem after a power on */ +/*--------------------------------------------------------------------------*/ +sc_err_t rm_init_subsys(sc_sub_t ss, sc_bool_t block_enb) +{ + #ifdef XRDC_SUPPORT + sc_rm_idx_t r; + + SIMU_ASRT(ss < SC_NUM_SUBSYS, + "bad ss"); + + /* Enable RDC master (if powered) */ + ss_rdc_enable(ss, SC_TRUE); + + /* Load resource info */ + for (r = rm_ss_map_data[ss]; r < SC_NUM_RSRC; r++) + { + if ((block_enb != SC_FALSE) && (rm_rsrc_data[r].owner + == SC_SUBSYS_SC)) + { + continue; + } + + if (rm_rsrc_data[r].ss == ss) + { + (void) update_rdc_resource(r, SC_TRUE, SC_TRUE); + } + else + { + break; + } + } + + /* Load memory region info */ + if (block_enb == SC_FALSE) + { + rm_load_memrg(); + } + + /* Enable RDC and load XRDC defaults (if powered) */ + ss_rdc_enable(ss, SC_FALSE); + + /* Load child subsystems */ + for (sc_sub_t css = 0U; css < SC_NUM_SUBSYS; css++) + { + if ((sc_ss_info[css].parent == ss) + && (ss_is_powered(css) == SC_TRUE)) + { + (void) rm_init_subsys(css, block_enb); + } + } + #endif /* XRDC_SUPPORT */ + + return SC_ERR_NONE; +} + +/*--------------------------------------------------------------------------*/ +/* Reload memory region info */ +/*--------------------------------------------------------------------------*/ +void rm_load_memrg(void) +{ + sc_rm_mr_t m; + + /* Loop over all memory regions in list */ + for (m = 0U; m < rm_mreg_list_count; m++) + { + /* Get region from ordered list */ + sc_rm_mr_t mr = rm_mreg_list[m]; + + /* Update region */ + (void) update_rdc_memreg(mr, rm_mreg_data[mr].start, + rm_mreg_data[mr].end, rm_mreg_data[mr].start, + rm_mreg_data[mr].end); + } +} + +/*--------------------------------------------------------------------------*/ +/* Dump RM state for debug */ +/*--------------------------------------------------------------------------*/ +void rm_dump(sc_rm_pt_t caller_pt) +{ + #ifdef DEBUG + sc_rm_pt_t p; + + debug_print(0, "\n*** Partitions **********************************\n"); + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + rm_dump_partition(p); + } + + debug_print(0, "\n*** Resources ***********************************\n"); + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + rm_dump_resources(p); + } + + debug_print(0, "\n*** Memory Regions ******************************\n"); + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + rm_dump_memregs(p); + } + + debug_print(0, "\n*** Pads ****************************************\n"); + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + rm_dump_pads(p); + } + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Dump RM resource state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) + void rm_dump_partition(sc_rm_pt_t pt) + { + SIMU_ASRT(pt < SC_RM_NUM_PARTITION, + "bad pt"); + + /* Check if partition enabled */ + if (rm_is_partition_used(pt) != SC_FALSE) + { + /* Dump data */ + #if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + always_print(" Partition: %u", pt); + if (rm_part_names[pt] != NULL) + { + always_print(" (%s)", rm_part_names[pt]); + } + always_print("\n"); + #else + always_print(" Partition: %u\n", pt); + #endif + #if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + always_print(" Parent: %u", + rm_part_data[pt].parent); + if (rm_part_names[rm_part_data[pt].parent] != NULL) + { + always_print(" (%s)", + rm_part_names[rm_part_data[pt].parent]); + } + always_print("\n"); + #else + always_print(" Parent: %u\n", + rm_part_data[pt].parent); + #endif + always_print(" DID: %u\n", rm_part_data[pt].did); + always_print(" Flags:\n"); + if (rm_part_data[pt].used != SC_FALSE) + { + always_print(" Used\n"); + } + if (rm_part_data[pt].secure != SC_FALSE) + { + always_print(" Secure\n"); + } + if (rm_part_data[pt].restricted != SC_FALSE) + { + always_print(" Restricted\n"); + } + if (rm_part_data[pt].isolated != SC_FALSE) + { + always_print(" Isolated\n"); + } + if (rm_part_data[pt].confidential != SC_FALSE) + { + always_print(" Confidential\n"); + } + if (rm_part_data[pt].locked != SC_FALSE) + { + always_print(" Locked\n"); + } + if (rm_part_data[pt].grant != SC_FALSE) + { + always_print(" Grant\n"); + } + if (rm_is_sys_access(pt)) + { + always_print(" System Access\n"); + } + } + } +#endif + +/*--------------------------------------------------------------------------*/ +/* Dump RM resource state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) + void rm_dump_resources(sc_rm_pt_t pt) + { + /* Check if partition enabled */ + if (rm_is_partition_used(pt) != SC_FALSE) + { + sc_rm_idx_t r; + + /* Dump data */ + #if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + always_print(" Partition: %u", pt); + if (rm_part_names[pt] != NULL) + { + always_print(" (%s)", rm_part_names[pt]); + } + always_print("\n"); + #else + always_print(" Partition: %u\n", pt); + #endif + for (r = 0; r < SC_NUM_RSRC; r++) + { + if ((rm_rsrc_data[r].owner == pt) + && (rm_is_ridx_avail(r) != SC_FALSE)) + { + always_print(" %s\n", rnames[r]); + + if ((rm_is_ridx_master(r) != SC_FALSE) + && (rm_rsrc_data[r].sid != SC_BYPASS_SID)) + { + always_print(" SID: 0x%X\n", + rm_rsrc_data[r].sid); + } + } + } + } + } +#endif + +/*--------------------------------------------------------------------------*/ +/* Dump RM memreg state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) + void rm_dump_memregs(sc_rm_pt_t pt) + { + /* Check if partition enabled */ + if (rm_is_partition_used(pt) != SC_FALSE) + { + sc_rm_mr_t m; + + /* Dump data */ + #if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + always_print(" Partition: %u", pt); + if (rm_part_names[pt] != NULL) + { + always_print(" (%s)", rm_part_names[pt]); + } + always_print("\n"); + #else + always_print(" Partition: %u\n", pt); + #endif + for (m = 0; m < SC_RM_NUM_MEMREG; m++) + { + if ((rm_mreg_data[m].used != SC_FALSE) + && (rm_mreg_data[m].owner == pt)) + { + sc_faddr_t start, end; + sc_rm_pt_t p; + + start = rm_mreg_data[m].start; + end = rm_mreg_data[m].end; + always_print(" %03d: 0x%01X", m, + UINT64_H(start)); + always_print("%08X", + UINT64_L(start)); + always_print(" - 0x%01X", + UINT64_H(end)); + always_print("%08X\n", + UINT64_L(end)); + always_print(" "); + always_print("Perms: "); + for (p = 0; p < SC_RM_NUM_PARTITION; p++) + { + sc_rm_did_t d = rm_part_data[p].did; + sc_rm_perm_t perm; + + if (rm_part_data[p].used == SC_FALSE) + { + always_print("x"); + } + else + { + get_perms(rm_mreg_data[m].perms, d, &perm); + always_print("%d", perm); + } + } + always_print("\n"); + if (rm_mreg_data[m].parent != m) + { + always_print(" "); + always_print("Parent: %u\n", rm_mreg_data[m].parent); + } + if (rm_mreg_data[m].rmsg != 0U) + { + always_print(" "); + always_print("RMSG: %u\n", rm_mreg_data[m].rmsg); + } + if (rm_mreg_data[m].det != 0U) + { + always_print(" "); + always_print("DET: %u\n", rm_mreg_data[m].det); + } + } + } + } + } +#endif + +/*--------------------------------------------------------------------------*/ +/* Dump RM pad state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) + void rm_dump_pads(sc_rm_pt_t pt) + { + /* Check if partition enabled */ + if (rm_is_partition_used(pt) != SC_FALSE) + { + sc_pad_t n; + + /* Dump data */ + #if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + always_print(" Partition: %u", pt); + if (rm_part_names[pt] != NULL) + { + always_print(" (%s)", rm_part_names[pt]); + } + always_print("\n"); + #else + always_print(" Partition: %u\n", pt); + #endif + for (n = 0; n < SC_NUM_PAD; n++) + { + if (rm_pad_data[n].owner == pt) + { + always_print(" %s\n", pnames[n]); + } + } + } + } +#endif + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Clear all resource permissions */ +/*--------------------------------------------------------------------------*/ +static void clear_perms(permz_t *perms) +{ + sc_rm_did_t d; + + for (d = 0; d < (SC_RM_NUM_DOMAIN / 2U); d++) + { + perms[d] = 0; + } +} + +/*--------------------------------------------------------------------------*/ +/* Copy memory region permissions */ +/*--------------------------------------------------------------------------*/ +static void copy_perms(sc_rm_mr_t mr_src, sc_rm_mr_t mr_dst) +{ + sc_rm_did_t d; + + SIMU_ASRT(mr_src < SC_RM_NUM_MEMREG, + "bad mr"); + SIMU_ASRT(mr_dst < SC_RM_NUM_MEMREG, + "bad mr"); + + for (d = 0; d < (SC_RM_NUM_DOMAIN / 2U); d++) + { + rm_mreg_data[mr_dst].perms[d] = rm_mreg_data[mr_src].perms[d]; + } +} + +/*--------------------------------------------------------------------------*/ +/* Set resource permission for a domain */ +/*--------------------------------------------------------------------------*/ +static void set_perms(permz_t *perms, sc_rm_did_t did, + sc_rm_perm_t perm) +{ + uint8_t byte = did / 2U; + uint8_t bit = (did % 2U) * 4U; + permz_t data; + + /* Check parms */ + SIMU_ASRT(did < SC_RM_NUM_DOMAIN, + "bad did"); + + /* Encode perm */ + data = perms[byte]; + data &= ~(0x7U << bit); + data |= perm << bit; + perms[byte] = data; +} + +/*--------------------------------------------------------------------------*/ +/* Get permissions for a domain */ +/*--------------------------------------------------------------------------*/ +static void get_perms(const permz_t *perms, sc_rm_did_t did, + sc_rm_perm_t *perm) +{ + uint8_t byte = did / 2U; + uint8_t bit = (did % 2U) * 4U; + + /* Check parms */ + SIMU_ASRT(did < SC_RM_NUM_DOMAIN, + "bad did"); + + /* Extract perm */ + *perm = (perms[byte] >> bit) & 0x7U; +} + +/*--------------------------------------------------------------------------*/ +/* Update RDC resource */ +/*--------------------------------------------------------------------------*/ +static void update_rdc_resource(sc_rm_idx_t idx, sc_bool_t master, + sc_bool_t peripheral) +{ + #ifdef XRDC_SUPPORT + sc_bool_t is_master = SC_FALSE; + sc_bool_t is_peripheral = SC_FALSE; + + SIMU_ASRT(idx < SC_NUM_RSRC, + "bad rsrc idx"); + SIMU_ASRT(rm_rsrc_data[idx].owner < SC_RM_NUM_PARTITION, + "bad owner pt"); + + if (rm_rsrc_data[idx].ss <= SC_SUBSYS_LAST) + { + is_master = ss_base_info[rm_rsrc_data[idx].ss] + ->rsrc[rm_rsrc_data[idx].ss_idx].master; + is_peripheral = ss_base_info[rm_rsrc_data[idx].ss] + ->rsrc[rm_rsrc_data[idx].ss_idx].peripheral; + } + + /* Update Master */ + if ((is_master != SC_FALSE) && (master != SC_FALSE)) + { + sc_rm_spa_t sa = rm_rsrc_data[idx].sa; + sc_rm_spa_t pa = rm_rsrc_data[idx].pa; + sc_rm_did_t did = rm_part_data[rm_rsrc_data[idx].owner].did; + sc_rm_sid_t sid = rm_rsrc_data[idx].sid; + + ss_rdc_set_master(idx, SC_TRUE, SC_FALSE, sa, pa, did, sid, 0xFF); + } + + /* Update Peripheral */ + if ((is_peripheral != SC_FALSE) && (peripheral != SC_FALSE)) + { + sc_rm_did_t d; + sc_rm_perm_t perms[SC_RM_NUM_DOMAIN]; + + /* Extract compressed access perms */ + for (d = 0; d < SC_RM_NUM_DOMAIN; d++) + { + get_perms(rm_rsrc_data[idx].perms, d, &(perms[d])); + } + + /* SC always needs access */ + perms[SC_DID] = SC_RM_PERM_SEC_RW; + + /* Grant parent access */ + if (rm_part_data[rm_rsrc_data[idx].owner].grant != SC_FALSE) + { + sc_rm_did_t did = rm_part_data[rm_rsrc_data[idx].owner].did; + sc_rm_did_t pdid + = rm_part_data[rm_part_data[rm_rsrc_data[idx].owner].parent].did; + + perms[pdid] = MAX(perms[pdid], perms[did]); + } + + /* Block access */ + if ((blocking != SC_FALSE) && (rm_rsrc_data[idx].block != SC_FALSE)) + { + for (d = 0; d < SC_RM_NUM_DOMAIN; d++) + { + perms[d] = SC_RM_PERM_NONE; + } + } + + ss_rdc_set_peripheral(idx, SC_TRUE, SC_FALSE, perms, SC_FALSE); + } + #endif /* XRDC_SUPPORT */ +} + +/*--------------------------------------------------------------------------*/ +/* Update RDC memory region */ +/*--------------------------------------------------------------------------*/ +static sc_err_t update_rdc_memreg(sc_rm_mr_t mr, sc_faddr_t old_start, + sc_faddr_t old_end, sc_faddr_t new_start, sc_faddr_t new_end) +{ + #ifdef XRDC_SUPPORT + sc_rm_did_t d; + sc_rm_perm_t perms[SC_RM_NUM_DOMAIN]; + sc_rm_mr_t m; + sc_bool_t used; + + SIMU_ASRT(mr < SC_RM_NUM_MEMREG, + "bad mr"); + SIMU_ASRT(rm_mreg_data[mr].owner < SC_RM_NUM_PARTITION, + "bad owner pt"); + + /* Prep */ + used = SC_FALSE; + for (d = 0U; d < SC_RM_NUM_DOMAIN; d++) + { + perms[d] = 0U; + } + + /* Extract permissions for all coincident regions */ + for (m = 0U; m < SC_RM_NUM_MEMREG; m++) + { + /* Coincident? */ + if ((rm_mreg_data[m].used != SC_FALSE) + && (rm_mreg_data[m].start == old_start) + && (rm_mreg_data[m].end == old_end)) + { + /* Extract compressed access perms */ + for (d = 0U; d < SC_RM_NUM_DOMAIN; d++) + { + sc_rm_perm_t p; + + /* Get permissions */ + get_perms(rm_mreg_data[m].perms, d, &p); + + /* Take max */ + perms[d] = MAX(perms[d], p); + } + + if (rm_mreg_data[m].used != SC_FALSE) + { + used = SC_TRUE; + } + } + } + + /* SC always needs access */ + perms[SC_DID] = SC_RM_PERM_SEC_RW; + + /* Give SECO access if monitor in use */ + if (has_monitor != SC_FALSE) + { + perms[SECO_DID] = MAX(perms[SECO_DID], SC_RM_PERM_SEC_RW); + } + + /* Grant parent access */ + if (rm_part_data[rm_mreg_data[mr].owner].grant != SC_FALSE) + { + sc_rm_did_t did = rm_part_data[rm_mreg_data[mr].owner].did; + sc_rm_did_t pdid + = rm_part_data[rm_part_data[rm_mreg_data[mr].owner].parent].did; + + perms[pdid] = MAX(perms[pdid], perms[did]); + } + +#ifdef ERR050601_WORKAROUND + /* Update perms to block AP */ + soc_block_ap_memreg(mr, perms); +#endif + + return ss_rdc_set_memory(rm_mreg_data[mr].start, rm_mreg_data[mr].end, + used, perms, rm_mreg_data[mr].det, rm_mreg_data[mr].rmsg, + new_start, new_end); + #else + return SC_ERR_NONE; + #endif /* XRDC_SUPPORT */ +} + +/** @} */ + diff --git a/platform/svc/rm/svc.h b/platform/svc/rm/svc.h new file mode 100755 index 0000000..2bae1d4 --- /dev/null +++ b/platform/svc/rm/svc.h @@ -0,0 +1,757 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/rm/svc.h + * + * Header file containing the API for the System Controller (SC) Resource + * Management (RM) function. This includes functions for partitioning + * resources, pads, and memory regions. + * + * @addtogroup RM_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_RM_SVC_H +#define SC_RM_SVC_H + +/* Includes */ + +#include "main/main.h" +#include "svc/rm/api.h" + +/* Defines */ + +/*! Width of SS index */ +#define SC_SS_IDX_W 8U + +/*! Define used to indicate function should apply to all partitions */ +#define SC_PT_ALL SC_RM_NUM_PARTITION + +#define RM_RANGE_MASK U16(0x8000U) +#define RM_RANGE(X,Y) ((X) | RM_RANGE_MASK), (Y) + +/* Types */ + +/*! Type for a ss resource index */ +typedef uint8_t sc_ss_idx_t; + +/*! + * This type is used for a memory list. + */ +typedef struct +{ + sc_faddr_t addr_start; + sc_faddr_t addr_end; +} sc_rm_mem_list_t; + +/* Functions */ + +/*! + * @name Internal Functions + * @{ + */ + +/*! + * Internal SC function to initialize the RM service. + * + * @param[in] api_phase init phase + * + * Initializes the API if /a api_phase = SC_TRUE, otherwise initializes the HW + * managed by the RM service. API must be initialized before anything else is + * done with the service. + */ +void rm_init(sc_bool_t api_phase); + +/*! + * Internal SC function to specify the number of static partitions. + * + * @param[in] num number of static partitions + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Static partitions will be skipped when a new partition is allocated. + * The minimum possible is 0 and the max possible is SC_RM_NUM_PARTITION. + */ +sc_err_t rm_reserve_static_pt(sc_rm_pt_t num); + +/*! + * Internal SC function to specify the number of static domains. + * + * @param[in] num number of static domains + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Static domains will be skipped when a new partition is allocated. + * The minimum possible is 0 and the max possible is SC_RM_NUM_DOMAIN. + */ +sc_err_t rm_reserve_static_did(sc_rm_did_t num); + +/*! + * Internal SC function to request that the SC create a new resource partition. + * + * @see sc_rm_partition_alloc(). + */ +sc_err_t rm_partition_alloc(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt, + sc_bool_t secure, sc_bool_t isolated, sc_bool_t restricted, sc_bool_t grant, + sc_bool_t coherent); + +/*! + * Internal SC function to make a partition confidential. + * + * @see sc_rm_set_confidential(). + */ +sc_err_t rm_set_confidential(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, sc_bool_t retro); + +/*! + * Internal SC function to free a partition and assigns all resources to the caller. + * + * @see sc_rm_partition_free(). + */ +sc_err_t rm_partition_free(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! + * Internal SC function to get the partition handle of the caller. + * + * @see sc_rm_get_partition(). + */ +sc_err_t rm_get_partition(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt); + +/*! + * Internal SC function to determine if a partition is enabled (used) or not. + * + * @param[in] pt partition to check + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_bool_t rm_is_partition_used(sc_rm_pt_t pt); + +/*! + * Internal SC function to get the security state of partition. + * + * @return Returns SC_TRUE if \a caller's partition is secure. + */ +sc_bool_t rm_is_secure_partition(sc_rm_pt_t caller_pt); + +/*! + * Internal SC function to get the isolation state of partition. + * + * @return Returns SC_TRUE if \a caller's partition is isolated. + */ +sc_bool_t rm_is_partition_isolated(sc_rm_pt_t pt); + +/*! + * Internal SC function to return if the partition has system access. + * + * @param[in] pt partition to check + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_bool_t rm_is_sys_access(sc_rm_pt_t pt); + +/*! + * Internal SC function to set the control partition. + * + * @param[in] pt partition to be controlled + * @param[in] control partition that will have control + * + * Allows the following functions to be called by \a control for + * partition \a pt. + * + * - sc_pm_boot() + * - sc_pm_set_partition_power_mode() + * - sc_pm_reboot_partition() + */ +void rm_set_control_partition(sc_rm_pt_t pt, sc_rm_pt_t control); + +/*! + * Internal SC function to return the control partition. + * + * @param[in] pt partition to return + * + * @return Returns the control partition (0 if none). + */ +sc_rm_pt_t rm_get_control_partition(sc_rm_pt_t pt); + +/*! + * Internal SC function to return the parent of a partition. + * + * @param[in] pt partition to check + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_rm_pt_t rm_get_partition_parent(sc_rm_pt_t pt); + +/*! + * Internal SC function to get the DID of the caller's partition. + * + * @see sc_rm_get_did(). + */ +sc_rm_did_t rm_get_did(sc_rm_pt_t caller_pt); + +/*! + * Internal SC function to force a partition to use a specific static DID. + * + * @see sc_rm_partition_static(). + */ +sc_err_t rm_partition_static(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rm_did_t did); + +/*! + * Internal SC function to lock a partition. + * + * @see sc_rm_partition_lock(). + */ +sc_err_t rm_partition_lock(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! + * Internal SC function to set a new parent for a partition. + * + * @see sc_rm_set_parent(). + */ +sc_err_t rm_set_parent(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rm_pt_t pt_parent); + +/*! + * Internal SC function to check if caller is the parent of a partition. + * + * @param[in] caller_pt handle of caller partition + * @param[in] pt handle of partition to check + * + * Returns SC_TRUE of the caller is the parent of another partition. + * Used to check access permissions on functions that affect a partition. + */ +sc_bool_t rm_is_parent(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! + * Internal SC function to check if caller is an ancestor of owner. + * + * @param[in] caller_pt handle of caller partition + * @param[in] pt_owner handle of owner partition + * + * Returns SC_TRUE of the caller is the owner or is an ancestor of the + * owner. Used to check access permissions on functions that affect + * a partition. + */ +sc_bool_t rm_check_ancestor(sc_rm_pt_t caller_pt, sc_rm_pt_t pt_owner); + +/*! + * Internal SC function to move all resources/pads owned by a source partition to a + * destination partition. + * + * @see sc_rm_move_all(). + */ +sc_err_t rm_move_all(sc_rm_pt_t caller_pt, sc_rm_pt_t pt_src, + sc_rm_pt_t pt_dst, sc_bool_t move_rsrc, sc_bool_t move_pads); + +/*! + * Internal SC function to assign ownership of a resource to a partition. + * + * @see sc_rm_assign_resource(). + */ +sc_err_t rm_assign_resource(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rsrc_t resource); + +/*! + * Internal SC function to flag resource as movable or not. + * + * @see sc_rm_set_resource_movable(). + */ +sc_err_t rm_set_resource_movable(sc_rm_pt_t caller_pt, + sc_rsrc_t resource_fst, sc_rsrc_t resource_lst, sc_bool_t movable); + +/*! + * Internal SC function to flag all of a subsystem's resources as movable + * or not. + * + * @see sc_rm_set_subsys_rsrc_movable(). + */ + sc_err_t rm_set_subsys_rsrc_movable(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_bool_t movable); + +/*! + * Internal SC function to set attributes for a resource which is a bus master + * (i.e. capable of DMA). + * + * @see sc_rm_set_master_attributes(). + */ +sc_err_t rm_set_master_attributes(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_spa_t sa, sc_rm_spa_t pa, sc_bool_t smmu_bypass); + +/*! + * Internal SC function to set the StreamID for a resource which is a + * bus master (i.e. capable of DMA). + * + * @see sc_rm_set_master_sid(). + */ +sc_err_t rm_set_master_sid(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_sid_t sid); + +/*! + * Internal SC function to update a master resource. It takes a + * resource index as an argument. + * + * @param[in] idx unified resource index + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t rm_update_master(sc_rm_idx_t idx); + +/*! + * Internal SC function to set access permissions for a peripheral resource. + * + * @see sc_rm_set_peripheral_permissions(). + */ +sc_err_t rm_set_peripheral_permissions(sc_rm_pt_t caller_pt, + sc_rsrc_t resource, sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * Internal SC function to update a peripheral resource. It takes a + * resource index as an argument. + * + * @param[in] idx unified resource index + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t rm_update_peripheral(sc_rm_idx_t idx); + +/*! + * Internal SC function to update a resource in HW. + * + * @param[in] resource resource to update + */ +void rm_update_resource(sc_rsrc_t resource); + +/*! + * Internal SC function to return subsystem specific info about a resource. It + * takes a resource index as an argument. + * + * @param[in] idx unified resource index + * @param[out] ss subsystem + * @param[out] ss_idx subsystem relative resource index + */ +void rm_get_ridx_ss_info(sc_rm_idx_t idx, sc_sub_t *ss, sc_ss_idx_t *ss_idx); + +/*! + * Internal SC function to check the validity of a resource and return the + * unified resource index. + * + * @param[in] resource resource to check + * @param[out] idx unified resource index + * + * @return Returns SC_TRUE if \a resource is valid. + * + * The index can be used to index into any resource array of size + * SC_NUM_RSRCS. It is also used for most private RM functions. + */ +sc_bool_t rm_check_map_ridx(sc_rsrc_t resource, sc_rm_idx_t *idx); + +/*! + * Internal SC function to check the validity of a resource and return the + * unified resource index. + * + * @param[in] resource resource to check + * @param[out] idx unified resource index + * + * The index can be used to index into any resource array of size + * SC_NUM_RSRCS. It is also used for most private RM functions. + */ +void rm_check_map_ridx_v(sc_rsrc_t resource, sc_rm_idx_t *idx); + +/*! + * Internal SC function to get ownership status of a resource. + * + * @see sc_rm_is_resource_owned(). + */ +sc_bool_t rm_is_resource_owned(sc_rm_pt_t caller_pt, sc_rsrc_t resource); + +/*! + * Internal SC function to check if a resource is owned by the caller. It takes a + * resource index as an argument. + * + * @param[in] caller_pt handle of caller partition + * @param[in] idx unified resource index + * + * @return Returns SC_TRUE if \a idx is owned. + */ +sc_bool_t rm_is_ridx_owned(sc_rm_pt_t caller_pt, sc_rm_idx_t idx); + +/*! + * Internal SC function to check if a resource is available. It takes a + * resource as an argument. Resource availability is based in hardware, + * fuses, and board. Not based on partition ownership. + * + * @param[in] resource resource to check + * + * @return Returns SC_TRUE if \a resource is available. + */ +sc_bool_t rm_is_resource_avail(sc_rsrc_t resource); + +/*! + * Internal SC function covvert a resource index to a resource. + * + * @param[in] idx unified resource index + * + * @return Returns resource. +*/ +sc_rsrc_t rm_get_resource(sc_rm_idx_t idx); + +/*! + * Internal SC function to check if a resource is available. It takes a + * resource index as an argument. Resource availability is based in + * hardware, fuses, and board. Not based on partition ownership. + * + * @param[in] idx unified resource index + * + * @return Returns SC_TRUE if \a idx is available. + */ +sc_bool_t rm_is_ridx_avail(sc_rm_idx_t idx); + +/*! + * Internal SC function to get access rights of a resource. + * + * @param[in] caller_pt handle of caller partition + * @param[in] resource resource to check + * + * @return Returns SC_TRUE if \a resource is accessible. + */ +sc_bool_t rm_is_resource_access_allowed(sc_rm_pt_t caller_pt, sc_rsrc_t resource); + +/*! + * Internal SC function to check if a resource is controllable by the caller. + * It takes a resource index as an argument. + * + * @param[in] caller_pt handle of caller partition + * @param[in] idx unified resource index + * + * @return Returns SC_TRUE if \a idx access is allowed. + */ +sc_bool_t rm_is_ridx_access_allowed(sc_rm_pt_t caller_pt, sc_rm_idx_t idx); + +/*! + * Internal SC function to return the owner partition for a resource. + * + * @see sc_rm_get_resource_owner(). + */ +sc_err_t rm_get_resource_owner(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_pt_t *pt); + +/*! + * Internal SC function to return the ownering partition for a resource. It takes a + * resource index as an argument. + * + * @param[in] idx unified resource index + * @param[out] pt return handle for partition + */ +void rm_get_ridx_owner(sc_rm_idx_t idx, sc_rm_pt_t *pt); + +/*! + * Internal SC function used to test if a resource is a bus master. + * + * @see sc_rm_is_resource_master(). + */ +sc_bool_t rm_is_resource_master(sc_rm_pt_t caller_pt, sc_rsrc_t resource); + +/*! + * Internal SC function to check if a resource is a master. It takes a + * resource index as an argument. + * + * @param[in] idx unified resource index + * + * @return Returns SC_TRUE if \a idx is a master. + */ +sc_bool_t rm_is_ridx_master(sc_rm_idx_t idx); + +/*! + * Internal SC function used to test if a resource is a peripheral. + * + * @see sc_rm_is_resource_peripheral(). + */ +sc_bool_t rm_is_resource_peripheral(sc_rm_pt_t caller_pt, sc_rsrc_t resource); + +/*! + * Internal SC function to check if a resource is a peripheral. It takes a + * resource index as an argument. + * + * @param[in] idx unified resource index + * + * @return Returns SC_TRUE if \a idx is a peripheral. + */ +sc_bool_t rm_is_ridx_peripheral(sc_rm_idx_t idx); + +/*! + * Internal SC function used to obtain info about a resource. + * + * @see sc_rm_get_resource_info(). + */ +sc_err_t rm_get_resource_info(sc_rm_pt_t caller_pt, sc_rsrc_t resource, + sc_rm_sid_t *sid); + +/*! + * Internal SC function to control if a access to a resource should be + * blocked via HW. + * + * @param[in] idx unified resource index + * @param[in] block block state (SC_TRUE to block) + * + * @return Returns current block state. + */ +sc_bool_t rm_ridx_block(sc_rm_idx_t idx, sc_bool_t block); + +/*! + * Internal SC function to request that the SC create a new memory region. + * + * @see sc_rm_memreg_alloc(). + */ +sc_err_t rm_memreg_alloc(sc_rm_pt_t caller_pt, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * Internal SC function to split a memory region. + * + * @see sc_rm_memreg_split(). + */ +sc_err_t rm_memreg_split(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_rm_mr_t *mr_ret, sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * Internal SC function to fragment a memory region. + * + * @see sc_rm_memreg_frag(). + */ +sc_err_t rm_memreg_frag(sc_rm_pt_t caller_pt, sc_rm_mr_t *mr_ret, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * Internal SC function to free a memory region. + * + * @see sc_rm_memreg_free(). + */ +sc_err_t rm_memreg_free(sc_rm_pt_t caller_pt, sc_rm_mr_t mr); + +/*! + * Internal SC function to find a memory region. + * + * @see sc_rm_find_memreg(). + */ +sc_err_t rm_find_memreg(sc_rm_pt_t caller_pt, sc_rm_mr_t *mr, + sc_faddr_t addr_start, sc_faddr_t addr_end); + +/*! + * Internal SC function to assign ownership of a memory region. + * + * @see sc_rm_assign_memreg(). + */ +sc_err_t rm_assign_memreg(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_rm_mr_t mr); + +/*! + * Internal SC function to set access permissions for a memory region. + * + * @see sc_rm_set_memreg_permissions(). + */ +sc_err_t rm_set_memreg_permissions(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_rm_pt_t pt, sc_rm_perm_t perm); + +/*! + * Internal SC function to set configure IEE parameters for a mem region. + * + * @see sc_rm_set_memreg_iee(). + */ +sc_err_t rm_set_memreg_iee(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_rm_det_t det, sc_rm_rmsg_t rmsg); + +/*! + * Internal SC function to get ownership status of a memory region. + * + * @see sc_rm_is_memreg_owned(). + */ +sc_bool_t rm_is_memreg_owned(sc_rm_pt_t caller_pt, sc_rm_mr_t mr); + +/*! + * Internal SC function used to obtain info about a memory region. + * + * @see sc_rm_get_memreg_info(). + */ +sc_err_t rm_get_memreg_info(sc_rm_pt_t caller_pt, sc_rm_mr_t mr, + sc_faddr_t *addr_start, sc_faddr_t *addr_end); + +/*! + * Internal SC function to assign ownership of a pad to a partition. + * + * @see sc_rm_assign_pad(). + */ +sc_err_t rm_assign_pad(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_pad_t pad); + +/*! + * Internal SC function to flag pad as movable or not. + * + * @see sc_rm_set_pad_movable(). + */ +sc_err_t rm_set_pad_movable(sc_rm_pt_t caller_pt, sc_pad_t pad_first, + sc_pad_t pad_last, sc_bool_t movable); + +/*! + * Internal SC function to get ownership status of a pad. + * + * @see sc_rm_is_pad_owned(). + */ +sc_bool_t rm_is_pad_owned(sc_rm_pt_t caller_pt, sc_pad_t pad); + +/*! + * Internal SC function to get the owner of a pad. + * + * @param[in] pad pad to get + * @param[out] pt pointer to return partition + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t rm_get_pad_owner(sc_pad_t pad, sc_rm_pt_t *pt); + + +/*! + * Internal function to create a partition and assign all resources. + * + * @param[in] caller_pt handle of caller partition + * @param[out] pt return handle for partition + * @param[in] secure boolean indicating if this partition should be secure + * @param[in] isolated boolean indicating if this partition should be HW isolated + * @param[in] restricted boolean indicating if this partition should be restricted + * @param[in] grant boolean indicating if this partition should always grant + * @param[in] coherent boolean indicating if this partition is coherent + * @param[in] resource resource in subsystem to completly assign (SC_NUM_RESOURCE for none) + * @param[in] rsrc_lst pointer to resource list (NULL if none) + * @param[in] rsrc_cnt number of entries in the resource list (0 if none) + * @param[in] pad_lst pointer to pad list (NULL if none) + * @param[in] pad_cnt number of entries in the pad list (0 if none) + * @param[in] mem_lst pointer to memory list (NULL if none) + * @param[in] mem_cnt number of entries in the memory list (0 if none) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * See sc_rm_partition_alloc() for info on most parameters and error returns. + * + * Use RM_RANGE() to specifiy a resource/pad range. Counts as two in the + * count parameter. + */ +sc_err_t rm_partition_create(sc_rm_pt_t caller_pt, sc_rm_pt_t *pt, + sc_bool_t secure, sc_bool_t isolated, sc_bool_t restricted, + sc_bool_t grant, sc_bool_t coherent, sc_rsrc_t resource, + const sc_rsrc_t *rsrc_lst, uint32_t rsrc_cnt, + const sc_pad_t *pad_lst, uint32_t pad_cnt, + const sc_rm_mem_list_t *mem_lst, uint32_t mem_cnt); + +/*! + * Enable blocking of resources powered off. + */ +void rm_enable_blocking(void); + +/*! + * Internal SC function to reload a subsystem's XRDC info after a power on. + * + * @param[in] ss subsystem + * @param[in] block_enb flag to skip SCU, skip mem + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +sc_err_t rm_init_subsys(sc_sub_t ss, sc_bool_t block_enb); + +/*! + * Internal SC function to reload all memory regions. + */ +void rm_load_memrg(void); + +/*! + * Internal SC function to dump RM state for debug. + * + * @see sc_rm_set_pad_movable(). + */ +void rm_dump(sc_rm_pt_t caller_pt); + +/** @} */ + +#ifdef DEBUG + + /*! + * @name Debug Functions + * @{ + */ + + /*! + * Internal SC function to dump the internal partition state of the RM service. + * + * @param[in] pt partition to dump + */ + void rm_dump_partition(sc_rm_pt_t pt); + + /*! + * Internal SC function to dump the internal resource state of the RM service. + * + * @param[in] pt partition to dump + */ + void rm_dump_resources(sc_rm_pt_t pt); + + /*! + * Internal SC function to dump the internal memory state of the RM service. + * + * @param[in] pt partition to dump + */ + void rm_dump_memregs(sc_rm_pt_t pt); + + /*! + * Internal SC function to dump the internal pad state of the RM service. + * + * @param[in] pt partition to dump + */ + void rm_dump_pads(sc_rm_pt_t pt); + + /** @} */ +#endif + +/*! Max domain used */ +extern uint8_t rm_max_did; + +#if defined(DEBUG) && defined(HAS_PARTITION_NAMES) + /*! Partition name pointers */ + extern const char *rm_part_names[SC_RM_NUM_PARTITION]; +#endif + +#endif /* SC_RM_SVC_H */ + +/** @} */ + diff --git a/platform/svc/seco/Makefile b/platform/svc/seco/Makefile new file mode 100755 index 0000000..b5c5f8c --- /dev/null +++ b/platform/svc/seco/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/seco/svc.o + +RPCS += $(OUT)/svc/seco/rpc_srv.o + +RPCL += $(OUT)/svc/seco/rpc_clnt.o + +RPCH += $(SRC)/svc/seco/rpc.h + +RPCC += $(SRC)/svc/seco/rpc_srv.c \ + $(SRC)/svc/seco/rpc_clnt.c \ + $(SRC)/svc/seco/rpc_xlate.c + +RPCHDR += $(SRC)/svc/seco/rpc_header.h + +DIRS += $(OUT)/svc/seco + diff --git a/platform/svc/seco/api.h b/platform/svc/seco/api.h new file mode 100755 index 0000000..6d42dfc --- /dev/null +++ b/platform/svc/seco/api.h @@ -0,0 +1,952 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/seco/api.h + * + * Header file containing the public API for the System Controller (SC) + * Security (SECO) function. + * + * @addtogroup SECO_SVC SECO: Security Service + * + * @brief Module for the Security (SECO) service. + * + * @anchor seco_err + * + * @includedoc seco/details.dox + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SECO_API_H +#define SC_SECO_API_H + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" + +/* Defines */ + +/*! + * @name Defines for sc_seco_auth_cmd_t + */ +/** @{ */ +#define SC_SECO_AUTH_CONTAINER 0U /*!< Authenticate container */ +#define SC_SECO_VERIFY_IMAGE 1U /*!< Verify image */ +#define SC_SECO_REL_CONTAINER 2U /*!< Release container */ +#define SC_SECO_AUTH_SECO_FW 3U /*!< SECO Firmware */ +#define SC_SECO_AUTH_HDMI_TX_FW 4U /*!< HDMI TX Firmware */ +#define SC_SECO_AUTH_HDMI_RX_FW 5U /*!< HDMI RX Firmware */ +#define SC_SECO_EVERIFY_IMAGE 6U /*!< Enhanced verify image */ +/** @} */ + +/*! + * @name Defines for seco_rng_stat_t + */ +/** @{ */ +#define SC_SECO_RNG_STAT_UNAVAILABLE 0U /*!< Unable to initialize the RNG */ +#define SC_SECO_RNG_STAT_INPROGRESS 1U /*!< Initialization is on-going */ +#define SC_SECO_RNG_STAT_READY 2U /*!< Initialized */ +/** @} */ + +/* Types */ + +/*! + * This type is used to issue SECO authenticate commands. + */ +typedef uint8_t sc_seco_auth_cmd_t; + +/*! + * This type is used to return the RNG initialization status. + */ +typedef uint32_t sc_seco_rng_stat_t; + +/* Functions */ + +/*! + * @name Image Functions + * @{ + */ + +/*! + * This function loads a SECO image. + * + * @param[in] ipc IPC handle + * @param[in] addr_src address of image source + * @param[in] addr_dst address of image destination + * @param[in] len length of image to load + * @param[in] fw SC_TRUE = firmware load + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to load images via the SECO. Examples include SECO + * Firmware and IVT/CSF data used for authentication. These are usually + * loaded into SECO TCM. \a addr_src is in secure memory. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 IMAGE_LOAD(UI64 addr_src, UI64 addr_dst, UI32 len, IB fw) #1 */ +sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * This function is used to authenticate a SECO image or command. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_BUSY if SECO is busy with another authentication request, + * - SC_ERR_FAIL if SECO response is bad, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to authenticate a SECO image or issue a security + * command. \a addr often points to an container. It is also + * just data (or even unused) for some commands. + * + * Implementation of this command depends on the underlying security + * architecture of the device. For example, on devices with SECO FW, + * the following options apply: + * + * - cmd=SC_SECO_AUTH_CONTAINER, addr=container address (sends AHAB_AUTH_CONTAINER_REQ to SECO) + * - cmd=SC_SECO_VERIFY_IMAGE, addr=image mask (sends AHAB_VERIFY_IMAGE_REQ to SECO) + * - cmd=SC_SECO_REL_CONTAINER, addr unused (sends AHAB_RELEASE_CONTAINER_REQ to SECO) + * - cmd=SC_SECO_AUTH_HDMI_TX_FW, addr unused (sends AHAB_ENABLE_HDMI_X_REQ with Subsystem=0 to SECO) + * - cmd=SC_SECO_AUTH_HDMI_RX_FW, addr unused (sends AHAB_ENABLE_HDMI_X_REQ with Subsystem=1 to SECO) + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 AUTHENTICATE(UI8 cmd, UI64 addr) #2 */ +sc_err_t sc_seco_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/*! + * This function is used to authenticate a SECO image or command. This is an + * enhanced version that has additional mask arguments. + * + * @param[in] ipc IPC handle + * @param[in] cmd authenticate command + * @param[in] addr address of/or metadata + * @param[in] mask1 metadata + * @param[in] mask2 metadata + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_BUSY if SECO is busy with another authentication request, + * - SC_ERR_FAIL if SECO response is bad, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This supports all the commands found in sc_seco_authenticate(). Those + * commands should set both masks to 0 (except SC_SECO_VERIFY_IMAGE). + + * New commands are as follows: + * + * - cmd=SC_SECO_VERIFY_IMAGE, addr unused, mask1=image mask, mask2 unused (sends AHAB_VERIFY_IMAGE_REQ to SECO) + * - cmd=SC_SECO_EVERIFY_IMAGE, addr=container address, mask1=image mask, mask2=move mask (sends AHAB_EVERIFY_IMAGE_REQ to SECO) + * + * Note SC_SECO_EVERIFY_IMAGE not available on all SoC or SoC versions. + * Calling with this option will return an error if not supported. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 ENH_AUTHENTICATE(UI8 cmd, UI64 addr, UI32 mask1, UI32 mask2) #24 */ +sc_err_t sc_seco_enh_authenticate(sc_ipc_t ipc, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr, + uint32_t mask1, uint32_t mask2); + +/** @} */ + +/*! + * @name Lifecycle Functions + * @{ + */ + +/*! + * This function updates the lifecycle of the device. + * + * @param[in] ipc IPC handle + * @param[in] change desired lifecycle transition + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used for going from Open to NXP Closed to OEM Closed. + * Note \a change is NOT the new desired lifecycle. It is a lifecycle + * transition as documented in the SECO API Reference Guide. + * + * If any SECO request fails or only succeeds because the part is in an + * "OEM open" lifecycle, then a request to transition from "NXP closed" + * to "OEM closed" will also fail. For example, booting a signed container + * when the OEM SRK is not fused will succeed, but as it is an abnormal + * situation, a subsequent request to transition the lifecycle will return + * an error. + */ +/* IDL: E8 FORWARD_LIFECYCLE(UI32 change) #3 */ +sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change); + +/*! + * This function updates the lifecycle to one of the return lifecycles. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * To switch back to NXP states (Full Field Return), message must be signed + * by NXP SRK. For OEM States (Partial Field Return), must be signed by OEM + * SRK. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 RETURN_LIFECYCLE(UI64 addr) #4 */ +sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to commit into the fuses any new SRK revocation + * and FW version information that have been found in the primary and + * secondary containers. + * + * @param[in] ipc IPC handle + * @param[in,out] info pointer to information type to be committed + * + * The return \a info will contain what was actually committed. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a info is invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + */ +/* IDL: E8 COMMIT(UIO32 info) #5 */ +sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info); + +/** @} */ + +/*! + * @name Attestation Functions + * @{ + */ + +/*! + * This function is used to set the attestation mode. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] mode mode + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a mode is invalid, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to set the SECO attestation mode. This can be prover + * or verifier. See the SECO API Reference Guide for more on the + * supported modes, mode values, and mode behavior. + */ +/* IDL: E8 ATTEST_MODE(UI32 mode) #6 */ +sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode); + +/*! + * This function is used to request attestation. Only the owner of + * the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] nonce unique value + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This is used to ask SECO to perform an attestation. The result depends + * on the attestation mode. After this call, the signature can be + * requested or a verify can be requested. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 ATTEST(UI64 nonce) #7 */ +sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce); + +/*! + * This function is used to retrieve the attestation public key. + * Mode must be verifier. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parameter must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 96 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 GET_ATTEST_PKEY(UI64 addr) #8 */ +sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to retrieve attestation signature and parameters. + * Mode must be provider. Only the owner of the SC_R_ATTESTATION resource + * may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address to write response + * + * Result will be written to \a addr. The \a addr parameter must point + * to an address SECO can access. It must be 64-bit aligned. There + * should be 120 bytes of space. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 GET_ATTEST_SIGN(UI64 addr) #9 */ +sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to verify attestation. Mode must be verifier. + * Only the owner of the SC_R_ATTESTATION resource may make this call. + * + * @param[in] ipc IPC handle + * @param[in] addr address of signature + * + * The \a addr parameter must point to an address SECO can access. It must be + * 64-bit aligned. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if \a addr bad or attestation has not been requested, + * - SC_ERR_NOACCESS if SC_R_ATTESTATON not owned by caller, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_FAIL if signature doesn't match, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 ATTEST_VERIFY(UI64 addr) #10 */ +sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr); + +/** @} */ + +/*! + * @name Key Functions + * @{ + */ + +/*! + * This function is used to generate a SECO key blob. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] load_addr load address + * @param[in] export_addr export address + * @param[in] max_size max export size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used to encapsulate sensitive keys in a specific structure + * called a blob, which provides both confidentiality and integrity protection. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 GEN_KEY_BLOB(UI32 id, UI64 load_addr, UI64 export_addr, UI16 max_size) #11 */ +sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size); + +/*! + * This function is used to load a SECO key. + * + * @param[in] ipc IPC handle + * @param[in] id key identifier + * @param[in] addr key address + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used to install private cryptographic keys encapsulated + * in a blob previously generated by SECO. The controller can be either the + * IEE or the VPU. The blob header carries the controller type and the key + * size, as provided by the user when generating the key blob. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 LOAD_KEY(UI32 id, UI64 addr) #12 */ +sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id, + sc_faddr_t addr); + +/** @} */ + +/*! + * @name Manufacturing Protection Functions + * @{ + */ + +/*! + * This function is used to get the manufacturing protection public key. + * + * @param[in] ipc IPC handle + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is supported only in OEM-closed lifecycle. It generates + * the mfg public key and stores it in a specific location in the secure + * memory. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 GET_MP_KEY(UI64 dst_addr, UI16 dst_size) #13 */ +sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + uint16_t dst_size); + +/*! + * This function is used to update the manufacturing protection message + * register. + * + * @param[in] ipc IPC handle + * @param[in] addr data address + * @param[in] size size + * @param[in] lock lock_reg + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is supported only in OEM-closed lifecycle. It updates the + * content of the MPMR (Manufacturing Protection Message register of 256 + * bits). This register will be appended to the input-data message when + * generating the signature. Please refer to the CAAM block guide for details. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 UPDATE_MPMR(UI64 addr, UI8 size, UI8 lock) #14 */ +sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + uint8_t size, uint8_t lock); + +/*! + * This function is used to get the manufacturing protection signature. + * + * @param[in] ipc IPC handle + * @param[in] msg_addr message address + * @param[in] msg_size message size + * @param[in] dst_addr destination address + * @param[in] dst_size destination size + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_PARM if word fuse index param out of range or invalid, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * This function is used to generate an ECDSA signature for an input-data + * message and to store it in a specific location in the secure memory. It + * is only supported in OEM-closed lifecycle. In order to get the ECDSA + * signature, the RNG must be initialized. In case it has not been started + * an error will be returned. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 GET_MP_SIGN(UI64 msg_addr, UI16 msg_size, UI64 dst_addr, UI16 dst_size) #15 */ +sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size); + +/** @} */ + +/*! + * @name Debug Functions + * @{ + */ + +/*! + * This function is used to return the SECO FW build info. + * + * @param[in] ipc IPC handle + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + */ +/* IDL: R0 BUILD_INFO(UO32 version, UO32 commit) #16 */ +void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); + +/*! + * This function is used to return the V2X FW build info. + * + * @param[in] ipc IPC handle + * @param[out] version pointer to return build number + * @param[out] commit pointer to return commit ID (git SHA-1) + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOTFOUND if V2X not available, + * - SC_ERR_IPC if V2X response has bad header tag or size, + * - SC_ERR_VERSION if V2X response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + */ +/* IDL: E8 V2X_BUILD_INFO(UO32 version, UO32 commit) #30 ^API_HAS_V2X */ +sc_err_t sc_seco_v2x_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit); + +/*! + * This function is used to return SECO chip info. + * + * @param[in] ipc IPC handle + * @param[out] lc pointer to return lifecycle + * @param[out] monotonic pointer to return monotonic counter + * @param[out] uid_l pointer to return UID (lower 32 bits) + * @param[out] uid_h pointer to return UID (upper 32 bits) + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + */ +/* IDL: E8 CHIP_INFO(UO16 lc, UO16 monotonic, UO32 uid_l, UO32 uid_h) #17 */ +sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h); + +/*! + * This function securely enables debug. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 ENABLE_DEBUG(UI64 addr) #18 */ +sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to return an event from the SECO error log. + * + * @param[in] ipc IPC handle + * @param[out] idx index of event to return + * @param[out] event pointer to return event + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Read of \a idx 0 captures events from SECO. Loop starting + * with 0 until an error is returned to dump all events. + */ +/* IDL: E8 GET_EVENT(UI8 idx, UO32 event) #19 */ +sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, + uint32_t *event); + +/** @} */ + +/*! + * @name Miscellaneous Functions + * @{ + */ + +/*! + * This function securely writes a group of fuse words. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 FUSE_WRITE(UI64 addr) #20 */ +sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function applies a patch. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 PATCH(UI64 addr) #21 */ +sc_err_t sc_seco_patch(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function partitions the monotonic counter. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in,out] she pointer to number of SHE bits + * + * SECO uses an OTP monotonic counter to protect the SHE and HSM key-stores + * from roll-back attack. This function is used to define the number of + * monotonic counter bits allocated to SHE use. Two monotonic counter bits + * are used to store this information while the remaining bits are allocated + * to the HSM user. This function must be called before any SHE or HSM key stores + * are created in the system, otherwise the default configuration is applied. + * Returns the actual number of SHE bits. + * + * If the partition has been already configured, any attempt to re-configure + * the SHE partition to a different value will result in a failure response. + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 SET_MONO_COUNTER_PARTITION(UIO16 she) #28 */ +sc_err_t sc_seco_set_mono_counter_partition(sc_ipc_t ipc, uint16_t *she); + +/*! + * This function configures the SECO in FIPS mode. Only the owner of the + * SC_R_SYSTEM resource or a partition with access permissions to + * SC_R_SYSTEM can do this. + * + * @param[in] ipc IPC handle + * @param[in] mode FIPS mode + * @param[out] reason pointer to return failure reason + * + * This function permanently configures the SECO in FIPS approved mode. When in + * FIPS approved mode the following services will be disabled and receive a + * failure response: + * + * - Encrypted boot is not supported + * - Attestation is not supported + * - Manufacturing protection is not supported + * - DTCP load + * - SHE services are not supported + * - Assign JR is not supported (all JRs owned by SECO) + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_NOACCESS if caller does not have SC_R_SYSTEM access + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 SET_FIPS_MODE(UI8 mode, UO32 reason) #29 */ +sc_err_t sc_seco_set_fips_mode(sc_ipc_t ipc, uint8_t mode, uint32_t *reason); + +/*! + * This function will securely zeroize all plaintext secret and private + * cryptographic keys and CSPs within the module. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * This function is effective when the part is configured in FIPS approved + * mode only, no effects otherwise. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 FIPS_KEY_ZERO(UI64 addr) #31 */ +sc_err_t sc_seco_fips_key_zero(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function starts the random number generator. + * + * @param[in] ipc IPC handle + * @param[out] status pointer to return state of RNG + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * The RNG is started automatically after all CPUs are booted. This + * function can be used to start earlier and to check the status. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 START_RNG(UO32 status) #22 */ +sc_err_t sc_seco_start_rng(sc_ipc_t ipc, sc_seco_rng_stat_t *status); + +/*! + * This function sends a generic signed message to the + * SECO SHE/HSM components. + * + * @param[in] ipc IPC handle + * @param[in] addr address of message block + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Note \a addr must be a pointer to a signed message block. + * + * See the SECO API Reference Guide for more info. + */ +/* IDL: E8 SAB_MSG(UI64 addr) #23 */ +sc_err_t sc_seco_sab_msg(sc_ipc_t ipc, sc_faddr_t addr); + +/*! + * This function is used to enable security violation and tamper interrupts. + * These are then reported using the IRQ service via the SC_IRQ_SECVIO + * interrupt. Note it is automatically enabled at boot. + * + * @param[in] ipc IPC handle + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if caller does not own SC_R_SECVIO, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * The security violation interrupt is self-masking. Once it is cleared in + * the SNVS it must be re-enabled using this function. + */ +/* IDL: E8 SECVIO_ENABLE() #25 */ +sc_err_t sc_seco_secvio_enable(sc_ipc_t ipc); + +/*! + * This function is used to read/write SNVS security violation + * and tamper registers. + * + * @param[in] ipc IPC handle + * @param[in] id register ID + * @param[in] access 0=read, 1=write + * @param[in] data0 pointer to data to read or write + * @param[in] data1 pointer to data to read or write + * @param[in] data2 pointer to data to read or write + * @param[in] data3 pointer to data to read or write + * @param[in] data4 pointer to data to read or write + * @param[in] size number of valid data words + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if caller does not own SC_R_SECVIO, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * Unused data words can be passed a NULL pointer. + * + * See AHAB_MANAGE_SNVS_REQ in the SECO API Reference Guide for + * more info. + */ +/* IDL: E8 SECVIO_CONFIG(UI8 id, UI8 access, UIO32 data0, UIO32 data1, UIO32 data2, UIO32 data3, UIO32 data4, UI8 size) #26 */ +sc_err_t sc_seco_secvio_config(sc_ipc_t ipc, uint8_t id, uint8_t access, + uint32_t *data0, uint32_t *data1, uint32_t *data2, uint32_t *data3, + uint32_t *data4, uint8_t size); + +/*! + * This function is used to read/write SNVS security violation + * and tamper DGO registers. + * + * @param[in] ipc IPC handle + * @param[in] id regsiter ID + * @param[in] access 0=read, 1=write + * @param[in] data pointer to data to read or write + * + * @return Returns and error code (SC_ERR_NONE = success). + * + * Return errors codes: + * - SC_ERR_NOACCESS if caller does not own SC_R_SECVIO, + * - SC_ERR_UNAVAILABLE if SECO not available, + * - SC_ERR_IPC if SECO response has bad header tag or size, + * - SC_ERR_VERSION if SECO response has bad version, + * - Others, see the [Security Service Detailed Description](\ref seco_err) section + * + * See AHAB_MANAGE_SNVS_DGO_REQ in the SECO API Reference Guide + * for more info. + */ +/* IDL: E8 SECVIO_DGO_CONFIG(UI8 id, UI8 access, UIO32 data) #27 */ +sc_err_t sc_seco_secvio_dgo_config(sc_ipc_t ipc, uint8_t id, + uint8_t access, uint32_t *data); + +/** @} */ + +#endif /* SC_SECO_API_H */ + +/** @} */ + diff --git a/platform/svc/seco/rpc.h b/platform/svc/seco/rpc.h new file mode 100644 index 0000000..b40ee9e --- /dev/null +++ b/platform/svc/seco/rpc.h @@ -0,0 +1,110 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the SECO RPC implementation. + * + * @addtogroup SECO_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_SECO_RPC_H +#define SC_SECO_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC SECO function calls + */ +/** @{ */ +#define SECO_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define SECO_FUNC_IMAGE_LOAD 1U /*!< Index for sc_seco_image_load() RPC call */ +#define SECO_FUNC_AUTHENTICATE 2U /*!< Index for sc_seco_authenticate() RPC call */ +#define SECO_FUNC_ENH_AUTHENTICATE 24U /*!< Index for sc_seco_enh_authenticate() RPC call */ +#define SECO_FUNC_FORWARD_LIFECYCLE 3U /*!< Index for sc_seco_forward_lifecycle() RPC call */ +#define SECO_FUNC_RETURN_LIFECYCLE 4U /*!< Index for sc_seco_return_lifecycle() RPC call */ +#define SECO_FUNC_COMMIT 5U /*!< Index for sc_seco_commit() RPC call */ +#define SECO_FUNC_ATTEST_MODE 6U /*!< Index for sc_seco_attest_mode() RPC call */ +#define SECO_FUNC_ATTEST 7U /*!< Index for sc_seco_attest() RPC call */ +#define SECO_FUNC_GET_ATTEST_PKEY 8U /*!< Index for sc_seco_get_attest_pkey() RPC call */ +#define SECO_FUNC_GET_ATTEST_SIGN 9U /*!< Index for sc_seco_get_attest_sign() RPC call */ +#define SECO_FUNC_ATTEST_VERIFY 10U /*!< Index for sc_seco_attest_verify() RPC call */ +#define SECO_FUNC_GEN_KEY_BLOB 11U /*!< Index for sc_seco_gen_key_blob() RPC call */ +#define SECO_FUNC_LOAD_KEY 12U /*!< Index for sc_seco_load_key() RPC call */ +#define SECO_FUNC_GET_MP_KEY 13U /*!< Index for sc_seco_get_mp_key() RPC call */ +#define SECO_FUNC_UPDATE_MPMR 14U /*!< Index for sc_seco_update_mpmr() RPC call */ +#define SECO_FUNC_GET_MP_SIGN 15U /*!< Index for sc_seco_get_mp_sign() RPC call */ +#define SECO_FUNC_BUILD_INFO 16U /*!< Index for sc_seco_build_info() RPC call */ +#define SECO_FUNC_V2X_BUILD_INFO 30U /*!< Index for sc_seco_v2x_build_info() RPC call */ +#define SECO_FUNC_CHIP_INFO 17U /*!< Index for sc_seco_chip_info() RPC call */ +#define SECO_FUNC_ENABLE_DEBUG 18U /*!< Index for sc_seco_enable_debug() RPC call */ +#define SECO_FUNC_GET_EVENT 19U /*!< Index for sc_seco_get_event() RPC call */ +#define SECO_FUNC_FUSE_WRITE 20U /*!< Index for sc_seco_fuse_write() RPC call */ +#define SECO_FUNC_PATCH 21U /*!< Index for sc_seco_patch() RPC call */ +#define SECO_FUNC_SET_MONO_COUNTER_PARTITION 28U /*!< Index for sc_seco_set_mono_counter_partition() RPC call */ +#define SECO_FUNC_SET_FIPS_MODE 29U /*!< Index for sc_seco_set_fips_mode() RPC call */ +#define SECO_FUNC_FIPS_KEY_ZERO 31U /*!< Index for sc_seco_fips_key_zero() RPC call */ +#define SECO_FUNC_START_RNG 22U /*!< Index for sc_seco_start_rng() RPC call */ +#define SECO_FUNC_SAB_MSG 23U /*!< Index for sc_seco_sab_msg() RPC call */ +#define SECO_FUNC_SECVIO_ENABLE 25U /*!< Index for sc_seco_secvio_enable() RPC call */ +#define SECO_FUNC_SECVIO_CONFIG 26U /*!< Index for sc_seco_secvio_config() RPC call */ +#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /*!< Index for sc_seco_secvio_dgo_config() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming SECO RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void seco_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_SECO_RPC_H */ + +/** @} */ + diff --git a/platform/svc/seco/rpc_clnt.c b/platform/svc/seco/rpc_clnt.c new file mode 100644 index 0000000..250b3e7 --- /dev/null +++ b/platform/svc/seco/rpc_clnt.c @@ -0,0 +1,949 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the SECO service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup SECO_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "svc/seco/api.h" +#include "../../main/rpc.h" +#include "svc/seco/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 IMAGE_LOAD(UI64 addr_src, UI64 addr_dst, UI32 len, IB fw) #1 */ +sc_err_t sc_seco_image_load(sc_ipc_t ipc, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 7U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_IMAGE_LOAD); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr_src >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr_src); + RPC_U32(&msg, 8U) = U32(addr_dst >> 32ULL); + RPC_U32(&msg, 12U) = U32(addr_dst); + RPC_U32(&msg, 16U) = U32(len); + RPC_U8(&msg, 20U) = B2U8(fw); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 AUTHENTICATE(UI8 cmd, UI64 addr) #2 */ +sc_err_t sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, + sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_AUTHENTICATE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U8(&msg, 8U) = U8(cmd); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 ENH_AUTHENTICATE(UI8 cmd, UI64 addr, UI32 mask1, UI32 mask2) #24 */ +sc_err_t sc_seco_enh_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, + sc_faddr_t addr, uint32_t mask1, uint32_t mask2) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 6U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ENH_AUTHENTICATE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U32(&msg, 8U) = U32(mask1); + RPC_U32(&msg, 12U) = U32(mask2); + RPC_U8(&msg, 16U) = U8(cmd); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 FORWARD_LIFECYCLE(UI32 change) #3 */ +sc_err_t sc_seco_forward_lifecycle(sc_ipc_t ipc, uint32_t change) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_FORWARD_LIFECYCLE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(change); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 RETURN_LIFECYCLE(UI64 addr) #4 */ +sc_err_t sc_seco_return_lifecycle(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_RETURN_LIFECYCLE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 COMMIT(UIO32 info) #5 */ +sc_err_t sc_seco_commit(sc_ipc_t ipc, uint32_t *info) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_COMMIT); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(*info); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + *info = (uint32_t) RPC_U32(&msg, 0U); + + /* Return result */ + return err; +} + +/* IDL: E8 ATTEST_MODE(UI32 mode) #6 */ +sc_err_t sc_seco_attest_mode(sc_ipc_t ipc, uint32_t mode) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST_MODE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 ATTEST(UI64 nonce) #7 */ +sc_err_t sc_seco_attest(sc_ipc_t ipc, uint64_t nonce) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(nonce >> 32ULL); + RPC_U32(&msg, 4U) = U32(nonce); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_ATTEST_PKEY(UI64 addr) #8 */ +sc_err_t sc_seco_get_attest_pkey(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_ATTEST_PKEY); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_ATTEST_SIGN(UI64 addr) #9 */ +sc_err_t sc_seco_get_attest_sign(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_ATTEST_SIGN); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 ATTEST_VERIFY(UI64 addr) #10 */ +sc_err_t sc_seco_attest_verify(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ATTEST_VERIFY); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GEN_KEY_BLOB(UI32 id, UI64 load_addr, UI64 export_addr, UI16 max_size) #11 */ +sc_err_t sc_seco_gen_key_blob(sc_ipc_t ipc, uint32_t id, sc_faddr_t load_addr, + sc_faddr_t export_addr, uint16_t max_size) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 7U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GEN_KEY_BLOB); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(load_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(load_addr); + RPC_U32(&msg, 8U) = U32(export_addr >> 32ULL); + RPC_U32(&msg, 12U) = U32(export_addr); + RPC_U32(&msg, 16U) = U32(id); + RPC_U16(&msg, 20U) = U16(max_size); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 LOAD_KEY(UI32 id, UI64 addr) #12 */ +sc_err_t sc_seco_load_key(sc_ipc_t ipc, uint32_t id, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_LOAD_KEY); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U32(&msg, 8U) = U32(id); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_MP_KEY(UI64 dst_addr, UI16 dst_size) #13 */ +sc_err_t sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + uint16_t dst_size) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_MP_KEY); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(dst_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(dst_addr); + RPC_U16(&msg, 8U) = U16(dst_size); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 UPDATE_MPMR(UI64 addr, UI8 size, UI8 lock) #14 */ +sc_err_t sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, uint8_t size, + uint8_t lock) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 4U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_UPDATE_MPMR); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + RPC_U8(&msg, 8U) = U8(size); + RPC_U8(&msg, 9U) = U8(lock); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_MP_SIGN(UI64 msg_addr, UI16 msg_size, UI64 dst_addr, UI16 dst_size) #15 */ +sc_err_t sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 6U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_MP_SIGN); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(msg_addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(msg_addr); + RPC_U32(&msg, 8U) = U32(dst_addr >> 32ULL); + RPC_U32(&msg, 12U) = U32(dst_addr); + RPC_U16(&msg, 16U) = U16(msg_size); + RPC_U16(&msg, 18U) = U16(dst_size); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: R0 BUILD_INFO(UO32 version, UO32 commit) #16 */ +void sc_seco_build_info(sc_ipc_t ipc, uint32_t *version, uint32_t *commit) +{ + sc_rpc_msg_t msg; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_BUILD_INFO); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out receive message */ + if (version != NULL) + { + *version = (uint32_t) RPC_U32(&msg, 0U); + } + if (commit != NULL) + { + *commit = (uint32_t) RPC_U32(&msg, 4U); + } +} + +/* IDL: E8 V2X_BUILD_INFO(UO32 version, UO32 commit) #30 ^API_HAS_V2X */ +sc_err_t sc_seco_v2x_build_info(sc_ipc_t ipc, uint32_t *version, + uint32_t *commit) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_V2X_BUILD_INFO); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (version != NULL) + { + *version = (uint32_t) RPC_U32(&msg, 0U); + } + if (commit != NULL) + { + *commit = (uint32_t) RPC_U32(&msg, 4U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 CHIP_INFO(UO16 lc, UO16 monotonic, UO32 uid_l, UO32 uid_h) #17 */ +sc_err_t sc_seco_chip_info(sc_ipc_t ipc, uint16_t *lc, uint16_t *monotonic, + uint32_t *uid_l, uint32_t *uid_h) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_CHIP_INFO); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (uid_l != NULL) + { + *uid_l = (uint32_t) RPC_U32(&msg, 0U); + } + if (uid_h != NULL) + { + *uid_h = (uint32_t) RPC_U32(&msg, 4U); + } + if (lc != NULL) + { + *lc = (uint16_t) RPC_U16(&msg, 8U); + } + if (monotonic != NULL) + { + *monotonic = (uint16_t) RPC_U16(&msg, 10U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 ENABLE_DEBUG(UI64 addr) #18 */ +sc_err_t sc_seco_enable_debug(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_ENABLE_DEBUG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_EVENT(UI8 idx, UO32 event) #19 */ +sc_err_t sc_seco_get_event(sc_ipc_t ipc, uint8_t idx, uint32_t *event) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_GET_EVENT); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(idx); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (event != NULL) + { + *event = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 FUSE_WRITE(UI64 addr) #20 */ +sc_err_t sc_seco_fuse_write(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_FUSE_WRITE); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 PATCH(UI64 addr) #21 */ +sc_err_t sc_seco_patch(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_PATCH); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_MONO_COUNTER_PARTITION(UIO16 she) #28 */ +sc_err_t sc_seco_set_mono_counter_partition(sc_ipc_t ipc, uint16_t *she) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_SET_MONO_COUNTER_PARTITION); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(*she); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + *she = (uint16_t) RPC_U16(&msg, 0U); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_FIPS_MODE(UI8 mode, UO32 reason) #29 */ +sc_err_t sc_seco_set_fips_mode(sc_ipc_t ipc, uint8_t mode, uint32_t *reason) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_SET_FIPS_MODE); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(mode); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (reason != NULL) + { + *reason = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 FIPS_KEY_ZERO(UI64 addr) #31 */ +sc_err_t sc_seco_fips_key_zero(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_FIPS_KEY_ZERO); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 START_RNG(UO32 status) #22 */ +sc_err_t sc_seco_start_rng(sc_ipc_t ipc, sc_seco_rng_stat_t *status) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_START_RNG); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (status != NULL) + { + *status = (sc_seco_rng_stat_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SAB_MSG(UI64 addr) #23 */ +sc_err_t sc_seco_sab_msg(sc_ipc_t ipc, sc_faddr_t addr) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_SAB_MSG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(addr >> 32ULL); + RPC_U32(&msg, 4U) = U32(addr); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SECVIO_ENABLE() #25 */ +sc_err_t sc_seco_secvio_enable(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_SECVIO_ENABLE); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SECVIO_CONFIG(UI8 id, UI8 access, UIO32 data0, UIO32 data1, UIO32 data2, UIO32 data3, UIO32 data4, UI8 size) #26 */ +sc_err_t sc_seco_secvio_config(sc_ipc_t ipc, uint8_t id, uint8_t access, + uint32_t *data0, uint32_t *data1, uint32_t *data2, uint32_t *data3, + uint32_t *data4, uint8_t size) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 7U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_SECVIO_CONFIG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(*data0); + RPC_U32(&msg, 4U) = U32(*data1); + RPC_U32(&msg, 8U) = U32(*data2); + RPC_U32(&msg, 12U) = U32(*data3); + RPC_U32(&msg, 16U) = U32(*data4); + RPC_U8(&msg, 20U) = U8(id); + RPC_U8(&msg, 21U) = U8(access); + RPC_U8(&msg, 22U) = U8(size); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + *data0 = (uint32_t) RPC_U32(&msg, 0U); + *data1 = (uint32_t) RPC_U32(&msg, 4U); + *data2 = (uint32_t) RPC_U32(&msg, 8U); + *data3 = (uint32_t) RPC_U32(&msg, 12U); + *data4 = (uint32_t) RPC_U32(&msg, 16U); + + /* Return result */ + return err; +} + +/* IDL: E8 SECVIO_DGO_CONFIG(UI8 id, UI8 access, UIO32 data) #27 */ +sc_err_t sc_seco_secvio_dgo_config(sc_ipc_t ipc, uint8_t id, uint8_t access, + uint32_t *data) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = U8(SECO_FUNC_SECVIO_DGO_CONFIG); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(*data); + RPC_U8(&msg, 4U) = U8(id); + RPC_U8(&msg, 5U) = U8(access); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + *data = (uint32_t) RPC_U32(&msg, 0U); + + /* Return result */ + return err; +} + +/** @} */ + diff --git a/platform/svc/seco/rpc_srv.c b/platform/svc/seco/rpc_srv.c new file mode 100644 index 0000000..2ca0ed8 --- /dev/null +++ b/platform/svc/seco/rpc_srv.c @@ -0,0 +1,659 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the SECO service. + * + * @addtogroup SECO_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/seco/svc.h" +#include "svc/seco/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void seco_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case SECO_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch image_load() */ + case SECO_FUNC_IMAGE_LOAD : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr_src = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_faddr_t addr_dst = ((sc_faddr_t) RPC_U64(msg, 8U)); + uint32_t len = ((uint32_t) RPC_U32(msg, 16U)); + sc_bool_t fw = U2B(RPC_U8(msg, 20U)); + + /* Call function */ + err = seco_image_load(caller_pt, addr_src, addr_dst, len, fw); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch authenticate() */ + case SECO_FUNC_AUTHENTICATE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_seco_auth_cmd_t cmd = ((sc_seco_auth_cmd_t) RPC_U8(msg, 8U)); + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_authenticate(caller_pt, cmd, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch enh_authenticate() */ + case SECO_FUNC_ENH_AUTHENTICATE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_seco_auth_cmd_t cmd = ((sc_seco_auth_cmd_t) RPC_U8(msg, 16U)); + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + uint32_t mask1 = ((uint32_t) RPC_U32(msg, 8U)); + uint32_t mask2 = ((uint32_t) RPC_U32(msg, 12U)); + + /* Call function */ + err = seco_enh_authenticate(caller_pt, cmd, addr, mask1, mask2); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch forward_lifecycle() */ + case SECO_FUNC_FORWARD_LIFECYCLE : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t change = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = seco_forward_lifecycle(caller_pt, change); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch return_lifecycle() */ + case SECO_FUNC_RETURN_LIFECYCLE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_return_lifecycle(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch commit() */ + case SECO_FUNC_COMMIT : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t info = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = seco_commit(caller_pt, &info); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(info); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch attest_mode() */ + case SECO_FUNC_ATTEST_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t mode = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = seco_attest_mode(caller_pt, mode); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch attest() */ + case SECO_FUNC_ATTEST : + { + /* Declare return and parameters */ + sc_err_t result; + uint64_t nonce = ((uint64_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_attest(caller_pt, nonce); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_attest_pkey() */ + case SECO_FUNC_GET_ATTEST_PKEY : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_get_attest_pkey(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_attest_sign() */ + case SECO_FUNC_GET_ATTEST_SIGN : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_get_attest_sign(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch attest_verify() */ + case SECO_FUNC_ATTEST_VERIFY : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_attest_verify(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch gen_key_blob() */ + case SECO_FUNC_GEN_KEY_BLOB : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t id = ((uint32_t) RPC_U32(msg, 16U)); + sc_faddr_t load_addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + sc_faddr_t export_addr = ((sc_faddr_t) RPC_U64(msg, 8U)); + uint16_t max_size = ((uint16_t) RPC_U16(msg, 20U)); + + /* Call function */ + err = seco_gen_key_blob(caller_pt, id, load_addr, export_addr, + max_size); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch load_key() */ + case SECO_FUNC_LOAD_KEY : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t id = ((uint32_t) RPC_U32(msg, 8U)); + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_load_key(caller_pt, id, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_mp_key() */ + case SECO_FUNC_GET_MP_KEY : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t dst_addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + uint16_t dst_size = ((uint16_t) RPC_U16(msg, 8U)); + + /* Call function */ + err = seco_get_mp_key(caller_pt, dst_addr, dst_size); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch update_mpmr() */ + case SECO_FUNC_UPDATE_MPMR : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + uint8_t size = ((uint8_t) RPC_U8(msg, 8U)); + uint8_t lock = ((uint8_t) RPC_U8(msg, 9U)); + + /* Call function */ + err = seco_update_mpmr(caller_pt, addr, size, lock); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_mp_sign() */ + case SECO_FUNC_GET_MP_SIGN : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t msg_addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + uint16_t msg_size = ((uint16_t) RPC_U16(msg, 16U)); + sc_faddr_t dst_addr = ((sc_faddr_t) RPC_U64(msg, 8U)); + uint16_t dst_size = ((uint16_t) RPC_U16(msg, 18U)); + + /* Call function */ + err = seco_get_mp_sign(caller_pt, msg_addr, msg_size, dst_addr, + dst_size); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch build_info() */ + case SECO_FUNC_BUILD_INFO : + { + /* Declare return and parameters */ + uint32_t version = ((uint32_t) 0U); + uint32_t commit = ((uint32_t) 0U); + + /* Call function */ + seco_build_info(caller_pt, &version, &commit); + + /* Copy in return parameters */ + RPC_U32(msg, 0U) = U32(version); + RPC_U32(msg, 4U) = U32(commit); + RPC_SIZE(msg) = 3U; + break; + } +#ifdef API_HAS_V2X + /* Dispatch v2x_build_info() */ + case SECO_FUNC_V2X_BUILD_INFO : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t version = ((uint32_t) 0U); + uint32_t commit = ((uint32_t) 0U); + + /* Call function */ + err = seco_v2x_build_info(caller_pt, &version, &commit); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(version); + RPC_U32(msg, 4U) = U32(commit); + RPC_SIZE(msg) = 3U; + break; + } +#endif + /* Dispatch chip_info() */ + case SECO_FUNC_CHIP_INFO : + { + /* Declare return and parameters */ + sc_err_t result; + uint16_t lc = ((uint16_t) 0U); + uint16_t monotonic = ((uint16_t) 0U); + uint32_t uid_l = ((uint32_t) 0U); + uint32_t uid_h = ((uint32_t) 0U); + + /* Call function */ + err = seco_chip_info(caller_pt, &lc, &monotonic, &uid_l, + &uid_h); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U16(msg, 8U) = U16(lc); + RPC_U16(msg, 10U) = U16(monotonic); + RPC_U32(msg, 0U) = U32(uid_l); + RPC_U32(msg, 4U) = U32(uid_h); + RPC_SIZE(msg) = 4U; + break; + } + /* Dispatch enable_debug() */ + case SECO_FUNC_ENABLE_DEBUG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_enable_debug(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_event() */ + case SECO_FUNC_GET_EVENT : + { + /* Declare return and parameters */ + sc_err_t result; + uint8_t idx = ((uint8_t) RPC_U8(msg, 0U)); + uint32_t event = ((uint32_t) 0U); + + /* Call function */ + err = seco_get_event(caller_pt, idx, &event); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(event); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch fuse_write() */ + case SECO_FUNC_FUSE_WRITE : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_fuse_write(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch patch() */ + case SECO_FUNC_PATCH : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_patch(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_mono_counter_partition() */ + case SECO_FUNC_SET_MONO_COUNTER_PARTITION : + { + /* Declare return and parameters */ + sc_err_t result; + uint16_t she = ((uint16_t) RPC_U16(msg, 0U)); + + /* Call function */ + err = seco_set_mono_counter_partition(caller_pt, &she); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U16(msg, 0U) = U16(she); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_fips_mode() */ + case SECO_FUNC_SET_FIPS_MODE : + { + /* Declare return and parameters */ + sc_err_t result; + uint8_t mode = ((uint8_t) RPC_U8(msg, 0U)); + uint32_t reason = ((uint32_t) 0U); + + /* Call function */ + err = seco_set_fips_mode(caller_pt, mode, &reason); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(reason); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch fips_key_zero() */ + case SECO_FUNC_FIPS_KEY_ZERO : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_fips_key_zero(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch start_rng() */ + case SECO_FUNC_START_RNG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_seco_rng_stat_t status = ((sc_seco_rng_stat_t) 0U); + + /* Call function */ + err = seco_start_rng(caller_pt, &status); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(status); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch sab_msg() */ + case SECO_FUNC_SAB_MSG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_faddr_t addr = ((sc_faddr_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = seco_sab_msg(caller_pt, addr); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch secvio_enable() */ + case SECO_FUNC_SECVIO_ENABLE : + { + /* Declare return and parameters */ + sc_err_t result; + + /* Call function */ + err = seco_secvio_enable(caller_pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch secvio_config() */ + case SECO_FUNC_SECVIO_CONFIG : + { + /* Declare return and parameters */ + sc_err_t result; + uint8_t id = ((uint8_t) RPC_U8(msg, 20U)); + uint8_t access = ((uint8_t) RPC_U8(msg, 21U)); + uint32_t data0 = ((uint32_t) RPC_U32(msg, 0U)); + uint32_t data1 = ((uint32_t) RPC_U32(msg, 4U)); + uint32_t data2 = ((uint32_t) RPC_U32(msg, 8U)); + uint32_t data3 = ((uint32_t) RPC_U32(msg, 12U)); + uint32_t data4 = ((uint32_t) RPC_U32(msg, 16U)); + uint8_t size = ((uint8_t) RPC_U8(msg, 22U)); + + /* Call function */ + err = seco_secvio_config(caller_pt, id, access, &data0, &data1, + &data2, &data3, &data4, size); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(data0); + RPC_U32(msg, 4U) = U32(data1); + RPC_U32(msg, 8U) = U32(data2); + RPC_U32(msg, 12U) = U32(data3); + RPC_U32(msg, 16U) = U32(data4); + RPC_SIZE(msg) = 6U; + break; + } + /* Dispatch secvio_dgo_config() */ + case SECO_FUNC_SECVIO_DGO_CONFIG : + { + /* Declare return and parameters */ + sc_err_t result; + uint8_t id = ((uint8_t) RPC_U8(msg, 4U)); + uint8_t access = ((uint8_t) RPC_U8(msg, 5U)); + uint32_t data = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = seco_secvio_dgo_config(caller_pt, id, access, &data); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(data); + RPC_SIZE(msg) = 2U; + break; + } + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=seco, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=seco, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/seco/svc.c b/platform/svc/seco/svc.c new file mode 100755 index 0000000..c1a6991 --- /dev/null +++ b/platform/svc/seco/svc.c @@ -0,0 +1,682 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/seco/svc.c + * + * File containing the implementation of the System Controller (SC) + * Security (SECO) function. + * + * @addtogroup SECO_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "svc/seco/svc.h" +#include "svc/rm/svc.h" +#include "ss/inf/inf.h" +#ifdef HAS_SECO +#include "drivers/seco/fsl_seco.h" +#endif +#ifdef HAS_V2X +#include "drivers/v2x/fsl_v2x.h" +#endif +#include "drivers/snvs/fsl_snvs.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* Local Variables */ + +/*--------------------------------------------------------------------------*/ +/* Load a SECO image */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_image_load(sc_rm_pt_t caller_pt, sc_faddr_t addr_src, + sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw) +{ + #ifdef HAS_SECO + SECO_Image_Load(addr_src, addr_dst, len, fw); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Authenticate a SECO image or command */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_authenticate(sc_rm_pt_t caller_pt, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_Authenticate(cmd, addr, 0U, 0U); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Authenticate a SECO image or command (enhanced version) */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_enh_authenticate(sc_rm_pt_t caller_pt, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr, + uint32_t mask1, uint32_t mask2) +{ + #ifdef HAS_SECO + SECO_Authenticate(cmd, addr, mask1, mask2); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Load a SECO key */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_load_key(sc_rm_pt_t caller_pt, uint32_t id, + sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_LoadKey(id, addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Generate key blob */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_gen_key_blob(sc_rm_pt_t caller_pt, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size) +{ + #ifdef HAS_SECO + SECO_GenKeyBlob(id, load_addr, export_addr, max_size); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Secure fuse write command */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_fuse_write(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_SecureWriteFuse(addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Secure patch */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_patch(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_ScuPatch(addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Partition the monotonic counte */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_set_mono_counter_partition(sc_rm_pt_t caller_pt, uint16_t *she) +{ + #ifdef HAS_SECO + sc_err_t err = SC_ERR_NONE; + + /* Check access permissions */ + SYSTEM(caller_pt); + + if (err == SC_ERR_NONE) + { + *she = SECO_SetMonoCounterPartition(*she); + err = seco_err; + } + + return err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Set FIPS mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_set_fips_mode(sc_rm_pt_t caller_pt, uint8_t mode, + uint32_t *reason) +{ + #ifdef HAS_SECO + sc_err_t err = SC_ERR_NONE; + + /* Check access permissions */ + SYSTEM(caller_pt); + + if (err == SC_ERR_NONE) + { + *reason = SECO_SetFipsMode(mode); + err = seco_err; + } + + return err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* zeroize all plaintext secret and private cryptographic keys */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_fips_key_zero(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_FipsKeyZero(addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Start RNG */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_start_rng(sc_rm_pt_t caller_pt, sc_seco_rng_stat_t *status) +{ + #ifdef HAS_SECO + *status = SECO_StartRNG(); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Enabled debug */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_enable_debug(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_EnableDebug(addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Move SECO lifecycle forward */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_forward_lifecycle(sc_rm_pt_t caller_pt, uint32_t change) +{ + #ifdef HAS_SECO + SECO_ForwardLifecycle(change); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Return SECO lifecycle */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_return_lifecycle(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_ReturnLifecycle(addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Return SECO FW build info */ +/*--------------------------------------------------------------------------*/ +void seco_build_info(sc_rm_pt_t caller_pt, uint32_t *version, + uint32_t *commit) +{ + #ifdef HAS_SECO + sc_bool_t dirty; + + /* Return info */ + SECO_Version(version, commit, &dirty); + + if (seco_err != SC_ERR_NONE) + { + *version = 0U; + *commit = 0U; + } + #else + *version = 0U; + *commit = 0U; + #endif +} + +#ifdef API_HAS_V2X +/*--------------------------------------------------------------------------*/ +/* Return V2X FW build info */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_v2x_build_info(sc_rm_pt_t caller_pt, uint32_t *version, + uint32_t *commit) +{ + sc_err_t err = SC_ERR_NONE; + sc_bool_t dirty; + sc_pm_power_mode_t mode = SC_PM_PW_MODE_OFF; + + /* Get V2X power state */ + err = pm_get_resource_power_mode(SC_PT, SC_R_V2X, &mode); + + /* Error? */ + if (err == SC_ERR_NONE) + { + /* V2X on? */ + if (mode > SC_PM_PW_MODE_STBY) + { + V2X_Version(version, commit, &dirty); + if (v2x_err != SC_ERR_NONE) + { + err = v2x_err; + } + } + else + { + /* No power so error */ + err = SC_ERR_NOPOWER; + } + } + + /* Return 0 version on error */ + if (err != SC_ERR_NONE) + { + *version = 0U; + *commit = 0U; + } + + return err; +} +#endif + +/*--------------------------------------------------------------------------*/ +/* Return SECO chip info */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_chip_info(sc_rm_pt_t caller_pt, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h) +{ + #ifdef HAS_SECO + /* Return info */ + SECO_ChipInfo(lc, monotonic, uid_l, uid_h); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Return SECO event */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_get_event(sc_rm_pt_t caller_pt, uint8_t idx, + uint32_t *event) +{ + #ifdef HAS_SECO + /* Return event */ + *event = SECO_GetEvent(idx); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Set the attestation mode */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_attest_mode(sc_rm_pt_t caller_pt, uint32_t mode) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check permissions */ + OWNED(SC_R_ATTESTATION); + + #ifdef HAS_SECO + /* Return info */ + if (err == SC_ERR_NONE) + { + SECO_AttestMode(mode); + err = seco_err; + } + #else + err = SC_ERR_UNAVAILABLE; + #endif + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Request atestation */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_attest(sc_rm_pt_t caller_pt, uint64_t nonce) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check permissions */ + OWNED(SC_R_ATTESTATION); + + #ifdef HAS_SECO + /* Return info */ + if (err == SC_ERR_NONE) + { + SECO_Attest(nonce); + err = seco_err; + } + #else + err = SC_ERR_UNAVAILABLE; + #endif + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Retrieve attestation public key */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_get_attest_pkey(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check permissions */ + OWNED(SC_R_ATTESTATION); + + #ifdef HAS_SECO + /* Return info */ + if (err == SC_ERR_NONE) + { + SECO_GetAttestPublicKey(addr); + err = seco_err; + } + #else + err = SC_ERR_UNAVAILABLE; + #endif + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Retrieve attestation signature and parameters */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_get_attest_sign(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check permissions */ + OWNED(SC_R_ATTESTATION); + + #ifdef HAS_SECO + /* Return info */ + if (err == SC_ERR_NONE) + { + SECO_GetAttestSign(addr); + err = seco_err; + } + #else + err = SC_ERR_UNAVAILABLE; + #endif + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Verify attestation */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_attest_verify(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check permissions */ + OWNED(SC_R_ATTESTATION); + + #ifdef HAS_SECO + /* Return info */ + if (err == SC_ERR_NONE) + { + SECO_AttestVerify(addr); + err = seco_err; + } + #else + err = SC_ERR_UNAVAILABLE; + #endif + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Commit SRK/FW info */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_commit(sc_rm_pt_t caller_pt, uint32_t *info) +{ + #ifdef HAS_SECO + /* Return info */ + SECO_Commit(info); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get manufacturing protection public key */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_get_mp_key(sc_rm_pt_t caller_pt, sc_faddr_t dst_addr, + uint16_t dst_size) +{ + #ifdef HAS_SECO + /* Return info */ + SECO_GetMPKey(dst_addr, dst_size); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Update manufacturing protection message register */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_update_mpmr(sc_rm_pt_t caller_pt, sc_faddr_t addr, + uint8_t size, uint8_t lock) +{ + #ifdef HAS_SECO + /* Return info */ + SECO_UpdateMPMR(addr, size, lock); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Get manufacturing protection signature */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_get_mp_sign(sc_rm_pt_t caller_pt, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size) +{ + #ifdef HAS_SECO + /* Return info */ + SECO_GetMPSign(msg_addr, msg_size, dst_addr, dst_size); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Send a generic signed message to the SECO SHE/HSM components */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_sab_msg(sc_rm_pt_t caller_pt, sc_faddr_t addr) +{ + #ifdef HAS_SECO + SECO_SABSignedMesg(addr); + + return seco_err; + #else + return SC_ERR_UNAVAILABLE; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Enable security violation and tamper interrupts */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_secvio_enable(sc_rm_pt_t caller_pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check permissions */ + OWNED(SC_R_SECVIO); + + /* Return info */ + if (err == SC_ERR_NONE) + { + #if defined(FSL_FEATURE_SOC_SNVS_COUNT) && FSL_FEATURE_SOC_SNVS_COUNT + SNVS_SecurityViolation_Enable(); + err = snvs_err; + #else + err = SC_ERR_UNAVAILABLE; + #endif + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Send a message to SECO to read/write SNVS secvio and tamper registers */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_secvio_config(sc_rm_pt_t caller_pt, uint8_t id, uint8_t access, + uint32_t *data0, uint32_t *data1, uint32_t *data2, uint32_t *data3, + uint32_t *data4, uint8_t size) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check parameters */ + ASRT_ERR(access <= SECO_SNVS_WRITE, SC_ERR_PARM); + ASRT_ERR(size <= 5U, SC_ERR_PARM); + + /* Check permissions */ + OWNED(SC_R_SECVIO); + + /* Return info */ + if (err == SC_ERR_NONE) + { + #if defined(FSL_FEATURE_SOC_SNVS_COUNT) && FSL_FEATURE_SOC_SNVS_COUNT + SNVS_SecVio(id, access, data0, data1, data2, data3, data4, size); + err = snvs_err; + #else + err = SC_ERR_UNAVAILABLE; + #endif + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Send a message to SECO to read/write SNVS secvio and tamper DGO regs */ +/*--------------------------------------------------------------------------*/ +sc_err_t seco_secvio_dgo_config(sc_rm_pt_t caller_pt, uint8_t id, + uint8_t access, uint32_t *data) +{ + sc_err_t err = SC_ERR_NONE; + + /* Check parameters */ + ASRT_ERR(access <= SECO_SNVS_WRITE, SC_ERR_PARM); + + /* Check permissions */ + OWNED(SC_R_SECVIO); + + /* Return info */ + if (err == SC_ERR_NONE) + { + #if defined(FSL_FEATURE_SOC_SNVS_COUNT) && FSL_FEATURE_SOC_SNVS_COUNT + SNVS_SecVioDgo(id, access, data); + err = seco_err; + #else + err = SC_ERR_UNAVAILABLE; + #endif + } + + return err; +} + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Dump SECO state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) && defined(DEBUG_SECO) + void seco_dump(sc_rm_pt_t pt) + { + } +#endif + +/** @} */ + diff --git a/platform/svc/seco/svc.h b/platform/svc/seco/svc.h new file mode 100755 index 0000000..3c9e0f9 --- /dev/null +++ b/platform/svc/seco/svc.h @@ -0,0 +1,328 @@ +/* +** ################################################################### +** +** Copyright 2019-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/seco/svc.h + * + * Header file containing the API for the System Controller (SC) + * Security (SECO) function. + * + * @addtogroup SECO_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_SECO_SVC_H +#define SC_SECO_SVC_H + +/* Includes */ + +#include "svc/seco/api.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * @name Internal Functions + * @{ + */ + +/*! + * Internal SC function to load a SECO image. + * + * @see sc_seco_image_load(). + */ +sc_err_t seco_image_load(sc_rm_pt_t caller_pt, + sc_faddr_t addr_src, sc_faddr_t addr_dst, uint32_t len, sc_bool_t fw); + +/*! + * Internal SC function to authenticate a SECO image or command. + * + * @see sc_seco_authenticate(). + */ +sc_err_t seco_authenticate(sc_rm_pt_t caller_pt, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr); + +/*! + * Internal SC function to authenticate a SECO image or command + ( (enhanced version). + * + * @see sc_seco_enh_authenticate(). + */ +sc_err_t seco_enh_authenticate(sc_rm_pt_t caller_pt, + sc_seco_auth_cmd_t cmd, sc_faddr_t addr, + uint32_t mask1, uint32_t mask2); + +/*! + * Internal SC function to load a SECO key. + * + * @see sc_seco_load_key(). + */ +sc_err_t seco_load_key(sc_rm_pt_t caller_pt, + uint32_t id, sc_faddr_t addr); + +/*! + * Internal SC function to generate a key blob. + * + * @see sc_seco_gen_key_blob(). + */ +sc_err_t seco_gen_key_blob(sc_rm_pt_t caller_pt, uint32_t id, + sc_faddr_t load_addr, sc_faddr_t export_addr, uint16_t max_size); + +/*! + * Internal SC function to securely write a group of fuse words. + * + * @see sc_seco_fuse_write(). + */ +sc_err_t seco_fuse_write(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to apply a patch. + * + * @see sc_seco_patch(). + */ +sc_err_t seco_patch(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to partition the monotonic counter. + * + * @see sc_seco_set_mono_counter_partition(). + */ +sc_err_t seco_set_mono_counter_partition(sc_rm_pt_t caller_pt, + uint16_t *she); + +/*! + * Internal SC function to set FIPS mode. + * + * @see sc_seco_set_fips_mode(). + */ +sc_err_t seco_set_fips_mode(sc_rm_pt_t caller_pt, uint8_t mode, + uint32_t *reason); + +/*! + * Internal SC function to securely zeroize all plaintext secret and private + * cryptographic keys and CSPs within the module. + * + * @see sc_seco_fips_key_zero(). + */ +sc_err_t seco_fips_key_zero(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to start the RNG. + * + * @see sc_seco_start_rng(). + */ +sc_err_t seco_start_rng(sc_rm_pt_t caller_pt, sc_seco_rng_stat_t *status); + +/*! + * Internal SC function to securely enable debug. + * + * @see sc_seco_enabled_debug(). + */ +sc_err_t seco_enable_debug(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to update the lifecycle. + * + * @see sc_seco_forward_lifecycle(). + */ +sc_err_t seco_forward_lifecycle(sc_rm_pt_t caller_pt, uint32_t change); + +/*! + * Internal SC function to securely reverse the lifecycle. + * + * @see sc_seco_return_lifecycle(). + */ +sc_err_t seco_return_lifecycle(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to return SECO FW version info. + * + * @see sc_seco_build_info(). + */ +void seco_build_info(sc_rm_pt_t caller_pt, uint32_t *version, + uint32_t *commit); + +#ifdef API_HAS_V2X +/*! + * Internal SC function to return V2X FW version info. + * + * @see sc_seco_v2x_build_info(). + */ +sc_err_t seco_v2x_build_info(sc_rm_pt_t caller_pt, uint32_t *version, + uint32_t *commit); +#endif + +/*! + * Internal SC function to return SECO chip info. + * + * @see sc_seco_chip_info(). + */ +sc_err_t seco_chip_info(sc_rm_pt_t caller_pt, uint16_t *lc, + uint16_t *monotonic, uint32_t *uid_l, uint32_t *uid_h); + +/*! + * Internal SC function to return an event from the SECO error log. + * + * @see sc_seco_get_event(). + */ +sc_err_t seco_get_event(sc_rm_pt_t caller_pt, uint8_t idx, + uint32_t *event); + +/*! + * Internal SC function to set the attestation mode. + * + * @see sc_seco_attest_mode(). + */ +sc_err_t seco_attest_mode(sc_rm_pt_t caller_pt, uint32_t mode); + +/*! + * Internal SC function to request atestation. + * + * @see sc_seco_attest(). + */ +sc_err_t seco_attest(sc_rm_pt_t caller_pt, uint64_t nonce); + +/*! + * Internal SC function to retrieve attestation public key. + * + * @see sc_seco_get_attest_pkey(). + */ +sc_err_t seco_get_attest_pkey(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to retrieve attestation signature and parameters. + * + * @see sc_seco_get_attest_sign(). + */ +sc_err_t seco_get_attest_sign(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to verify attestation. + * + * @see sc_seco_attest_verify(). + */ +sc_err_t seco_attest_verify(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to commit SRK/FW changes. + * + * @see sc_seco_commit(). + */ +sc_err_t seco_commit(sc_rm_pt_t caller_pt, uint32_t *info); + +/** @} */ + +/*! + * Internal SC function to get manufacturing protection public key. + * + * @see sc_seco_get_mp_key(). + */ +sc_err_t seco_get_mp_key(sc_rm_pt_t caller_pt, sc_faddr_t dst_addr, + uint16_t dst_size); + +/*! + * Internal SC function to update manufacturing protection message register. + * + * @see sc_seco_update_mpmr(). + */ +sc_err_t seco_update_mpmr(sc_rm_pt_t caller_pt, sc_faddr_t addr, + uint8_t size, uint8_t lock); + +/*! + * Internal SC function to get manufacturing protection signature. + * + * @see sc_seco_get_mp_sign(). + */ +sc_err_t seco_get_mp_sign(sc_rm_pt_t caller_pt, sc_faddr_t msg_addr, + uint16_t msg_size, sc_faddr_t dst_addr, uint16_t dst_size); + +/*! + * Internal SC function to send a generic signed message to the + * SECO SHE/HSM components. + * + * @see sc_seco_sab_msg(). + */ +sc_err_t seco_sab_msg(sc_rm_pt_t caller_pt, sc_faddr_t addr); + +/*! + * Internal SC function to enable the security violation interrupt. + * + * @see sc_seco_secvio_enable(). + */ +sc_err_t seco_secvio_enable(sc_rm_pt_t caller_pt); + +/*! + * Internal SC function to read/write SNVS security violation + * and tamper registers. + * + * @see sc_seco_secvio_config(). + */ +sc_err_t seco_secvio_config(sc_rm_pt_t caller_pt, uint8_t id, uint8_t access, + uint32_t *data0, uint32_t *data1, uint32_t *data2, uint32_t *data3, + uint32_t *data4, uint8_t size); + +/*! + * Internal SC function to read/write SNVS security violation + * and tamper DGO registers. + * + * @see sc_seco_secvio_dgo_config(). + */ +sc_err_t seco_secvio_dgo_config(sc_rm_pt_t caller_pt, uint8_t id, + uint8_t access, uint32_t *data); + +#if defined(DEBUG) && defined(DEBUG_SECO) + /*! + * @name Debug Functions + * @{ + */ + + /*! + * Internal SC function to dump the internal state of the SECO service. + * + * @param[in] pt partition to dump + */ + void seco_dump(sc_rm_pt_t pt); + + /** @} */ +#endif + +#endif /* SC_SECO_SVC_H */ + +/** @} */ + diff --git a/platform/svc/timer/Makefile b/platform/svc/timer/Makefile new file mode 100755 index 0000000..c8559ad --- /dev/null +++ b/platform/svc/timer/Makefile @@ -0,0 +1,17 @@ + +OBJS += $(OUT)/svc/timer/svc.o + +RPCS += $(OUT)/svc/timer/rpc_srv.o + +RPCL += $(OUT)/svc/timer/rpc_clnt.o + +RPCH += $(SRC)/svc/timer/rpc.h + +RPCC += $(SRC)/svc/timer/rpc_srv.c \ + $(SRC)/svc/timer/rpc_clnt.c \ + $(SRC)/svc/timer/rpc_xlate.c + +RPCHDR += $(SRC)/svc/timer/rpc_header.h + +DIRS += $(OUT)/svc/timer + diff --git a/platform/svc/timer/api.h b/platform/svc/timer/api.h new file mode 100755 index 0000000..7b2902a --- /dev/null +++ b/platform/svc/timer/api.h @@ -0,0 +1,440 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/timer/api.h + * + * Header file containing the public API for the System Controller (SC) + * Timer function. + * + * @addtogroup TIMER_SVC TIMER: Timer Service + * + * @brief Module for the Timer service. This includes support for the watchdog, RTC, + * and system counter. Note every resource partition has a watchdog it can + * use. + * + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" + +/* Defines */ + +/*! + * @name Defines for type widths + */ +/** @{ */ +#define SC_TIMER_ACTION_W 3U /*!< Width of sc_timer_wdog_action_t */ +/** @} */ + +/*! + * @name Defines for sc_timer_wdog_action_t + */ +/** @{ */ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /*!< Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /*!< Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /*!< Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /*!< Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /*!< Only generate IRQs */ +/** @} */ + +/* Types */ + +/*! + * This type is used to configure the watchdog action. + */ +typedef uint8_t sc_timer_wdog_action_t; + +/*! + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef uint32_t sc_timer_wdog_time_t; + +/* Functions */ + +/*! + * @name Watchdog Functions + * @{ + */ + +/*! + * This function sets the watchdog timeout in milliseconds. If not + * set then the timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] timeout timeout period for the watchdog + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +/* IDL: E8 SET_WDOG_TIMEOUT(UI32 timeout) #1 */ +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t timeout); + +/*! + * This function sets the watchdog pre-timeout in milliseconds. If not + * set then the pre-timeout defaults to the max. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] pre_timeout pre-timeout period for the watchdog + * + * When the pre-timout expires an IRQ will be generated. Note this timeout + * clears when the IRQ is triggered. An IRQ is generated for the failing + * partition and all of its child partitions. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 SET_WDOG_PRE_TIMEOUT(UI32 pre_timeout) #12 */ +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout); + +/*! + * This function sets the watchdog window in milliseconds. If not + * set then the window defaults to the 0. Once locked this value + * cannot be changed. + * + * @param[in] ipc IPC handle + * @param[in] window window period for the watchdog + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + * + * Calling sc_timer_ping_wdog() before the window time has expired will + * result in the watchdog action being taken. + */ +/* IDL: E8 SET_WDOG_WINDOW(UI32 window) #19 */ +sc_err_t sc_timer_set_wdog_window(sc_ipc_t ipc, + sc_timer_wdog_time_t window); + +/*! + * This function starts the watchdog. + * + * @param[in] ipc IPC handle + * @param[in] lock boolean indicating the lock status + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_NOACCESS if caller's partition is not isolated, + * - SC_ERR_BUSY if already started + * + * If \a lock is set then the watchdog cannot be stopped or the timeout + * period changed. + * + * If the calling partition is not isolated then the wdog cannot be used. + * This is always the case if a non-secure partition is running on the same + * CPU as a secure partition (e.g. Linux under TZ). See sc_rm_partition_alloc(). + */ +/* IDL: E8 START_WDOG(IB lock) #2 */ +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock); + +/*! + * This function stops the watchdog if it is not locked. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_LOCKED + * = locked). + */ +/* IDL: E8 STOP_WDOG() #3 */ +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc); + +/*! + * This function pings (services, kicks) the watchdog resetting the time + * before expiration back to the timeout. + * + * @param[in] ipc IPC handle + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 PING_WDOG() #4 */ +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc); + +/*! + * This function gets the status of the watchdog. All arguments are + * in milliseconds. + * + * @param[in] ipc IPC handle + * @param[out] timeout pointer to return the timeout + * @param[out] max_timeout pointer to return the max timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 GET_WDOG_STATUS(UO32 timeout, UO32 max_timeout, UO32 remaining_time) #5 */ +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * This function gets the status of the watchdog of a partition. All + * arguments are in milliseconds. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to query + * @param[out] enb pointer to return enable status + * @param[out] timeout pointer to return the timeout + * @param[out] remaining_time pointer to return the time remaining + * until trigger + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 PT_GET_WDOG_STATUS(UI8 pt, OB enb, UO32 timeout, UO32 remaining_time) #13 */ +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time); + +/*! + * This function configures the action to be taken when a watchdog + * expires. + * + * @param[in] ipc IPC handle + * @param[in] pt partition to affect + * @param[in] action action to take + * + * Default action is inherited from the parent. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid parameters, + * - SC_ERR_NOACCESS if caller's partition is not the SYSTEM owner, + * - SC_ERR_LOCKED if the watchdog is locked + */ +/* IDL: E8 SET_WDOG_ACTION(UI8 pt, UI8 action) #10 */ +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, + sc_rm_pt_t pt, sc_timer_wdog_action_t action); + +/** @} */ + +/*! + * @name Real-Time Clock (RTC) Functions + * @{ + */ + +/*! + * This function sets the RTC time. Only the owner of the SC_R_SYSTEM + * resource or a partition with access permissions to SC_R_SYSTEM can + * set the time. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters, + * - SC_ERR_NOACCESS if caller's partition cannot access SC_R_SYSTEM + */ +/* IDL: E8 SET_RTC_TIME(UI16 year, UI8 mon, UI8 day, UI8 hour, UI8 min, UI8 sec) #6 */ +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * This function gets the RTC time. + * + * @param[in] ipc IPC handle + * @param[out] year pointer to return year (min 1970) + * @param[out] mon pointer to return month (1-12) + * @param[out] day pointer to return day of the month (1-31) + * @param[out] hour pointer to return hour (0-23) + * @param[out] min pointer to return minute (0-59) + * @param[out] sec pointer to return second (0-59) + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 GET_RTC_TIME(UO16 year, UO8 mon, UO8 day, UO8 hour, UO8 min, UO8 sec) #7 */ +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec); + +/*! + * This function gets the RTC time in seconds since 1/1/1970. + * + * @param[in] ipc IPC handle + * @param[out] sec pointer to return seconds + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 GET_RTC_SEC1970(UO32 sec) #9 */ +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec); + +/*! + * This function sets the RTC alarm. + * + * @param[in] ipc IPC handle + * @param[in] year year (min 1970) + * @param[in] mon month (1-12) + * @param[in] day day of the month (1-31) + * @param[in] hour hour (0-23) + * @param[in] min minute (0-59) + * @param[in] sec second (0-59) + * + * Note this alarm setting clears when the alarm is triggered. This is an + * absolute time. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +/* IDL: E8 SET_RTC_ALARM(UI16 year, UI8 mon, UI8 day, UI8 hour, UI8 min, UI8 sec) #8 */ +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * This function sets the RTC alarm (periodic mode). + * + * @param[in] ipc IPC handle + * @param[in] sec period in seconds + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Note this is a relative time. + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +/* IDL: E8 SET_RTC_PERIODIC_ALARM(UI32 sec) #14 */ +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec); + +/*! + * This function cancels the RTC alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +/* IDL: E8 CANCEL_RTC_ALARM() #15 */ +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc); + +/*! + * This function sets the RTC calibration value. Only the owner of the SC_R_SYSTEM + * resource or a partition with access permissions to SC_R_SYSTEM can set the + * calibration. + * + * @param[in] ipc IPC handle + * @param[in] count calibration count (-16 to 15) + * + * The calibration value is a 5-bit value including the sign bit, which is + * implemented in 2's complement. It is added or subtracted from the RTC on + * a periodic basis, once per 32768 cycles of the RTC clock. + * + * @return Returns an error code (SC_ERR_NONE = success). + */ +/* IDL: E8 SET_RTC_CALB(I8 count) #11 */ +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count); + +/** @} */ + +/*! + * @name System Counter (SYSCTR) Functions + * @{ + */ + +/*! + * This function sets the SYSCTR alarm. + * + * @param[in] ipc IPC handle + * @param[in] ticks number of 8MHz cycles + * + * Note the \a ticks parameter is an absolute time. This alarm + * setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +/* IDL: E8 SET_SYSCTR_ALARM(UI64 ticks) #16 */ +sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks); + +/*! + * This function sets the SYSCTR alarm (periodic mode). + * + * @param[in] ipc IPC handle + * @param[in] ticks number of 8MHz cycles + * + * Note the \a ticks parameter is a relative time. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +/* IDL: E8 SET_SYSCTR_PERIODIC_ALARM(UI64 ticks) #17 */ +sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, + uint64_t ticks); + +/*! + * This function cancels the SYSCTR alarm. + * + * @param[in] ipc IPC handle + * + * Note this alarm setting clears when the alarm is triggered. + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Return errors: + * - SC_ERR_PARM if invalid time/date parameters + */ +/* IDL: E8 CANCEL_SYSCTR_ALARM() #18 */ +sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc); + +/** @} */ + +#endif /* SC_TIMER_API_H */ + +/** @} */ + diff --git a/platform/svc/timer/rpc.h b/platform/svc/timer/rpc.h new file mode 100644 index 0000000..00c855f --- /dev/null +++ b/platform/svc/timer/rpc.h @@ -0,0 +1,98 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file for the TIMER RPC implementation. + * + * @addtogroup TIMER_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_h.pl */ + +#ifndef SC_TIMER_RPC_H +#define SC_TIMER_RPC_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Defines for RPC TIMER function calls + */ +/** @{ */ +#define TIMER_FUNC_UNKNOWN 0 /*!< Unknown function */ +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /*!< Index for sc_timer_set_wdog_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /*!< Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_WINDOW 19U /*!< Index for sc_timer_set_wdog_window() RPC call */ +#define TIMER_FUNC_START_WDOG 2U /*!< Index for sc_timer_start_wdog() RPC call */ +#define TIMER_FUNC_STOP_WDOG 3U /*!< Index for sc_timer_stop_wdog() RPC call */ +#define TIMER_FUNC_PING_WDOG 4U /*!< Index for sc_timer_ping_wdog() RPC call */ +#define TIMER_FUNC_GET_WDOG_STATUS 5U /*!< Index for sc_timer_get_wdog_status() RPC call */ +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /*!< Index for sc_timer_pt_get_wdog_status() RPC call */ +#define TIMER_FUNC_SET_WDOG_ACTION 10U /*!< Index for sc_timer_set_wdog_action() RPC call */ +#define TIMER_FUNC_SET_RTC_TIME 6U /*!< Index for sc_timer_set_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_TIME 7U /*!< Index for sc_timer_get_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_SEC1970 9U /*!< Index for sc_timer_get_rtc_sec1970() RPC call */ +#define TIMER_FUNC_SET_RTC_ALARM 8U /*!< Index for sc_timer_set_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /*!< Index for sc_timer_set_rtc_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /*!< Index for sc_timer_cancel_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_CALB 11U /*!< Index for sc_timer_set_rtc_calb() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /*!< Index for sc_timer_set_sysctr_alarm() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /*!< Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /*!< Index for sc_timer_cancel_sysctr_alarm() RPC call */ +/** @} */ + +/* Types */ + +/* Functions */ + +/*! + * This function dispatches an incoming TIMER RPC request. + * + * @param[in] caller_pt caller partition + * @param[in] mu MU message came from + * @param[in] msg pointer to RPC message + */ +void timer_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg); + +#endif /* SC_TIMER_RPC_H */ + +/** @} */ + diff --git a/platform/svc/timer/rpc_clnt.c b/platform/svc/timer/rpc_clnt.c new file mode 100644 index 0000000..7d2c5b8 --- /dev/null +++ b/platform/svc/timer/rpc_clnt.c @@ -0,0 +1,599 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing client-side RPC functions for the TIMER service. These + * functions are ported to clients that communicate to the SC. + * + * @addtogroup TIMER_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_clnt_c.pl */ + +/* Includes */ + +#include "main/types.h" +#include "svc/rm/api.h" +#include "svc/timer/api.h" +#include "../../main/rpc.h" +#include "svc/timer/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/* Local Functions */ + +/* IDL: E8 SET_WDOG_TIMEOUT(UI32 timeout) #1 */ +sc_err_t sc_timer_set_wdog_timeout(sc_ipc_t ipc, sc_timer_wdog_time_t timeout) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_TIMEOUT); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(timeout); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_WDOG_PRE_TIMEOUT(UI32 pre_timeout) #12 */ +sc_err_t sc_timer_set_wdog_pre_timeout(sc_ipc_t ipc, + sc_timer_wdog_time_t pre_timeout) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_PRE_TIMEOUT); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(pre_timeout); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_WDOG_WINDOW(UI32 window) #19 */ +sc_err_t sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_WINDOW); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(window); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 START_WDOG(IB lock) #2 */ +sc_err_t sc_timer_start_wdog(sc_ipc_t ipc, sc_bool_t lock) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_START_WDOG); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = B2U8(lock); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 STOP_WDOG() #3 */ +sc_err_t sc_timer_stop_wdog(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_STOP_WDOG); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 PING_WDOG() #4 */ +sc_err_t sc_timer_ping_wdog(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_PING_WDOG); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_WDOG_STATUS(UO32 timeout, UO32 max_timeout, UO32 remaining_time) #5 */ +sc_err_t sc_timer_get_wdog_status(sc_ipc_t ipc, sc_timer_wdog_time_t *timeout, + sc_timer_wdog_time_t *max_timeout, sc_timer_wdog_time_t *remaining_time) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_WDOG_STATUS); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (timeout != NULL) + { + *timeout = (sc_timer_wdog_time_t) RPC_U32(&msg, 0U); + } + if (max_timeout != NULL) + { + *max_timeout = (sc_timer_wdog_time_t) RPC_U32(&msg, 4U); + } + if (remaining_time != NULL) + { + *remaining_time = (sc_timer_wdog_time_t) RPC_U32(&msg, 8U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 PT_GET_WDOG_STATUS(UI8 pt, OB enb, UO32 timeout, UO32 remaining_time) #13 */ +sc_err_t sc_timer_pt_get_wdog_status(sc_ipc_t ipc, sc_rm_pt_t pt, sc_bool_t *enb, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *remaining_time) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_PT_GET_WDOG_STATUS); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (timeout != NULL) + { + *timeout = (sc_timer_wdog_time_t) RPC_U32(&msg, 0U); + } + if (remaining_time != NULL) + { + *remaining_time = (sc_timer_wdog_time_t) RPC_U32(&msg, 4U); + } + if (enb != NULL) + { + *enb = (sc_bool_t) U2B(RPC_U8(&msg, 8U)); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_WDOG_ACTION(UI8 pt, UI8 action) #10 */ +sc_err_t sc_timer_set_wdog_action(sc_ipc_t ipc, sc_rm_pt_t pt, + sc_timer_wdog_action_t action) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_WDOG_ACTION); + + /* Fill in send message */ + RPC_U8(&msg, 0U) = U8(pt); + RPC_U8(&msg, 1U) = U8(action); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RTC_TIME(UI16 year, UI8 mon, UI8 day, UI8 hour, UI8 min, UI8 sec) #6 */ +sc_err_t sc_timer_set_rtc_time(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_TIME); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(year); + RPC_U8(&msg, 2U) = U8(mon); + RPC_U8(&msg, 3U) = U8(day); + RPC_U8(&msg, 4U) = U8(hour); + RPC_U8(&msg, 5U) = U8(min); + RPC_U8(&msg, 6U) = U8(sec); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 GET_RTC_TIME(UO16 year, UO8 mon, UO8 day, UO8 hour, UO8 min, UO8 sec) #7 */ +sc_err_t sc_timer_get_rtc_time(sc_ipc_t ipc, uint16_t *year, uint8_t *mon, + uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_TIME); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (year != NULL) + { + *year = (uint16_t) RPC_U16(&msg, 0U); + } + if (mon != NULL) + { + *mon = (uint8_t) RPC_U8(&msg, 2U); + } + if (day != NULL) + { + *day = (uint8_t) RPC_U8(&msg, 3U); + } + if (hour != NULL) + { + *hour = (uint8_t) RPC_U8(&msg, 4U); + } + if (min != NULL) + { + *min = (uint8_t) RPC_U8(&msg, 5U); + } + if (sec != NULL) + { + *sec = (uint8_t) RPC_U8(&msg, 6U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 GET_RTC_SEC1970(UO32 sec) #9 */ +sc_err_t sc_timer_get_rtc_sec1970(sc_ipc_t ipc, uint32_t *sec) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_GET_RTC_SEC1970); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Copy out receive message */ + if (sec != NULL) + { + *sec = (uint32_t) RPC_U32(&msg, 0U); + } + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RTC_ALARM(UI16 year, UI8 mon, UI8 day, UI8 hour, UI8 min, UI8 sec) #8 */ +sc_err_t sc_timer_set_rtc_alarm(sc_ipc_t ipc, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_ALARM); + + /* Fill in send message */ + RPC_U16(&msg, 0U) = U16(year); + RPC_U8(&msg, 2U) = U8(mon); + RPC_U8(&msg, 3U) = U8(day); + RPC_U8(&msg, 4U) = U8(hour); + RPC_U8(&msg, 5U) = U8(min); + RPC_U8(&msg, 6U) = U8(sec); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RTC_PERIODIC_ALARM(UI32 sec) #14 */ +sc_err_t sc_timer_set_rtc_periodic_alarm(sc_ipc_t ipc, uint32_t sec) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_PERIODIC_ALARM); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(sec); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 CANCEL_RTC_ALARM() #15 */ +sc_err_t sc_timer_cancel_rtc_alarm(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_RTC_ALARM); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_RTC_CALB(I8 count) #11 */ +sc_err_t sc_timer_set_rtc_calb(sc_ipc_t ipc, int8_t count) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_RTC_CALB); + + /* Fill in send message */ + RPC_I8(&msg, 0U) = I8(count); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_SYSCTR_ALARM(UI64 ticks) #16 */ +sc_err_t sc_timer_set_sysctr_alarm(sc_ipc_t ipc, uint64_t ticks) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_ALARM); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(ticks >> 32ULL); + RPC_U32(&msg, 4U) = U32(ticks); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 SET_SYSCTR_PERIODIC_ALARM(UI64 ticks) #17 */ +sc_err_t sc_timer_set_sysctr_periodic_alarm(sc_ipc_t ipc, uint64_t ticks) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 3U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM); + + /* Fill in send message */ + RPC_U32(&msg, 0U) = U32(ticks >> 32ULL); + RPC_U32(&msg, 4U) = U32(ticks); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/* IDL: E8 CANCEL_SYSCTR_ALARM() #18 */ +sc_err_t sc_timer_cancel_sysctr_alarm(sc_ipc_t ipc) +{ + sc_rpc_msg_t msg; + sc_err_t err; + + /* Fill in header */ + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = U8(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = U8(TIMER_FUNC_CANCEL_SYSCTR_ALARM); + + /* Call RPC */ + sc_call_rpc(ipc, &msg, SC_FALSE); + + /* Copy out result */ + err = (sc_err_t) RPC_R8(&msg); + + /* Return result */ + return err; +} + +/** @} */ + diff --git a/platform/svc/timer/rpc_srv.c b/platform/svc/timer/rpc_srv.c new file mode 100644 index 0000000..c30f746 --- /dev/null +++ b/platform/svc/timer/rpc_srv.c @@ -0,0 +1,448 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * File containing server-side RPC functions for the TIMER service. + * + * @addtogroup TIMER_SVC + * @{ + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by bin/perl/rpc_srv_c.pl */ + +/* Includes */ + +#include "main/scfw.h" +#include "main/types.h" +#include "main/main.h" +#include "main/rpc.h" +#include "svc/timer/svc.h" +#include "svc/timer/rpc.h" + +/* Local Defines */ + +/* Local Types */ + +/*--------------------------------------------------------------------------*/ +/* Dispatch incoming RPC function call */ +/*--------------------------------------------------------------------------*/ +void timer_dispatch(sc_rm_pt_t caller_pt, sc_rsrc_t mu, sc_rpc_msg_t *msg) +{ + uint8_t func = RPC_FUNC(msg); + sc_err_t err = SC_ERR_NONE; + + switch (func) + { + /* Handle uknown function */ + case TIMER_FUNC_UNKNOWN : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + /* Dispatch set_wdog_timeout() */ + case TIMER_FUNC_SET_WDOG_TIMEOUT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_timer_wdog_time_t timeout = ((sc_timer_wdog_time_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = timer_set_wdog_timeout(caller_pt, timeout); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_wdog_pre_timeout() */ + case TIMER_FUNC_SET_WDOG_PRE_TIMEOUT : + { + /* Declare return and parameters */ + sc_err_t result; + sc_timer_wdog_time_t pre_timeout = ((sc_timer_wdog_time_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = timer_set_wdog_pre_timeout(caller_pt, pre_timeout); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_wdog_window() */ + case TIMER_FUNC_SET_WDOG_WINDOW : + { + /* Declare return and parameters */ + sc_err_t result; + sc_timer_wdog_time_t window = ((sc_timer_wdog_time_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = timer_set_wdog_window(caller_pt, window); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch start_wdog() */ + case TIMER_FUNC_START_WDOG : + { + /* Declare return and parameters */ + sc_err_t result; + sc_bool_t lock = U2B(RPC_U8(msg, 0U)); + + /* Call function */ + err = timer_start_wdog(caller_pt, lock); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch stop_wdog() */ + case TIMER_FUNC_STOP_WDOG : + { + /* Declare return and parameters */ + sc_err_t result; + + /* Call function */ + err = timer_stop_wdog(caller_pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch ping_wdog() */ + case TIMER_FUNC_PING_WDOG : + { + /* Declare return and parameters */ + sc_err_t result; + + /* Call function */ + err = timer_ping_wdog(caller_pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_wdog_status() */ + case TIMER_FUNC_GET_WDOG_STATUS : + { + /* Declare return and parameters */ + sc_err_t result; + sc_timer_wdog_time_t timeout = ((sc_timer_wdog_time_t) 0U); + sc_timer_wdog_time_t max_timeout = ((sc_timer_wdog_time_t) 0U); + sc_timer_wdog_time_t remaining_time = ((sc_timer_wdog_time_t) 0U); + + /* Call function */ + err = timer_get_wdog_status(caller_pt, &timeout, &max_timeout, + &remaining_time); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(timeout); + RPC_U32(msg, 4U) = U32(max_timeout); + RPC_U32(msg, 8U) = U32(remaining_time); + RPC_SIZE(msg) = 4U; + break; + } + /* Dispatch pt_get_wdog_status() */ + case TIMER_FUNC_PT_GET_WDOG_STATUS : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_bool_t enb = SC_FALSE; + sc_timer_wdog_time_t timeout = ((sc_timer_wdog_time_t) 0U); + sc_timer_wdog_time_t remaining_time = ((sc_timer_wdog_time_t) 0U); + + /* Call function */ + err = timer_pt_get_wdog_status(caller_pt, pt, &enb, &timeout, + &remaining_time); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U8(msg, 8U) = B2U8(enb); + RPC_U32(msg, 0U) = U32(timeout); + RPC_U32(msg, 4U) = U32(remaining_time); + RPC_SIZE(msg) = 4U; + break; + } + /* Dispatch set_wdog_action() */ + case TIMER_FUNC_SET_WDOG_ACTION : + { + /* Declare return and parameters */ + sc_err_t result; + sc_rm_pt_t pt = ((sc_rm_pt_t) RPC_U8(msg, 0U)); + sc_timer_wdog_action_t action = ((sc_timer_wdog_action_t) RPC_U8(msg, 1U)); + + /* Call function */ + err = timer_set_wdog_action(caller_pt, pt, action); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_rtc_time() */ + case TIMER_FUNC_SET_RTC_TIME : + { + /* Declare return and parameters */ + sc_err_t result; + uint16_t year = ((uint16_t) RPC_U16(msg, 0U)); + uint8_t mon = ((uint8_t) RPC_U8(msg, 2U)); + uint8_t day = ((uint8_t) RPC_U8(msg, 3U)); + uint8_t hour = ((uint8_t) RPC_U8(msg, 4U)); + uint8_t min = ((uint8_t) RPC_U8(msg, 5U)); + uint8_t sec = ((uint8_t) RPC_U8(msg, 6U)); + + /* Call function */ + err = timer_set_rtc_time(caller_pt, year, mon, day, hour, min, + sec); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch get_rtc_time() */ + case TIMER_FUNC_GET_RTC_TIME : + { + /* Declare return and parameters */ + sc_err_t result; + uint16_t year = ((uint16_t) 0U); + uint8_t mon = ((uint8_t) 0U); + uint8_t day = ((uint8_t) 0U); + uint8_t hour = ((uint8_t) 0U); + uint8_t min = ((uint8_t) 0U); + uint8_t sec = ((uint8_t) 0U); + + /* Call function */ + err = timer_get_rtc_time(caller_pt, &year, &mon, &day, &hour, + &min, &sec); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U16(msg, 0U) = U16(year); + RPC_U8(msg, 2U) = U8(mon); + RPC_U8(msg, 3U) = U8(day); + RPC_U8(msg, 4U) = U8(hour); + RPC_U8(msg, 5U) = U8(min); + RPC_U8(msg, 6U) = U8(sec); + RPC_SIZE(msg) = 3U; + break; + } + /* Dispatch get_rtc_sec1970() */ + case TIMER_FUNC_GET_RTC_SEC1970 : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t sec = ((uint32_t) 0U); + + /* Call function */ + err = timer_get_rtc_sec1970(caller_pt, &sec); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_U32(msg, 0U) = U32(sec); + RPC_SIZE(msg) = 2U; + break; + } + /* Dispatch set_rtc_alarm() */ + case TIMER_FUNC_SET_RTC_ALARM : + { + /* Declare return and parameters */ + sc_err_t result; + uint16_t year = ((uint16_t) RPC_U16(msg, 0U)); + uint8_t mon = ((uint8_t) RPC_U8(msg, 2U)); + uint8_t day = ((uint8_t) RPC_U8(msg, 3U)); + uint8_t hour = ((uint8_t) RPC_U8(msg, 4U)); + uint8_t min = ((uint8_t) RPC_U8(msg, 5U)); + uint8_t sec = ((uint8_t) RPC_U8(msg, 6U)); + + /* Call function */ + err = timer_set_rtc_alarm(caller_pt, year, mon, day, hour, min, + sec); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_rtc_periodic_alarm() */ + case TIMER_FUNC_SET_RTC_PERIODIC_ALARM : + { + /* Declare return and parameters */ + sc_err_t result; + uint32_t sec = ((uint32_t) RPC_U32(msg, 0U)); + + /* Call function */ + err = timer_set_rtc_periodic_alarm(caller_pt, sec); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch cancel_rtc_alarm() */ + case TIMER_FUNC_CANCEL_RTC_ALARM : + { + /* Declare return and parameters */ + sc_err_t result; + + /* Call function */ + err = timer_cancel_rtc_alarm(caller_pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_rtc_calb() */ + case TIMER_FUNC_SET_RTC_CALB : + { + /* Declare return and parameters */ + sc_err_t result; + int8_t count = ((int8_t) RPC_I8(msg, 0U)); + + /* Call function */ + err = timer_set_rtc_calb(caller_pt, count); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_sysctr_alarm() */ + case TIMER_FUNC_SET_SYSCTR_ALARM : + { + /* Declare return and parameters */ + sc_err_t result; + uint64_t ticks = ((uint64_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = timer_set_sysctr_alarm(caller_pt, ticks); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch set_sysctr_periodic_alarm() */ + case TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM : + { + /* Declare return and parameters */ + sc_err_t result; + uint64_t ticks = ((uint64_t) RPC_U64(msg, 0U)); + + /* Call function */ + err = timer_set_sysctr_periodic_alarm(caller_pt, ticks); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Dispatch cancel_sysctr_alarm() */ + case TIMER_FUNC_CANCEL_SYSCTR_ALARM : + { + /* Declare return and parameters */ + sc_err_t result; + + /* Call function */ + err = timer_cancel_sysctr_alarm(caller_pt); + result = err; + + /* Copy in return parameters */ + RPC_R8(msg) = U8(result); + RPC_SIZE(msg) = 1U; + break; + } + /* Handle default */ + default : + { + RPC_SIZE(msg) = 1; + err = SC_ERR_NOTFOUND; + RPC_R8(msg) = (uint8_t) err; + } + break; + } + + /* Fill in header */ + RPC_VER(msg) = SC_RPC_VERSION; + RPC_SVC(msg) = (uint8_t) SC_RPC_SVC_RETURN; + + /* Handle error debug */ + if (err != SC_ERR_NONE) + { + if (rpc_debug) + { + always_print("ipc_err: api=timer, func=%d, err=%d\n", func, err); + } + else + { + rpc_print(0, "ipc_err: api=timer, func=%d, err=%d\n", func, err); + } + } +} + +/** @} */ + diff --git a/platform/svc/timer/svc.c b/platform/svc/timer/svc.c new file mode 100755 index 0000000..a0c5f91 --- /dev/null +++ b/platform/svc/timer/svc.c @@ -0,0 +1,1209 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/timer/svc.c + * + * File containing the implementation of the System Controller (SC) Timer + * function. + * + * @addtogroup TIMER_SVC + * @{ + */ +/*==========================================================================*/ + +/* Includes */ + +#include "main/scfw.h" +#include "main/main.h" +#include "main/board.h" +#include "svc/timer/svc.h" +#include "svc/rm/svc.h" +#include "ss/inf/inf.h" +#include "drivers/snvs/fsl_snvs.h" +#ifdef HAS_SECO +#include "drivers/seco/fsl_seco.h" +#endif +#include "drivers/sysctr/fsl_sysctr.h" + +/* Local Defines */ + +#define MAX_TIMEOUT (UINT32_MAX - 1U) //!< Max Timeout + +#define EPOCH 1970U +#define LEAP_YEAR(X) ((!U2B((X) % 4U) && U2B((X) % 100U)) || !U2B((X) % 400U)) +#define MIN_SECS 60U +#define HOUR_SECS (60U * MIN_SECS) +#define DAY_SECS (24U * HOUR_SECS) +#define YEAR_DAYS(X) (LEAP_YEAR(X) ? 366U : 365U) + +/* Local Types */ + +/*! + * This type is used to store dynamic info needed to track partition + * specific data for the watchdog service. + */ +typedef struct +{ + uint64_t sysctr_alarm; + uint64_t sysctr_period; + sc_timer_wdog_time_t wdog_time; + sc_timer_wdog_time_t wdog_timeout; + sc_timer_wdog_time_t wdog_window; + sc_timer_wdog_time_t wdog_pre_timeout; + uint32_t rtc_alarm; + uint32_t rtc_period; + sc_timer_wdog_action_t action : SC_TIMER_ACTION_W; + sc_bool_t wdog_enabled : SC_BOOL_W; + sc_bool_t wdog_locked : SC_BOOL_W; +} timer_part_data_t; + +/* Local Functions */ + +static void update_alarm(void); +static void update_sysctr(void); +static uint32_t epoc2secs(uint16_t year, uint8_t mon, uint8_t day, + uint8_t hour, uint8_t min, uint8_t sec); +static void notify_wdog_children(sc_rm_pt_t pt); + +/* Local Variables */ + +/*! Array of days in months */ +static const uint8_t days_in_month[2][12] = +{ + { 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U }, + { 31U, 29U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U } +}; + +#if defined(SC_FAKE_RTC) + /*! Fake RTC seconds */ + static uint32_t rtc_seconds; + /*! Fake RTC milliseconds */ + static uint32_t rtc_mseconds; + /*! Fake RTC seconds */ +#endif + +/*! + * @name Local Variables (not initialized) + * + * @{ + */ +static timer_part_data_t timer_part_data[SC_RM_NUM_PARTITION]; +/** @} */ + +/*--------------------------------------------------------------------------*/ +/* Init the timer service */ +/*--------------------------------------------------------------------------*/ +void timer_init(sc_bool_t api_phase) +{ + if (api_phase != SC_FALSE) + { + sc_rm_pt_t p; + + /* All partitions disabled */ + for (p = 0; p < SC_RM_NUM_PARTITION; p++) + { + timer_init_part(SC_PT, p); + } + } +} + +/*--------------------------------------------------------------------------*/ +/* Initialize a new partition */ +/*--------------------------------------------------------------------------*/ +void timer_init_part(sc_rm_pt_t caller_pt, sc_rm_pt_t pt) +{ + /* Init partition wdog data */ + timer_part_data[pt].wdog_enabled = SC_FALSE; + timer_part_data[pt].wdog_locked= SC_FALSE; + timer_part_data[pt].wdog_timeout = MAX_TIMEOUT; + timer_part_data[pt].wdog_window = 0U; + timer_part_data[pt].wdog_pre_timeout = MAX_TIMEOUT; + + /* Init partition RTC data */ + timer_part_data[pt].rtc_alarm = UINT32_MAX; + timer_part_data[pt].rtc_period = 0U; + + /* Init partition system counter data */ + timer_part_data[pt].sysctr_alarm = UINT64_MAX; + timer_part_data[pt].sysctr_period = 0ULL; + + /* Check for SCU PT */ + if (pt == SC_PT) + { + /* Action is to reboot partition */ + timer_part_data[pt].action = SC_TIMER_WDOG_ACTION_PARTITION; + } + else + { + sc_rm_pt_t parent = rm_get_partition_parent(pt); + + /* Action defaults to that of parent */ + timer_part_data[pt].action = timer_part_data[parent].action; + } +} + +/*--------------------------------------------------------------------------*/ +/* Set the timeout in mS (if not locked) */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_wdog_timeout(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t timeout) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check permissions */ + ASRT_ERR(timer_part_data[caller_pt].wdog_locked == SC_FALSE, + SC_ERR_LOCKED) + + if (err == SC_ERR_NONE) + { + /* Update */ + timer_part_data[caller_pt].wdog_timeout = timeout; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the pre-timeout in mS (if not locked) */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_wdog_pre_timeout(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t pre_timeout) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(pre_timeout <= MAX_TIMEOUT, SC_ERR_PARM) + + if (err == SC_ERR_NONE) + { + /* Update */ + timer_part_data[caller_pt].wdog_pre_timeout = pre_timeout; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the timeout in mS (if not locked) */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_wdog_window(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t window) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check permissions */ + ASRT_ERR(timer_part_data[caller_pt].wdog_locked == SC_FALSE, + SC_ERR_LOCKED) + + if (err == SC_ERR_NONE) + { + /* Update */ + timer_part_data[caller_pt].wdog_window = window; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Start the watchdog */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_start_wdog(sc_rm_pt_t caller_pt, sc_bool_t lock) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check permissions */ + ASRT_ERR(rm_is_partition_isolated(caller_pt) != SC_FALSE, + SC_ERR_NOACCESS); + ASRT_ERR(timer_part_data[caller_pt].wdog_enabled == SC_FALSE, + SC_ERR_BUSY); + + if (err == SC_ERR_NONE) + { + /* Update */ + timer_part_data[caller_pt].wdog_time = 0U; + timer_part_data[caller_pt].wdog_enabled = SC_TRUE; + timer_part_data[caller_pt].wdog_locked = lock; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Stop the watchdog (if not locked) */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_stop_wdog(sc_rm_pt_t caller_pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check permissions */ + ASRT_ERR(timer_part_data[caller_pt].wdog_locked == SC_FALSE, + SC_ERR_LOCKED) + + if (err == SC_ERR_NONE) + { + /* Update */ + timer_part_data[caller_pt].wdog_enabled = SC_FALSE; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Halt and reset watchdog even if locked */ +/*--------------------------------------------------------------------------*/ +void timer_halt_wdog(sc_rm_pt_t pt) +{ + /* Reset wdog */ + timer_part_data[pt].wdog_enabled = SC_FALSE; + timer_part_data[pt].wdog_time = 0U; + timer_part_data[pt].wdog_timeout = MAX_TIMEOUT; + timer_part_data[pt].wdog_window = 0U; + timer_part_data[pt].wdog_pre_timeout = MAX_TIMEOUT; + timer_part_data[pt].wdog_locked = SC_FALSE; + + /* Reset wdog action */ + timer_part_data[pt].action = SC_TIMER_WDOG_ACTION_PARTITION; +} + +/*--------------------------------------------------------------------------*/ +/* Ping (kick) the watchdog */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_ping_wdog(sc_rm_pt_t caller_pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Reboot/notify if timeout expired */ + if (timer_part_data[caller_pt].wdog_time + < timer_part_data[caller_pt].wdog_window) + { + timer_part_data[caller_pt].wdog_enabled = SC_FALSE; + + err = timer_take_wdog_action(caller_pt); + } + + /* Ping virtual timer */ + timer_part_data[caller_pt].wdog_time = 0U; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the watchdog status (all times in mS) */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_get_wdog_status(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Return data */ + if (timeout != NULL) + { + *timeout = timer_part_data[caller_pt].wdog_timeout; + } + + if (max_timeout != NULL) + { + *max_timeout = MAX_TIMEOUT; + } + + if (remaining_time != NULL) + { + *remaining_time = timer_part_data[caller_pt].wdog_timeout + - timer_part_data[caller_pt].wdog_time; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get a partition watchdog status (all times in mS) */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_pt_get_wdog_status(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_bool_t *enb, sc_timer_wdog_time_t *timeout, + sc_timer_wdog_time_t *remaining_time) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + + if (err == SC_ERR_NONE) + { + /* Return data */ + if (enb != NULL) + { + *enb = timer_part_data[pt].wdog_enabled; + } + + if (timeout != NULL) + { + *timeout = timer_part_data[pt].wdog_timeout; + } + + if (remaining_time != NULL) + { + *remaining_time = timer_part_data[pt].wdog_timeout + - timer_part_data[pt].wdog_time; + } + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Configure the action to be taken when a watchdog expires */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_wdog_action(sc_rm_pt_t caller_pt, + sc_rm_pt_t pt, sc_timer_wdog_action_t action) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + BOUND_PT(pt); + ASRT_ERR(action <= SC_TIMER_WDOG_ACTION_IRQ, SC_ERR_PARM) + + /* Check permissions */ + SYSTEM(caller_pt); + ASRT_ERR((pt != SC_PT) || (caller_pt == SC_PT), SC_ERR_NOACCESS) + + /* Check if locked */ + ASRT_ERR(timer_part_data[pt].wdog_locked == SC_FALSE, + SC_ERR_LOCKED) + + /* Set action */ + if (err == SC_ERR_NONE) + { + timer_part_data[pt].action = action; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Reboot partition or board depending on action */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_take_wdog_action(sc_rm_pt_t pt) +{ + sc_err_t err = SC_ERR_NONE; + sc_rm_idx_t idx; + sc_rm_pt_t system_pt; + + switch (timer_part_data[pt].action) + { + case SC_TIMER_WDOG_ACTION_PARTITION : + err = pm_reboot_part(pt, pt, SC_PM_RESET_TYPE_COLD, + SC_PM_RESET_REASON_WDOG, SC_PM_PW_MODE_OFF); + break; + case SC_TIMER_WDOG_ACTION_WARM : + err = board_reset(SC_PM_RESET_TYPE_WARM, SC_PM_RESET_REASON_WDOG, + pt); + break; + case SC_TIMER_WDOG_ACTION_COLD : + err = board_reset(SC_PM_RESET_TYPE_COLD, SC_PM_RESET_REASON_WDOG, + pt); + break; + case SC_TIMER_WDOG_ACTION_BOARD : + err = board_reset(SC_PM_RESET_TYPE_BOARD, SC_PM_RESET_REASON_WDOG, + pt); + break; + case SC_TIMER_WDOG_ACTION_IRQ : + /* Notify parent */ + ss_irq_trigger(SC_IRQ_GROUP_WDOG, + BIT(rm_get_partition_parent(pt)), SC_PT_ALL); + + /* Notify SYSTEM */ + if (rm_check_map_ridx(SC_R_SYSTEM, &idx) != SC_FALSE) + { + rm_get_ridx_owner(idx, &system_pt); + if (system_pt != rm_get_partition_parent(pt)) + { + ss_irq_trigger(SC_IRQ_GROUP_WDOG, + BIT(system_pt), SC_PT_ALL); + } + } + break; + default : + ; /* Intentional empty default */ + break; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the RTC time */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_rtc_time(sc_rm_pt_t caller_pt, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(year >= EPOCH, SC_ERR_PARM) + ASRT_ERR((mon >= 1U) && (mon <= 12U), SC_ERR_PARM) + ASRT_ERR((day >= 1U) && (day <= 31U), SC_ERR_PARM) + ASRT_ERR(hour < 24U, SC_ERR_PARM) + ASRT_ERR(min < 60U, SC_ERR_PARM) + ASRT_ERR(sec < 60U, SC_ERR_PARM) + + /* Check permissions */ + SYSTEM(caller_pt); + + /* Convert to seconds since epoc */ + if (err == SC_ERR_NONE) + { + uint32_t seconds; + uint32_t secs = 0U; + + seconds = epoc2secs(year, mon, day, hour, min, sec); + + /* Dump for debug */ + timer_print(3, "Time = %u\n", seconds); + + /* Read from the RTC */ + #if defined(SC_FAKE_RTC) + secs = rtc_seconds; + #else + SNVS_GetRtc(&secs); + #endif + + /* Update periodic alarms */ + for (sc_rm_pt_t p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if (timer_part_data[p].rtc_period != 0U) + { + timer_part_data[p].rtc_alarm = + timer_part_data[p].rtc_alarm + - secs + seconds; + } + } + + /* Program into the RTC */ + #if defined(SC_FAKE_RTC) + rtc_seconds = seconds; + rtc_mseconds = 0U; + #else + SNVS_SetRtc(seconds); + err = snvs_err; + if (err == SC_ERR_NONE) + { + SNVS_Functional_IRQHandler(); + } + #endif + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Get the RTC time */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_get_rtc_time(sc_rm_pt_t caller_pt, uint16_t *year, + uint8_t *mon, uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec) +{ + sc_err_t err = SC_ERR_NONE; + uint32_t secs; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Read from the RTC */ + if (err == SC_ERR_NONE) + { + #if defined(SC_FAKE_RTC) + secs = rtc_seconds; + #else + SNVS_GetRtc(&secs); + err = snvs_err; + #endif + } + + if (err == SC_ERR_NONE) + { + uint32_t days; + uint32_t daytime; + + /* Figure out time */ + daytime = secs % DAY_SECS; + *hour = U8(daytime / HOUR_SECS); + *min = U8((daytime % HOUR_SECS) / MIN_SECS); + *sec = U8(daytime % MIN_SECS); + + /* Figure out year */ + days = secs / DAY_SECS; + *year = EPOCH; + while (days >= YEAR_DAYS((*year))) + { + days -= YEAR_DAYS((*year)); + (*year)++; + } + + /* Figure out month */ + *mon = 0U; + while (days >= days_in_month[B2U16(LEAP_YEAR(*year))][*mon]) + { + days -= days_in_month[B2U16(LEAP_YEAR(*year))][*mon]; + (*mon)++; + } + *mon += 1U; + *day = U8(days) + 1U; + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the RTC alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_rtc_alarm(sc_rm_pt_t caller_pt, uint16_t year, + uint8_t mon, uint8_t day, uint8_t hour, uint8_t min, uint8_t sec) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(year >= EPOCH, SC_ERR_PARM) + ASRT_ERR((mon >= 1U) && (mon <= 12U), SC_ERR_PARM) + ASRT_ERR((day >= 1U) && (day <= 31U), SC_ERR_PARM) + ASRT_ERR(hour < 24U, SC_ERR_PARM) + ASRT_ERR(min < 60U, SC_ERR_PARM) + ASRT_ERR(sec < 60U, SC_ERR_PARM) + + /* Check for error */ + if (err == SC_ERR_NONE) + { + uint32_t seconds; + + /* Convert to seconds since epoc */ + seconds = epoc2secs(year, mon, day, hour, min, sec); + + /* Dump for debug */ + timer_print(3, "Set RTC alarm = %u\n", seconds); + + /* Program into the RTC alarm */ + timer_part_data[caller_pt].rtc_alarm = seconds; + timer_part_data[caller_pt].rtc_period = 0U; + + /* Update alarm */ + update_alarm(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the RTC periodic alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_rtc_periodic_alarm(sc_rm_pt_t caller_pt, uint32_t sec) +{ + sc_err_t err = SC_ERR_NONE; + uint32_t secs; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(sec != 0U, SC_ERR_PARM); + + if (err == SC_ERR_NONE) + { + /* Dump for debug */ + timer_print(3, "Set RTC periodic alarm = %u\n", sec); + + /* Read from the RTC */ + #if defined(SC_FAKE_RTC) + secs = rtc_seconds; + #else + SNVS_GetRtc(&secs); + err = snvs_err; + #endif + } + + if (err == SC_ERR_NONE) + { + uint32_t seconds; + + /* Program into the RTC alarm */ + seconds = secs + sec; + timer_part_data[caller_pt].rtc_alarm = seconds; + timer_part_data[caller_pt].rtc_period = sec; + + update_alarm(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Cancel RTC alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_cancel_rtc_alarm(sc_rm_pt_t caller_pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Program into the RTC alarm */ + timer_part_data[caller_pt].rtc_alarm = UINT32_MAX; + timer_part_data[caller_pt].rtc_period = 0U; + + update_alarm(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Query RTC alarm */ +/*--------------------------------------------------------------------------*/ +void timer_query_rtc_alarm(sc_rm_pt_t pt, uint32_t *alarm, + uint32_t *period) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(pt); + + if (err == SC_ERR_NONE) + { + /* Return RTC alarm data for the partition */ + *alarm = timer_part_data[pt].rtc_alarm; + *period = timer_part_data[pt].rtc_period; + } +} + +/*--------------------------------------------------------------------------*/ +/* Restore RTC alarm */ +/*--------------------------------------------------------------------------*/ +void timer_restore_rtc_alarm(sc_rm_pt_t pt, uint32_t alarm, + uint32_t period) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(pt); + + if (err == SC_ERR_NONE) + { + /* Restore RTC alarm data for the partition */ + timer_part_data[pt].rtc_alarm = alarm; + timer_part_data[pt].rtc_period = period; + + update_alarm(); + } +} + +/*--------------------------------------------------------------------------*/ +/* Get the RTC time in seconds since 1/1/1970 */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_get_rtc_sec1970(sc_rm_pt_t caller_pt, uint32_t *sec) +{ + /* Read from the RTC */ + #if defined(SC_FAKE_RTC) + *sec = rtc_seconds; + + return SC_ERR_NONE; + #else + SNVS_GetRtc(sec); + + return snvs_err; + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Set the RTC calibration */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_rtc_calb(sc_rm_pt_t caller_pt, int8_t count) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + /* Check parameters */ + ASRT_ERR(count >= -16, SC_ERR_PARM) + ASRT_ERR(count <= 15, SC_ERR_PARM) + + /* Check permissions */ + SYSTEM(caller_pt); + + if (err == SC_ERR_NONE) + { + #if !defined(SC_FAKE_RTC) + SNVS_SetRtcCalb(count); + SNVS_SetSecureRtcCalb(count); + err = snvs_err; + #else + err = SC_ERR_UNAVAILABLE; + #endif + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Tick timer services */ +/*--------------------------------------------------------------------------*/ +void timer_tick(uint16_t msec) +{ + sc_rm_pt_t p; + + #if defined(SC_FAKE_RTC) + uint32_t sec; + + /* Tick fake RTC */ + rtc_mseconds += msec; + sec = rtc_mseconds / 1000U; + rtc_mseconds -= (sec * 1000U); + rtc_seconds += sec; + + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if (rtc_seconds >= timer_part_data[p].rtc_alarm) + { + if (timer_part_data[p].rtc_period == 0U) + { + timer_part_data[p].rtc_alarm = UINT32_MAX; + } + else + { + timer_part_data[p].rtc_alarm = rtc_seconds + + timer_part_data[p].rtc_period; + } + ss_irq_trigger(SC_IRQ_GROUP_RTC, BIT(p), p); + if (p == SC_PT) + { +#ifdef HAS_SECO + SECO_KickWdog(); +#endif + } + } + } + #endif + + /* Tick watchdogs */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if (timer_part_data[p].wdog_enabled != SC_FALSE) + { + timer_part_data[p].wdog_time += msec; + + /* Generate IRQ if pre-timeout expired */ + if (timer_part_data[p].wdog_time + >= timer_part_data[p].wdog_pre_timeout) + { + timer_part_data[p].wdog_pre_timeout = UINT32_MAX; + notify_wdog_children(p); + } + + /* Reboot/notify if timeout expired */ + if (timer_part_data[p].wdog_time + >= timer_part_data[p].wdog_timeout) + { + timer_part_data[p].wdog_enabled = SC_FALSE; + + (void) timer_take_wdog_action(p); + } + } + } +} + +/*--------------------------------------------------------------------------*/ +/* RTC alarm ISR */ +/*--------------------------------------------------------------------------*/ +#if !defined(SC_FAKE_RTC) + void SNVS_Functional_IRQHandler(void) + { + uint32_t seconds = UINT32_MAX; + sc_rm_pt_t p; + + SNVS_GetRtc(&seconds); + + /* Notify users of alarm */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + /* Alarm time expired? */ + if (seconds >= timer_part_data[p].rtc_alarm) + { + /* Handle one-shot alarm */ + if (timer_part_data[p].rtc_period == 0U) + { + timer_part_data[p].rtc_alarm = UINT32_MAX; + } + else + { + timer_part_data[p].rtc_alarm = seconds + + timer_part_data[p].rtc_period; + } + /* Trigger user interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_RTC, BIT(p), p); + if (p == SC_PT) + { +#ifdef HAS_SECO + /* Service SECO watchdog */ + SECO_KickWdog(); +#endif + } + } + } + + /* Configure next alarm (and clear) */ + update_alarm(); + } +#endif + +/*--------------------------------------------------------------------------*/ +/* Set the sysctr alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_sysctr_alarm(sc_rm_pt_t caller_pt, uint64_t ticks) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Program into the RTC alarm */ + timer_part_data[caller_pt].sysctr_alarm = ticks; + timer_part_data[caller_pt].sysctr_period = 0ULL; + + update_sysctr(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Set the periodic sysctr alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_set_sysctr_periodic_alarm(sc_rm_pt_t caller_pt, + uint64_t ticks) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + ASRT_ERR(ticks != 0ULL, SC_ERR_PARM); + + if (err == SC_ERR_NONE) + { + /* Program into the SYSCTR alarm */ + timer_part_data[caller_pt].sysctr_alarm = SYSCTR_GetCounter64() + + ticks; + timer_part_data[caller_pt].sysctr_period = ticks; + + update_sysctr(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* Cancel the sysctr alarm */ +/*--------------------------------------------------------------------------*/ +sc_err_t timer_cancel_sysctr_alarm(sc_rm_pt_t caller_pt) +{ + sc_err_t err = SC_ERR_NONE; + + /* Bounds check */ + BOUND_PT(caller_pt); + + if (err == SC_ERR_NONE) + { + /* Program into the RTC alarm */ + timer_part_data[caller_pt].sysctr_alarm = UINT64_MAX; + timer_part_data[caller_pt].sysctr_period = 0ULL; + + update_sysctr(); + } + + return err; +} + +/*--------------------------------------------------------------------------*/ +/* SYSCTR alarm ISR */ +/*--------------------------------------------------------------------------*/ +void SYSCTR_CMP1_IRQHandler(void) +{ + uint64_t ticks; + sc_rm_pt_t p; + + ticks = SYSCTR_GetCounter64(); + + /* Notify users of alarm */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if (ticks >= timer_part_data[p].sysctr_alarm) + { + if (timer_part_data[p].sysctr_period == 0ULL) + { + timer_part_data[p].sysctr_alarm = UINT64_MAX; + } + else + { + timer_part_data[p].sysctr_alarm = ticks + + timer_part_data[p].sysctr_period; + } + if (p != SC_PT) + { + ss_irq_trigger(SC_IRQ_GROUP_SYSCTR, BIT(p), p); + } + else + { + pm_reboot_continue_all(); + } + } + } + + /* Configure next alarm (and clear) */ + #ifndef NO_DEVICE_ACCESS + SYSCTR_Compare1Disable(); + #endif + update_sysctr(); +} + +/*--------------------------------------------------------------------------*/ +/* Dump timer state for debug */ +/*--------------------------------------------------------------------------*/ +#if defined(DEBUG) && defined(DEBUG_TIMER) + void timer_dump(sc_rm_pt_t pt) + { + sc_err_t err = SC_ERR_NONE; + + /* Check if partition enabled */ + USED_PT(pt); + + if ((debug != SC_FALSE) && (err == SC_ERR_NONE)) + { + /* Dump data */ + #if defined(SC_FAKE_RTC) + if (pt == 0U) + { + timer_print(2, " RTC (fake): %u.%03u\n", rtc_seconds, + rtc_mseconds); + } + #endif + timer_print(2, " Partition: %u\n", pt); + timer_print(2, " Wdog time: %u\n", + timer_part_data[pt].wdog_time); + timer_print(2, " Wdog timeout: %u\n", + timer_part_data[pt].wdog_timeout); + timer_print(2, " Wdog pre-timeout: %u\n", + timer_part_data[pt].wdog_pre_timeout); + timer_print(2, " Wdog flags:\n"); + if (timer_part_data[pt].wdog_enabled != SC_FALSE) + { + timer_print(2, " Enabled\n"); + } + if (timer_part_data[pt].wdog_locked != SC_FALSE) + { + timer_print(2, " Locked\n"); + } + } + } +#endif + +/*==========================================================================*/ + +/*--------------------------------------------------------------------------*/ +/* Update RTC alarm */ +/*--------------------------------------------------------------------------*/ +static void update_alarm(void) +{ + #if !defined(SC_FAKE_RTC) + sc_rm_pt_t p; + uint32_t secs; + uint32_t seconds = UINT32_MAX; + + /* Get current RTC */ + SNVS_GetRtc(&secs); + + /* Search for next time */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + /* Alarm time passed? */ + if (timer_part_data[p].rtc_alarm <= secs) + { + /* Periodic? */ + if (timer_part_data[p].rtc_period == 0U) + { + /* Cancel */ + timer_part_data[p].rtc_alarm = UINT32_MAX; + } + else + { + /* Next period */ + timer_part_data[p].rtc_alarm = seconds + + timer_part_data[p].rtc_period; + } + + /* Trigger interrupt */ + ss_irq_trigger(SC_IRQ_GROUP_RTC, BIT(p), p); + } + else + { + /* Earlier time? */ + seconds = MIN(seconds, timer_part_data[p].rtc_alarm); + } + } + + SNVS_SetRtcAlarm(seconds); + #endif +} + +/*--------------------------------------------------------------------------*/ +/* Update sysctr alarm */ +/*--------------------------------------------------------------------------*/ +static void update_sysctr(void) +{ + sc_rm_pt_t p; + uint64_t ticks = UINT64_MAX; + + /* Search for next time */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + /* Earlier time? */ + ticks = MIN(ticks, timer_part_data[p].sysctr_alarm); + } + +#ifndef NO_DEVICE_ACCESS + /* Found a time? */ + if (ticks != UINT64_MAX) + { + /* Enable counter compare */ + SYSCTR_Compare1Enable(ticks); + } + else + { + /* Disable counter compare */ + SYSCTR_Compare1Disable(); + } +#endif +} + +/*--------------------------------------------------------------------------*/ +/* Convert date/time to seconds since epoc */ +/*--------------------------------------------------------------------------*/ +static uint32_t epoc2secs(uint16_t year, uint8_t mon, uint8_t day, + uint8_t hour, uint8_t min, uint8_t sec) +{ + uint32_t secs = 0U; + uint8_t new_mon = mon; + uint16_t new_year = year; + + /* Add time */ + secs += U32(hour) * HOUR_SECS; + secs += U32(min) * MIN_SECS; + secs += U32(sec); + + /* Add month */ + new_mon--; + while (new_mon > 0U) + { + secs += days_in_month[B2U16(LEAP_YEAR(new_year))][new_mon - 1U] + * DAY_SECS; + new_mon--; + } + + /* Add day */ + secs += (U32(day) - 1U) * DAY_SECS; + + /* Add year */ + new_year--; + while (new_year >= EPOCH) + { + secs += YEAR_DAYS(new_year) * DAY_SECS; + new_year--; + } + + return secs; +} + +/*--------------------------------------------------------------------------*/ +/* Generate a WDOG IRQ to a partition and all children */ +/*--------------------------------------------------------------------------*/ +static void notify_wdog_children(sc_rm_pt_t pt) +{ + sc_rm_pt_t p; + + /* Notify children */ + for (p = 0U; p < SC_RM_NUM_PARTITION; p++) + { + if (rm_get_partition_parent(p) == pt) + { + notify_wdog_children(p); + } + } + + /* Notify parent */ + ss_irq_trigger(SC_IRQ_GROUP_WDOG, BIT(pt), + SC_PT_ALL); +} + +/** @} */ + diff --git a/platform/svc/timer/svc.h b/platform/svc/timer/svc.h new file mode 100755 index 0000000..b522942 --- /dev/null +++ b/platform/svc/timer/svc.h @@ -0,0 +1,304 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file svc/timer/svc.h + * + * Header file containing the API for the System Controller (SC) Timer + * function. + * + * @addtogroup TIMER_SVC + * @{ + */ +/*==========================================================================*/ + +#ifndef SC_TIMER_SVC_H +#define SC_TIMER_SVC_H + +/* Includes */ + +#include "svc/timer/api.h" + +/* Defines */ + +/* Types */ + +/* Functions */ + +/*! + * @name Internal Functions + * @{ + */ + +/*! + * Internal SC function to initializes the TIMER service. + * + * @param[in] api_phase init phase + * + * Initializes the API if /a api_phase = SC_TRUE, otherwise initializes the HW + * managed by the timer service. API must be initialized before anything + * else is done with the service. + */ +void timer_init(sc_bool_t api_phase); + +/*! + * This function initializes a new partition. + * + * @param[in] caller_pt handle of caller partition + * @param[in] pt handle of partition + * + * Note this function should only be called by the resource manager when + * a new partition is allocated. + */ +void timer_init_part(sc_rm_pt_t caller_pt, sc_rm_pt_t pt); + +/*! + * Internal SC function to set the watchdog timeout in milliseconds. + * + * @see sc_timer_set_wdog_timeout(). + */ +sc_err_t timer_set_wdog_timeout(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t timeout); + +/*! + * Internal SC function to set the watchdog pre-timeout in milliseconds. + * + * @see sc_timer_set_wdog_pre_timeout(). + */ +sc_err_t timer_set_wdog_pre_timeout(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t pre_timeout); + +/*! + * Internal SC function to set the watchdog window in milliseconds. + * + * @see sc_timer_set_wdog_window(). + */ +sc_err_t timer_set_wdog_window(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t window); + +/*! + * Internal SC function to start the watchdog. + * + * @see sc_timer_start_wdog(). + */ +sc_err_t timer_start_wdog(sc_rm_pt_t caller_pt, sc_bool_t lock); + +/*! + * Internal SC function to stop the watchdog (if not locked). + * + * @see sc_timer_stop_wdog(). + */ +sc_err_t timer_stop_wdog(sc_rm_pt_t caller_pt); + +/*! + * Internal SC function to stop halt the wdog when the partition is deleted. + * + * @param[in] pt partition whose wdog should be halted + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * This function will halt the wdog even if locked. + */ +void timer_halt_wdog(sc_rm_pt_t pt); + +/*! + * Internal SC function to ping (services, kicks) the watchdog resetting + * the time before expiration back to the timeout. + * + * @see sc_timer_ping_wdog(). + */ +sc_err_t timer_ping_wdog(sc_rm_pt_t caller_pt); + +/*! + * Internal SC function to get the status of the watchdog. All arguments + * are in milliseconds. + * + * @see sc_timer_get_wdog_status(). + */ +sc_err_t timer_get_wdog_status(sc_rm_pt_t caller_pt, + sc_timer_wdog_time_t *timeout, sc_timer_wdog_time_t *max_timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * Internal SC function to get the status of the watchdog of a partition. + * All arguments are in milliseconds. + * + * @see sc_timer_pt_get_wdog_status(). + */ +sc_err_t timer_pt_get_wdog_status(sc_rm_pt_t caller_pt, sc_rm_pt_t pt, + sc_bool_t *enb, sc_timer_wdog_time_t *timeout, + sc_timer_wdog_time_t *remaining_time); + +/*! + * Internal SC function to configure the action to be taken when a + * watchdog expires. + * + * @see sc_timer_set_wdog_action(). + */ +sc_err_t timer_set_wdog_action(sc_rm_pt_t caller_pt, + sc_rm_pt_t pt, sc_timer_wdog_action_t action); + +/*! + * Internal SC function to take the wdog action specified. + * + * @param[in] pt partition to affect + * + * @return Returns an error code (SC_ERR_NONE = success). + * + * Reboots the partition, board, and/or generate IRQs. + */ +sc_err_t timer_take_wdog_action(sc_rm_pt_t pt); + +/*! + * Internal SC function to set the RTC time. + * + * @see sc_timer_set_rtc_time(). + */ +sc_err_t timer_set_rtc_time(sc_rm_pt_t caller_pt, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * Internal SC function to get the RTC time. + * + * @see sc_timer_get_rtc_time(). + */ +sc_err_t timer_get_rtc_time(sc_rm_pt_t caller_pt, uint16_t *year, + uint8_t *mon, uint8_t *day, uint8_t *hour, uint8_t *min, uint8_t *sec); + +/*! + * Internal SC function to set the RTC alarm. + * + * @see sc_timer_set_rtc_alarm(). + */ +sc_err_t timer_set_rtc_alarm(sc_rm_pt_t caller_pt, uint16_t year, uint8_t mon, + uint8_t day, uint8_t hour, uint8_t min, uint8_t sec); + +/*! + * Internal SC function to set a periodic RTC alarm. + * + * @see sc_timer_set_rtc_periodic_alarm(). + */ +sc_err_t timer_set_rtc_periodic_alarm(sc_rm_pt_t caller_pt, uint32_t sec); + +/*! + * Internal SC function to cancel an RTC alarm. + * + * @see sc_timer_cancel_rtc_alarm(). + */ +sc_err_t timer_cancel_rtc_alarm(sc_rm_pt_t caller_pt); + +/*! + * Internal SC function to query an RTC alarm. + * + * @param[in] pt partition to query + * @param[out] alarm pointer to return alarm + * @param[out] period pointer to return period + * + * Companion function to timer_restore_rtc_alarm(). + */ +void timer_query_rtc_alarm(sc_rm_pt_t pt, uint32_t *alarm, + uint32_t *period); + +/*! + * Internal SC function to restore an RTC alarm. + * + * @param[in] pt partition to restore + * @param[in] alarm alarm + * @param[in] period period + * + * Companion function to timer_query_rtc_alarm(). + */ +void timer_restore_rtc_alarm(sc_rm_pt_t pt, uint32_t alarm, + uint32_t period); + +/*! + * Internal SC function to get the RTC time in seconds since 1/1/1970. + * + * @see sc_timer_get_rtc_sec1970(). + */ +sc_err_t timer_get_rtc_sec1970(sc_rm_pt_t caller_pt, uint32_t *sec); + +/*! + * Internal SC function to set the RTC calibration. + * + * @see sc_timer_set_rtc_calb(). + */ +sc_err_t timer_set_rtc_calb(sc_rm_pt_t caller_pt, int8_t count); + +/*! + * Internal SC function to increment the RTC. + */ +void timer_tick(uint16_t msec); + +/*! + * Internal SC function to set the sysctr alarm. + */ +sc_err_t timer_set_sysctr_alarm(sc_rm_pt_t caller_pt, + uint64_t ticks); + +/*! + * Internal SC function to set the periodic sysctr alarm. + */ +sc_err_t timer_set_sysctr_periodic_alarm(sc_rm_pt_t caller_pt, + uint64_t ticks); + +/*! + * Internal SC function to cancel the sysctr alarm. + */ +sc_err_t timer_cancel_sysctr_alarm(sc_rm_pt_t caller_pt); + +/** @} */ + +#if defined(DEBUG) && defined(DEBUG_TIMER) + /*! + * @name Debug Functions + * @{ + */ + + /*! + * Internal SC function to dump the internal state of the timer service. + * + * @param[in] pt partition to dump + */ + void timer_dump(sc_rm_pt_t pt); + + /** @} */ +#endif + +#endif /* SC_TIMER_SVC_H */ + +/** @} */ + diff --git a/platform/test/Makefile b/platform/test/Makefile new file mode 100755 index 0000000..da38cf9 --- /dev/null +++ b/platform/test/Makefile @@ -0,0 +1,40 @@ + +include $(SRC)/test/$(CONFIG)/test.bom + +TEST_DIRNAME=platform/test/drv +ifneq "$(wildcard $(TEST_DIRNAME) )" "" + TEST_TARGET := $(shell find platform/test -name test_$(LOWER_T).c -printf "%P\n") +else + TEST_DIRNAME2=$(OUT)/test + ifneq "$(wildcard $(TEST_DIRNAME2) )" "" + TEST_TARGET := $(shell find $(OUT)/test -name test_$(LOWER_T).o -printf "%P\n") + endif +endif + +ifeq ($(LOWER_T), all) + TEST_TARGET := $(CONFIG)/test_all.c +endif + +ifneq ($(UPPER_T), NONE) + objs_test += common/test.o $(TEST_TARGET:.c=.o) +endif + +ifeq ($(LOWER_T), all) + objs_test += $(AUTO_TEST) +endif + +OBJS += \ + $(foreach object,$(objs_test),$(OUT)/test/$(object)) + +EOBJS = $(OUT)/test/common/test.o $(OUT)/test/$(CONFIG)/test_all.o + +EOBJS += \ + $(foreach object,$(AUTO_TEST),$(OUT)/test/$(object)) + +EOBJS += \ + $(foreach object,$(EXPT_TEST),$(OUT)/test/$(object)) + +DIRS += $(OUT)/test $(OUT)/test/common $(OUT)/test/drv $(OUT)/test/ss \ + $(OUT)/test/svc $(OUT)/test/misc $(OUT)/test/ddr $(OUT)/test/sys \ + $(OUT)/test/$(CONFIG) + diff --git a/platform/test/common/test.h b/platform/test/common/test.h new file mode 100644 index 0000000..737b81e --- /dev/null +++ b/platform/test/common/test.h @@ -0,0 +1,308 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file with prototypes so main can call test functions. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by test_h.pl */ + +#ifndef SC_TEST_H +#define SC_TEST_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +#ifdef DEBUG +#ifdef HAS_TEST_PTIM + #define CHECK_NERR(X) {SC_PTIM_SETREF(testProf, __FILE__, __LINE__); \ + err = (X); \ + if (err != SC_ERR_NONE) \ + { \ + error_print("error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#else + #define CHECK_NERR(X) {err = (X); \ + if (err != SC_ERR_NONE) \ + { \ + error_print("error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#endif // HAS_TEST_PTIM + #ifdef CONFIRM_ERR +#ifdef HAS_TEST_PTIM + #define CHECK_ERR(X) {SC_PTIM_SETREF(testProf, __FILE__, __LINE__); \ + err = (X); \ + if ((err = (X)) == SC_ERR_NONE) \ + { \ + error_print("non error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#else + #define CHECK_ERR(X) {err = (X); \ + if (err == SC_ERR_NONE) \ + { \ + error_print("non error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#endif + #else + #define CHECK_ERR(X) NOP + #endif + +#else + #define CHECK_NERR(X) X + #define CHECK_ERR(X) X +#endif + +#define ASRT_TST_ERR(X,ERROR) \ + if (!(X)) \ + { \ + error_print("error @ line %d: %d\n", \ + __LINE__, ERROR); \ + board_exit(ERROR); \ + } + +#if TEST_LSIO + #define CHECK_LSIO(X) NOP +#else + #define CHECK_LSIO(X) return (X) +#endif + +#if HAS_SS_MCU_0 + #define CHECK_MCU_0(X) NOP +#else + #define CHECK_MCU_0(X) return (X) +#endif + +#if HAS_SS_MCU_1 + #define CHECK_MCU_1(X) NOP +#else + #define CHECK_MCU_1(X) return (X) +#endif + +#define TEST_DRV_START(X) \ + test_print(TL1, "\n*** %s DRV Test\n\n", X); + +#define TEST_DRV_END \ + test_print(TL1, "\n") + +#define TEST_SC_START(X) \ + test_print(TL1, "\n*** %s SC Test\n\n", X); \ + sc_pm_power_mode_t dblogic_mode; \ + (void) pm_get_resource_power_mode(SC_PT, SC_R_DBLOGIC, &dblogic_mode); \ + pm_force_resource_power_mode_v(SC_R_DBLOGIC, SC_PM_PW_MODE_ON); \ + sc_pm_power_mode_t db_mode[SC_NUM_DB]; \ + for (uint8_t db = 0U; db < SC_NUM_DB; db++) \ + { \ + (void) pm_get_resource_power_mode(SC_PT, sc_db_info[db].rsrc, &db_mode[db]); \ + pm_force_resource_power_mode_v(sc_db_info[db].rsrc, SC_PM_PW_MODE_ON); \ + } + +#define TEST_SC_END \ + for (uint8_t db = SC_NUM_DB; db > 0U; db--) \ + { \ + if (db_mode[db - 1U] == SC_PM_PW_MODE_OFF) \ + { \ + pm_force_resource_power_mode_v(sc_db_info[db - 1U].rsrc, SC_PM_PW_MODE_OFF); \ + } \ + } \ + if (dblogic_mode == SC_PM_PW_MODE_OFF) \ + pm_force_resource_power_mode_v(SC_R_DBLOGIC, SC_PM_PW_MODE_OFF); \ + test_print(TL1, "\n") + +#define TEST_AP_START(X) \ + sc_ipc_t ipc_sc; \ + test_print(TL1, "\n*** %s AP Test\n\n", X); \ + sc_ipc_open(&ipc_sc, (sc_ipc_id_t) MU_SC_1A); \ + (void) sc_rm_set_peripheral_permissions(ipc_sc, SC_R_MU_0A, SC_PT, SC_RM_PERM_FULL) + +#define TEST_AP_END \ + sc_ipc_close(ipc_sc); \ + test_print(TL1, "\n") + +#define TEST_DRV(X) sc_err_t test_drv_ ## X(sc_bool_t *const stop) +#define TEST_SC(X) sc_err_t test_sc_ ## X(sc_bool_t *const stop) +#define TEST_AP(X) sc_err_t test_ap_ ## X(sc_bool_t *const stop) + +#define TEST_PROTO(X) sc_err_t test_drv_ ## X(sc_bool_t *const stop); \ + sc_err_t test_sc_ ## X(sc_bool_t *const stop); \ + sc_err_t test_ap_ ## X(sc_bool_t *const stop); + +#define DBGSTR_PU "Power up %s\n" +#define DBGSTR_PD "Power down %s\n" +#define DBGSTR_TRY "Try %s access...\n" +#define DBGSTR_READ_GPIO "Read from GPIO_%s = 0x%08x\n" +#define DBGSTR_READ_IGPIO "Read from GPIO_%u = 0x%08x\n" +#define DBGSTR_READ_MU "Read from MU_%s.SR = 0x%08x\n" +#define DBGSTR_READ_UART "Read from UART_%s.VERID = 0x%08x\n" +#define DBGSTR_READ_I2C "Read from I2C_%s.VERID = 0x%08x\n" +#define DBGSTR_READ_LPCG "Read from LPCG_%s = 0x%08x\n" + +#define TEST_RSRC_NUM 43U + +#define TEST_READ32(X) test_read32(U32(X)) +#define TEST_WRITE32(X,Y) test_write32(U32(X), (Y)) +#define TEST_CHECK32(X,Y) test_check32(U32(X), (Y)) +#define TEST_NO_READ32(X) test_pid32(0U, U32(X), SC_TRUE) +#define TEST_PID_READ32(X,Y) test_pid32((X), U32(Y), SC_FALSE) +#define TEST_PID_NO_READ32(X,Y) test_pid32((X), U32(Y), SC_TRUE) + +/* Types */ + +/* Enums */ + +/* Sub Includes */ + +/* Functions */ + +#if defined(HAS_TEST) || defined(DEBUG) +TEST_PROTO(all) +TEST_PROTO(dump) +TEST_PROTO(board) +TEST_PROTO(rpc) +TEST_PROTO(temp) +TEST_PROTO(partnum) +TEST_PROTO(reboot) +TEST_PROTO(uboot) +TEST_PROTO(wdog) +TEST_PROTO(boot) +TEST_PROTO(xrdc) +TEST_PROTO(smmu) +TEST_PROTO(snvs) +TEST_PROTO(drv) +TEST_PROTO(lpi2c) +TEST_PROTO(pll) +TEST_PROTO(otp) +TEST_PROTO(dsc) +TEST_PROTO(pmic) +TEST_PROTO(lsio) +TEST_PROTO(hdmi_rx) +TEST_PROTO(dma) +TEST_PROTO(csi) +TEST_PROTO(dc) +TEST_PROTO(ap) +TEST_PROTO(mcu) +TEST_PROTO(pi) +TEST_PROTO(mipi) +TEST_PROTO(gpu) +TEST_PROTO(db) +TEST_PROTO(img) +TEST_PROTO(hdmi) +TEST_PROTO(isi) +TEST_PROTO(v2x) +TEST_PROTO(lvds) +TEST_PROTO(dc_lvds) +TEST_PROTO(cci) +TEST_PROTO(dblogic) +TEST_PROTO(hsio) +TEST_PROTO(vpu) +TEST_PROTO(audio) +TEST_PROTO(conn) +TEST_PROTO(drc) +TEST_PROTO(lcdif) +TEST_PROTO(misc) +TEST_PROTO(pad) +TEST_PROTO(timer) +TEST_PROTO(pm) +TEST_PROTO(rm) +TEST_PROTO(rm2) +TEST_PROTO(seco) +TEST_PROTO(osc24trim) +TEST_PROTO(pd) +TEST_PROTO(nmi_lockup) +TEST_PROTO(nmi_msi) +TEST_PROTO(timers) +TEST_PROTO(memreg) +TEST_PROTO(examples) +TEST_PROTO(fusedump) +TEST_PROTO(mtemp) +TEST_PROTO(obd) +TEST_PROTO(bench) +TEST_PROTO(pllchar) +TEST_PROTO(nmi_ecc) +TEST_PROTO(membw) +TEST_PROTO(profile) +TEST_PROTO(hmppm) +TEST_PROTO(audio_pll) +TEST_PROTO(powerall) +TEST_PROTO(boottime) +TEST_PROTO(fusewrite) +TEST_PROTO(critsec) +TEST_PROTO(refgencal) +TEST_PROTO(hexdump) +TEST_PROTO(ddr_retention) +TEST_PROTO(ddr_selfrefresh) +TEST_PROTO(ddr) +#endif + +sc_err_t test_force_power(sc_rsrc_t resource, sc_pm_power_mode_t mode); +sc_err_t test_power(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); +sc_err_t test_force_power_list_on(const sc_rsrc_t *resource, uint32_t num); +sc_err_t test_force_power_list_off(const sc_rsrc_t *resource, uint32_t num); +sc_err_t test_power_list_on(sc_ipc_t ipc, const sc_rsrc_t *resource, + uint32_t num); +sc_err_t test_power_list_off(sc_ipc_t ipc, const sc_rsrc_t *resource, + uint32_t num); +uint32_t test_read32(uint32_t addr); +void test_write32(uint32_t addr, uint32_t val); +void test_check32(uint32_t addr, uint32_t val); +void test_pid32(uint32_t pid, uint32_t addr, sc_bool_t fail); +void test_reset(sc_rsrc_t resource, uint32_t addr, uint32_t val, + uint32_t reset_val); +sc_err_t test_clock_rate_change(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, uint32_t new_rate); + +/* External Variables. */ + +extern sc_bool_t dma_up_down; +extern volatile uint32_t test_val; +extern const sc_rsrc_t test_rsrc_list[TEST_RSRC_NUM]; + +#endif /* SC_TEST_H */ + diff --git a/platform/test/common/test.t.h b/platform/test/common/test.t.h new file mode 100755 index 0000000..6163e9c --- /dev/null +++ b/platform/test/common/test.t.h @@ -0,0 +1,236 @@ +/* +** ################################################################### +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2017-2020 NXP +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** +** ################################################################### +*/ + +/*==========================================================================*/ +/*! + * @file + * + * Header file with prototypes so main can call test functions. + */ +/*==========================================================================*/ + +/* DO NOT EDIT - This file auto generated by $cmd */ + +#ifndef SC_TEST_H +#define SC_TEST_H + +/* Includes */ + +#include "main/types.h" + +/* Defines */ + +#ifdef DEBUG +#ifdef HAS_TEST_PTIM + #define CHECK_NERR(X) {SC_PTIM_SETREF(testProf, __FILE__, __LINE__); \ + err = (X); \ + if (err != SC_ERR_NONE) \ + { \ + error_print("error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#else + #define CHECK_NERR(X) {err = (X); \ + if (err != SC_ERR_NONE) \ + { \ + error_print("error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#endif // HAS_TEST_PTIM + #ifdef CONFIRM_ERR +#ifdef HAS_TEST_PTIM + #define CHECK_ERR(X) {SC_PTIM_SETREF(testProf, __FILE__, __LINE__); \ + err = (X); \ + if ((err = (X)) == SC_ERR_NONE) \ + { \ + error_print("non error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#else + #define CHECK_ERR(X) {err = (X); \ + if (err == SC_ERR_NONE) \ + { \ + error_print("non error @ line %d: %d\n", \ + __LINE__, err); \ + board_exit(err); \ + }} +#endif + #else + #define CHECK_ERR(X) NOP + #endif + +#else + #define CHECK_NERR(X) X + #define CHECK_ERR(X) X +#endif + +#define ASRT_TST_ERR(X,ERROR) \ + if (!(X)) \ + { \ + error_print("error @ line %d: %d\n", \ + __LINE__, ERROR); \ + board_exit(ERROR); \ + } + +#if TEST_LSIO + #define CHECK_LSIO(X) NOP +#else + #define CHECK_LSIO(X) return (X) +#endif + +#if HAS_SS_MCU_0 + #define CHECK_MCU_0(X) NOP +#else + #define CHECK_MCU_0(X) return (X) +#endif + +#if HAS_SS_MCU_1 + #define CHECK_MCU_1(X) NOP +#else + #define CHECK_MCU_1(X) return (X) +#endif + +#define TEST_DRV_START(X) \ + test_print(TL1, "\n*** %s DRV Test\n\n", X); + +#define TEST_DRV_END \ + test_print(TL1, "\n") + +#define TEST_SC_START(X) \ + test_print(TL1, "\n*** %s SC Test\n\n", X); \ + sc_pm_power_mode_t dblogic_mode; \ + (void) pm_get_resource_power_mode(SC_PT, SC_R_DBLOGIC, &dblogic_mode); \ + pm_force_resource_power_mode_v(SC_R_DBLOGIC, SC_PM_PW_MODE_ON); \ + sc_pm_power_mode_t db_mode[SC_NUM_DB]; \ + for (uint8_t db = 0U; db < SC_NUM_DB; db++) \ + { \ + (void) pm_get_resource_power_mode(SC_PT, sc_db_info[db].rsrc, &db_mode[db]); \ + pm_force_resource_power_mode_v(sc_db_info[db].rsrc, SC_PM_PW_MODE_ON); \ + } + +#define TEST_SC_END \ + for (uint8_t db = SC_NUM_DB; db > 0U; db--) \ + { \ + if (db_mode[db - 1U] == SC_PM_PW_MODE_OFF) \ + { \ + pm_force_resource_power_mode_v(sc_db_info[db - 1U].rsrc, SC_PM_PW_MODE_OFF); \ + } \ + } \ + if (dblogic_mode == SC_PM_PW_MODE_OFF) \ + pm_force_resource_power_mode_v(SC_R_DBLOGIC, SC_PM_PW_MODE_OFF); \ + test_print(TL1, "\n") + +#define TEST_AP_START(X) \ + sc_ipc_t ipc_sc; \ + test_print(TL1, "\n*** %s AP Test\n\n", X); \ + sc_ipc_open(&ipc_sc, (sc_ipc_id_t) MU_SC_1A); \ + (void) sc_rm_set_peripheral_permissions(ipc_sc, SC_R_MU_0A, SC_PT, SC_RM_PERM_FULL) + +#define TEST_AP_END \ + sc_ipc_close(ipc_sc); \ + test_print(TL1, "\n") + +#define TEST_DRV(X) sc_err_t test_drv_ ## X(sc_bool_t *const stop) +#define TEST_SC(X) sc_err_t test_sc_ ## X(sc_bool_t *const stop) +#define TEST_AP(X) sc_err_t test_ap_ ## X(sc_bool_t *const stop) + +#define TEST_PROTO(X) sc_err_t test_drv_ ## X(sc_bool_t *const stop); \ + sc_err_t test_sc_ ## X(sc_bool_t *const stop); \ + sc_err_t test_ap_ ## X(sc_bool_t *const stop); + +#define DBGSTR_PU "Power up %s\n" +#define DBGSTR_PD "Power down %s\n" +#define DBGSTR_TRY "Try %s access...\n" +#define DBGSTR_READ_GPIO "Read from GPIO_%s = 0x%08x\n" +#define DBGSTR_READ_IGPIO "Read from GPIO_%u = 0x%08x\n" +#define DBGSTR_READ_MU "Read from MU_%s.SR = 0x%08x\n" +#define DBGSTR_READ_UART "Read from UART_%s.VERID = 0x%08x\n" +#define DBGSTR_READ_I2C "Read from I2C_%s.VERID = 0x%08x\n" +#define DBGSTR_READ_LPCG "Read from LPCG_%s = 0x%08x\n" + +#define TEST_RSRC_NUM 43U + +#define TEST_READ32(X) test_read32(U32(X)) +#define TEST_WRITE32(X,Y) test_write32(U32(X), (Y)) +#define TEST_CHECK32(X,Y) test_check32(U32(X), (Y)) +#define TEST_NO_READ32(X) test_pid32(0U, U32(X), SC_TRUE) +#define TEST_PID_READ32(X,Y) test_pid32((X), U32(Y), SC_FALSE) +#define TEST_PID_NO_READ32(X,Y) test_pid32((X), U32(Y), SC_TRUE) + +/* Types */ + +/* Enums */ + +/* Sub Includes */ + +/* Functions */ + +#if defined(HAS_TEST) || defined(DEBUG) +TEST_PROTO(all) +<% $counter = 0 %> +<%PROTO_LIST%> +TEST_PROTO($tests[$counter]) +<% $counter++; return 'PROTO_LIST' if $counter < scalar(@tests); '' %> +#endif + +sc_err_t test_force_power(sc_rsrc_t resource, sc_pm_power_mode_t mode); +sc_err_t test_power(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_power_mode_t mode); +sc_err_t test_force_power_list_on(const sc_rsrc_t *resource, uint32_t num); +sc_err_t test_force_power_list_off(const sc_rsrc_t *resource, uint32_t num); +sc_err_t test_power_list_on(sc_ipc_t ipc, const sc_rsrc_t *resource, + uint32_t num); +sc_err_t test_power_list_off(sc_ipc_t ipc, const sc_rsrc_t *resource, + uint32_t num); +uint32_t test_read32(uint32_t addr); +void test_write32(uint32_t addr, uint32_t val); +void test_check32(uint32_t addr, uint32_t val); +void test_pid32(uint32_t pid, uint32_t addr, sc_bool_t fail); +void test_reset(sc_rsrc_t resource, uint32_t addr, uint32_t val, + uint32_t reset_val); +sc_err_t test_clock_rate_change(sc_ipc_t ipc, sc_rsrc_t resource, + sc_pm_clk_t clk, uint32_t new_rate); + +/* External Variables. */ + +extern sc_bool_t dma_up_down; +extern volatile uint32_t test_val; +extern const sc_rsrc_t test_rsrc_list[TEST_RSRC_NUM]; + +#endif /* SC_TEST_H */ + diff --git a/platform/test/mx8dxl/test.bom b/platform/test/mx8dxl/test.bom new file mode 100755 index 0000000..6b833fa --- /dev/null +++ b/platform/test/mx8dxl/test.bom @@ -0,0 +1,96 @@ +## ################################################################### +## +## Copyright 2020 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +# This BOM will include tests applicable in a T=all build + +AUTO_TEST += drv/test_dsc.o \ + drv/test_pll.o \ + drv/test_snvs.o \ + drv/test_pmic.o \ + ss/test_dblogic.o \ + ss/test_db.o \ + ss/test_drc.o \ + ss/test_lsio.o \ + ss/test_dma.o \ + ss/test_conn.o \ + ss/test_ap.o \ + ss/test_audio.o \ + ss/test_hsio.o \ + ss/test_mcu.o \ + ss/test_v2x.o \ + misc/test_pd.o \ + svc/test_pm.o \ + svc/test_timer.o \ + svc/test_rm.o \ + svc/test_misc.o \ + svc/test_pad.o \ + svc/test_rm2.o \ + svc/test_seco.o \ + ddr/test_hexdump.o \ + ddr/test_ddr.o \ + misc/test_audio_pll.o \ + sys/test_temp.o \ + sys/test_uboot.o \ + sys/test_xrdc.o \ + sys/test_dump.o \ + sys/test_rpc.o + +EXPT_TEST += ddr/test_ddr_retention.o \ + ddr/test_ddr_selfrefresh.o \ + drv/test_drv.o \ + drv/test_lpi2c.o \ + drv/test_otp.o \ + misc/test_bench.o \ + misc/test_boottime.o \ + misc/test_critsec.o \ + misc/test_examples.o \ + misc/test_fusewrite.o \ + misc/test_hmppm.o \ + misc/test_memreg.o \ + misc/test_mtemp.o \ + misc/test_nmi_ecc.o \ + misc/test_nmi_lockup.o \ + misc/test_nmi_msi.o \ + misc/test_obd.o \ + misc/test_osc24trim.o \ + misc/test_pllchar.o \ + misc/test_powerall.o \ + misc/test_profile.o \ + misc/test_refgencal.o \ + misc/test_timers.o \ + sys/test_board.o \ + sys/test_boot.o \ + sys/test_partnum.o \ + sys/test_reboot.o \ + sys/test_smmu.o \ + sys/test_wdog.o + diff --git a/platform/test/mx8qm/test.bom b/platform/test/mx8qm/test.bom new file mode 100755 index 0000000..36e7165 --- /dev/null +++ b/platform/test/mx8qm/test.bom @@ -0,0 +1,109 @@ +## ################################################################### +## +## Copyright 2020 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +# This BOM will include tests applicable in a T=all build + +AUTO_TEST += drv/test_dsc.o \ + drv/test_pll.o \ + drv/test_snvs.o \ + drv/test_pmic.o \ + ss/test_dblogic.o \ + ss/test_db.o \ + ss/test_drc.o \ + ss/test_lsio.o \ + ss/test_dma.o \ + ss/test_conn.o \ + ss/test_cci.o \ + ss/test_ap.o \ + ss/test_audio.o \ + ss/test_dc.o \ + ss/test_mipi.o \ + ss/test_lvds.o \ + ss/test_dc_lvds.o \ + ss/test_hdmi.o \ + ss/test_img.o \ + ss/test_csi.o \ + ss/test_hdmi_rx.o \ + ss/test_gpu.o \ + ss/test_vpu.o \ + ss/test_hsio.o \ + ss/test_mcu.o \ + ss/test_lcdif.o \ + ss/test_isi.o \ + misc/test_pd.o \ + svc/test_pm.o \ + svc/test_timer.o \ + svc/test_rm.o \ + svc/test_misc.o \ + svc/test_pad.o \ + svc/test_rm2.o \ + svc/test_seco.o \ + ddr/test_hexdump.o \ + ddr/test_ddr.o \ + misc/test_audio_pll.o \ + sys/test_temp.o \ + sys/test_uboot.o \ + sys/test_xrdc.o \ + sys/test_dump.o \ + sys/test_rpc.o + +EXPT_TEST += ddr/test_ddr_retention.o \ + ddr/test_ddr_selfrefresh.o \ + drv/test_drv.o \ + drv/test_lpi2c.o \ + drv/test_otp.o \ + misc/test_bench.o \ + misc/test_boottime.o \ + misc/test_critsec.o \ + misc/test_examples.o \ + misc/test_fusedump.o \ + misc/test_fusewrite.o \ + misc/test_hmppm.o \ + misc/test_memreg.o \ + misc/test_mtemp.o \ + misc/test_nmi_ecc.o \ + misc/test_nmi_lockup.o \ + misc/test_nmi_msi.o \ + misc/test_obd.o \ + misc/test_osc24trim.o \ + misc/test_pllchar.o \ + misc/test_powerall.o \ + misc/test_profile.o \ + misc/test_refgencal.o \ + misc/test_timers.o \ + sys/test_board.o \ + sys/test_boot.o \ + sys/test_partnum.o \ + sys/test_reboot.o \ + sys/test_smmu.o \ + sys/test_wdog.o + diff --git a/platform/test/mx8qx/test.bom b/platform/test/mx8qx/test.bom new file mode 100755 index 0000000..af630cf --- /dev/null +++ b/platform/test/mx8qx/test.bom @@ -0,0 +1,106 @@ +## ################################################################### +## +## Copyright 2020 NXP +## +## Redistribution and use in source and binary forms, with or without modification, +## are permitted provided that the following conditions are met: +## +## o Redistributions of source code must retain the above copyright notice, this list +## of conditions and the following disclaimer. +## +## o Redistributions in binary form must reproduce the above copyright notice, this +## list of conditions and the following disclaimer in the documentation and/or +## other materials provided with the distribution. +## +## o Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## +## ################################################################### + +# This BOM will include tests applicable in a T=all build + +AUTO_TEST += drv/test_dsc.o \ + drv/test_pll.o \ + drv/test_snvs.o \ + drv/test_pmic.o \ + ss/test_dblogic.o \ + ss/test_db.o \ + ss/test_drc.o \ + ss/test_lsio.o \ + ss/test_dma.o \ + ss/test_conn.o \ + ss/test_ap.o \ + ss/test_audio.o \ + ss/test_dc.o \ + ss/test_mipi.o \ + ss/test_lvds.o \ + ss/test_dc_lvds.o \ + ss/test_img.o \ + ss/test_csi.o \ + ss/test_pi.o \ + ss/test_gpu.o \ + ss/test_vpu.o \ + ss/test_hsio.o \ + ss/test_mcu.o \ + ss/test_isi.o \ + ss/test_lcdif.o \ + misc/test_pd.o \ + svc/test_pm.o \ + svc/test_timer.o \ + svc/test_rm.o \ + svc/test_misc.o \ + svc/test_pad.o \ + svc/test_rm2.o \ + svc/test_seco.o \ + ddr/test_hexdump.o \ + ddr/test_ddr.o \ + misc/test_audio_pll.o \ + sys/test_temp.o \ + sys/test_uboot.o \ + sys/test_xrdc.o \ + sys/test_dump.o \ + sys/test_rpc.o + +EXPT_TEST += ddr/test_ddr_retention.o \ + ddr/test_ddr_selfrefresh.o \ + drv/test_drv.o \ + drv/test_lpi2c.o \ + drv/test_otp.o \ + misc/test_bench.o \ + misc/test_boottime.o \ + misc/test_critsec.o \ + misc/test_examples.o \ + misc/test_fusewrite.o \ + misc/test_hmppm.o \ + misc/test_memreg.o \ + misc/test_mtemp.o \ + misc/test_nmi_ecc.o \ + misc/test_nmi_lockup.o \ + misc/test_nmi_msi.o \ + misc/test_obd.o \ + misc/test_osc24trim.o \ + misc/test_pllchar.o \ + misc/test_powerall.o \ + misc/test_profile.o \ + misc/test_refgencal.o \ + misc/test_timers.o \ + sys/test_board.o \ + sys/test_boot.o \ + sys/test_partnum.o \ + sys/test_reboot.o \ + sys/test_smmu.o \ + sys/test_wdog.o + diff --git a/platform/utilities/Makefile b/platform/utilities/Makefile new file mode 100755 index 0000000..61ddc80 --- /dev/null +++ b/platform/utilities/Makefile @@ -0,0 +1,10 @@ + +ifeq ($(D),1) +objs_utilities := newlib_stubs.o + +OBJS += \ + $(foreach object,$(objs_utilities),$(OUT)/utilities/$(object)) + +DIRS += $(OUT)/utilities +endif +

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