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drivers/ata/ata_piix.c
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/* |
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* ata_piix.c - Intel PATA/SATA controllers * * Maintained by: Jeff Garzik <jgarzik@pobox.com> * Please ALWAYS copy linux-ide@vger.kernel.org * on emails. * * * Copyright 2003-2005 Red Hat Inc * Copyright 2003-2005 Jeff Garzik * * * Copyright header from piix.c: * * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
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* Copyright (C) 2003 Red Hat Inc |
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* * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; see the file COPYING. If not, write to * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. * * * libata documentation is available via 'make {ps|pdf}docs', * as Documentation/DocBook/libata.* * * Hardware documentation available at http://developer.intel.com/ * |
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* Documentation * Publically available from Intel web site. Errata documentation * is also publically available. As an aide to anyone hacking on this |
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* driver the list of errata that are relevant is below, going back to |
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* PIIX4. Older device documentation is now a bit tricky to find. * |
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* The chipsets all follow very much the same design. The original Triton |
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* series chipsets do _not_ support independant device timings, but this * is fixed in Triton II. With the odd mobile exception the chips then * change little except in gaining more modes until SATA arrives. This * driver supports only the chips with independant timing (that is those * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix * for the early chip drivers. * * Errata of note: * * Unfixable * PIIX4 errata #9 - Only on ultra obscure hw * ICH3 errata #13 - Not observed to affect real hw * by Intel * * Things we must deal with * PIIX4 errata #10 - BM IDE hang with non UDMA * (must stop/start dma to recover) * 440MX errata #15 - As PIIX4 errata #10 * PIIX4 errata #15 - Must not read control registers * during a PIO transfer * 440MX errata #13 - As PIIX4 errata #15 * ICH2 errata #21 - DMA mode 0 doesn't work right * ICH0/1 errata #55 - As ICH2 errata #21 * ICH2 spec c #9 - Extra operations needed to handle * drive hotswap [NOT YET SUPPORTED] * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary * and must be dword aligned * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
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* ICH7 errata #16 - MWDMA1 timings are incorrect |
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* * Should have been BIOS fixed: * 450NX: errata #19 - DMA hangs on old 450NX * 450NX: errata #20 - DMA hangs on old 450NX * 450NX: errata #25 - Corruption with DMA on old 450NX * ICH3 errata #15 - IDE deadlock under high load * (BIOS must set dev 31 fn 0 bit 23) * ICH3 errata #18 - Don't use native mode |
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*/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/gfp.h> |
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#include <scsi/scsi_host.h> #include <linux/libata.h> |
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#include <linux/dmi.h> |
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#define DRV_NAME "ata_piix" |
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#define DRV_VERSION "2.13" |
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enum { PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ ICH5_PMR = 0x90, /* port mapping register */ ICH5_PCS = 0x92, /* port control and status */ |
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PIIX_SIDPR_BAR = 5, PIIX_SIDPR_LEN = 16, PIIX_SIDPR_IDX = 0, PIIX_SIDPR_DATA = 4, |
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PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
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PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ |
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PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, |
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PIIX_80C_PRI = (1 << 5) | (1 << 4), PIIX_80C_SEC = (1 << 7) | (1 << 6), |
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/* constants for mapping table */ P0 = 0, /* port 0 */ P1 = 1, /* port 1 */ P2 = 2, /* port 2 */ P3 = 3, /* port 3 */ IDE = -1, /* IDE */ NA = -2, /* not avaliable */ RV = -3, /* reserved */ |
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PIIX_AHCI_DEVICE = 6, |
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/* host->flags bits */ PIIX_HOST_BROKEN_SUSPEND = (1 << 24), |
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}; |
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enum piix_controller_ids { /* controller IDs */ piix_pata_mwdma, /* PIIX3 MWDMA only */ piix_pata_33, /* PIIX4 at 33Mhz */ ich_pata_33, /* ICH up to UDMA 33 only */ ich_pata_66, /* ICH up to 66 Mhz */ ich_pata_100, /* ICH up to UDMA 100 */ |
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ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/ |
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ich5_sata, ich6_sata, |
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ich6m_sata, ich8_sata, |
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ich8_2port_sata, |
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ich8m_apple_sata, /* locks up on second port enable */ tolapai_sata, |
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piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ }; |
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struct piix_map_db { const u32 mask; |
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const u16 port_enable; |
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const int map[][4]; }; |
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struct piix_host_priv { const int *map; |
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u32 saved_iocfg; |
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spinlock_t sidpr_lock; /* FIXME: remove once locking in EH is fixed */ |
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void __iomem *sidpr; |
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}; |
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static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
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static void piix_remove_one(struct pci_dev *pdev); |
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static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); |
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static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); |
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static int ich_pata_cable_detect(struct ata_port *ap); |
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static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
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static int piix_sidpr_scr_read(struct ata_link *link, unsigned int reg, u32 *val); static int piix_sidpr_scr_write(struct ata_link *link, unsigned int reg, u32 val); |
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static bool piix_irq_check(struct ata_port *ap); |
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#ifdef CONFIG_PM static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); static int piix_pci_device_resume(struct pci_dev *pdev); #endif |
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static unsigned int in_module_init = 1; |
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static const struct pci_device_id piix_pci_tbl[] = { |
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/* Intel PIIX3 for the 430HX etc */ { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, |
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/* VMware ICH4 */ { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, |
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/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
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/* Intel PIIX4 */ { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, /* Intel PIIX4 */ { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, /* Intel PIIX */ { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, /* Intel ICH (i810, i815, i840) UDMA 66*/ { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, /* Intel ICH0 : UDMA 33*/ { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, /* Intel ICH2M */ { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* Intel ICH3M */ { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* Intel ICH3 (E7500/1) UDMA 100 */ { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* Intel ICH5 */ |
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{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
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/* C-ICH (i810E2) */ { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
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/* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
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{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* ICH6 (and 6) (i915) UDMA 100 */ { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, /* ICH7/7-R (i945, i975) UDMA 100*/ |
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{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 }, |
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/* ICH8 Mobile PATA Controller */ { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
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/* SATA ports */ |
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/* 82801EB (ICH5) */ |
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{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
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/* 82801EB (ICH5) */ |
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{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
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/* 6300ESB (ICH5 variant with broken PCS present bits) */ |
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{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
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/* 6300ESB pretending RAID */ |
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{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
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/* 82801FB/FW (ICH6/ICH6W) */ |
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{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
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/* 82801FR/FRW (ICH6R/ICH6RW) */ |
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{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
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/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). * Attach iff the controller is in IDE mode. */ { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, |
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PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, |
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/* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
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{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
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/* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, |
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/* Enterprise Southbridge 2 (631xESB/632xESB) */ |
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{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
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/* SATA Controller 1 IDE (ICH8) */ |
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{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller 2 IDE (ICH8) */ |
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{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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/* Mobile SATA Controller IDE (ICH8M), Apple */ |
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{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, |
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{ 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, |
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{ 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, |
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/* Mobile SATA Controller IDE (ICH8M) */ { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller IDE (ICH9) */ |
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{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller IDE (ICH9) */ |
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{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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/* SATA Controller IDE (ICH9) */ |
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{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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/* SATA Controller IDE (ICH9M) */ |
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{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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/* SATA Controller IDE (ICH9M) */ |
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{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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/* SATA Controller IDE (ICH9M) */ |
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{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller IDE (Tolapai) */ |
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{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, |
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/* SATA Controller IDE (ICH10) */ |
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{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller IDE (ICH10) */ { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (ICH10) */ |
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{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller IDE (ICH10) */ { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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/* SATA Controller IDE (PCH) */ { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, /* SATA Controller IDE (PCH) */ |
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{ 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (PCH) */ |
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{ 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (PCH) */ |
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{ 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, /* SATA Controller IDE (PCH) */ |
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{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (PCH) */ { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
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/* SATA Controller IDE (CPT) */ { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, /* SATA Controller IDE (CPT) */ { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, /* SATA Controller IDE (CPT) */ { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, /* SATA Controller IDE (CPT) */ { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
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{ } /* terminate list */ }; static struct pci_driver piix_pci_driver = { .name = DRV_NAME, .id_table = piix_pci_tbl, .probe = piix_init_one, |
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.remove = piix_remove_one, |
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#ifdef CONFIG_PM |
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.suspend = piix_pci_device_suspend, .resume = piix_pci_device_resume, |
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#endif |
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}; |
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static struct scsi_host_template piix_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations piix_sata_ops = { |
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.inherits = &ata_bmdma32_port_ops, |
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.sff_irq_check = piix_irq_check, }; static struct ata_port_operations piix_pata_ops = { .inherits = &piix_sata_ops, |
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.cable_detect = ata_cable_40wire, |
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.set_piomode = piix_set_piomode, .set_dmamode = piix_set_dmamode, |
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.prereset = piix_pata_prereset, |
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}; |
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static struct ata_port_operations piix_vmw_ops = { .inherits = &piix_pata_ops, .bmdma_status = piix_vmw_bmdma_status, |
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}; |
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static struct ata_port_operations ich_pata_ops = { .inherits = &piix_pata_ops, .cable_detect = ich_pata_cable_detect, .set_dmamode = ich_set_dmamode, |
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}; |
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static struct ata_port_operations piix_sidpr_sata_ops = { .inherits = &piix_sata_ops, |
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.hardreset = sata_std_hardreset, |
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.scr_read = piix_sidpr_scr_read, .scr_write = piix_sidpr_scr_write, |
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}; |
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static const struct piix_map_db ich5_map_db = { |
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.mask = 0x7, |
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.port_enable = 0x3, |
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.map = { /* PM PS SM SS MAP */ { P0, NA, P1, NA }, /* 000b */ { P1, NA, P0, NA }, /* 001b */ { RV, RV, RV, RV }, { RV, RV, RV, RV }, { P0, P1, IDE, IDE }, /* 100b */ { P1, P0, IDE, IDE }, /* 101b */ { IDE, IDE, P0, P1 }, /* 110b */ { IDE, IDE, P1, P0 }, /* 111b */ }, }; |
d96715c1a
|
356 |
static const struct piix_map_db ich6_map_db = { |
d33f58b88
|
357 |
.mask = 0x3, |
ea35d29e2
|
358 |
.port_enable = 0xf, |
d33f58b88
|
359 360 |
.map = { /* PM PS SM SS MAP */ |
79ea24e72
|
361 |
{ P0, P2, P1, P3 }, /* 00b */ |
d33f58b88
|
362 363 364 365 366 |
{ IDE, IDE, P1, P3 }, /* 01b */ { P0, P2, IDE, IDE }, /* 10b */ { RV, RV, RV, RV }, }, }; |
d96715c1a
|
367 |
static const struct piix_map_db ich6m_map_db = { |
d33f58b88
|
368 |
.mask = 0x3, |
ea35d29e2
|
369 |
.port_enable = 0x5, |
670837417
|
370 371 |
/* Map 01b isn't specified in the doc but some notebooks use |
c6446a4cd
|
372 373 |
* it anyway. MAP 01b have been spotted on both ICH6M and * ICH7M. |
670837417
|
374 375 376 |
*/ .map = { /* PM PS SM SS MAP */ |
e04b3b9d0
|
377 |
{ P0, P2, NA, NA }, /* 00b */ |
670837417
|
378 379 380 381 382 |
{ IDE, IDE, P1, P3 }, /* 01b */ { P0, P2, IDE, IDE }, /* 10b */ { RV, RV, RV, RV }, }, }; |
08f12edc3
|
383 384 |
static const struct piix_map_db ich8_map_db = { .mask = 0x3, |
a0ce9aca9
|
385 |
.port_enable = 0xf, |
08f12edc3
|
386 387 |
.map = { /* PM PS SM SS MAP */ |
158f30c89
|
388 |
{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc3
|
389 |
{ RV, RV, RV, RV }, |
ac2b04371
|
390 |
{ P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc3
|
391 392 393 |
{ RV, RV, RV, RV }, }, }; |
00242ec87
|
394 |
static const struct piix_map_db ich8_2port_map_db = { |
e2d352af6
|
395 396 397 398 399 400 401 402 403 |
.mask = 0x3, .port_enable = 0x3, .map = { /* PM PS SM SS MAP */ { P0, NA, P1, NA }, /* 00b */ { RV, RV, RV, RV }, /* 01b */ { RV, RV, RV, RV }, /* 10b */ { RV, RV, RV, RV }, }, |
c5cf0ffa7
|
404 |
}; |
8d8ef2fb9
|
405 406 407 408 409 410 411 412 413 414 415 |
static const struct piix_map_db ich8m_apple_map_db = { .mask = 0x3, .port_enable = 0x1, .map = { /* PM PS SM SS MAP */ { P0, NA, NA, NA }, /* 00b */ { RV, RV, RV, RV }, { P0, P2, IDE, IDE }, /* 10b */ { RV, RV, RV, RV }, }, }; |
00242ec87
|
416 |
static const struct piix_map_db tolapai_map_db = { |
8f73a6880
|
417 418 419 420 421 422 423 424 425 426 |
.mask = 0x3, .port_enable = 0x3, .map = { /* PM PS SM SS MAP */ { P0, NA, P1, NA }, /* 00b */ { RV, RV, RV, RV }, /* 01b */ { RV, RV, RV, RV }, /* 10b */ { RV, RV, RV, RV }, }, }; |
d96715c1a
|
427 428 |
static const struct piix_map_db *piix_map_db_table[] = { [ich5_sata] = &ich5_map_db, |
d96715c1a
|
429 |
[ich6_sata] = &ich6_map_db, |
9c0bf6750
|
430 431 |
[ich6m_sata] = &ich6m_map_db, [ich8_sata] = &ich8_map_db, |
00242ec87
|
432 |
[ich8_2port_sata] = &ich8_2port_map_db, |
9c0bf6750
|
433 434 |
[ich8m_apple_sata] = &ich8m_apple_map_db, [tolapai_sata] = &tolapai_map_db, |
d96715c1a
|
435 |
}; |
1da177e4c
|
436 |
static struct ata_port_info piix_port_info[] = { |
00242ec87
|
437 438 |
[piix_pata_mwdma] = /* PIIX3 MWDMA only */ { |
00242ec87
|
439 |
.flags = PIIX_PATA_FLAGS, |
14bdef982
|
440 441 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
00242ec87
|
442 443 |
.port_ops = &piix_pata_ops, }, |
ec300d99e
|
444 |
[piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b8
|
445 |
{ |
b3362f88a
|
446 |
.flags = PIIX_PATA_FLAGS, |
14bdef982
|
447 448 449 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ .udma_mask = ATA_UDMA2, |
1d076e5b8
|
450 451 |
.port_ops = &piix_pata_ops, }, |
ec300d99e
|
452 |
[ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db41
|
453 |
{ |
b3362f88a
|
454 |
.flags = PIIX_PATA_FLAGS, |
14bdef982
|
455 456 457 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */ .udma_mask = ATA_UDMA2, |
669a5db41
|
458 459 |
.port_ops = &ich_pata_ops, }, |
ec300d99e
|
460 461 |
[ich_pata_66] = /* ICH controllers up to 66MHz */ |
1da177e4c
|
462 |
{ |
b3362f88a
|
463 |
.flags = PIIX_PATA_FLAGS, |
14bdef982
|
464 465 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */ |
669a5db41
|
466 467 468 |
.udma_mask = ATA_UDMA4, .port_ops = &ich_pata_ops, }, |
85cd7251b
|
469 |
|
ec300d99e
|
470 |
[ich_pata_100] = |
669a5db41
|
471 |
{ |
b3362f88a
|
472 |
.flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
14bdef982
|
473 474 475 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, .udma_mask = ATA_UDMA5, |
669a5db41
|
476 |
.port_ops = &ich_pata_ops, |
1da177e4c
|
477 |
}, |
c611bed78
|
478 479 480 481 482 483 484 485 |
[ich_pata_100_nomwdma1] = { .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2_ONLY, .udma_mask = ATA_UDMA5, .port_ops = &ich_pata_ops, }, |
ec300d99e
|
486 |
[ich5_sata] = |
1da177e4c
|
487 |
{ |
228c1590b
|
488 |
.flags = PIIX_SATA_FLAGS, |
14bdef982
|
489 490 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
491 |
.udma_mask = ATA_UDMA6, |
1da177e4c
|
492 493 |
.port_ops = &piix_sata_ops, }, |
ec300d99e
|
494 |
[ich6_sata] = |
1da177e4c
|
495 |
{ |
723159c58
|
496 |
.flags = PIIX_SATA_FLAGS, |
14bdef982
|
497 498 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
499 |
.udma_mask = ATA_UDMA6, |
1da177e4c
|
500 501 |
.port_ops = &piix_sata_ops, }, |
9c0bf6750
|
502 |
[ich6m_sata] = |
c368ca4ef
|
503 |
{ |
5016d7d21
|
504 |
.flags = PIIX_SATA_FLAGS, |
14bdef982
|
505 506 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
507 |
.udma_mask = ATA_UDMA6, |
c368ca4ef
|
508 509 |
.port_ops = &piix_sata_ops, }, |
1d076e5b8
|
510 |
|
9c0bf6750
|
511 |
[ich8_sata] = |
08f12edc3
|
512 |
{ |
5016d7d21
|
513 |
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
14bdef982
|
514 515 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
516 |
.udma_mask = ATA_UDMA6, |
08f12edc3
|
517 518 |
.port_ops = &piix_sata_ops, }, |
669a5db41
|
519 |
|
00242ec87
|
520 |
[ich8_2port_sata] = |
c5cf0ffa7
|
521 |
{ |
5016d7d21
|
522 |
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
14bdef982
|
523 524 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
c5cf0ffa7
|
525 526 527 |
.udma_mask = ATA_UDMA6, .port_ops = &piix_sata_ops, }, |
8f73a6880
|
528 |
|
9c0bf6750
|
529 |
[tolapai_sata] = |
8f73a6880
|
530 |
{ |
5016d7d21
|
531 |
.flags = PIIX_SATA_FLAGS, |
14bdef982
|
532 533 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
8f73a6880
|
534 535 536 |
.udma_mask = ATA_UDMA6, .port_ops = &piix_sata_ops, }, |
8d8ef2fb9
|
537 |
|
9c0bf6750
|
538 |
[ich8m_apple_sata] = |
8d8ef2fb9
|
539 |
{ |
23cf296e3
|
540 |
.flags = PIIX_SATA_FLAGS, |
14bdef982
|
541 542 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
8d8ef2fb9
|
543 544 545 |
.udma_mask = ATA_UDMA6, .port_ops = &piix_sata_ops, }, |
25f98131a
|
546 547 |
[piix_pata_vmw] = { |
25f98131a
|
548 |
.flags = PIIX_PATA_FLAGS, |
14bdef982
|
549 550 551 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ .udma_mask = ATA_UDMA2, |
25f98131a
|
552 553 |
.port_ops = &piix_vmw_ops, }, |
1da177e4c
|
554 555 556 557 558 559 560 561 562 563 564 565 |
}; static struct pci_bits piix_enable_bits[] = { { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ }; MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, piix_pci_tbl); MODULE_VERSION(DRV_VERSION); |
fc085150b
|
566 567 568 569 570 571 572 573 574 575 576 577 578 |
struct ich_laptop { u16 device; u16 subvendor; u16 subdevice; }; /* * List of laptops that use short cables rather than 80 wire */ static const struct ich_laptop ich_laptop[] = { /* devid, subvendor, subdev */ { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
2655e2cee
|
579 |
{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
babfb682c
|
580 |
{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
6034734d3
|
581 |
{ 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */ |
123401068
|
582 |
{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
54174db30
|
583 |
{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
af901ca18
|
584 |
{ 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */ |
d09addf65
|
585 |
{ 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */ |
6034734d3
|
586 |
{ 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */ |
b33620f9f
|
587 |
{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
e1fefea9c
|
588 589 |
{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ |
01ce2601e
|
590 |
{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
124a6eece
|
591 |
{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */ |
fc085150b
|
592 593 594 |
/* end marker */ { 0, } }; |
1da177e4c
|
595 |
/** |
eb4a2c7f0
|
596 |
* ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4c
|
597 598 599 600 601 602 603 604 |
* @ap: Port for which cable detect info is desired * * Read 80c cable indicator from ATA PCI device's PCI config * register. This register is normally set by firmware (BIOS). * * LOCKING: * None (inherited from caller). */ |
669a5db41
|
605 |
|
eb4a2c7f0
|
606 |
static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4c
|
607 |
{ |
cca3974e4
|
608 |
struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
2852bcf7c
|
609 |
struct piix_host_priv *hpriv = ap->host->private_data; |
fc085150b
|
610 |
const struct ich_laptop *lap = &ich_laptop[0]; |
2852bcf7c
|
611 |
u8 mask; |
1da177e4c
|
612 |
|
fc085150b
|
613 614 615 616 |
/* Check for specials - Acer Aspire 5602WLMi */ while (lap->device) { if (lap->device == pdev->device && lap->subvendor == pdev->subsystem_vendor && |
2dcb407e6
|
617 |
lap->subdevice == pdev->subsystem_device) |
eb4a2c7f0
|
618 |
return ATA_CBL_PATA40_SHORT; |
2dcb407e6
|
619 |
|
fc085150b
|
620 621 |
lap++; } |
1da177e4c
|
622 |
/* check BIOS cable detect results */ |
2a88d1ac8
|
623 |
mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
2852bcf7c
|
624 |
if ((hpriv->saved_iocfg & mask) == 0) |
eb4a2c7f0
|
625 626 |
return ATA_CBL_PATA40; return ATA_CBL_PATA80; |
1da177e4c
|
627 628 629 |
} /** |
ccc4672af
|
630 |
* piix_pata_prereset - prereset for PATA host controller |
cc0680a58
|
631 |
* @link: Target link |
d4b2bab4f
|
632 |
* @deadline: deadline jiffies for the operation |
1da177e4c
|
633 |
* |
573db6b8f
|
634 635 636 |
* LOCKING: * None (inherited from caller). */ |
cc0680a58
|
637 |
static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4c
|
638 |
{ |
cc0680a58
|
639 |
struct ata_port *ap = link->ap; |
cca3974e4
|
640 |
struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4c
|
641 |
|
c961922b7
|
642 643 |
if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) return -ENOENT; |
9363c3825
|
644 |
return ata_sff_prereset(link, deadline); |
ccc4672af
|
645 |
} |
60c3be387
|
646 |
static DEFINE_SPINLOCK(piix_lock); |
1da177e4c
|
647 648 649 650 |
/** * piix_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: um |
1da177e4c
|
651 652 653 654 655 656 |
* * Set PIO mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller). */ |
2dcb407e6
|
657 |
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
1da177e4c
|
658 |
{ |
cca3974e4
|
659 |
struct pci_dev *dev = to_pci_dev(ap->host->dev); |
60c3be387
|
660 661 |
unsigned long flags; unsigned int pio = adev->pio_mode - XFER_PIO_0; |
1da177e4c
|
662 |
unsigned int is_slave = (adev->devno != 0); |
2a88d1ac8
|
663 |
unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4c
|
664 665 666 |
unsigned int slave_port = 0x44; u16 master_data; u8 slave_data; |
669a5db41
|
667 668 |
u8 udma_enable; int control = 0; |
85cd7251b
|
669 |
|
669a5db41
|
670 671 672 673 |
/* * See Intel Document 298600-004 for the timing programing rules * for ICH controllers. */ |
1da177e4c
|
674 675 676 677 678 679 680 |
static const /* ISP RTC */ u8 timings[][2] = { { 0, 0 }, { 0, 0 }, { 1, 0 }, { 2, 1 }, { 2, 3 }, }; |
669a5db41
|
681 682 683 684 |
if (pio >= 2) control |= 1; /* TIME1 enable */ if (ata_pio_need_iordy(adev)) control |= 2; /* IE enable */ |
85cd7251b
|
685 |
/* Intel specifies that the PPE functionality is for disk only */ |
669a5db41
|
686 687 |
if (adev->class == ATA_DEV_ATA) control |= 4; /* PPE enable */ |
60c3be387
|
688 |
spin_lock_irqsave(&piix_lock, flags); |
a5bf5f5a3
|
689 690 691 692 |
/* PIO configuration clears DTE unconditionally. It will be * programmed in set_dmamode which is guaranteed to be called * after set_piomode if any DMA mode is available. */ |
1da177e4c
|
693 694 |
pci_read_config_word(dev, master_port, &master_data); if (is_slave) { |
a5bf5f5a3
|
695 696 |
/* clear TIME1|IE1|PPE1|DTE1 */ master_data &= 0xff0f; |
1967b7ff7
|
697 |
/* Enable SITRE (separate slave timing register) */ |
1da177e4c
|
698 |
master_data |= 0x4000; |
669a5db41
|
699 700 |
/* enable PPE1, IE1 and TIME1 as needed */ master_data |= (control << 4); |
1da177e4c
|
701 |
pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac8
|
702 |
slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db41
|
703 |
/* Load the timing nibble for this slave */ |
a5bf5f5a3
|
704 705 |
slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
1da177e4c
|
706 |
} else { |
a5bf5f5a3
|
707 708 |
/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ master_data &= 0xccf0; |
669a5db41
|
709 710 |
/* Enable PPE, IE and TIME as appropriate */ master_data |= control; |
a5bf5f5a3
|
711 |
/* load ISP and RCT */ |
1da177e4c
|
712 713 714 715 716 717 718 |
master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); } pci_write_config_word(dev, master_port, master_data); if (is_slave) pci_write_config_byte(dev, slave_port, slave_data); |
669a5db41
|
719 720 721 |
/* Ensure the UDMA bit is off - it will be turned back on if UDMA is selected */ |
85cd7251b
|
722 |
|
669a5db41
|
723 724 725 726 727 |
if (ap->udma_mask) { pci_read_config_byte(dev, 0x48, &udma_enable); udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); pci_write_config_byte(dev, 0x48, udma_enable); } |
60c3be387
|
728 729 |
spin_unlock_irqrestore(&piix_lock, flags); |
1da177e4c
|
730 731 732 |
} /** |
669a5db41
|
733 |
* do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4c
|
734 |
* @ap: Port whose timings we are configuring |
669a5db41
|
735 |
* @adev: Drive in question |
c32a8fd7c
|
736 |
* @isich: set if the chip is an ICH device |
1da177e4c
|
737 738 739 740 741 742 |
* * Set UDMA mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller). */ |
2dcb407e6
|
743 |
static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4c
|
744 |
{ |
cca3974e4
|
745 |
struct pci_dev *dev = to_pci_dev(ap->host->dev); |
60c3be387
|
746 |
unsigned long flags; |
669a5db41
|
747 748 749 750 |
u8 master_port = ap->port_no ? 0x42 : 0x40; u16 master_data; u8 speed = adev->dma_mode; int devid = adev->devno + 2 * ap->port_no; |
dedf61db4
|
751 |
u8 udma_enable = 0; |
85cd7251b
|
752 |
|
669a5db41
|
753 754 755 756 757 758 |
static const /* ISP RTC */ u8 timings[][2] = { { 0, 0 }, { 0, 0 }, { 1, 0 }, { 2, 1 }, { 2, 3 }, }; |
60c3be387
|
759 |
spin_lock_irqsave(&piix_lock, flags); |
669a5db41
|
760 |
pci_read_config_word(dev, master_port, &master_data); |
d2cdfc0db
|
761 762 |
if (ap->udma_mask) pci_read_config_byte(dev, 0x48, &udma_enable); |
1da177e4c
|
763 764 |
if (speed >= XFER_UDMA_0) { |
669a5db41
|
765 766 767 768 |
unsigned int udma = adev->dma_mode - XFER_UDMA_0; u16 udma_timing; u16 ideconf; int u_clock, u_speed; |
85cd7251b
|
769 |
|
669a5db41
|
770 |
/* |
2dcb407e6
|
771 |
* UDMA is handled by a combination of clock switching and |
85cd7251b
|
772 773 |
* selection of dividers * |
669a5db41
|
774 |
* Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251b
|
775 |
* except UDMA0 which is 00 |
669a5db41
|
776 777 778 779 780 781 782 783 |
*/ u_speed = min(2 - (udma & 1), udma); if (udma == 5) u_clock = 0x1000; /* 100Mhz */ else if (udma > 2) u_clock = 1; /* 66Mhz */ else u_clock = 0; /* 33Mhz */ |
85cd7251b
|
784 |
|
669a5db41
|
785 |
udma_enable |= (1 << devid); |
85cd7251b
|
786 |
|
669a5db41
|
787 788 789 790 791 |
/* Load the CT/RP selection */ pci_read_config_word(dev, 0x4A, &udma_timing); udma_timing &= ~(3 << (4 * devid)); udma_timing |= u_speed << (4 * devid); pci_write_config_word(dev, 0x4A, udma_timing); |
85cd7251b
|
792 |
if (isich) { |
669a5db41
|
793 794 795 796 797 798 799 |
/* Select a 33/66/100Mhz clock */ pci_read_config_word(dev, 0x54, &ideconf); ideconf &= ~(0x1001 << devid); ideconf |= u_clock << devid; /* For ICH or later we should set bit 10 for better performance (WR_PingPong_En) */ pci_write_config_word(dev, 0x54, ideconf); |
1da177e4c
|
800 |
} |
1da177e4c
|
801 |
} else { |
669a5db41
|
802 803 804 805 806 807 808 809 810 811 812 813 |
/* * MWDMA is driven by the PIO timings. We must also enable * IORDY unconditionally along with TIME1. PPE has already * been set when the PIO timing was set. */ unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; unsigned int control; u8 slave_data; const unsigned int needed_pio[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; int pio = needed_pio[mwdma] - XFER_PIO_0; |
85cd7251b
|
814 |
|
669a5db41
|
815 |
control = 3; /* IORDY|TIME1 */ |
85cd7251b
|
816 |
|
669a5db41
|
817 818 |
/* If the drive MWDMA is faster than it can do PIO then we must force PIO into PIO0 */ |
85cd7251b
|
819 |
|
669a5db41
|
820 821 822 823 824 825 826 827 |
if (adev->pio_mode < needed_pio[mwdma]) /* Enable DMA timing only */ control |= 8; /* PIO cycles in PIO0 */ if (adev->devno) { /* Slave */ master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ master_data |= control << 4; pci_read_config_byte(dev, 0x44, &slave_data); |
a5bf5f5a3
|
828 |
slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db41
|
829 830 831 832 |
/* Load the matching timing */ slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); pci_write_config_byte(dev, 0x44, slave_data); } else { /* Master */ |
85cd7251b
|
833 |
master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db41
|
834 835 836 837 838 839 |
and master timing bits */ master_data |= control; master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); } |
a5bf5f5a3
|
840 |
|
693859437
|
841 |
if (ap->udma_mask) |
a5bf5f5a3
|
842 |
udma_enable &= ~(1 << devid); |
693859437
|
843 844 |
pci_write_config_word(dev, master_port, master_data); |
1da177e4c
|
845 |
} |
669a5db41
|
846 847 848 |
/* Don't scribble on 0x48 if the controller does not support UDMA */ if (ap->udma_mask) pci_write_config_byte(dev, 0x48, udma_enable); |
60c3be387
|
849 850 |
spin_unlock_irqrestore(&piix_lock, flags); |
669a5db41
|
851 852 853 854 855 856 857 858 859 860 861 862 |
} /** * piix_set_dmamode - Initialize host controller PATA DMA timings * @ap: Port whose timings we are configuring * @adev: um * * Set MW/UDMA mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller). */ |
2dcb407e6
|
863 |
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db41
|
864 865 866 867 868 869 870 871 872 873 874 875 876 877 |
{ do_pata_set_dmamode(ap, adev, 0); } /** * ich_set_dmamode - Initialize host controller PATA DMA timings * @ap: Port whose timings we are configuring * @adev: um * * Set MW/UDMA mode for device, in host controller PCI config space. * * LOCKING: * None (inherited from caller). */ |
2dcb407e6
|
878 |
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
669a5db41
|
879 880 |
{ do_pata_set_dmamode(ap, adev, 1); |
1da177e4c
|
881 |
} |
c72907245
|
882 883 884 885 |
/* * Serial ATA Index/Data Pair Superset Registers access * * Beginning from ICH8, there's a sane way to access SCRs using index |
be77e43ab
|
886 887 888 |
* and data register pair located at BAR5 which means that we have * separate SCRs for master and slave. This is handled using libata * slave_link facility. |
c72907245
|
889 890 891 892 893 894 |
*/ static const int piix_sidx_map[] = { [SCR_STATUS] = 0, [SCR_ERROR] = 2, [SCR_CONTROL] = 1, }; |
be77e43ab
|
895 |
static void piix_sidpr_sel(struct ata_link *link, unsigned int reg) |
c72907245
|
896 |
{ |
be77e43ab
|
897 |
struct ata_port *ap = link->ap; |
c72907245
|
898 |
struct piix_host_priv *hpriv = ap->host->private_data; |
be77e43ab
|
899 |
iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg], |
c72907245
|
900 901 |
hpriv->sidpr + PIIX_SIDPR_IDX); } |
82ef04fb4
|
902 903 |
static int piix_sidpr_scr_read(struct ata_link *link, unsigned int reg, u32 *val) |
c72907245
|
904 |
{ |
be77e43ab
|
905 |
struct piix_host_priv *hpriv = link->ap->host->private_data; |
213373cf9
|
906 |
unsigned long flags; |
c72907245
|
907 908 909 |
if (reg >= ARRAY_SIZE(piix_sidx_map)) return -EINVAL; |
213373cf9
|
910 |
spin_lock_irqsave(&hpriv->sidpr_lock, flags); |
be77e43ab
|
911 912 |
piix_sidpr_sel(link, reg); *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); |
213373cf9
|
913 |
spin_unlock_irqrestore(&hpriv->sidpr_lock, flags); |
c72907245
|
914 915 |
return 0; } |
82ef04fb4
|
916 917 |
static int piix_sidpr_scr_write(struct ata_link *link, unsigned int reg, u32 val) |
c72907245
|
918 |
{ |
be77e43ab
|
919 |
struct piix_host_priv *hpriv = link->ap->host->private_data; |
213373cf9
|
920 |
unsigned long flags; |
82ef04fb4
|
921 |
|
c72907245
|
922 923 |
if (reg >= ARRAY_SIZE(piix_sidx_map)) return -EINVAL; |
213373cf9
|
924 |
spin_lock_irqsave(&hpriv->sidpr_lock, flags); |
be77e43ab
|
925 926 |
piix_sidpr_sel(link, reg); iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); |
213373cf9
|
927 |
spin_unlock_irqrestore(&hpriv->sidpr_lock, flags); |
c72907245
|
928 929 |
return 0; } |
27943620c
|
930 931 932 933 934 935 936 |
static bool piix_irq_check(struct ata_port *ap) { if (unlikely(!ap->ioaddr.bmdma_addr)) return false; return ap->ops->bmdma_status(ap) & ATA_DMA_INTR; } |
b8b275efc
|
937 |
#ifdef CONFIG_PM |
8c3832ebe
|
938 939 |
static int piix_broken_suspend(void) { |
1855256c4
|
940 |
static const struct dmi_system_id sysids[] = { |
8c3832ebe
|
941 |
{ |
4c74d4ec3
|
942 943 944 945 946 947 948 |
.ident = "TECRA M3", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), }, }, { |
04d86d6fc
|
949 950 951 952 953 954 955 |
.ident = "TECRA M3", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), }, }, { |
d1aa690a7
|
956 957 958 959 960 961 962 |
.ident = "TECRA M4", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), }, }, { |
040dee53a
|
963 964 965 966 967 968 969 |
.ident = "TECRA M4", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), }, }, { |
8c3832ebe
|
970 971 972 973 974 |
.ident = "TECRA M5", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), }, |
b8b275efc
|
975 |
}, |
8c3832ebe
|
976 |
{ |
ffe188dd8
|
977 978 979 980 981 982 983 |
.ident = "TECRA M6", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), }, }, { |
5c08ea019
|
984 985 986 987 988 989 990 |
.ident = "TECRA M7", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), }, }, { |
04d86d6fc
|
991 992 993 994 995 996 997 |
.ident = "TECRA A8", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), }, }, { |
ffe188dd8
|
998 999 1000 1001 1002 1003 1004 |
.ident = "Satellite R20", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), }, }, { |
04d86d6fc
|
1005 1006 1007 1008 1009 1010 1011 |
.ident = "Satellite R25", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), }, }, { |
3cc0b9d3b
|
1012 1013 1014 1015 1016 1017 1018 |
.ident = "Satellite U200", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), }, }, { |
04d86d6fc
|
1019 1020 1021 1022 1023 1024 1025 |
.ident = "Satellite U200", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), }, }, { |
62320e23c
|
1026 1027 1028 1029 1030 1031 1032 |
.ident = "Satellite Pro U200", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), }, }, { |
8c3832ebe
|
1033 1034 1035 1036 1037 |
.ident = "Satellite U205", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), }, |
b8b275efc
|
1038 |
}, |
8c3832ebe
|
1039 |
{ |
de753e5e8
|
1040 1041 1042 1043 1044 1045 1046 |
.ident = "SATELLITE U205", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), }, }, { |
8c3832ebe
|
1047 1048 1049 1050 1051 |
.ident = "Portege M500", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), }, |
b8b275efc
|
1052 |
}, |
c3f93b8fc
|
1053 1054 1055 1056 1057 1058 1059 |
{ .ident = "VGN-BX297XP", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"), DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"), }, }, |
7d0515484
|
1060 1061 |
{ } /* terminate list */ |
8c3832ebe
|
1062 |
}; |
7abe79c35
|
1063 1064 1065 1066 |
static const char *oemstrs[] = { "Tecra M3,", }; int i; |
8c3832ebe
|
1067 1068 1069 |
if (dmi_check_system(sysids)) return 1; |
7abe79c35
|
1070 1071 1072 |
for (i = 0; i < ARRAY_SIZE(oemstrs); i++) if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) return 1; |
1eedb4a90
|
1073 1074 1075 1076 1077 1078 |
/* TECRA M4 sometimes forgets its identify and reports bogus * DMI information. As the bogus information is a bit * generic, match as many entries as possible. This manual * matching is necessary because dmi_system_id.matches is * limited to four entries. */ |
3c387730e
|
1079 1080 1081 1082 1083 1084 1085 |
if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") && dmi_match(DMI_PRODUCT_NAME, "000000") && dmi_match(DMI_PRODUCT_VERSION, "000000") && dmi_match(DMI_PRODUCT_SERIAL, "000000") && dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") && dmi_match(DMI_BOARD_NAME, "Portable PC") && dmi_match(DMI_BOARD_VERSION, "Version A0")) |
1eedb4a90
|
1086 |
return 1; |
8c3832ebe
|
1087 1088 |
return 0; } |
b8b275efc
|
1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 |
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) { struct ata_host *host = dev_get_drvdata(&pdev->dev); unsigned long flags; int rc = 0; rc = ata_host_suspend(host, mesg); if (rc) return rc; /* Some braindamaged ACPI suspend implementations expect the * controller to be awake on entry; otherwise, it burns cpu * cycles and power trying to do something to the sleeping * beauty. */ |
3a2d5b700
|
1105 |
if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { |
b8b275efc
|
1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 |
pci_save_state(pdev); /* mark its power state as "unknown", since we don't * know if e.g. the BIOS will change its device state * when we suspend. */ if (pdev->current_state == PCI_D0) pdev->current_state = PCI_UNKNOWN; /* tell resume that it's waking up from broken suspend */ spin_lock_irqsave(&host->lock, flags); host->flags |= PIIX_HOST_BROKEN_SUSPEND; spin_unlock_irqrestore(&host->lock, flags); } else ata_pci_device_do_suspend(pdev, mesg); return 0; } static int piix_pci_device_resume(struct pci_dev *pdev) { struct ata_host *host = dev_get_drvdata(&pdev->dev); unsigned long flags; int rc; if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { spin_lock_irqsave(&host->lock, flags); host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; spin_unlock_irqrestore(&host->lock, flags); pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); /* PCI device wasn't disabled during suspend. Use |
0b62e13b5
|
1140 1141 |
* pci_reenable_device() to avoid affecting the enable * count. |
b8b275efc
|
1142 |
*/ |
0b62e13b5
|
1143 |
rc = pci_reenable_device(pdev); |
b8b275efc
|
1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 |
if (rc) dev_printk(KERN_ERR, &pdev->dev, "failed to enable " "device after resume (%d) ", rc); } else rc = ata_pci_device_do_resume(pdev); if (rc == 0) ata_host_resume(host); return rc; } #endif |
25f98131a
|
1157 1158 1159 1160 |
static u8 piix_vmw_bmdma_status(struct ata_port *ap) { return ata_bmdma_status(ap) & ~ATA_DMA_ERR; } |
1da177e4c
|
1161 1162 1163 1164 1165 |
#define AHCI_PCI_BAR 5 #define AHCI_GLOBAL_CTL 0x04 #define AHCI_ENABLE (1 << 31) static int piix_disable_ahci(struct pci_dev *pdev) { |
ea6ba10bb
|
1166 |
void __iomem *mmio; |
1da177e4c
|
1167 1168 1169 1170 1171 1172 |
u32 tmp; int rc = 0; /* BUG: pci_enable_device has not yet been called. This * works because this device is usually set up by BIOS. */ |
374b18735
|
1173 1174 |
if (!pci_resource_start(pdev, AHCI_PCI_BAR) || !pci_resource_len(pdev, AHCI_PCI_BAR)) |
1da177e4c
|
1175 |
return 0; |
7b6dbd687
|
1176 |
|
374b18735
|
1177 |
mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4c
|
1178 1179 |
if (!mmio) return -ENOMEM; |
7b6dbd687
|
1180 |
|
c47a631f8
|
1181 |
tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4c
|
1182 1183 |
if (tmp & AHCI_ENABLE) { tmp &= ~AHCI_ENABLE; |
c47a631f8
|
1184 |
iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
1da177e4c
|
1185 |
|
c47a631f8
|
1186 |
tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
1da177e4c
|
1187 1188 1189 |
if (tmp & AHCI_ENABLE) rc = -EIO; } |
7b6dbd687
|
1190 |
|
374b18735
|
1191 |
pci_iounmap(pdev, mmio); |
1da177e4c
|
1192 1193 1194 1195 |
return rc; } /** |
c621b1406
|
1196 |
* piix_check_450nx_errata - Check for problem 450NX setup |
c893a3ae4
|
1197 |
* @ata_dev: the PCI device to check |
2e9edbf81
|
1198 |
* |
c621b1406
|
1199 1200 1201 1202 1203 1204 1205 1206 |
* Check for the present of 450NX errata #19 and errata #25. If * they are found return an error code so we can turn off DMA */ static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) { struct pci_dev *pdev = NULL; u16 cfg; |
c621b1406
|
1207 |
int no_piix_dma = 0; |
2e9edbf81
|
1208 |
|
2dcb407e6
|
1209 |
while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
c621b1406
|
1210 1211 |
/* Look for 450NX PXB. Check for problem configurations A PCI quirk checks bit 6 already */ |
c621b1406
|
1212 1213 |
pci_read_config_word(pdev, 0x41, &cfg); /* Only on the original revision: IDE DMA can hang */ |
44c10138f
|
1214 |
if (pdev->revision == 0x00) |
c621b1406
|
1215 1216 |
no_piix_dma = 1; /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
44c10138f
|
1217 |
else if (cfg & (1<<14) && pdev->revision < 5) |
c621b1406
|
1218 1219 |
no_piix_dma = 2; } |
31a34fe75
|
1220 |
if (no_piix_dma) |
c621b1406
|
1221 1222 |
dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA. "); |
31a34fe75
|
1223 |
if (no_piix_dma == 2) |
c621b1406
|
1224 1225 1226 |
dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this. "); return no_piix_dma; |
2e9edbf81
|
1227 |
} |
c621b1406
|
1228 |
|
8b09f0da0
|
1229 |
static void __devinit piix_init_pcs(struct ata_host *host, |
ea35d29e2
|
1230 1231 |
const struct piix_map_db *map_db) { |
8b09f0da0
|
1232 |
struct pci_dev *pdev = to_pci_dev(host->dev); |
ea35d29e2
|
1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 |
u16 pcs, new_pcs; pci_read_config_word(pdev, ICH5_PCS, &pcs); new_pcs = pcs | map_db->port_enable; if (new_pcs != pcs) { DPRINTK("updating PCS from 0x%x to 0x%x ", pcs, new_pcs); pci_write_config_word(pdev, ICH5_PCS, new_pcs); msleep(150); } } |
8b09f0da0
|
1246 1247 1248 |
static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, struct ata_port_info *pinfo, const struct piix_map_db *map_db) |
d33f58b88
|
1249 |
{ |
b4482a4b2
|
1250 |
const int *map; |
d33f58b88
|
1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 |
int i, invalid_map = 0; u8 map_value; pci_read_config_byte(pdev, ICH5_PMR, &map_value); map = map_db->map[map_value & map_db->mask]; dev_printk(KERN_INFO, &pdev->dev, "MAP ["); for (i = 0; i < 4; i++) { switch (map[i]) { case RV: invalid_map = 1; printk(" XX"); break; case NA: printk(" --"); break; case IDE: WARN_ON((i & 1) || map[i + 1] != IDE); |
669a5db41
|
1272 |
pinfo[i / 2] = piix_port_info[ich_pata_100]; |
d33f58b88
|
1273 1274 1275 1276 1277 1278 1279 |
i++; printk(" IDE IDE"); break; default: printk(" P%d", map[i]); if (i & 1) |
cca3974e4
|
1280 |
pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b88
|
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 |
break; } } printk(" ] "); if (invalid_map) dev_printk(KERN_ERR, &pdev->dev, "invalid MAP value %u ", map_value); |
8b09f0da0
|
1291 |
return map; |
d33f58b88
|
1292 |
} |
e9c1670c2
|
1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 |
static bool piix_no_sidpr(struct ata_host *host) { struct pci_dev *pdev = to_pci_dev(host->dev); /* * Samsung DB-P70 only has three ATA ports exposed and * curiously the unconnected first port reports link online * while not responding to SRST protocol causing excessive * detection delay. * * Unfortunately, the system doesn't carry enough DMI * information to identify the machine but does have subsystem * vendor and device set. As it's unclear whether the * subsystem vendor/device is used only for this specific * board, the port can't be disabled solely with the * information; however, turning off SIDPR access works around * the problem. Turn it off. * * This problem is reported in bnc#441240. * * https://bugzilla.novell.com/show_bug.cgi?id=441420 */ if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && pdev->subsystem_device == 0xb049) { dev_printk(KERN_WARNING, host->dev, "Samsung DB-P70 detected, disabling SIDPR "); return true; } return false; } |
be77e43ab
|
1326 |
static int __devinit piix_init_sidpr(struct ata_host *host) |
c72907245
|
1327 1328 1329 |
{ struct pci_dev *pdev = to_pci_dev(host->dev); struct piix_host_priv *hpriv = host->private_data; |
be77e43ab
|
1330 |
struct ata_link *link0 = &host->ports[0]->link; |
cb6716c87
|
1331 |
u32 scontrol; |
be77e43ab
|
1332 |
int i, rc; |
c72907245
|
1333 1334 1335 1336 |
/* check for availability */ for (i = 0; i < 4; i++) if (hpriv->map[i] == IDE) |
be77e43ab
|
1337 |
return 0; |
c72907245
|
1338 |
|
e9c1670c2
|
1339 1340 1341 |
/* is it blacklisted? */ if (piix_no_sidpr(host)) return 0; |
c72907245
|
1342 |
if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) |
be77e43ab
|
1343 |
return 0; |
c72907245
|
1344 1345 1346 |
if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) |
be77e43ab
|
1347 |
return 0; |
c72907245
|
1348 1349 |
if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) |
be77e43ab
|
1350 |
return 0; |
c72907245
|
1351 1352 |
hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; |
cb6716c87
|
1353 1354 1355 1356 1357 |
/* SCR access via SIDPR doesn't work on some configurations. * Give it a test drive by inhibiting power save modes which * we'll do anyway. */ |
be77e43ab
|
1358 |
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); |
cb6716c87
|
1359 1360 1361 1362 1363 1364 1365 |
/* if IPM is already 3, SCR access is probably working. Don't * un-inhibit power save modes as BIOS might have inhibited * them for a reason. */ if ((scontrol & 0xf00) != 0x300) { scontrol |= 0x300; |
be77e43ab
|
1366 1367 |
piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol); piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol); |
cb6716c87
|
1368 1369 1370 1371 1372 |
if ((scontrol & 0xf00) != 0x300) { dev_printk(KERN_INFO, host->dev, "SCR access via " "SIDPR is available but doesn't work "); |
be77e43ab
|
1373 |
return 0; |
cb6716c87
|
1374 1375 |
} } |
be77e43ab
|
1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 |
/* okay, SCRs available, set ops and ask libata for slave_link */ for (i = 0; i < 2; i++) { struct ata_port *ap = host->ports[i]; ap->ops = &piix_sidpr_sata_ops; if (ap->flags & ATA_FLAG_SLAVE_POSS) { rc = ata_slave_link_init(ap); if (rc) return rc; } } return 0; |
c72907245
|
1390 |
} |
2852bcf7c
|
1391 |
static void piix_iocfg_bit18_quirk(struct ata_host *host) |
43a98f05d
|
1392 |
{ |
1855256c4
|
1393 |
static const struct dmi_system_id sysids[] = { |
43a98f05d
|
1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 |
{ /* Clevo M570U sets IOCFG bit 18 if the cdrom * isn't used to boot the system which * disables the channel. */ .ident = "M570U", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), }, }, |
7d0515484
|
1405 1406 |
{ } /* terminate list */ |
43a98f05d
|
1407 |
}; |
2852bcf7c
|
1408 1409 |
struct pci_dev *pdev = to_pci_dev(host->dev); struct piix_host_priv *hpriv = host->private_data; |
43a98f05d
|
1410 1411 1412 1413 1414 1415 1416 1417 |
if (!dmi_check_system(sysids)) return; /* The datasheet says that bit 18 is NOOP but certain systems * seem to use it to disable a channel. Clear the bit on the * affected systems. */ |
2852bcf7c
|
1418 |
if (hpriv->saved_iocfg & (1 << 18)) { |
43a98f05d
|
1419 1420 1421 |
dev_printk(KERN_INFO, &pdev->dev, "applying IOCFG bit18 quirk "); |
2852bcf7c
|
1422 1423 |
pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg & ~(1 << 18)); |
43a98f05d
|
1424 1425 |
} } |
5f451fe1a
|
1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 |
static bool piix_broken_system_poweroff(struct pci_dev *pdev) { static const struct dmi_system_id broken_systems[] = { { .ident = "HP Compaq 2510p", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"), }, /* PCI slot number of the controller */ .driver_data = (void *)0x1FUL, }, |
65e316431
|
1438 1439 1440 1441 1442 1443 1444 1445 1446 |
{ .ident = "HP Compaq nc6000", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"), }, /* PCI slot number of the controller */ .driver_data = (void *)0x1FUL, }, |
5f451fe1a
|
1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 |
{ } /* terminate list */ }; const struct dmi_system_id *dmi = dmi_first_match(broken_systems); if (dmi) { unsigned long slot = (unsigned long)dmi->driver_data; /* apply the quirk only to on-board controllers */ return slot == PCI_SLOT(pdev->devfn); } return false; } |
c621b1406
|
1460 |
/** |
1da177e4c
|
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 |
* piix_init_one - Register PIIX ATA PCI device with kernel services * @pdev: PCI device to register * @ent: Entry in piix_pci_tbl matching with @pdev * * Called from kernel PCI layer. We probe for combined mode (sigh), * and then hand over control to libata, for it to do the rest. * * LOCKING: * Inherited from PCI layer (may sleep). * * RETURNS: * Zero on success, or -ERRNO value. */ |
bc5468f52
|
1474 1475 |
static int __devinit piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4c
|
1476 1477 |
{ static int printed_version; |
24dc5f33e
|
1478 |
struct device *dev = &pdev->dev; |
d33f58b88
|
1479 |
struct ata_port_info port_info[2]; |
1626aeb88
|
1480 |
const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
cca3974e4
|
1481 |
unsigned long port_flags; |
8b09f0da0
|
1482 1483 1484 |
struct ata_host *host; struct piix_host_priv *hpriv; int rc; |
1da177e4c
|
1485 1486 |
if (!printed_version++) |
6248e6472
|
1487 1488 1489 |
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION " "); |
1da177e4c
|
1490 |
|
347979a03
|
1491 1492 |
/* no hotplugging support for later devices (FIXME) */ if (!in_module_init && ent->driver_data >= ich5_sata) |
1da177e4c
|
1493 |
return -ENODEV; |
5f451fe1a
|
1494 1495 1496 1497 1498 1499 1500 1501 |
if (piix_broken_system_poweroff(pdev)) { piix_port_info[ent->driver_data].flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN | ATA_FLAG_NO_HIBERNATE_SPINDOWN; dev_info(&pdev->dev, "quirky BIOS, skipping spindown " "on poweroff and hibernation "); } |
8b09f0da0
|
1502 1503 1504 1505 1506 1507 1508 1509 1510 |
port_info[0] = piix_port_info[ent->driver_data]; port_info[1] = piix_port_info[ent->driver_data]; port_flags = port_info[0].flags; /* enable device and prepare host */ rc = pcim_enable_device(pdev); if (rc) return rc; |
2852bcf7c
|
1511 1512 1513 |
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); if (!hpriv) return -ENOMEM; |
213373cf9
|
1514 |
spin_lock_init(&hpriv->sidpr_lock); |
2852bcf7c
|
1515 1516 1517 1518 1519 1520 1521 |
/* Save IOCFG, this will be used for cable detection, quirk * detection and restoration on detach. This is necessary * because some ACPI implementations mess up cable related * bits on _STM. Reported on kernel bz#11879. */ pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg); |
5016d7d21
|
1522 1523 1524 1525 1526 |
/* ICH6R may be driven by either ata_piix or ahci driver * regardless of BIOS configuration. Make sure AHCI mode is * off. */ if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { |
da3ceb228
|
1527 |
rc = piix_disable_ahci(pdev); |
5016d7d21
|
1528 1529 1530 |
if (rc) return rc; } |
8b09f0da0
|
1531 |
/* SATA map init can change port_info, do it before prepping host */ |
8b09f0da0
|
1532 1533 1534 |
if (port_flags & ATA_FLAG_SATA) hpriv->map = piix_init_sata_map(pdev, port_info, piix_map_db_table[ent->driver_data]); |
1da177e4c
|
1535 |
|
1c5afdf7a
|
1536 |
rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
8b09f0da0
|
1537 1538 1539 |
if (rc) return rc; host->private_data = hpriv; |
ff0fc1467
|
1540 |
|
8b09f0da0
|
1541 |
/* initialize controller */ |
c72907245
|
1542 |
if (port_flags & ATA_FLAG_SATA) { |
8b09f0da0
|
1543 |
piix_init_pcs(host, piix_map_db_table[ent->driver_data]); |
be77e43ab
|
1544 1545 1546 |
rc = piix_init_sidpr(host); if (rc) return rc; |
c72907245
|
1547 |
} |
1da177e4c
|
1548 |
|
43a98f05d
|
1549 |
/* apply IOCFG bit18 quirk */ |
2852bcf7c
|
1550 |
piix_iocfg_bit18_quirk(host); |
43a98f05d
|
1551 |
|
1da177e4c
|
1552 1553 1554 1555 1556 1557 |
/* On ICH5, some BIOSen disable the interrupt using the * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. * On ICH6, this bit has the same effect, but only when * MSI is disabled (and it is disabled, as we don't use * message-signalled interrupts currently). */ |
cca3974e4
|
1558 |
if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ffc
|
1559 |
pci_intx(pdev, 1); |
1da177e4c
|
1560 |
|
c621b1406
|
1561 1562 1563 1564 |
if (piix_check_450nx_errata(pdev)) { /* This writes into the master table but it does not really matter for this errata as we will apply it to all the PIIX devices on the board */ |
8b09f0da0
|
1565 1566 1567 1568 |
host->ports[0]->mwdma_mask = 0; host->ports[0]->udma_mask = 0; host->ports[1]->mwdma_mask = 0; host->ports[1]->udma_mask = 0; |
c621b1406
|
1569 |
} |
517d3cc15
|
1570 |
host->flags |= ATA_HOST_PARALLEL_SCAN; |
8b09f0da0
|
1571 1572 |
pci_set_master(pdev); |
c3b288942
|
1573 |
return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &piix_sht); |
1da177e4c
|
1574 |
} |
2852bcf7c
|
1575 1576 1577 1578 1579 1580 1581 1582 1583 |
static void piix_remove_one(struct pci_dev *pdev) { struct ata_host *host = dev_get_drvdata(&pdev->dev); struct piix_host_priv *hpriv = host->private_data; pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg); ata_pci_remove_one(pdev); } |
1da177e4c
|
1584 1585 1586 |
static int __init piix_init(void) { int rc; |
b7887196e
|
1587 1588 1589 |
DPRINTK("pci_register_driver "); rc = pci_register_driver(&piix_pci_driver); |
1da177e4c
|
1590 1591 1592 1593 1594 1595 1596 1597 1598 |
if (rc) return rc; in_module_init = 0; DPRINTK("done "); return 0; } |
1da177e4c
|
1599 1600 1601 1602 1603 1604 1605 |
static void __exit piix_exit(void) { pci_unregister_driver(&piix_pci_driver); } module_init(piix_init); module_exit(piix_exit); |