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drivers/ata/pata_hpt37x.c
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/* * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. * * This driver is heavily based upon: * * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 * * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> * Portions Copyright (C) 2001 Sun Microsystems, Inc. * Portions Copyright (C) 2003 Red Hat Inc |
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* Portions Copyright (C) 2005-2009 MontaVista Software, Inc. |
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* * TODO |
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* Look into engine reset on timeout errors. Should not be required. |
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*/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #define DRV_NAME "pata_hpt37x" |
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#define DRV_VERSION "0.6.15" |
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struct hpt_clock { u8 xfer_speed; u32 timing; }; struct hpt_chip { const char *name; unsigned int base; struct hpt_clock const *clocks[4]; }; /* key for bus clock timings * bit |
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* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. * cycles = value + 1 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. * cycles = value + 1 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
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* register access. |
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* 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
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* register access. |
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* 18:20 udma_cycle_time. Clock cycles for UDMA xfer. * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
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* register access. |
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* 28 UDMA enable. * 29 DMA enable. * 30 PIO_MST enable. If set, the chip is in bus master mode during * PIO xfer. * 31 FIFO enable. Only for PIO. |
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*/ |
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static struct hpt_clock hpt37x_timings_33[] = { { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ { XFER_UDMA_5, 0x12446231 }, { XFER_UDMA_4, 0x12446231 }, { XFER_UDMA_3, 0x126c6231 }, { XFER_UDMA_2, 0x12486231 }, { XFER_UDMA_1, 0x124c6233 }, { XFER_UDMA_0, 0x12506297 }, { XFER_MW_DMA_2, 0x22406c31 }, { XFER_MW_DMA_1, 0x22406c33 }, { XFER_MW_DMA_0, 0x22406c97 }, { XFER_PIO_4, 0x06414e31 }, { XFER_PIO_3, 0x06414e42 }, { XFER_PIO_2, 0x06414e53 }, { XFER_PIO_1, 0x06814e93 }, { XFER_PIO_0, 0x06814ea7 } |
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}; |
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static struct hpt_clock hpt37x_timings_50[] = { { XFER_UDMA_6, 0x12848242 }, { XFER_UDMA_5, 0x12848242 }, { XFER_UDMA_4, 0x12ac8242 }, { XFER_UDMA_3, 0x128c8242 }, { XFER_UDMA_2, 0x120c8242 }, { XFER_UDMA_1, 0x12148254 }, { XFER_UDMA_0, 0x121882ea }, { XFER_MW_DMA_2, 0x22808242 }, { XFER_MW_DMA_1, 0x22808254 }, { XFER_MW_DMA_0, 0x228082ea }, { XFER_PIO_4, 0x0a81f442 }, { XFER_PIO_3, 0x0a81f443 }, { XFER_PIO_2, 0x0a81f454 }, { XFER_PIO_1, 0x0ac1f465 }, { XFER_PIO_0, 0x0ac1f48a } |
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}; |
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static struct hpt_clock hpt37x_timings_66[] = { { XFER_UDMA_6, 0x1c869c62 }, { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ { XFER_UDMA_4, 0x1c8a9c62 }, { XFER_UDMA_3, 0x1c8e9c62 }, { XFER_UDMA_2, 0x1c929c62 }, { XFER_UDMA_1, 0x1c9a9c62 }, { XFER_UDMA_0, 0x1c829c62 }, { XFER_MW_DMA_2, 0x2c829c62 }, { XFER_MW_DMA_1, 0x2c829c66 }, { XFER_MW_DMA_0, 0x2c829d2e }, { XFER_PIO_4, 0x0c829c62 }, { XFER_PIO_3, 0x0c829c84 }, { XFER_PIO_2, 0x0c829ca6 }, { XFER_PIO_1, 0x0d029d26 }, { XFER_PIO_0, 0x0d029d5e } |
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}; |
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static const struct hpt_chip hpt370 = { "HPT370", 48, { |
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hpt37x_timings_33, |
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NULL, NULL, |
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NULL |
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} }; static const struct hpt_chip hpt370a = { "HPT370A", 48, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, |
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NULL |
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} }; static const struct hpt_chip hpt372 = { "HPT372", 55, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt302 = { "HPT302", 66, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt371 = { "HPT371", 66, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt372a = { "HPT372A", 66, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt374 = { "HPT374", 48, { |
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hpt37x_timings_33, |
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NULL, NULL, NULL } }; /** * hpt37x_find_mode - reset the hpt37x bus * @ap: ATA port * @speed: transfer mode * * Return the 32bit register programming information for this channel * that matches the speed provided. */ |
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static u32 hpt37x_find_mode(struct ata_port *ap, int speed) { struct hpt_clock *clocks = ap->host->private_data; |
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while(clocks->xfer_speed) { if (clocks->xfer_speed == speed) return clocks->timing; clocks++; } BUG(); return 0xffffffffU; /* silence compiler warning */ } static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) { |
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unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
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int i = 0; |
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ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
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while (list[i] != NULL) { if (!strcmp(list[i], model_num)) { |
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printk(KERN_WARNING DRV_NAME ": %s is not supported for %s. ", |
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modestr, list[i]); return 1; } i++; } return 0; } static const char *bad_ata33[] = { "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", "Maxtor 90510D4", "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", NULL }; static const char *bad_ata100_5[] = { "IBM-DTLA-307075", "IBM-DTLA-307060", "IBM-DTLA-307045", "IBM-DTLA-307030", "IBM-DTLA-307020", "IBM-DTLA-307015", "IBM-DTLA-305040", "IBM-DTLA-305030", "IBM-DTLA-305020", "IC35L010AVER07-0", "IC35L020AVER07-0", "IC35L030AVER07-0", "IC35L040AVER07-0", "IC35L060AVER07-0", "WDC AC310200R", NULL }; /** * hpt370_filter - mode selection filter |
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* @adev: ATA device * * Block UDMA on devices that cause trouble with this controller. */ |
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static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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if (adev->class == ATA_DEV_ATA) { |
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if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) mask &= ~ATA_MASK_UDMA; if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
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mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
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} |
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return mask; |
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} /** * hpt370a_filter - mode selection filter |
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* @adev: ATA device * * Block UDMA on devices that cause trouble with this controller. */ |
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static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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if (adev->class == ATA_DEV_ATA) { |
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if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
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mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
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} |
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return mask; |
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} |
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/** |
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* hpt37x_cable_detect - Detect the cable type * @ap: ATA port to detect on * * Return the cable type attached to this port */ static int hpt37x_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 scr2, ata66; pci_read_config_byte(pdev, 0x5B, &scr2); pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); |
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udelay(10); /* debounce */ |
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/* Cable register now active */ pci_read_config_byte(pdev, 0x5A, &ata66); /* Restore state */ pci_write_config_byte(pdev, 0x5B, scr2); if (ata66 & (2 >> ap->port_no)) return ATA_CBL_PATA40; else return ATA_CBL_PATA80; } /** * hpt374_fn1_cable_detect - Detect the cable type * @ap: ATA port to detect on * * Return the cable type attached to this port */ static int hpt374_fn1_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); unsigned int mcrbase = 0x50 + 4 * ap->port_no; u16 mcr3; u8 ata66; /* Do the extra channel work */ pci_read_config_word(pdev, mcrbase + 2, &mcr3); /* Set bit 15 of 0x52 to enable TCBLID as input */ pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); pci_read_config_byte(pdev, 0x5A, &ata66); /* Reset TCBLID/FCBLID to output */ pci_write_config_word(pdev, mcrbase + 2, mcr3); if (ata66 & (2 >> ap->port_no)) return ATA_CBL_PATA40; else return ATA_CBL_PATA80; } /** |
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* hpt37x_pre_reset - reset the hpt37x bus |
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* @link: ATA link to reset |
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* @deadline: deadline jiffies for the operation |
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* |
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* Perform the initial reset handling for the HPT37x. |
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*/ |
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static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
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{ |
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struct ata_port *ap = link->ap; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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static const struct pci_bits hpt37x_enable_bits[] = { { 0x50, 1, 0x04, 0x04 }, { 0x54, 1, 0x04, 0x04 } }; if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) return -ENOENT; |
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/* Reset the state machine */ |
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pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
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udelay(100); |
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return ata_sff_prereset(link, deadline); |
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} |
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static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) |
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{ struct pci_dev *pdev = to_pci_dev(ap->host->dev); u32 addr1, addr2; |
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u32 reg, timing, mask; |
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u8 fast; addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); addr2 = 0x51 + 4 * ap->port_no; |
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/* Fast interrupt prediction disable, hold off interrupt disable */ pci_read_config_byte(pdev, addr2, &fast); fast &= ~0x02; fast |= 0x01; pci_write_config_byte(pdev, addr2, fast); |
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/* Determine timing mask and find matching mode entry */ if (mode < XFER_MW_DMA_0) mask = 0xcfc3ffff; else if (mode < XFER_UDMA_0) mask = 0x31c001ff; else mask = 0x303c0000; timing = hpt37x_find_mode(ap, mode); |
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pci_read_config_dword(pdev, addr1, ®); |
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reg = (reg & ~mask) | (timing & mask); pci_write_config_dword(pdev, addr1, reg); } /** * hpt370_set_piomode - PIO setup * @ap: ATA interface * @adev: device on the interface * * Perform PIO mode setup. */ static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) { hpt370_set_mode(ap, adev, adev->pio_mode); |
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} /** * hpt370_set_dmamode - DMA timing setup * @ap: ATA interface * @adev: Device being configured * |
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* Set up the channel for MWDMA or UDMA modes. |
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*/ |
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static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) { |
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hpt370_set_mode(ap, adev, adev->dma_mode); |
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} /** |
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* hpt370_bmdma_end - DMA engine stop * @qc: ATA command * * Work around the HPT370 DMA engine. */ |
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static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
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u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); u8 dma_cmd; |
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if (dma_stat & ATA_DMA_ACTIVE) { |
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udelay(20); |
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dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
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} |
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if (dma_stat & ATA_DMA_ACTIVE) { |
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/* Clear the engine */ pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); udelay(10); /* Stop DMA */ |
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dma_cmd = ioread8(bmdma + ATA_DMA_CMD); iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); |
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/* Clear Error */ |
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dma_stat = ioread8(bmdma + ATA_DMA_STATUS); iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, bmdma + ATA_DMA_STATUS); |
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/* Clear the engine */ pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); udelay(10); } ata_bmdma_stop(qc); } |
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static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) |
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{ struct pci_dev *pdev = to_pci_dev(ap->host->dev); u32 addr1, addr2; |
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u32 reg, timing, mask; |
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u8 fast; addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); addr2 = 0x51 + 4 * ap->port_no; |
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/* Fast interrupt prediction disable, hold off interrupt disable */ pci_read_config_byte(pdev, addr2, &fast); fast &= ~0x07; pci_write_config_byte(pdev, addr2, fast); |
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/* Determine timing mask and find matching mode entry */ if (mode < XFER_MW_DMA_0) mask = 0xcfc3ffff; else if (mode < XFER_UDMA_0) mask = 0x31c001ff; else mask = 0x303c0000; timing = hpt37x_find_mode(ap, mode); |
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pci_read_config_dword(pdev, addr1, ®); |
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reg = (reg & ~mask) | (timing & mask); pci_write_config_dword(pdev, addr1, reg); } |
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/** * hpt372_set_piomode - PIO setup * @ap: ATA interface * @adev: device on the interface * * Perform PIO mode setup. */ static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) { hpt372_set_mode(ap, adev, adev->pio_mode); |
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} /** * hpt372_set_dmamode - DMA timing setup * @ap: ATA interface * @adev: Device being configured * |
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* Set up the channel for MWDMA or UDMA modes. |
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*/ |
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static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) { |
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hpt372_set_mode(ap, adev, adev->dma_mode); |
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526 527 528 529 530 531 532 533 |
} /** * hpt37x_bmdma_end - DMA engine stop * @qc: ATA command * * Clean up after the HPT372 and later DMA engine */ |
85cd7251b
|
534 |
|
669a5db41
|
535 536 537 538 |
static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
6929da442
|
539 |
int mscreg = 0x50 + 4 * ap->port_no; |
669a5db41
|
540 |
u8 bwsr_stat, msc_stat; |
85cd7251b
|
541 |
|
669a5db41
|
542 543 544 545 546 547 548 549 550 |
pci_read_config_byte(pdev, 0x6A, &bwsr_stat); pci_read_config_byte(pdev, mscreg, &msc_stat); if (bwsr_stat & (1 << ap->port_no)) pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); ata_bmdma_stop(qc); } static struct scsi_host_template hpt37x_sht = { |
68d1d07b5
|
551 |
ATA_BMDMA_SHT(DRV_NAME), |
669a5db41
|
552 553 554 555 556 |
}; /* * Configuration for HPT370 */ |
85cd7251b
|
557 |
|
669a5db41
|
558 |
static struct ata_port_operations hpt370_port_ops = { |
029cfd6b7
|
559 |
.inherits = &ata_bmdma_port_ops, |
669a5db41
|
560 |
|
669a5db41
|
561 |
.bmdma_stop = hpt370_bmdma_stop, |
669a5db41
|
562 |
|
029cfd6b7
|
563 |
.mode_filter = hpt370_filter, |
9e87be9ed
|
564 |
.cable_detect = hpt37x_cable_detect, |
029cfd6b7
|
565 566 |
.set_piomode = hpt370_set_piomode, .set_dmamode = hpt370_set_dmamode, |
a1efdaba2
|
567 |
.prereset = hpt37x_pre_reset, |
85cd7251b
|
568 |
}; |
669a5db41
|
569 570 571 572 |
/* * Configuration for HPT370A. Close to 370 but less filters */ |
85cd7251b
|
573 |
|
669a5db41
|
574 |
static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b7
|
575 |
.inherits = &hpt370_port_ops, |
669a5db41
|
576 |
.mode_filter = hpt370a_filter, |
85cd7251b
|
577 |
}; |
669a5db41
|
578 579 580 581 582 |
/* * Configuration for HPT372, HPT371, HPT302. Slightly different PIO * and DMA mode setting functionality. */ |
85cd7251b
|
583 |
|
669a5db41
|
584 |
static struct ata_port_operations hpt372_port_ops = { |
029cfd6b7
|
585 |
.inherits = &ata_bmdma_port_ops, |
669a5db41
|
586 |
|
669a5db41
|
587 |
.bmdma_stop = hpt37x_bmdma_stop, |
669a5db41
|
588 |
|
9e87be9ed
|
589 |
.cable_detect = hpt37x_cable_detect, |
029cfd6b7
|
590 591 |
.set_piomode = hpt372_set_piomode, .set_dmamode = hpt372_set_dmamode, |
a1efdaba2
|
592 |
.prereset = hpt37x_pre_reset, |
85cd7251b
|
593 |
}; |
669a5db41
|
594 595 596 |
/* * Configuration for HPT374. Mode setting works like 372 and friends |
a1efdaba2
|
597 |
* but we have a different cable detection procedure for function 1. |
669a5db41
|
598 |
*/ |
85cd7251b
|
599 |
|
a1efdaba2
|
600 |
static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b7
|
601 |
.inherits = &hpt372_port_ops, |
9e87be9ed
|
602 |
.cable_detect = hpt374_fn1_cable_detect, |
ab81a505a
|
603 |
.prereset = hpt37x_pre_reset, |
85cd7251b
|
604 |
}; |
669a5db41
|
605 606 |
/** |
ad452d64c
|
607 |
* hpt37x_clock_slot - Turn timing to PC clock entry |
669a5db41
|
608 609 610 611 612 613 |
* @freq: Reported frequency timing * @base: Base timing * * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 * and 3 for 66Mhz) */ |
85cd7251b
|
614 |
|
669a5db41
|
615 616 617 618 619 620 621 622 623 624 625 626 627 628 |
static int hpt37x_clock_slot(unsigned int freq, unsigned int base) { unsigned int f = (base * freq) / 192; /* Mhz */ if (f < 40) return 0; /* 33Mhz slot */ if (f < 45) return 1; /* 40Mhz slot */ if (f < 55) return 2; /* 50Mhz slot */ return 3; /* 60Mhz slot */ } /** * hpt37x_calibrate_dpll - Calibrate the DPLL loop |
85cd7251b
|
629 |
* @dev: PCI device |
669a5db41
|
630 631 632 633 634 635 636 637 638 639 |
* * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this * succeeds */ static int hpt37x_calibrate_dpll(struct pci_dev *dev) { u8 reg5b; u32 reg5c; int tries; |
85cd7251b
|
640 |
|
669a5db41
|
641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 |
for(tries = 0; tries < 0x5000; tries++) { udelay(50); pci_read_config_byte(dev, 0x5b, ®5b); if (reg5b & 0x80) { /* See if it stays set */ for(tries = 0; tries < 0x1000; tries ++) { pci_read_config_byte(dev, 0x5b, ®5b); /* Failed ? */ if ((reg5b & 0x80) == 0) return 0; } /* Turn off tuning, we have the DPLL set */ pci_read_config_dword(dev, 0x5c, ®5c); pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); return 1; } } /* Never went stable */ return 0; } |
73946f9fc
|
661 662 663 664 665 666 |
static u32 hpt374_read_freq(struct pci_dev *pdev) { u32 freq; unsigned long io_base = pci_resource_start(pdev, 4); if (PCI_FUNC(pdev->devfn) & 1) { |
40f46f178
|
667 668 669 |
struct pci_dev *pdev_0; pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); |
73946f9fc
|
670 671 672 673 674 675 |
/* Someone hot plugged the controller on us ? */ if (pdev_0 == NULL) return 0; io_base = pci_resource_start(pdev_0, 4); freq = inl(io_base + 0x90); pci_dev_put(pdev_0); |
40f46f178
|
676 |
} else |
73946f9fc
|
677 678 679 |
freq = inl(io_base + 0x90); return freq; } |
669a5db41
|
680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 |
/** * hpt37x_init_one - Initialise an HPT37X/302 * @dev: PCI device * @id: Entry in match table * * Initialise an HPT37x device. There are some interesting complications * here. Firstly the chip may report 366 and be one of several variants. * Secondly all the timings depend on the clock for the chip which we must * detect and look up * * This is the known chip mappings. It may be missing a couple of later * releases. * * Chip version PCI Rev Notes * HPT366 4 (HPT366) 0 Other driver * HPT366 4 (HPT366) 1 Other driver * HPT368 4 (HPT366) 2 Other driver * HPT370 4 (HPT366) 3 UDMA100 * HPT370A 4 (HPT366) 4 UDMA100 * HPT372 4 (HPT366) 5 UDMA133 (1) * HPT372N 4 (HPT366) 6 Other driver * HPT372A 5 (HPT372) 1 UDMA133 (1) * HPT372N 5 (HPT372) 2 Other driver * HPT302 6 (HPT302) 1 UDMA133 * HPT302N 6 (HPT302) 2 Other driver * HPT371 7 (HPT371) * UDMA133 * HPT374 8 (HPT374) * UDMA133 4 channel * HPT372N 9 (HPT372N) * Other driver * * (1) UDMA133 support depends on the bus clock */ |
85cd7251b
|
711 |
|
669a5db41
|
712 713 714 |
static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) { /* HPT370 - UDMA100 */ |
1626aeb88
|
715 |
static const struct ata_port_info info_hpt370 = { |
1d2808fd3
|
716 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
717 718 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
719 |
.udma_mask = ATA_UDMA5, |
669a5db41
|
720 721 722 |
.port_ops = &hpt370_port_ops }; /* HPT370A - UDMA100 */ |
1626aeb88
|
723 |
static const struct ata_port_info info_hpt370a = { |
1d2808fd3
|
724 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
725 726 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
727 |
.udma_mask = ATA_UDMA5, |
669a5db41
|
728 729 |
.port_ops = &hpt370a_port_ops }; |
fcc2f69a6
|
730 |
/* HPT370 - UDMA100 */ |
1626aeb88
|
731 |
static const struct ata_port_info info_hpt370_33 = { |
1d2808fd3
|
732 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
733 734 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
73946f9fc
|
735 |
.udma_mask = ATA_UDMA5, |
fcc2f69a6
|
736 737 738 |
.port_ops = &hpt370_port_ops }; /* HPT370A - UDMA100 */ |
1626aeb88
|
739 |
static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd3
|
740 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
741 742 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
73946f9fc
|
743 |
.udma_mask = ATA_UDMA5, |
fcc2f69a6
|
744 745 |
.port_ops = &hpt370a_port_ops }; |
669a5db41
|
746 |
/* HPT371, 372 and friends - UDMA133 */ |
1626aeb88
|
747 |
static const struct ata_port_info info_hpt372 = { |
1d2808fd3
|
748 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
749 750 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
751 |
.udma_mask = ATA_UDMA6, |
669a5db41
|
752 753 |
.port_ops = &hpt372_port_ops }; |
a1efdaba2
|
754 755 756 |
/* HPT374 - UDMA100, function 1 uses different prereset method */ static const struct ata_port_info info_hpt374_fn0 = { .flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
757 758 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
a1efdaba2
|
759 760 761 762 |
.udma_mask = ATA_UDMA5, .port_ops = &hpt372_port_ops }; static const struct ata_port_info info_hpt374_fn1 = { |
1d2808fd3
|
763 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982
|
764 765 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85
|
766 |
.udma_mask = ATA_UDMA5, |
a1efdaba2
|
767 |
.port_ops = &hpt374_fn1_port_ops |
669a5db41
|
768 769 770 |
}; static const int MHz[4] = { 33, 40, 50, 66 }; |
1626aeb88
|
771 |
void *private_data = NULL; |
887125e37
|
772 |
const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b3603
|
773 |
u8 rev = dev->revision; |
669a5db41
|
774 |
u8 irqmask; |
fcc2f69a6
|
775 |
u8 mcr1; |
669a5db41
|
776 |
u32 freq; |
fcc2f69a6
|
777 |
int prefer_dpll = 1; |
a617c09f6
|
778 |
|
fcc2f69a6
|
779 |
unsigned long iobase = pci_resource_start(dev, 4); |
669a5db41
|
780 781 782 |
const struct hpt_chip *chip_table; int clock_slot; |
f08048e94
|
783 784 785 786 787 |
int rc; rc = pcim_enable_device(dev); if (rc) return rc; |
669a5db41
|
788 |
|
669a5db41
|
789 790 791 |
if (dev->device == PCI_DEVICE_ID_TTI_HPT366) { /* May be a later chip in disguise. Check */ /* Older chips are in the HPT366 driver. Ignore them */ |
89d3b3603
|
792 |
if (rev < 3) |
669a5db41
|
793 794 |
return -ENODEV; /* N series chips have their own driver. Ignore */ |
89d3b3603
|
795 |
if (rev == 6) |
669a5db41
|
796 |
return -ENODEV; |
89d3b3603
|
797 |
switch(rev) { |
669a5db41
|
798 |
case 3: |
887125e37
|
799 |
ppi[0] = &info_hpt370; |
669a5db41
|
800 |
chip_table = &hpt370; |
fcc2f69a6
|
801 |
prefer_dpll = 0; |
669a5db41
|
802 803 |
break; case 4: |
887125e37
|
804 |
ppi[0] = &info_hpt370a; |
669a5db41
|
805 |
chip_table = &hpt370a; |
fcc2f69a6
|
806 |
prefer_dpll = 0; |
669a5db41
|
807 808 |
break; case 5: |
887125e37
|
809 |
ppi[0] = &info_hpt372; |
669a5db41
|
810 811 812 |
chip_table = &hpt372; break; default: |
89d3b3603
|
813 814 815 |
printk(KERN_ERR "pata_hpt37x: Unknown HPT366 " "subtype, please report (%d). ", rev); |
669a5db41
|
816 817 818 819 820 821 |
return -ENODEV; } } else { switch(dev->device) { case PCI_DEVICE_ID_TTI_HPT372: /* 372N if rev >= 2*/ |
89d3b3603
|
822 |
if (rev >= 2) |
669a5db41
|
823 |
return -ENODEV; |
887125e37
|
824 |
ppi[0] = &info_hpt372; |
669a5db41
|
825 826 827 828 |
chip_table = &hpt372a; break; case PCI_DEVICE_ID_TTI_HPT302: /* 302N if rev > 1 */ |
89d3b3603
|
829 |
if (rev > 1) |
669a5db41
|
830 |
return -ENODEV; |
887125e37
|
831 |
ppi[0] = &info_hpt372; |
669a5db41
|
832 833 834 835 |
/* Check this */ chip_table = &hpt302; break; case PCI_DEVICE_ID_TTI_HPT371: |
89d3b3603
|
836 |
if (rev > 1) |
fcc2f69a6
|
837 |
return -ENODEV; |
887125e37
|
838 |
ppi[0] = &info_hpt372; |
669a5db41
|
839 |
chip_table = &hpt371; |
a47344685
|
840 841 |
/* Single channel device, master is not present but the BIOS (or us for non x86) must mark it |
fcc2f69a6
|
842 843 844 845 |
absent */ pci_read_config_byte(dev, 0x50, &mcr1); mcr1 &= ~0x04; pci_write_config_byte(dev, 0x50, mcr1); |
669a5db41
|
846 847 848 |
break; case PCI_DEVICE_ID_TTI_HPT374: chip_table = &hpt374; |
a1efdaba2
|
849 850 851 852 |
if (!(PCI_FUNC(dev->devfn) & 1)) *ppi = &info_hpt374_fn0; else *ppi = &info_hpt374_fn1; |
669a5db41
|
853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 |
break; default: printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d). ", dev->device); return -ENODEV; } } /* Ok so this is a chip we support */ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); pci_read_config_byte(dev, 0x5A, &irqmask); irqmask &= ~0x10; pci_write_config_byte(dev, 0x5a, irqmask); /* * default to pci clock. make sure MA15/16 are set to output * to prevent drives having problems with 40-pin cables. Needed * for some drives such as IBM-DTLA which will not enter ready * state on reset when PDIAG is a input. */ |
85cd7251b
|
877 |
pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f6
|
878 |
|
fcc2f69a6
|
879 880 881 882 883 884 |
/* * HighPoint does this for HPT372A. * NOTE: This register is only writeable via I/O space. */ if (chip_table == &hpt372a) outb(0x0e, iobase + 0x9c); |
85cd7251b
|
885 |
|
fcc2f69a6
|
886 |
/* Some devices do not let this value be accessed via PCI space |
73946f9fc
|
887 888 889 890 891 892 893 894 895 |
according to the old driver. In addition we must use the value from FN 0 on the HPT374 */ if (chip_table == &hpt374) { freq = hpt374_read_freq(dev); if (freq == 0) return -ENODEV; } else freq = inl(iobase + 0x90); |
fcc2f69a6
|
896 |
|
669a5db41
|
897 898 899 900 |
if ((freq >> 12) != 0xABCDE) { int i; u8 sr; u32 total = 0; |
85cd7251b
|
901 |
|
669a5db41
|
902 903 |
printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks. "); |
85cd7251b
|
904 |
|
669a5db41
|
905 906 907 |
/* This is the process the HPT371 BIOS is reported to use */ for(i = 0; i < 128; i++) { pci_read_config_byte(dev, 0x78, &sr); |
fcc2f69a6
|
908 |
total += sr & 0x1FF; |
669a5db41
|
909 910 911 912 913 |
udelay(15); } freq = total / 128; } freq &= 0x1FF; |
85cd7251b
|
914 |
|
669a5db41
|
915 916 917 918 |
/* * Turn the frequency check into a band and then find a timing * table to match it. */ |
a617c09f6
|
919 |
|
669a5db41
|
920 |
clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a6
|
921 |
if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db41
|
922 923 |
/* * We need to try PLL mode instead |
fcc2f69a6
|
924 925 926 |
* * For non UDMA133 capable devices we should * use a 50MHz DPLL by choice |
669a5db41
|
927 |
*/ |
fcc2f69a6
|
928 |
unsigned int f_low, f_high; |
960c8a10c
|
929 |
int dpll, adjust; |
a617c09f6
|
930 |
|
960c8a10c
|
931 |
/* Compute DPLL */ |
887125e37
|
932 |
dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f6
|
933 |
|
960c8a10c
|
934 |
f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a6
|
935 |
f_high = f_low + 2; |
960c8a10c
|
936 937 |
if (clock_slot > 1) f_high += 2; |
fcc2f69a6
|
938 939 940 |
/* Select the DPLL clock. */ pci_write_config_byte(dev, 0x5b, 0x21); |
64a817097
|
941 |
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
85cd7251b
|
942 |
|
669a5db41
|
943 944 945 946 |
for(adjust = 0; adjust < 8; adjust++) { if (hpt37x_calibrate_dpll(dev)) break; /* See if it'll settle at a fractionally different clock */ |
64a817097
|
947 948 949 950 951 |
if (adjust & 1) f_low -= adjust >> 1; else f_high += adjust >> 1; pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
669a5db41
|
952 953 |
} if (adjust == 8) { |
80b8987c8
|
954 955 |
printk(KERN_ERR "pata_hpt37x: DPLL did not stabilize! "); |
669a5db41
|
956 957 |
return -ENODEV; } |
960c8a10c
|
958 |
if (dpll == 3) |
1626aeb88
|
959 |
private_data = (void *)hpt37x_timings_66; |
fcc2f69a6
|
960 |
else |
1626aeb88
|
961 |
private_data = (void *)hpt37x_timings_50; |
85cd7251b
|
962 |
|
80b8987c8
|
963 964 965 |
printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using %dMHz DPLL. ", MHz[clock_slot], MHz[dpll]); |
669a5db41
|
966 |
} else { |
1626aeb88
|
967 |
private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db41
|
968 |
/* |
a47344685
|
969 970 971 972 |
* Perform a final fixup. Note that we will have used the * DPLL on the HPT372 which means we don't have to worry * about lack of UDMA133 support on lower clocks */ |
85cd7251b
|
973 |
|
887125e37
|
974 975 976 977 |
if (clock_slot < 2 && ppi[0] == &info_hpt370) ppi[0] = &info_hpt370_33; if (clock_slot < 2 && ppi[0] == &info_hpt370a) ppi[0] = &info_hpt370a_33; |
80b8987c8
|
978 979 980 |
printk(KERN_INFO "pata_hpt37x: %s using %dMHz bus clock. ", chip_table->name, MHz[clock_slot]); |
669a5db41
|
981 |
} |
fcc2f69a6
|
982 |
|
669a5db41
|
983 |
/* Now kick off ATA set up */ |
1c5afdf7a
|
984 |
return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db41
|
985 |
} |
2d2744fc8
|
986 987 988 989 990 991 992 993 |
static const struct pci_device_id hpt37x[] = { { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, { }, |
669a5db41
|
994 995 996 |
}; static struct pci_driver hpt37x_pci_driver = { |
2d2744fc8
|
997 |
.name = DRV_NAME, |
669a5db41
|
998 999 1000 1001 1002 1003 1004 1005 1006 |
.id_table = hpt37x, .probe = hpt37x_init_one, .remove = ata_pci_remove_one }; static int __init hpt37x_init(void) { return pci_register_driver(&hpt37x_pci_driver); } |
669a5db41
|
1007 1008 1009 1010 |
static void __exit hpt37x_exit(void) { pci_unregister_driver(&hpt37x_pci_driver); } |
669a5db41
|
1011 1012 1013 1014 1015 1016 1017 1018 |
MODULE_AUTHOR("Alan Cox"); MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, hpt37x); MODULE_VERSION(DRV_VERSION); module_init(hpt37x_init); module_exit(hpt37x_exit); |