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drivers/media/video/saa7115.c
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/* saa711x - Philips SAA711x video decoder driver * This driver can work with saa7111, saa7111a, saa7113, saa7114, * saa7115 and saa7118. |
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* * Based on saa7114 driver by Maxim Yevtyushkin, which is based on * the saa7111 driver by Dave Perks. * * Copyright (C) 1998 Dave Perks <dperks@ibm.net> * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com> * * Slight changes for video timing and attachment output by * Wolfgang Scherr <scherr@net4you.net> * * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003) * by Ronald Bultje <rbultje@ronald.bitfreak.net> * * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com> * (2/17/2003) * * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl> |
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* * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> * SAA7111, SAA7113 and SAA7118 support |
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* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ |
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#include "saa711x_regs.h" |
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#include <linux/kernel.h> #include <linux/module.h> #include <linux/slab.h> #include <linux/i2c.h> #include <linux/videodev2.h> |
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#include <media/v4l2-device.h> |
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#include <media/v4l2-chip-ident.h> |
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#include <media/v4l2-i2c-drv-legacy.h> |
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#include <media/saa7115.h> |
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#include <asm/div64.h> |
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#define VRES_60HZ (480+16) |
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MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver"); |
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MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, " "Hans Verkuil, Mauro Carvalho Chehab"); |
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MODULE_LICENSE("GPL"); |
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static int debug; |
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module_param(debug, bool, 0644); |
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MODULE_PARM_DESC(debug, "Debug level (0-1)"); |
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static unsigned short normal_i2c[] = { |
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0x4a >> 1, 0x48 >> 1, /* SAA7111, SAA7111A and SAA7113 */ 0x42 >> 1, 0x40 >> 1, /* SAA7114, SAA7115 and SAA7118 */ |
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I2C_CLIENT_END }; |
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I2C_CLIENT_INSMOD; |
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struct saa711x_state { |
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struct v4l2_subdev sd; |
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v4l2_std_id std; int input; |
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int output; |
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int enable; |
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int radio; |
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int bright; int contrast; int hue; int sat; |
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int width; int height; |
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u32 ident; |
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u32 audclk_freq; |
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u32 crystal_freq; u8 ucgc; u8 cgcdiv; u8 apll; |
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}; |
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static inline struct saa711x_state *to_state(struct v4l2_subdev *sd) { return container_of(sd, struct saa711x_state, sd); } |
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/* ----------------------------------------------------------------------- */ |
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static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value) |
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{ |
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struct i2c_client *client = v4l2_get_subdevdata(sd); |
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return i2c_smbus_write_byte_data(client, reg, value); } |
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/* Sanity routine to check if a register is present */ static int saa711x_has_reg(const int id, const u8 reg) { |
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if (id == V4L2_IDENT_SAA7111) return reg < 0x20 && reg != 0x01 && reg != 0x0f && (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e; /* common for saa7113/4/5/8 */ if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f || reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) || reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) || reg == 0x82 || (reg >= 0x89 && reg <= 0x8e))) return 0; |
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switch (id) { |
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case V4L2_IDENT_SAA7113: |
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return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) && reg != 0x5d && reg < 0x63; |
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case V4L2_IDENT_SAA7114: |
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return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) && (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 && reg != 0x81 && reg < 0xf0; |
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case V4L2_IDENT_SAA7115: |
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return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe); |
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case V4L2_IDENT_SAA7118: |
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return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) && (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 && (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0; |
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} |
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return 1; } |
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static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs) |
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{ |
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struct saa711x_state *state = to_state(sd); |
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unsigned char reg, data; while (*regs != 0x00) { reg = *(regs++); data = *(regs++); |
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/* According with datasheets, reserved regs should be filled with 0 - seems better not to touch on they */ |
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if (saa711x_has_reg(state->ident, reg)) { if (saa711x_write(sd, reg, data) < 0) |
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return -1; |
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} else { |
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v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x ", reg); |
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} |
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} return 0; } |
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static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg) |
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{ |
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struct i2c_client *client = v4l2_get_subdevdata(sd); |
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return i2c_smbus_read_byte_data(client, reg); } /* ----------------------------------------------------------------------- */ |
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/* SAA7111 initialization table */ |
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static const unsigned char saa7111_init[] = { |
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R_01_INC_DELAY, 0x00, /* reserved */ /*front end */ R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */ R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0, * GAFIX=0, GAI1=256, GAI2=256 */ R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */ R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */ /* decoder */ R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz) * pixels after end of last line */ R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to * work with NTSC, too */ R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0, * VTRC=1, HPLL=0, VNOI=0 */ R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0, * VBLB=0, UPTCV=0, APER=1 */ R_0A_LUMA_BRIGHT_CNTL, 0x80, R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */ R_0C_CHROMA_SAT_CNTL, 0x40, R_0D_CHROMA_HUE_CNTL, 0x00, R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0, * FCTC=0, CHBW=1 */ R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */ R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */ R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1, * OEYC=1, OEHV=1, VIPB=0, COLO=0 */ R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */ R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */ R_14_ANAL_ADC_COMPAT_CNTL, 0x00, R_15_VGATE_START_FID_CHG, 0x00, R_16_VGATE_STOP, 0x00, R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 0x00, 0x00 }; /* SAA7113 init codes */ |
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static const unsigned char saa7113_init[] = { |
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R_01_INC_DELAY, 0x08, R_02_INPUT_CNTL_1, 0xc2, R_03_INPUT_CNTL_2, 0x30, R_04_INPUT_CNTL_3, 0x00, R_05_INPUT_CNTL_4, 0x00, R_06_H_SYNC_START, 0x89, R_07_H_SYNC_STOP, 0x0d, R_08_SYNC_CNTL, 0x88, R_09_LUMA_CNTL, 0x01, R_0A_LUMA_BRIGHT_CNTL, 0x80, R_0B_LUMA_CONTRAST_CNTL, 0x47, R_0C_CHROMA_SAT_CNTL, 0x40, R_0D_CHROMA_HUE_CNTL, 0x00, R_0E_CHROMA_CNTL_1, 0x01, R_0F_CHROMA_GAIN_CNTL, 0x2a, R_10_CHROMA_CNTL_2, 0x08, R_11_MODE_DELAY_CNTL, 0x0c, R_12_RT_SIGNAL_CNTL, 0x07, R_13_RT_X_PORT_OUT_CNTL, 0x00, R_14_ANAL_ADC_COMPAT_CNTL, 0x00, R_15_VGATE_START_FID_CHG, 0x00, R_16_VGATE_STOP, 0x00, R_17_MISC_VGATE_CONF_AND_MSB, 0x00, 0x00, 0x00 }; |
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/* If a value differs from the Hauppauge driver values, then the comment starts with 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the Hauppauge driver sets. */ |
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/* SAA7114 and SAA7115 initialization table */ |
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static const unsigned char saa7115_init_auto_input[] = { |
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/* Front-End Part */ |
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R_01_INC_DELAY, 0x48, /* white peak control disabled */ R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */ R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */ R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */ |
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/* Decoder Part */ |
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R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */ R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */ |
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R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */ |
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R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */ R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */ R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */ R_0D_CHROMA_HUE_CNTL, 0x00, R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */ R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */ R_11_MODE_DELAY_CNTL, 0x00, R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */ R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */ R_14_ANAL_ADC_COMPAT_CNTL, 0x00, R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */ R_19_RAW_DATA_OFF_CNTL, 0x80, R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */ R_1B_MISC_TVVCRDET, 0x42, /* recommended value */ R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */ R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */ |
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R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */ |
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/* Power Device Control */ |
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R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */ |
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0x00, 0x00 }; |
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/* Used to reset saa7113, saa7114 and saa7115 */ |
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static const unsigned char saa7115_cfg_reset_scaler[] = { |
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R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */ |
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0x00, 0x00 }; /* ============== SAA7715 VIDEO templates ============= */ |
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static const unsigned char saa7115_cfg_60hz_video[] = { |
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R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ |
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R_15_VGATE_START_FID_CHG, 0x03, R_16_VGATE_STOP, 0x11, R_17_MISC_VGATE_CONF_AND_MSB, 0x9c, |
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R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */ R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */ |
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R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */ |
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/* Task A */ |
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R_90_A_TASK_HANDLING_CNTL, 0x80, R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, /* hoffset low (input), 0x0002 is minimum */ R_94_A_HORIZ_INPUT_WINDOW_START, 0x01, R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, /* hsize low (input), 0x02d0 = 720 */ R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, R_98_A_VERT_INPUT_WINDOW_START, 0x05, R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c, R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c, R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, |
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/* Task B */ |
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R_C0_B_TASK_HANDLING_CNTL, 0x00, R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, /* 0x0002 is minimum */ R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02, R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, /* 0x02d0 = 720 */ R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, /* vwindow start 0x12 = 18 */ R_C8_B_VERT_INPUT_WINDOW_START, 0x12, R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, /* vwindow length 0xf8 = 248 */ |
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R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1, R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9, |
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/* hwindow 0x02d0 = 720 */ R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */ R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */ R_F5_PULSGEN_LINE_LENGTH, 0xad, R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, |
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0x00, 0x00 }; |
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static const unsigned char saa7115_cfg_50hz_video[] = { |
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R_80_GLOBAL_CNTL_1, 0x00, R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ |
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R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */ R_16_VGATE_STOP, 0x16, R_17_MISC_VGATE_CONF_AND_MSB, 0x99, |
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R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */ R_0E_CHROMA_CNTL_1, 0x07, |
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R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */ |
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/* Task A */ |
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R_90_A_TASK_HANDLING_CNTL, 0x81, R_91_A_X_PORT_FORMATS_AND_CONF, 0x48, R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40, R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84, |
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/* This is weird: the datasheet says that you should use 2 as the minimum value, */ /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ |
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/* hoffset low (input), 0x0002 is minimum */ R_94_A_HORIZ_INPUT_WINDOW_START, 0x00, R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00, /* hsize low (input), 0x02d0 = 720 */ R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, R_98_A_VERT_INPUT_WINDOW_START, 0x03, R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00, /* vsize 0x12 = 18 */ R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12, R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00, /* hsize 0x05a0 = 1440 */ R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0, R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */ R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */ R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */ |
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/* Task B */ |
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|
385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 |
R_C0_B_TASK_HANDLING_CNTL, 0x00, R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08, R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00, R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80, /* This is weird: the datasheet says that you should use 2 as the minimum value, */ /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */ /* hoffset low (input), 0x0002 is minimum. See comment above. */ R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00, R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00, /* hsize 0x02d0 = 720 */ R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0, R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02, /* voffset 0x16 = 22 */ R_C8_B_VERT_INPUT_WINDOW_START, 0x16, R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00, /* vsize 0x0120 = 288 */ R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20, R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01, /* hsize 0x02d0 = 720 */ R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02, |
96ecfc4ed
|
411 412 413 414 |
R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */ R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */ R_F5_PULSGEN_LINE_LENGTH, 0xb0, R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01, |
e19b2fccc
|
415 416 417 418 419 420 |
0x00, 0x00 }; /* ============== SAA7715 VIDEO templates (end) ======= */ static const unsigned char saa7115_cfg_vbi_on[] = { |
96ecfc4ed
|
421 422 423 424 425 |
R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ |
e19b2fccc
|
426 427 428 429 |
0x00, 0x00 }; static const unsigned char saa7115_cfg_vbi_off[] = { |
96ecfc4ed
|
430 431 432 433 434 |
R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */ R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */ R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */ |
e19b2fccc
|
435 436 |
0x00, 0x00 }; |
f5762e441
|
437 |
|
e19b2fccc
|
438 |
static const unsigned char saa7115_init_misc[] = { |
96ecfc4ed
|
439 |
R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01, |
96ecfc4ed
|
440 441 442 443 444 |
R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01, R_84_I_PORT_SIGNAL_DEF, 0x20, R_85_I_PORT_SIGNAL_POLAR, 0x21, R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, |
e19b2fccc
|
445 446 |
/* Task A */ |
96ecfc4ed
|
447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 |
R_A0_A_HORIZ_PRESCALING, 0x01, R_A1_A_ACCUMULATION_LENGTH, 0x00, R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, /* Configure controls at nominal value*/ R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80, R_A5_A_LUMA_CONTRAST_CNTL, 0x40, R_A6_A_CHROMA_SATURATION_CNTL, 0x40, /* note: 2 x zoom ensures that VBI lines have same length as video lines. */ R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00, R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02, R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00, /* must be horiz lum scaling / 2 */ R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00, R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01, /* must be offset luma / 2 */ R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00, R_B0_A_VERT_LUMA_SCALING_INC, 0x00, R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04, R_B2_A_VERT_CHROMA_SCALING_INC, 0x00, R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04, R_B4_A_VERT_SCALING_MODE_CNTL, 0x01, R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00, R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00, R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00, R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00, R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00, R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00, R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00, R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00, |
e19b2fccc
|
486 487 |
/* Task B */ |
96ecfc4ed
|
488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 |
R_D0_B_HORIZ_PRESCALING, 0x01, R_D1_B_ACCUMULATION_LENGTH, 0x00, R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00, /* Configure controls at nominal value*/ R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80, R_D5_B_LUMA_CONTRAST_CNTL, 0x40, R_D6_B_CHROMA_SATURATION_CNTL, 0x40, /* hor lum scaling 0x0400 = 1 */ R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04, R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00, /* must be hor lum scaling / 2 */ R_DC_B_HORIZ_CHROMA_SCALING, 0x00, R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02, /* must be offset luma / 2 */ R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00, R_E0_B_VERT_LUMA_SCALING_INC, 0x00, R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04, R_E2_B_VERT_CHROMA_SCALING_INC, 0x00, R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04, R_E4_B_VERT_SCALING_MODE_CNTL, 0x01, R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00, R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00, R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00, R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00, R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00, R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00, R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00, R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00, R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */ R_F3_PLL_INCREMENT, 0x46, R_F4_PLL2_STATUS, 0x00, R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */ R_F8_PULSE_B_POS, 0x00, R_F9_PULSE_B_POS_MSB, 0x4b, R_FA_PULSE_C_POS, 0x00, R_FB_PULSE_C_POS_MSB, 0x4b, /* PLL2 lock detection settings: 71 lines 50% phase error */ R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88, |
e19b2fccc
|
539 540 |
/* Turn off VBI */ |
96ecfc4ed
|
541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 |
R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */ R_41_LCR_BASE, 0xff, R_41_LCR_BASE+1, 0xff, R_41_LCR_BASE+2, 0xff, R_41_LCR_BASE+3, 0xff, R_41_LCR_BASE+4, 0xff, R_41_LCR_BASE+5, 0xff, R_41_LCR_BASE+6, 0xff, R_41_LCR_BASE+7, 0xff, R_41_LCR_BASE+8, 0xff, R_41_LCR_BASE+9, 0xff, R_41_LCR_BASE+10, 0xff, R_41_LCR_BASE+11, 0xff, R_41_LCR_BASE+12, 0xff, R_41_LCR_BASE+13, 0xff, R_41_LCR_BASE+14, 0xff, R_41_LCR_BASE+15, 0xff, R_41_LCR_BASE+16, 0xff, R_41_LCR_BASE+17, 0xff, R_41_LCR_BASE+18, 0xff, R_41_LCR_BASE+19, 0xff, R_41_LCR_BASE+20, 0xff, R_41_LCR_BASE+21, 0xff, R_41_LCR_BASE+22, 0xff, R_58_PROGRAM_FRAMING_CODE, 0x40, R_59_H_OFF_FOR_SLICER, 0x47, R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83, R_5D_DID, 0xbd, R_5E_SDID, 0x35, R_02_INPUT_CNTL_1, 0x84, /* input tuner -> input 4, amplifier active */ |
96ecfc4ed
|
572 573 574 575 |
R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */ R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, |
e19b2fccc
|
576 577 |
0x00, 0x00 }; |
66ec1193b
|
578 |
static int saa711x_odd_parity(u8 c) |
e19b2fccc
|
579 580 581 582 583 584 585 |
{ c ^= (c >> 4); c ^= (c >> 2); c ^= (c >> 1); return c & 1; } |
9415f4b21
|
586 |
static int saa711x_decode_vps(u8 *dst, u8 *p) |
e19b2fccc
|
587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 |
{ static const u8 biphase_tbl[] = { 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87, 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3, 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85, 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1, 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86, 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2, 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84, 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0, 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4, 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0, 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, }; int i; u8 c, err = 0; for (i = 0; i < 2 * 13; i += 2) { err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]]; c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4); dst[i / 2] = c; } return err & 0xf0; } |
9415f4b21
|
632 |
static int saa711x_decode_wss(u8 *p) |
e19b2fccc
|
633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 |
{ static const int wss_bits[8] = { 0, 0, 0, 1, 0, 1, 1, 1 }; unsigned char parity; int wss = 0; int i; for (i = 0; i < 16; i++) { int b1 = wss_bits[p[i] & 7]; int b2 = wss_bits[(p[i] >> 3) & 7]; if (b1 == b2) return -1; wss |= b2 << i; } parity = wss & 15; parity ^= parity >> 2; parity ^= parity >> 1; if (!(parity & 1)) return -1; return wss; } |
9415f4b21
|
658 |
static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq) |
e19b2fccc
|
659 |
{ |
9415f4b21
|
660 |
struct saa711x_state *state = to_state(sd); |
3578d3dd0
|
661 662 663 664 |
u32 acpf; u32 acni; u32 hz; u64 f; |
b7f8292c9
|
665 |
u8 acc = 0; /* reg 0x3a, audio clock control */ |
e19b2fccc
|
666 |
|
89f75ffc7
|
667 |
/* Checks for chips that don't have audio clock (saa7111, saa7113) */ |
9415f4b21
|
668 |
if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD)) |
89f75ffc7
|
669 |
return 0; |
9415f4b21
|
670 671 |
v4l2_dbg(1, debug, sd, "set audio clock freq: %d ", freq); |
3578d3dd0
|
672 673 674 675 676 677 678 679 680 681 682 |
/* sanity check */ if (freq < 32000 || freq > 48000) return -EINVAL; /* hz is the refresh rate times 100 */ hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000; /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */ acpf = (25600 * freq) / hz; /* acni = (256 * freq * 2^23) / crystal_frequency = (freq * 2^(8+23)) / crystal_frequency = |
b7f8292c9
|
683 |
(freq << 31) / crystal_frequency */ |
3578d3dd0
|
684 685 |
f = freq; f = f << 31; |
b7f8292c9
|
686 |
do_div(f, state->crystal_freq); |
3578d3dd0
|
687 |
acni = f; |
b7f8292c9
|
688 689 690 691 692 693 694 695 696 |
if (state->ucgc) { acpf = acpf * state->cgcdiv / 16; acni = acni * state->cgcdiv / 16; acc = 0x80; if (state->cgcdiv == 3) acc |= 0x40; } if (state->apll) acc |= 0x08; |
3578d3dd0
|
697 |
|
9415f4b21
|
698 699 700 |
saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03); saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10); saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc); |
96ecfc4ed
|
701 |
|
9415f4b21
|
702 703 |
saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff); saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1, |
96ecfc4ed
|
704 |
(acpf >> 8) & 0xff); |
9415f4b21
|
705 |
saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2, |
96ecfc4ed
|
706 |
(acpf >> 16) & 0x03); |
9415f4b21
|
707 708 709 |
saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff); saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff); saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f); |
e19b2fccc
|
710 711 712 |
state->audclk_freq = freq; return 0; } |
9415f4b21
|
713 |
static int saa711x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
e19b2fccc
|
714 |
{ |
9415f4b21
|
715 |
struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
716 717 718 719 |
switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: if (ctrl->value < 0 || ctrl->value > 255) { |
9415f4b21
|
720 721 |
v4l2_err(sd, "invalid brightness setting %d ", ctrl->value); |
e19b2fccc
|
722 723 724 725 |
return -ERANGE; } state->bright = ctrl->value; |
9415f4b21
|
726 |
saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, state->bright); |
e19b2fccc
|
727 728 729 730 |
break; case V4L2_CID_CONTRAST: if (ctrl->value < 0 || ctrl->value > 127) { |
9415f4b21
|
731 732 |
v4l2_err(sd, "invalid contrast setting %d ", ctrl->value); |
e19b2fccc
|
733 734 735 736 |
return -ERANGE; } state->contrast = ctrl->value; |
9415f4b21
|
737 |
saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, state->contrast); |
e19b2fccc
|
738 739 740 741 |
break; case V4L2_CID_SATURATION: if (ctrl->value < 0 || ctrl->value > 127) { |
9415f4b21
|
742 743 |
v4l2_err(sd, "invalid saturation setting %d ", ctrl->value); |
e19b2fccc
|
744 745 746 747 |
return -ERANGE; } state->sat = ctrl->value; |
9415f4b21
|
748 |
saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, state->sat); |
e19b2fccc
|
749 750 751 |
break; case V4L2_CID_HUE: |
de6476f5f
|
752 |
if (ctrl->value < -128 || ctrl->value > 127) { |
9415f4b21
|
753 754 |
v4l2_err(sd, "invalid hue setting %d ", ctrl->value); |
e19b2fccc
|
755 756 757 758 |
return -ERANGE; } state->hue = ctrl->value; |
9415f4b21
|
759 |
saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, state->hue); |
e19b2fccc
|
760 |
break; |
3faeeae48
|
761 762 763 |
default: return -EINVAL; |
e19b2fccc
|
764 765 766 767 |
} return 0; } |
9415f4b21
|
768 |
static int saa711x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
e19b2fccc
|
769 |
{ |
9415f4b21
|
770 |
struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 |
switch (ctrl->id) { case V4L2_CID_BRIGHTNESS: ctrl->value = state->bright; break; case V4L2_CID_CONTRAST: ctrl->value = state->contrast; break; case V4L2_CID_SATURATION: ctrl->value = state->sat; break; case V4L2_CID_HUE: ctrl->value = state->hue; break; default: return -EINVAL; } return 0; } |
9415f4b21
|
791 |
static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height) |
d9dce96fa
|
792 |
{ |
9415f4b21
|
793 |
struct saa711x_state *state = to_state(sd); |
d9dce96fa
|
794 795 796 797 798 |
int HPSC, HFSC; int VSCY; int res; int is_50hz = state->std & V4L2_STD_625_50; int Vsrc = is_50hz ? 576 : 480; |
9415f4b21
|
799 800 |
v4l2_dbg(1, debug, sd, "decoder set size to %ix%i ", width, height); |
d9dce96fa
|
801 802 803 804 805 806 |
/* FIXME need better bounds checking here */ if ((width < 1) || (width > 1440)) return -EINVAL; if ((height < 1) || (height > Vsrc)) return -EINVAL; |
9415f4b21
|
807 |
if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) { |
d9dce96fa
|
808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 |
/* Decoder only supports 720 columns and 480 or 576 lines */ if (width != 720) return -EINVAL; if (height != Vsrc) return -EINVAL; } state->width = width; state->height = height; if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH)) return 0; /* probably have a valid size, let's set it */ /* Set output width/height */ /* width */ |
9415f4b21
|
824 |
saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, |
d9dce96fa
|
825 |
(u8) (width & 0xff)); |
9415f4b21
|
826 |
saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, |
d9dce96fa
|
827 828 829 |
(u8) ((width >> 8) & 0xff)); /* Vertical Scaling uses height/2 */ |
9415f4b21
|
830 |
res = height / 2; |
d9dce96fa
|
831 832 833 |
/* On 60Hz, it is using a higher Vertical Output Size */ if (!is_50hz) |
d0d30c03e
|
834 |
res += (VRES_60HZ - 480) >> 1; |
d9dce96fa
|
835 836 |
/* height */ |
9415f4b21
|
837 |
saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, |
d9dce96fa
|
838 |
(u8) (res & 0xff)); |
9415f4b21
|
839 |
saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, |
d9dce96fa
|
840 841 842 843 844 845 846 847 848 849 |
(u8) ((res >> 8) & 0xff)); /* Scaling settings */ /* Hprescaler is floor(inres/outres) */ HPSC = (int)(720 / width); /* 0 is not allowed (div. by zero) */ HPSC = HPSC ? HPSC : 1; HFSC = (int)((1024 * 720) / (HPSC * width)); /* FIXME hardcodes to "Task B" * write H prescaler integer */ |
9415f4b21
|
850 |
saa711x_write(sd, R_D0_B_HORIZ_PRESCALING, |
d9dce96fa
|
851 |
(u8) (HPSC & 0x3f)); |
9415f4b21
|
852 853 |
v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x ", HPSC, HFSC); |
d9dce96fa
|
854 |
/* write H fine-scaling (luminance) */ |
9415f4b21
|
855 |
saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC, |
d9dce96fa
|
856 |
(u8) (HFSC & 0xff)); |
9415f4b21
|
857 |
saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, |
d9dce96fa
|
858 859 860 |
(u8) ((HFSC >> 8) & 0xff)); /* write H fine-scaling (chrominance) * must be lum/2, so i'll just bitshift :) */ |
9415f4b21
|
861 |
saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING, |
d9dce96fa
|
862 |
(u8) ((HFSC >> 1) & 0xff)); |
9415f4b21
|
863 |
saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB, |
d9dce96fa
|
864 865 866 |
(u8) ((HFSC >> 9) & 0xff)); VSCY = (int)((1024 * Vsrc) / height); |
9415f4b21
|
867 868 |
v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x ", Vsrc, VSCY); |
d9dce96fa
|
869 870 |
/* Correct Contrast and Luminance */ |
9415f4b21
|
871 |
saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL, |
d9dce96fa
|
872 |
(u8) (64 * 1024 / VSCY)); |
9415f4b21
|
873 |
saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL, |
d9dce96fa
|
874 875 876 |
(u8) (64 * 1024 / VSCY)); /* write V fine-scaling (luminance) */ |
9415f4b21
|
877 |
saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC, |
d9dce96fa
|
878 |
(u8) (VSCY & 0xff)); |
9415f4b21
|
879 |
saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB, |
d9dce96fa
|
880 881 |
(u8) ((VSCY >> 8) & 0xff)); /* write V fine-scaling (chrominance) */ |
9415f4b21
|
882 |
saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC, |
d9dce96fa
|
883 |
(u8) (VSCY & 0xff)); |
9415f4b21
|
884 |
saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB, |
d9dce96fa
|
885 |
(u8) ((VSCY >> 8) & 0xff)); |
9415f4b21
|
886 |
saa711x_writeregs(sd, saa7115_cfg_reset_scaler); |
d9dce96fa
|
887 888 |
/* Activates task "B" */ |
9415f4b21
|
889 890 |
saa711x_write(sd, R_80_GLOBAL_CNTL_1, saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20); |
d9dce96fa
|
891 892 893 |
return 0; } |
9415f4b21
|
894 |
static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std) |
e19b2fccc
|
895 |
{ |
9415f4b21
|
896 |
struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
897 |
|
30b54d50f
|
898 899 900 901 902 903 904 905 906 |
/* Prevent unnecessary standard changes. During a standard change the I-Port is temporarily disabled. Any devices reading from that port can get confused. Note that VIDIOC_S_STD is also used to switch from radio to TV mode, so if a VIDIOC_S_STD is broadcast to all I2C devices then you do not want to have an unwanted side-effect here. */ if (std == state->std) return; |
d9dce96fa
|
907 |
state->std = std; |
e19b2fccc
|
908 909 |
// This works for NTSC-M, SECAM-L and the 50Hz PAL variants. if (std & V4L2_STD_525_60) { |
9415f4b21
|
910 911 912 913 |
v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz "); saa711x_writeregs(sd, saa7115_cfg_60hz_video); saa711x_set_size(sd, 720, 480); |
e19b2fccc
|
914 |
} else { |
9415f4b21
|
915 916 917 918 |
v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz "); saa711x_writeregs(sd, saa7115_cfg_50hz_video); saa711x_set_size(sd, 720, 576); |
e19b2fccc
|
919 |
} |
f89982a97
|
920 |
/* Register 0E - Bits D6-D4 on NO-AUTO mode |
89f75ffc7
|
921 |
(SAA7111 and SAA7113 doesn't have auto mode) |
f89982a97
|
922 923 924 925 926 927 928 |
50 Hz / 625 lines 60 Hz / 525 lines 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz) 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz) 011 NTSC N (3.58MHz) PAL M (3.58MHz) 100 reserved NTSC-Japan (3.58MHz) */ |
89f75ffc7
|
929 930 |
if (state->ident == V4L2_IDENT_SAA7111 || state->ident == V4L2_IDENT_SAA7113) { |
9415f4b21
|
931 |
u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f; |
f89982a97
|
932 |
|
02c17224d
|
933 |
if (std == V4L2_STD_PAL_M) { |
013423588
|
934 |
reg |= 0x30; |
e0028027c
|
935 |
} else if (std == V4L2_STD_PAL_Nc) { |
013423588
|
936 |
reg |= 0x20; |
02c17224d
|
937 |
} else if (std == V4L2_STD_PAL_60) { |
013423588
|
938 |
reg |= 0x10; |
02c17224d
|
939 |
} else if (std == V4L2_STD_NTSC_M_JP) { |
013423588
|
940 |
reg |= 0x40; |
a9aaec4e8
|
941 |
} else if (std & V4L2_STD_SECAM) { |
fc2fa31f4
|
942 |
reg |= 0x50; |
f89982a97
|
943 |
} |
9415f4b21
|
944 |
saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg); |
89f75ffc7
|
945 946 |
} else { /* restart task B if needed */ |
9415f4b21
|
947 |
int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10; |
f89982a97
|
948 |
|
89f75ffc7
|
949 |
if (taskb && state->ident == V4L2_IDENT_SAA7114) { |
9415f4b21
|
950 |
saa711x_writeregs(sd, saa7115_cfg_vbi_on); |
89f75ffc7
|
951 |
} |
e19b2fccc
|
952 |
|
89f75ffc7
|
953 |
/* switch audio mode too! */ |
9415f4b21
|
954 |
saa711x_s_clock_freq(sd, state->audclk_freq); |
21fa715e6
|
955 |
} |
e19b2fccc
|
956 957 958 |
} /* setup the sliced VBI lcr registers according to the sliced VBI format */ |
9415f4b21
|
959 |
static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt) |
e19b2fccc
|
960 |
{ |
9415f4b21
|
961 |
struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
962 963 964 |
int is_50hz = (state->std & V4L2_STD_625_50); u8 lcr[24]; int i, x; |
89f75ffc7
|
965 966 |
#if 1 /* saa7113/7114/7118 VBI support are experimental */ |
9415f4b21
|
967 |
if (!saa711x_has_reg(state->ident, R_41_LCR_BASE)) |
89f75ffc7
|
968 969 970 971 |
return; #else /* SAA7113 and SAA7118 also should support VBI - Need testing */ |
f5762e441
|
972 |
if (state->ident != V4L2_IDENT_SAA7115) |
e19b2fccc
|
973 |
return; |
89f75ffc7
|
974 |
#endif |
e19b2fccc
|
975 976 977 |
for (i = 0; i <= 23; i++) lcr[i] = 0xff; |
a8b864354
|
978 |
if (fmt == NULL) { |
e19b2fccc
|
979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 |
/* raw VBI */ if (is_50hz) for (i = 6; i <= 23; i++) lcr[i] = 0xdd; else for (i = 10; i <= 21; i++) lcr[i] = 0xdd; } else { /* sliced VBI */ /* first clear lines that cannot be captured */ if (is_50hz) { for (i = 0; i <= 5; i++) fmt->service_lines[0][i] = fmt->service_lines[1][i] = 0; } else { for (i = 0; i <= 9; i++) fmt->service_lines[0][i] = fmt->service_lines[1][i] = 0; for (i = 22; i <= 23; i++) fmt->service_lines[0][i] = fmt->service_lines[1][i] = 0; } /* Now set the lcr values according to the specified service */ for (i = 6; i <= 23; i++) { lcr[i] = 0; for (x = 0; x <= 1; x++) { switch (fmt->service_lines[1-x][i]) { case 0: lcr[i] |= 0xf << (4 * x); break; |
9bc7400a9
|
1011 |
case V4L2_SLICED_TELETEXT_B: |
e19b2fccc
|
1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 |
lcr[i] |= 1 << (4 * x); break; case V4L2_SLICED_CAPTION_525: lcr[i] |= 4 << (4 * x); break; case V4L2_SLICED_WSS_625: lcr[i] |= 5 << (4 * x); break; case V4L2_SLICED_VPS: lcr[i] |= 7 << (4 * x); break; } } } } /* write the lcr registers */ for (i = 2; i <= 23; i++) { |
9415f4b21
|
1030 |
saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]); |
e19b2fccc
|
1031 1032 1033 |
} /* enable/disable raw VBI capturing */ |
9415f4b21
|
1034 |
saa711x_writeregs(sd, fmt == NULL ? |
96ecfc4ed
|
1035 1036 |
saa7115_cfg_vbi_on : saa7115_cfg_vbi_off); |
e19b2fccc
|
1037 |
} |
9415f4b21
|
1038 |
static int saa711x_g_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
e19b2fccc
|
1039 1040 |
{ static u16 lcr2vbi[] = { |
9bc7400a9
|
1041 |
0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */ |
e19b2fccc
|
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 |
0, V4L2_SLICED_CAPTION_525, /* 4 */ V4L2_SLICED_WSS_625, 0, /* 5 */ V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */ 0, 0, 0, 0 }; struct v4l2_sliced_vbi_format *sliced = &fmt->fmt.sliced; int i; if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE) return -EINVAL; memset(sliced, 0, sizeof(*sliced)); /* done if using raw VBI */ |
9415f4b21
|
1054 |
if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10) |
e19b2fccc
|
1055 1056 |
return 0; for (i = 2; i <= 23; i++) { |
9415f4b21
|
1057 |
u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE); |
e19b2fccc
|
1058 1059 1060 1061 1062 1063 1064 1065 |
sliced->service_lines[0][i] = lcr2vbi[v >> 4]; sliced->service_lines[1][i] = lcr2vbi[v & 0xf]; sliced->service_set |= sliced->service_lines[0][i] | sliced->service_lines[1][i]; } return 0; } |
9415f4b21
|
1066 |
static int saa711x_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt) |
59ba91549
|
1067 1068 |
{ if (fmt->type == V4L2_BUF_TYPE_SLICED_VBI_CAPTURE) { |
9415f4b21
|
1069 |
saa711x_set_lcr(sd, &fmt->fmt.sliced); |
59ba91549
|
1070 1071 |
return 0; } |
a8b864354
|
1072 |
if (fmt->type == V4L2_BUF_TYPE_VBI_CAPTURE) { |
9415f4b21
|
1073 |
saa711x_set_lcr(sd, NULL); |
a8b864354
|
1074 1075 |
return 0; } |
59ba91549
|
1076 1077 |
if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) return -EINVAL; |
9415f4b21
|
1078 |
return saa711x_set_size(sd, fmt->fmt.pix.width, fmt->fmt.pix.height); |
59ba91549
|
1079 |
} |
e19b2fccc
|
1080 1081 1082 1083 |
/* Decode the sliced VBI data stream as created by the saa7115. The format is described in the saa7115 datasheet in Tables 25 and 26 and in Figure 33. The current implementation uses SAV/EAV codes and not the ancillary data |
96ecfc4ed
|
1084 |
headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV |
e19b2fccc
|
1085 |
code. */ |
9415f4b21
|
1086 |
static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi) |
e19b2fccc
|
1087 |
{ |
9415f4b21
|
1088 |
struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
1089 1090 1091 |
static const char vbi_no_data_pattern[] = { 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0 }; |
e19b2fccc
|
1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 |
u8 *p = vbi->p; u32 wss; int id1, id2; /* the ID1 and ID2 bytes from the internal header */ vbi->type = 0; /* mark result as a failure */ id1 = p[2]; id2 = p[3]; /* Note: the field bit is inverted for 60 Hz video */ if (state->std & V4L2_STD_525_60) id1 ^= 0x40; /* Skip internal header, p now points to the start of the payload */ p += 4; vbi->p = p; /* calculate field and line number of the VBI packet (1-23) */ vbi->is_second_field = ((id1 & 0x40) != 0); vbi->line = (id1 & 0x3f) << 3; vbi->line |= (id2 & 0x70) >> 4; /* Obtain data type */ id2 &= 0xf; /* If the VBI slicer does not detect any signal it will fill up the payload buffer with 0xa0 bytes. */ if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern))) |
9415f4b21
|
1118 |
return 0; |
e19b2fccc
|
1119 1120 1121 1122 |
/* decode payloads */ switch (id2) { case 1: |
9bc7400a9
|
1123 |
vbi->type = V4L2_SLICED_TELETEXT_B; |
e19b2fccc
|
1124 1125 |
break; case 4: |
59ba91549
|
1126 |
if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1])) |
9415f4b21
|
1127 |
return 0; |
e19b2fccc
|
1128 1129 1130 |
vbi->type = V4L2_SLICED_CAPTION_525; break; case 5: |
66ec1193b
|
1131 |
wss = saa711x_decode_wss(p); |
e19b2fccc
|
1132 |
if (wss == -1) |
9415f4b21
|
1133 |
return 0; |
e19b2fccc
|
1134 1135 1136 1137 1138 |
p[0] = wss & 0xff; p[1] = wss >> 8; vbi->type = V4L2_SLICED_WSS_625; break; case 7: |
66ec1193b
|
1139 |
if (saa711x_decode_vps(p, p) != 0) |
9415f4b21
|
1140 |
return 0; |
e19b2fccc
|
1141 1142 1143 |
vbi->type = V4L2_SLICED_VPS; break; default: |
9415f4b21
|
1144 |
break; |
e19b2fccc
|
1145 |
} |
9415f4b21
|
1146 |
return 0; |
e19b2fccc
|
1147 1148 1149 |
} /* ============ SAA7115 AUDIO settings (end) ============= */ |
9415f4b21
|
1150 |
static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) |
e19b2fccc
|
1151 |
{ |
9415f4b21
|
1152 1153 |
struct saa711x_state *state = to_state(sd); int status; |
e19b2fccc
|
1154 |
|
9415f4b21
|
1155 1156 1157 |
if (state->radio) return 0; status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); |
e19b2fccc
|
1158 |
|
9415f4b21
|
1159 1160 1161 1162 1163 |
v4l2_dbg(1, debug, sd, "status: 0x%02x ", status); vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0; return 0; } |
e19b2fccc
|
1164 |
|
9415f4b21
|
1165 1166 1167 1168 |
static int saa711x_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc) { switch (qc->id) { case V4L2_CID_BRIGHTNESS: |
10afbef15
|
1169 |
return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); |
9415f4b21
|
1170 1171 |
case V4L2_CID_CONTRAST: case V4L2_CID_SATURATION: |
10afbef15
|
1172 |
return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); |
9415f4b21
|
1173 |
case V4L2_CID_HUE: |
10afbef15
|
1174 |
return v4l2_ctrl_query_fill(qc, -128, 127, 1, 0); |
9415f4b21
|
1175 1176 1177 1178 |
default: return -EINVAL; } } |
e19b2fccc
|
1179 |
|
9415f4b21
|
1180 1181 1182 |
static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std) { struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
1183 |
|
9415f4b21
|
1184 1185 1186 1187 |
state->radio = 0; saa711x_set_v4lstd(sd, std); return 0; } |
e19b2fccc
|
1188 |
|
9415f4b21
|
1189 1190 1191 |
static int saa711x_s_radio(struct v4l2_subdev *sd) { struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
1192 |
|
9415f4b21
|
1193 1194 1195 |
state->radio = 1; return 0; } |
e19b2fccc
|
1196 |
|
9415f4b21
|
1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 |
static int saa711x_s_routing(struct v4l2_subdev *sd, const struct v4l2_routing *route) { struct saa711x_state *state = to_state(sd); u32 input = route->input; u8 mask = (state->ident == V4L2_IDENT_SAA7111) ? 0xf8 : 0xf0; v4l2_dbg(1, debug, sd, "decoder set input %d output %d ", route->input, route->output); /* saa7111/3 does not have these inputs */ if ((state->ident == V4L2_IDENT_SAA7113 || state->ident == V4L2_IDENT_SAA7111) && (route->input == SAA7115_COMPOSITE4 || route->input == SAA7115_COMPOSITE5)) { return -EINVAL; } if (route->input > SAA7115_SVIDEO3) return -EINVAL; if (route->output > SAA7115_IPORT_ON) return -EINVAL; if (state->input == route->input && state->output == route->output) return 0; v4l2_dbg(1, debug, sd, "now setting %s input %s output ", (route->input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite", (route->output == SAA7115_IPORT_ON) ? "iport on" : "iport off"); state->input = route->input; /* saa7111 has slightly different input numbering */ if (state->ident == V4L2_IDENT_SAA7111) { if (input >= SAA7115_COMPOSITE4) input -= 2; /* saa7111 specific */ saa711x_write(sd, R_10_CHROMA_CNTL_2, (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) | ((route->output & 0xc0) ^ 0x40)); saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) | ((route->output & 2) ? 0x0a : 0)); } |
e19b2fccc
|
1236 |
|
9415f4b21
|
1237 1238 1239 1240 |
/* select mode */ saa711x_write(sd, R_02_INPUT_CNTL_1, (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) | input); |
e19b2fccc
|
1241 |
|
9415f4b21
|
1242 1243 1244 1245 |
/* bypass chrominance trap for S-Video modes */ saa711x_write(sd, R_09_LUMA_CNTL, (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) | (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0)); |
da4ae5a72
|
1246 |
|
9415f4b21
|
1247 1248 1249 1250 1251 1252 |
state->output = route->output; if (state->ident == V4L2_IDENT_SAA7114 || state->ident == V4L2_IDENT_SAA7115) { saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK, (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) | (state->output & 0x01)); |
da4ae5a72
|
1253 |
} |
9415f4b21
|
1254 1255 |
return 0; } |
da4ae5a72
|
1256 |
|
9415f4b21
|
1257 1258 1259 |
static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val) { struct saa711x_state *state = to_state(sd); |
e19b2fccc
|
1260 |
|
9415f4b21
|
1261 1262 1263 1264 1265 1266 |
if (state->ident != V4L2_IDENT_SAA7111) return -EINVAL; saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) | (val ? 0x80 : 0)); return 0; } |
e19b2fccc
|
1267 |
|
9415f4b21
|
1268 1269 1270 |
static int saa711x_s_stream(struct v4l2_subdev *sd, int enable) { struct saa711x_state *state = to_state(sd); |
3faeeae48
|
1271 |
|
9415f4b21
|
1272 1273 1274 |
v4l2_dbg(1, debug, sd, "%s output ", enable ? "enable" : "disable"); |
1f8f5fa9b
|
1275 |
|
674a32321
|
1276 1277 1278 1279 1280 1281 |
if (state->enable == enable) return 0; state->enable = enable; if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED)) return 0; saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable); |
9415f4b21
|
1282 1283 |
return 0; } |
1f8f5fa9b
|
1284 |
|
9415f4b21
|
1285 1286 1287 |
static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, struct v4l2_crystal_freq *freq) { struct saa711x_state *state = to_state(sd); |
6bd6dff63
|
1288 |
|
9415f4b21
|
1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 |
if (freq->freq != SAA7115_FREQ_32_11_MHZ && freq->freq != SAA7115_FREQ_24_576_MHZ) return -EINVAL; state->crystal_freq = freq->freq; state->cgcdiv = (freq->flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4; state->ucgc = (freq->flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0; state->apll = (freq->flags & SAA7115_FREQ_FL_APLL) ? 1 : 0; saa711x_s_clock_freq(sd, state->audclk_freq); return 0; } |
1f8f5fa9b
|
1299 |
|
9415f4b21
|
1300 1301 1302 1303 1304 1305 1306 |
static int saa711x_reset(struct v4l2_subdev *sd, u32 val) { v4l2_dbg(1, debug, sd, "decoder RESET "); saa711x_writeregs(sd, saa7115_cfg_reset_scaler); return 0; } |
4cbca185e
|
1307 |
|
9415f4b21
|
1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 |
static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data) { /* Note: the internal field ID is inverted for NTSC, so data->field 0 maps to the saa7115 even field, whereas for PAL it maps to the saa7115 odd field. */ switch (data->id) { case V4L2_SLICED_WSS_625: if (saa711x_read(sd, 0x6b) & 0xc0) return -EIO; data->data[0] = saa711x_read(sd, 0x6c); data->data[1] = saa711x_read(sd, 0x6d); return 0; case V4L2_SLICED_CAPTION_525: if (data->field == 0) { /* CC */ if (saa711x_read(sd, 0x66) & 0x30) return -EIO; data->data[0] = saa711x_read(sd, 0x69); data->data[1] = saa711x_read(sd, 0x6a); return 0; |
4cbca185e
|
1328 |
} |
9415f4b21
|
1329 1330 1331 1332 1333 1334 1335 1336 |
/* XDS */ if (saa711x_read(sd, 0x66) & 0xc0) return -EIO; data->data[0] = saa711x_read(sd, 0x67); data->data[1] = saa711x_read(sd, 0x68); return 0; default: return -EINVAL; |
1f8f5fa9b
|
1337 |
} |
9415f4b21
|
1338 |
} |
1f8f5fa9b
|
1339 |
|
17bdd9ddd
|
1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 |
static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) { struct saa711x_state *state = to_state(sd); int reg1e; *std = V4L2_STD_ALL; if (state->ident != V4L2_IDENT_SAA7115) return 0; reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); switch (reg1e & 0x03) { case 1: *std = V4L2_STD_NTSC; break; case 2: *std = V4L2_STD_PAL; break; case 3: *std = V4L2_STD_SECAM; break; default: break; } return 0; } static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status) { struct saa711x_state *state = to_state(sd); int reg1e = 0x80; int reg1f; *status = V4L2_IN_ST_NO_SIGNAL; if (state->ident == V4L2_IDENT_SAA7115) reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80) *status = 0; return 0; } |
9415f4b21
|
1380 |
#ifdef CONFIG_VIDEO_ADV_DEBUG |
aecde8b53
|
1381 |
static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) |
9415f4b21
|
1382 1383 |
{ struct i2c_client *client = v4l2_get_subdevdata(sd); |
e19b2fccc
|
1384 |
|
aecde8b53
|
1385 |
if (!v4l2_chip_match_i2c_client(client, ®->match)) |
9415f4b21
|
1386 1387 1388 1389 |
return -EINVAL; if (!capable(CAP_SYS_ADMIN)) return -EPERM; reg->val = saa711x_read(sd, reg->reg & 0xff); |
aecde8b53
|
1390 |
reg->size = 1; |
9415f4b21
|
1391 1392 |
return 0; } |
b7f8292c9
|
1393 |
|
aecde8b53
|
1394 |
static int saa711x_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) |
9415f4b21
|
1395 1396 |
{ struct i2c_client *client = v4l2_get_subdevdata(sd); |
b7f8292c9
|
1397 |
|
aecde8b53
|
1398 |
if (!v4l2_chip_match_i2c_client(client, ®->match)) |
9415f4b21
|
1399 1400 1401 1402 1403 1404 1405 |
return -EINVAL; if (!capable(CAP_SYS_ADMIN)) return -EPERM; saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff); return 0; } #endif |
e19b2fccc
|
1406 |
|
aecde8b53
|
1407 |
static int saa711x_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip) |
9415f4b21
|
1408 1409 1410 |
{ struct saa711x_state *state = to_state(sd); struct i2c_client *client = v4l2_get_subdevdata(sd); |
e19b2fccc
|
1411 |
|
9415f4b21
|
1412 1413 |
return v4l2_chip_ident_i2c_client(client, chip, state->ident, 0); } |
6bd6dff63
|
1414 |
|
9415f4b21
|
1415 1416 1417 1418 1419 1420 |
static int saa711x_log_status(struct v4l2_subdev *sd) { struct saa711x_state *state = to_state(sd); int reg1e, reg1f; int signalOk; int vcr; |
e19b2fccc
|
1421 |
|
9415f4b21
|
1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 |
v4l2_info(sd, "Audio frequency: %d Hz ", state->audclk_freq); if (state->ident != V4L2_IDENT_SAA7115) { /* status for the saa7114 */ reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); signalOk = (reg1f & 0xc1) == 0x81; v4l2_info(sd, "Video signal: %s ", signalOk ? "ok" : "bad"); v4l2_info(sd, "Frequency: %s ", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); return 0; |
e19b2fccc
|
1433 |
} |
9415f4b21
|
1434 1435 1436 |
/* status for the saa7115 */ reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC); reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC); |
e19b2fccc
|
1437 |
|
9415f4b21
|
1438 1439 |
signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80; vcr = !(reg1f & 0x10); |
e19b2fccc
|
1440 |
|
9415f4b21
|
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 |
if (state->input >= 6) v4l2_info(sd, "Input: S-Video %d ", state->input - 6); else v4l2_info(sd, "Input: Composite %d ", state->input); v4l2_info(sd, "Video signal: %s ", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad"); v4l2_info(sd, "Frequency: %s ", (reg1f & 0x20) ? "60 Hz" : "50 Hz"); |
e19b2fccc
|
1451 |
|
9415f4b21
|
1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 |
switch (reg1e & 0x03) { case 1: v4l2_info(sd, "Detected format: NTSC "); break; case 2: v4l2_info(sd, "Detected format: PAL "); break; case 3: v4l2_info(sd, "Detected format: SECAM "); break; |
e19b2fccc
|
1465 |
default: |
9415f4b21
|
1466 1467 1468 |
v4l2_info(sd, "Detected format: BW/No color "); break; |
e19b2fccc
|
1469 |
} |
9415f4b21
|
1470 1471 |
v4l2_info(sd, "Width, Height: %d, %d ", state->width, state->height); |
e19b2fccc
|
1472 1473 |
return 0; } |
9415f4b21
|
1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 |
static int saa711x_command(struct i2c_client *client, unsigned cmd, void *arg) { return v4l2_subdev_command(i2c_get_clientdata(client), cmd, arg); } /* ----------------------------------------------------------------------- */ static const struct v4l2_subdev_core_ops saa711x_core_ops = { .log_status = saa711x_log_status, .g_chip_ident = saa711x_g_chip_ident, .g_ctrl = saa711x_g_ctrl, .s_ctrl = saa711x_s_ctrl, .queryctrl = saa711x_queryctrl, .reset = saa711x_reset, .s_gpio = saa711x_s_gpio, #ifdef CONFIG_VIDEO_ADV_DEBUG .g_register = saa711x_g_register, .s_register = saa711x_s_register, #endif }; static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = { .s_std = saa711x_s_std, .s_radio = saa711x_s_radio, .g_tuner = saa711x_g_tuner, }; static const struct v4l2_subdev_audio_ops saa711x_audio_ops = { .s_clock_freq = saa711x_s_clock_freq, }; static const struct v4l2_subdev_video_ops saa711x_video_ops = { .s_routing = saa711x_s_routing, .s_crystal_freq = saa711x_s_crystal_freq, .g_fmt = saa711x_g_fmt, .s_fmt = saa711x_s_fmt, .g_vbi_data = saa711x_g_vbi_data, .decode_vbi_line = saa711x_decode_vbi_line, .s_stream = saa711x_s_stream, |
17bdd9ddd
|
1513 1514 |
.querystd = saa711x_querystd, .g_input_status = saa711x_g_input_status, |
9415f4b21
|
1515 1516 1517 1518 1519 1520 1521 1522 |
}; static const struct v4l2_subdev_ops saa711x_ops = { .core = &saa711x_core_ops, .tuner = &saa711x_tuner_ops, .audio = &saa711x_audio_ops, .video = &saa711x_video_ops, }; |
e19b2fccc
|
1523 |
/* ----------------------------------------------------------------------- */ |
9415f4b21
|
1524 |
static int saa711x_probe(struct i2c_client *client, |
d2653e927
|
1525 |
const struct i2c_device_id *id) |
e19b2fccc
|
1526 |
{ |
66ec1193b
|
1527 |
struct saa711x_state *state; |
9415f4b21
|
1528 |
struct v4l2_subdev *sd; |
236f16d24
|
1529 1530 |
int i; char name[17]; |
af294867a
|
1531 1532 |
char chip_id; int autodetect = !id || id->driver_data == 1; |
e19b2fccc
|
1533 1534 |
/* Check if the adapter supports the needed features */ |
fbaa3d0db
|
1535 |
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
188f3457c
|
1536 |
return -EIO; |
e19b2fccc
|
1537 |
|
d0d30c03e
|
1538 |
for (i = 0; i < 0x0f; i++) { |
9415f4b21
|
1539 1540 |
i2c_smbus_write_byte_data(client, 0, i); name[i] = (i2c_smbus_read_byte_data(client, 0) & 0x0f) + '0'; |
d0d30c03e
|
1541 1542 |
if (name[i] > '9') name[i] += 'a' - '9' - 1; |
236f16d24
|
1543 |
} |
d0d30c03e
|
1544 |
name[i] = '\0'; |
236f16d24
|
1545 |
|
af294867a
|
1546 |
chip_id = name[5]; |
3e7d3e573
|
1547 |
|
f7668162a
|
1548 1549 1550 1551 |
/* Check whether this chip is part of the saa711x series */ if (memcmp(name, "1f711", 5)) { v4l_dbg(1, debug, client, "chip found @ 0x%x (ID %s) does not match a known saa711x chip. ", |
fbaa3d0db
|
1552 |
client->addr << 1, name); |
188f3457c
|
1553 |
return -ENODEV; |
f7668162a
|
1554 |
} |
af294867a
|
1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 |
/* Safety check */ if (!autodetect && id->name[6] != chip_id) { v4l_warn(client, "found saa711%c while %s was expected ", chip_id, id->name); } snprintf(client->name, sizeof(client->name), "saa711%c", chip_id); v4l_info(client, "saa711%c found (%s) @ 0x%x (%s) ", chip_id, name, client->addr << 1, client->adapter->name); |
e19b2fccc
|
1565 |
|
66ec1193b
|
1566 |
state = kzalloc(sizeof(struct saa711x_state), GFP_KERNEL); |
c5bf204f4
|
1567 |
if (state == NULL) |
e19b2fccc
|
1568 |
return -ENOMEM; |
9415f4b21
|
1569 1570 |
sd = &state->sd; v4l2_i2c_subdev_init(sd, client, &saa711x_ops); |
e19b2fccc
|
1571 |
state->input = -1; |
4cbca185e
|
1572 |
state->output = SAA7115_IPORT_ON; |
e19b2fccc
|
1573 |
state->enable = 1; |
3faeeae48
|
1574 |
state->radio = 0; |
e19b2fccc
|
1575 1576 1577 1578 |
state->bright = 128; state->contrast = 64; state->hue = 0; state->sat = 64; |
f5762e441
|
1579 |
switch (chip_id) { |
af294867a
|
1580 |
case '1': |
89f75ffc7
|
1581 1582 |
state->ident = V4L2_IDENT_SAA7111; break; |
af294867a
|
1583 |
case '3': |
f5762e441
|
1584 1585 |
state->ident = V4L2_IDENT_SAA7113; break; |
af294867a
|
1586 |
case '4': |
f5762e441
|
1587 1588 |
state->ident = V4L2_IDENT_SAA7114; break; |
af294867a
|
1589 |
case '5': |
f5762e441
|
1590 1591 |
state->ident = V4L2_IDENT_SAA7115; break; |
af294867a
|
1592 |
case '8': |
89f75ffc7
|
1593 1594 1595 1596 |
state->ident = V4L2_IDENT_SAA7118; break; default: state->ident = V4L2_IDENT_SAA7111; |
9415f4b21
|
1597 1598 |
v4l2_info(sd, "WARNING: Chip is not known - Falling back to saa7111 "); |
89f75ffc7
|
1599 |
|
f5762e441
|
1600 |
} |
3578d3dd0
|
1601 |
state->audclk_freq = 48000; |
e19b2fccc
|
1602 |
|
9415f4b21
|
1603 1604 |
v4l2_dbg(1, debug, sd, "writing init values "); |
e19b2fccc
|
1605 1606 |
/* init to 60hz/48khz */ |
183d896a0
|
1607 1608 1609 |
state->crystal_freq = SAA7115_FREQ_24_576_MHZ; switch (state->ident) { case V4L2_IDENT_SAA7111: |
9415f4b21
|
1610 |
saa711x_writeregs(sd, saa7111_init); |
183d896a0
|
1611 1612 |
break; case V4L2_IDENT_SAA7113: |
9415f4b21
|
1613 |
saa711x_writeregs(sd, saa7113_init); |
183d896a0
|
1614 1615 |
break; default: |
b7f8292c9
|
1616 |
state->crystal_freq = SAA7115_FREQ_32_11_MHZ; |
9415f4b21
|
1617 |
saa711x_writeregs(sd, saa7115_init_auto_input); |
b7f8292c9
|
1618 |
} |
6bd6dff63
|
1619 |
if (state->ident != V4L2_IDENT_SAA7111) |
9415f4b21
|
1620 1621 |
saa711x_writeregs(sd, saa7115_init_misc); saa711x_set_v4lstd(sd, V4L2_STD_NTSC); |
e19b2fccc
|
1622 |
|
9415f4b21
|
1623 1624 1625 1626 |
v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x ", saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC), saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC)); |
e19b2fccc
|
1627 1628 |
return 0; } |
fbaa3d0db
|
1629 |
/* ----------------------------------------------------------------------- */ |
e19b2fccc
|
1630 |
|
9415f4b21
|
1631 |
static int saa711x_remove(struct i2c_client *client) |
e19b2fccc
|
1632 |
{ |
9415f4b21
|
1633 1634 1635 1636 |
struct v4l2_subdev *sd = i2c_get_clientdata(client); v4l2_device_unregister_subdev(sd); kfree(to_state(sd)); |
e19b2fccc
|
1637 1638 |
return 0; } |
af294867a
|
1639 |
static const struct i2c_device_id saa7115_id[] = { |
9edd350f5
|
1640 |
{ "saa7115_auto", 1 }, /* autodetect */ |
af294867a
|
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{ "saa7111", 0 }, { "saa7113", 0 }, { "saa7114", 0 }, { "saa7115", 0 }, { "saa7118", 0 }, { } }; MODULE_DEVICE_TABLE(i2c, saa7115_id); |
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static struct v4l2_i2c_driver_data v4l2_i2c_data = { .name = "saa7115", .driverid = I2C_DRIVERID_SAA711X, |
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.command = saa711x_command, .probe = saa711x_probe, .remove = saa711x_remove, |
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.legacy_class = I2C_CLASS_TV_ANALOG | I2C_CLASS_TV_DIGITAL, |
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.id_table = saa7115_id, |
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}; |