Blame view
include/linux/sh_intc.h
3.11 KB
bbfbd8b15
|
1 2 |
#ifndef __SH_INTC_H #define __SH_INTC_H |
dec710b77
|
3 |
#include <linux/ioport.h> |
bbfbd8b15
|
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 |
typedef unsigned char intc_enum; struct intc_vect { intc_enum enum_id; unsigned short vect; }; #define INTC_VECT(enum_id, vect) { enum_id, vect } #define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq)) struct intc_group { intc_enum enum_id; intc_enum enum_ids[32]; }; #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } } |
c1e30ad98
|
20 21 22 23 24 |
struct intc_subgroup { unsigned long reg, reg_width; intc_enum parent_id; intc_enum enum_ids[32]; }; |
bbfbd8b15
|
25 26 27 |
struct intc_mask_reg { unsigned long set_reg, clr_reg, reg_width; intc_enum enum_ids[32]; |
dc825b179
|
28 29 30 |
#ifdef CONFIG_INTC_BALANCING unsigned long dist_reg; #endif |
bbfbd8b15
|
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 |
#ifdef CONFIG_SMP unsigned long smp; #endif }; struct intc_prio_reg { unsigned long set_reg, clr_reg, reg_width, field_width; intc_enum enum_ids[16]; #ifdef CONFIG_SMP unsigned long smp; #endif }; struct intc_sense_reg { unsigned long reg, reg_width, field_width; intc_enum enum_ids[16]; }; |
dc825b179
|
48 49 50 51 52 |
#ifdef CONFIG_INTC_BALANCING #define INTC_SMP_BALANCING(reg) .dist_reg = (reg) #else #define INTC_SMP_BALANCING(reg) #endif |
bbfbd8b15
|
53 |
#ifdef CONFIG_SMP |
dc825b179
|
54 |
#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8) |
bbfbd8b15
|
55 56 57 |
#else #define INTC_SMP(stride, nr) #endif |
577cd7584
|
58 |
struct intc_hw_desc { |
bbfbd8b15
|
59 60 61 62 63 64 65 66 67 68 |
struct intc_vect *vectors; unsigned int nr_vectors; struct intc_group *groups; unsigned int nr_groups; struct intc_mask_reg *mask_regs; unsigned int nr_mask_regs; struct intc_prio_reg *prio_regs; unsigned int nr_prio_regs; struct intc_sense_reg *sense_regs; unsigned int nr_sense_regs; |
bbfbd8b15
|
69 70 |
struct intc_mask_reg *ack_regs; unsigned int nr_ack_regs; |
c1e30ad98
|
71 72 |
struct intc_subgroup *subgroups; unsigned int nr_subgroups; |
bbfbd8b15
|
73 |
}; |
99870bd78
|
74 |
#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a) |
c1e30ad98
|
75 |
|
577cd7584
|
76 77 78 79 80 81 82 83 84 85 |
#define INTC_HW_DESC(vectors, groups, mask_regs, \ prio_regs, sense_regs, ack_regs) \ { \ _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ _INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \ } struct intc_desc { char *name; |
dec710b77
|
86 87 |
struct resource *resource; unsigned int num_resources; |
d51909534
|
88 |
intc_enum force_enable; |
d85429a31
|
89 |
intc_enum force_disable; |
577cd7584
|
90 91 |
struct intc_hw_desc hw; }; |
bbfbd8b15
|
92 93 94 |
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ mask_regs, prio_regs, sense_regs) \ struct intc_desc symbol __initdata = { \ |
577cd7584
|
95 96 97 |
.name = chipname, \ .hw = INTC_HW_DESC(vectors, groups, mask_regs, \ prio_regs, sense_regs, NULL), \ |
bbfbd8b15
|
98 |
} |
bbfbd8b15
|
99 100 101 |
#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \ mask_regs, prio_regs, sense_regs, ack_regs) \ struct intc_desc symbol __initdata = { \ |
577cd7584
|
102 103 104 |
.name = chipname, \ .hw = INTC_HW_DESC(vectors, groups, mask_regs, \ prio_regs, sense_regs, ack_regs), \ |
bbfbd8b15
|
105 |
} |
bbfbd8b15
|
106 |
|
2be6bb0c7
|
107 |
int register_intc_controller(struct intc_desc *desc); |
4bacd796c
|
108 |
void reserve_intc_vectors(struct intc_vect *vectors, unsigned int nr_vecs); |
bbfbd8b15
|
109 |
int intc_set_priority(unsigned int irq, unsigned int prio); |
d74310d3b
|
110 |
int intc_irq_lookup(const char *chipname, intc_enum enum_id); |
c1e30ad98
|
111 |
void intc_finalize(void); |
bbfbd8b15
|
112 |
|
43b8774dc
|
113 114 115 116 117 118 119 120 |
#ifdef CONFIG_INTC_USERIMASK int register_intc_userimask(unsigned long addr); #else static inline int register_intc_userimask(unsigned long addr) { return 0; } #endif |
bbfbd8b15
|
121 |
#endif /* __SH_INTC_H */ |