Eric Lee / linux-smarc-t335x-v3.2

Commit 61f2e7b0f474225b4226772830ae4b29a3a21f8d

Authored by Akinobu Mita 2011-03-24 07:42:16 +0800

Committed by Linus Torvalds 2011-03-24 10:46:22 +0800

Exists in master and in 4 other branches

bitops: remove minix bitops from asm/bitops.h

minix bit operations are only used by minix filesystem and useless by
other modules.  Because byte order of inode and block bitmaps is different
on each architecture like below:

m68k:
	big-endian 16bit indexed bitmaps

h8300, microblaze, s390, sparc, m68knommu:
	big-endian 32 or 64bit indexed bitmaps

m32r, mips, sh, xtensa:
	big-endian 32 or 64bit indexed bitmaps for big-endian mode
	little-endian bitmaps for little-endian mode

Others:
	little-endian bitmaps

In order to move minix bit operations from asm/bitops.h to architecture
independent code in minix filesystem, this provides two config options.

CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k.
CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use
native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu,
m32r, mips, sh, xtensa).  The architectures which always use little-endian
bitmaps do not select these options.

Finally, we can remove minix bit operations from asm/bitops.h for all
architectures.

Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Michal Simek <monstr@monstr.eu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 27 changed files with 82 additions and 110 deletions Inline Diff

arch/alpha/include/asm/bitops.h
arch/arm/include/asm/bitops.h
arch/avr32/include/asm/bitops.h
arch/blackfin/include/asm/bitops.h
arch/cris/include/asm/bitops.h
arch/frv/include/asm/bitops.h
arch/h8300/include/asm/bitops.h
arch/ia64/include/asm/bitops.h
arch/m32r/include/asm/bitops.h
arch/m68k/include/asm/bitops_mm.h
arch/m68k/include/asm/bitops_no.h
arch/mips/include/asm/bitops.h
arch/mn10300/include/asm/bitops.h
arch/parisc/include/asm/bitops.h
arch/powerpc/include/asm/bitops.h
arch/s390/include/asm/bitops.h
arch/sh/include/asm/bitops.h
arch/sparc/include/asm/bitops_32.h
arch/sparc/include/asm/bitops_64.h
arch/tile/include/asm/bitops.h
arch/x86/include/asm/bitops.h
arch/xtensa/include/asm/bitops.h
fs/minix/Kconfig
fs/minix/minix.h
include/asm-generic/bitops.h
include/asm-generic/bitops/minix-le.h
include/asm-generic/bitops/minix.h

arch/alpha/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _ALPHA_BITOPS_H
 #define _ALPHA_BITOPS_H
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm/compiler.h>
 #include <asm/barrier.h>
 /*
  * Copyright 1994, Linus Torvalds.
  */
 /*
  * These have to be done with inline assembly: that way the bit-setting
  * is guaranteed to be atomic. All bit operations return 0 if the bit
  * was cleared before the operation and != 0 if it was not.
  *
  * To get proper branch prediction for the main line, we must branch
  * forward to code at the end of this object's .text section, then
  * branch back to restart the operation.
  *
  * bit 0 is the LSB of addr; bit 64 is the LSB of (addr+1).
  */
 static inline void
 set_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 	"1:	ldl_l %0,%3\n"
 	"	bis %0,%2,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,2f\n"
 	".subsection 2\n"
 	"2:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m)
 	:"Ir" (1UL << (nr & 31)), "m" (*m));
 }
 /*
  * WARNING: non atomic version.
  */
 static inline void
 __set_bit(unsigned long nr, volatile void * addr)
 {
 	int *m = ((int *) addr) + (nr >> 5);
 	*m |= 1 << (nr & 31);
 }
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
 static inline void
 clear_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 	"1:	ldl_l %0,%3\n"
 	"	bic %0,%2,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,2f\n"
 	".subsection 2\n"
 	"2:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m)
 	:"Ir" (1UL << (nr & 31)), "m" (*m));
 }
 static inline void
 clear_bit_unlock(unsigned long nr, volatile void * addr)
 {
 	smp_mb();
 	clear_bit(nr, addr);
 }
 /*
  * WARNING: non atomic version.
  */
 static __inline__ void
 __clear_bit(unsigned long nr, volatile void * addr)
 {
 	int *m = ((int *) addr) + (nr >> 5);
 	*m &= ~(1 << (nr & 31));
 }
 static inline void
 __clear_bit_unlock(unsigned long nr, volatile void * addr)
 {
 	smp_mb();
 	__clear_bit(nr, addr);
 }
 static inline void
 change_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 	"1:	ldl_l %0,%3\n"
 	"	xor %0,%2,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,2f\n"
 	".subsection 2\n"
 	"2:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m)
 	:"Ir" (1UL << (nr & 31)), "m" (*m));
 }
 /*
  * WARNING: non atomic version.
  */
 static __inline__ void
 __change_bit(unsigned long nr, volatile void * addr)
 {
 	int *m = ((int *) addr) + (nr >> 5);
 	*m ^= 1 << (nr & 31);
 }
 static inline int
 test_and_set_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned long oldbit;
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	"1:	ldl_l %0,%4\n"
 	"	and %0,%3,%2\n"
 	"	bne %2,2f\n"
 	"	xor %0,%3,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,3f\n"
 	"2:\n"
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	".subsection 2\n"
 	"3:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
 	:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
 	return oldbit != 0;
 }
 static inline int
 test_and_set_bit_lock(unsigned long nr, volatile void *addr)
 {
 	unsigned long oldbit;
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 	"1:	ldl_l %0,%4\n"
 	"	and %0,%3,%2\n"
 	"	bne %2,2f\n"
 	"	xor %0,%3,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,3f\n"
 	"2:\n"
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	".subsection 2\n"
 	"3:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
 	:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
 	return oldbit != 0;
 }
 /*
  * WARNING: non atomic version.
  */
 static inline int
 __test_and_set_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long mask = 1 << (nr & 0x1f);
 	int *m = ((int *) addr) + (nr >> 5);
 	int old = *m;
 	*m = old | mask;
 	return (old & mask) != 0;
 }
 static inline int
 test_and_clear_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long oldbit;
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	"1:	ldl_l %0,%4\n"
 	"	and %0,%3,%2\n"
 	"	beq %2,2f\n"
 	"	xor %0,%3,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,3f\n"
 	"2:\n"
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	".subsection 2\n"
 	"3:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
 	:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
 	return oldbit != 0;
 }
 /*
  * WARNING: non atomic version.
  */
 static inline int
 __test_and_clear_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long mask = 1 << (nr & 0x1f);
 	int *m = ((int *) addr) + (nr >> 5);
 	int old = *m;
 	*m = old & ~mask;
 	return (old & mask) != 0;
 }
 static inline int
 test_and_change_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long oldbit;
 	unsigned long temp;
 	int *m = ((int *) addr) + (nr >> 5);
 	__asm__ __volatile__(
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	"1:	ldl_l %0,%4\n"
 	"	and %0,%3,%2\n"
 	"	xor %0,%3,%0\n"
 	"	stl_c %0,%1\n"
 	"	beq %0,3f\n"
 #ifdef CONFIG_SMP
 	"	mb\n"
 #endif
 	".subsection 2\n"
 	"3:	br 1b\n"
 	".previous"
 	:"=&r" (temp), "=m" (*m), "=&r" (oldbit)
 	:"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
 	return oldbit != 0;
 }
 /*
  * WARNING: non atomic version.
  */
 static __inline__ int
 __test_and_change_bit(unsigned long nr, volatile void * addr)
 {
 	unsigned long mask = 1 << (nr & 0x1f);
 	int *m = ((int *) addr) + (nr >> 5);
 	int old = *m;
 	*m = old ^ mask;
 	return (old & mask) != 0;
 }
 static inline int
 test_bit(int nr, const volatile void * addr)
 {
 	return (1UL & (((const int *) addr)[nr >> 5] >> (nr & 31))) != 0UL;
 }
 /*
  * ffz = Find First Zero in word. Undefined if no zero exists,
  * so code should check against ~0UL first..
  *
  * Do a binary search on the bits.  Due to the nature of large
  * constants on the alpha, it is worthwhile to split the search.
  */
 static inline unsigned long ffz_b(unsigned long x)
 {
 	unsigned long sum, x1, x2, x4;
 	x = ~x & -~x;		/* set first 0 bit, clear others */
 	x1 = x & 0xAA;
 	x2 = x & 0xCC;
 	x4 = x & 0xF0;
 	sum = x2 ? 2 : 0;
 	sum += (x4 != 0) * 4;
 	sum += (x1 != 0);
 	return sum;
 }
 static inline unsigned long ffz(unsigned long word)
 {
 #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
 	/* Whee.  EV67 can calculate it directly.  */
 	return __kernel_cttz(~word);
 #else
 	unsigned long bits, qofs, bofs;
 	bits = __kernel_cmpbge(word, ~0UL);
 	qofs = ffz_b(bits);
 	bits = __kernel_extbl(word, qofs);
 	bofs = ffz_b(bits);
 	return qofs*8 + bofs;
 #endif
 }
 /*
  * __ffs = Find First set bit in word.  Undefined if no set bit exists.
  */
 static inline unsigned long __ffs(unsigned long word)
 {
 #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
 	/* Whee.  EV67 can calculate it directly.  */
 	return __kernel_cttz(word);
 #else
 	unsigned long bits, qofs, bofs;
 	bits = __kernel_cmpbge(0, word);
 	qofs = ffz_b(bits);
 	bits = __kernel_extbl(word, qofs);
 	bofs = ffz_b(~bits);
 	return qofs*8 + bofs;
 #endif
 }
 #ifdef __KERNEL__
 /*
  * ffs: find first bit set. This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above __ffs.
  */
 static inline int ffs(int word)
 {
 	int result = __ffs(word) + 1;
 	return word ? result : 0;
 }
 /*
  * fls: find last bit set.
  */
 #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
 static inline int fls64(unsigned long word)
 {
 	return 64 - __kernel_ctlz(word);
 }
 #else
 extern const unsigned char __flsm1_tab[256];
 static inline int fls64(unsigned long x)
 {
 	unsigned long t, a, r;
 	t = __kernel_cmpbge (x, 0x0101010101010101UL);
 	a = __flsm1_tab[t];
 	t = __kernel_extbl (x, a);
 	r = a*8 + __flsm1_tab[t] + (x != 0);
 	return r;
 }
 #endif
 static inline unsigned long __fls(unsigned long x)
 {
 	return fls64(x) - 1;
 }
 static inline int fls(int x)
 {
 	return fls64((unsigned int) x);
 }
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
 #if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
 /* Whee.  EV67 can calculate it directly.  */
 static inline unsigned long __arch_hweight64(unsigned long w)
 {
 	return __kernel_ctpop(w);
 }
 static inline unsigned int __arch_hweight32(unsigned int w)
 {
 	return __arch_hweight64(w);
 }
 static inline unsigned int __arch_hweight16(unsigned int w)
 {
 	return __arch_hweight64(w & 0xffff);
 }
 static inline unsigned int __arch_hweight8(unsigned int w)
 {
 	return __arch_hweight64(w & 0xff);
 }
 #else
 #include <asm-generic/bitops/arch_hweight.h>
 #endif
 #include <asm-generic/bitops/const_hweight.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/find.h>
 #ifdef __KERNEL__
 /*
  * Every architecture must define this function. It's the fastest
  * way of searching a 100-bit bitmap.  It's guaranteed that at least
  * one of the 100 bits is cleared.
  */
 static inline unsigned long
 sched_find_first_bit(const unsigned long b[2])
 {
 	unsigned long b0, b1, ofs, tmp;
 	b0 = b[0];
 	b1 = b[1];
 	ofs = (b0 ? 0 : 64);
 	tmp = (b0 ? b0 : b1);
 	return __ffs(tmp) + ofs;
 }
 #include <asm-generic/bitops/le.h>
 #define ext2_set_bit_atomic(l,n,a)   test_and_set_bit(n,a)
 #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* _ALPHA_BITOPS_H */

arch/arm/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * Copyright 1995, Russell King.
  * Various bits and pieces copyrights include:
  *  Linus Torvalds (test_bit).
  * Big endian support: Copyright 2001, Nicolas Pitre
  *  reworked by rmk.
  *
  * bit 0 is the LSB of an "unsigned long" quantity.
  *
  * Please note that the code in this file should never be included
  * from user space.  Many of these are not implemented in assembler
  * since they would be too costly.  Also, they require privileged
  * instructions (which are not available from user mode) to ensure
  * that they are atomic.
  */
 #ifndef __ASM_ARM_BITOPS_H
 #define __ASM_ARM_BITOPS_H
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <asm/system.h>
 #define smp_mb__before_clear_bit()	mb()
 #define smp_mb__after_clear_bit()	mb()
 /*
  * These functions are the basis of our bit ops.
  *
  * First, the atomic bitops. These use native endian.
  */
 static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
 {
 	unsigned long flags;
 	unsigned long mask = 1UL << (bit & 31);
 	p += bit >> 5;
 	raw_local_irq_save(flags);
 	*p |= mask;
 	raw_local_irq_restore(flags);
 }
 static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
 {
 	unsigned long flags;
 	unsigned long mask = 1UL << (bit & 31);
 	p += bit >> 5;
 	raw_local_irq_save(flags);
 	*p &= ~mask;
 	raw_local_irq_restore(flags);
 }
 static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
 {
 	unsigned long flags;
 	unsigned long mask = 1UL << (bit & 31);
 	p += bit >> 5;
 	raw_local_irq_save(flags);
 	*p ^= mask;
 	raw_local_irq_restore(flags);
 }
 static inline int
 ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
 {
 	unsigned long flags;
 	unsigned int res;
 	unsigned long mask = 1UL << (bit & 31);
 	p += bit >> 5;
 	raw_local_irq_save(flags);
 	res = *p;
 	*p = res | mask;
 	raw_local_irq_restore(flags);
 	return (res & mask) != 0;
 }
 static inline int
 ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
 {
 	unsigned long flags;
 	unsigned int res;
 	unsigned long mask = 1UL << (bit & 31);
 	p += bit >> 5;
 	raw_local_irq_save(flags);
 	res = *p;
 	*p = res & ~mask;
 	raw_local_irq_restore(flags);
 	return (res & mask) != 0;
 }
 static inline int
 ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
 {
 	unsigned long flags;
 	unsigned int res;
 	unsigned long mask = 1UL << (bit & 31);
 	p += bit >> 5;
 	raw_local_irq_save(flags);
 	res = *p;
 	*p = res ^ mask;
 	raw_local_irq_restore(flags);
 	return (res & mask) != 0;
 }
 #include <asm-generic/bitops/non-atomic.h>
 /*
  *  A note about Endian-ness.
  *  -------------------------
  *
  * When the ARM is put into big endian mode via CR15, the processor
  * merely swaps the order of bytes within words, thus:
  *
  *          ------------ physical data bus bits -----------
  *          D31 ... D24  D23 ... D16  D15 ... D8  D7 ... D0
  * little     byte 3       byte 2       byte 1      byte 0
  * big        byte 0       byte 1       byte 2      byte 3
  *
  * This means that reading a 32-bit word at address 0 returns the same
  * value irrespective of the endian mode bit.
  *
  * Peripheral devices should be connected with the data bus reversed in
  * "Big Endian" mode.  ARM Application Note 61 is applicable, and is
  * available from http://www.arm.com/.
  *
  * The following assumes that the data bus connectivity for big endian
  * mode has been followed.
  *
  * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
  */
 /*
  * Native endian assembly bitops.  nr = 0 -> word 0 bit 0.
  */
 extern void _set_bit(int nr, volatile unsigned long * p);
 extern void _clear_bit(int nr, volatile unsigned long * p);
 extern void _change_bit(int nr, volatile unsigned long * p);
 extern int _test_and_set_bit(int nr, volatile unsigned long * p);
 extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
 extern int _test_and_change_bit(int nr, volatile unsigned long * p);
 /*
  * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.
  */
 extern int _find_first_zero_bit_le(const void * p, unsigned size);
 extern int _find_next_zero_bit_le(const void * p, int size, int offset);
 extern int _find_first_bit_le(const unsigned long *p, unsigned size);
 extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
 /*
  * Big endian assembly bitops.  nr = 0 -> byte 3 bit 0.
  */
 extern int _find_first_zero_bit_be(const void * p, unsigned size);
 extern int _find_next_zero_bit_be(const void * p, int size, int offset);
 extern int _find_first_bit_be(const unsigned long *p, unsigned size);
 extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 #ifndef CONFIG_SMP
 /*
  * The __* form of bitops are non-atomic and may be reordered.
  */
 #define ATOMIC_BITOP(name,nr,p)			\
 	(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))
 #else
 #define ATOMIC_BITOP(name,nr,p)		_##name(nr,p)
 #endif
 /*
  * Native endian atomic definitions.
  */
 #define set_bit(nr,p)			ATOMIC_BITOP(set_bit,nr,p)
 #define clear_bit(nr,p)			ATOMIC_BITOP(clear_bit,nr,p)
 #define change_bit(nr,p)		ATOMIC_BITOP(change_bit,nr,p)
 #define test_and_set_bit(nr,p)		ATOMIC_BITOP(test_and_set_bit,nr,p)
 #define test_and_clear_bit(nr,p)	ATOMIC_BITOP(test_and_clear_bit,nr,p)
 #define test_and_change_bit(nr,p)	ATOMIC_BITOP(test_and_change_bit,nr,p)
 #ifndef __ARMEB__
 /*
  * These are the little endian, atomic definitions.
  */
 #define find_first_zero_bit(p,sz)	_find_first_zero_bit_le(p,sz)
 #define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_le(p,sz,off)
 #define find_first_bit(p,sz)		_find_first_bit_le(p,sz)
 #define find_next_bit(p,sz,off)		_find_next_bit_le(p,sz,off)
 #define WORD_BITOFF_TO_LE(x)		((x))
 #else
 /*
  * These are the big endian, atomic definitions.
  */
 #define find_first_zero_bit(p,sz)	_find_first_zero_bit_be(p,sz)
 #define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_be(p,sz,off)
 #define find_first_bit(p,sz)		_find_first_bit_be(p,sz)
 #define find_next_bit(p,sz,off)		_find_next_bit_be(p,sz,off)
 #define WORD_BITOFF_TO_LE(x)		((x) ^ 0x18)
 #endif
 #if __LINUX_ARM_ARCH__ < 5
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/ffs.h>
 #else
 static inline int constant_fls(int x)
 {
 	int r = 32;
 	if (!x)
 		return 0;
 	if (!(x & 0xffff0000u)) {
 		x <<= 16;
 		r -= 16;
 	}
 	if (!(x & 0xff000000u)) {
 		x <<= 8;
 		r -= 8;
 	}
 	if (!(x & 0xf0000000u)) {
 		x <<= 4;
 		r -= 4;
 	}
 	if (!(x & 0xc0000000u)) {
 		x <<= 2;
 		r -= 2;
 	}
 	if (!(x & 0x80000000u)) {
 		x <<= 1;
 		r -= 1;
 	}
 	return r;
 }
 /*
  * On ARMv5 and above those functions can be implemented around
  * the clz instruction for much better code efficiency.
  */
 static inline int fls(int x)
 {
 	int ret;
 	if (__builtin_constant_p(x))
 	       return constant_fls(x);
 	asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
        	ret = 32 - ret;
 	return ret;
 }
 #define __fls(x) (fls(x) - 1)
 #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
 #define __ffs(x) (ffs(x) - 1)
 #define ffz(x) __ffs( ~(x) )
 #endif
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 static inline void __set_bit_le(int nr, void *addr)
 {
 	__set_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline void __clear_bit_le(int nr, void *addr)
 {
 	__clear_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline int __test_and_set_bit_le(int nr, void *addr)
 {
 	return __test_and_set_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline int test_and_set_bit_le(int nr, void *addr)
 {
 	return test_and_set_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline int __test_and_clear_bit_le(int nr, void *addr)
 {
 	return __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline int test_and_clear_bit_le(int nr, void *addr)
 {
 	return test_and_clear_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline int test_bit_le(int nr, const void *addr)
 {
 	return test_bit(WORD_BITOFF_TO_LE(nr), addr);
 }
 static inline int find_first_zero_bit_le(const void *p, unsigned size)
 {
 	return _find_first_zero_bit_le(p, size);
 }
 static inline int find_next_zero_bit_le(const void *p, int size, int offset)
 {
 	return _find_next_zero_bit_le(p, size, offset);
 }
 static inline int find_next_bit_le(const void *p, int size, int offset)
 {
 	return _find_next_bit_le(p, size, offset);
 }
 /*
  * Ext2 is defined to use little-endian byte ordering.
  */
 #define ext2_set_bit_atomic(lock, nr, p)	\
 		test_and_set_bit_le(nr, p)
 #define ext2_clear_bit_atomic(lock, nr, p)	\
 		test_and_clear_bit_le(nr, p)
-/*
- * Minix is defined to use little-endian byte ordering.
- * These do not need to be atomic.
- */
-#define minix_set_bit __set_bit_le
-#define minix_test_bit test_bit_le
-#define minix_test_and_set_bit __test_and_set_bit_le
-#define minix_test_and_clear_bit __test_and_clear_bit_le
-#define minix_find_first_zero_bit find_first_zero_bit_le
 #endif /* __KERNEL__ */
 #endif /* _ARM_BITOPS_H */

arch/avr32/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * Copyright (C) 2004-2006 Atmel Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 #ifndef __ASM_AVR32_BITOPS_H
 #define __ASM_AVR32_BITOPS_H
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm/byteorder.h>
 #include <asm/system.h>
 /*
  * clear_bit() doesn't provide any barrier for the compiler
  */
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  *
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static inline void set_bit(int nr, volatile void * addr)
 {
 	unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
 	unsigned long tmp;
 	if (__builtin_constant_p(nr)) {
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %2\n"
 			"	sbr	%0, %3\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p)
 			: "m"(*p), "i"(nr)
 			: "cc");
 	} else {
 		unsigned long mask = 1UL << (nr % BITS_PER_LONG);
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %2\n"
 			"	or	%0, %3\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p)
 			: "m"(*p), "r"(mask)
 			: "cc");
 	}
 }
 /*
  * clear_bit - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and may not be reordered.  However, it does
  * not contain a memory barrier, so if it is used for locking purposes,
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
 static inline void clear_bit(int nr, volatile void * addr)
 {
 	unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
 	unsigned long tmp;
 	if (__builtin_constant_p(nr)) {
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %2\n"
 			"	cbr	%0, %3\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p)
 			: "m"(*p), "i"(nr)
 			: "cc");
 	} else {
 		unsigned long mask = 1UL << (nr % BITS_PER_LONG);
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %2\n"
 			"	andn	%0, %3\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p)
 			: "m"(*p), "r"(mask)
 			: "cc");
 	}
 }
 /*
  * change_bit - Toggle a bit in memory
  * @nr: Bit to change
  * @addr: Address to start counting from
  *
  * change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static inline void change_bit(int nr, volatile void * addr)
 {
 	unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
 	unsigned long mask = 1UL << (nr % BITS_PER_LONG);
 	unsigned long tmp;
 	asm volatile(
 		"1:	ssrf	5\n"
 		"	ld.w	%0, %2\n"
 		"	eor	%0, %3\n"
 		"	stcond	%1, %0\n"
 		"	brne	1b"
 		: "=&r"(tmp), "=o"(*p)
 		: "m"(*p), "r"(mask)
 		: "cc");
 }
 /*
  * test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_set_bit(int nr, volatile void * addr)
 {
 	unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
 	unsigned long mask = 1UL << (nr % BITS_PER_LONG);
 	unsigned long tmp, old;
 	if (__builtin_constant_p(nr)) {
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %3\n"
 			"	mov	%2, %0\n"
 			"	sbr	%0, %4\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p), "=&r"(old)
 			: "m"(*p), "i"(nr)
 			: "memory", "cc");
 	} else {
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%2, %3\n"
 			"	or	%0, %2, %4\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p), "=&r"(old)
 			: "m"(*p), "r"(mask)
 			: "memory", "cc");
 	}
 	return (old & mask) != 0;
 }
 /*
  * test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_clear_bit(int nr, volatile void * addr)
 {
 	unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
 	unsigned long mask = 1UL << (nr % BITS_PER_LONG);
 	unsigned long tmp, old;
 	if (__builtin_constant_p(nr)) {
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %3\n"
 			"	mov	%2, %0\n"
 			"	cbr	%0, %4\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p), "=&r"(old)
 			: "m"(*p), "i"(nr)
 			: "memory", "cc");
 	} else {
 		asm volatile(
 			"1:	ssrf	5\n"
 			"	ld.w	%0, %3\n"
 			"	mov	%2, %0\n"
 			"	andn	%0, %4\n"
 			"	stcond	%1, %0\n"
 			"	brne	1b"
 			: "=&r"(tmp), "=o"(*p), "=&r"(old)
 			: "m"(*p), "r"(mask)
 			: "memory", "cc");
 	}
 	return (old & mask) != 0;
 }
 /*
  * test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_change_bit(int nr, volatile void * addr)
 {
 	unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
 	unsigned long mask = 1UL << (nr % BITS_PER_LONG);
 	unsigned long tmp, old;
 	asm volatile(
 		"1:	ssrf	5\n"
 		"	ld.w	%2, %3\n"
 		"	eor	%0, %2, %4\n"
 		"	stcond	%1, %0\n"
 		"	brne	1b"
 		: "=&r"(tmp), "=o"(*p), "=&r"(old)
 		: "m"(*p), "r"(mask)
 		: "memory", "cc");
 	return (old & mask) != 0;
 }
 #include <asm-generic/bitops/non-atomic.h>
 /* Find First bit Set */
 static inline unsigned long __ffs(unsigned long word)
 {
 	unsigned long result;
 	asm("brev %1\n\t"
 	    "clz %0,%1"
 	    : "=r"(result), "=&r"(word)
 	    : "1"(word));
 	return result;
 }
 /* Find First Zero */
 static inline unsigned long ffz(unsigned long word)
 {
 	return __ffs(~word);
 }
 /* Find Last bit Set */
 static inline int fls(unsigned long word)
 {
 	unsigned long result;
 	asm("clz %0,%1" : "=r"(result) : "r"(word));
 	return 32 - result;
 }
 static inline int __fls(unsigned long word)
 {
 	return fls(word) - 1;
 }
 unsigned long find_first_zero_bit(const unsigned long *addr,
 				  unsigned long size);
 unsigned long find_next_zero_bit(const unsigned long *addr,
 				 unsigned long size,
 				 unsigned long offset);
 unsigned long find_first_bit(const unsigned long *addr,
 			     unsigned long size);
 unsigned long find_next_bit(const unsigned long *addr,
 				 unsigned long size,
 				 unsigned long offset);
 /*
  * ffs: find first bit set. This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  *
  * The difference is that bit numbering starts at 1, and if no bit is set,
  * the function returns 0.
  */
 static inline int ffs(unsigned long word)
 {
 	if(word == 0)
 		return 0;
 	return __ffs(word) + 1;
 }
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix-le.h>
 #endif /* __ASM_AVR32_BITOPS_H */

arch/blackfin/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * Copyright 2004-2009 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
 #ifndef _BLACKFIN_BITOPS_H
 #define _BLACKFIN_BITOPS_H
 #include <linux/compiler.h>
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/find.h>
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/const_hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #ifndef CONFIG_SMP
 #include <linux/irqflags.h>
 /*
  * clear_bit may not imply a memory barrier
  */
 #ifndef smp_mb__before_clear_bit
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
 #endif
 #include <asm-generic/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 #else
 #include <asm/byteorder.h>	/* swab32 */
 #include <linux/linkage.h>
 asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
 asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
 asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
 asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
 asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
 asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
 asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
 static inline void set_bit(int nr, volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr + (nr >> 5);
 	__raw_bit_set_asm(a, nr & 0x1f);
 }
 static inline void clear_bit(int nr, volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr + (nr >> 5);
 	__raw_bit_clear_asm(a, nr & 0x1f);
 }
 static inline void change_bit(int nr, volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr + (nr >> 5);
 	__raw_bit_toggle_asm(a, nr & 0x1f);
 }
 static inline int test_bit(int nr, const volatile unsigned long *addr)
 {
 	volatile const unsigned long *a = addr + (nr >> 5);
 	return __raw_bit_test_asm(a, nr & 0x1f) != 0;
 }
 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr + (nr >> 5);
 	return __raw_bit_test_set_asm(a, nr & 0x1f);
 }
 static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr + (nr >> 5);
 	return __raw_bit_test_clear_asm(a, nr & 0x1f);
 }
 static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr + (nr >> 5);
 	return __raw_bit_test_toggle_asm(a, nr & 0x1f);
 }
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 #define test_bit __skip_test_bit
 #include <asm-generic/bitops/non-atomic.h>
 #undef test_bit
 #endif /* CONFIG_SMP */
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
 static inline unsigned int __arch_hweight32(unsigned int w)
 {
 	unsigned int res;
 	__asm__ ("%0.l = ONES %1;"
 		"%0 = %0.l (Z);"
 		: "=d" (res) : "d" (w));
 	return res;
 }
 static inline unsigned int __arch_hweight64(__u64 w)
 {
 	return __arch_hweight32((unsigned int)(w >> 32)) +
 	       __arch_hweight32((unsigned int)w);
 }
 static inline unsigned int __arch_hweight16(unsigned int w)
 {
 	return __arch_hweight32(w & 0xffff);
 }
 static inline unsigned int __arch_hweight8(unsigned int w)
 {
 	return __arch_hweight32(w & 0xff);
 }
 #endif				/* _BLACKFIN_BITOPS_H */

arch/cris/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /* asm/bitops.h for Linux/CRIS
  *
  * TODO: asm versions if speed is needed
  *
  * All bit operations return 0 if the bit was cleared before the
  * operation and != 0 if it was not.
  *
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 #ifndef _CRIS_BITOPS_H
 #define _CRIS_BITOPS_H
 /* Currently this is unsuitable for consumption outside the kernel.  */
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <arch/bitops.h>
 #include <asm/system.h>
 #include <asm/atomic.h>
 #include <linux/compiler.h>
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 #define set_bit(nr, addr)    (void)test_and_set_bit(nr, addr)
 /*
  * clear_bit - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and may not be reordered.  However, it does
  * not contain a memory barrier, so if it is used for locking purposes,
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
 #define clear_bit(nr, addr)  (void)test_and_clear_bit(nr, addr)
 /*
  * change_bit - Toggle a bit in memory
  * @nr: Bit to change
  * @addr: Address to start counting from
  *
  * change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 #define change_bit(nr, addr) (void)test_and_change_bit(nr, addr)
 /**
  * test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned long flags;
 	unsigned int *adr = (unsigned int *)addr;
 	adr += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	cris_atomic_save(addr, flags);
 	retval = (mask & *adr) != 0;
 	*adr |= mask;
 	cris_atomic_restore(addr, flags);
 	return retval;
 }
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()      barrier()
 #define smp_mb__after_clear_bit()       barrier()
 /**
  * test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned long flags;
 	unsigned int *adr = (unsigned int *)addr;
 	adr += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	cris_atomic_save(addr, flags);
 	retval = (mask & *adr) != 0;
 	*adr &= ~mask;
 	cris_atomic_restore(addr, flags);
 	return retval;
 }
 /**
  * test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 {
 	unsigned int mask, retval;
 	unsigned long flags;
 	unsigned int *adr = (unsigned int *)addr;
 	adr += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	cris_atomic_save(addr, flags);
 	retval = (mask & *adr) != 0;
 	*adr ^= mask;
 	cris_atomic_restore(addr, flags);
 	return retval;
 }
 #include <asm-generic/bitops/non-atomic.h>
 /*
  * Since we define it "external", it collides with the built-in
  * definition, which doesn't have the same semantics.  We don't want to
  * use -fno-builtin, so just hide the name ffs.
  */
 #define ffs kernel_ffs
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/le.h>
 #define ext2_set_bit_atomic(l,n,a)   test_and_set_bit(n,a)
 #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
-#include <asm-generic/bitops/minix.h>
 #include <asm-generic/bitops/sched.h>
 #endif /* __KERNEL__ */
 #endif /* _CRIS_BITOPS_H */

arch/frv/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /* bitops.h: bit operations for the Fujitsu FR-V CPUs
  *
  * For an explanation of how atomic ops work in this arch, see:
  *   Documentation/frv/atomic-ops.txt
  *
  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
 #ifndef _ASM_BITOPS_H
 #define _ASM_BITOPS_H
 #include <linux/compiler.h>
 #include <asm/byteorder.h>
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm-generic/bitops/ffz.h>
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
 static inline
 unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
 {
 	unsigned long old, tmp;
 	asm volatile(
 		"0:						\n"
 		"	orcc		gr0,gr0,gr0,icc3	\n"	/* set ICC3.Z */
 		"	ckeq		icc3,cc7		\n"
 		"	ld.p		%M0,%1			\n"	/* LD.P/ORCR are atomic */
 		"	orcr		cc7,cc7,cc3		\n"	/* set CC3 to true */
 		"	and%I3		%1,%3,%2		\n"
 		"	cst.p		%2,%M0		,cc3,#1	\n"	/* if store happens... */
 		"	corcc		gr29,gr29,gr0	,cc3,#1	\n"	/* ... clear ICC3.Z */
 		"	beq		icc3,#0,0b		\n"
 		: "+U"(*v), "=&r"(old), "=r"(tmp)
 		: "NPr"(~mask)
 		: "memory", "cc7", "cc3", "icc3"
 		);
 	return old;
 }
 static inline
 unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
 {
 	unsigned long old, tmp;
 	asm volatile(
 		"0:						\n"
 		"	orcc		gr0,gr0,gr0,icc3	\n"	/* set ICC3.Z */
 		"	ckeq		icc3,cc7		\n"
 		"	ld.p		%M0,%1			\n"	/* LD.P/ORCR are atomic */
 		"	orcr		cc7,cc7,cc3		\n"	/* set CC3 to true */
 		"	or%I3		%1,%3,%2		\n"
 		"	cst.p		%2,%M0		,cc3,#1	\n"	/* if store happens... */
 		"	corcc		gr29,gr29,gr0	,cc3,#1	\n"	/* ... clear ICC3.Z */
 		"	beq		icc3,#0,0b		\n"
 		: "+U"(*v), "=&r"(old), "=r"(tmp)
 		: "NPr"(mask)
 		: "memory", "cc7", "cc3", "icc3"
 		);
 	return old;
 }
 static inline
 unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
 {
 	unsigned long old, tmp;
 	asm volatile(
 		"0:						\n"
 		"	orcc		gr0,gr0,gr0,icc3	\n"	/* set ICC3.Z */
 		"	ckeq		icc3,cc7		\n"
 		"	ld.p		%M0,%1			\n"	/* LD.P/ORCR are atomic */
 		"	orcr		cc7,cc7,cc3		\n"	/* set CC3 to true */
 		"	xor%I3		%1,%3,%2		\n"
 		"	cst.p		%2,%M0		,cc3,#1	\n"	/* if store happens... */
 		"	corcc		gr29,gr29,gr0	,cc3,#1	\n"	/* ... clear ICC3.Z */
 		"	beq		icc3,#0,0b		\n"
 		: "+U"(*v), "=&r"(old), "=r"(tmp)
 		: "NPr"(mask)
 		: "memory", "cc7", "cc3", "icc3"
 		);
 	return old;
 }
 #else
 extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
 extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
 extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
 #endif
 #define atomic_clear_mask(mask, v)	atomic_test_and_ANDNOT_mask((mask), (v))
 #define atomic_set_mask(mask, v)	atomic_test_and_OR_mask((mask), (v))
 static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *ptr = addr;
 	unsigned long mask = 1UL << (nr & 31);
 	ptr += nr >> 5;
 	return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
 }
 static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *ptr = addr;
 	unsigned long mask = 1UL << (nr & 31);
 	ptr += nr >> 5;
 	return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
 }
 static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *ptr = addr;
 	unsigned long mask = 1UL << (nr & 31);
 	ptr += nr >> 5;
 	return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
 }
 static inline void clear_bit(unsigned long nr, volatile void *addr)
 {
 	test_and_clear_bit(nr, addr);
 }
 static inline void set_bit(unsigned long nr, volatile void *addr)
 {
 	test_and_set_bit(nr, addr);
 }
 static inline void change_bit(unsigned long nr, volatile void *addr)
 {
 	test_and_change_bit(nr, addr);
 }
 static inline void __clear_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *a = addr;
 	int mask;
 	a += nr >> 5;
 	mask = 1 << (nr & 31);
 	*a &= ~mask;
 }
 static inline void __set_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *a = addr;
 	int mask;
 	a += nr >> 5;
 	mask = 1 << (nr & 31);
 	*a |= mask;
 }
 static inline void __change_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *a = addr;
 	int mask;
 	a += nr >> 5;
 	mask = 1 << (nr & 31);
 	*a ^= mask;
 }
 static inline int __test_and_clear_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *a = addr;
 	int mask, retval;
 	a += nr >> 5;
 	mask = 1 << (nr & 31);
 	retval = (mask & *a) != 0;
 	*a &= ~mask;
 	return retval;
 }
 static inline int __test_and_set_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *a = addr;
 	int mask, retval;
 	a += nr >> 5;
 	mask = 1 << (nr & 31);
 	retval = (mask & *a) != 0;
 	*a |= mask;
 	return retval;
 }
 static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
 {
 	volatile unsigned long *a = addr;
 	int mask, retval;
 	a += nr >> 5;
 	mask = 1 << (nr & 31);
 	retval = (mask & *a) != 0;
 	*a ^= mask;
 	return retval;
 }
 /*
  * This routine doesn't need to be atomic.
  */
 static inline int
 __constant_test_bit(unsigned long nr, const volatile void *addr)
 {
 	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
 }
 static inline int __test_bit(unsigned long nr, const volatile void *addr)
 {
 	int 	* a = (int *) addr;
 	int	mask;
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	return ((mask & *a) != 0);
 }
 #define test_bit(nr,addr) \
 (__builtin_constant_p(nr) ? \
  __constant_test_bit((nr),(addr)) : \
  __test_bit((nr),(addr)))
 #include <asm-generic/bitops/find.h>
 /**
  * fls - find last bit set
  * @x: the word to search
  *
  * This is defined the same way as ffs:
  * - return 32..1 to indicate bit 31..0 most significant bit set
  * - return 0 to indicate no bits set
  */
 #define fls(x)						\
 ({							\
 	int bit;					\
 							\
 	asm("	subcc	%1,gr0,gr0,icc0		\n"	\
 	    "	ckne	icc0,cc4		\n"	\
 	    "	cscan.p	%1,gr0,%0	,cc4,#1	\n"	\
 	    "	csub	%0,%0,%0	,cc4,#0	\n"	\
 	    "   csub    %2,%0,%0	,cc4,#1	\n"	\
 	    : "=&r"(bit)				\
 	    : "r"(x), "r"(32)				\
 	    : "icc0", "cc4"				\
 	    );						\
 							\
 	bit;						\
 })
 /**
  * fls64 - find last bit set in a 64-bit value
  * @n: the value to search
  *
  * This is defined the same way as ffs:
  * - return 64..1 to indicate bit 63..0 most significant bit set
  * - return 0 to indicate no bits set
  */
 static inline __attribute__((const))
 int fls64(u64 n)
 {
 	union {
 		u64 ll;
 		struct { u32 h, l; };
 	} _;
 	int bit, x, y;
 	_.ll = n;
 	asm("	subcc.p		%3,gr0,gr0,icc0		\n"
 	    "	subcc		%4,gr0,gr0,icc1		\n"
 	    "	ckne		icc0,cc4		\n"
 	    "	ckne		icc1,cc5		\n"
 	    "	norcr		cc4,cc5,cc6		\n"
 	    "	csub.p		%0,%0,%0	,cc6,1	\n"
 	    "	orcr		cc5,cc4,cc4		\n"
 	    "	andcr		cc4,cc5,cc4		\n"
 	    "	cscan.p		%3,gr0,%0	,cc4,0	\n"
 	    "   setlos		#64,%1			\n"
 	    "	cscan.p		%4,gr0,%0	,cc4,1	\n"
 	    "   setlos		#32,%2			\n"
 	    "	csub.p		%1,%0,%0	,cc4,0	\n"
 	    "	csub		%2,%0,%0	,cc4,1	\n"
 	    : "=&r"(bit), "=r"(x), "=r"(y)
 	    : "0r"(_.h), "r"(_.l)
 	    : "icc0", "icc1", "cc4", "cc5", "cc6"
 	    );
 	return bit;
 }
 /**
  * ffs - find first bit set
  * @x: the word to search
  *
  * - return 32..1 to indicate bit 31..0 most least significant bit set
  * - return 0 to indicate no bits set
  */
 static inline __attribute__((const))
 int ffs(int x)
 {
 	/* Note: (x & -x) gives us a mask that is the least significant
 	 * (rightmost) 1-bit of the value in x.
 	 */
 	return fls(x & -x);
 }
 /**
  * __ffs - find first bit set
  * @x: the word to search
  *
  * - return 31..0 to indicate bit 31..0 most least significant bit set
  * - if no bits are set in x, the result is undefined
  */
 static inline __attribute__((const))
 int __ffs(unsigned long x)
 {
 	int bit;
 	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
 	return 31 - bit;
 }
 /**
  * __fls - find last (most-significant) set bit in a long word
  * @word: the word to search
  *
  * Undefined if no set bit exists, so code should check against 0 first.
  */
 static inline unsigned long __fls(unsigned long word)
 {
 	unsigned long bit;
 	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word));
 	return bit;
 }
 /*
  * special slimline version of fls() for calculating ilog2_u32()
  * - note: no protection against n == 0
  */
 #define ARCH_HAS_ILOG2_U32
 static inline __attribute__((const))
 int __ilog2_u32(u32 n)
 {
 	int bit;
 	asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
 	return 31 - bit;
 }
 /*
  * special slimline version of fls64() for calculating ilog2_u64()
  * - note: no protection against n == 0
  */
 #define ARCH_HAS_ILOG2_U64
 static inline __attribute__((const))
 int __ilog2_u64(u64 n)
 {
 	union {
 		u64 ll;
 		struct { u32 h, l; };
 	} _;
 	int bit, x, y;
 	_.ll = n;
 	asm("	subcc		%3,gr0,gr0,icc0		\n"
 	    "	ckeq		icc0,cc4		\n"
 	    "	cscan.p		%3,gr0,%0	,cc4,0	\n"
 	    "   setlos		#63,%1			\n"
 	    "	cscan.p		%4,gr0,%0	,cc4,1	\n"
 	    "   setlos		#31,%2			\n"
 	    "	csub.p		%1,%0,%0	,cc4,0	\n"
 	    "	csub		%2,%0,%0	,cc4,1	\n"
 	    : "=&r"(bit), "=r"(x), "=r"(y)
 	    : "0r"(_.h), "r"(_.l)
 	    : "icc0", "cc4"
 	    );
 	return bit;
 }
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/le.h>
 #define ext2_set_bit_atomic(lock,nr,addr)	test_and_set_bit  ((nr) ^ 0x18, (addr))
 #define ext2_clear_bit_atomic(lock,nr,addr)	test_and_clear_bit((nr) ^ 0x18, (addr))
-#include <asm-generic/bitops/minix-le.h>
 #endif /* __KERNEL__ */
 #endif /* _ASM_BITOPS_H */

arch/h8300/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _H8300_BITOPS_H
 #define _H8300_BITOPS_H
 /*
  * Copyright 1992, Linus Torvalds.
  * Copyright 2002, Yoshinori Sato
  */
 #include <linux/compiler.h>
 #include <asm/system.h>
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 /*
  * Function prototypes to keep gcc -Wall happy
  */
 /*
  * ffz = Find First Zero in word. Undefined if no zero exists,
  * so code should check against ~0UL first..
  */
 static __inline__ unsigned long ffz(unsigned long word)
 {
 	unsigned long result;
 	result = -1;
 	__asm__("1:\n\t"
 		"shlr.l %2\n\t"
 		"adds #1,%0\n\t"
 		"bcs 1b"
 		: "=r" (result)
 		: "0"  (result),"r" (word));
 	return result;
 }
 #define H8300_GEN_BITOP_CONST(OP,BIT)			    \
 	case BIT:					    \
 	__asm__(OP " #" #BIT ",@%0"::"r"(b_addr):"memory"); \
 	break;
 #define H8300_GEN_BITOP(FNAME,OP)				      \
 static __inline__ void FNAME(int nr, volatile unsigned long* addr)    \
 {								      \
 	volatile unsigned char *b_addr;				      \
 	b_addr = (volatile unsigned char *)addr + ((nr >> 3) ^ 3);    \
 	if (__builtin_constant_p(nr)) {				      \
 		switch(nr & 7) {				      \
 			H8300_GEN_BITOP_CONST(OP,0)		      \
 			H8300_GEN_BITOP_CONST(OP,1)		      \
 			H8300_GEN_BITOP_CONST(OP,2)		      \
 			H8300_GEN_BITOP_CONST(OP,3)		      \
 			H8300_GEN_BITOP_CONST(OP,4)		      \
 			H8300_GEN_BITOP_CONST(OP,5)		      \
 			H8300_GEN_BITOP_CONST(OP,6)		      \
 			H8300_GEN_BITOP_CONST(OP,7)		      \
 		}						      \
 	} else {						      \
 		__asm__(OP " %w0,@%1"::"r"(nr),"r"(b_addr):"memory"); \
 	}							      \
 }
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 H8300_GEN_BITOP(set_bit	  ,"bset")
 H8300_GEN_BITOP(clear_bit ,"bclr")
 H8300_GEN_BITOP(change_bit,"bnot")
 #define __set_bit(nr,addr)    set_bit((nr),(addr))
 #define __clear_bit(nr,addr)  clear_bit((nr),(addr))
 #define __change_bit(nr,addr) change_bit((nr),(addr))
 #undef H8300_GEN_BITOP
 #undef H8300_GEN_BITOP_CONST
 static __inline__ int test_bit(int nr, const unsigned long* addr)
 {
 	return (*((volatile unsigned char *)addr +
                ((nr >> 3) ^ 3)) & (1UL << (nr & 7))) != 0;
 }
 #define __test_bit(nr, addr) test_bit(nr, addr)
 #define H8300_GEN_TEST_BITOP_CONST_INT(OP,BIT)			     \
 	case BIT:						     \
 	__asm__("stc ccr,%w1\n\t"				     \
 		"orc #0x80,ccr\n\t"				     \
 		"bld #" #BIT ",@%4\n\t"				     \
 		OP " #" #BIT ",@%4\n\t"				     \
 		"rotxl.l %0\n\t"				     \
 		"ldc %w1,ccr"					     \
 		: "=r"(retval),"=&r"(ccrsave),"=m"(*b_addr)	     \
 		: "0" (retval),"r" (b_addr)			     \
 		: "memory");                                         \
         break;
 #define H8300_GEN_TEST_BITOP_CONST(OP,BIT)			     \
 	case BIT:						     \
 	__asm__("bld #" #BIT ",@%3\n\t"				     \
 		OP " #" #BIT ",@%3\n\t"				     \
 		"rotxl.l %0\n\t"				     \
 		: "=r"(retval),"=m"(*b_addr)			     \
 		: "0" (retval),"r" (b_addr)			     \
 		: "memory");                                         \
         break;
 #define H8300_GEN_TEST_BITOP(FNNAME,OP)				     \
 static __inline__ int FNNAME(int nr, volatile void * addr)	     \
 {								     \
 	int retval = 0;						     \
 	char ccrsave;						     \
 	volatile unsigned char *b_addr;				     \
 	b_addr = (volatile unsigned char *)addr + ((nr >> 3) ^ 3);   \
 	if (__builtin_constant_p(nr)) {				     \
 		switch(nr & 7) {				     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,0)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,1)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,2)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,3)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,4)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,5)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,6)	     \
 			H8300_GEN_TEST_BITOP_CONST_INT(OP,7)	     \
 		}						     \
 	} else {						     \
 		__asm__("stc ccr,%w1\n\t"			     \
 			"orc #0x80,ccr\n\t"			     \
 			"btst %w5,@%4\n\t"			     \
 			OP " %w5,@%4\n\t"			     \
 			"beq 1f\n\t"				     \
 			"inc.l #1,%0\n"				     \
 			"1:\n\t"				     \
 			"ldc %w1,ccr"				     \
 			: "=r"(retval),"=&r"(ccrsave),"=m"(*b_addr)  \
 			: "0" (retval),"r" (b_addr),"r"(nr)	     \
 			: "memory");				     \
 	}							     \
 	return retval;						     \
 }								     \
 								     \
 static __inline__ int __ ## FNNAME(int nr, volatile void * addr)     \
 {								     \
 	int retval = 0;						     \
 	volatile unsigned char *b_addr;				     \
 	b_addr = (volatile unsigned char *)addr + ((nr >> 3) ^ 3);   \
 	if (__builtin_constant_p(nr)) {				     \
 		switch(nr & 7) {				     \
 			H8300_GEN_TEST_BITOP_CONST(OP,0) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,1) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,2) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,3) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,4) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,5) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,6) 	     \
 			H8300_GEN_TEST_BITOP_CONST(OP,7) 	     \
 		}						     \
 	} else {						     \
 		__asm__("btst %w4,@%3\n\t"			     \
 			OP " %w4,@%3\n\t"			     \
 			"beq 1f\n\t"				     \
 			"inc.l #1,%0\n"				     \
 			"1:"					     \
 			: "=r"(retval),"=m"(*b_addr)		     \
 			: "0" (retval),"r" (b_addr),"r"(nr)	     \
 			: "memory");				     \
 	}							     \
 	return retval;						     \
 }
 H8300_GEN_TEST_BITOP(test_and_set_bit,	 "bset")
 H8300_GEN_TEST_BITOP(test_and_clear_bit, "bclr")
 H8300_GEN_TEST_BITOP(test_and_change_bit,"bnot")
 #undef H8300_GEN_TEST_BITOP_CONST
 #undef H8300_GEN_TEST_BITOP_CONST_INT
 #undef H8300_GEN_TEST_BITOP
 #include <asm-generic/bitops/ffs.h>
 static __inline__ unsigned long __ffs(unsigned long word)
 {
 	unsigned long result;
 	result = -1;
 	__asm__("1:\n\t"
 		"shlr.l %2\n\t"
 		"adds #1,%0\n\t"
 		"bcc 1b"
 		: "=r" (result)
 		: "0"(result),"r"(word));
 	return result;
 }
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #endif /* _H8300_BITOPS_H */

arch/ia64/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _ASM_IA64_BITOPS_H
 #define _ASM_IA64_BITOPS_H
 /*
  * Copyright (C) 1998-2003 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
  * O(1) scheduler patch
  */
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <asm/intrinsics.h>
 /**
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  *
  * The address must be (at least) "long" aligned.
  * Note that there are driver (e.g., eepro100) which use these operations to
  * operate on hw-defined data-structures, so we can't easily change these
  * operations to force a bigger alignment.
  *
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 static __inline__ void
 set_bit (int nr, volatile void *addr)
 {
 	__u32 bit, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	bit = 1 << (nr & 31);
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old | bit;
 	} while (cmpxchg_acq(m, old, new) != old);
 }
 /**
  * __set_bit - Set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * Unlike set_bit(), this function is non-atomic and may be reordered.
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
 static __inline__ void
 __set_bit (int nr, volatile void *addr)
 {
 	*((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
 }
 /*
  * clear_bit() has "acquire" semantics.
  */
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	do { /* skip */; } while (0)
 /**
  * clear_bit - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and may not be reordered.  However, it does
  * not contain a memory barrier, so if it is used for locking purposes,
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
 static __inline__ void
 clear_bit (int nr, volatile void *addr)
 {
 	__u32 mask, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	mask = ~(1 << (nr & 31));
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old & mask;
 	} while (cmpxchg_acq(m, old, new) != old);
 }
 /**
  * clear_bit_unlock - Clears a bit in memory with release
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit_unlock() is atomic and may not be reordered.  It does
  * contain a memory barrier suitable for unlock type operations.
  */
 static __inline__ void
 clear_bit_unlock (int nr, volatile void *addr)
 {
 	__u32 mask, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	mask = ~(1 << (nr & 31));
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old & mask;
 	} while (cmpxchg_rel(m, old, new) != old);
 }
 /**
  * __clear_bit_unlock - Non-atomically clears a bit in memory with release
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * Similarly to clear_bit_unlock, the implementation uses a store
  * with release semantics. See also arch_spin_unlock().
  */
 static __inline__ void
 __clear_bit_unlock(int nr, void *addr)
 {
 	__u32 * const m = (__u32 *) addr + (nr >> 5);
 	__u32 const new = *m & ~(1 << (nr & 31));
 	ia64_st4_rel_nta(m, new);
 }
 /**
  * __clear_bit - Clears a bit in memory (non-atomic version)
  * @nr: the bit to clear
  * @addr: the address to start counting from
  *
  * Unlike clear_bit(), this function is non-atomic and may be reordered.
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
 static __inline__ void
 __clear_bit (int nr, volatile void *addr)
 {
 	*((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31));
 }
 /**
  * change_bit - Toggle a bit in memory
  * @nr: Bit to toggle
  * @addr: Address to start counting from
  *
  * change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static __inline__ void
 change_bit (int nr, volatile void *addr)
 {
 	__u32 bit, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	bit = (1 << (nr & 31));
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old ^ bit;
 	} while (cmpxchg_acq(m, old, new) != old);
 }
 /**
  * __change_bit - Toggle a bit in memory
  * @nr: the bit to toggle
  * @addr: the address to start counting from
  *
  * Unlike change_bit(), this function is non-atomic and may be reordered.
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
 static __inline__ void
 __change_bit (int nr, volatile void *addr)
 {
 	*((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
 }
 /**
  * test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies the acquisition side of the memory barrier.
  */
 static __inline__ int
 test_and_set_bit (int nr, volatile void *addr)
 {
 	__u32 bit, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	bit = 1 << (nr & 31);
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old | bit;
 	} while (cmpxchg_acq(m, old, new) != old);
 	return (old & bit) != 0;
 }
 /**
  * test_and_set_bit_lock - Set a bit and return its old value for lock
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This is the same as test_and_set_bit on ia64
  */
 #define test_and_set_bit_lock test_and_set_bit
 /**
  * __test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
 static __inline__ int
 __test_and_set_bit (int nr, volatile void *addr)
 {
 	__u32 *p = (__u32 *) addr + (nr >> 5);
 	__u32 m = 1 << (nr & 31);
 	int oldbitset = (*p & m) != 0;
 	*p |= m;
 	return oldbitset;
 }
 /**
  * test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies the acquisition side of the memory barrier.
  */
 static __inline__ int
 test_and_clear_bit (int nr, volatile void *addr)
 {
 	__u32 mask, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	mask = ~(1 << (nr & 31));
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old & mask;
 	} while (cmpxchg_acq(m, old, new) != old);
 	return (old & ~mask) != 0;
 }
 /**
  * __test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
 static __inline__ int
 __test_and_clear_bit(int nr, volatile void * addr)
 {
 	__u32 *p = (__u32 *) addr + (nr >> 5);
 	__u32 m = 1 << (nr & 31);
 	int oldbitset = (*p & m) != 0;
 	*p &= ~m;
 	return oldbitset;
 }
 /**
  * test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies the acquisition side of the memory barrier.
  */
 static __inline__ int
 test_and_change_bit (int nr, volatile void *addr)
 {
 	__u32 bit, old, new;
 	volatile __u32 *m;
 	CMPXCHG_BUGCHECK_DECL
 	m = (volatile __u32 *) addr + (nr >> 5);
 	bit = (1 << (nr & 31));
 	do {
 		CMPXCHG_BUGCHECK(m);
 		old = *m;
 		new = old ^ bit;
 	} while (cmpxchg_acq(m, old, new) != old);
 	return (old & bit) != 0;
 }
 /**
  * __test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
  * @addr: Address to count from
  *
  * This operation is non-atomic and can be reordered.
  */
 static __inline__ int
 __test_and_change_bit (int nr, void *addr)
 {
 	__u32 old, bit = (1 << (nr & 31));
 	__u32 *m = (__u32 *) addr + (nr >> 5);
 	old = *m;
 	*m = old ^ bit;
 	return (old & bit) != 0;
 }
 static __inline__ int
 test_bit (int nr, const volatile void *addr)
 {
 	return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
 }
 /**
  * ffz - find the first zero bit in a long word
  * @x: The long word to find the bit in
  *
  * Returns the bit-number (0..63) of the first (least significant) zero bit.
  * Undefined if no zero exists, so code should check against ~0UL first...
  */
 static inline unsigned long
 ffz (unsigned long x)
 {
 	unsigned long result;
 	result = ia64_popcnt(x & (~x - 1));
 	return result;
 }
 /**
  * __ffs - find first bit in word.
  * @x: The word to search
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
 static __inline__ unsigned long
 __ffs (unsigned long x)
 {
 	unsigned long result;
 	result = ia64_popcnt((x-1) & ~x);
 	return result;
 }
 #ifdef __KERNEL__
 /*
  * Return bit number of last (most-significant) bit set.  Undefined
  * for x==0.  Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
  */
 static inline unsigned long
 ia64_fls (unsigned long x)
 {
 	long double d = x;
 	long exp;
 	exp = ia64_getf_exp(d);
 	return exp - 0xffff;
 }
 /*
  * Find the last (most significant) bit set.  Returns 0 for x==0 and
  * bits are numbered from 1..32 (e.g., fls(9) == 4).
  */
 static inline int
 fls (int t)
 {
 	unsigned long x = t & 0xffffffffu;
 	if (!x)
 		return 0;
 	x |= x >> 1;
 	x |= x >> 2;
 	x |= x >> 4;
 	x |= x >> 8;
 	x |= x >> 16;
 	return ia64_popcnt(x);
 }
 /*
  * Find the last (most significant) bit set.  Undefined for x==0.
  * Bits are numbered from 0..63 (e.g., __fls(9) == 3).
  */
 static inline unsigned long
 __fls (unsigned long x)
 {
 	x |= x >> 1;
 	x |= x >> 2;
 	x |= x >> 4;
 	x |= x >> 8;
 	x |= x >> 16;
 	x |= x >> 32;
 	return ia64_popcnt(x) - 1;
 }
 #include <asm-generic/bitops/fls64.h>
 /*
  * ffs: find first bit set. This is defined the same way as the libc and
  * compiler builtin ffs routines, therefore differs in spirit from the above
  * ffz (man ffs): it operates on "int" values only and the result value is the
  * bit number + 1.  ffs(0) is defined to return zero.
  */
 #define ffs(x)	__builtin_ffs(x)
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
 static __inline__ unsigned long __arch_hweight64(unsigned long x)
 {
 	unsigned long result;
 	result = ia64_popcnt(x);
 	return result;
 }
 #define __arch_hweight32(x) ((unsigned int) __arch_hweight64((x) & 0xfffffffful))
 #define __arch_hweight16(x) ((unsigned int) __arch_hweight64((x) & 0xfffful))
 #define __arch_hweight8(x)  ((unsigned int) __arch_hweight64((x) & 0xfful))
 #include <asm-generic/bitops/const_hweight.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/find.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/le.h>
 #define ext2_set_bit_atomic(l,n,a)	test_and_set_bit(n,a)
 #define ext2_clear_bit_atomic(l,n,a)	test_and_clear_bit(n,a)
-#include <asm-generic/bitops/minix.h>
 #include <asm-generic/bitops/sched.h>
 #endif /* __KERNEL__ */
 #endif /* _ASM_IA64_BITOPS_H */

arch/m32r/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _ASM_M32R_BITOPS_H
 #define _ASM_M32R_BITOPS_H
 /*
  *  linux/include/asm-m32r/bitops.h
  *
  *  Copyright 1992, Linus Torvalds.
  *
  *  M32R version:
  *    Copyright (C) 2001, 2002  Hitoshi Yamamoto
  *    Copyright (C) 2004  Hirokazu Takata <takata at linux-m32r.org>
  */
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <asm/assembler.h>
 #include <asm/system.h>
 #include <asm/byteorder.h>
 #include <asm/types.h>
 /*
  * These have to be done with inline assembly: that way the bit-setting
  * is guaranteed to be atomic. All bit operations return 0 if the bit
  * was cleared before the operation and != 0 if it was not.
  *
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 /**
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static __inline__ void set_bit(int nr, volatile void * addr)
 {
 	__u32 mask;
 	volatile __u32 *a = addr;
 	unsigned long flags;
 	unsigned long tmp;
 	a += (nr >> 5);
 	mask = (1 << (nr & 0x1F));
 	local_irq_save(flags);
 	__asm__ __volatile__ (
 		DCACHE_CLEAR("%0", "r6", "%1")
 		M32R_LOCK" %0, @%1;		\n\t"
 		"or	%0, %2;			\n\t"
 		M32R_UNLOCK" %0, @%1;		\n\t"
 		: "=&r" (tmp)
 		: "r" (a), "r" (mask)
 		: "memory"
 #ifdef CONFIG_CHIP_M32700_TS1
 		, "r6"
 #endif	/* CONFIG_CHIP_M32700_TS1 */
 	);
 	local_irq_restore(flags);
 }
 /**
  * clear_bit - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and may not be reordered.  However, it does
  * not contain a memory barrier, so if it is used for locking purposes,
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
 static __inline__ void clear_bit(int nr, volatile void * addr)
 {
 	__u32 mask;
 	volatile __u32 *a = addr;
 	unsigned long flags;
 	unsigned long tmp;
 	a += (nr >> 5);
 	mask = (1 << (nr & 0x1F));
 	local_irq_save(flags);
 	__asm__ __volatile__ (
 		DCACHE_CLEAR("%0", "r6", "%1")
 		M32R_LOCK" %0, @%1;		\n\t"
 		"and	%0, %2;			\n\t"
 		M32R_UNLOCK" %0, @%1;		\n\t"
 		: "=&r" (tmp)
 		: "r" (a), "r" (~mask)
 		: "memory"
 #ifdef CONFIG_CHIP_M32700_TS1
 		, "r6"
 #endif	/* CONFIG_CHIP_M32700_TS1 */
 	);
 	local_irq_restore(flags);
 }
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 /**
  * change_bit - Toggle a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static __inline__ void change_bit(int nr, volatile void * addr)
 {
 	__u32  mask;
 	volatile __u32  *a = addr;
 	unsigned long flags;
 	unsigned long tmp;
 	a += (nr >> 5);
 	mask = (1 << (nr & 0x1F));
 	local_irq_save(flags);
 	__asm__ __volatile__ (
 		DCACHE_CLEAR("%0", "r6", "%1")
 		M32R_LOCK" %0, @%1;		\n\t"
 		"xor	%0, %2;			\n\t"
 		M32R_UNLOCK" %0, @%1;		\n\t"
 		: "=&r" (tmp)
 		: "r" (a), "r" (mask)
 		: "memory"
 #ifdef CONFIG_CHIP_M32700_TS1
 		, "r6"
 #endif	/* CONFIG_CHIP_M32700_TS1 */
 	);
 	local_irq_restore(flags);
 }
 /**
  * test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static __inline__ int test_and_set_bit(int nr, volatile void * addr)
 {
 	__u32 mask, oldbit;
 	volatile __u32 *a = addr;
 	unsigned long flags;
 	unsigned long tmp;
 	a += (nr >> 5);
 	mask = (1 << (nr & 0x1F));
 	local_irq_save(flags);
 	__asm__ __volatile__ (
 		DCACHE_CLEAR("%0", "%1", "%2")
 		M32R_LOCK" %0, @%2;		\n\t"
 		"mv	%1, %0;			\n\t"
 		"and	%0, %3;			\n\t"
 		"or	%1, %3;			\n\t"
 		M32R_UNLOCK" %1, @%2;		\n\t"
 		: "=&r" (oldbit), "=&r" (tmp)
 		: "r" (a), "r" (mask)
 		: "memory"
 	);
 	local_irq_restore(flags);
 	return (oldbit != 0);
 }
 /**
  * test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
 {
 	__u32 mask, oldbit;
 	volatile __u32 *a = addr;
 	unsigned long flags;
 	unsigned long tmp;
 	a += (nr >> 5);
 	mask = (1 << (nr & 0x1F));
 	local_irq_save(flags);
 	__asm__ __volatile__ (
 		DCACHE_CLEAR("%0", "%1", "%3")
 		M32R_LOCK" %0, @%3;		\n\t"
 		"mv	%1, %0;			\n\t"
 		"and	%0, %2;			\n\t"
 		"not	%2, %2;			\n\t"
 		"and	%1, %2;			\n\t"
 		M32R_UNLOCK" %1, @%3;		\n\t"
 		: "=&r" (oldbit), "=&r" (tmp), "+r" (mask)
 		: "r" (a)
 		: "memory"
 	);
 	local_irq_restore(flags);
 	return (oldbit != 0);
 }
 /**
  * test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static __inline__ int test_and_change_bit(int nr, volatile void * addr)
 {
 	__u32 mask, oldbit;
 	volatile __u32 *a = addr;
 	unsigned long flags;
 	unsigned long tmp;
 	a += (nr >> 5);
 	mask = (1 << (nr & 0x1F));
 	local_irq_save(flags);
 	__asm__ __volatile__ (
 		DCACHE_CLEAR("%0", "%1", "%2")
 		M32R_LOCK" %0, @%2;		\n\t"
 		"mv	%1, %0;			\n\t"
 		"and	%0, %3;			\n\t"
 		"xor	%1, %3;			\n\t"
 		M32R_UNLOCK" %1, @%2;		\n\t"
 		: "=&r" (oldbit), "=&r" (tmp)
 		: "r" (a), "r" (mask)
 		: "memory"
 	);
 	local_irq_restore(flags);
 	return (oldbit != 0);
 }
 #include <asm-generic/bitops/non-atomic.h>
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #endif /* __KERNEL__ */
 #ifdef __KERNEL__
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* _ASM_M32R_BITOPS_H */

arch/m68k/include/asm/bitops_mm.h

Diff comments View file @ 61f2e7b

 #ifndef _M68K_BITOPS_H
 #define _M68K_BITOPS_H
 /*
  * Copyright 1992, Linus Torvalds.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file COPYING in the main directory of this archive
  * for more details.
  */
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 /*
  * Require 68020 or better.
  *
  * They use the standard big-endian m680x0 bit ordering.
  */
 #define test_and_set_bit(nr,vaddr) \
   (__builtin_constant_p(nr) ? \
    __constant_test_and_set_bit(nr, vaddr) : \
    __generic_test_and_set_bit(nr, vaddr))
 #define __test_and_set_bit(nr,vaddr) test_and_set_bit(nr,vaddr)
 static inline int __constant_test_and_set_bit(int nr, unsigned long *vaddr)
 {
 	char *p = (char *)vaddr + (nr ^ 31) / 8;
 	char retval;
 	__asm__ __volatile__ ("bset %2,%1; sne %0"
 			: "=d" (retval), "+m" (*p)
 			: "di" (nr & 7));
 	return retval;
 }
 static inline int __generic_test_and_set_bit(int nr, unsigned long *vaddr)
 {
 	char retval;
 	__asm__ __volatile__ ("bfset %2{%1:#1}; sne %0"
 			: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
 	return retval;
 }
 #define set_bit(nr,vaddr) \
   (__builtin_constant_p(nr) ? \
    __constant_set_bit(nr, vaddr) : \
    __generic_set_bit(nr, vaddr))
 #define __set_bit(nr,vaddr) set_bit(nr,vaddr)
 static inline void __constant_set_bit(int nr, volatile unsigned long *vaddr)
 {
 	char *p = (char *)vaddr + (nr ^ 31) / 8;
 	__asm__ __volatile__ ("bset %1,%0"
 			: "+m" (*p) : "di" (nr & 7));
 }
 static inline void __generic_set_bit(int nr, volatile unsigned long *vaddr)
 {
 	__asm__ __volatile__ ("bfset %1{%0:#1}"
 			: : "d" (nr^31), "o" (*vaddr) : "memory");
 }
 #define test_and_clear_bit(nr,vaddr) \
   (__builtin_constant_p(nr) ? \
    __constant_test_and_clear_bit(nr, vaddr) : \
    __generic_test_and_clear_bit(nr, vaddr))
 #define __test_and_clear_bit(nr,vaddr) test_and_clear_bit(nr,vaddr)
 static inline int __constant_test_and_clear_bit(int nr, unsigned long *vaddr)
 {
 	char *p = (char *)vaddr + (nr ^ 31) / 8;
 	char retval;
 	__asm__ __volatile__ ("bclr %2,%1; sne %0"
 			: "=d" (retval), "+m" (*p)
 			: "di" (nr & 7));
 	return retval;
 }
 static inline int __generic_test_and_clear_bit(int nr, unsigned long *vaddr)
 {
 	char retval;
 	__asm__ __volatile__ ("bfclr %2{%1:#1}; sne %0"
 			: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
 	return retval;
 }
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 #define clear_bit(nr,vaddr) \
   (__builtin_constant_p(nr) ? \
    __constant_clear_bit(nr, vaddr) : \
    __generic_clear_bit(nr, vaddr))
 #define __clear_bit(nr,vaddr) clear_bit(nr,vaddr)
 static inline void __constant_clear_bit(int nr, volatile unsigned long *vaddr)
 {
 	char *p = (char *)vaddr + (nr ^ 31) / 8;
 	__asm__ __volatile__ ("bclr %1,%0"
 			: "+m" (*p) : "di" (nr & 7));
 }
 static inline void __generic_clear_bit(int nr, volatile unsigned long *vaddr)
 {
 	__asm__ __volatile__ ("bfclr %1{%0:#1}"
 			: : "d" (nr^31), "o" (*vaddr) : "memory");
 }
 #define test_and_change_bit(nr,vaddr) \
   (__builtin_constant_p(nr) ? \
    __constant_test_and_change_bit(nr, vaddr) : \
    __generic_test_and_change_bit(nr, vaddr))
 #define __test_and_change_bit(nr,vaddr) test_and_change_bit(nr,vaddr)
 #define __change_bit(nr,vaddr) change_bit(nr,vaddr)
 static inline int __constant_test_and_change_bit(int nr, unsigned long *vaddr)
 {
 	char *p = (char *)vaddr + (nr ^ 31) / 8;
 	char retval;
 	__asm__ __volatile__ ("bchg %2,%1; sne %0"
 			: "=d" (retval), "+m" (*p)
 			: "di" (nr & 7));
 	return retval;
 }
 static inline int __generic_test_and_change_bit(int nr, unsigned long *vaddr)
 {
 	char retval;
 	__asm__ __volatile__ ("bfchg %2{%1:#1}; sne %0"
 			: "=d" (retval) : "d" (nr^31), "o" (*vaddr) : "memory");
 	return retval;
 }
 #define change_bit(nr,vaddr) \
   (__builtin_constant_p(nr) ? \
    __constant_change_bit(nr, vaddr) : \
    __generic_change_bit(nr, vaddr))
 static inline void __constant_change_bit(int nr, unsigned long *vaddr)
 {
 	char *p = (char *)vaddr + (nr ^ 31) / 8;
 	__asm__ __volatile__ ("bchg %1,%0"
 			: "+m" (*p) : "di" (nr & 7));
 }
 static inline void __generic_change_bit(int nr, unsigned long *vaddr)
 {
 	__asm__ __volatile__ ("bfchg %1{%0:#1}"
 			: : "d" (nr^31), "o" (*vaddr) : "memory");
 }
 static inline int test_bit(int nr, const unsigned long *vaddr)
 {
 	return (vaddr[nr >> 5] & (1UL << (nr & 31))) != 0;
 }
 static inline int find_first_zero_bit(const unsigned long *vaddr,
 				      unsigned size)
 {
 	const unsigned long *p = vaddr;
 	int res = 32;
 	unsigned long num;
 	if (!size)
 		return 0;
 	size = (size + 31) >> 5;
 	while (!(num = ~*p++)) {
 		if (!--size)
 			goto out;
 	}
 	__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
 			      : "=d" (res) : "d" (num & -num));
 	res ^= 31;
 out:
 	return ((long)p - (long)vaddr - 4) * 8 + res;
 }
 static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
 				     int offset)
 {
 	const unsigned long *p = vaddr + (offset >> 5);
 	int bit = offset & 31UL, res;
 	if (offset >= size)
 		return size;
 	if (bit) {
 		unsigned long num = ~*p++ & (~0UL << bit);
 		offset -= bit;
 		/* Look for zero in first longword */
 		__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
 				      : "=d" (res) : "d" (num & -num));
 		if (res < 32)
 			return offset + (res ^ 31);
 		offset += 32;
 	}
 	/* No zero yet, search remaining full bytes for a zero */
 	res = find_first_zero_bit(p, size - ((long)p - (long)vaddr) * 8);
 	return offset + res;
 }
 static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
 {
 	const unsigned long *p = vaddr;
 	int res = 32;
 	unsigned long num;
 	if (!size)
 		return 0;
 	size = (size + 31) >> 5;
 	while (!(num = *p++)) {
 		if (!--size)
 			goto out;
 	}
 	__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
 			      : "=d" (res) : "d" (num & -num));
 	res ^= 31;
 out:
 	return ((long)p - (long)vaddr - 4) * 8 + res;
 }
 static inline int find_next_bit(const unsigned long *vaddr, int size,
 				int offset)
 {
 	const unsigned long *p = vaddr + (offset >> 5);
 	int bit = offset & 31UL, res;
 	if (offset >= size)
 		return size;
 	if (bit) {
 		unsigned long num = *p++ & (~0UL << bit);
 		offset -= bit;
 		/* Look for one in first longword */
 		__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
 				      : "=d" (res) : "d" (num & -num));
 		if (res < 32)
 			return offset + (res ^ 31);
 		offset += 32;
 	}
 	/* No one yet, search remaining full bytes for a one */
 	res = find_first_bit(p, size - ((long)p - (long)vaddr) * 8);
 	return offset + res;
 }
 /*
  * ffz = Find First Zero in word. Undefined if no zero exists,
  * so code should check against ~0UL first..
  */
 static inline unsigned long ffz(unsigned long word)
 {
 	int res;
 	__asm__ __volatile__ ("bfffo %1{#0,#0},%0"
 			      : "=d" (res) : "d" (~word & -~word));
 	return res ^ 31;
 }
 #ifdef __KERNEL__
 /*
  * ffs: find first bit set. This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
 static inline int ffs(int x)
 {
 	int cnt;
 	asm ("bfffo %1{#0:#0},%0" : "=d" (cnt) : "dm" (x & -x));
 	return 32 - cnt;
 }
 #define __ffs(x) (ffs(x) - 1)
 /*
  * fls: find last bit set.
  */
 static inline int fls(int x)
 {
 	int cnt;
 	asm ("bfffo %1{#0,#0},%0" : "=d" (cnt) : "dm" (x));
 	return 32 - cnt;
 }
 static inline int __fls(int x)
 {
 	return fls(x) - 1;
 }
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
-/* Bitmap functions for the minix filesystem */
-static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size)
-{
-	const unsigned short *p = vaddr, *addr = vaddr;
-	unsigned short num;
-	if (!size)
-		return 0;
-	size = (size >> 4) + ((size & 15) > 0);
-	while (*p++ == 0xffff) {
-		if (--size == 0)
-			return (p - addr) << 4;
-	}
-	num = *--p;
-	return ((p - addr) << 4) + ffz(num);
-}
-#define minix_test_and_set_bit(nr, addr)	__test_and_set_bit((nr) ^ 16, (unsigned long *)(addr))
-#define minix_set_bit(nr,addr)			__set_bit((nr) ^ 16, (unsigned long *)(addr))
-#define minix_test_and_clear_bit(nr, addr)	__test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr))
-static inline int minix_test_bit(int nr, const void *vaddr)
-{
-	const unsigned short *p = vaddr;
-	return (p[nr >> 4] & (1U << (nr & 15))) != 0;
-}
 /* Bitmap functions for the little endian bitmap. */
 static inline void __set_bit_le(int nr, void *addr)
 {
 	__set_bit(nr ^ 24, addr);
 }
 static inline void __clear_bit_le(int nr, void *addr)
 {
 	__clear_bit(nr ^ 24, addr);
 }
 static inline int __test_and_set_bit_le(int nr, void *addr)
 {
 	return __test_and_set_bit(nr ^ 24, addr);
 }
 static inline int test_and_set_bit_le(int nr, void *addr)
 {
 	return test_and_set_bit(nr ^ 24, addr);
 }
 static inline int __test_and_clear_bit_le(int nr, void *addr)
 {
 	return __test_and_clear_bit(nr ^ 24, addr);
 }
 static inline int test_and_clear_bit_le(int nr, void *addr)
 {
 	return test_and_clear_bit(nr ^ 24, addr);
 }
 static inline int test_bit_le(int nr, const void *vaddr)
 {
 	const unsigned char *p = vaddr;
 	return (p[nr >> 3] & (1U << (nr & 7))) != 0;
 }
 static inline int find_first_zero_bit_le(const void *vaddr, unsigned size)
 {
 	const unsigned long *p = vaddr, *addr = vaddr;
 	int res;
 	if (!size)
 		return 0;
 	size = (size >> 5) + ((size & 31) > 0);
 	while (*p++ == ~0UL)
 	{
 		if (--size == 0)
 			return (p - addr) << 5;
 	}
 	--p;
 	for (res = 0; res < 32; res++)
 		if (!test_bit_le(res, p))
 			break;
 	return (p - addr) * 32 + res;
 }
 static inline unsigned long find_next_zero_bit_le(const void *addr,
 		unsigned long size, unsigned long offset)
 {
 	const unsigned long *p = addr;
 	int bit = offset & 31UL, res;
 	if (offset >= size)
 		return size;
 	p += offset >> 5;
 	if (bit) {
 		offset -= bit;
 		/* Look for zero in first longword */
 		for (res = bit; res < 32; res++)
 			if (!test_bit_le(res, p))
 				return offset + res;
 		p++;
 		offset += 32;
 	}
 	/* No zero yet, search remaining full bytes for a zero */
 	return offset + find_first_zero_bit_le(p, size - offset);
 }
 static inline int find_first_bit_le(const void *vaddr, unsigned size)
 {
 	const unsigned long *p = vaddr, *addr = vaddr;
 	int res;
 	if (!size)
 		return 0;
 	size = (size >> 5) + ((size & 31) > 0);
 	while (*p++ == 0UL) {
 		if (--size == 0)
 			return (p - addr) << 5;
 	}
 	--p;
 	for (res = 0; res < 32; res++)
 		if (test_bit_le(res, p))
 			break;
 	return (p - addr) * 32 + res;
 }
 static inline unsigned long find_next_bit_le(const void *addr,
 		unsigned long size, unsigned long offset)
 {
 	const unsigned long *p = addr;
 	int bit = offset & 31UL, res;
 	if (offset >= size)
 		return size;
 	p += offset >> 5;
 	if (bit) {
 		offset -= bit;
 		/* Look for one in first longword */
 		for (res = bit; res < 32; res++)
 			if (test_bit_le(res, p))
 				return offset + res;
 		p++;
 		offset += 32;
 	}
 	/* No set bit yet, search remaining full bytes for a set bit */
 	return offset + find_first_bit_le(p, size - offset);
 }
 /* Bitmap functions for the ext2 filesystem. */
 #define ext2_set_bit_atomic(lock, nr, addr)	\
 	test_and_set_bit_le(nr, addr)
 #define ext2_clear_bit_atomic(lock, nr, addr)	\
 	test_and_clear_bit_le(nr, addr)
 #endif /* __KERNEL__ */
 #endif /* _M68K_BITOPS_H */

arch/m68k/include/asm/bitops_no.h

Diff comments View file @ 61f2e7b

 #ifndef _M68KNOMMU_BITOPS_H
 #define _M68KNOMMU_BITOPS_H
 /*
  * Copyright 1992, Linus Torvalds.
  */
 #include <linux/compiler.h>
 #include <asm/byteorder.h>	/* swab32 */
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #if defined (__mcfisaaplus__) || defined (__mcfisac__)
 static inline int ffs(unsigned int val)
 {
         if (!val)
                 return 0;
         asm volatile(
                         "bitrev %0\n\t"
                         "ff1 %0\n\t"
                         : "=d" (val)
                         : "0" (val)
 		    );
         val++;
         return val;
 }
 static inline int __ffs(unsigned int val)
 {
         asm volatile(
                         "bitrev %0\n\t"
                         "ff1 %0\n\t"
                         : "=d" (val)
                         : "0" (val)
 		    );
         return val;
 }
 #else
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/__ffs.h>
 #endif
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/ffz.h>
 static __inline__ void set_bit(int nr, volatile unsigned long * addr)
 {
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)"
 	     : "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "d" (nr)
 	     : "%a0", "cc");
 #else
 	__asm__ __volatile__ ("bset %1,%0"
 	     : "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "di" (nr)
 	     : "cc");
 #endif
 }
 #define __set_bit(nr, addr) set_bit(nr, addr)
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
 {
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)"
 	     : "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "d" (nr)
 	     : "%a0", "cc");
 #else
 	__asm__ __volatile__ ("bclr %1,%0"
 	     : "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "di" (nr)
 	     : "cc");
 #endif
 }
 #define __clear_bit(nr, addr) clear_bit(nr, addr)
 static __inline__ void change_bit(int nr, volatile unsigned long * addr)
 {
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)"
 	     : "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "d" (nr)
 	     : "%a0", "cc");
 #else
 	__asm__ __volatile__ ("bchg %1,%0"
 	     : "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "di" (nr)
 	     : "cc");
 #endif
 }
 #define __change_bit(nr, addr) change_bit(nr, addr)
 static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
 {
 	char retval;
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "d" (nr)
 	     : "%a0");
 #else
 	__asm__ __volatile__ ("bset %2,%1; sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "di" (nr)
 	     /* No clobber */);
 #endif
 	return retval;
 }
 #define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
 static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
 {
 	char retval;
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "d" (nr)
 	     : "%a0");
 #else
 	__asm__ __volatile__ ("bclr %2,%1; sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "di" (nr)
 	     /* No clobber */);
 #endif
 	return retval;
 }
 #define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
 static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
 {
 	char retval;
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "d" (nr)
 	     : "%a0");
 #else
 	__asm__ __volatile__ ("bchg %2,%1; sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3])
 	     : "di" (nr)
 	     /* No clobber */);
 #endif
 	return retval;
 }
 #define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr)
 /*
  * This routine doesn't need to be atomic.
  */
 static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr)
 {
 	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
 }
 static __inline__ int __test_bit(int nr, const volatile unsigned long * addr)
 {
 	int 	* a = (int *) addr;
 	int	mask;
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	return ((mask & *a) != 0);
 }
 #define test_bit(nr,addr) \
 (__builtin_constant_p(nr) ? \
  __constant_test_bit((nr),(addr)) : \
  __test_bit((nr),(addr)))
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #define BITOP_LE_SWIZZLE	((BITS_PER_LONG-1) & ~0x7)
 static inline void __set_bit_le(int nr, void *addr)
 {
 	__set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline void __clear_bit_le(int nr, void *addr)
 {
 	__clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline int __test_and_set_bit_le(int nr, volatile void *addr)
 {
 	char retval;
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
 	     : "d" (nr)
 	     : "%a0");
 #else
 	__asm__ __volatile__ ("bset %2,%1; sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
 	     : "di" (nr)
 	     /* No clobber */);
 #endif
 	return retval;
 }
 static inline int __test_and_clear_bit_le(int nr, volatile void *addr)
 {
 	char retval;
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
 	     : "d" (nr)
 	     : "%a0");
 #else
 	__asm__ __volatile__ ("bclr %2,%1; sne %0"
 	     : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3])
 	     : "di" (nr)
 	     /* No clobber */);
 #endif
 	return retval;
 }
 #define ext2_set_bit_atomic(lock, nr, addr)		\
 	({						\
 		int ret;				\
 		spin_lock(lock);			\
 		ret = __test_and_set_bit_le((nr), (addr));	\
 		spin_unlock(lock);			\
 		ret;					\
 	})
 #define ext2_clear_bit_atomic(lock, nr, addr)		\
 	({						\
 		int ret;				\
 		spin_lock(lock);			\
 		ret = __test_and_clear_bit_le((nr), (addr));	\
 		spin_unlock(lock);			\
 		ret;					\
 	})
 static inline int test_bit_le(int nr, const volatile void *addr)
 {
 	char retval;
 #ifdef CONFIG_COLDFIRE
 	__asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0"
 	     : "=d" (retval)
 	     : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr)
 	     : "%a0");
 #else
 	__asm__ __volatile__ ("btst %2,%1; sne %0"
 	     : "=d" (retval)
 	     : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr)
 	     /* No clobber */);
 #endif
 	return retval;
 }
 #define find_first_zero_bit_le(addr, size)	\
 	find_next_zero_bit_le((addr), (size), 0)
 static inline unsigned long find_next_zero_bit_le(void *addr, unsigned long size, unsigned long offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
 	unsigned long tmp;
 	if (offset >= size)
 		return size;
 	size -= result;
 	offset &= 31UL;
 	if(offset) {
 		/* We hold the little endian value in tmp, but then the
 		 * shift is illegal. So we could keep a big endian value
 		 * in tmp, like this:
 		 *
 		 * tmp = __swab32(*(p++));
 		 * tmp |= ~0UL >> (32-offset);
 		 *
 		 * but this would decrease performance, so we change the
 		 * shift:
 		 */
 		tmp = *(p++);
 		tmp |= __swab32(~0UL >> (32-offset));
 		if(size < 32)
 			goto found_first;
 		if(~tmp)
 			goto found_middle;
 		size -= 32;
 		result += 32;
 	}
 	while(size & ~31UL) {
 		if(~(tmp = *(p++)))
 			goto found_middle;
 		result += 32;
 		size -= 32;
 	}
 	if(!size)
 		return result;
 	tmp = *p;
 found_first:
 	/* tmp is little endian, so we would have to swab the shift,
 	 * see above. But then we have to swab tmp below for ffz, so
 	 * we might as well do this here.
 	 */
 	return result + ffz(__swab32(tmp) | (~0UL << size));
 found_middle:
 	return result + ffz(__swab32(tmp));
 }
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #endif /* _M68KNOMMU_BITOPS_H */

arch/mips/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (c) 1994 - 1997, 99, 2000, 06, 07  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
  */
 #ifndef _ASM_BITOPS_H
 #define _ASM_BITOPS_H
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <linux/irqflags.h>
 #include <linux/types.h>
 #include <asm/barrier.h>
 #include <asm/bug.h>
 #include <asm/byteorder.h>		/* sigh ... */
 #include <asm/cpu-features.h>
 #include <asm/sgidefs.h>
 #include <asm/war.h>
 #if _MIPS_SZLONG == 32
 #define SZLONG_LOG 5
 #define SZLONG_MASK 31UL
 #define __LL		"ll	"
 #define __SC		"sc	"
 #define __INS		"ins    "
 #define __EXT		"ext    "
 #elif _MIPS_SZLONG == 64
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL		"lld	"
 #define __SC		"scd	"
 #define __INS		"dins    "
 #define __EXT		"dext    "
 #endif
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	smp_mb__before_llsc()
 #define smp_mb__after_clear_bit()	smp_llsc_mb()
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 	unsigned short bit = nr & SZLONG_MASK;
 	unsigned long temp;
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		__asm__ __volatile__(
 		"	.set	mips3					\n"
 		"1:	" __LL "%0, %1			# set_bit	\n"
 		"	or	%0, %2					\n"
 		"	" __SC	"%0, %1					\n"
 		"	beqzl	%0, 1b					\n"
 		"	.set	mips0					\n"
 		: "=&r" (temp), "=m" (*m)
 		: "ir" (1UL << bit), "m" (*m));
 #ifdef CONFIG_CPU_MIPSR2
 	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
 		do {
 			__asm__ __volatile__(
 			"	" __LL "%0, %1		# set_bit	\n"
 			"	" __INS "%0, %3, %2, 1			\n"
 			"	" __SC "%0, %1				\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (bit), "r" (~0));
 		} while (unlikely(!temp));
 #endif /* CONFIG_CPU_MIPSR2 */
 	} else if (kernel_uses_llsc) {
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL "%0, %1		# set_bit	\n"
 			"	or	%0, %2				\n"
 			"	" __SC	"%0, %1				\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (1UL << bit));
 		} while (unlikely(!temp));
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		*a |= mask;
 		raw_local_irq_restore(flags);
 	}
 }
 /*
  * clear_bit - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and may not be reordered.  However, it does
  * not contain a memory barrier, so if it is used for locking purposes,
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 	unsigned short bit = nr & SZLONG_MASK;
 	unsigned long temp;
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		__asm__ __volatile__(
 		"	.set	mips3					\n"
 		"1:	" __LL "%0, %1			# clear_bit	\n"
 		"	and	%0, %2					\n"
 		"	" __SC "%0, %1					\n"
 		"	beqzl	%0, 1b					\n"
 		"	.set	mips0					\n"
 		: "=&r" (temp), "+m" (*m)
 		: "ir" (~(1UL << bit)));
 #ifdef CONFIG_CPU_MIPSR2
 	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
 		do {
 			__asm__ __volatile__(
 			"	" __LL "%0, %1		# clear_bit	\n"
 			"	" __INS "%0, $0, %2, 1			\n"
 			"	" __SC "%0, %1				\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (bit));
 		} while (unlikely(!temp));
 #endif /* CONFIG_CPU_MIPSR2 */
 	} else if (kernel_uses_llsc) {
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL "%0, %1		# clear_bit	\n"
 			"	and	%0, %2				\n"
 			"	" __SC "%0, %1				\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (~(1UL << bit)));
 		} while (unlikely(!temp));
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		*a &= ~mask;
 		raw_local_irq_restore(flags);
 	}
 }
 /*
  * clear_bit_unlock - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and implies release semantics before the memory
  * operation. It can be used for an unlock.
  */
 static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
 {
 	smp_mb__before_clear_bit();
 	clear_bit(nr, addr);
 }
 /*
  * change_bit - Toggle a bit in memory
  * @nr: Bit to change
  * @addr: Address to start counting from
  *
  * change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned short bit = nr & SZLONG_MASK;
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		__asm__ __volatile__(
 		"	.set	mips3				\n"
 		"1:	" __LL "%0, %1		# change_bit	\n"
 		"	xor	%0, %2				\n"
 		"	" __SC	"%0, %1				\n"
 		"	beqzl	%0, 1b				\n"
 		"	.set	mips0				\n"
 		: "=&r" (temp), "+m" (*m)
 		: "ir" (1UL << bit));
 	} else if (kernel_uses_llsc) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL "%0, %1		# change_bit	\n"
 			"	xor	%0, %2				\n"
 			"	" __SC	"%0, %1				\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m)
 			: "ir" (1UL << bit));
 		} while (unlikely(!temp));
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		*a ^= mask;
 		raw_local_irq_restore(flags);
 	}
 }
 /*
  * test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_set_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
 	unsigned short bit = nr & SZLONG_MASK;
 	unsigned long res;
 	smp_mb__before_llsc();
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		__asm__ __volatile__(
 		"	.set	mips3					\n"
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 		"	or	%2, %0, %3				\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
 		"	.set	mips0					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
 	} else if (kernel_uses_llsc) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 			"	or	%2, %0, %3			\n"
 			"	" __SC	"%2, %1				\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
 		} while (unlikely(!res));
 		res = temp & (1UL << bit);
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		res = (mask & *a);
 		*a |= mask;
 		raw_local_irq_restore(flags);
 	}
 	smp_llsc_mb();
 	return res != 0;
 }
 /*
  * test_and_set_bit_lock - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and implies acquire ordering semantics
  * after the memory operation.
  */
 static inline int test_and_set_bit_lock(unsigned long nr,
 	volatile unsigned long *addr)
 {
 	unsigned short bit = nr & SZLONG_MASK;
 	unsigned long res;
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		__asm__ __volatile__(
 		"	.set	mips3					\n"
 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
 		"	or	%2, %0, %3				\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
 		"	.set	mips0					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
 	} else if (kernel_uses_llsc) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL "%0, %1	# test_and_set_bit	\n"
 			"	or	%2, %0, %3			\n"
 			"	" __SC	"%2, %1				\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
 		} while (unlikely(!res));
 		res = temp & (1UL << bit);
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		res = (mask & *a);
 		*a |= mask;
 		raw_local_irq_restore(flags);
 	}
 	smp_llsc_mb();
 	return res != 0;
 }
 /*
  * test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_clear_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
 	unsigned short bit = nr & SZLONG_MASK;
 	unsigned long res;
 	smp_mb__before_llsc();
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		__asm__ __volatile__(
 		"	.set	mips3					\n"
 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
 		"	or	%2, %0, %3				\n"
 		"	xor	%2, %3					\n"
 		"	" __SC 	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
 		"	.set	mips0					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
 #ifdef CONFIG_CPU_MIPSR2
 	} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		do {
 			__asm__ __volatile__(
 			"	" __LL	"%0, %1	# test_and_clear_bit	\n"
 			"	" __EXT "%2, %0, %3, 1			\n"
 			"	" __INS	"%0, $0, %3, 1			\n"
 			"	" __SC 	"%0, %1				\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "ir" (bit)
 			: "memory");
 		} while (unlikely(!temp));
 #endif
 	} else if (kernel_uses_llsc) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL	"%0, %1	# test_and_clear_bit	\n"
 			"	or	%2, %0, %3			\n"
 			"	xor	%2, %3				\n"
 			"	" __SC 	"%2, %1				\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
 		} while (unlikely(!res));
 		res = temp & (1UL << bit);
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		res = (mask & *a);
 		*a &= ~mask;
 		raw_local_irq_restore(flags);
 	}
 	smp_llsc_mb();
 	return res != 0;
 }
 /*
  * test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_change_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
 	unsigned short bit = nr & SZLONG_MASK;
 	unsigned long res;
 	smp_mb__before_llsc();
 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		__asm__ __volatile__(
 		"	.set	mips3					\n"
 		"1:	" __LL	"%0, %1		# test_and_change_bit	\n"
 		"	xor	%2, %0, %3				\n"
 		"	" __SC	"%2, %1					\n"
 		"	beqzl	%2, 1b					\n"
 		"	and	%2, %0, %3				\n"
 		"	.set	mips0					\n"
 		: "=&r" (temp), "+m" (*m), "=&r" (res)
 		: "r" (1UL << bit)
 		: "memory");
 	} else if (kernel_uses_llsc) {
 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 		unsigned long temp;
 		do {
 			__asm__ __volatile__(
 			"	.set	mips3				\n"
 			"	" __LL	"%0, %1	# test_and_change_bit	\n"
 			"	xor	%2, %0, %3			\n"
 			"	" __SC	"\t%2, %1			\n"
 			"	.set	mips0				\n"
 			: "=&r" (temp), "+m" (*m), "=&r" (res)
 			: "r" (1UL << bit)
 			: "memory");
 		} while (unlikely(!res));
 		res = temp & (1UL << bit);
 	} else {
 		volatile unsigned long *a = addr;
 		unsigned long mask;
 		unsigned long flags;
 		a += nr >> SZLONG_LOG;
 		mask = 1UL << bit;
 		raw_local_irq_save(flags);
 		res = (mask & *a);
 		*a ^= mask;
 		raw_local_irq_restore(flags);
 	}
 	smp_llsc_mb();
 	return res != 0;
 }
 #include <asm-generic/bitops/non-atomic.h>
 /*
  * __clear_bit_unlock - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * __clear_bit() is non-atomic and implies release semantics before the memory
  * operation. It can be used for an unlock if no other CPUs can concurrently
  * modify other bits in the word.
  */
 static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
 {
 	smp_mb();
 	__clear_bit(nr, addr);
 }
 /*
  * Return the bit position (0..63) of the most significant 1 bit in a word
  * Returns -1 if no 1 bit exists
  */
 static inline unsigned long __fls(unsigned long word)
 {
 	int num;
 	if (BITS_PER_LONG == 32 &&
 	    __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
 		__asm__(
 		"	.set	push					\n"
 		"	.set	mips32					\n"
 		"	clz	%0, %1					\n"
 		"	.set	pop					\n"
 		: "=r" (num)
 		: "r" (word));
 		return 31 - num;
 	}
 	if (BITS_PER_LONG == 64 &&
 	    __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
 		__asm__(
 		"	.set	push					\n"
 		"	.set	mips64					\n"
 		"	dclz	%0, %1					\n"
 		"	.set	pop					\n"
 		: "=r" (num)
 		: "r" (word));
 		return 63 - num;
 	}
 	num = BITS_PER_LONG - 1;
 #if BITS_PER_LONG == 64
 	if (!(word & (~0ul << 32))) {
 		num -= 32;
 		word <<= 32;
 	}
 #endif
 	if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
 		num -= 16;
 		word <<= 16;
 	}
 	if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
 		num -= 8;
 		word <<= 8;
 	}
 	if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
 		num -= 4;
 		word <<= 4;
 	}
 	if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
 		num -= 2;
 		word <<= 2;
 	}
 	if (!(word & (~0ul << (BITS_PER_LONG-1))))
 		num -= 1;
 	return num;
 }
 /*
  * __ffs - find first bit in word.
  * @word: The word to search
  *
  * Returns 0..SZLONG-1
  * Undefined if no bit exists, so code should check against 0 first.
  */
 static inline unsigned long __ffs(unsigned long word)
 {
 	return __fls(word & -word);
 }
 /*
  * fls - find last bit set.
  * @word: The word to search
  *
  * This is defined the same way as ffs.
  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
  */
 static inline int fls(int x)
 {
 	int r;
 	if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
 		__asm__("clz %0, %1" : "=r" (x) : "r" (x));
 		return 32 - x;
 	}
 	r = 32;
 	if (!x)
 		return 0;
 	if (!(x & 0xffff0000u)) {
 		x <<= 16;
 		r -= 16;
 	}
 	if (!(x & 0xff000000u)) {
 		x <<= 8;
 		r -= 8;
 	}
 	if (!(x & 0xf0000000u)) {
 		x <<= 4;
 		r -= 4;
 	}
 	if (!(x & 0xc0000000u)) {
 		x <<= 2;
 		r -= 2;
 	}
 	if (!(x & 0x80000000u)) {
 		x <<= 1;
 		r -= 1;
 	}
 	return r;
 }
 #include <asm-generic/bitops/fls64.h>
 /*
  * ffs - find first bit set.
  * @word: The word to search
  *
  * This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
 static inline int ffs(int word)
 {
 	if (!word)
 		return 0;
 	return fls(word & -word);
 }
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/find.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/sched.h>
 #include <asm/arch_hweight.h>
 #include <asm-generic/bitops/const_hweight.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* _ASM_BITOPS_H */

arch/mn10300/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /* MN10300 bit operations
  *
  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
  * Written by David Howells (dhowells@redhat.com)
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public Licence
  * as published by the Free Software Foundation; either version
  * 2 of the Licence, or (at your option) any later version.
  *
  * These have to be done with inline assembly: that way the bit-setting
  * is guaranteed to be atomic. All bit operations return 0 if the bit
  * was cleared before the operation and != 0 if it was not.
  *
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 #ifndef __ASM_BITOPS_H
 #define __ASM_BITOPS_H
 #include <asm/cpu-regs.h>
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 /*
  * set bit
  */
 #define __set_bit(nr, addr)					\
 ({								\
 	volatile unsigned char *_a = (unsigned char *)(addr);	\
 	const unsigned shift = (nr) & 7;			\
 	_a += (nr) >> 3;					\
 								\
 	asm volatile("bset %2,(%1) # set_bit reg"		\
 		     : "=m"(*_a)				\
 		     : "a"(_a), "d"(1 << shift),  "m"(*_a)	\
 		     : "memory", "cc");				\
 })
 #define set_bit(nr, addr) __set_bit((nr), (addr))
 /*
  * clear bit
  */
 #define ___clear_bit(nr, addr)					\
 ({								\
 	volatile unsigned char *_a = (unsigned char *)(addr);	\
 	const unsigned shift = (nr) & 7;			\
 	_a += (nr) >> 3;					\
 								\
 	asm volatile("bclr %2,(%1) # clear_bit reg"		\
 		     : "=m"(*_a)				\
 		     : "a"(_a), "d"(1 << shift), "m"(*_a)	\
 		     : "memory", "cc");				\
 })
 #define clear_bit(nr, addr) ___clear_bit((nr), (addr))
 static inline void __clear_bit(unsigned long nr, volatile void *addr)
 {
 	unsigned int *a = (unsigned int *) addr;
 	int mask;
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	*a &= ~mask;
 }
 /*
  * test bit
  */
 static inline int test_bit(unsigned long nr, const volatile void *addr)
 {
 	return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31));
 }
 /*
  * change bit
  */
 static inline void __change_bit(unsigned long nr, volatile void *addr)
 {
 	int	mask;
 	unsigned int *a = (unsigned int *) addr;
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	*a ^= mask;
 }
 extern void change_bit(unsigned long nr, volatile void *addr);
 /*
  * test and set bit
  */
 #define __test_and_set_bit(nr,addr)				\
 ({								\
 	volatile unsigned char *_a = (unsigned char *)(addr);	\
 	const unsigned shift = (nr) & 7;			\
 	unsigned epsw;						\
 	_a += (nr) >> 3;					\
 								\
 	asm volatile("bset %3,(%2) # test_set_bit reg\n"	\
 		     "mov epsw,%1"				\
 		     : "=m"(*_a), "=d"(epsw)			\
 		     : "a"(_a), "d"(1 << shift), "m"(*_a)	\
 		     : "memory", "cc");				\
 								\
 	!(epsw & EPSW_FLAG_Z);					\
 })
 #define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr))
 /*
  * test and clear bit
  */
 #define __test_and_clear_bit(nr, addr)				\
 ({								\
         volatile unsigned char *_a = (unsigned char *)(addr);	\
 	const unsigned shift = (nr) & 7;			\
 	unsigned epsw;						\
 	_a += (nr) >> 3;					\
 								\
 	asm volatile("bclr %3,(%2) # test_clear_bit reg\n"	\
 		     "mov epsw,%1"				\
 		     : "=m"(*_a), "=d"(epsw)			\
 		     : "a"(_a), "d"(1 << shift), "m"(*_a)	\
 		     : "memory", "cc");				\
 								\
 	!(epsw & EPSW_FLAG_Z);					\
 })
 #define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr))
 /*
  * test and change bit
  */
 static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
 {
 	int	mask, retval;
 	unsigned int *a = (unsigned int *)addr;
 	a += nr >> 5;
 	mask = 1 << (nr & 0x1f);
 	retval = (mask & *a) != 0;
 	*a ^= mask;
 	return retval;
 }
 extern int test_and_change_bit(unsigned long nr, volatile void *addr);
 #include <asm-generic/bitops/lock.h>
 #ifdef __KERNEL__
 /**
  * __ffs - find first bit set
  * @x: the word to search
  *
  * - return 31..0 to indicate bit 31..0 most least significant bit set
  * - if no bits are set in x, the result is undefined
  */
 static inline __attribute__((const))
 unsigned long __ffs(unsigned long x)
 {
 	int bit;
 	asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x) : "cc");
 	return bit;
 }
 /*
  * special slimline version of fls() for calculating ilog2_u32()
  * - note: no protection against n == 0
  */
 static inline __attribute__((const))
 int __ilog2_u32(u32 n)
 {
 	int bit;
 	asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n) : "cc");
 	return bit;
 }
 /**
  * fls - find last bit set
  * @x: the word to search
  *
  * This is defined the same way as ffs:
  * - return 32..1 to indicate bit 31..0 most significant bit set
  * - return 0 to indicate no bits set
  */
 static inline __attribute__((const))
 int fls(int x)
 {
 	return (x != 0) ? __ilog2_u32(x) + 1 : 0;
 }
 /**
  * __fls - find last (most-significant) set bit in a long word
  * @word: the word to search
  *
  * Undefined if no set bit exists, so code should check against 0 first.
  */
 static inline unsigned long __fls(unsigned long word)
 {
 	return __ilog2_u32(word);
 }
 /**
  * ffs - find first bit set
  * @x: the word to search
  *
  * - return 32..1 to indicate bit 31..0 most least significant bit set
  * - return 0 to indicate no bits set
  */
 static inline __attribute__((const))
 int ffs(int x)
 {
 	/* Note: (x & -x) gives us a mask that is the least significant
 	 * (rightmost) 1-bit of the value in x.
 	 */
 	return fls(x & -x);
 }
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/hweight.h>
 #define ext2_set_bit_atomic(lock, nr, addr) \
 	test_and_set_bit((nr), (addr))
 #define ext2_clear_bit_atomic(lock, nr, addr) \
 	test_and_clear_bit((nr), (addr))
 #include <asm-generic/bitops/le.h>
-#include <asm-generic/bitops/minix-le.h>
 #endif /* __KERNEL__ */
 #endif /* __ASM_BITOPS_H */

arch/parisc/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _PARISC_BITOPS_H
 #define _PARISC_BITOPS_H
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <asm/types.h>		/* for BITS_PER_LONG/SHIFT_PER_LONG */
 #include <asm/byteorder.h>
 #include <asm/atomic.h>
 /*
  * HP-PARISC specific bit operations
  * for a detailed description of the functions please refer
  * to include/asm-i386/bitops.h or kerneldoc
  */
 #define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
 #define smp_mb__before_clear_bit()      smp_mb()
 #define smp_mb__after_clear_bit()       smp_mb()
 /* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
  * on use of volatile and __*_bit() (set/clear/change):
  *	*_bit() want use of volatile.
  *	__*_bit() are "relaxed" and don't use spinlock or volatile.
  */
 static __inline__ void set_bit(int nr, volatile unsigned long * addr)
 {
 	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
 	unsigned long flags;
 	addr += (nr >> SHIFT_PER_LONG);
 	_atomic_spin_lock_irqsave(addr, flags);
 	*addr |= mask;
 	_atomic_spin_unlock_irqrestore(addr, flags);
 }
 static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
 {
 	unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
 	unsigned long flags;
 	addr += (nr >> SHIFT_PER_LONG);
 	_atomic_spin_lock_irqsave(addr, flags);
 	*addr &= mask;
 	_atomic_spin_unlock_irqrestore(addr, flags);
 }
 static __inline__ void change_bit(int nr, volatile unsigned long * addr)
 {
 	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
 	unsigned long flags;
 	addr += (nr >> SHIFT_PER_LONG);
 	_atomic_spin_lock_irqsave(addr, flags);
 	*addr ^= mask;
 	_atomic_spin_unlock_irqrestore(addr, flags);
 }
 static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
 {
 	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
 	unsigned long old;
 	unsigned long flags;
 	int set;
 	addr += (nr >> SHIFT_PER_LONG);
 	_atomic_spin_lock_irqsave(addr, flags);
 	old = *addr;
 	set = (old & mask) ? 1 : 0;
 	if (!set)
 		*addr = old | mask;
 	_atomic_spin_unlock_irqrestore(addr, flags);
 	return set;
 }
 static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
 {
 	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
 	unsigned long old;
 	unsigned long flags;
 	int set;
 	addr += (nr >> SHIFT_PER_LONG);
 	_atomic_spin_lock_irqsave(addr, flags);
 	old = *addr;
 	set = (old & mask) ? 1 : 0;
 	if (set)
 		*addr = old & ~mask;
 	_atomic_spin_unlock_irqrestore(addr, flags);
 	return set;
 }
 static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
 {
 	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
 	unsigned long oldbit;
 	unsigned long flags;
 	addr += (nr >> SHIFT_PER_LONG);
 	_atomic_spin_lock_irqsave(addr, flags);
 	oldbit = *addr;
 	*addr = oldbit ^ mask;
 	_atomic_spin_unlock_irqrestore(addr, flags);
 	return (oldbit & mask) ? 1 : 0;
 }
 #include <asm-generic/bitops/non-atomic.h>
 #ifdef __KERNEL__
 /**
  * __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
  * @word: The word to search
  *
  * __ffs() return is undefined if no bit is set.
  *
  * 32-bit fast __ffs by LaMont Jones "lamont At hp com".
  * 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
  * (with help from willy/jejb to get the semantics right)
  *
  * This algorithm avoids branches by making use of nullification.
  * One side effect of "extr" instructions is it sets PSW[N] bit.
  * How PSW[N] (nullify next insn) gets set is determined by the
  * "condition" field (eg "<>" or "TR" below) in the extr* insn.
  * Only the 1st and one of either the 2cd or 3rd insn will get executed.
  * Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
  * cycles for each mispredicted branch.
  */
 static __inline__ unsigned long __ffs(unsigned long x)
 {
 	unsigned long ret;
 	__asm__(
 #ifdef CONFIG_64BIT
 		" ldi       63,%1\n"
 		" extrd,u,*<>  %0,63,32,%%r0\n"
 		" extrd,u,*TR  %0,31,32,%0\n"	/* move top 32-bits down */
 		" addi    -32,%1,%1\n"
 #else
 		" ldi       31,%1\n"
 #endif
 		" extru,<>  %0,31,16,%%r0\n"
 		" extru,TR  %0,15,16,%0\n"	/* xxxx0000 -> 0000xxxx */
 		" addi    -16,%1,%1\n"
 		" extru,<>  %0,31,8,%%r0\n"
 		" extru,TR  %0,23,8,%0\n"	/* 0000xx00 -> 000000xx */
 		" addi    -8,%1,%1\n"
 		" extru,<>  %0,31,4,%%r0\n"
 		" extru,TR  %0,27,4,%0\n"	/* 000000x0 -> 0000000x */
 		" addi    -4,%1,%1\n"
 		" extru,<>  %0,31,2,%%r0\n"
 		" extru,TR  %0,29,2,%0\n"	/* 0000000y, 1100b -> 0011b */
 		" addi    -2,%1,%1\n"
 		" extru,=  %0,31,1,%%r0\n"	/* check last bit */
 		" addi    -1,%1,%1\n"
 			: "+r" (x), "=r" (ret) );
 	return ret;
 }
 #include <asm-generic/bitops/ffz.h>
 /*
  * ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
  * This is defined the same way as the libc and compiler builtin
  * ffs routines, therefore differs in spirit from the above ffz (man ffs).
  */
 static __inline__ int ffs(int x)
 {
 	return x ? (__ffs((unsigned long)x) + 1) : 0;
 }
 /*
  * fls: find last (most significant) bit set.
  * fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
  */
 static __inline__ int fls(int x)
 {
 	int ret;
 	if (!x)
 		return 0;
 	__asm__(
 	"	ldi		1,%1\n"
 	"	extru,<>	%0,15,16,%%r0\n"
 	"	zdep,TR		%0,15,16,%0\n"		/* xxxx0000 */
 	"	addi		16,%1,%1\n"
 	"	extru,<>	%0,7,8,%%r0\n"
 	"	zdep,TR		%0,23,24,%0\n"		/* xx000000 */
 	"	addi		8,%1,%1\n"
 	"	extru,<>	%0,3,4,%%r0\n"
 	"	zdep,TR		%0,27,28,%0\n"		/* x0000000 */
 	"	addi		4,%1,%1\n"
 	"	extru,<>	%0,1,2,%%r0\n"
 	"	zdep,TR		%0,29,30,%0\n"		/* y0000000 (y&3 = 0) */
 	"	addi		2,%1,%1\n"
 	"	extru,=		%0,0,1,%%r0\n"
 	"	addi		1,%1,%1\n"		/* if y & 8, add 1 */
 		: "+r" (x), "=r" (ret) );
 	return ret;
 }
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/sched.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/find.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/le.h>
 /* '3' is bits per byte */
 #define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
 #define ext2_set_bit_atomic(l,nr,addr) \
 		test_and_set_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
 #define ext2_clear_bit_atomic(l,nr,addr) \
 		test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
 #endif	/* __KERNEL__ */
-#include <asm-generic/bitops/minix-le.h>
 #endif /* _PARISC_BITOPS_H */

arch/powerpc/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * PowerPC atomic bit operations.
  *
  * Merged version by David Gibson <david@gibson.dropbear.id.au>.
  * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
  * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard.  They
  * originally took it from the ppc32 code.
  *
  * Within a word, bits are numbered LSB first.  Lot's of places make
  * this assumption by directly testing bits with (val & (1<<nr)).
  * This can cause confusion for large (> 1 word) bitmaps on a
  * big-endian system because, unlike little endian, the number of each
  * bit depends on the word size.
  *
  * The bitop functions are defined to work on unsigned longs, so for a
  * ppc64 system the bits end up numbered:
  *   |63..............0|127............64|191...........128|255...........196|
  * and on ppc32:
  *   |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
  *
  * There are a few little-endian macros used mostly for filesystem
  * bitmaps, these work on similar bit arrays layouts, but
  * byte-oriented:
  *   |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
  *
  * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
  * number field needs to be reversed compared to the big-endian bit
  * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
 #ifndef _ASM_POWERPC_BITOPS_H
 #define _ASM_POWERPC_BITOPS_H
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
 /*
  * clear_bit doesn't imply a memory barrier
  */
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
 #define BITOP_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
 #define BITOP_WORD(nr)		((nr) / BITS_PER_LONG)
 #define BITOP_LE_SWIZZLE	((BITS_PER_LONG-1) & ~0x7)
 /* Macro for generating the ***_bits() functions */
 #define DEFINE_BITOP(fn, op, prefix, postfix)	\
 static __inline__ void fn(unsigned long mask,	\
 		volatile unsigned long *_p)	\
 {						\
 	unsigned long old;			\
 	unsigned long *p = (unsigned long *)_p;	\
 	__asm__ __volatile__ (			\
 	prefix					\
 "1:"	PPC_LLARX(%0,0,%3,0) "\n"		\
 	stringify_in_c(op) "%0,%0,%2\n"		\
 	PPC405_ERR77(0,%3)			\
 	PPC_STLCX "%0,0,%3\n"			\
 	"bne- 1b\n"				\
 	postfix					\
 	: "=&r" (old), "+m" (*p)		\
 	: "r" (mask), "r" (p)			\
 	: "cc", "memory");			\
 }
 DEFINE_BITOP(set_bits, or, "", "")
 DEFINE_BITOP(clear_bits, andc, "", "")
 DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER, "")
 DEFINE_BITOP(change_bits, xor, "", "")
 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
 {
 	set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
 {
 	clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
 {
 	clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 static __inline__ void change_bit(int nr, volatile unsigned long *addr)
 {
 	change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 /* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
  * operands. */
 #define DEFINE_TESTOP(fn, op, prefix, postfix, eh)	\
 static __inline__ unsigned long fn(			\
 		unsigned long mask,			\
 		volatile unsigned long *_p)		\
 {							\
 	unsigned long old, t;				\
 	unsigned long *p = (unsigned long *)_p;		\
 	__asm__ __volatile__ (				\
 	prefix						\
 "1:"	PPC_LLARX(%0,0,%3,eh) "\n"			\
 	stringify_in_c(op) "%1,%0,%2\n"			\
 	PPC405_ERR77(0,%3)				\
 	PPC_STLCX "%1,0,%3\n"				\
 	"bne- 1b\n"					\
 	postfix						\
 	: "=&r" (old), "=&r" (t)			\
 	: "r" (mask), "r" (p)				\
 	: "cc", "memory");				\
 	return (old & mask);				\
 }
 DEFINE_TESTOP(test_and_set_bits, or, PPC_RELEASE_BARRIER,
 	      PPC_ACQUIRE_BARRIER, 0)
 DEFINE_TESTOP(test_and_set_bits_lock, or, "",
 	      PPC_ACQUIRE_BARRIER, 1)
 DEFINE_TESTOP(test_and_clear_bits, andc, PPC_RELEASE_BARRIER,
 	      PPC_ACQUIRE_BARRIER, 0)
 DEFINE_TESTOP(test_and_change_bits, xor, PPC_RELEASE_BARRIER,
 	      PPC_ACQUIRE_BARRIER, 0)
 static __inline__ int test_and_set_bit(unsigned long nr,
 				       volatile unsigned long *addr)
 {
 	return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 static __inline__ int test_and_set_bit_lock(unsigned long nr,
 				       volatile unsigned long *addr)
 {
 	return test_and_set_bits_lock(BITOP_MASK(nr),
 				addr + BITOP_WORD(nr)) != 0;
 }
 static __inline__ int test_and_clear_bit(unsigned long nr,
 					 volatile unsigned long *addr)
 {
 	return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 static __inline__ int test_and_change_bit(unsigned long nr,
 					  volatile unsigned long *addr)
 {
 	return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 #include <asm-generic/bitops/non-atomic.h>
 static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
 {
 	__asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
 	__clear_bit(nr, addr);
 }
 /*
  * Return the zero-based bit position (LE, not IBM bit numbering) of
  * the most significant 1-bit in a double word.
  */
 static __inline__ __attribute__((const))
 int __ilog2(unsigned long x)
 {
 	int lz;
 	asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
 	return BITS_PER_LONG - 1 - lz;
 }
 static inline __attribute__((const))
 int __ilog2_u32(u32 n)
 {
 	int bit;
 	asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
 	return 31 - bit;
 }
 #ifdef __powerpc64__
 static inline __attribute__((const))
 int __ilog2_u64(u64 n)
 {
 	int bit;
 	asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
 	return 63 - bit;
 }
 #endif
 /*
  * Determines the bit position of the least significant 0 bit in the
  * specified double word. The returned bit position will be
  * zero-based, starting from the right side (63/31 - 0).
  */
 static __inline__ unsigned long ffz(unsigned long x)
 {
 	/* no zero exists anywhere in the 8 byte area. */
 	if ((x = ~x) == 0)
 		return BITS_PER_LONG;
 	/*
 	 * Calculate the bit position of the least signficant '1' bit in x
 	 * (since x has been changed this will actually be the least signficant
 	 * '0' bit in * the original x).  Note: (x & -x) gives us a mask that
 	 * is the least significant * (RIGHT-most) 1-bit of the value in x.
 	 */
 	return __ilog2(x & -x);
 }
 static __inline__ int __ffs(unsigned long x)
 {
 	return __ilog2(x & -x);
 }
 /*
  * ffs: find first bit set. This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
 static __inline__ int ffs(int x)
 {
 	unsigned long i = (unsigned long)x;
 	return __ilog2(i & -i) + 1;
 }
 /*
  * fls: find last (most-significant) bit set.
  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
  */
 static __inline__ int fls(unsigned int x)
 {
 	int lz;
 	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
 	return 32 - lz;
 }
 static __inline__ unsigned long __fls(unsigned long x)
 {
 	return __ilog2(x);
 }
 /*
  * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
  * instruction; for 32-bit we use the generic version, which does two
  * 32-bit fls calls.
  */
 #ifdef __powerpc64__
 static __inline__ int fls64(__u64 x)
 {
 	int lz;
 	asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
 	return 64 - lz;
 }
 #else
 #include <asm-generic/bitops/fls64.h>
 #endif /* __powerpc64__ */
 #ifdef CONFIG_PPC64
 unsigned int __arch_hweight8(unsigned int w);
 unsigned int __arch_hweight16(unsigned int w);
 unsigned int __arch_hweight32(unsigned int w);
 unsigned long __arch_hweight64(__u64 w);
 #include <asm-generic/bitops/const_hweight.h>
 #else
 #include <asm-generic/bitops/hweight.h>
 #endif
 #include <asm-generic/bitops/find.h>
 /* Little-endian versions */
 static __inline__ int test_bit_le(unsigned long nr,
 				  __const__ void *addr)
 {
 	__const__ unsigned char	*tmp = (__const__ unsigned char *) addr;
 	return (tmp[nr >> 3] >> (nr & 7)) & 1;
 }
 static inline void __set_bit_le(int nr, void *addr)
 {
 	__set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline void __clear_bit_le(int nr, void *addr)
 {
 	__clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline int test_and_set_bit_le(int nr, void *addr)
 {
 	return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline int test_and_clear_bit_le(int nr, void *addr)
 {
 	return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline int __test_and_set_bit_le(int nr, void *addr)
 {
 	return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 static inline int __test_and_clear_bit_le(int nr, void *addr)
 {
 	return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
 }
 #define find_first_zero_bit_le(addr, size) \
 	find_next_zero_bit_le((addr), (size), 0)
 unsigned long find_next_zero_bit_le(const void *addr,
 				    unsigned long size, unsigned long offset);
 unsigned long find_next_bit_le(const void *addr,
 				    unsigned long size, unsigned long offset);
 /* Bitmap functions for the ext2 filesystem */
 #define ext2_set_bit_atomic(lock, nr, addr) \
 	test_and_set_bit_le((nr), (unsigned long*)addr)
 #define ext2_clear_bit_atomic(lock, nr, addr) \
 	test_and_clear_bit_le((nr), (unsigned long*)addr)
-/* Bitmap functions for the minix filesystem.  */
-#define minix_test_and_set_bit(nr,addr) \
-	__test_and_set_bit_le(nr, (unsigned long *)addr)
-#define minix_set_bit(nr,addr) \
-	__set_bit_le(nr, (unsigned long *)addr)
-#define minix_test_and_clear_bit(nr,addr) \
-	__test_and_clear_bit_le(nr, (unsigned long *)addr)
-#define minix_test_bit(nr,addr) \
-	test_bit_le(nr, (unsigned long *)addr)
-#define minix_find_first_zero_bit(addr,size) \
-	find_first_zero_bit_le((unsigned long *)addr, size)
 #include <asm-generic/bitops/sched.h>
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_BITOPS_H */

arch/s390/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _S390_BITOPS_H
 #define _S390_BITOPS_H
 /*
  *  include/asm-s390/bitops.h
  *
  *  S390 version
  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/bitops.h"
  *    Copyright (C) 1992, Linus Torvalds
  *
  */
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 /*
  * 32 bit bitops format:
  * bit 0 is the LSB of *addr; bit 31 is the MSB of *addr;
  * bit 32 is the LSB of *(addr+4). That combined with the
  * big endian byte order on S390 give the following bit
  * order in memory:
  *    1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 \
  *    0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
  * after that follows the next long with bit numbers
  *    3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
  *    2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
  * The reason for this bit ordering is the fact that
  * in the architecture independent code bits operations
  * of the form "flags |= (1 << bitnr)" are used INTERMIXED
  * with operation of the form "set_bit(bitnr, flags)".
  *
  * 64 bit bitops format:
  * bit 0 is the LSB of *addr; bit 63 is the MSB of *addr;
  * bit 64 is the LSB of *(addr+8). That combined with the
  * big endian byte order on S390 give the following bit
  * order in memory:
  *    3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
  *    2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
  *    1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10
  *    0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
  * after that follows the next long with bit numbers
  *    7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70
  *    6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60
  *    5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50
  *    4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40
  * The reason for this bit ordering is the fact that
  * in the architecture independent code bits operations
  * of the form "flags |= (1 << bitnr)" are used INTERMIXED
  * with operation of the form "set_bit(bitnr, flags)".
  */
 /* bitmap tables from arch/s390/kernel/bitmap.c */
 extern const char _oi_bitmap[];
 extern const char _ni_bitmap[];
 extern const char _zb_findmap[];
 extern const char _sb_findmap[];
 #ifndef __s390x__
 #define __BITOPS_ALIGN		3
 #define __BITOPS_WORDSIZE	32
 #define __BITOPS_OR		"or"
 #define __BITOPS_AND		"nr"
 #define __BITOPS_XOR		"xr"
 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string)	\
 	asm volatile(						\
 		"	l	%0,%2\n"			\
 		"0:	lr	%1,%0\n"			\
 		__op_string "	%1,%3\n"			\
 		"	cs	%0,%1,%2\n"			\
 		"	jl	0b"				\
 		: "=&d" (__old), "=&d" (__new),			\
 		  "=Q" (*(unsigned long *) __addr)		\
 		: "d" (__val), "Q" (*(unsigned long *) __addr)	\
 		: "cc");
 #else /* __s390x__ */
 #define __BITOPS_ALIGN		7
 #define __BITOPS_WORDSIZE	64
 #define __BITOPS_OR		"ogr"
 #define __BITOPS_AND		"ngr"
 #define __BITOPS_XOR		"xgr"
 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string)	\
 	asm volatile(						\
 		"	lg	%0,%2\n"			\
 		"0:	lgr	%1,%0\n"			\
 		__op_string "	%1,%3\n"			\
 		"	csg	%0,%1,%2\n"			\
 		"	jl	0b"				\
 		: "=&d" (__old), "=&d" (__new),			\
 		  "=Q" (*(unsigned long *) __addr)		\
 		: "d" (__val), "Q" (*(unsigned long *) __addr)	\
 		: "cc");
 #endif /* __s390x__ */
 #define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
 #define __BITOPS_BARRIER() asm volatile("" : : : "memory")
 #ifdef CONFIG_SMP
 /*
  * SMP safe set_bit routine based on compare and swap (CS)
  */
 static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr, old, new, mask;
 	addr = (unsigned long) ptr;
 	/* calculate address for CS */
 	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
 	/* make OR mask */
 	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
 	/* Do the atomic update. */
 	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
 }
 /*
  * SMP safe clear_bit routine based on compare and swap (CS)
  */
 static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr, old, new, mask;
 	addr = (unsigned long) ptr;
 	/* calculate address for CS */
 	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
 	/* make AND mask */
 	mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
 	/* Do the atomic update. */
 	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
 }
 /*
  * SMP safe change_bit routine based on compare and swap (CS)
  */
 static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr, old, new, mask;
 	addr = (unsigned long) ptr;
 	/* calculate address for CS */
 	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
 	/* make XOR mask */
 	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
 	/* Do the atomic update. */
 	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
 }
 /*
  * SMP safe test_and_set_bit routine based on compare and swap (CS)
  */
 static inline int
 test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr, old, new, mask;
 	addr = (unsigned long) ptr;
 	/* calculate address for CS */
 	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
 	/* make OR/test mask */
 	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
 	/* Do the atomic update. */
 	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
 	__BITOPS_BARRIER();
 	return (old & mask) != 0;
 }
 /*
  * SMP safe test_and_clear_bit routine based on compare and swap (CS)
  */
 static inline int
 test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr, old, new, mask;
 	addr = (unsigned long) ptr;
 	/* calculate address for CS */
 	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
 	/* make AND/test mask */
 	mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
 	/* Do the atomic update. */
 	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
 	__BITOPS_BARRIER();
 	return (old ^ new) != 0;
 }
 /*
  * SMP safe test_and_change_bit routine based on compare and swap (CS)
  */
 static inline int
 test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
 {
         unsigned long addr, old, new, mask;
 	addr = (unsigned long) ptr;
 	/* calculate address for CS */
 	addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
 	/* make XOR/test mask */
 	mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
 	/* Do the atomic update. */
 	__BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
 	__BITOPS_BARRIER();
 	return (old & mask) != 0;
 }
 #endif /* CONFIG_SMP */
 /*
  * fast, non-SMP set_bit routine
  */
 static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	asm volatile(
 		"	oc	%O0(1,%R0),%1"
 		: "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" );
 }
 static inline void
 __constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	*(unsigned char *) addr |= 1 << (nr & 7);
 }
 #define set_bit_simple(nr,addr) \
 (__builtin_constant_p((nr)) ? \
  __constant_set_bit((nr),(addr)) : \
  __set_bit((nr),(addr)) )
 /*
  * fast, non-SMP clear_bit routine
  */
 static inline void
 __clear_bit(unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	asm volatile(
 		"	nc	%O0(1,%R0),%1"
 		: "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) : "cc" );
 }
 static inline void
 __constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	*(unsigned char *) addr &= ~(1 << (nr & 7));
 }
 #define clear_bit_simple(nr,addr) \
 (__builtin_constant_p((nr)) ? \
  __constant_clear_bit((nr),(addr)) : \
  __clear_bit((nr),(addr)) )
 /*
  * fast, non-SMP change_bit routine
  */
 static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	asm volatile(
 		"	xc	%O0(1,%R0),%1"
 		: "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" );
 }
 static inline void
 __constant_change_bit(const unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	*(unsigned char *) addr ^= 1 << (nr & 7);
 }
 #define change_bit_simple(nr,addr) \
 (__builtin_constant_p((nr)) ? \
  __constant_change_bit((nr),(addr)) : \
  __change_bit((nr),(addr)) )
 /*
  * fast, non-SMP test_and_set_bit routine
  */
 static inline int
 test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	unsigned char ch;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	ch = *(unsigned char *) addr;
 	asm volatile(
 		"	oc	%O0(1,%R0),%1"
 		: "=Q" (*(char *) addr)	: "Q" (_oi_bitmap[nr & 7])
 		: "cc", "memory");
 	return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_set_bit(X,Y)		test_and_set_bit_simple(X,Y)
 /*
  * fast, non-SMP test_and_clear_bit routine
  */
 static inline int
 test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	unsigned char ch;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	ch = *(unsigned char *) addr;
 	asm volatile(
 		"	nc	%O0(1,%R0),%1"
 		: "=Q" (*(char *) addr)	: "Q" (_ni_bitmap[nr & 7])
 		: "cc", "memory");
 	return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_clear_bit(X,Y)	test_and_clear_bit_simple(X,Y)
 /*
  * fast, non-SMP test_and_change_bit routine
  */
 static inline int
 test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	unsigned char ch;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	ch = *(unsigned char *) addr;
 	asm volatile(
 		"	xc	%O0(1,%R0),%1"
 		: "=Q" (*(char *) addr)	: "Q" (_oi_bitmap[nr & 7])
 		: "cc", "memory");
 	return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_change_bit(X,Y)	test_and_change_bit_simple(X,Y)
 #ifdef CONFIG_SMP
 #define set_bit             set_bit_cs
 #define clear_bit           clear_bit_cs
 #define change_bit          change_bit_cs
 #define test_and_set_bit    test_and_set_bit_cs
 #define test_and_clear_bit  test_and_clear_bit_cs
 #define test_and_change_bit test_and_change_bit_cs
 #else
 #define set_bit             set_bit_simple
 #define clear_bit           clear_bit_simple
 #define change_bit          change_bit_simple
 #define test_and_set_bit    test_and_set_bit_simple
 #define test_and_clear_bit  test_and_clear_bit_simple
 #define test_and_change_bit test_and_change_bit_simple
 #endif
 /*
  * This routine doesn't need to be atomic.
  */
 static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr)
 {
 	unsigned long addr;
 	unsigned char ch;
 	addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
 	ch = *(volatile unsigned char *) addr;
 	return (ch >> (nr & 7)) & 1;
 }
 static inline int
 __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
     return (((volatile char *) addr)
 	    [(nr^(__BITOPS_WORDSIZE-8))>>3] & (1<<(nr&7))) != 0;
 }
 #define test_bit(nr,addr) \
 (__builtin_constant_p((nr)) ? \
  __constant_test_bit((nr),(addr)) : \
  __test_bit((nr),(addr)) )
 /*
  * Optimized find bit helper functions.
  */
 /**
  * __ffz_word_loop - find byte offset of first long != -1UL
  * @addr: pointer to array of unsigned long
  * @size: size of the array in bits
  */
 static inline unsigned long __ffz_word_loop(const unsigned long *addr,
 					    unsigned long size)
 {
 	typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
 	unsigned long bytes = 0;
 	asm volatile(
 #ifndef __s390x__
 		"	ahi	%1,-1\n"
 		"	sra	%1,5\n"
 		"	jz	1f\n"
 		"0:	c	%2,0(%0,%3)\n"
 		"	jne	1f\n"
 		"	la	%0,4(%0)\n"
 		"	brct	%1,0b\n"
 		"1:\n"
 #else
 		"	aghi	%1,-1\n"
 		"	srag	%1,%1,6\n"
 		"	jz	1f\n"
 		"0:	cg	%2,0(%0,%3)\n"
 		"	jne	1f\n"
 		"	la	%0,8(%0)\n"
 		"	brct	%1,0b\n"
 		"1:\n"
 #endif
 		: "+&a" (bytes), "+&d" (size)
 		: "d" (-1UL), "a" (addr), "m" (*(addrtype *) addr)
 		: "cc" );
 	return bytes;
 }
 /**
  * __ffs_word_loop - find byte offset of first long != 0UL
  * @addr: pointer to array of unsigned long
  * @size: size of the array in bits
  */
 static inline unsigned long __ffs_word_loop(const unsigned long *addr,
 					    unsigned long size)
 {
 	typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
 	unsigned long bytes = 0;
 	asm volatile(
 #ifndef __s390x__
 		"	ahi	%1,-1\n"
 		"	sra	%1,5\n"
 		"	jz	1f\n"
 		"0:	c	%2,0(%0,%3)\n"
 		"	jne	1f\n"
 		"	la	%0,4(%0)\n"
 		"	brct	%1,0b\n"
 		"1:\n"
 #else
 		"	aghi	%1,-1\n"
 		"	srag	%1,%1,6\n"
 		"	jz	1f\n"
 		"0:	cg	%2,0(%0,%3)\n"
 		"	jne	1f\n"
 		"	la	%0,8(%0)\n"
 		"	brct	%1,0b\n"
 		"1:\n"
 #endif
 		: "+&a" (bytes), "+&a" (size)
 		: "d" (0UL), "a" (addr), "m" (*(addrtype *) addr)
 		: "cc" );
 	return bytes;
 }
 /**
  * __ffz_word - add number of the first unset bit
  * @nr: base value the bit number is added to
  * @word: the word that is searched for unset bits
  */
 static inline unsigned long __ffz_word(unsigned long nr, unsigned long word)
 {
 #ifdef __s390x__
 	if ((word & 0xffffffff) == 0xffffffff) {
 		word >>= 32;
 		nr += 32;
 	}
 #endif
 	if ((word & 0xffff) == 0xffff) {
 		word >>= 16;
 		nr += 16;
 	}
 	if ((word & 0xff) == 0xff) {
 		word >>= 8;
 		nr += 8;
 	}
 	return nr + _zb_findmap[(unsigned char) word];
 }
 /**
  * __ffs_word - add number of the first set bit
  * @nr: base value the bit number is added to
  * @word: the word that is searched for set bits
  */
 static inline unsigned long __ffs_word(unsigned long nr, unsigned long word)
 {
 #ifdef __s390x__
 	if ((word & 0xffffffff) == 0) {
 		word >>= 32;
 		nr += 32;
 	}
 #endif
 	if ((word & 0xffff) == 0) {
 		word >>= 16;
 		nr += 16;
 	}
 	if ((word & 0xff) == 0) {
 		word >>= 8;
 		nr += 8;
 	}
 	return nr + _sb_findmap[(unsigned char) word];
 }
 /**
  * __load_ulong_be - load big endian unsigned long
  * @p: pointer to array of unsigned long
  * @offset: byte offset of source value in the array
  */
 static inline unsigned long __load_ulong_be(const unsigned long *p,
 					    unsigned long offset)
 {
 	p = (unsigned long *)((unsigned long) p + offset);
 	return *p;
 }
 /**
  * __load_ulong_le - load little endian unsigned long
  * @p: pointer to array of unsigned long
  * @offset: byte offset of source value in the array
  */
 static inline unsigned long __load_ulong_le(const unsigned long *p,
 					    unsigned long offset)
 {
 	unsigned long word;
 	p = (unsigned long *)((unsigned long) p + offset);
 #ifndef __s390x__
 	asm volatile(
 		"	ic	%0,%O1(%R1)\n"
 		"	icm	%0,2,%O1+1(%R1)\n"
 		"	icm	%0,4,%O1+2(%R1)\n"
 		"	icm	%0,8,%O1+3(%R1)"
 		: "=&d" (word) : "Q" (*p) : "cc");
 #else
 	asm volatile(
 		"	lrvg	%0,%1"
 		: "=d" (word) : "m" (*p) );
 #endif
 	return word;
 }
 /*
  * The various find bit functions.
  */
 /*
  * ffz - find first zero in word.
  * @word: The word to search
  *
  * Undefined if no zero exists, so code should check against ~0UL first.
  */
 static inline unsigned long ffz(unsigned long word)
 {
 	return __ffz_word(0, word);
 }
 /**
  * __ffs - find first bit in word.
  * @word: The word to search
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
 static inline unsigned long __ffs (unsigned long word)
 {
 	return __ffs_word(0, word);
 }
 /**
  * ffs - find first bit set
  * @x: the word to search
  *
  * This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
 static inline int ffs(int x)
 {
 	if (!x)
 		return 0;
 	return __ffs_word(1, x);
 }
 /**
  * find_first_zero_bit - find the first zero bit in a memory region
  * @addr: The address to start the search at
  * @size: The maximum size to search
  *
  * Returns the bit-number of the first zero bit, not the number of the byte
  * containing a bit.
  */
 static inline unsigned long find_first_zero_bit(const unsigned long *addr,
 						unsigned long size)
 {
 	unsigned long bytes, bits;
         if (!size)
                 return 0;
 	bytes = __ffz_word_loop(addr, size);
 	bits = __ffz_word(bytes*8, __load_ulong_be(addr, bytes));
 	return (bits < size) ? bits : size;
 }
 /**
  * find_first_bit - find the first set bit in a memory region
  * @addr: The address to start the search at
  * @size: The maximum size to search
  *
  * Returns the bit-number of the first set bit, not the number of the byte
  * containing a bit.
  */
 static inline unsigned long find_first_bit(const unsigned long * addr,
 					   unsigned long size)
 {
 	unsigned long bytes, bits;
         if (!size)
                 return 0;
 	bytes = __ffs_word_loop(addr, size);
 	bits = __ffs_word(bytes*8, __load_ulong_be(addr, bytes));
 	return (bits < size) ? bits : size;
 }
 /**
  * find_next_zero_bit - find the first zero bit in a memory region
  * @addr: The address to base the search on
  * @offset: The bitnumber to start searching at
  * @size: The maximum size to search
  */
 static inline int find_next_zero_bit (const unsigned long * addr,
 				      unsigned long size,
 				      unsigned long offset)
 {
         const unsigned long *p;
 	unsigned long bit, set;
 	if (offset >= size)
 		return size;
 	bit = offset & (__BITOPS_WORDSIZE - 1);
 	offset -= bit;
 	size -= offset;
 	p = addr + offset / __BITOPS_WORDSIZE;
 	if (bit) {
 		/*
 		 * __ffz_word returns __BITOPS_WORDSIZE
 		 * if no zero bit is present in the word.
 		 */
 		set = __ffz_word(bit, *p >> bit);
 		if (set >= size)
 			return size + offset;
 		if (set < __BITOPS_WORDSIZE)
 			return set + offset;
 		offset += __BITOPS_WORDSIZE;
 		size -= __BITOPS_WORDSIZE;
 		p++;
 	}
 	return offset + find_first_zero_bit(p, size);
 }
 /**
  * find_next_bit - find the first set bit in a memory region
  * @addr: The address to base the search on
  * @offset: The bitnumber to start searching at
  * @size: The maximum size to search
  */
 static inline int find_next_bit (const unsigned long * addr,
 				 unsigned long size,
 				 unsigned long offset)
 {
         const unsigned long *p;
 	unsigned long bit, set;
 	if (offset >= size)
 		return size;
 	bit = offset & (__BITOPS_WORDSIZE - 1);
 	offset -= bit;
 	size -= offset;
 	p = addr + offset / __BITOPS_WORDSIZE;
 	if (bit) {
 		/*
 		 * __ffs_word returns __BITOPS_WORDSIZE
 		 * if no one bit is present in the word.
 		 */
 		set = __ffs_word(0, *p & (~0UL << bit));
 		if (set >= size)
 			return size + offset;
 		if (set < __BITOPS_WORDSIZE)
 			return set + offset;
 		offset += __BITOPS_WORDSIZE;
 		size -= __BITOPS_WORDSIZE;
 		p++;
 	}
 	return offset + find_first_bit(p, size);
 }
 /*
  * Every architecture must define this function. It's the fastest
  * way of searching a 140-bit bitmap where the first 100 bits are
  * unlikely to be set. It's guaranteed that at least one of the 140
  * bits is cleared.
  */
 static inline int sched_find_first_bit(unsigned long *b)
 {
 	return find_first_bit(b, 140);
 }
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 /*
  * ATTENTION: intel byte ordering convention for ext2 and minix !!
  * bit 0 is the LSB of addr; bit 31 is the MSB of addr;
  * bit 32 is the LSB of (addr+4).
  * That combined with the little endian byte order of Intel gives the
  * following bit order in memory:
  *    07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 \
  *    23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
  */
 static inline void __set_bit_le(unsigned long nr, void *addr)
 {
 	__set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline void __clear_bit_le(unsigned long nr, void *addr)
 {
 	__clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline int __test_and_set_bit_le(unsigned long nr, void *addr)
 {
 	return __test_and_set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline int test_and_set_bit_le(unsigned long nr, void *addr)
 {
 	return test_and_set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline int __test_and_clear_bit_le(unsigned long nr, void *addr)
 {
 	return __test_and_clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline int test_and_clear_bit_le(unsigned long nr, void *addr)
 {
 	return test_and_clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline int test_bit_le(unsigned long nr, const void *addr)
 {
 	return test_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
 }
 static inline int find_first_zero_bit_le(void *vaddr, unsigned int size)
 {
 	unsigned long bytes, bits;
         if (!size)
                 return 0;
 	bytes = __ffz_word_loop(vaddr, size);
 	bits = __ffz_word(bytes*8, __load_ulong_le(vaddr, bytes));
 	return (bits < size) ? bits : size;
 }
 static inline int find_next_zero_bit_le(void *vaddr, unsigned long size,
 					  unsigned long offset)
 {
         unsigned long *addr = vaddr, *p;
 	unsigned long bit, set;
         if (offset >= size)
                 return size;
 	bit = offset & (__BITOPS_WORDSIZE - 1);
 	offset -= bit;
 	size -= offset;
 	p = addr + offset / __BITOPS_WORDSIZE;
         if (bit) {
 		/*
 		 * s390 version of ffz returns __BITOPS_WORDSIZE
 		 * if no zero bit is present in the word.
 		 */
 		set = __ffz_word(bit, __load_ulong_le(p, 0) >> bit);
 		if (set >= size)
 			return size + offset;
 		if (set < __BITOPS_WORDSIZE)
 			return set + offset;
 		offset += __BITOPS_WORDSIZE;
 		size -= __BITOPS_WORDSIZE;
 		p++;
         }
 	return offset + find_first_zero_bit_le(p, size);
 }
 static inline unsigned long find_first_bit_le(void *vaddr, unsigned long size)
 {
 	unsigned long bytes, bits;
 	if (!size)
 		return 0;
 	bytes = __ffs_word_loop(vaddr, size);
 	bits = __ffs_word(bytes*8, __load_ulong_le(vaddr, bytes));
 	return (bits < size) ? bits : size;
 }
 static inline int find_next_bit_le(void *vaddr, unsigned long size,
 				     unsigned long offset)
 {
 	unsigned long *addr = vaddr, *p;
 	unsigned long bit, set;
 	if (offset >= size)
 		return size;
 	bit = offset & (__BITOPS_WORDSIZE - 1);
 	offset -= bit;
 	size -= offset;
 	p = addr + offset / __BITOPS_WORDSIZE;
 	if (bit) {
 		/*
 		 * s390 version of ffz returns __BITOPS_WORDSIZE
 		 * if no zero bit is present in the word.
 		 */
 		set = __ffs_word(0, __load_ulong_le(p, 0) & (~0UL << bit));
 		if (set >= size)
 			return size + offset;
 		if (set < __BITOPS_WORDSIZE)
 			return set + offset;
 		offset += __BITOPS_WORDSIZE;
 		size -= __BITOPS_WORDSIZE;
 		p++;
 	}
 	return offset + find_first_bit_le(p, size);
 }
 #define ext2_set_bit_atomic(lock, nr, addr)	\
 	test_and_set_bit_le(nr, addr)
 #define ext2_clear_bit_atomic(lock, nr, addr)	\
 	test_and_clear_bit_le(nr, addr)
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* _S390_BITOPS_H */

arch/sh/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef __ASM_SH_BITOPS_H
 #define __ASM_SH_BITOPS_H
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm/system.h>
 /* For __swab32 */
 #include <asm/byteorder.h>
 #ifdef CONFIG_GUSA_RB
 #include <asm/bitops-grb.h>
 #elif defined(CONFIG_CPU_SH2A)
 #include <asm-generic/bitops/atomic.h>
 #include <asm/bitops-op32.h>
 #elif defined(CONFIG_CPU_SH4A)
 #include <asm/bitops-llsc.h>
 #else
 #include <asm-generic/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 #endif
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
 #ifdef CONFIG_SUPERH32
 static inline unsigned long ffz(unsigned long word)
 {
 	unsigned long result;
 	__asm__("1:\n\t"
 		"shlr	%1\n\t"
 		"bt/s	1b\n\t"
 		" add	#1, %0"
 		: "=r" (result), "=r" (word)
 		: "0" (~0L), "1" (word)
 		: "t");
 	return result;
 }
 /**
  * __ffs - find first bit in word.
  * @word: The word to search
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
 static inline unsigned long __ffs(unsigned long word)
 {
 	unsigned long result;
 	__asm__("1:\n\t"
 		"shlr	%1\n\t"
 		"bf/s	1b\n\t"
 		" add	#1, %0"
 		: "=r" (result), "=r" (word)
 		: "0" (~0L), "1" (word)
 		: "t");
 	return result;
 }
 #else
 static inline unsigned long ffz(unsigned long word)
 {
 	unsigned long result, __d2, __d3;
         __asm__("gettr  tr0, %2\n\t"
                 "pta    $+32, tr0\n\t"
                 "andi   %1, 1, %3\n\t"
                 "beq    %3, r63, tr0\n\t"
                 "pta    $+4, tr0\n"
                 "0:\n\t"
                 "shlri.l        %1, 1, %1\n\t"
                 "addi   %0, 1, %0\n\t"
                 "andi   %1, 1, %3\n\t"
                 "beqi   %3, 1, tr0\n"
                 "1:\n\t"
                 "ptabs  %2, tr0\n\t"
                 : "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
                 : "0" (0L), "1" (word));
 	return result;
 }
 #include <asm-generic/bitops/__ffs.h>
 #endif
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #endif /* __KERNEL__ */
 #endif /* __ASM_SH_BITOPS_H */

arch/sparc/include/asm/bitops_32.h

Diff comments View file @ 61f2e7b

 /*
  * bitops.h: Bit string operations on the Sparc.
  *
  * Copyright 1995 David S. Miller (davem@caip.rutgers.edu)
  * Copyright 1996 Eddie C. Dost   (ecd@skynet.be)
  * Copyright 2001 Anton Blanchard (anton@samba.org)
  */
 #ifndef _SPARC_BITOPS_H
 #define _SPARC_BITOPS_H
 #include <linux/compiler.h>
 #include <asm/byteorder.h>
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 extern unsigned long ___set_bit(unsigned long *addr, unsigned long mask);
 extern unsigned long ___clear_bit(unsigned long *addr, unsigned long mask);
 extern unsigned long ___change_bit(unsigned long *addr, unsigned long mask);
 /*
  * Set bit 'nr' in 32-bit quantity at address 'addr' where bit '0'
  * is in the highest of the four bytes and bit '31' is the high bit
  * within the first byte. Sparc is BIG-Endian. Unless noted otherwise
  * all bit-ops return 0 if bit was previously clear and != 0 otherwise.
  */
 static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *ADDR, mask;
 	ADDR = ((unsigned long *) addr) + (nr >> 5);
 	mask = 1 << (nr & 31);
 	return ___set_bit(ADDR, mask) != 0;
 }
 static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *ADDR, mask;
 	ADDR = ((unsigned long *) addr) + (nr >> 5);
 	mask = 1 << (nr & 31);
 	(void) ___set_bit(ADDR, mask);
 }
 static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *ADDR, mask;
 	ADDR = ((unsigned long *) addr) + (nr >> 5);
 	mask = 1 << (nr & 31);
 	return ___clear_bit(ADDR, mask) != 0;
 }
 static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *ADDR, mask;
 	ADDR = ((unsigned long *) addr) + (nr >> 5);
 	mask = 1 << (nr & 31);
 	(void) ___clear_bit(ADDR, mask);
 }
 static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *ADDR, mask;
 	ADDR = ((unsigned long *) addr) + (nr >> 5);
 	mask = 1 << (nr & 31);
 	return ___change_bit(ADDR, mask) != 0;
 }
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
 	unsigned long *ADDR, mask;
 	ADDR = ((unsigned long *) addr) + (nr >> 5);
 	mask = 1 << (nr & 31);
 	(void) ___change_bit(ADDR, mask);
 }
 #include <asm-generic/bitops/non-atomic.h>
 #define smp_mb__before_clear_bit()	do { } while(0)
 #define smp_mb__after_clear_bit()	do { } while(0)
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* defined(_SPARC_BITOPS_H) */

arch/sparc/include/asm/bitops_64.h

Diff comments View file @ 61f2e7b

 /*
  * bitops.h: Bit string operations on the V9.
  *
  * Copyright 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
  */
 #ifndef _SPARC64_BITOPS_H
 #define _SPARC64_BITOPS_H
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <asm/byteorder.h>
 extern int test_and_set_bit(unsigned long nr, volatile unsigned long *addr);
 extern int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr);
 extern int test_and_change_bit(unsigned long nr, volatile unsigned long *addr);
 extern void set_bit(unsigned long nr, volatile unsigned long *addr);
 extern void clear_bit(unsigned long nr, volatile unsigned long *addr);
 extern void change_bit(unsigned long nr, volatile unsigned long *addr);
 #include <asm-generic/bitops/non-atomic.h>
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/ffs.h>
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
 #ifdef ULTRA_HAS_POPULATION_COUNT
 static inline unsigned int __arch_hweight64(unsigned long w)
 {
 	unsigned int res;
 	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w));
 	return res;
 }
 static inline unsigned int __arch_hweight32(unsigned int w)
 {
 	unsigned int res;
 	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffffffff));
 	return res;
 }
 static inline unsigned int __arch_hweight16(unsigned int w)
 {
 	unsigned int res;
 	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xffff));
 	return res;
 }
 static inline unsigned int __arch_hweight8(unsigned int w)
 {
 	unsigned int res;
 	__asm__ ("popc %1,%0" : "=r" (res) : "r" (w & 0xff));
 	return res;
 }
 #else
 #include <asm-generic/bitops/arch_hweight.h>
 #endif
 #include <asm-generic/bitops/const_hweight.h>
 #include <asm-generic/bitops/lock.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/find.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/le.h>
 #define ext2_set_bit_atomic(lock,nr,addr) \
 	test_and_set_bit((nr) ^ 0x38,(unsigned long *)(addr))
 #define ext2_clear_bit_atomic(lock,nr,addr) \
 	test_and_clear_bit((nr) ^ 0x38,(unsigned long *)(addr))
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* defined(_SPARC64_BITOPS_H) */

arch/tile/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * Copyright 1992, Linus Torvalds.
  * Copyright 2010 Tilera Corporation. All Rights Reserved.
  *
  *   This program is free software; you can redistribute it and/or
  *   modify it under the terms of the GNU General Public License
  *   as published by the Free Software Foundation, version 2.
  *
  *   This program is distributed in the hope that it will be useful, but
  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  *   NON INFRINGEMENT.  See the GNU General Public License for
  *   more details.
  */
 #ifndef _ASM_TILE_BITOPS_H
 #define _ASM_TILE_BITOPS_H
 #include <linux/types.h>
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #ifdef __tilegx__
 #include <asm/bitops_64.h>
 #else
 #include <asm/bitops_32.h>
 #endif
 /**
  * __ffs - find first set bit in word
  * @word: The word to search
  *
  * Undefined if no set bit exists, so code should check against 0 first.
  */
 static inline unsigned long __ffs(unsigned long word)
 {
 	return __builtin_ctzl(word);
 }
 /**
  * ffz - find first zero bit in word
  * @word: The word to search
  *
  * Undefined if no zero exists, so code should check against ~0UL first.
  */
 static inline unsigned long ffz(unsigned long word)
 {
 	return __builtin_ctzl(~word);
 }
 /**
  * __fls - find last set bit in word
  * @word: The word to search
  *
  * Undefined if no set bit exists, so code should check against 0 first.
  */
 static inline unsigned long __fls(unsigned long word)
 {
 	return (sizeof(word) * 8) - 1 - __builtin_clzl(word);
 }
 /**
  * ffs - find first set bit in word
  * @x: the word to search
  *
  * This is defined the same way as the libc and compiler builtin ffs
  * routines, therefore differs in spirit from the other bitops.
  *
  * ffs(value) returns 0 if value is 0 or the position of the first
  * set bit if value is nonzero. The first (least significant) bit
  * is at position 1.
  */
 static inline int ffs(int x)
 {
 	return __builtin_ffs(x);
 }
 /**
  * fls - find last set bit in word
  * @x: the word to search
  *
  * This is defined in a similar way as the libc and compiler builtin
  * ffs, but returns the position of the most significant set bit.
  *
  * fls(value) returns 0 if value is 0 or the position of the last
  * set bit if value is nonzero. The last (most significant) bit is
  * at position 32.
  */
 static inline int fls(int x)
 {
 	return (sizeof(int) * 8) - __builtin_clz(x);
 }
 static inline int fls64(__u64 w)
 {
 	return (sizeof(__u64) * 8) - __builtin_clzll(w);
 }
 static inline unsigned int __arch_hweight32(unsigned int w)
 {
 	return __builtin_popcount(w);
 }
 static inline unsigned int __arch_hweight16(unsigned int w)
 {
 	return __builtin_popcount(w & 0xffff);
 }
 static inline unsigned int __arch_hweight8(unsigned int w)
 {
 	return __builtin_popcount(w & 0xff);
 }
 static inline unsigned long __arch_hweight64(__u64 w)
 {
 	return __builtin_popcountll(w);
 }
 #include <asm-generic/bitops/const_hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/le.h>
-#include <asm-generic/bitops/minix.h>
 #endif /* _ASM_TILE_BITOPS_H */

arch/x86/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef _ASM_X86_BITOPS_H
 #define _ASM_X86_BITOPS_H
 /*
  * Copyright 1992, Linus Torvalds.
  *
  * Note: inlines with more than a single statement should be marked
  * __always_inline to avoid problems with older gcc's inlining heuristics.
  */
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <linux/compiler.h>
 #include <asm/alternative.h>
 /*
  * These have to be done with inline assembly: that way the bit-setting
  * is guaranteed to be atomic. All bit operations return 0 if the bit
  * was cleared before the operation and != 0 if it was not.
  *
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
 /* Technically wrong, but this avoids compilation errors on some gcc
    versions. */
 #define BITOP_ADDR(x) "=m" (*(volatile long *) (x))
 #else
 #define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
 #endif
 #define ADDR				BITOP_ADDR(addr)
 /*
  * We do the locked ops that don't return the old value as
  * a mask operation on a byte.
  */
 #define IS_IMMEDIATE(nr)		(__builtin_constant_p(nr))
 #define CONST_MASK_ADDR(nr, addr)	BITOP_ADDR((void *)(addr) + ((nr)>>3))
 #define CONST_MASK(nr)			(1 << ((nr) & 7))
 /**
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * This function is atomic and may not be reordered.  See __set_bit()
  * if you do not require the atomic guarantees.
  *
  * Note: there are no guarantees that this function will not be reordered
  * on non x86 architectures, so if you are writing portable code,
  * make sure not to rely on its reordering guarantees.
  *
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static __always_inline void
 set_bit(unsigned int nr, volatile unsigned long *addr)
 {
 	if (IS_IMMEDIATE(nr)) {
 		asm volatile(LOCK_PREFIX "orb %1,%0"
 			: CONST_MASK_ADDR(nr, addr)
 			: "iq" ((u8)CONST_MASK(nr))
 			: "memory");
 	} else {
 		asm volatile(LOCK_PREFIX "bts %1,%0"
 			: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
 	}
 }
 /**
  * __set_bit - Set a bit in memory
  * @nr: the bit to set
  * @addr: the address to start counting from
  *
  * Unlike set_bit(), this function is non-atomic and may be reordered.
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
 static inline void __set_bit(int nr, volatile unsigned long *addr)
 {
 	asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
 }
 /**
  * clear_bit - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and may not be reordered.  However, it does
  * not contain a memory barrier, so if it is used for locking purposes,
  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  * in order to ensure changes are visible on other processors.
  */
 static __always_inline void
 clear_bit(int nr, volatile unsigned long *addr)
 {
 	if (IS_IMMEDIATE(nr)) {
 		asm volatile(LOCK_PREFIX "andb %1,%0"
 			: CONST_MASK_ADDR(nr, addr)
 			: "iq" ((u8)~CONST_MASK(nr)));
 	} else {
 		asm volatile(LOCK_PREFIX "btr %1,%0"
 			: BITOP_ADDR(addr)
 			: "Ir" (nr));
 	}
 }
 /*
  * clear_bit_unlock - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * clear_bit() is atomic and implies release semantics before the memory
  * operation. It can be used for an unlock.
  */
 static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
 {
 	barrier();
 	clear_bit(nr, addr);
 }
 static inline void __clear_bit(int nr, volatile unsigned long *addr)
 {
 	asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
 }
 /*
  * __clear_bit_unlock - Clears a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
  *
  * __clear_bit() is non-atomic and implies release semantics before the memory
  * operation. It can be used for an unlock if no other CPUs can concurrently
  * modify other bits in the word.
  *
  * No memory barrier is required here, because x86 cannot reorder stores past
  * older loads. Same principle as spin_unlock.
  */
 static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
 {
 	barrier();
 	__clear_bit(nr, addr);
 }
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 /**
  * __change_bit - Toggle a bit in memory
  * @nr: the bit to change
  * @addr: the address to start counting from
  *
  * Unlike change_bit(), this function is non-atomic and may be reordered.
  * If it's called on the same region of memory simultaneously, the effect
  * may be that only one operation succeeds.
  */
 static inline void __change_bit(int nr, volatile unsigned long *addr)
 {
 	asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
 }
 /**
  * change_bit - Toggle a bit in memory
  * @nr: Bit to change
  * @addr: Address to start counting from
  *
  * change_bit() is atomic and may not be reordered.
  * Note that @nr may be almost arbitrarily large; this function is not
  * restricted to acting on a single-word quantity.
  */
 static inline void change_bit(int nr, volatile unsigned long *addr)
 {
 	if (IS_IMMEDIATE(nr)) {
 		asm volatile(LOCK_PREFIX "xorb %1,%0"
 			: CONST_MASK_ADDR(nr, addr)
 			: "iq" ((u8)CONST_MASK(nr)));
 	} else {
 		asm volatile(LOCK_PREFIX "btc %1,%0"
 			: BITOP_ADDR(addr)
 			: "Ir" (nr));
 	}
 }
 /**
  * test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
 {
 	int oldbit;
 	asm volatile(LOCK_PREFIX "bts %2,%1\n\t"
 		     "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
 	return oldbit;
 }
 /**
  * test_and_set_bit_lock - Set a bit and return its old value for lock
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This is the same as test_and_set_bit on x86.
  */
 static __always_inline int
 test_and_set_bit_lock(int nr, volatile unsigned long *addr)
 {
 	return test_and_set_bit(nr, addr);
 }
 /**
  * __test_and_set_bit - Set a bit and return its old value
  * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
 static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
 {
 	int oldbit;
 	asm("bts %2,%1\n\t"
 	    "sbb %0,%0"
 	    : "=r" (oldbit), ADDR
 	    : "Ir" (nr));
 	return oldbit;
 }
 /**
  * test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 	int oldbit;
 	asm volatile(LOCK_PREFIX "btr %2,%1\n\t"
 		     "sbb %0,%0"
 		     : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
 	return oldbit;
 }
 /**
  * __test_and_clear_bit - Clear a bit and return its old value
  * @nr: Bit to clear
  * @addr: Address to count from
  *
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
 static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
 	int oldbit;
 	asm volatile("btr %2,%1\n\t"
 		     "sbb %0,%0"
 		     : "=r" (oldbit), ADDR
 		     : "Ir" (nr));
 	return oldbit;
 }
 /* WARNING: non atomic and it can be reordered! */
 static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
 {
 	int oldbit;
 	asm volatile("btc %2,%1\n\t"
 		     "sbb %0,%0"
 		     : "=r" (oldbit), ADDR
 		     : "Ir" (nr) : "memory");
 	return oldbit;
 }
 /**
  * test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
  * @addr: Address to count from
  *
  * This operation is atomic and cannot be reordered.
  * It also implies a memory barrier.
  */
 static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 {
 	int oldbit;
 	asm volatile(LOCK_PREFIX "btc %2,%1\n\t"
 		     "sbb %0,%0"
 		     : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
 	return oldbit;
 }
 static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
 {
 	return ((1UL << (nr % BITS_PER_LONG)) &
 		(addr[nr / BITS_PER_LONG])) != 0;
 }
 static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
 {
 	int oldbit;
 	asm volatile("bt %2,%1\n\t"
 		     "sbb %0,%0"
 		     : "=r" (oldbit)
 		     : "m" (*(unsigned long *)addr), "Ir" (nr));
 	return oldbit;
 }
 #if 0 /* Fool kernel-doc since it doesn't do macros yet */
 /**
  * test_bit - Determine whether a bit is set
  * @nr: bit number to test
  * @addr: Address to start counting from
  */
 static int test_bit(int nr, const volatile unsigned long *addr);
 #endif
 #define test_bit(nr, addr)			\
 	(__builtin_constant_p((nr))		\
 	 ? constant_test_bit((nr), (addr))	\
 	 : variable_test_bit((nr), (addr)))
 /**
  * __ffs - find first set bit in word
  * @word: The word to search
  *
  * Undefined if no bit exists, so code should check against 0 first.
  */
 static inline unsigned long __ffs(unsigned long word)
 {
 	asm("bsf %1,%0"
 		: "=r" (word)
 		: "rm" (word));
 	return word;
 }
 /**
  * ffz - find first zero bit in word
  * @word: The word to search
  *
  * Undefined if no zero exists, so code should check against ~0UL first.
  */
 static inline unsigned long ffz(unsigned long word)
 {
 	asm("bsf %1,%0"
 		: "=r" (word)
 		: "r" (~word));
 	return word;
 }
 /*
  * __fls: find last set bit in word
  * @word: The word to search
  *
  * Undefined if no set bit exists, so code should check against 0 first.
  */
 static inline unsigned long __fls(unsigned long word)
 {
 	asm("bsr %1,%0"
 	    : "=r" (word)
 	    : "rm" (word));
 	return word;
 }
 #ifdef __KERNEL__
 /**
  * ffs - find first set bit in word
  * @x: the word to search
  *
  * This is defined the same way as the libc and compiler builtin ffs
  * routines, therefore differs in spirit from the other bitops.
  *
  * ffs(value) returns 0 if value is 0 or the position of the first
  * set bit if value is nonzero. The first (least significant) bit
  * is at position 1.
  */
 static inline int ffs(int x)
 {
 	int r;
 #ifdef CONFIG_X86_CMOV
 	asm("bsfl %1,%0\n\t"
 	    "cmovzl %2,%0"
 	    : "=r" (r) : "rm" (x), "r" (-1));
 #else
 	asm("bsfl %1,%0\n\t"
 	    "jnz 1f\n\t"
 	    "movl $-1,%0\n"
 	    "1:" : "=r" (r) : "rm" (x));
 #endif
 	return r + 1;
 }
 /**
  * fls - find last set bit in word
  * @x: the word to search
  *
  * This is defined in a similar way as the libc and compiler builtin
  * ffs, but returns the position of the most significant set bit.
  *
  * fls(value) returns 0 if value is 0 or the position of the last
  * set bit if value is nonzero. The last (most significant) bit is
  * at position 32.
  */
 static inline int fls(int x)
 {
 	int r;
 #ifdef CONFIG_X86_CMOV
 	asm("bsrl %1,%0\n\t"
 	    "cmovzl %2,%0"
 	    : "=&r" (r) : "rm" (x), "rm" (-1));
 #else
 	asm("bsrl %1,%0\n\t"
 	    "jnz 1f\n\t"
 	    "movl $-1,%0\n"
 	    "1:" : "=r" (r) : "rm" (x));
 #endif
 	return r + 1;
 }
 #endif /* __KERNEL__ */
 #undef ADDR
 #ifdef __KERNEL__
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/sched.h>
 #define ARCH_HAS_FAST_MULTIPLIER 1
 #include <asm/arch_hweight.h>
 #include <asm-generic/bitops/const_hweight.h>
 #endif /* __KERNEL__ */
 #include <asm-generic/bitops/fls64.h>
 #ifdef __KERNEL__
 #include <asm-generic/bitops/le.h>
 #define ext2_set_bit_atomic(lock, nr, addr)			\
 	test_and_set_bit((nr), (unsigned long *)(addr))
 #define ext2_clear_bit_atomic(lock, nr, addr)			\
 	test_and_clear_bit((nr), (unsigned long *)(addr))
-#include <asm-generic/bitops/minix.h>
 #endif /* __KERNEL__ */
 #endif /* _ASM_X86_BITOPS_H */

arch/xtensa/include/asm/bitops.h

Diff comments View file @ 61f2e7b

 /*
  * include/asm-xtensa/bitops.h
  *
  * Atomic operations that C can't guarantee us.Useful for resource counting etc.
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 2001 - 2007 Tensilica Inc.
  */
 #ifndef _XTENSA_BITOPS_H
 #define _XTENSA_BITOPS_H
 #ifdef __KERNEL__
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm/processor.h>
 #include <asm/byteorder.h>
 #include <asm/system.h>
 #ifdef CONFIG_SMP
 # error SMP not supported on this architecture
 #endif
 #define smp_mb__before_clear_bit()	barrier()
 #define smp_mb__after_clear_bit()	barrier()
 #include <asm-generic/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 #if XCHAL_HAVE_NSA
 static inline unsigned long __cntlz (unsigned long x)
 {
 	int lz;
 	asm ("nsau %0, %1" : "=r" (lz) : "r" (x));
 	return lz;
 }
 /*
  * ffz: Find first zero in word. Undefined if no zero exists.
  * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
  */
 static inline int ffz(unsigned long x)
 {
 	return 31 - __cntlz(~x & -~x);
 }
 /*
  * __ffs: Find first bit set in word. Return 0 for bit 0
  */
 static inline int __ffs(unsigned long x)
 {
 	return 31 - __cntlz(x & -x);
 }
 /*
  * ffs: Find first bit set in word. This is defined the same way as
  * the libc and compiler builtin ffs routines, therefore
  * differs in spirit from the above ffz (man ffs).
  */
 static inline int ffs(unsigned long x)
 {
 	return 32 - __cntlz(x & -x);
 }
 /*
  * fls: Find last (most-significant) bit set in word.
  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
  */
 static inline int fls (unsigned int x)
 {
 	return 32 - __cntlz(x);
 }
 /**
  * __fls - find last (most-significant) set bit in a long word
  * @word: the word to search
  *
  * Undefined if no set bit exists, so code should check against 0 first.
  */
 static inline unsigned long __fls(unsigned long word)
 {
 	return 31 - __cntlz(word);
 }
 #else
 /* Use the generic implementation if we don't have the nsa/nsau instructions. */
 # include <asm-generic/bitops/ffs.h>
 # include <asm-generic/bitops/__ffs.h>
 # include <asm-generic/bitops/ffz.h>
 # include <asm-generic/bitops/fls.h>
 # include <asm-generic/bitops/__fls.h>
 #endif
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/le.h>
 #ifdef __XTENSA_EL__
 # define ext2_set_bit_atomic(lock,nr,addr)				\
 	test_and_set_bit((nr), (unsigned long*)(addr))
 # define ext2_clear_bit_atomic(lock,nr,addr)				\
 	test_and_clear_bit((nr), (unsigned long*)(addr))
 #elif defined(__XTENSA_EB__)
 # define ext2_set_bit_atomic(lock,nr,addr)				\
 	test_and_set_bit((nr) ^ 0x18, (unsigned long*)(addr))
 # define ext2_clear_bit_atomic(lock,nr,addr)				\
 	test_and_clear_bit((nr) ^ 0x18, (unsigned long*)(addr))
 #else
 # error processor byte order undefined!
 #endif
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/minix.h>
 #endif	/* __KERNEL__ */
 #endif	/* _XTENSA_BITOPS_H */

fs/minix/Kconfig

Diff comments View file @ 61f2e7b

 config MINIX_FS
 	tristate "Minix file system support"
 	depends on BLOCK
 	help
 	  Minix is a simple operating system used in many classes about OS's.
 	  The minix file system (method to organize files on a hard disk
 	  partition or a floppy disk) was the original file system for Linux,
 	  but has been superseded by the second extended file system ext2fs.
 	  You don't want to use the minix file system on your hard disk
 	  because of certain built-in restrictions, but it is sometimes found
 	  on older Linux floppy disks.  This option will enlarge your kernel
 	  by about 28 KB. If unsure, say N.
 	  To compile this file system support as a module, choose M here: the
 	  module will be called minix.  Note that the file system of your root
 	  partition (the one containing the directory /) cannot be compiled as
 	  a module.
+config MINIX_FS_NATIVE_ENDIAN
+	def_bool MINIX_FS
+	depends on H8300 || M32R || MICROBLAZE || MIPS || S390 || SUPERH || SPARC || XTENSA || (M68K && !MMU)
+config MINIX_FS_BIG_ENDIAN_16BIT_INDEXED
+	def_bool MINIX_FS
+	depends on M68K && MMU

fs/minix/minix.h

Diff comments View file @ 61f2e7b

 #ifndef FS_MINIX_H
 #define FS_MINIX_H
 #include <linux/fs.h>
 #include <linux/pagemap.h>
 #include <linux/minix_fs.h>
 #define INODE_VERSION(inode)	minix_sb(inode->i_sb)->s_version
 #define MINIX_V1		0x0001		/* original minix fs */
 #define MINIX_V2		0x0002		/* minix V2 fs */
 #define MINIX_V3		0x0003		/* minix V3 fs */
 /*
  * minix fs inode data in memory
  */
 struct minix_inode_info {
 	union {
 		__u16 i1_data[16];
 		__u32 i2_data[16];
 	} u;
 	struct inode vfs_inode;
 };
 /*
  * minix super-block data in memory
  */
 struct minix_sb_info {
 	unsigned long s_ninodes;
 	unsigned long s_nzones;
 	unsigned long s_imap_blocks;
 	unsigned long s_zmap_blocks;
 	unsigned long s_firstdatazone;
 	unsigned long s_log_zone_size;
 	unsigned long s_max_size;
 	int s_dirsize;
 	int s_namelen;
 	int s_link_max;
 	struct buffer_head ** s_imap;
 	struct buffer_head ** s_zmap;
 	struct buffer_head * s_sbh;
 	struct minix_super_block * s_ms;
 	unsigned short s_mount_state;
 	unsigned short s_version;
 };
 extern struct inode *minix_iget(struct super_block *, unsigned long);
 extern struct minix_inode * minix_V1_raw_inode(struct super_block *, ino_t, struct buffer_head **);
 extern struct minix2_inode * minix_V2_raw_inode(struct super_block *, ino_t, struct buffer_head **);
 extern struct inode * minix_new_inode(const struct inode *, int, int *);
 extern void minix_free_inode(struct inode * inode);
 extern unsigned long minix_count_free_inodes(struct minix_sb_info *sbi);
 extern int minix_new_block(struct inode * inode);
 extern void minix_free_block(struct inode *inode, unsigned long block);
 extern unsigned long minix_count_free_blocks(struct minix_sb_info *sbi);
 extern int minix_getattr(struct vfsmount *, struct dentry *, struct kstat *);
 extern int minix_prepare_chunk(struct page *page, loff_t pos, unsigned len);
 extern void V1_minix_truncate(struct inode *);
 extern void V2_minix_truncate(struct inode *);
 extern void minix_truncate(struct inode *);
 extern void minix_set_inode(struct inode *, dev_t);
 extern int V1_minix_get_block(struct inode *, long, struct buffer_head *, int);
 extern int V2_minix_get_block(struct inode *, long, struct buffer_head *, int);
 extern unsigned V1_minix_blocks(loff_t, struct super_block *);
 extern unsigned V2_minix_blocks(loff_t, struct super_block *);
 extern struct minix_dir_entry *minix_find_entry(struct dentry*, struct page**);
 extern int minix_add_link(struct dentry*, struct inode*);
 extern int minix_delete_entry(struct minix_dir_entry*, struct page*);
 extern int minix_make_empty(struct inode*, struct inode*);
 extern int minix_empty_dir(struct inode*);
 extern void minix_set_link(struct minix_dir_entry*, struct page*, struct inode*);
 extern struct minix_dir_entry *minix_dotdot(struct inode*, struct page**);
 extern ino_t minix_inode_by_name(struct dentry*);
 extern const struct inode_operations minix_file_inode_operations;
 extern const struct inode_operations minix_dir_inode_operations;
 extern const struct file_operations minix_file_operations;
 extern const struct file_operations minix_dir_operations;
 static inline struct minix_sb_info *minix_sb(struct super_block *sb)
 {
 	return sb->s_fs_info;
 }
 static inline struct minix_inode_info *minix_i(struct inode *inode)
 {
 	return list_entry(inode, struct minix_inode_info, vfs_inode);
 }
+#if defined(CONFIG_MINIX_FS_NATIVE_ENDIAN) && \
+	defined(CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED)
+#error Minix file system byte order broken
+#elif defined(CONFIG_MINIX_FS_NATIVE_ENDIAN)
+/*
+ * big-endian 32 or 64 bit indexed bitmaps on big-endian system or
+ * little-endian bitmaps on little-endian system
+ */
+#define minix_test_and_set_bit(nr, addr)	\
+	__test_and_set_bit((nr), (unsigned long *)(addr))
+#define minix_set_bit(nr, addr)		\
+	__set_bit((nr), (unsigned long *)(addr))
+#define minix_test_and_clear_bit(nr, addr) \
+	__test_and_clear_bit((nr), (unsigned long *)(addr))
+#define minix_test_bit(nr, addr)		\
+	test_bit((nr), (unsigned long *)(addr))
+#define minix_find_first_zero_bit(addr, size) \
+	find_first_zero_bit((unsigned long *)(addr), (size))
+#elif defined(CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED)
+/*
+ * big-endian 16bit indexed bitmaps
+ */
+static inline int minix_find_first_zero_bit(const void *vaddr, unsigned size)
+{
+	const unsigned short *p = vaddr, *addr = vaddr;
+	unsigned short num;
+	if (!size)
+		return 0;
+	size = (size >> 4) + ((size & 15) > 0);
+	while (*p++ == 0xffff) {
+		if (--size == 0)
+			return (p - addr) << 4;
+	}
+	num = *--p;
+	return ((p - addr) << 4) + ffz(num);
+}
+#define minix_test_and_set_bit(nr, addr)	\
+	__test_and_set_bit((nr) ^ 16, (unsigned long *)(addr))
+#define minix_set_bit(nr, addr)	\
+	__set_bit((nr) ^ 16, (unsigned long *)(addr))
+#define minix_test_and_clear_bit(nr, addr)	\
+	__test_and_clear_bit((nr) ^ 16, (unsigned long *)(addr))
+static inline int minix_test_bit(int nr, const void *vaddr)
+{
+	const unsigned short *p = vaddr;
+	return (p[nr >> 4] & (1U << (nr & 15))) != 0;
+}
+#else
+/*
+ * little-endian bitmaps
+ */
+#define minix_test_and_set_bit	__test_and_set_bit_le
+#define minix_set_bit		__set_bit_le
+#define minix_test_and_clear_bit	__test_and_clear_bit_le
+#define minix_test_bit	test_bit_le
+#define minix_find_first_zero_bit	find_first_zero_bit_le
+#endif
 #endif /* FS_MINIX_H */

include/asm-generic/bitops.h

Diff comments View file @ 61f2e7b

 #ifndef __ASM_GENERIC_BITOPS_H
 #define __ASM_GENERIC_BITOPS_H
 /*
  * For the benefit of those who are trying to port Linux to another
  * architecture, here are some C-language equivalents.  You should
  * recode these in the native assembly language, if at all possible.
  *
  * C language equivalents written by Theodore Ts'o, 9/26/92
  */
 #include <linux/irqflags.h>
 #include <linux/compiler.h>
 /*
  * clear_bit may not imply a memory barrier
  */
 #ifndef smp_mb__before_clear_bit
 #define smp_mb__before_clear_bit()	smp_mb()
 #define smp_mb__after_clear_bit()	smp_mb()
 #endif
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/ffz.h>
 #include <asm-generic/bitops/fls.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls64.h>
 #include <asm-generic/bitops/find.h>
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
 #include <asm-generic/bitops/sched.h>
 #include <asm-generic/bitops/ffs.h>
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/atomic.h>
 #include <asm-generic/bitops/non-atomic.h>
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
 #endif /* __ASM_GENERIC_BITOPS_H */

include/asm-generic/bitops/minix-le.h

View file @ 61f2e7b

1	#ifndef _ASM_GENERIC_BITOPS_MINIX_LE_H_		File was deleted
2	#define _ASM_GENERIC_BITOPS_MINIX_LE_H_
3
4	#define minix_test_and_set_bit(nr,addr) \
5	__test_and_set_bit_le((nr), (unsigned long *)(addr))
6	#define minix_set_bit(nr,addr) \
7	__set_bit_le((nr), (unsigned long *)(addr))
8	#define minix_test_and_clear_bit(nr,addr) \
9	__test_and_clear_bit_le((nr), (unsigned long *)(addr))
10	#define minix_test_bit(nr,addr) \
11	test_bit_le((nr), (unsigned long *)(addr))
12	#define minix_find_first_zero_bit(addr,size) \
13	find_first_zero_bit_le((unsigned long *)(addr), (size))
14
15	#endif /* _ASM_GENERIC_BITOPS_MINIX_LE_H_ */
16		1	#ifndef _ASM_GENERIC_BITOPS_MINIX_LE_H_

include/asm-generic/bitops/minix.h

View file @ 61f2e7b

1	#ifndef _ASM_GENERIC_BITOPS_MINIX_H_		File was deleted
2	#define _ASM_GENERIC_BITOPS_MINIX_H_
3
4	#define minix_test_and_set_bit(nr,addr) \
5	__test_and_set_bit((nr),(unsigned long *)(addr))
6	#define minix_set_bit(nr,addr) \
7	__set_bit((nr),(unsigned long *)(addr))
8	#define minix_test_and_clear_bit(nr,addr) \
9	__test_and_clear_bit((nr),(unsigned long *)(addr))
10	#define minix_test_bit(nr,addr) \
11	test_bit((nr),(unsigned long *)(addr))
12	#define minix_find_first_zero_bit(addr,size) \
13	find_first_zero_bit((unsigned long *)(addr),(size))
14
15	#endif /* _ASM_GENERIC_BITOPS_MINIX_H_ */
16		1	#ifndef _ASM_GENERIC_BITOPS_MINIX_H_