diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index 633d21f..d36d0b5 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -18,7 +18,6 @@ * GNU General Public License for more details. */ #include -#include #include @@ -198,72 +197,12 @@ static struct omap_opp_def __initdata am33xx_es2_0_opp_def_list[] = { AM33XX_ES2_0_VDD_MPU_OPPNITRO_UV), }; -#define AM33XX_ES2_1_VDD_MPU_OPP50_UV 950000 -#define AM33XX_ES2_1_VDD_MPU_OPP100_UV 1100000 -#define AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV 1260000 -#define AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV 1350000 - -#define OPP_50_INDEX 0 -#define OPP_100_INDEX 1 -#define OPP_TURBO_INDEX 2 -#define OPP_NITRO_INDEX 3 - - -/* From AM335x TRM, SPRUH73H, Section 9.3.50 */ -#define AM33XX_EFUSE_SMA_OFFSET 0x7fc - -/* - * Bits [17-16] indicates package type - * 00 - reserved - * 01 - ZCZ - * 10 - ZCE - * 11 - reserved - */ -#define PACKAGE_TYPE_MASK 0x3 -#define PACKAGE_TYPE_SHFT 16 - -#define PACKAGE_TYPE_ZCZ 0x1 -#define PACKAGE_TYPE_ZCE 0x2 - -/* - * Bits [12:0] are OPP Disabled bits, - * 1 = OPP is disabled and not available, - * 0 = OPP available. - */ -#define MAX_FREQ_MASK 0x1fff -#define MAX_FREQ_SHFT 0 - -#define OPP_50_300MHZ_ZCZ_BIT 4 -#define OPP_100_600MHZ_ZCZ_BIT 6 -#define OPP_TURBO_800MHZ_ZCZ_BIT 8 -#define OPP_NITRO_1GHZ_ZCZ_BIT 9 - -#define OPP_50_300MHZ_ZCE_BIT 5 -#define OPP_100_600MHZ_ZCE_BIT 6 - - -static struct omap_opp_def __initdata am33xx_es2_1_opp_list[] = { - /* MPU OPP1 - OPP50 */ - OPP_INITIALIZER("mpu", false, 300000000, - AM33XX_ES2_1_VDD_MPU_OPP50_UV), - /* MPU OPP2 - OPP100 */ - OPP_INITIALIZER("mpu", false, 600000000, - AM33XX_ES2_1_VDD_MPU_OPP100_UV), - /* MPU OPP3 - OPPTurbo */ - OPP_INITIALIZER("mpu", false, 800000000, - AM33XX_ES2_1_VDD_MPU_OPPTURBO_UV), - /* MPU OPP4 - OPPNitro */ - OPP_INITIALIZER("mpu", false, 1000000000, - AM33XX_ES2_1_VDD_MPU_OPPNITRO_UV), -}; - /** * omap3_opp_init() - initialize omap3 opp table */ int __init omap3_opp_init(void) { int r = -ENODEV; - u32 rev, val, package_type, max_freq; if (!cpu_is_omap34xx()) return r; @@ -272,74 +211,16 @@ int __init omap3_opp_init(void) r = omap_init_opp_table(omap36xx_opp_def_list, ARRAY_SIZE(omap36xx_opp_def_list)); else if (cpu_is_am33xx()) { - rev = omap_rev(); - switch (rev) { - case AM335X_REV_ES1_0: + if (omap_rev() == AM335X_REV_ES1_0) r = omap_init_opp_table(am33xx_es1_0_opp_def_list, ARRAY_SIZE(am33xx_es1_0_opp_def_list)); - break; - - case AM335X_REV_ES2_1: - /* - * First read efuse sma reg to detect package type and - * supported frequency - */ - val = - readl(AM33XX_CTRL_REGADDR(AM33XX_EFUSE_SMA_OFFSET)); - - package_type = (val >> PACKAGE_TYPE_SHFT) & - PACKAGE_TYPE_MASK; - max_freq = val & MAX_FREQ_MASK; - - if (package_type == PACKAGE_TYPE_ZCZ) { - if (max_freq & OPP_50_300MHZ_ZCZ_BIT) - am33xx_es2_1_opp_list[OPP_50_INDEX]. - default_available = true; - - if (max_freq & OPP_100_600MHZ_ZCZ_BIT) - am33xx_es2_1_opp_list[OPP_100_INDEX]. - default_available = true; - - if (max_freq & OPP_TURBO_800MHZ_ZCZ_BIT) - am33xx_es2_1_opp_list[OPP_TURBO_INDEX]. - default_available = true; - - if (max_freq & OPP_NITRO_1GHZ_ZCZ_BIT) - am33xx_es2_1_opp_list[OPP_NITRO_INDEX]. - default_available = true; - } else if (package_type == PACKAGE_TYPE_ZCE) { - if (max_freq & OPP_50_300MHZ_ZCE_BIT) - am33xx_es2_1_opp_list[OPP_50_INDEX]. - default_available = true; - - if (max_freq & OPP_100_600MHZ_ZCE_BIT) - am33xx_es2_1_opp_list[OPP_100_INDEX]. - default_available = true; - } else { - /* - * if package type is not detected fall back to - * PG 2.0 OPP settings - */ - r = - omap_init_opp_table(am33xx_es2_0_opp_def_list, - ARRAY_SIZE(am33xx_es2_0_opp_def_list)); - break; - } - - r = omap_init_opp_table(am33xx_es2_1_opp_list, - ARRAY_SIZE(am33xx_es2_1_opp_list)); - break; - - case AM335X_REV_ES2_0: - /* FALLTHROUGH */ - default: + else r = omap_init_opp_table(am33xx_es2_0_opp_def_list, ARRAY_SIZE(am33xx_es2_0_opp_def_list)); - } - } else { + } + else r = omap_init_opp_table(omap34xx_opp_def_list, ARRAY_SIZE(omap34xx_opp_def_list)); - } return r; }