Eric Lee / linux-smarc-t335x-v3.2

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/*

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/*

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*

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*

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* Based on the LCD driver for TI Avalanche processors written by

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* Based on the LCD driver for TI Avalanche processors written by

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* Ajay Singh and Shalom Hai.

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* Ajay Singh and Shalom Hai.

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*

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*

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* This program is free software; you can redistribute it and/or modify

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License as published by

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* it under the terms of the GNU General Public License as published by

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* the Free Software Foundation; either version 2 of the License, or

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* the Free Software Foundation; either version 2 of the License, or

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* (at your option)any later version.

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* (at your option)any later version.

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*

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*

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* This program is distributed in the hope that it will be useful,

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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* GNU General Public License for more details.

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*

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*

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* You should have received a copy of the GNU General Public License

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* You should have received a copy of the GNU General Public License

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* along with this program; if not, write to the Free Software

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* along with this program; if not, write to the Free Software

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA

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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA

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*/

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*/

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#include <linux/module.h>

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#include <linux/module.h>

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#include <linux/kernel.h>

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#include <linux/kernel.h>

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#include <linux/fb.h>

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#include <linux/fb.h>

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#include <linux/dma-mapping.h>

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#include <linux/dma-mapping.h>

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#include <linux/device.h>

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#include <linux/device.h>

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#include <linux/platform_device.h>

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#include <linux/platform_device.h>

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#include <linux/uaccess.h>

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#include <linux/uaccess.h>

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#include <linux/interrupt.h>

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#include <linux/interrupt.h>

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#include <linux/clk.h>

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#include <linux/clk.h>

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#include <linux/cpufreq.h>

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#include <linux/cpufreq.h>

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#include <linux/console.h>

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#include <linux/console.h>

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#include <linux/spinlock.h>

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#include <linux/spinlock.h>

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#include <linux/slab.h>

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#include <linux/slab.h>

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#include <video/da8xx-fb.h>

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#include <video/da8xx-fb.h>

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#include <asm/mach-types.h>

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#include <asm/mach-types.h>

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#define DRIVER_NAME "da8xx_lcdc"

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#define DRIVER_NAME "da8xx_lcdc"

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#define LCD_VERSION_1 1

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#define LCD_VERSION_1 1

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#define LCD_VERSION_2 2

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#define LCD_VERSION_2 2

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/* LCD Status Register */

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/* LCD Status Register */

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#define LCD_END_OF_FRAME1 BIT(9)

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#define LCD_END_OF_FRAME1 BIT(9)

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#define LCD_END_OF_FRAME0 BIT(8)

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#define LCD_END_OF_FRAME0 BIT(8)

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#define LCD_PL_LOAD_DONE BIT(6)

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#define LCD_PL_LOAD_DONE BIT(6)

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#define LCD_FIFO_UNDERFLOW BIT(5)

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#define LCD_FIFO_UNDERFLOW BIT(5)

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#define LCD_SYNC_LOST BIT(2)

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#define LCD_SYNC_LOST BIT(2)

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/* LCD DMA Control Register */

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/* LCD DMA Control Register */

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#define LCD_DMA_BURST_SIZE(x) ((x) << 4)

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#define LCD_DMA_BURST_SIZE(x) ((x) << 4)

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#define LCD_DMA_BURST_1 0x0

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#define LCD_DMA_BURST_1 0x0

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#define LCD_DMA_BURST_2 0x1

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#define LCD_DMA_BURST_2 0x1

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#define LCD_DMA_BURST_4 0x2

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#define LCD_DMA_BURST_4 0x2

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#define LCD_DMA_BURST_8 0x3

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#define LCD_DMA_BURST_8 0x3

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#define LCD_DMA_BURST_16 0x4

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#define LCD_DMA_BURST_16 0x4

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#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)

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#define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)

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#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)

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#define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)

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#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)

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#define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)

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#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)

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#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)

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/* LCD Control Register */

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/* LCD Control Register */

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#define LCD_CLK_DIVISOR(x) ((x) << 8)

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#define LCD_CLK_DIVISOR(x) ((x) << 8)

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#define LCD_RASTER_MODE 0x01

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#define LCD_RASTER_MODE 0x01

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/* LCD Raster Control Register */

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/* LCD Raster Control Register */

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#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)

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#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)

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#define PALETTE_AND_DATA 0x00

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#define PALETTE_AND_DATA 0x00

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#define PALETTE_ONLY 0x01

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#define PALETTE_ONLY 0x01

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#define DATA_ONLY 0x02

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#define DATA_ONLY 0x02

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#define LCD_MONO_8BIT_MODE BIT(9)

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#define LCD_MONO_8BIT_MODE BIT(9)

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#define LCD_RASTER_ORDER BIT(8)

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#define LCD_RASTER_ORDER BIT(8)

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#define LCD_TFT_MODE BIT(7)

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#define LCD_TFT_MODE BIT(7)

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#define LCD_V1_UNDERFLOW_INT_ENA BIT(6)

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#define LCD_V1_UNDERFLOW_INT_ENA BIT(6)

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#define LCD_V2_UNDERFLOW_INT_ENA BIT(5)

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#define LCD_V2_UNDERFLOW_INT_ENA BIT(5)

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#define LCD_V1_PL_INT_ENA BIT(4)

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#define LCD_V1_PL_INT_ENA BIT(4)

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#define LCD_V2_PL_INT_ENA BIT(6)

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#define LCD_V2_PL_INT_ENA BIT(6)

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#define LCD_MONOCHROME_MODE BIT(1)

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#define LCD_MONOCHROME_MODE BIT(1)

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#define LCD_RASTER_ENABLE BIT(0)

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#define LCD_RASTER_ENABLE BIT(0)

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#define LCD_TFT_ALT_ENABLE BIT(23)

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#define LCD_TFT_ALT_ENABLE BIT(23)

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#define LCD_STN_565_ENABLE BIT(24)

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#define LCD_STN_565_ENABLE BIT(24)

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#define LCD_V2_DMA_CLK_EN BIT(2)

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#define LCD_V2_DMA_CLK_EN BIT(2)

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#define LCD_V2_LIDD_CLK_EN BIT(1)

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#define LCD_V2_LIDD_CLK_EN BIT(1)

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#define LCD_V2_CORE_CLK_EN BIT(0)

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#define LCD_V2_CORE_CLK_EN BIT(0)

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#define LCD_V2_LPP_B10 26

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#define LCD_V2_LPP_B10 26

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#define LCD_V2_TFT_24BPP_MODE BIT(25)

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#define LCD_V2_TFT_24BPP_MODE BIT(25)

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#define LCD_V2_TFT_24BPP_UNPACK BIT(26)

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#define LCD_V2_TFT_24BPP_UNPACK BIT(26)

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/* LCD Raster Timing 2 Register */

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/* LCD Raster Timing 2 Register */

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#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)

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#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)

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#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)

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#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)

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#define LCD_SYNC_CTRL BIT(25)

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#define LCD_SYNC_CTRL BIT(25)

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#define LCD_SYNC_EDGE BIT(24)

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#define LCD_SYNC_EDGE BIT(24)

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#define LCD_INVERT_PIXEL_CLOCK BIT(22)

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#define LCD_INVERT_PIXEL_CLOCK BIT(22)

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#define LCD_INVERT_LINE_CLOCK BIT(21)

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#define LCD_INVERT_LINE_CLOCK BIT(21)

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#define LCD_INVERT_FRAME_CLOCK BIT(20)

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#define LCD_INVERT_FRAME_CLOCK BIT(20)

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/* LCD Block */

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/* LCD Block */

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#define LCD_PID_REG 0x0

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#define LCD_PID_REG 0x0

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#define LCD_CTRL_REG 0x4

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#define LCD_CTRL_REG 0x4

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#define LCD_STAT_REG 0x8

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#define LCD_STAT_REG 0x8

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#define LCD_RASTER_CTRL_REG 0x28

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#define LCD_RASTER_CTRL_REG 0x28

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#define LCD_RASTER_TIMING_0_REG 0x2C

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#define LCD_RASTER_TIMING_0_REG 0x2C

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#define LCD_RASTER_TIMING_1_REG 0x30

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#define LCD_RASTER_TIMING_1_REG 0x30

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#define LCD_RASTER_TIMING_2_REG 0x34

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#define LCD_RASTER_TIMING_2_REG 0x34

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#define LCD_DMA_CTRL_REG 0x40

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#define LCD_DMA_CTRL_REG 0x40

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#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44

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#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44

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#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48

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#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48

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#define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C

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#define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C

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#define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50

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#define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50

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/* Interrupt Registers available only in Version 2 */

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/* Interrupt Registers available only in Version 2 */

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#define LCD_RAW_STAT_REG 0x58

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#define LCD_RAW_STAT_REG 0x58

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#define LCD_MASKED_STAT_REG 0x5c

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#define LCD_MASKED_STAT_REG 0x5c

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#define LCD_INT_ENABLE_SET_REG 0x60

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#define LCD_INT_ENABLE_SET_REG 0x60

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#define LCD_INT_ENABLE_CLR_REG 0x64

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#define LCD_INT_ENABLE_CLR_REG 0x64

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#define LCD_END_OF_INT_IND_REG 0x68

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#define LCD_END_OF_INT_IND_REG 0x68

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/* Clock registers available only on Version 2 */

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/* Clock registers available only on Version 2 */

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#define LCD_CLK_ENABLE_REG 0x6c

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#define LCD_CLK_ENABLE_REG 0x6c

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#define LCD_CLK_RESET_REG 0x70

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#define LCD_CLK_RESET_REG 0x70

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#define LCD_CLK_MAIN_RESET BIT(3)

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#define LCD_CLK_MAIN_RESET BIT(3)

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#define LCD_NUM_BUFFERS 2

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#define LCD_NUM_BUFFERS 2

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#define WSI_TIMEOUT 50

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#define WSI_TIMEOUT 50

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#define PALETTE_SIZE 256

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#define PALETTE_SIZE 256

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#define LEFT_MARGIN 64

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#define LEFT_MARGIN 64

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#define RIGHT_MARGIN 64

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#define RIGHT_MARGIN 64

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#define UPPER_MARGIN 32

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#define UPPER_MARGIN 32

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#define LOWER_MARGIN 32

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#define LOWER_MARGIN 32

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static resource_size_t da8xx_fb_reg_base;

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static resource_size_t da8xx_fb_reg_base;

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static struct resource *lcdc_regs;

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static struct resource *lcdc_regs;

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static unsigned int lcd_revision;

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static unsigned int lcd_revision;

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static irq_handler_t lcdc_irq_handler;

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static irq_handler_t lcdc_irq_handler;

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static inline unsigned int lcdc_read(unsigned int addr)

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static inline unsigned int lcdc_read(unsigned int addr)

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{

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{

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return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));

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return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));

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}

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}

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static inline void lcdc_write(unsigned int val, unsigned int addr)

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static inline void lcdc_write(unsigned int val, unsigned int addr)

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{

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{

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__raw_writel(val, da8xx_fb_reg_base + (addr));

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__raw_writel(val, da8xx_fb_reg_base + (addr));

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}

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}

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struct da8xx_fb_par {

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struct da8xx_fb_par {

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resource_size_t p_palette_base;

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resource_size_t p_palette_base;

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unsigned char *v_palette_base;

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unsigned char *v_palette_base;

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dma_addr_t vram_phys;

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dma_addr_t vram_phys;

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unsigned long vram_size;

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unsigned long vram_size;

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void *vram_virt;

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void *vram_virt;

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unsigned int dma_start;

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unsigned int dma_start;

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unsigned int dma_end;

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unsigned int dma_end;

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struct clk *lcdc_clk;

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struct clk *lcdc_clk;

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int irq;

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int irq;

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unsigned short pseudo_palette[32];

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unsigned short pseudo_palette[32];

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unsigned int palette_sz;

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unsigned int palette_sz;

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unsigned int pxl_clk;

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unsigned int pxl_clk;

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int blank;

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int blank;

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wait_queue_head_t vsync_wait;

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wait_queue_head_t vsync_wait;

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int vsync_flag;

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int vsync_flag;

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int vsync_timeout;

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int vsync_timeout;

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spinlock_t lock_for_chan_update;

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spinlock_t lock_for_chan_update;

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/*

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/*

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* LCDC has 2 ping pong DMA channels, channel 0

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* LCDC has 2 ping pong DMA channels, channel 0

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* and channel 1.

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* and channel 1.

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*/

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*/

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unsigned int which_dma_channel_done;

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unsigned int which_dma_channel_done;

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#ifdef CONFIG_CPU_FREQ

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#ifdef CONFIG_CPU_FREQ

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struct notifier_block freq_transition;

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struct notifier_block freq_transition;

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#endif

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#endif

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void (*panel_power_ctrl)(int);

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void (*panel_power_ctrl)(int);

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};

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};

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/* Variable Screen Information */

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/* Variable Screen Information */

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static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {

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static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {

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.xoffset = 0,

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.xoffset = 0,

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.yoffset = 0,

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.yoffset = 0,

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.transp = {0, 0, 0},

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.transp = {0, 0, 0},

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.nonstd = 0,

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.nonstd = 0,

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.activate = 0,

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.activate = 0,

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.height = -1,

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.height = -1,

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.width = -1,

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.width = -1,

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.pixclock = 33333,/*Pico Sec*/

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.pixclock = 33333,/*Pico Sec*/

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.accel_flags = 0,

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.accel_flags = 0,

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.left_margin = LEFT_MARGIN,

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.left_margin = LEFT_MARGIN,

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.right_margin = RIGHT_MARGIN,

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.right_margin = RIGHT_MARGIN,

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.upper_margin = UPPER_MARGIN,

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.upper_margin = UPPER_MARGIN,

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.lower_margin = LOWER_MARGIN,

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.lower_margin = LOWER_MARGIN,

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.sync = 0,

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.sync = 0,

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.vmode = FB_VMODE_NONINTERLACED

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.vmode = FB_VMODE_NONINTERLACED

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};

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};

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static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {

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static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {

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.id = "DA8xx FB Drv",

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.id = "DA8xx FB Drv",

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.type = FB_TYPE_PACKED_PIXELS,

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.type = FB_TYPE_PACKED_PIXELS,

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.type_aux = 0,

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.type_aux = 0,

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.visual = FB_VISUAL_PSEUDOCOLOR,

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.visual = FB_VISUAL_PSEUDOCOLOR,

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.xpanstep = 0,

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.xpanstep = 0,

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.ypanstep = 1,

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.ypanstep = 1,

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.ywrapstep = 0,

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.ywrapstep = 0,

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.accel = FB_ACCEL_NONE

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.accel = FB_ACCEL_NONE

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};

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};

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struct da8xx_panel {

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struct da8xx_panel {

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const char name[25]; /* Full name <vendor>_<model> */

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const char name[25]; /* Full name <vendor>_<model> */

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unsigned short width;

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unsigned short width;

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unsigned short height;

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unsigned short height;

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int hfp; /* Horizontal front porch */

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int hfp; /* Horizontal front porch */

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int hbp; /* Horizontal back porch */

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int hbp; /* Horizontal back porch */

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int hsw; /* Horizontal Sync Pulse Width */

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int hsw; /* Horizontal Sync Pulse Width */

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int vfp; /* Vertical front porch */

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int vfp; /* Vertical front porch */

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int vbp; /* Vertical back porch */

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int vbp; /* Vertical back porch */

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int vsw; /* Vertical Sync Pulse Width */

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int vsw; /* Vertical Sync Pulse Width */

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unsigned int pxl_clk; /* Pixel clock */

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unsigned int pxl_clk; /* Pixel clock */

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unsigned char invert_pxl_clk; /* Invert Pixel clock */

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unsigned char invert_pxl_clk; /* Invert Pixel clock */

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};

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};

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static vsync_callback_t vsync_cb_handler;

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static vsync_callback_t vsync_cb_handler;

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static void *vsync_cb_arg;

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static void *vsync_cb_arg;

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static struct da8xx_panel known_lcd_panels[] = {

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static struct da8xx_panel known_lcd_panels[] = {

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/* Sharp LCD035Q3DG01 */

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/* Sharp LCD035Q3DG01 */

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[0] = {

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[0] = {

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.name = "Sharp_LCD035Q3DG01",

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.name = "Sharp_LCD035Q3DG01",

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.width = 320,

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.width = 320,

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.height = 240,

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.height = 240,

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.hfp = 8,

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.hfp = 8,

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.hbp = 6,

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.hbp = 6,

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.hsw = 0,

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.hsw = 0,

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.vfp = 2,

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.vfp = 2,

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.vbp = 2,

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.vbp = 2,

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.vsw = 0,

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.vsw = 0,

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.pxl_clk = 4608000,

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.pxl_clk = 4608000,

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.invert_pxl_clk = 1,

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.invert_pxl_clk = 1,

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},

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},

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/* Sharp LK043T1DG01 */

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/* Sharp LK043T1DG01 */

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[1] = {

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[1] = {

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.name = "Sharp_LK043T1DG01",

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.name = "Sharp_LK043T1DG01",

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.width = 480,

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.width = 480,

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.height = 272,

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.height = 272,

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.hfp = 2,

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.hfp = 2,

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.hbp = 2,

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.hbp = 2,

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.hsw = 41,

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.hsw = 41,

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.vfp = 3,

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.vfp = 3,

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.vbp = 3,

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.vbp = 3,

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.vsw = 10,

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.vsw = 10,

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.pxl_clk = 7833600,

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.pxl_clk = 7833600,

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.invert_pxl_clk = 0,

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.invert_pxl_clk = 0,

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},

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},

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/* ThreeFive S9700RTWV35TR */

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/* ThreeFive S9700RTWV35TR */

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[2] = {

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[2] = {

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.name = "TFC_S9700RTWV35TR_01B",

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.name = "TFC_S9700RTWV35TR_01B",

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.width = 800,

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.width = 800,

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.height = 480,

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.height = 480,

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.hfp = 39,

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.hfp = 39,

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.hbp = 39,

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.hbp = 39,

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.hsw = 47,

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.hsw = 47,

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.vfp = 13,

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.vfp = 13,

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.vbp = 29,

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.vbp = 29,

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.vsw = 2,

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.vsw = 2,

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.pxl_clk = 30000000,

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.pxl_clk = 30000000,

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.invert_pxl_clk = 0,

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.invert_pxl_clk = 0,

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},

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},

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};

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};

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/* Enable the Raster Engine of the LCD Controller */

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/* Enable the Raster Engine of the LCD Controller */

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static inline void lcd_enable_raster(void)

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static inline void lcd_enable_raster(void)

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{

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{

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u32 reg;

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u32 reg;

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/* Bring LCDC out of reset */

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/* Bring LCDC out of reset */

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if (lcd_revision == LCD_VERSION_2)

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if (lcd_revision == LCD_VERSION_2)

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lcdc_write(0, LCD_CLK_RESET_REG);

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lcdc_write(0, LCD_CLK_RESET_REG);

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reg = lcdc_read(LCD_RASTER_CTRL_REG);

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reg = lcdc_read(LCD_RASTER_CTRL_REG);

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if (!(reg & LCD_RASTER_ENABLE))

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if (!(reg & LCD_RASTER_ENABLE))

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lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);

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lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);

283

}

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}

284

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/* Disable the Raster Engine of the LCD Controller */

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/* Disable the Raster Engine of the LCD Controller */

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static inline void lcd_disable_raster(void)

286

static inline void lcd_disable_raster(void)

287

{

287

{

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u32 reg;

288

u32 reg;

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reg = lcdc_read(LCD_RASTER_CTRL_REG);

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reg = lcdc_read(LCD_RASTER_CTRL_REG);

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if (reg & LCD_RASTER_ENABLE)

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if (reg & LCD_RASTER_ENABLE)

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lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);

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lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);

293

294

if (lcd_revision == LCD_VERSION_2)

294

if (lcd_revision == LCD_VERSION_2)

295

/* Write 1 to reset LCDC */

295

/* Write 1 to reset LCDC */

296

lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);

296

lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);

297

}

297

}

298

299

static void lcd_blit(int load_mode, struct da8xx_fb_par *par)

299

static void lcd_blit(int load_mode, struct da8xx_fb_par *par)

300

{

300

{

301

u32 start;

301

u32 start;

302

u32 end;

302

u32 end;

303

u32 reg_ras;

303

u32 reg_ras;

304

u32 reg_dma;

304

u32 reg_dma;

305

u32 reg_int;

305

u32 reg_int;

306

307

/* init reg to clear PLM (loading mode) fields */

307

/* init reg to clear PLM (loading mode) fields */

308

reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);

308

reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);

309

reg_ras &= ~(3 << 20);

309

reg_ras &= ~(3 << 20);

310

311

reg_dma = lcdc_read(LCD_DMA_CTRL_REG);

311

reg_dma = lcdc_read(LCD_DMA_CTRL_REG);

312

313

if (load_mode == LOAD_DATA) {

313

if (load_mode == LOAD_DATA) {

314

start = par->dma_start;

314

start = par->dma_start;

315

end = par->dma_end;

315

end = par->dma_end;

316

317

reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);

317

reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);

318

if (lcd_revision == LCD_VERSION_1) {

318

if (lcd_revision == LCD_VERSION_1) {

319

reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;

319

reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;

320

} else {

320

} else {

321

reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |

321

reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |

322

LCD_V2_END_OF_FRAME0_INT_ENA |

322

LCD_V2_END_OF_FRAME0_INT_ENA |

323

LCD_V2_END_OF_FRAME1_INT_ENA;

323

LCD_V2_END_OF_FRAME1_INT_ENA;

324

lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);

324

lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);

325

}

325

}

326

reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;

326

reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;

327

328

lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

328

lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

329

lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

329

lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

330

lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

330

lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

331

lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

331

lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

332

} else if (load_mode == LOAD_PALETTE) {

332

} else if (load_mode == LOAD_PALETTE) {

333

start = par->p_palette_base;

333

start = par->p_palette_base;

334

end = start + par->palette_sz - 1;

334

end = start + par->palette_sz - 1;

335

336

reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);

336

reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);

337

338

if (lcd_revision == LCD_VERSION_1) {

338

if (lcd_revision == LCD_VERSION_1) {

339

reg_ras |= LCD_V1_PL_INT_ENA;

339

reg_ras |= LCD_V1_PL_INT_ENA;

340

} else {

340

} else {

341

reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |

341

reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |

342

LCD_V2_PL_INT_ENA;

342

LCD_V2_PL_INT_ENA;

343

lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);

343

lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);

344

}

344

}

345

346

lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

346

lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

347

lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

347

lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

348

}

348

}

349

350

lcdc_write(reg_dma, LCD_DMA_CTRL_REG);

350

lcdc_write(reg_dma, LCD_DMA_CTRL_REG);

351

lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);

351

lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);

352

353

/*

353

/*

354

* The Raster enable bit must be set after all other control fields are

354

* The Raster enable bit must be set after all other control fields are

355

* set.

355

* set.

356

*/

356

*/

357

lcd_enable_raster();

357

lcd_enable_raster();

358

}

358

}

359

360

/* Configure the Burst Size and fifo threhold of DMA */

360

/* Configure the Burst Size and fifo threhold of DMA */

361

static int lcd_cfg_dma(int burst_size, int fifo_th)

361

static int lcd_cfg_dma(int burst_size, int fifo_th)

362

{

362

{

363

u32 reg;

363

u32 reg;

364

365

reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;

365

reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;

366

switch (burst_size) {

366

switch (burst_size) {

367

case 1:

367

case 1:

368

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);

368

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);

369

break;

369

break;

370

case 2:

370

case 2:

371

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);

371

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);

372

break;

372

break;

373

case 4:

373

case 4:

374

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);

374

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);

375

break;

375

break;

376

case 8:

376

case 8:

377

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);

377

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);

378

break;

378

break;

379

case 16:

379

case 16:

380

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);

380

reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);

381

break;

381

break;

382

default:

382

default:

383

return -EINVAL;

383

return -EINVAL;

384

}

384

}

385

386

reg |= (fifo_th << 8);

386

reg |= (fifo_th << 8);

387

388

lcdc_write(reg, LCD_DMA_CTRL_REG);

388

lcdc_write(reg, LCD_DMA_CTRL_REG);

389

390

return 0;

390

return 0;

391

}

391

}

392

393

static void lcd_cfg_ac_bias(int period, int transitions_per_int)

393

static void lcd_cfg_ac_bias(int period, int transitions_per_int)

394

{

394

{

395

u32 reg;

395

u32 reg;

396

397

/* Set the AC Bias Period and Number of Transisitons per Interrupt */

397

/* Set the AC Bias Period and Number of Transisitons per Interrupt */

398

reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;

398

reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;

399

reg |= LCD_AC_BIAS_FREQUENCY(period) |

399

reg |= LCD_AC_BIAS_FREQUENCY(period) |

400

LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);

400

LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);

401

lcdc_write(reg, LCD_RASTER_TIMING_2_REG);

401

lcdc_write(reg, LCD_RASTER_TIMING_2_REG);

402

}

402

}

403

404

static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,

404

static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,

405

int front_porch)

405

int front_porch)

406

{

406

{

407

u32 reg;

407

u32 reg;

408

409

reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;

409

reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;

410

reg |= ((back_porch & 0xff) << 24)

410

reg |= ((back_porch & 0xff) << 24)

411

| ((front_porch & 0xff) << 16)

411

| ((front_porch & 0xff) << 16)

412

| ((pulse_width & 0x3f) << 10);

412

| ((pulse_width & 0x3f) << 10);

413

lcdc_write(reg, LCD_RASTER_TIMING_0_REG);

413

lcdc_write(reg, LCD_RASTER_TIMING_0_REG);

414

}

414

}

415

416

static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,

416

static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,

417

int front_porch)

417

int front_porch)

418

{

418

{

419

u32 reg;

419

u32 reg;

420

421

reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;

421

reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;

422

reg |= ((back_porch & 0xff) << 24)

422

reg |= ((back_porch & 0xff) << 24)

423

| ((front_porch & 0xff) << 16)

423

| ((front_porch & 0xff) << 16)

424

| ((pulse_width & 0x3f) << 10);

424

| ((pulse_width & 0x3f) << 10);

425

lcdc_write(reg, LCD_RASTER_TIMING_1_REG);

425

lcdc_write(reg, LCD_RASTER_TIMING_1_REG);

426

}

426

}

427

428

static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)

428

static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)

429

{

429

{

430

u32 reg;

430

u32 reg;

431

u32 reg_int;

431

u32 reg_int;

432

433

reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |

433

reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |

434

LCD_MONO_8BIT_MODE |

434

LCD_MONO_8BIT_MODE |

435

LCD_MONOCHROME_MODE);

435

LCD_MONOCHROME_MODE);

436

437

switch (cfg->p_disp_panel->panel_shade) {

437

switch (cfg->p_disp_panel->panel_shade) {

438

case MONOCHROME:

438

case MONOCHROME:

439

reg |= LCD_MONOCHROME_MODE;

439

reg |= LCD_MONOCHROME_MODE;

440

if (cfg->mono_8bit_mode)

440

if (cfg->mono_8bit_mode)

441

reg |= LCD_MONO_8BIT_MODE;

441

reg |= LCD_MONO_8BIT_MODE;

442

break;

442

break;

443

case COLOR_ACTIVE:

443

case COLOR_ACTIVE:

444

reg |= LCD_TFT_MODE;

444

reg |= LCD_TFT_MODE;

445

if (cfg->tft_alt_mode)

445

if (cfg->tft_alt_mode)

446

reg |= LCD_TFT_ALT_ENABLE;

446

reg |= LCD_TFT_ALT_ENABLE;

447

break;

447

break;

448

449

case COLOR_PASSIVE:

449

case COLOR_PASSIVE:

450

if (cfg->stn_565_mode)

450

if (cfg->stn_565_mode)

451

reg |= LCD_STN_565_ENABLE;

451

reg |= LCD_STN_565_ENABLE;

452

break;

452

break;

453

454

default:

454

default:

455

return -EINVAL;

455

return -EINVAL;

456

}

456

}

457

458

/* enable additional interrupts here */

458

/* enable additional interrupts here */

459

if (lcd_revision == LCD_VERSION_1) {

459

if (lcd_revision == LCD_VERSION_1) {

460

reg |= LCD_V1_UNDERFLOW_INT_ENA;

460

reg |= LCD_V1_UNDERFLOW_INT_ENA;

461

} else {

461

} else {

462

reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |

462

reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |

463

LCD_V2_UNDERFLOW_INT_ENA;

463

LCD_V2_UNDERFLOW_INT_ENA;

464

lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);

464

lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);

465

}

465

}

466

467

lcdc_write(reg, LCD_RASTER_CTRL_REG);

467

lcdc_write(reg, LCD_RASTER_CTRL_REG);

468

469

reg = lcdc_read(LCD_RASTER_TIMING_2_REG);

469

reg = lcdc_read(LCD_RASTER_TIMING_2_REG);

470

471

if (cfg->sync_ctrl)

471

if (cfg->sync_ctrl)

472

reg |= LCD_SYNC_CTRL;

472

reg |= LCD_SYNC_CTRL;

473

else

473

else

474

reg &= ~LCD_SYNC_CTRL;

474

reg &= ~LCD_SYNC_CTRL;

475

476

if (cfg->sync_edge)

476

if (cfg->sync_edge)

477

reg |= LCD_SYNC_EDGE;

477

reg |= LCD_SYNC_EDGE;

478

else

478

else

479

reg &= ~LCD_SYNC_EDGE;

479

reg &= ~LCD_SYNC_EDGE;

480

481

if (cfg->invert_line_clock)

481

if (cfg->invert_line_clock)

482

reg |= LCD_INVERT_LINE_CLOCK;

482

reg |= LCD_INVERT_LINE_CLOCK;

483

else

483

else

484

reg &= ~LCD_INVERT_LINE_CLOCK;

484

reg &= ~LCD_INVERT_LINE_CLOCK;

485

486

if (cfg->invert_frm_clock)

486

if (cfg->invert_frm_clock)

487

reg |= LCD_INVERT_FRAME_CLOCK;

487

reg |= LCD_INVERT_FRAME_CLOCK;

488

else

488

else

489

reg &= ~LCD_INVERT_FRAME_CLOCK;

489

reg &= ~LCD_INVERT_FRAME_CLOCK;

490

491

lcdc_write(reg, LCD_RASTER_TIMING_2_REG);

491

lcdc_write(reg, LCD_RASTER_TIMING_2_REG);

492

493

return 0;

493

return 0;

494

}

494

}

495

496

static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,

496

static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,

497

u32 bpp, u32 raster_order)

497

u32 bpp, u32 raster_order)

498

{

498

{

499

u32 reg;

499

u32 reg;

500

501

/* Set the Panel Width */

501

/* Set the Panel Width */

502

/* Pixels per line = (PPL + 1)*16 */

502

/* Pixels per line = (PPL + 1)*16 */

503

if (lcd_revision == LCD_VERSION_1) {

503

if (lcd_revision == LCD_VERSION_1) {

504

/*

504

/*

505

* 0x3F in bits 4..9 gives max horizontal resolution = 1024

505

* 0x3F in bits 4..9 gives max horizontal resolution = 1024

506

* pixels.

506

* pixels.

507

*/

507

*/

508

width &= 0x3f0;

508

width &= 0x3f0;

509

} else {

509

} else {

510

/*

510

/*

511

* 0x7F in bits 4..10 gives max horizontal resolution = 2048

511

* 0x7F in bits 4..10 gives max horizontal resolution = 2048

512

* pixels.

512

* pixels.

513

*/

513

*/

514

width &= 0x7f0;

514

width &= 0x7f0;

515

}

515

}

516

517

reg = lcdc_read(LCD_RASTER_TIMING_0_REG);

517

reg = lcdc_read(LCD_RASTER_TIMING_0_REG);

518

reg &= 0xfffffc00;

518

reg &= 0xfffffc00;

519

if (lcd_revision == LCD_VERSION_1) {

519

if (lcd_revision == LCD_VERSION_1) {

520

reg |= ((width >> 4) - 1) << 4;

520

reg |= ((width >> 4) - 1) << 4;

521

} else {

521

} else {

522

width = (width >> 4) - 1;

522

width = (width >> 4) - 1;

523

reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);

523

reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);

524

}

524

}

525

lcdc_write(reg, LCD_RASTER_TIMING_0_REG);

525

lcdc_write(reg, LCD_RASTER_TIMING_0_REG);

526

527

/* Set the Panel Height */

527

/* Set the Panel Height */

528

/* Set bits 9:0 of Lines Per Pixel */

528

/* Set bits 9:0 of Lines Per Pixel */

529

reg = lcdc_read(LCD_RASTER_TIMING_1_REG);

529

reg = lcdc_read(LCD_RASTER_TIMING_1_REG);

530

reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);

530

reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);

531

lcdc_write(reg, LCD_RASTER_TIMING_1_REG);

531

lcdc_write(reg, LCD_RASTER_TIMING_1_REG);

532

533

/* Set bit 10 of Lines Per Pixel */

533

/* Set bit 10 of Lines Per Pixel */

534

if (lcd_revision == LCD_VERSION_2) {

534

if (lcd_revision == LCD_VERSION_2) {

535

reg = lcdc_read(LCD_RASTER_TIMING_2_REG);

535

reg = lcdc_read(LCD_RASTER_TIMING_2_REG);

536

reg |= ((height - 1) & 0x400) << 16;

536

reg |= ((height - 1) & 0x400) << 16;

537

lcdc_write(reg, LCD_RASTER_TIMING_2_REG);

537

lcdc_write(reg, LCD_RASTER_TIMING_2_REG);

538

}

538

}

539

540

/* Set the Raster Order of the Frame Buffer */

540

/* Set the Raster Order of the Frame Buffer */

541

reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);

541

reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);

542

if (raster_order)

542

if (raster_order)

543

reg |= LCD_RASTER_ORDER;

543

reg |= LCD_RASTER_ORDER;

544

545

if (bpp == 24)

545

if (bpp == 24)

546

reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);

546

reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);

547

else if (bpp == 32)

547

else if (bpp == 32)

548

reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE

548

reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE

549

| LCD_V2_TFT_24BPP_UNPACK);

549

| LCD_V2_TFT_24BPP_UNPACK);

550

551

lcdc_write(reg, LCD_RASTER_CTRL_REG);

551

lcdc_write(reg, LCD_RASTER_CTRL_REG);

552

553

switch (bpp) {

553

switch (bpp) {

554

case 1:

554

case 1:

555

case 2:

555

case 2:

556

case 4:

556

case 4:

557

case 16:

557

case 16:

558

case 24:

558

case 24:

559

case 32:

559

case 32:

560

par->palette_sz = 16 * 2;

560

par->palette_sz = 16 * 2;

561

break;

561

break;

562

563

case 8:

563

case 8:

564

par->palette_sz = 256 * 2;

564

par->palette_sz = 256 * 2;

565

break;

565

break;

566

567

default:

567

default:

568

return -EINVAL;

568

return -EINVAL;

569

}

569

}

570

571

return 0;

571

return 0;

572

}

572

}

573

574

static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,

574

static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,

575

unsigned blue, unsigned transp,

575

unsigned blue, unsigned transp,

576

struct fb_info *info)

576

struct fb_info *info)

577

{

577

{

578

struct da8xx_fb_par *par = info->par;

578

struct da8xx_fb_par *par = info->par;

579

unsigned short *palette = (unsigned short *) par->v_palette_base;

579

unsigned short *palette = (unsigned short *) par->v_palette_base;

580

u_short pal;

580

u_short pal;

581

int update_hw = 0;

581

int update_hw = 0;

582

583

if (regno > 255)

583

if (regno > 255)

584

return 1;

584

return 1;

585

586

if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)

586

if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)

587

return 1;

587

return 1;

588

589

if (info->var.bits_per_pixel == 8) {

589

if (info->var.bits_per_pixel == 8) {

590

red >>= 4;

590

red >>= 4;

591

green >>= 8;

591

green >>= 8;

592

blue >>= 12;

592

blue >>= 12;

593

594

pal = (red & 0x0f00);

594

pal = (red & 0x0f00);

595

pal |= (green & 0x00f0);

595

pal |= (green & 0x00f0);

596

pal |= (blue & 0x000f);

596

pal |= (blue & 0x000f);

597

598

if (palette[regno] != pal) {

598

if (palette[regno] != pal) {

599

update_hw = 1;

599

update_hw = 1;

600

palette[regno] = pal;

600

palette[regno] = pal;

601

}

601

}

602

} else if ((info->var.bits_per_pixel == 16) && regno < 16) {

602

} else if ((info->var.bits_per_pixel == 16) && regno < 16) {

603

red >>= (16 - info->var.red.length);

603

red >>= (16 - info->var.red.length);

604

red <<= info->var.red.offset;

604

red <<= info->var.red.offset;

605

606

green >>= (16 - info->var.green.length);

606

green >>= (16 - info->var.green.length);

607

green <<= info->var.green.offset;

607

green <<= info->var.green.offset;

608

609

blue >>= (16 - info->var.blue.length);

609

blue >>= (16 - info->var.blue.length);

610

blue <<= info->var.blue.offset;

610

blue <<= info->var.blue.offset;

611

612

par->pseudo_palette[regno] = red | green | blue;

612

par->pseudo_palette[regno] = red | green | blue;

613

614

if (palette[0] != 0x4000) {

614

if (palette[0] != 0x4000) {

615

update_hw = 1;

615

update_hw = 1;

616

palette[0] = 0x4000;

616

palette[0] = 0x4000;

617

}

617

}

618

} else if (((info->var.bits_per_pixel == 32) && regno < 32) ||

618

} else if (((info->var.bits_per_pixel == 32) && regno < 32) ||

619

((info->var.bits_per_pixel == 24) && regno < 24)) {

619

((info->var.bits_per_pixel == 24) && regno < 24)) {

620

red >>= (24 - info->var.red.length);

620

red >>= (24 - info->var.red.length);

621

red <<= info->var.red.offset;

621

red <<= info->var.red.offset;

622

623

green >>= (24 - info->var.green.length);

623

green >>= (24 - info->var.green.length);

624

green <<= info->var.green.offset;

624

green <<= info->var.green.offset;

625

626

blue >>= (24 - info->var.blue.length);

626

blue >>= (24 - info->var.blue.length);

627

blue <<= info->var.blue.offset;

627

blue <<= info->var.blue.offset;

628

629

par->pseudo_palette[regno] = red | green | blue;

629

par->pseudo_palette[regno] = red | green | blue;

630

631

if (palette[0] != 0x4000) {

631

if (palette[0] != 0x4000) {

632

update_hw = 1;

632

update_hw = 1;

633

palette[0] = 0x4000;

633

palette[0] = 0x4000;

634

}

634

}

635

}

635

}

636

637

/* Update the palette in the h/w as needed. */

637

/* Update the palette in the h/w as needed. */

638

if (update_hw)

638

if (update_hw)

639

lcd_blit(LOAD_PALETTE, par);

639

lcd_blit(LOAD_PALETTE, par);

640

641

return 0;

641

return 0;

642

}

642

}

643

644

static void lcd_reset(struct da8xx_fb_par *par)

644

static void lcd_reset(struct da8xx_fb_par *par)

645

{

645

{

646

/* Disable the Raster if previously Enabled */

646

/* Disable the Raster if previously Enabled */

647

lcd_disable_raster();

647

lcd_disable_raster();

648

649

/* DMA has to be disabled */

649

/* DMA has to be disabled */

650

lcdc_write(0, LCD_DMA_CTRL_REG);

650

lcdc_write(0, LCD_DMA_CTRL_REG);

651

lcdc_write(0, LCD_RASTER_CTRL_REG);

651

lcdc_write(0, LCD_RASTER_CTRL_REG);

652

653

if (lcd_revision == LCD_VERSION_2) {

653

if (lcd_revision == LCD_VERSION_2) {

654

lcdc_write(0, LCD_INT_ENABLE_SET_REG);

654

lcdc_write(0, LCD_INT_ENABLE_SET_REG);

655

/* Write 1 to reset */

655

/* Write 1 to reset */

656

lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);

656

lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);

657

lcdc_write(0, LCD_CLK_RESET_REG);

657

lcdc_write(0, LCD_CLK_RESET_REG);

658

}

658

}

659

}

659

}

660

661

static void lcd_calc_clk_divider(struct da8xx_fb_par *par)

661

static void lcd_calc_clk_divider(struct da8xx_fb_par *par)

662

{

662

{

663

unsigned int lcd_clk, div;

663

unsigned int lcd_clk, div;

664

665

lcd_clk = clk_get_rate(par->lcdc_clk);

665

lcd_clk = clk_get_rate(par->lcdc_clk);

666

div = lcd_clk / par->pxl_clk;

666

div = lcd_clk / par->pxl_clk;

667

668

/* Configure the LCD clock divisor. */

668

/* Configure the LCD clock divisor. */

669

lcdc_write(LCD_CLK_DIVISOR(div) |

669

lcdc_write(LCD_CLK_DIVISOR(div) |

670

(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);

670

(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);

671

672

if (lcd_revision == LCD_VERSION_2)

672

if (lcd_revision == LCD_VERSION_2)

673

lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |

673

lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |

674

LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);

674

LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);

675

676

}

676

}

677

678

static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,

678

static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,

679

struct da8xx_panel *panel)

679

struct da8xx_panel *panel)

680

{

680

{

681

u32 bpp;

681

u32 bpp;

682

int ret = 0;

682

int ret = 0;

683

684

lcd_reset(par);

684

lcd_reset(par);

685

686

/* Calculate the divider */

686

/* Calculate the divider */

687

lcd_calc_clk_divider(par);

687

lcd_calc_clk_divider(par);

688

689

if (panel->invert_pxl_clk)

689

if (panel->invert_pxl_clk)

690

lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |

690

lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |

691

LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);

691

LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);

692

else

692

else

693

lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &

693

lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &

694

~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);

694

~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);

695

696

/* Configure the DMA burst size and fifo threshold. */

696

/* Configure the DMA burst size and fifo threshold. */

697

ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);

697

ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);

698

if (ret < 0)

698

if (ret < 0)

699

return ret;

699

return ret;

700

701

/* Configure the AC bias properties. */

701

/* Configure the AC bias properties. */

702

lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);

702

lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);

703

704

/* Configure the vertical and horizontal sync properties. */

704

/* Configure the vertical and horizontal sync properties. */

705

lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);

705

lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);

706

lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);

706

lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);

707

708

/* Configure for disply */

708

/* Configure for disply */

709

ret = lcd_cfg_display(cfg);

709

ret = lcd_cfg_display(cfg);

710

if (ret < 0)

710

if (ret < 0)

711

return ret;

711

return ret;

712

713

714

if ((QVGA != cfg->p_disp_panel->panel_type) &&

714

if ((QVGA != cfg->p_disp_panel->panel_type) &&

715

(WVGA != cfg->p_disp_panel->panel_type))

715

(WVGA != cfg->p_disp_panel->panel_type))

716

return -EINVAL;

716

return -EINVAL;

717

718

if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&

718

if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&

719

cfg->bpp >= cfg->p_disp_panel->min_bpp)

719

cfg->bpp >= cfg->p_disp_panel->min_bpp)

720

bpp = cfg->bpp;

720

bpp = cfg->bpp;

721

else

721

else

722

bpp = cfg->p_disp_panel->max_bpp;

722

bpp = cfg->p_disp_panel->max_bpp;

723

if (bpp == 12)

723

if (bpp == 12)

724

bpp = 16;

724

bpp = 16;

725

ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,

725

ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,

726

(unsigned int)panel->height, bpp,

726

(unsigned int)panel->height, bpp,

727

cfg->raster_order);

727

cfg->raster_order);

728

if (ret < 0)

728

if (ret < 0)

729

return ret;

729

return ret;

730

731

/* Configure FDD */

731

/* Configure FDD */

732

lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |

732

lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |

733

(cfg->fdd << 12), LCD_RASTER_CTRL_REG);

733

(cfg->fdd << 12), LCD_RASTER_CTRL_REG);

734

735

return 0;

735

return 0;

736

}

736

}

737

738

int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)

738

int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)

739

{

739

{

740

if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {

740

if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {

741

vsync_cb_handler = handler;

741

vsync_cb_handler = handler;

742

vsync_cb_arg = arg;

742

vsync_cb_arg = arg;

743

} else {

743

} else {

744

return -EEXIST;

744

return -EEXIST;

745

}

745

}

746

747

return 0;

747

return 0;

748

}

748

}

749

EXPORT_SYMBOL(register_vsync_cb);

749

EXPORT_SYMBOL(register_vsync_cb);

750

751

int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)

751

int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)

752

{

752

{

753

if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {

753

if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {

754

vsync_cb_handler = NULL;

754

vsync_cb_handler = NULL;

755

vsync_cb_arg = NULL;

755

vsync_cb_arg = NULL;

756

} else {

756

} else {

757

return -ENXIO;

757

return -ENXIO;

758

}

758

}

759

760

return 0;

760

return 0;

761

}

761

}

762

EXPORT_SYMBOL(unregister_vsync_cb);

762

EXPORT_SYMBOL(unregister_vsync_cb);

763

764

/* IRQ handler for version 2 of LCDC */

764

/* IRQ handler for version 2 of LCDC */

765

static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)

765

static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)

766

{

766

{

767

struct da8xx_fb_par *par = arg;

767

struct da8xx_fb_par *par = arg;

768

u32 stat = lcdc_read(LCD_MASKED_STAT_REG);

768

u32 stat = lcdc_read(LCD_MASKED_STAT_REG);

769

u32 reg_int;

769

u32 reg_int;

770

771

if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {

771

if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {

772

printk(KERN_ERR "LCDC sync lost or underflow error occured\n");

772

lcd_disable_raster();

773

lcd_disable_raster();

773

clk_disable(par->lcdc_clk);

774

clk_disable(par->lcdc_clk);

774

lcdc_write(stat, LCD_MASKED_STAT_REG);

775

lcdc_write(stat, LCD_MASKED_STAT_REG);

775

lcd_enable_raster();

776

lcd_enable_raster();

776

clk_enable(par->lcdc_clk);

777

clk_enable(par->lcdc_clk);

777

} else if (stat & LCD_PL_LOAD_DONE) {

778

} else if (stat & LCD_PL_LOAD_DONE) {

778

/*

779

/*

779

* Must disable raster before changing state of any control bit.

780

* Must disable raster before changing state of any control bit.

780

* And also must be disabled before clearing the PL loading

781

* And also must be disabled before clearing the PL loading

781

* interrupt via the following write to the status register. If

782

* interrupt via the following write to the status register. If

782

* this is done after then one gets multiple PL done interrupts.

783

* this is done after then one gets multiple PL done interrupts.

783

*/

784

*/

784

lcd_disable_raster();

785

lcd_disable_raster();

785

786

lcdc_write(stat, LCD_MASKED_STAT_REG);

787

lcdc_write(stat, LCD_MASKED_STAT_REG);

787

788

/* Disable PL completion inerrupt */

789

/* Disable PL completion inerrupt */

789

reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |

790

reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |

790

(LCD_V2_PL_INT_ENA);

791

(LCD_V2_PL_INT_ENA);

791

lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);

792

lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);

792

793

/* Setup and start data loading mode */

794

/* Setup and start data loading mode */

794

lcd_blit(LOAD_DATA, par);

795

lcd_blit(LOAD_DATA, par);

795

} else {

796

} else {

796

lcdc_write(stat, LCD_MASKED_STAT_REG);

797

lcdc_write(stat, LCD_MASKED_STAT_REG);

797

798

if (stat & LCD_END_OF_FRAME0) {

799

if (stat & LCD_END_OF_FRAME0) {

799

par->which_dma_channel_done = 0;

800

par->which_dma_channel_done = 0;

800

lcdc_write(par->dma_start,

801

lcdc_write(par->dma_start,

801

LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

802

LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

802

lcdc_write(par->dma_end,

803

lcdc_write(par->dma_end,

803

LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

804

LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

804

par->vsync_flag = 1;

805

par->vsync_flag = 1;

805

wake_up_interruptible(&par->vsync_wait);

806

wake_up_interruptible(&par->vsync_wait);

806

if (vsync_cb_handler)

807

if (vsync_cb_handler)

807

vsync_cb_handler(vsync_cb_arg);

808

vsync_cb_handler(vsync_cb_arg);

808

}

809

}

809

810

if (stat & LCD_END_OF_FRAME1) {

811

if (stat & LCD_END_OF_FRAME1) {

811

par->which_dma_channel_done = 1;

812

par->which_dma_channel_done = 1;

812

lcdc_write(par->dma_start,

813

lcdc_write(par->dma_start,

813

LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

814

LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

814

lcdc_write(par->dma_end,

815

lcdc_write(par->dma_end,

815

LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

816

LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

816

par->vsync_flag = 1;

817

par->vsync_flag = 1;

817

wake_up_interruptible(&par->vsync_wait);

818

wake_up_interruptible(&par->vsync_wait);

818

if (vsync_cb_handler)

819

if (vsync_cb_handler)

819

vsync_cb_handler(vsync_cb_arg);

820

vsync_cb_handler(vsync_cb_arg);

820

}

821

}

821

}

822

}

822

823

lcdc_write(0, LCD_END_OF_INT_IND_REG);

824

lcdc_write(0, LCD_END_OF_INT_IND_REG);

824

return IRQ_HANDLED;

825

return IRQ_HANDLED;

825

}

826

}

826

827

/* IRQ handler for version 1 LCDC */

828

/* IRQ handler for version 1 LCDC */

828

static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)

829

static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)

829

{

830

{

830

struct da8xx_fb_par *par = arg;

831

struct da8xx_fb_par *par = arg;

831

u32 stat = lcdc_read(LCD_STAT_REG);

832

u32 stat = lcdc_read(LCD_STAT_REG);

832

u32 reg_ras;

833

u32 reg_ras;

833

834

if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {

835

if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {

836

printk(KERN_ERR "LCDC sync lost or underflow error occured\n");

835

lcd_disable_raster();

837

lcd_disable_raster();

836

clk_disable(par->lcdc_clk);

838

clk_disable(par->lcdc_clk);

837

lcdc_write(stat, LCD_STAT_REG);

839

lcdc_write(stat, LCD_STAT_REG);

838

lcd_enable_raster();

840

lcd_enable_raster();

839

clk_enable(par->lcdc_clk);

841

clk_enable(par->lcdc_clk);

840

} else if (stat & LCD_PL_LOAD_DONE) {

842

} else if (stat & LCD_PL_LOAD_DONE) {

841

/*

843

/*

842

* Must disable raster before changing state of any control bit.

844

* Must disable raster before changing state of any control bit.

843

* And also must be disabled before clearing the PL loading

845

* And also must be disabled before clearing the PL loading

844

* interrupt via the following write to the status register. If

846

* interrupt via the following write to the status register. If

845

* this is done after then one gets multiple PL done interrupts.

847

* this is done after then one gets multiple PL done interrupts.

846

*/

848

*/

847

lcd_disable_raster();

849

lcd_disable_raster();

848

850

849

lcdc_write(stat, LCD_STAT_REG);

851

lcdc_write(stat, LCD_STAT_REG);

850

852

851

/* Disable PL completion inerrupt */

853

/* Disable PL completion inerrupt */

852

reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);

854

reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);

853

reg_ras &= ~LCD_V1_PL_INT_ENA;

855

reg_ras &= ~LCD_V1_PL_INT_ENA;

854

lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);

856

lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);

855

857

856

/* Setup and start data loading mode */

858

/* Setup and start data loading mode */

857

lcd_blit(LOAD_DATA, par);

859

lcd_blit(LOAD_DATA, par);

858

} else {

860

} else {

859

lcdc_write(stat, LCD_STAT_REG);

861

lcdc_write(stat, LCD_STAT_REG);

860

862

861

if (stat & LCD_END_OF_FRAME0) {

863

if (stat & LCD_END_OF_FRAME0) {

862

lcdc_write(par->dma_start,

864

lcdc_write(par->dma_start,

863

LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

865

LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

864

lcdc_write(par->dma_end,

866

lcdc_write(par->dma_end,

865

LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

867

LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

866

par->vsync_flag = 1;

868

par->vsync_flag = 1;

867

wake_up_interruptible(&par->vsync_wait);

869

wake_up_interruptible(&par->vsync_wait);

868

}

870

}

869

871

870

if (stat & LCD_END_OF_FRAME1) {

872

if (stat & LCD_END_OF_FRAME1) {

871

lcdc_write(par->dma_start,

873

lcdc_write(par->dma_start,

872

LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

874

LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

873

lcdc_write(par->dma_end,

875

lcdc_write(par->dma_end,

874

LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

876

LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

875

par->vsync_flag = 1;

877

par->vsync_flag = 1;

876

wake_up_interruptible(&par->vsync_wait);

878

wake_up_interruptible(&par->vsync_wait);

877

}

879

}

878

}

880

}

879

881

880

return IRQ_HANDLED;

882

return IRQ_HANDLED;

881

}

883

}

882

884

883

static int fb_check_var(struct fb_var_screeninfo *var,

885

static int fb_check_var(struct fb_var_screeninfo *var,

884

struct fb_info *info)

886

struct fb_info *info)

885

{

887

{

886

int err = 0;

888

int err = 0;

887

889

888

switch (var->bits_per_pixel) {

890

switch (var->bits_per_pixel) {

889

case 1:

891

case 1:

890

case 8:

892

case 8:

891

var->red.offset = 0;

893

var->red.offset = 0;

892

var->red.length = 8;

894

var->red.length = 8;

893

var->green.offset = 0;

895

var->green.offset = 0;

894

var->green.length = 8;

896

var->green.length = 8;

895

var->blue.offset = 0;

897

var->blue.offset = 0;

896

var->blue.length = 8;

898

var->blue.length = 8;

897

var->transp.offset = 0;

899

var->transp.offset = 0;

898

var->transp.length = 0;

900

var->transp.length = 0;

899

break;

901

break;

900

case 4:

902

case 4:

901

var->red.offset = 0;

903

var->red.offset = 0;

902

var->red.length = 4;

904

var->red.length = 4;

903

var->green.offset = 0;

905

var->green.offset = 0;

904

var->green.length = 4;

906

var->green.length = 4;

905

var->blue.offset = 0;

907

var->blue.offset = 0;

906

var->blue.length = 4;

908

var->blue.length = 4;

907

var->transp.offset = 0;

909

var->transp.offset = 0;

908

var->transp.length = 0;

910

var->transp.length = 0;

909

break;

911

break;

910

case 16: /* RGB 565 */

912

case 16: /* RGB 565 */

911

var->red.offset = 11;

913

var->red.offset = 11;

912

var->red.length = 5;

914

var->red.length = 5;

913

var->green.offset = 5;

915

var->green.offset = 5;

914

var->green.length = 6;

916

var->green.length = 6;

915

var->blue.offset = 0;

917

var->blue.offset = 0;

916

var->blue.length = 5;

918

var->blue.length = 5;

917

var->transp.offset = 0;

919

var->transp.offset = 0;

918

var->transp.length = 0;

920

var->transp.length = 0;

919

break;

921

break;

920

case 24:

922

case 24:

921

var->red.offset = 16;

923

var->red.offset = 16;

922

var->red.length = 8;

924

var->red.length = 8;

923

var->green.offset = 8;

925

var->green.offset = 8;

924

var->green.length = 8;

926

var->green.length = 8;

925

var->blue.offset = 0;

927

var->blue.offset = 0;

926

var->blue.length = 8;

928

var->blue.length = 8;

927

break;

929

break;

928

case 32:

930

case 32:

929

var->transp.offset = 24;

931

var->transp.offset = 24;

930

var->transp.length = 8;

932

var->transp.length = 8;

931

var->red.offset = 16;

933

var->red.offset = 16;

932

var->red.length = 8;

934

var->red.length = 8;

933

var->green.offset = 8;

935

var->green.offset = 8;

934

var->green.length = 8;

936

var->green.length = 8;

935

var->blue.offset = 0;

937

var->blue.offset = 0;

936

var->blue.length = 8;

938

var->blue.length = 8;

937

break;

939

break;

938

default:

940

default:

939

err = -EINVAL;

941

err = -EINVAL;

940

}

942

}

941

943

942

var->red.msb_right = 0;

944

var->red.msb_right = 0;

943

var->green.msb_right = 0;

945

var->green.msb_right = 0;

944

var->blue.msb_right = 0;

946

var->blue.msb_right = 0;

945

var->transp.msb_right = 0;

947

var->transp.msb_right = 0;

946

return err;

948

return err;

947

}

949

}

948

950

949

#ifdef CONFIG_CPU_FREQ

951

#ifdef CONFIG_CPU_FREQ

950

static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,

952

static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,

951

unsigned long val, void *data)

953

unsigned long val, void *data)

952

{

954

{

953

struct da8xx_fb_par *par;

955

struct da8xx_fb_par *par;

954

956

955

par = container_of(nb, struct da8xx_fb_par, freq_transition);

957

par = container_of(nb, struct da8xx_fb_par, freq_transition);

956

if (val == CPUFREQ_PRECHANGE) {

958

if (val == CPUFREQ_PRECHANGE) {

957

lcd_disable_raster();

959

lcd_disable_raster();

958

} else if (val == CPUFREQ_POSTCHANGE) {

960

} else if (val == CPUFREQ_POSTCHANGE) {

959

lcd_calc_clk_divider(par);

961

lcd_calc_clk_divider(par);

960

lcd_enable_raster();

962

lcd_enable_raster();

961

}

963

}

962

964

963

return 0;

965

return 0;

964

}

966

}

965

967

966

static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)

968

static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)

967

{

969

{

968

par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;

970

par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;

969

971

970

return cpufreq_register_notifier(&par->freq_transition,

972

return cpufreq_register_notifier(&par->freq_transition,

971

CPUFREQ_TRANSITION_NOTIFIER);

973

CPUFREQ_TRANSITION_NOTIFIER);

972

}

974

}

973

975

974

static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)

976

static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)

975

{

977

{

976

cpufreq_unregister_notifier(&par->freq_transition,

978

cpufreq_unregister_notifier(&par->freq_transition,

977

CPUFREQ_TRANSITION_NOTIFIER);

979

CPUFREQ_TRANSITION_NOTIFIER);

978

}

980

}

979

#endif

981

#endif

980

982

981

static int __devexit fb_remove(struct platform_device *dev)

983

static int __devexit fb_remove(struct platform_device *dev)

982

{

984

{

983

struct fb_info *info = dev_get_drvdata(&dev->dev);

985

struct fb_info *info = dev_get_drvdata(&dev->dev);

984

986

985

if (info) {

987

if (info) {

986

struct da8xx_fb_par *par = info->par;

988

struct da8xx_fb_par *par = info->par;

987

989

988

#ifdef CONFIG_CPU_FREQ

990

#ifdef CONFIG_CPU_FREQ

989

lcd_da8xx_cpufreq_deregister(par);

991

lcd_da8xx_cpufreq_deregister(par);

990

#endif

992

#endif

991

if (par->panel_power_ctrl)

993

if (par->panel_power_ctrl)

992

par->panel_power_ctrl(0);

994

par->panel_power_ctrl(0);

993

995

994

lcd_disable_raster();

996

lcd_disable_raster();

995

lcdc_write(0, LCD_RASTER_CTRL_REG);

997

lcdc_write(0, LCD_RASTER_CTRL_REG);

996

998

997

/* disable DMA */

999

/* disable DMA */

998

lcdc_write(0, LCD_DMA_CTRL_REG);

1000

lcdc_write(0, LCD_DMA_CTRL_REG);

999

1001

1000

unregister_framebuffer(info);

1002

unregister_framebuffer(info);

1001

fb_dealloc_cmap(&info->cmap);

1003

fb_dealloc_cmap(&info->cmap);

1002

dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,

1004

dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,

1003

par->p_palette_base);

1005

par->p_palette_base);

1004

dma_free_coherent(NULL, par->vram_size, par->vram_virt,

1006

dma_free_coherent(NULL, par->vram_size, par->vram_virt,

1005

par->vram_phys);

1007

par->vram_phys);

1006

free_irq(par->irq, par);

1008

free_irq(par->irq, par);

1007

clk_disable(par->lcdc_clk);

1009

clk_disable(par->lcdc_clk);

1008

clk_put(par->lcdc_clk);

1010

clk_put(par->lcdc_clk);

1009

framebuffer_release(info);

1011

framebuffer_release(info);

1010

iounmap((void __iomem *)da8xx_fb_reg_base);

1012

iounmap((void __iomem *)da8xx_fb_reg_base);

1011

release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));

1013

release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));

1012

1014

1013

}

1015

}

1014

return 0;

1016

return 0;

1015

}

1017

}

1016

1018

1017

/*

1019

/*

1018

* Function to wait for vertical sync which for this LCD peripheral

1020

* Function to wait for vertical sync which for this LCD peripheral

1019

* translates into waiting for the current raster frame to complete.

1021

* translates into waiting for the current raster frame to complete.

1020

*/

1022

*/

1021

static int fb_wait_for_vsync(struct fb_info *info)

1023

static int fb_wait_for_vsync(struct fb_info *info)

1022

{

1024

{

1023

struct da8xx_fb_par *par = info->par;

1025

struct da8xx_fb_par *par = info->par;

1024

int ret;

1026

int ret;

1025

1027

1026

/*

1028

/*

1027

* Set flag to 0 and wait for isr to set to 1. It would seem there is a

1029

* Set flag to 0 and wait for isr to set to 1. It would seem there is a

1028

* race condition here where the ISR could have occurred just before or

1030

* race condition here where the ISR could have occurred just before or

1029

* just after this set. But since we are just coarsely waiting for

1031

* just after this set. But since we are just coarsely waiting for

1030

* a frame to complete then that's OK. i.e. if the frame completed

1032

* a frame to complete then that's OK. i.e. if the frame completed

1031

* just before this code executed then we have to wait another full

1033

* just before this code executed then we have to wait another full

1032

* frame time but there is no way to avoid such a situation. On the

1034

* frame time but there is no way to avoid such a situation. On the

1033

* other hand if the frame completed just after then we don't need

1035

* other hand if the frame completed just after then we don't need

1034

* to wait long at all. Either way we are guaranteed to return to the

1036

* to wait long at all. Either way we are guaranteed to return to the

1035

* user immediately after a frame completion which is all that is

1037

* user immediately after a frame completion which is all that is

1036

* required.

1038

* required.

1037

*/

1039

*/

1038

par->vsync_flag = 0;

1040

par->vsync_flag = 0;

1039

ret = wait_event_interruptible_timeout(par->vsync_wait,

1041

ret = wait_event_interruptible_timeout(par->vsync_wait,

1040

par->vsync_flag != 0,

1042

par->vsync_flag != 0,

1041

par->vsync_timeout);

1043

par->vsync_timeout);

1042

if (ret < 0)

1044

if (ret < 0)

1043

return ret;

1045

return ret;

1044

if (ret == 0)

1046

if (ret == 0)

1045

return -ETIMEDOUT;

1047

return -ETIMEDOUT;

1046

1048

1047

if (par->panel_power_ctrl) {

1049

if (par->panel_power_ctrl) {

1048

/* Switch off panel power and backlight */

1050

/* Switch off panel power and backlight */

1049

par->panel_power_ctrl(0);

1051

par->panel_power_ctrl(0);

1050

1052

1051

/* Switch on panel power and backlight */

1053

/* Switch on panel power and backlight */

1052

par->panel_power_ctrl(1);

1054

par->panel_power_ctrl(1);

1053

}

1055

}

1054

1056

1055

return 0;

1057

return 0;

1056

}

1058

}

1057

1059

1058

static int fb_ioctl(struct fb_info *info, unsigned int cmd,

1060

static int fb_ioctl(struct fb_info *info, unsigned int cmd,

1059

unsigned long arg)

1061

unsigned long arg)

1060

{

1062

{

1061

struct lcd_sync_arg sync_arg;

1063

struct lcd_sync_arg sync_arg;

1062

1064

1063

switch (cmd) {

1065

switch (cmd) {

1064

case FBIOGET_CONTRAST:

1066

case FBIOGET_CONTRAST:

1065

case FBIOPUT_CONTRAST:

1067

case FBIOPUT_CONTRAST:

1066

case FBIGET_BRIGHTNESS:

1068

case FBIGET_BRIGHTNESS:

1067

case FBIPUT_BRIGHTNESS:

1069

case FBIPUT_BRIGHTNESS:

1068

case FBIGET_COLOR:

1070

case FBIGET_COLOR:

1069

case FBIPUT_COLOR:

1071

case FBIPUT_COLOR:

1070

return -ENOTTY;

1072

return -ENOTTY;

1071

case FBIPUT_HSYNC:

1073

case FBIPUT_HSYNC:

1072

if (copy_from_user(&sync_arg, (char *)arg,

1074

if (copy_from_user(&sync_arg, (char *)arg,

1073

sizeof(struct lcd_sync_arg)))

1075

sizeof(struct lcd_sync_arg)))

1074

return -EFAULT;

1076

return -EFAULT;

1075

lcd_cfg_horizontal_sync(sync_arg.back_porch,

1077

lcd_cfg_horizontal_sync(sync_arg.back_porch,

1076

sync_arg.pulse_width,

1078

sync_arg.pulse_width,

1077

sync_arg.front_porch);

1079

sync_arg.front_porch);

1078

break;

1080

break;

1079

case FBIPUT_VSYNC:

1081

case FBIPUT_VSYNC:

1080

if (copy_from_user(&sync_arg, (char *)arg,

1082

if (copy_from_user(&sync_arg, (char *)arg,

1081

sizeof(struct lcd_sync_arg)))

1083

sizeof(struct lcd_sync_arg)))

1082

return -EFAULT;

1084

return -EFAULT;

1083

lcd_cfg_vertical_sync(sync_arg.back_porch,

1085

lcd_cfg_vertical_sync(sync_arg.back_porch,

1084

sync_arg.pulse_width,

1086

sync_arg.pulse_width,

1085

sync_arg.front_porch);

1087

sync_arg.front_porch);

1086

break;

1088

break;

1087

case FBIO_WAITFORVSYNC:

1089

case FBIO_WAITFORVSYNC:

1088

return fb_wait_for_vsync(info);

1090

return fb_wait_for_vsync(info);

1089

default:

1091

default:

1090

return -EINVAL;

1092

return -EINVAL;

1091

}

1093

}

1092

return 0;

1094

return 0;

1093

}

1095

}

1094

1096

1095

static int cfb_blank(int blank, struct fb_info *info)

1097

static int cfb_blank(int blank, struct fb_info *info)

1096

{

1098

{

1097

struct da8xx_fb_par *par = info->par;

1099

struct da8xx_fb_par *par = info->par;

1098

int ret = 0;

1100

int ret = 0;

1099

1101

1100

if (par->blank == blank)

1102

if (par->blank == blank)

1101

return 0;

1103

return 0;

1102

1104

1103

par->blank = blank;

1105

par->blank = blank;

1104

switch (blank) {

1106

switch (blank) {

1105

case FB_BLANK_UNBLANK:

1107

case FB_BLANK_UNBLANK:

1106

if (par->panel_power_ctrl)

1108

if (par->panel_power_ctrl)

1107

par->panel_power_ctrl(1);

1109

par->panel_power_ctrl(1);

1108

1110

1109

lcd_enable_raster();

1111

lcd_enable_raster();

1110

break;

1112

break;

1111

case FB_BLANK_POWERDOWN:

1113

case FB_BLANK_POWERDOWN:

1112

if (par->panel_power_ctrl)

1114

if (par->panel_power_ctrl)

1113

par->panel_power_ctrl(0);

1115

par->panel_power_ctrl(0);

1114

1116

1115

lcd_disable_raster();

1117

lcd_disable_raster();

1116

break;

1118

break;

1117

default:

1119

default:

1118

ret = -EINVAL;

1120

ret = -EINVAL;

1119

}

1121

}

1120

1122

1121

return ret;

1123

return ret;

1122

}

1124

}

1123

1125

1124

/*

1126

/*

1125

* Set new x,y offsets in the virtual display for the visible area and switch

1127

* Set new x,y offsets in the virtual display for the visible area and switch

1126

* to the new mode.

1128

* to the new mode.

1127

*/

1129

*/

1128

static int da8xx_pan_display(struct fb_var_screeninfo *var,

1130

static int da8xx_pan_display(struct fb_var_screeninfo *var,

1129

struct fb_info *fbi)

1131

struct fb_info *fbi)

1130

{

1132

{

1131

int ret = 0;

1133

int ret = 0;

1132

struct fb_var_screeninfo new_var;

1134

struct fb_var_screeninfo new_var;

1133

struct da8xx_fb_par *par = fbi->par;

1135

struct da8xx_fb_par *par = fbi->par;

1134

struct fb_fix_screeninfo *fix = &fbi->fix;

1136

struct fb_fix_screeninfo *fix = &fbi->fix;

1135

unsigned int end;

1137

unsigned int end;

1136

unsigned int start;

1138

unsigned int start;

1137

unsigned long irq_flags;

1139

unsigned long irq_flags;

1138

1140

1139

if (var->xoffset != fbi->var.xoffset ||

1141

if (var->xoffset != fbi->var.xoffset ||

1140

var->yoffset != fbi->var.yoffset) {

1142

var->yoffset != fbi->var.yoffset) {

1141

memcpy(&new_var, &fbi->var, sizeof(new_var));

1143

memcpy(&new_var, &fbi->var, sizeof(new_var));

1142

new_var.xoffset = var->xoffset;

1144

new_var.xoffset = var->xoffset;

1143

new_var.yoffset = var->yoffset;

1145

new_var.yoffset = var->yoffset;

1144

if (fb_check_var(&new_var, fbi))

1146

if (fb_check_var(&new_var, fbi))

1145

ret = -EINVAL;

1147

ret = -EINVAL;

1146

else {

1148

else {

1147

memcpy(&fbi->var, &new_var, sizeof(new_var));

1149

memcpy(&fbi->var, &new_var, sizeof(new_var));

1148

1150

1149

start = fix->smem_start +

1151

start = fix->smem_start +

1150

new_var.yoffset * fix->line_length +

1152

new_var.yoffset * fix->line_length +

1151

new_var.xoffset * var->bits_per_pixel / 8;

1153

new_var.xoffset * var->bits_per_pixel / 8;

1152

end = start + var->yres * fix->line_length - 1;

1154

end = start + var->yres * fix->line_length - 1;

1153

par->dma_start = start;

1155

par->dma_start = start;

1154

par->dma_end = end;

1156

par->dma_end = end;

1155

spin_lock_irqsave(&par->lock_for_chan_update,

1157

spin_lock_irqsave(&par->lock_for_chan_update,

1156

irq_flags);

1158

irq_flags);

1157

if (par->which_dma_channel_done == 0) {

1159

if (par->which_dma_channel_done == 0) {

1158

lcdc_write(par->dma_start,

1160

lcdc_write(par->dma_start,

1159

LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

1161

LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);

1160

lcdc_write(par->dma_end,

1162

lcdc_write(par->dma_end,

1161

LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

1163

LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);

1162

} else if (par->which_dma_channel_done == 1) {

1164

} else if (par->which_dma_channel_done == 1) {

1163

lcdc_write(par->dma_start,

1165

lcdc_write(par->dma_start,

1164

LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

1166

LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);

1165

lcdc_write(par->dma_end,

1167

lcdc_write(par->dma_end,

1166

LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

1168

LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);

1167

}

1169

}

1168

spin_unlock_irqrestore(&par->lock_for_chan_update,

1170

spin_unlock_irqrestore(&par->lock_for_chan_update,

1169

irq_flags);

1171

irq_flags);

1170

}

1172

}

1171

}

1173

}

1172

1174

1173

return ret;

1175

return ret;

1174

}

1176

}

1175

1177

1176

static struct fb_ops da8xx_fb_ops = {

1178

static struct fb_ops da8xx_fb_ops = {

1177

.owner = THIS_MODULE,

1179

.owner = THIS_MODULE,

1178

.fb_check_var = fb_check_var,

1180

.fb_check_var = fb_check_var,

1179

.fb_setcolreg = fb_setcolreg,

1181

.fb_setcolreg = fb_setcolreg,

1180

.fb_pan_display = da8xx_pan_display,

1182

.fb_pan_display = da8xx_pan_display,

1181

.fb_ioctl = fb_ioctl,

1183

.fb_ioctl = fb_ioctl,

1182

.fb_fillrect = cfb_fillrect,

1184

.fb_fillrect = cfb_fillrect,

1183

.fb_copyarea = cfb_copyarea,

1185

.fb_copyarea = cfb_copyarea,

1184

.fb_imageblit = cfb_imageblit,

1186

.fb_imageblit = cfb_imageblit,

1185

.fb_blank = cfb_blank,

1187

.fb_blank = cfb_blank,

1186

};

1188

};

1187

1189

1188

static int __devinit fb_probe(struct platform_device *device)

1190

static int __devinit fb_probe(struct platform_device *device)

1189

{

1191

{

1190

struct da8xx_lcdc_platform_data *fb_pdata =

1192

struct da8xx_lcdc_platform_data *fb_pdata =

1191

device->dev.platform_data;

1193

device->dev.platform_data;

1192

struct lcd_ctrl_config *lcd_cfg;

1194

struct lcd_ctrl_config *lcd_cfg;

1193

struct da8xx_panel *lcdc_info;

1195

struct da8xx_panel *lcdc_info;

1194

struct fb_info *da8xx_fb_info;

1196

struct fb_info *da8xx_fb_info;

1195

struct clk *fb_clk = NULL;

1197

struct clk *fb_clk = NULL;

1196

struct clk *fb_l3ick = NULL, *fb_l4ick = NULL;

1198

struct clk *fb_l3ick = NULL, *fb_l4ick = NULL;

1197

struct da8xx_fb_par *par;

1199

struct da8xx_fb_par *par;

1198

resource_size_t len;

1200

resource_size_t len;

1199

int ret, i;

1201

int ret, i;

1200

1202

1201

if (fb_pdata == NULL) {

1203

if (fb_pdata == NULL) {

1202

dev_err(&device->dev, "Can not get platform data\n");

1204

dev_err(&device->dev, "Can not get platform data\n");

1203

return -ENOENT;

1205

return -ENOENT;

1204

}

1206

}

1205

1207

1206

lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);

1208

lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);

1207

if (!lcdc_regs) {

1209

if (!lcdc_regs) {

1208

dev_err(&device->dev,

1210

dev_err(&device->dev,

1209

"Can not get memory resource for LCD controller\n");

1211

"Can not get memory resource for LCD controller\n");

1210

return -ENOENT;

1212

return -ENOENT;

1211

}

1213

}

1212

1214

1213

len = resource_size(lcdc_regs);

1215

len = resource_size(lcdc_regs);

1214

1216

1215

lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);

1217

lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);

1216

if (!lcdc_regs)

1218

if (!lcdc_regs)

1217

return -EBUSY;

1219

return -EBUSY;

1218

1220

1219

da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);

1221

da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);

1220

if (!da8xx_fb_reg_base) {

1222

if (!da8xx_fb_reg_base) {

1221

ret = -EBUSY;

1223

ret = -EBUSY;

1222

goto err_request_mem;

1224

goto err_request_mem;

1223

}

1225

}

1224

1226

1225

if (machine_is_am335xevm()) {

1227

if (machine_is_am335xevm()) {

1226

fb_l3ick = clk_get(&device->dev, "lcdc_ick_l3_clk");

1228

fb_l3ick = clk_get(&device->dev, "lcdc_ick_l3_clk");

1227

if (IS_ERR(fb_l3ick)) {

1229

if (IS_ERR(fb_l3ick)) {

1228

dev_err(&device->dev, "Can not get l3 interface"

1230

dev_err(&device->dev, "Can not get l3 interface"

1229

"clock\n");

1231

"clock\n");

1230

ret = -ENODEV;

1232

ret = -ENODEV;

1231

goto err_ioremap;

1233

goto err_ioremap;

1232

}

1234

}

1233

ret = clk_enable(fb_l3ick);

1235

ret = clk_enable(fb_l3ick);

1234

if (ret)

1236

if (ret)

1235

goto err_clk_put0;

1237

goto err_clk_put0;

1236

1238

1237

fb_l4ick = clk_get(&device->dev, "lcdc_ick_l4_clk");

1239

fb_l4ick = clk_get(&device->dev, "lcdc_ick_l4_clk");

1238

if (IS_ERR(fb_l4ick)) {

1240

if (IS_ERR(fb_l4ick)) {

1239

dev_err(&device->dev, "Can not get l4 interface"

1241

dev_err(&device->dev, "Can not get l4 interface"

1240

"clock\n");

1242

"clock\n");

1241

ret = -ENODEV;

1243

ret = -ENODEV;

1242

goto err_clk_get0;

1244

goto err_clk_get0;

1243

}

1245

}

1244

ret = clk_enable(fb_l4ick);

1246

ret = clk_enable(fb_l4ick);

1245

if (ret)

1247

if (ret)

1246

goto err_clk_put1;

1248

goto err_clk_put1;

1247

}

1249

}

1248

1250

1249

fb_clk = clk_get(&device->dev, NULL);

1251

fb_clk = clk_get(&device->dev, NULL);

1250

if (IS_ERR(fb_clk)) {

1252

if (IS_ERR(fb_clk)) {

1251

dev_err(&device->dev, "Can not get device clock\n");

1253

dev_err(&device->dev, "Can not get device clock\n");

1252

ret = -ENODEV;

1254

ret = -ENODEV;

1253

goto err_clk_get1;

1255

goto err_clk_get1;

1254

}

1256

}

1255

ret = clk_enable(fb_clk);

1257

ret = clk_enable(fb_clk);

1256

if (ret)

1258

if (ret)

1257

goto err_clk_put2;

1259

goto err_clk_put2;

1258

1260

1259

/* Determine LCD IP Version */

1261

/* Determine LCD IP Version */

1260

switch (lcdc_read(LCD_PID_REG)) {

1262

switch (lcdc_read(LCD_PID_REG)) {

1261

case 0x4C100102:

1263

case 0x4C100102:

1262

lcd_revision = LCD_VERSION_1;

1264

lcd_revision = LCD_VERSION_1;

1263

break;

1265

break;

1264

case 0x4F200800:

1266

case 0x4F200800:

1265

case 0x4F201000:

1267

case 0x4F201000:

1266

lcd_revision = LCD_VERSION_2;

1268

lcd_revision = LCD_VERSION_2;

1267

break;

1269

break;

1268

default:

1270

default:

1269

dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "

1271

dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "

1270

"defaulting to LCD revision 1\n",

1272

"defaulting to LCD revision 1\n",

1271

lcdc_read(LCD_PID_REG));

1273

lcdc_read(LCD_PID_REG));

1272

lcd_revision = LCD_VERSION_1;

1274

lcd_revision = LCD_VERSION_1;

1273

break;

1275

break;

1274

}

1276

}

1275

1277

1276

for (i = 0, lcdc_info = known_lcd_panels;

1278

for (i = 0, lcdc_info = known_lcd_panels;

1277

i < ARRAY_SIZE(known_lcd_panels);

1279

i < ARRAY_SIZE(known_lcd_panels);

1278

i++, lcdc_info++) {

1280

i++, lcdc_info++) {

1279

if (strcmp(fb_pdata->type, lcdc_info->name) == 0)

1281

if (strcmp(fb_pdata->type, lcdc_info->name) == 0)

1280

break;

1282

break;

1281

}

1283

}

1282

1284

1283

if (i == ARRAY_SIZE(known_lcd_panels)) {

1285

if (i == ARRAY_SIZE(known_lcd_panels)) {

1284

dev_err(&device->dev, "GLCD: No valid panel found\n");

1286

dev_err(&device->dev, "GLCD: No valid panel found\n");

1285

ret = -ENODEV;

1287

ret = -ENODEV;

1286

goto err_clk_disable;

1288

goto err_clk_disable;

1287

} else

1289

} else

1288

dev_info(&device->dev, "GLCD: Found %s panel\n",

1290

dev_info(&device->dev, "GLCD: Found %s panel\n",

1289

fb_pdata->type);

1291

fb_pdata->type);

1290

1292

1291

lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;

1293

lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;

1292

1294

1293

da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),

1295

da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),

1294

&device->dev);

1296

&device->dev);

1295

if (!da8xx_fb_info) {

1297

if (!da8xx_fb_info) {

1296

dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");

1298

dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");

1297

ret = -ENOMEM;

1299

ret = -ENOMEM;

1298

goto err_clk_disable;

1300

goto err_clk_disable;

1299

}

1301

}

1300

1302

1301

par = da8xx_fb_info->par;

1303

par = da8xx_fb_info->par;

1302

par->lcdc_clk = fb_clk;

1304

par->lcdc_clk = fb_clk;

1303

par->pxl_clk = lcdc_info->pxl_clk;

1305

par->pxl_clk = lcdc_info->pxl_clk;

1304

if (fb_pdata->panel_power_ctrl) {

1306

if (fb_pdata->panel_power_ctrl) {

1305

par->panel_power_ctrl = fb_pdata->panel_power_ctrl;

1307

par->panel_power_ctrl = fb_pdata->panel_power_ctrl;

1306

par->panel_power_ctrl(1);

1308

par->panel_power_ctrl(1);

1307

}

1309

}

1308

1310

1309

if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {

1311

if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {

1310

dev_err(&device->dev, "lcd_init failed\n");

1312

dev_err(&device->dev, "lcd_init failed\n");

1311

ret = -EFAULT;

1313

ret = -EFAULT;

1312

goto err_release_fb;

1314

goto err_release_fb;

1313

}

1315

}

1314

1316

1315

/* allocate frame buffer */

1317

/* allocate frame buffer */

1316

par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;

1318

par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;

1317

par->vram_size = PAGE_ALIGN(par->vram_size/8);

1319

par->vram_size = PAGE_ALIGN(par->vram_size/8);

1318

par->vram_size = par->vram_size * LCD_NUM_BUFFERS;

1320

par->vram_size = par->vram_size * LCD_NUM_BUFFERS;

1319

1321

1320

par->vram_virt = dma_alloc_coherent(NULL,

1322

par->vram_virt = dma_alloc_coherent(NULL,

1321

par->vram_size,

1323

par->vram_size,

1322

(resource_size_t *) &par->vram_phys,

1324

(resource_size_t *) &par->vram_phys,

1323

GFP_KERNEL | GFP_DMA);

1325

GFP_KERNEL | GFP_DMA);

1324

if (!par->vram_virt) {

1326

if (!par->vram_virt) {

1325

dev_err(&device->dev,

1327

dev_err(&device->dev,

1326

"GLCD: kmalloc for frame buffer failed\n");

1328

"GLCD: kmalloc for frame buffer failed\n");

1327

ret = -EINVAL;

1329

ret = -EINVAL;

1328

goto err_release_fb;

1330

goto err_release_fb;

1329

}

1331

}

1330

1332

1331

da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;

1333

da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;

1332

da8xx_fb_fix.smem_start = par->vram_phys;

1334

da8xx_fb_fix.smem_start = par->vram_phys;

1333

da8xx_fb_fix.smem_len = par->vram_size;

1335

da8xx_fb_fix.smem_len = par->vram_size;

1334

da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;

1336

da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;

1335

1337

1336

par->dma_start = par->vram_phys;

1338

par->dma_start = par->vram_phys;

1337

par->dma_end = par->dma_start + lcdc_info->height *

1339

par->dma_end = par->dma_start + lcdc_info->height *

1338

da8xx_fb_fix.line_length - 1;

1340

da8xx_fb_fix.line_length - 1;

1339

1341

1340

/* allocate palette buffer */

1342

/* allocate palette buffer */

1341

par->v_palette_base = dma_alloc_coherent(NULL,

1343

par->v_palette_base = dma_alloc_coherent(NULL,

1342

PALETTE_SIZE,

1344

PALETTE_SIZE,

1343

(resource_size_t *)

1345

(resource_size_t *)

1344

&par->p_palette_base,

1346

&par->p_palette_base,

1345

GFP_KERNEL | GFP_DMA);

1347

GFP_KERNEL | GFP_DMA);

1346

if (!par->v_palette_base) {

1348

if (!par->v_palette_base) {

1347

dev_err(&device->dev,

1349

dev_err(&device->dev,

1348

"GLCD: kmalloc for palette buffer failed\n");

1350

"GLCD: kmalloc for palette buffer failed\n");

1349

ret = -EINVAL;

1351

ret = -EINVAL;

1350

goto err_release_fb_mem;

1352

goto err_release_fb_mem;

1351

}

1353

}

1352

memset(par->v_palette_base, 0, PALETTE_SIZE);

1354

memset(par->v_palette_base, 0, PALETTE_SIZE);

1353

1355

1354

par->irq = platform_get_irq(device, 0);

1356

par->irq = platform_get_irq(device, 0);

1355

if (par->irq < 0) {

1357

if (par->irq < 0) {

1356

ret = -ENOENT;

1358

ret = -ENOENT;

1357

goto err_release_pl_mem;

1359

goto err_release_pl_mem;

1358

}

1360

}

1359

1361

1360

/* Initialize par */

1362

/* Initialize par */

1361

da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;

1363

da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;

1362

1364

1363

da8xx_fb_var.xres = lcdc_info->width;

1365

da8xx_fb_var.xres = lcdc_info->width;

1364

da8xx_fb_var.xres_virtual = lcdc_info->width;

1366

da8xx_fb_var.xres_virtual = lcdc_info->width;

1365

1367

1366

da8xx_fb_var.yres = lcdc_info->height;

1368

da8xx_fb_var.yres = lcdc_info->height;

1367

da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;

1369

da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;

1368

1370

1369

da8xx_fb_var.grayscale =

1371

da8xx_fb_var.grayscale =

1370

lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;

1372

lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;

1371

da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;

1373

da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;

1372

1374

1373

da8xx_fb_var.hsync_len = lcdc_info->hsw;

1375

da8xx_fb_var.hsync_len = lcdc_info->hsw;

1374

da8xx_fb_var.vsync_len = lcdc_info->vsw;

1376

da8xx_fb_var.vsync_len = lcdc_info->vsw;

1375

1377

1376

da8xx_fb_var.right_margin = lcdc_info->hfp;

1378

da8xx_fb_var.right_margin = lcdc_info->hfp;

1377

da8xx_fb_var.left_margin = lcdc_info->hbp;

1379

da8xx_fb_var.left_margin = lcdc_info->hbp;

1378

da8xx_fb_var.lower_margin = lcdc_info->vfp;

1380

da8xx_fb_var.lower_margin = lcdc_info->vfp;

1379

da8xx_fb_var.upper_margin = lcdc_info->vbp;

1381

da8xx_fb_var.upper_margin = lcdc_info->vbp;

1380

1382

1381

/* Initialize fbinfo */

1383

/* Initialize fbinfo */

1382

da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;

1384

da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;

1383

da8xx_fb_info->fix = da8xx_fb_fix;

1385

da8xx_fb_info->fix = da8xx_fb_fix;

1384

da8xx_fb_info->var = da8xx_fb_var;

1386

da8xx_fb_info->var = da8xx_fb_var;

1385

da8xx_fb_info->fbops = &da8xx_fb_ops;

1387

da8xx_fb_info->fbops = &da8xx_fb_ops;

1386

da8xx_fb_info->pseudo_palette = par->pseudo_palette;

1388

da8xx_fb_info->pseudo_palette = par->pseudo_palette;

1387

da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?

1389

da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?

1388

FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;

1390

FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;

1389

1391

1390

ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);

1392

ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);

1391

if (ret)

1393

if (ret)

1392

goto err_release_pl_mem;

1394

goto err_release_pl_mem;

1393

da8xx_fb_info->cmap.len = par->palette_sz;

1395

da8xx_fb_info->cmap.len = par->palette_sz;

1394

1396

1395

/* initialize var_screeninfo */

1397

/* initialize var_screeninfo */

1396

da8xx_fb_var.activate = FB_ACTIVATE_FORCE;

1398

da8xx_fb_var.activate = FB_ACTIVATE_FORCE;

1397

fb_set_var(da8xx_fb_info, &da8xx_fb_var);

1399

fb_set_var(da8xx_fb_info, &da8xx_fb_var);

1398

1400

1399

dev_set_drvdata(&device->dev, da8xx_fb_info);

1401

dev_set_drvdata(&device->dev, da8xx_fb_info);

1400

1402

1401

/* initialize the vsync wait queue */

1403

/* initialize the vsync wait queue */

1402

init_waitqueue_head(&par->vsync_wait);

1404

init_waitqueue_head(&par->vsync_wait);

1403

par->vsync_timeout = HZ / 5;

1405

par->vsync_timeout = HZ / 5;

1404

par->which_dma_channel_done = -1;

1406

par->which_dma_channel_done = -1;

1405

spin_lock_init(&par->lock_for_chan_update);

1407

spin_lock_init(&par->lock_for_chan_update);

1406

1408

1407

/* Register the Frame Buffer */

1409

/* Register the Frame Buffer */

1408

if (register_framebuffer(da8xx_fb_info) < 0) {

1410

if (register_framebuffer(da8xx_fb_info) < 0) {

1409

dev_err(&device->dev,

1411

dev_err(&device->dev,

1410

"GLCD: Frame Buffer Registration Failed!\n");

1412

"GLCD: Frame Buffer Registration Failed!\n");

1411

ret = -EINVAL;

1413

ret = -EINVAL;

1412

goto err_dealloc_cmap;

1414

goto err_dealloc_cmap;

1413

}

1415

}

1414

1416

1415

#ifdef CONFIG_CPU_FREQ

1417

#ifdef CONFIG_CPU_FREQ

1416

ret = lcd_da8xx_cpufreq_register(par);

1418

ret = lcd_da8xx_cpufreq_register(par);

1417

if (ret) {

1419

if (ret) {

1418

dev_err(&device->dev, "failed to register cpufreq\n");

1420

dev_err(&device->dev, "failed to register cpufreq\n");

1419

goto err_cpu_freq;

1421

goto err_cpu_freq;

1420

}

1422

}

1421

#endif

1423

#endif

1422

1424

1423

if (lcd_revision == LCD_VERSION_1)

1425

if (lcd_revision == LCD_VERSION_1)

1424

lcdc_irq_handler = lcdc_irq_handler_rev01;

1426

lcdc_irq_handler = lcdc_irq_handler_rev01;

1425

else

1427

else

1426

lcdc_irq_handler = lcdc_irq_handler_rev02;

1428

lcdc_irq_handler = lcdc_irq_handler_rev02;

1427

1429

1428

ret = request_irq(par->irq, lcdc_irq_handler, 0,

1430

ret = request_irq(par->irq, lcdc_irq_handler, 0,

1429

DRIVER_NAME, par);

1431

DRIVER_NAME, par);

1430

if (ret)

1432

if (ret)

1431

goto irq_freq;

1433

goto irq_freq;

1432

return 0;

1434

return 0;

1433

1435

1434

irq_freq:

1436

irq_freq:

1435

#ifdef CONFIG_CPU_FREQ

1437

#ifdef CONFIG_CPU_FREQ

1436

lcd_da8xx_cpufreq_deregister(par);

1438

lcd_da8xx_cpufreq_deregister(par);

1437

err_cpu_freq:

1439

err_cpu_freq:

1438

#endif

1440

#endif

1439

unregister_framebuffer(da8xx_fb_info);

1441

unregister_framebuffer(da8xx_fb_info);

1440

1442

1441

err_dealloc_cmap:

1443

err_dealloc_cmap:

1442

fb_dealloc_cmap(&da8xx_fb_info->cmap);

1444

fb_dealloc_cmap(&da8xx_fb_info->cmap);

1443

1445

1444

err_release_pl_mem:

1446

err_release_pl_mem:

1445

dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,

1447

dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,

1446

par->p_palette_base);

1448

par->p_palette_base);

1447

1449

1448

err_release_fb_mem:

1450

err_release_fb_mem:

1449

dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);

1451

dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);

1450

1452

1451

err_release_fb:

1453

err_release_fb:

1452

framebuffer_release(da8xx_fb_info);

1454

framebuffer_release(da8xx_fb_info);

1453

1455

1454

err_clk_disable:

1456

err_clk_disable:

1455

clk_disable(fb_clk);

1457

clk_disable(fb_clk);

1456

1458

1457

err_clk_put2:

1459

err_clk_put2:

1458

clk_put(fb_clk);

1460

clk_put(fb_clk);

1459

1461

1460

err_clk_get1:

1462

err_clk_get1:

1461

clk_disable(fb_l4ick);

1463

clk_disable(fb_l4ick);

1462

1464

1463

err_clk_put1:

1465

err_clk_put1:

1464

clk_put(fb_l4ick);

1466

clk_put(fb_l4ick);

1465

1467

1466

err_clk_get0:

1468

err_clk_get0:

1467

clk_disable(fb_l3ick);

1469

clk_disable(fb_l3ick);

1468

1470

1469

err_clk_put0:

1471

err_clk_put0:

1470

clk_put(fb_l3ick);

1472

clk_put(fb_l3ick);

1471

1473

1472

err_ioremap:

1474

err_ioremap:

1473

iounmap((void __iomem *)da8xx_fb_reg_base);

1475

iounmap((void __iomem *)da8xx_fb_reg_base);

1474

1476

1475

err_request_mem:

1477

err_request_mem:

1476

release_mem_region(lcdc_regs->start, len);

1478

release_mem_region(lcdc_regs->start, len);

1477

1479

1478

return ret;

1480

return ret;

1479

}

1481

}

1480

1482

1481

#ifdef CONFIG_PM

1483

#ifdef CONFIG_PM

1482

static int fb_suspend(struct platform_device *dev, pm_message_t state)

1484

static int fb_suspend(struct platform_device *dev, pm_message_t state)

1483

{

1485

{

1484

struct fb_info *info = platform_get_drvdata(dev);

1486

struct fb_info *info = platform_get_drvdata(dev);

1485

struct da8xx_fb_par *par = info->par;

1487

struct da8xx_fb_par *par = info->par;

1486

unsigned long timeo = jiffies + msecs_to_jiffies(5000);

1488

unsigned long timeo = jiffies + msecs_to_jiffies(5000);

1487

u32 stat;

1489

u32 stat;

1488

1490

1489

console_lock();

1491

console_lock();

1490

if (par->panel_power_ctrl)

1492

if (par->panel_power_ctrl)

1491

par->panel_power_ctrl(0);

1493

par->panel_power_ctrl(0);

1492

1494

1493

fb_set_suspend(info, 1);

1495

fb_set_suspend(info, 1);

1494

lcd_disable_raster();

1496

lcd_disable_raster();

1495

1497

1496

/* Wait for the current frame to complete */

1498

/* Wait for the current frame to complete */

1497

do {

1499

do {

1498

if (lcd_revision == LCD_VERSION_1)

1500

if (lcd_revision == LCD_VERSION_1)

1499

stat = lcdc_read(LCD_STAT_REG);

1501

stat = lcdc_read(LCD_STAT_REG);

1500

else

1502

else

1501

stat = lcdc_read(LCD_MASKED_STAT_REG);

1503

stat = lcdc_read(LCD_MASKED_STAT_REG);

1502

cpu_relax();

1504

cpu_relax();

1503

} while (!(stat & BIT(0)) && time_before(jiffies, timeo));

1505

} while (!(stat & BIT(0)) && time_before(jiffies, timeo));

1504

1506

1505

if (lcd_revision == LCD_VERSION_1)

1507

if (lcd_revision == LCD_VERSION_1)

1506

lcdc_write(stat, LCD_STAT_REG);

1508

lcdc_write(stat, LCD_STAT_REG);

1507

else

1509

else

1508

lcdc_write(stat, LCD_MASKED_STAT_REG);

1510

lcdc_write(stat, LCD_MASKED_STAT_REG);

1509

1511

1510

if (time_after_eq(jiffies, timeo)) {

1512

if (time_after_eq(jiffies, timeo)) {

1511

dev_err(&dev->dev, "controller timed out\n");

1513

dev_err(&dev->dev, "controller timed out\n");

1512

return -ETIMEDOUT;

1514

return -ETIMEDOUT;

1513

}

1515

}

1514

1516

1515

clk_disable(par->lcdc_clk);

1517

clk_disable(par->lcdc_clk);

1516

console_unlock();

1518

console_unlock();

1517

1519

1518

return 0;

1520

return 0;

1519

}

1521

}

1520

static int fb_resume(struct platform_device *dev)

1522

static int fb_resume(struct platform_device *dev)

1521

{

1523

{

1522

struct fb_info *info = platform_get_drvdata(dev);

1524

struct fb_info *info = platform_get_drvdata(dev);

1523

struct da8xx_fb_par *par = info->par;

1525

struct da8xx_fb_par *par = info->par;

1524

1526

1525

console_lock();

1527

console_lock();

1526

if (par->panel_power_ctrl)

1528

if (par->panel_power_ctrl)

1527

par->panel_power_ctrl(1);

1529

par->panel_power_ctrl(1);

1528

1530

1529

clk_enable(par->lcdc_clk);

1531

clk_enable(par->lcdc_clk);

1530

1532

1531

lcd_enable_raster();

1533

lcd_enable_raster();

1532

1534

1533

if (par->panel_power_ctrl)

1535

if (par->panel_power_ctrl)

1534

par->panel_power_ctrl(1);

1536

par->panel_power_ctrl(1);

1535

1537

1536

fb_set_suspend(info, 0);

1538

fb_set_suspend(info, 0);

1537

console_unlock();

1539

console_unlock();

1538

1540

1539

return 0;

1541

return 0;

1540

}

1542

}

1541

#else

1543

#else

1542

#define fb_suspend NULL

1544

#define fb_suspend NULL

1543

#define fb_resume NULL

1545

#define fb_resume NULL

1544

#endif

1546

#endif

1545

1547

1546

static struct platform_driver da8xx_fb_driver = {

1548

static struct platform_driver da8xx_fb_driver = {

1547

.probe = fb_probe,

1549

.probe = fb_probe,

1548

.remove = __devexit_p(fb_remove),

1550

.remove = __devexit_p(fb_remove),

1549

.suspend = fb_suspend,

1551

.suspend = fb_suspend,

1550

.resume = fb_resume,

1552

.resume = fb_resume,

1551

.driver = {

1553

.driver = {

1552

.name = DRIVER_NAME,

1554

.name = DRIVER_NAME,

1553

.owner = THIS_MODULE,

1555

.owner = THIS_MODULE,

1554

},

1556

},

1555

};

1557

};

1556

1558

1557

static int __init da8xx_fb_init(void)

1559

static int __init da8xx_fb_init(void)

1558

{

1560

{

1559

return platform_driver_register(&da8xx_fb_driver);

1561

return platform_driver_register(&da8xx_fb_driver);

1560

}

1562

}

1561

1563

1562

static void __exit da8xx_fb_cleanup(void)

1564

static void __exit da8xx_fb_cleanup(void)

1563

{

1565

{

1564

platform_driver_unregister(&da8xx_fb_driver);

1566

platform_driver_unregister(&da8xx_fb_driver);

1565

}

1567

}

1566

1568

1567

module_init(da8xx_fb_init);

1569

module_init(da8xx_fb_init);

1568

module_exit(da8xx_fb_cleanup);

1570

module_exit(da8xx_fb_cleanup);

1569

1571

1570

MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");

1572

MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");

1571

MODULE_AUTHOR("Texas Instruments");

1573

MODULE_AUTHOR("Texas Instruments");

1572

MODULE_LICENSE("GPL");

1574

MODULE_LICENSE("GPL");

1573

1575

GITLAB

Eric Lee / linux-smarc-t335x-v3.2

video: da8xx-fb: Add debug message on sync and underflow error

 /*
  * Copyright (C) 2008-2009 MontaVista Software Inc.
  * Copyright (C) 2008-2009 Texas Instruments Inc
  *
  * Based on the LCD driver for TI Avalanche processors written by
  * Ajay Singh and Shalom Hai.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option)any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/fb.h>
 #include <linux/dma-mapping.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/uaccess.h>
 #include <linux/interrupt.h>
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 #include <linux/console.h>
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <video/da8xx-fb.h>
 #include <asm/mach-types.h>
 #define DRIVER_NAME "da8xx_lcdc"
 #define LCD_VERSION_1	1
 #define LCD_VERSION_2	2
 /* LCD Status Register */
 #define LCD_END_OF_FRAME1		BIT(9)
 #define LCD_END_OF_FRAME0		BIT(8)
 #define LCD_PL_LOAD_DONE		BIT(6)
 #define LCD_FIFO_UNDERFLOW		BIT(5)
 #define LCD_SYNC_LOST			BIT(2)
 /* LCD DMA Control Register */
 #define LCD_DMA_BURST_SIZE(x)		((x) << 4)
 #define LCD_DMA_BURST_1			0x0
 #define LCD_DMA_BURST_2			0x1
 #define LCD_DMA_BURST_4			0x2
 #define LCD_DMA_BURST_8			0x3
 #define LCD_DMA_BURST_16		0x4
 #define LCD_V1_END_OF_FRAME_INT_ENA	BIT(2)
 #define LCD_V2_END_OF_FRAME0_INT_ENA	BIT(8)
 #define LCD_V2_END_OF_FRAME1_INT_ENA	BIT(9)
 #define LCD_DUAL_FRAME_BUFFER_ENABLE	BIT(0)
 /* LCD Control Register */
 #define LCD_CLK_DIVISOR(x)		((x) << 8)
 #define LCD_RASTER_MODE			0x01
 /* LCD Raster Control Register */
 #define LCD_PALETTE_LOAD_MODE(x)	((x) << 20)
 #define PALETTE_AND_DATA		0x00
 #define PALETTE_ONLY			0x01
 #define DATA_ONLY			0x02
 #define LCD_MONO_8BIT_MODE		BIT(9)
 #define LCD_RASTER_ORDER		BIT(8)
 #define LCD_TFT_MODE			BIT(7)
 #define LCD_V1_UNDERFLOW_INT_ENA	BIT(6)
 #define LCD_V2_UNDERFLOW_INT_ENA	BIT(5)
 #define LCD_V1_PL_INT_ENA		BIT(4)
 #define LCD_V2_PL_INT_ENA		BIT(6)
 #define LCD_MONOCHROME_MODE		BIT(1)
 #define LCD_RASTER_ENABLE		BIT(0)
 #define LCD_TFT_ALT_ENABLE		BIT(23)
 #define LCD_STN_565_ENABLE		BIT(24)
 #define LCD_V2_DMA_CLK_EN		BIT(2)
 #define LCD_V2_LIDD_CLK_EN		BIT(1)
 #define LCD_V2_CORE_CLK_EN		BIT(0)
 #define LCD_V2_LPP_B10			26
 #define LCD_V2_TFT_24BPP_MODE		BIT(25)
 #define LCD_V2_TFT_24BPP_UNPACK		BIT(26)
 /* LCD Raster Timing 2 Register */
 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)	((x) << 16)
 #define LCD_AC_BIAS_FREQUENCY(x)		((x) << 8)
 #define LCD_SYNC_CTRL				BIT(25)
 #define LCD_SYNC_EDGE				BIT(24)
 #define LCD_INVERT_PIXEL_CLOCK			BIT(22)
 #define LCD_INVERT_LINE_CLOCK			BIT(21)
 #define LCD_INVERT_FRAME_CLOCK			BIT(20)
 /* LCD Block */
 #define  LCD_PID_REG				0x0
 #define  LCD_CTRL_REG				0x4
 #define  LCD_STAT_REG				0x8
 #define  LCD_RASTER_CTRL_REG			0x28
 #define  LCD_RASTER_TIMING_0_REG		0x2C
 #define  LCD_RASTER_TIMING_1_REG		0x30
 #define  LCD_RASTER_TIMING_2_REG		0x34
 #define  LCD_DMA_CTRL_REG			0x40
 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG	0x44
 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG	0x48
 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG	0x4C
 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG	0x50
 /* Interrupt Registers available only in Version 2 */
 #define  LCD_RAW_STAT_REG			0x58
 #define  LCD_MASKED_STAT_REG			0x5c
 #define  LCD_INT_ENABLE_SET_REG			0x60
 #define  LCD_INT_ENABLE_CLR_REG			0x64
 #define  LCD_END_OF_INT_IND_REG			0x68
 /* Clock registers available only on Version 2 */
 #define  LCD_CLK_ENABLE_REG			0x6c
 #define  LCD_CLK_RESET_REG			0x70
 #define  LCD_CLK_MAIN_RESET			BIT(3)
 #define LCD_NUM_BUFFERS	2
 #define WSI_TIMEOUT	50
 #define PALETTE_SIZE	256
 #define LEFT_MARGIN	64
 #define RIGHT_MARGIN	64
 #define UPPER_MARGIN	32
 #define LOWER_MARGIN	32
 static resource_size_t da8xx_fb_reg_base;
 static struct resource *lcdc_regs;
 static unsigned int lcd_revision;
 static irq_handler_t lcdc_irq_handler;
 static inline unsigned int lcdc_read(unsigned int addr)
 {
 	return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 }
 static inline void lcdc_write(unsigned int val, unsigned int addr)
 {
 	__raw_writel(val, da8xx_fb_reg_base + (addr));
 }
 struct da8xx_fb_par {
 	resource_size_t p_palette_base;
 	unsigned char *v_palette_base;
 	dma_addr_t		vram_phys;
 	unsigned long		vram_size;
 	void			*vram_virt;
 	unsigned int		dma_start;
 	unsigned int		dma_end;
 	struct clk *lcdc_clk;
 	int irq;
 	unsigned short pseudo_palette[32];
 	unsigned int palette_sz;
 	unsigned int pxl_clk;
 	int blank;
 	wait_queue_head_t	vsync_wait;
 	int			vsync_flag;
 	int			vsync_timeout;
 	spinlock_t		lock_for_chan_update;
 	/*
 	 * LCDC has 2 ping pong DMA channels, channel 0
 	 * and channel 1.
 	 */
 	unsigned int		which_dma_channel_done;
 #ifdef CONFIG_CPU_FREQ
 	struct notifier_block	freq_transition;
 #endif
 	void (*panel_power_ctrl)(int);
 };
 /* Variable Screen Information */
 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
 	.xoffset = 0,
 	.yoffset = 0,
 	.transp = {0, 0, 0},
 	.nonstd = 0,
 	.activate = 0,
 	.height = -1,
 	.width = -1,
 	.pixclock = 33333,/*Pico Sec*/
 	.accel_flags = 0,
 	.left_margin = LEFT_MARGIN,
 	.right_margin = RIGHT_MARGIN,
 	.upper_margin = UPPER_MARGIN,
 	.lower_margin = LOWER_MARGIN,
 	.sync = 0,
 	.vmode = FB_VMODE_NONINTERLACED
 };
 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
 	.id = "DA8xx FB Drv",
 	.type = FB_TYPE_PACKED_PIXELS,
 	.type_aux = 0,
 	.visual = FB_VISUAL_PSEUDOCOLOR,
 	.xpanstep = 0,
 	.ypanstep = 1,
 	.ywrapstep = 0,
 	.accel = FB_ACCEL_NONE
 };
 struct da8xx_panel {
 	const char	name[25];	/* Full name <vendor>_<model> */
 	unsigned short	width;
 	unsigned short	height;
 	int		hfp;		/* Horizontal front porch */
 	int		hbp;		/* Horizontal back porch */
 	int		hsw;		/* Horizontal Sync Pulse Width */
 	int		vfp;		/* Vertical front porch */
 	int		vbp;		/* Vertical back porch */
 	int		vsw;		/* Vertical Sync Pulse Width */
 	unsigned int	pxl_clk;	/* Pixel clock */
 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
 };
 static vsync_callback_t vsync_cb_handler;
 static void *vsync_cb_arg;
 static struct da8xx_panel known_lcd_panels[] = {
 	/* Sharp LCD035Q3DG01 */
 	[0] = {
 		.name = "Sharp_LCD035Q3DG01",
 		.width = 320,
 		.height = 240,
 		.hfp = 8,
 		.hbp = 6,
 		.hsw = 0,
 		.vfp = 2,
 		.vbp = 2,
 		.vsw = 0,
 		.pxl_clk = 4608000,
 		.invert_pxl_clk = 1,
 	},
 	/* Sharp LK043T1DG01 */
 	[1] = {
 		.name = "Sharp_LK043T1DG01",
 		.width = 480,
 		.height = 272,
 		.hfp = 2,
 		.hbp = 2,
 		.hsw = 41,
 		.vfp = 3,
 		.vbp = 3,
 		.vsw = 10,
 		.pxl_clk = 7833600,
 		.invert_pxl_clk = 0,
 	},
 	/* ThreeFive S9700RTWV35TR */
 	[2] = {
 		.name = "TFC_S9700RTWV35TR_01B",
 		.width = 800,
 		.height = 480,
 		.hfp = 39,
 		.hbp = 39,
 		.hsw = 47,
 		.vfp = 13,
 		.vbp = 29,
 		.vsw = 2,
 		.pxl_clk = 30000000,
 		.invert_pxl_clk = 0,
 	},
 };
 /* Enable the Raster Engine of the LCD Controller */
 static inline void lcd_enable_raster(void)
 {
 	u32 reg;
 	/* Bring LCDC out of reset */
 	if (lcd_revision == LCD_VERSION_2)
 		lcdc_write(0, LCD_CLK_RESET_REG);
 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
 	if (!(reg & LCD_RASTER_ENABLE))
 		lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 }
 /* Disable the Raster Engine of the LCD Controller */
 static inline void lcd_disable_raster(void)
 {
 	u32 reg;
 	reg = lcdc_read(LCD_RASTER_CTRL_REG);
 	if (reg & LCD_RASTER_ENABLE)
 		lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 	if (lcd_revision == LCD_VERSION_2)
 		/* Write 1 to reset LCDC */
 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 }
 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 {
 	u32 start;
 	u32 end;
 	u32 reg_ras;
 	u32 reg_dma;
 	u32 reg_int;
 	/* init reg to clear PLM (loading mode) fields */
 	reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
 	reg_ras &= ~(3 << 20);
 	reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
 	if (load_mode == LOAD_DATA) {
 		start    = par->dma_start;
 		end      = par->dma_end;
 		reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 		if (lcd_revision == LCD_VERSION_1) {
 			reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 		} else {
 			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 				LCD_V2_END_OF_FRAME0_INT_ENA |
 				LCD_V2_END_OF_FRAME1_INT_ENA;
 			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 		}
 		reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 		lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 		lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 		lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 		lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 	} else if (load_mode == LOAD_PALETTE) {
 		start    = par->p_palette_base;
 		end      = start + par->palette_sz - 1;
 		reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 		if (lcd_revision == LCD_VERSION_1) {
 			reg_ras |= LCD_V1_PL_INT_ENA;
 		} else {
 			reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 				LCD_V2_PL_INT_ENA;
 			lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 		}
 		lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 		lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 	}
 	lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
 	lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 	/*
 	 * The Raster enable bit must be set after all other control fields are
 	 * set.
 	 */
 	lcd_enable_raster();
 }
 /* Configure the Burst Size and fifo threhold of DMA */
 static int lcd_cfg_dma(int burst_size,  int fifo_th)
 {
 	u32 reg;
 	reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 	switch (burst_size) {
 	case 1:
 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 		break;
 	case 2:
 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 		break;
 	case 4:
 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 		break;
 	case 8:
 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 		break;
 	case 16:
 		reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 		break;
 	default:
 		return -EINVAL;
 	}
 	reg |= (fifo_th << 8);
 	lcdc_write(reg, LCD_DMA_CTRL_REG);
 	return 0;
 }
 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 {
 	u32 reg;
 	/* Set the AC Bias Period and Number of Transisitons per Interrupt */
 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 	reg |= LCD_AC_BIAS_FREQUENCY(period) |
 		LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 }
 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 		int front_porch)
 {
 	u32 reg;
 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
 	reg |= ((back_porch & 0xff) << 24)
 	    | ((front_porch & 0xff) << 16)
 	    | ((pulse_width & 0x3f) << 10);
 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 }
 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 		int front_porch)
 {
 	u32 reg;
 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 	reg |= ((back_porch & 0xff) << 24)
 	    | ((front_porch & 0xff) << 16)
 	    | ((pulse_width & 0x3f) << 10);
 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 }
 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 {
 	u32 reg;
 	u32 reg_int;
 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 						LCD_MONO_8BIT_MODE |
 						LCD_MONOCHROME_MODE);
 	switch (cfg->p_disp_panel->panel_shade) {
 	case MONOCHROME:
 		reg |= LCD_MONOCHROME_MODE;
 		if (cfg->mono_8bit_mode)
 			reg |= LCD_MONO_8BIT_MODE;
 		break;
 	case COLOR_ACTIVE:
 		reg |= LCD_TFT_MODE;
 		if (cfg->tft_alt_mode)
 			reg |= LCD_TFT_ALT_ENABLE;
 		break;
 	case COLOR_PASSIVE:
 		if (cfg->stn_565_mode)
 			reg |= LCD_STN_565_ENABLE;
 		break;
 	default:
 		return -EINVAL;
 	}
 	/* enable additional interrupts here */
 	if (lcd_revision == LCD_VERSION_1) {
 		reg |= LCD_V1_UNDERFLOW_INT_ENA;
 	} else {
 		reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 			LCD_V2_UNDERFLOW_INT_ENA;
 		lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 	}
 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
 	reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 	if (cfg->sync_ctrl)
 		reg |= LCD_SYNC_CTRL;
 	else
 		reg &= ~LCD_SYNC_CTRL;
 	if (cfg->sync_edge)
 		reg |= LCD_SYNC_EDGE;
 	else
 		reg &= ~LCD_SYNC_EDGE;
 	if (cfg->invert_line_clock)
 		reg |= LCD_INVERT_LINE_CLOCK;
 	else
 		reg &= ~LCD_INVERT_LINE_CLOCK;
 	if (cfg->invert_frm_clock)
 		reg |= LCD_INVERT_FRAME_CLOCK;
 	else
 		reg &= ~LCD_INVERT_FRAME_CLOCK;
 	lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 	return 0;
 }
 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 		u32 bpp, u32 raster_order)
 {
 	u32 reg;
 	/* Set the Panel Width */
 	/* Pixels per line = (PPL + 1)*16 */
 	if (lcd_revision == LCD_VERSION_1) {
 		/*
 		 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 		 * pixels.
 		 */
 		width &= 0x3f0;
 	} else {
 		/*
 		 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 		 * pixels.
 		 */
 		width &= 0x7f0;
 	}
 	reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 	reg &= 0xfffffc00;
 	if (lcd_revision == LCD_VERSION_1) {
 		reg |= ((width >> 4) - 1) << 4;
 	} else {
 		width = (width >> 4) - 1;
 		reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 	}
 	lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 	/* Set the Panel Height */
 	/* Set bits 9:0 of Lines Per Pixel */
 	reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 	reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 	lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 	/* Set bit 10 of Lines Per Pixel */
 	if (lcd_revision == LCD_VERSION_2) {
 		reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 		reg |= ((height - 1) & 0x400) << 16;
 		lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 	}
 	/* Set the Raster Order of the Frame Buffer */
 	reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 	if (raster_order)
 		reg |= LCD_RASTER_ORDER;
 	if (bpp == 24)
 		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
 	else if (bpp == 32)
 		reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
 				| LCD_V2_TFT_24BPP_UNPACK);
 	lcdc_write(reg, LCD_RASTER_CTRL_REG);
 	switch (bpp) {
 	case 1:
 	case 2:
 	case 4:
 	case 16:
 	case 24:
 	case 32:
 		par->palette_sz = 16 * 2;
 		break;
 	case 8:
 		par->palette_sz = 256 * 2;
 		break;
 	default:
 		return -EINVAL;
 	}
 	return 0;
 }
 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 			      unsigned blue, unsigned transp,
 			      struct fb_info *info)
 {
 	struct da8xx_fb_par *par = info->par;
 	unsigned short *palette = (unsigned short *) par->v_palette_base;
 	u_short pal;
 	int update_hw = 0;
 	if (regno > 255)
 		return 1;
 	if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 		return 1;
 	if (info->var.bits_per_pixel == 8) {
 		red >>= 4;
 		green >>= 8;
 		blue >>= 12;
 		pal = (red & 0x0f00);
 		pal |= (green & 0x00f0);
 		pal |= (blue & 0x000f);
 		if (palette[regno] != pal) {
 			update_hw = 1;
 			palette[regno] = pal;
 		}
 	} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
 		red >>= (16 - info->var.red.length);
 		red <<= info->var.red.offset;
 		green >>= (16 - info->var.green.length);
 		green <<= info->var.green.offset;
 		blue >>= (16 - info->var.blue.length);
 		blue <<= info->var.blue.offset;
 		par->pseudo_palette[regno] = red | green | blue;
 		if (palette[0] != 0x4000) {
 			update_hw = 1;
 			palette[0] = 0x4000;
 		}
 	} else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
 		    ((info->var.bits_per_pixel == 24) && regno < 24)) {
 		red >>= (24 - info->var.red.length);
 		red <<= info->var.red.offset;
 		green >>= (24 - info->var.green.length);
 		green <<= info->var.green.offset;
 		blue >>= (24 - info->var.blue.length);
 		blue <<= info->var.blue.offset;
 		par->pseudo_palette[regno] = red | green | blue;
 		if (palette[0] != 0x4000) {
 			update_hw = 1;
 			palette[0] = 0x4000;
 		}
 	}
 	/* Update the palette in the h/w as needed. */
 	if (update_hw)
 		lcd_blit(LOAD_PALETTE, par);
 	return 0;
 }
 static void lcd_reset(struct da8xx_fb_par *par)
 {
 	/* Disable the Raster if previously Enabled */
 	lcd_disable_raster();
 	/* DMA has to be disabled */
 	lcdc_write(0, LCD_DMA_CTRL_REG);
 	lcdc_write(0, LCD_RASTER_CTRL_REG);
 	if (lcd_revision == LCD_VERSION_2) {
 		lcdc_write(0, LCD_INT_ENABLE_SET_REG);
 		/* Write 1 to reset */
 		lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 		lcdc_write(0, LCD_CLK_RESET_REG);
 	}
 }
 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
 {
 	unsigned int lcd_clk, div;
 	lcd_clk = clk_get_rate(par->lcdc_clk);
 	div = lcd_clk / par->pxl_clk;
 	/* Configure the LCD clock divisor. */
 	lcdc_write(LCD_CLK_DIVISOR(div) |
 			(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 	if (lcd_revision == LCD_VERSION_2)
 		lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 				LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
 }
 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 		struct da8xx_panel *panel)
 {
 	u32 bpp;
 	int ret = 0;
 	lcd_reset(par);
 	/* Calculate the divider */
 	lcd_calc_clk_divider(par);
 	if (panel->invert_pxl_clk)
 		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 			LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 	else
 		lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 			~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 	/* Configure the DMA burst size and fifo threshold. */
 	ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
 	if (ret < 0)
 		return ret;
 	/* Configure the AC bias properties. */
 	lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 	/* Configure the vertical and horizontal sync properties. */
 	lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 	lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 	/* Configure for disply */
 	ret = lcd_cfg_display(cfg);
 	if (ret < 0)
 		return ret;
 	if ((QVGA != cfg->p_disp_panel->panel_type) &&
 			(WVGA != cfg->p_disp_panel->panel_type))
 		return -EINVAL;
 	if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
 	    cfg->bpp >= cfg->p_disp_panel->min_bpp)
 		bpp = cfg->bpp;
 	else
 		bpp = cfg->p_disp_panel->max_bpp;
 	if (bpp == 12)
 		bpp = 16;
 	ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
 				(unsigned int)panel->height, bpp,
 				cfg->raster_order);
 	if (ret < 0)
 		return ret;
 	/* Configure FDD */
 	lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 		       (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 	return 0;
 }
 int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
 {
 	if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
 		vsync_cb_handler = handler;
 		vsync_cb_arg = arg;
 	} else {
 		return -EEXIST;
 	}
 	return 0;
 }
 EXPORT_SYMBOL(register_vsync_cb);
 int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
 {
 	if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
 		vsync_cb_handler = NULL;
 		vsync_cb_arg = NULL;
 	} else {
 		return -ENXIO;
 	}
 	return 0;
 }
 EXPORT_SYMBOL(unregister_vsync_cb);
 /* IRQ handler for version 2 of LCDC */
 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
 {
 	struct da8xx_fb_par *par = arg;
 	u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
 	u32 reg_int;
 	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
 		lcd_disable_raster();
 		clk_disable(par->lcdc_clk);
 		lcdc_write(stat, LCD_MASKED_STAT_REG);
 		lcd_enable_raster();
 		clk_enable(par->lcdc_clk);
 	} else if (stat & LCD_PL_LOAD_DONE) {
 		/*
 		 * Must disable raster before changing state of any control bit.
 		 * And also must be disabled before clearing the PL loading
 		 * interrupt via the following write to the status register. If
 		 * this is done after then one gets multiple PL done interrupts.
 		 */
 		lcd_disable_raster();
 		lcdc_write(stat, LCD_MASKED_STAT_REG);
 		/* Disable PL completion inerrupt */
 		reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
 		       (LCD_V2_PL_INT_ENA);
 		lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
 		/* Setup and start data loading mode */
 		lcd_blit(LOAD_DATA, par);
 	} else {
 		lcdc_write(stat, LCD_MASKED_STAT_REG);
 		if (stat & LCD_END_OF_FRAME0) {
 			par->which_dma_channel_done = 0;
 			lcdc_write(par->dma_start,
 				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 			lcdc_write(par->dma_end,
 				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 			par->vsync_flag = 1;
 			wake_up_interruptible(&par->vsync_wait);
 			if (vsync_cb_handler)
 				vsync_cb_handler(vsync_cb_arg);
 		}
 		if (stat & LCD_END_OF_FRAME1) {
 			par->which_dma_channel_done = 1;
 			lcdc_write(par->dma_start,
 				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 			lcdc_write(par->dma_end,
 				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 			par->vsync_flag = 1;
 			wake_up_interruptible(&par->vsync_wait);
 			if (vsync_cb_handler)
 				vsync_cb_handler(vsync_cb_arg);
 		}
 	}
 	lcdc_write(0, LCD_END_OF_INT_IND_REG);
 	return IRQ_HANDLED;
 }
 /* IRQ handler for version 1 LCDC */
 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
 {
 	struct da8xx_fb_par *par = arg;
 	u32 stat = lcdc_read(LCD_STAT_REG);
 	u32 reg_ras;
 	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
+		printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
 		lcd_disable_raster();
 		clk_disable(par->lcdc_clk);
 		lcdc_write(stat, LCD_STAT_REG);
 		lcd_enable_raster();
 		clk_enable(par->lcdc_clk);
 	} else if (stat & LCD_PL_LOAD_DONE) {
 		/*
 		 * Must disable raster before changing state of any control bit.
 		 * And also must be disabled before clearing the PL loading
 		 * interrupt via the following write to the status register. If
 		 * this is done after then one gets multiple PL done interrupts.
 		 */
 		lcd_disable_raster();
 		lcdc_write(stat, LCD_STAT_REG);
 		/* Disable PL completion inerrupt */
 		reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
 		reg_ras &= ~LCD_V1_PL_INT_ENA;
 		lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 		/* Setup and start data loading mode */
 		lcd_blit(LOAD_DATA, par);
 	} else {
 		lcdc_write(stat, LCD_STAT_REG);
 		if (stat & LCD_END_OF_FRAME0) {
 			lcdc_write(par->dma_start,
 				   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 			lcdc_write(par->dma_end,
 				   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 			par->vsync_flag = 1;
 			wake_up_interruptible(&par->vsync_wait);
 		}
 		if (stat & LCD_END_OF_FRAME1) {
 			lcdc_write(par->dma_start,
 				   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 			lcdc_write(par->dma_end,
 				   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 			par->vsync_flag = 1;
 			wake_up_interruptible(&par->vsync_wait);
 		}
 	}
 	return IRQ_HANDLED;
 }
 static int fb_check_var(struct fb_var_screeninfo *var,
 			struct fb_info *info)
 {
 	int err = 0;
 	switch (var->bits_per_pixel) {
 	case 1:
 	case 8:
 		var->red.offset = 0;
 		var->red.length = 8;
 		var->green.offset = 0;
 		var->green.length = 8;
 		var->blue.offset = 0;
 		var->blue.length = 8;
 		var->transp.offset = 0;
 		var->transp.length = 0;
 		break;
 	case 4:
 		var->red.offset = 0;
 		var->red.length = 4;
 		var->green.offset = 0;
 		var->green.length = 4;
 		var->blue.offset = 0;
 		var->blue.length = 4;
 		var->transp.offset = 0;
 		var->transp.length = 0;
 		break;
 	case 16:		/* RGB 565 */
 		var->red.offset = 11;
 		var->red.length = 5;
 		var->green.offset = 5;
 		var->green.length = 6;
 		var->blue.offset = 0;
 		var->blue.length = 5;
 		var->transp.offset = 0;
 		var->transp.length = 0;
 		break;
 	case 24:
 		var->red.offset = 16;
 		var->red.length = 8;
 		var->green.offset = 8;
 		var->green.length = 8;
 		var->blue.offset = 0;
 		var->blue.length = 8;
 		break;
 	case 32:
 		var->transp.offset = 24;
 		var->transp.length = 8;
 		var->red.offset = 16;
 		var->red.length = 8;
 		var->green.offset = 8;
 		var->green.length = 8;
 		var->blue.offset = 0;
 		var->blue.length = 8;
 		break;
 	default:
 		err = -EINVAL;
 	}
 	var->red.msb_right = 0;
 	var->green.msb_right = 0;
 	var->blue.msb_right = 0;
 	var->transp.msb_right = 0;
 	return err;
 }
 #ifdef CONFIG_CPU_FREQ
 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
 				     unsigned long val, void *data)
 {
 	struct da8xx_fb_par *par;
 	par = container_of(nb, struct da8xx_fb_par, freq_transition);
 	if (val == CPUFREQ_PRECHANGE) {
 		lcd_disable_raster();
 	} else if (val == CPUFREQ_POSTCHANGE) {
 		lcd_calc_clk_divider(par);
 		lcd_enable_raster();
 	}
 	return 0;
 }
 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
 {
 	par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
 	return cpufreq_register_notifier(&par->freq_transition,
 					 CPUFREQ_TRANSITION_NOTIFIER);
 }
 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
 {
 	cpufreq_unregister_notifier(&par->freq_transition,
 				    CPUFREQ_TRANSITION_NOTIFIER);
 }
 #endif
 static int __devexit fb_remove(struct platform_device *dev)
 {
 	struct fb_info *info = dev_get_drvdata(&dev->dev);
 	if (info) {
 		struct da8xx_fb_par *par = info->par;
 #ifdef CONFIG_CPU_FREQ
 		lcd_da8xx_cpufreq_deregister(par);
 #endif
 		if (par->panel_power_ctrl)
 			par->panel_power_ctrl(0);
 		lcd_disable_raster();
 		lcdc_write(0, LCD_RASTER_CTRL_REG);
 		/* disable DMA  */
 		lcdc_write(0, LCD_DMA_CTRL_REG);
 		unregister_framebuffer(info);
 		fb_dealloc_cmap(&info->cmap);
 		dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
 				  par->p_palette_base);
 		dma_free_coherent(NULL, par->vram_size, par->vram_virt,
 				  par->vram_phys);
 		free_irq(par->irq, par);
 		clk_disable(par->lcdc_clk);
 		clk_put(par->lcdc_clk);
 		framebuffer_release(info);
 		iounmap((void __iomem *)da8xx_fb_reg_base);
 		release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
 	}
 	return 0;
 }
 /*
  * Function to wait for vertical sync which for this LCD peripheral
  * translates into waiting for the current raster frame to complete.
  */
 static int fb_wait_for_vsync(struct fb_info *info)
 {
 	struct da8xx_fb_par *par = info->par;
 	int ret;
 	/*
 	 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
 	 * race condition here where the ISR could have occurred just before or
 	 * just after this set. But since we are just coarsely waiting for
 	 * a frame to complete then that's OK. i.e. if the frame completed
 	 * just before this code executed then we have to wait another full
 	 * frame time but there is no way to avoid such a situation. On the
 	 * other hand if the frame completed just after then we don't need
 	 * to wait long at all. Either way we are guaranteed to return to the
 	 * user immediately after a frame completion which is all that is
 	 * required.
 	 */
 	par->vsync_flag = 0;
 	ret = wait_event_interruptible_timeout(par->vsync_wait,
 					       par->vsync_flag != 0,
 					       par->vsync_timeout);
 	if (ret < 0)
 		return ret;
 	if (ret == 0)
 		return -ETIMEDOUT;
 	if (par->panel_power_ctrl) {
 		/* Switch off panel power and backlight */
 		par->panel_power_ctrl(0);
 		/* Switch on panel power and backlight */
 		par->panel_power_ctrl(1);
 	}
 	return 0;
 }
 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
 			  unsigned long arg)
 {
 	struct lcd_sync_arg sync_arg;
 	switch (cmd) {
 	case FBIOGET_CONTRAST:
 	case FBIOPUT_CONTRAST:
 	case FBIGET_BRIGHTNESS:
 	case FBIPUT_BRIGHTNESS:
 	case FBIGET_COLOR:
 	case FBIPUT_COLOR:
 		return -ENOTTY;
 	case FBIPUT_HSYNC:
 		if (copy_from_user(&sync_arg, (char *)arg,
 				sizeof(struct lcd_sync_arg)))
 			return -EFAULT;
 		lcd_cfg_horizontal_sync(sync_arg.back_porch,
 					sync_arg.pulse_width,
 					sync_arg.front_porch);
 		break;
 	case FBIPUT_VSYNC:
 		if (copy_from_user(&sync_arg, (char *)arg,
 				sizeof(struct lcd_sync_arg)))
 			return -EFAULT;
 		lcd_cfg_vertical_sync(sync_arg.back_porch,
 					sync_arg.pulse_width,
 					sync_arg.front_porch);
 		break;
 	case FBIO_WAITFORVSYNC:
 		return fb_wait_for_vsync(info);
 	default:
 		return -EINVAL;
 	}
 	return 0;
 }
 static int cfb_blank(int blank, struct fb_info *info)
 {
 	struct da8xx_fb_par *par = info->par;
 	int ret = 0;
 	if (par->blank == blank)
 		return 0;
 	par->blank = blank;
 	switch (blank) {
 	case FB_BLANK_UNBLANK:
 		if (par->panel_power_ctrl)
 			par->panel_power_ctrl(1);
 		lcd_enable_raster();
 		break;
 	case FB_BLANK_POWERDOWN:
 		if (par->panel_power_ctrl)
 			par->panel_power_ctrl(0);
 		lcd_disable_raster();
 		break;
 	default:
 		ret = -EINVAL;
 	}
 	return ret;
 }
 /*
  * Set new x,y offsets in the virtual display for the visible area and switch
  * to the new mode.
  */
 static int da8xx_pan_display(struct fb_var_screeninfo *var,
 			     struct fb_info *fbi)
 {
 	int ret = 0;
 	struct fb_var_screeninfo new_var;
 	struct da8xx_fb_par         *par = fbi->par;
 	struct fb_fix_screeninfo    *fix = &fbi->fix;
 	unsigned int end;
 	unsigned int start;
 	unsigned long irq_flags;
 	if (var->xoffset != fbi->var.xoffset ||
 			var->yoffset != fbi->var.yoffset) {
 		memcpy(&new_var, &fbi->var, sizeof(new_var));
 		new_var.xoffset = var->xoffset;
 		new_var.yoffset = var->yoffset;
 		if (fb_check_var(&new_var, fbi))
 			ret = -EINVAL;
 		else {
 			memcpy(&fbi->var, &new_var, sizeof(new_var));
 			start	= fix->smem_start +
 				new_var.yoffset * fix->line_length +
 				new_var.xoffset * var->bits_per_pixel / 8;
 			end	= start + var->yres * fix->line_length - 1;
 			par->dma_start	= start;
 			par->dma_end	= end;
 			spin_lock_irqsave(&par->lock_for_chan_update,
 					irq_flags);
 			if (par->which_dma_channel_done == 0) {
 				lcdc_write(par->dma_start,
 					   LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 				lcdc_write(par->dma_end,
 					   LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 			} else if (par->which_dma_channel_done == 1) {
 				lcdc_write(par->dma_start,
 					   LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 				lcdc_write(par->dma_end,
 					   LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 			}
 			spin_unlock_irqrestore(&par->lock_for_chan_update,
 					irq_flags);
 		}
 	}
 	return ret;
 }
 static struct fb_ops da8xx_fb_ops = {
 	.owner = THIS_MODULE,
 	.fb_check_var = fb_check_var,
 	.fb_setcolreg = fb_setcolreg,
 	.fb_pan_display = da8xx_pan_display,
 	.fb_ioctl = fb_ioctl,
 	.fb_fillrect = cfb_fillrect,
 	.fb_copyarea = cfb_copyarea,
 	.fb_imageblit = cfb_imageblit,
 	.fb_blank = cfb_blank,
 };
 static int __devinit fb_probe(struct platform_device *device)
 {
 	struct da8xx_lcdc_platform_data *fb_pdata =
 						device->dev.platform_data;
 	struct lcd_ctrl_config *lcd_cfg;
 	struct da8xx_panel *lcdc_info;
 	struct fb_info *da8xx_fb_info;
 	struct clk *fb_clk = NULL;
 	struct clk *fb_l3ick = NULL, *fb_l4ick = NULL;
 	struct da8xx_fb_par *par;
 	resource_size_t len;
 	int ret, i;
 	if (fb_pdata == NULL) {
 		dev_err(&device->dev, "Can not get platform data\n");
 		return -ENOENT;
 	}
 	lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
 	if (!lcdc_regs) {
 		dev_err(&device->dev,
 			"Can not get memory resource for LCD controller\n");
 		return -ENOENT;
 	}
 	len = resource_size(lcdc_regs);
 	lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
 	if (!lcdc_regs)
 		return -EBUSY;
 	da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
 	if (!da8xx_fb_reg_base) {
 		ret = -EBUSY;
 		goto err_request_mem;
 	}
 	if (machine_is_am335xevm()) {
 		fb_l3ick = clk_get(&device->dev, "lcdc_ick_l3_clk");
 		if (IS_ERR(fb_l3ick)) {
 			dev_err(&device->dev, "Can not get l3 interface"
 					"clock\n");
 			ret = -ENODEV;
 			goto err_ioremap;
 		}
 		ret = clk_enable(fb_l3ick);
 		if (ret)
 			goto err_clk_put0;
 		fb_l4ick = clk_get(&device->dev, "lcdc_ick_l4_clk");
 		if (IS_ERR(fb_l4ick)) {
 			dev_err(&device->dev, "Can not get l4 interface"
 					"clock\n");
 			ret = -ENODEV;
 			goto err_clk_get0;
 		}
 		ret = clk_enable(fb_l4ick);
 		if (ret)
 			goto err_clk_put1;
 	}
 	fb_clk = clk_get(&device->dev, NULL);
 	if (IS_ERR(fb_clk)) {
 		dev_err(&device->dev, "Can not get device clock\n");
 		ret = -ENODEV;
 		goto err_clk_get1;
 	}
 	ret = clk_enable(fb_clk);
 	if (ret)
 		goto err_clk_put2;
 	/* Determine LCD IP Version */
 	switch (lcdc_read(LCD_PID_REG)) {
 	case 0x4C100102:
 		lcd_revision = LCD_VERSION_1;
 		break;
 	case 0x4F200800:
 	case 0x4F201000:
 		lcd_revision = LCD_VERSION_2;
 		break;
 	default:
 		dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
 				"defaulting to LCD revision 1\n",
 				lcdc_read(LCD_PID_REG));
 		lcd_revision = LCD_VERSION_1;
 		break;
 	}
 	for (i = 0, lcdc_info = known_lcd_panels;
 		i < ARRAY_SIZE(known_lcd_panels);
 		i++, lcdc_info++) {
 		if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
 			break;
 	}
 	if (i == ARRAY_SIZE(known_lcd_panels)) {
 		dev_err(&device->dev, "GLCD: No valid panel found\n");
 		ret = -ENODEV;
 		goto err_clk_disable;
 	} else
 		dev_info(&device->dev, "GLCD: Found %s panel\n",
 					fb_pdata->type);
 	lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
 	da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
 					&device->dev);
 	if (!da8xx_fb_info) {
 		dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
 		ret = -ENOMEM;
 		goto err_clk_disable;
 	}
 	par = da8xx_fb_info->par;
 	par->lcdc_clk = fb_clk;
 	par->pxl_clk = lcdc_info->pxl_clk;
 	if (fb_pdata->panel_power_ctrl) {
 		par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
 		par->panel_power_ctrl(1);
 	}
 	if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
 		dev_err(&device->dev, "lcd_init failed\n");
 		ret = -EFAULT;
 		goto err_release_fb;
 	}
 	/* allocate frame buffer */
 	par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
 	par->vram_size = PAGE_ALIGN(par->vram_size/8);
 	par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
 	par->vram_virt = dma_alloc_coherent(NULL,
 					    par->vram_size,
 					    (resource_size_t *) &par->vram_phys,
 					    GFP_KERNEL | GFP_DMA);
 	if (!par->vram_virt) {
 		dev_err(&device->dev,
 			"GLCD: kmalloc for frame buffer failed\n");
 		ret = -EINVAL;
 		goto err_release_fb;
 	}
 	da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
 	da8xx_fb_fix.smem_start    = par->vram_phys;
 	da8xx_fb_fix.smem_len      = par->vram_size;
 	da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
 	par->dma_start = par->vram_phys;
 	par->dma_end   = par->dma_start + lcdc_info->height *
 		da8xx_fb_fix.line_length - 1;
 	/* allocate palette buffer */
 	par->v_palette_base = dma_alloc_coherent(NULL,
 					       PALETTE_SIZE,
 					       (resource_size_t *)
 					       &par->p_palette_base,
 					       GFP_KERNEL | GFP_DMA);
 	if (!par->v_palette_base) {
 		dev_err(&device->dev,
 			"GLCD: kmalloc for palette buffer failed\n");
 		ret = -EINVAL;
 		goto err_release_fb_mem;
 	}
 	memset(par->v_palette_base, 0, PALETTE_SIZE);
 	par->irq = platform_get_irq(device, 0);
 	if (par->irq < 0) {
 		ret = -ENOENT;
 		goto err_release_pl_mem;
 	}
 	/* Initialize par */
 	da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
 	da8xx_fb_var.xres = lcdc_info->width;
 	da8xx_fb_var.xres_virtual = lcdc_info->width;
 	da8xx_fb_var.yres         = lcdc_info->height;
 	da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
 	da8xx_fb_var.grayscale =
 	    lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
 	da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
 	da8xx_fb_var.hsync_len = lcdc_info->hsw;
 	da8xx_fb_var.vsync_len = lcdc_info->vsw;
 	da8xx_fb_var.right_margin = lcdc_info->hfp;
 	da8xx_fb_var.left_margin  = lcdc_info->hbp;
 	da8xx_fb_var.lower_margin = lcdc_info->vfp;
 	da8xx_fb_var.upper_margin = lcdc_info->vbp;
 	/* Initialize fbinfo */
 	da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
 	da8xx_fb_info->fix = da8xx_fb_fix;
 	da8xx_fb_info->var = da8xx_fb_var;
 	da8xx_fb_info->fbops = &da8xx_fb_ops;
 	da8xx_fb_info->pseudo_palette = par->pseudo_palette;
 	da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
 				FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 	ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
 	if (ret)
 		goto err_release_pl_mem;
 	da8xx_fb_info->cmap.len = par->palette_sz;
 	/* initialize var_screeninfo */
 	da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
 	fb_set_var(da8xx_fb_info, &da8xx_fb_var);
 	dev_set_drvdata(&device->dev, da8xx_fb_info);
 	/* initialize the vsync wait queue */
 	init_waitqueue_head(&par->vsync_wait);
 	par->vsync_timeout = HZ / 5;
 	par->which_dma_channel_done = -1;
 	spin_lock_init(&par->lock_for_chan_update);
 	/* Register the Frame Buffer  */
 	if (register_framebuffer(da8xx_fb_info) < 0) {
 		dev_err(&device->dev,
 			"GLCD: Frame Buffer Registration Failed!\n");
 		ret = -EINVAL;
 		goto err_dealloc_cmap;
 	}
 #ifdef CONFIG_CPU_FREQ
 	ret = lcd_da8xx_cpufreq_register(par);
 	if (ret) {
 		dev_err(&device->dev, "failed to register cpufreq\n");
 		goto err_cpu_freq;
 	}
 #endif
 	if (lcd_revision == LCD_VERSION_1)
 		lcdc_irq_handler = lcdc_irq_handler_rev01;
 	else
 		lcdc_irq_handler = lcdc_irq_handler_rev02;
 	ret = request_irq(par->irq, lcdc_irq_handler, 0,
 			DRIVER_NAME, par);
 	if (ret)
 		goto irq_freq;
 	return 0;
 irq_freq:
 #ifdef CONFIG_CPU_FREQ
 	lcd_da8xx_cpufreq_deregister(par);
 err_cpu_freq:
 #endif
 	unregister_framebuffer(da8xx_fb_info);
 err_dealloc_cmap:
 	fb_dealloc_cmap(&da8xx_fb_info->cmap);
 err_release_pl_mem:
 	dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
 			  par->p_palette_base);
 err_release_fb_mem:
 	dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
 err_release_fb:
 	framebuffer_release(da8xx_fb_info);
 err_clk_disable:
 	clk_disable(fb_clk);
 err_clk_put2:
 	clk_put(fb_clk);
 err_clk_get1:
 	clk_disable(fb_l4ick);
 err_clk_put1:
 	clk_put(fb_l4ick);
 err_clk_get0:
 	clk_disable(fb_l3ick);
 err_clk_put0:
 	clk_put(fb_l3ick);
 err_ioremap:
 	iounmap((void __iomem *)da8xx_fb_reg_base);
 err_request_mem:
 	release_mem_region(lcdc_regs->start, len);
 	return ret;
 }
 #ifdef CONFIG_PM
 static int fb_suspend(struct platform_device *dev, pm_message_t state)
 {
 	struct fb_info *info = platform_get_drvdata(dev);
 	struct da8xx_fb_par *par = info->par;
 	unsigned long timeo = jiffies + msecs_to_jiffies(5000);
 	u32 stat;
 	console_lock();
 	if (par->panel_power_ctrl)
 		par->panel_power_ctrl(0);
 	fb_set_suspend(info, 1);
 	lcd_disable_raster();
 	/* Wait for the current frame to complete */
 	do {
 		if (lcd_revision == LCD_VERSION_1)
 			stat = lcdc_read(LCD_STAT_REG);
 		else
 			stat = lcdc_read(LCD_MASKED_STAT_REG);
 		cpu_relax();
 	} while (!(stat & BIT(0)) && time_before(jiffies, timeo));
 	if (lcd_revision == LCD_VERSION_1)
 		lcdc_write(stat, LCD_STAT_REG);
 	else
 		lcdc_write(stat, LCD_MASKED_STAT_REG);
 	if (time_after_eq(jiffies, timeo)) {
 		dev_err(&dev->dev, "controller timed out\n");
 		return -ETIMEDOUT;
 	}
 	clk_disable(par->lcdc_clk);
 	console_unlock();
 	return 0;
 }
 static int fb_resume(struct platform_device *dev)
 {
 	struct fb_info *info = platform_get_drvdata(dev);
 	struct da8xx_fb_par *par = info->par;
 	console_lock();
 	if (par->panel_power_ctrl)
 		par->panel_power_ctrl(1);
 	clk_enable(par->lcdc_clk);
 	lcd_enable_raster();
 	if (par->panel_power_ctrl)
 		par->panel_power_ctrl(1);
 	fb_set_suspend(info, 0);
 	console_unlock();
 	return 0;
 }
 #else
 #define fb_suspend NULL
 #define fb_resume NULL
 #endif
 static struct platform_driver da8xx_fb_driver = {
 	.probe = fb_probe,
 	.remove = __devexit_p(fb_remove),
 	.suspend = fb_suspend,
 	.resume = fb_resume,
 	.driver = {
 		   .name = DRIVER_NAME,
 		   .owner = THIS_MODULE,
 		   },
 };
 static int __init da8xx_fb_init(void)
 {
 	return platform_driver_register(&da8xx_fb_driver);
 }
 static void __exit da8xx_fb_cleanup(void)
 {
 	platform_driver_unregister(&da8xx_fb_driver);
 }
 module_init(da8xx_fb_init);
 module_exit(da8xx_fb_cleanup);
 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
 MODULE_AUTHOR("Texas Instruments");
 MODULE_LICENSE("GPL");