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drivers/cpufreq/pmac64-cpufreq.c
17.5 KB
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// SPDX-License-Identifier: GPL-2.0-only |
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/* * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org> * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de> * |
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* This driver adds basic cpufreq support for SMU & 970FX based G5 Macs, * that is iMac G5 and latest single CPU desktop. */ |
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#undef DEBUG |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/module.h> #include <linux/types.h> #include <linux/errno.h> #include <linux/kernel.h> #include <linux/delay.h> #include <linux/sched.h> |
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#include <linux/cpufreq.h> #include <linux/init.h> #include <linux/completion.h> |
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#include <linux/mutex.h> |
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#include <linux/of_device.h> |
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#include <asm/prom.h> #include <asm/machdep.h> #include <asm/irq.h> #include <asm/sections.h> #include <asm/cputable.h> #include <asm/time.h> #include <asm/smu.h> |
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#include <asm/pmac_pfunc.h> |
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#define DBG(fmt...) pr_debug(fmt) |
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/* see 970FX user manual */ #define SCOM_PCR 0x0aa001 /* PCR scom addr */ #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */ #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */ #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */ #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */ #define PCR_SPEED_MASK 0x000e0000U /* speed mask */ #define PCR_SPEED_SHIFT 17 #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */ #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */ #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */ #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */ #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */ #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */ #define SCOM_PSR 0x408001 /* PSR scom addr */ /* warning: PSR is a 64 bits register */ #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */ #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */ #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */ #define PSR_CUR_SPEED_SHIFT (56) /* * The G5 only supports two frequencies (Quarter speed is not supported) */ #define CPUFREQ_HIGH 0 #define CPUFREQ_LOW 1 static struct cpufreq_frequency_table g5_cpu_freqs[] = { |
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{0, CPUFREQ_HIGH, 0}, {0, CPUFREQ_LOW, 0}, {0, 0, CPUFREQ_TABLE_END}, |
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}; |
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/* Power mode data is an array of the 32 bits PCR values to use for |
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* the various frequencies, retrieved from the device-tree |
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*/ |
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static int g5_pmode_cur; |
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static void (*g5_switch_volt)(int speed_mode); static int (*g5_switch_freq)(int speed_mode); static int (*g5_query_freq)(void); |
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static unsigned long transition_latency; |
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#ifdef CONFIG_PMAC_SMU |
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static const u32 *g5_pmode_data; |
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static int g5_pmode_max; |
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static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */ static int g5_fvt_count; /* number of op. points */ static int g5_fvt_cur; /* current op. point */ |
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/* * SMU based voltage switching for Neo2 platforms */ |
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static void g5_smu_switch_volt(int speed_mode) |
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{ struct smu_simple_cmd cmd; |
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DECLARE_COMPLETION_ONSTACK(comp); |
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smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete, &comp, 'V', 'S', 'L', 'E', 'W', 0xff, g5_fvt_cur+1, speed_mode); wait_for_completion(&comp); } |
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/* * Platform function based voltage/vdnap switching for Neo2 */ static struct pmf_function *pfunc_set_vdnap0; static struct pmf_function *pfunc_vdnap0_complete; static void g5_vdnap_switch_volt(int speed_mode) |
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{ |
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struct pmf_args args; u32 slew, done = 0; unsigned long timeout; |
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slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0; args.count = 1; args.u[0].p = &slew; |
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pmf_call_one(pfunc_set_vdnap0, &args); |
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/* It's an irq GPIO so we should be able to just block here, * I'll do that later after I've properly tested the IRQ code for * platform functions */ timeout = jiffies + HZ/10; while(!time_after(jiffies, timeout)) { args.count = 1; args.u[0].p = &done; pmf_call_one(pfunc_vdnap0_complete, &args); if (done) break; |
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usleep_range(1000, 1000); |
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} if (done == 0) |
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pr_warn("Timeout in clock slewing ! "); |
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} |
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/* * SCOM based frequency switching for 970FX rev3 */ static int g5_scom_switch_freq(int speed_mode) { unsigned long flags; int to; |
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/* If frequency is going up, first ramp up the voltage */ if (speed_mode < g5_pmode_cur) g5_switch_volt(speed_mode); |
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local_irq_save(flags); |
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/* Clear PCR high */ scom970_write(SCOM_PCR, 0); /* Clear PCR low */ scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0); /* Set PCR low */ scom970_write(SCOM_PCR, PCR_HILO_SELECT | g5_pmode_data[speed_mode]); /* Wait for completion */ for (to = 0; to < 10; to++) { unsigned long psr = scom970_read(SCOM_PSR); if ((psr & PSR_CMD_RECEIVED) == 0 && (((psr >> PSR_CUR_SPEED_SHIFT) ^ (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3) == 0) break; if (psr & PSR_CMD_COMPLETED) break; udelay(100); } |
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local_irq_restore(flags); |
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/* If frequency is going down, last ramp the voltage */ if (speed_mode > g5_pmode_cur) g5_switch_volt(speed_mode); g5_pmode_cur = speed_mode; ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; |
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return 0; } |
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static int g5_scom_query_freq(void) |
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{ unsigned long psr = scom970_read(SCOM_PSR); int i; for (i = 0; i <= g5_pmode_max; i++) if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0) break; return i; } |
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/* |
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* Fake voltage switching for platforms with missing support */ static void g5_dummy_switch_volt(int speed_mode) { } |
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#endif /* CONFIG_PMAC_SMU */ |
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/* |
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* Platform function based voltage switching for PowerMac7,2 & 7,3 */ static struct pmf_function *pfunc_cpu0_volt_high; static struct pmf_function *pfunc_cpu0_volt_low; static struct pmf_function *pfunc_cpu1_volt_high; static struct pmf_function *pfunc_cpu1_volt_low; static void g5_pfunc_switch_volt(int speed_mode) { if (speed_mode == CPUFREQ_HIGH) { if (pfunc_cpu0_volt_high) pmf_call_one(pfunc_cpu0_volt_high, NULL); if (pfunc_cpu1_volt_high) pmf_call_one(pfunc_cpu1_volt_high, NULL); } else { if (pfunc_cpu0_volt_low) pmf_call_one(pfunc_cpu0_volt_low, NULL); if (pfunc_cpu1_volt_low) pmf_call_one(pfunc_cpu1_volt_low, NULL); } |
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usleep_range(10000, 10000); /* should be faster , to fix */ |
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} /* * Platform function based frequency switching for PowerMac7,2 & 7,3 */ static struct pmf_function *pfunc_cpu_setfreq_high; static struct pmf_function *pfunc_cpu_setfreq_low; static struct pmf_function *pfunc_cpu_getfreq; |
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static struct pmf_function *pfunc_slewing_done; |
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static int g5_pfunc_switch_freq(int speed_mode) { struct pmf_args args; u32 done = 0; unsigned long timeout; |
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int rc; DBG("g5_pfunc_switch_freq(%d) ", speed_mode); |
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/* If frequency is going up, first ramp up the voltage */ if (speed_mode < g5_pmode_cur) g5_switch_volt(speed_mode); /* Do it */ if (speed_mode == CPUFREQ_HIGH) |
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rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL); |
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else |
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rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL); if (rc) |
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pr_warn("pfunc switch error %d ", rc); |
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/* It's an irq GPIO so we should be able to just block here, * I'll do that later after I've properly tested the IRQ code for * platform functions */ timeout = jiffies + HZ/10; while(!time_after(jiffies, timeout)) { args.count = 1; args.u[0].p = &done; pmf_call_one(pfunc_slewing_done, &args); if (done) break; |
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usleep_range(500, 500); |
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} if (done == 0) |
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pr_warn("Timeout in clock slewing ! "); |
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/* If frequency is going down, last ramp the voltage */ if (speed_mode > g5_pmode_cur) g5_switch_volt(speed_mode); g5_pmode_cur = speed_mode; ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul; return 0; } static int g5_pfunc_query_freq(void) { struct pmf_args args; u32 val = 0; args.count = 1; args.u[0].p = &val; pmf_call_one(pfunc_cpu_getfreq, &args); return val ? CPUFREQ_HIGH : CPUFREQ_LOW; } |
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/* * Common interface to the cpufreq core */ |
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static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index) |
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{ |
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return g5_switch_freq(index); |
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} static unsigned int g5_cpufreq_get_speed(unsigned int cpu) { return g5_cpu_freqs[g5_pmode_cur].frequency; } static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy) { |
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cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency); return 0; |
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} |
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static struct cpufreq_driver g5_cpufreq_driver = { .name = "powermac", |
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.flags = CPUFREQ_CONST_LOOPS, .init = g5_cpufreq_cpu_init, |
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.verify = cpufreq_generic_frequency_table_verify, |
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.target_index = g5_cpufreq_target, |
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.get = g5_cpufreq_get_speed, |
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.attr = cpufreq_generic_attr, |
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}; |
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#ifdef CONFIG_PMAC_SMU |
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static int __init g5_neo2_cpufreq_init(struct device_node *cpunode) |
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{ |
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unsigned int psize, ssize; |
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unsigned long max_freq; |
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char *freq_method, *volt_method; |
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const u32 *valp; u32 pvr_hi; |
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int use_volts_vdnap = 0; int use_volts_smu = 0; |
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int rc = -ENODEV; |
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/* Check supported platforms */ |
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if (of_machine_is_compatible("PowerMac8,1") || of_machine_is_compatible("PowerMac8,2") || |
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of_machine_is_compatible("PowerMac9,1") || of_machine_is_compatible("PowerMac12,1")) |
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use_volts_smu = 1; |
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else if (of_machine_is_compatible("PowerMac11,2")) |
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use_volts_vdnap = 1; else return -ENODEV; |
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/* Check 970FX for now */ |
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valp = of_get_property(cpunode, "cpu-version", NULL); |
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if (!valp) { DBG("No cpu-version property ! "); goto bail_noprops; } |
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pvr_hi = (*valp) >> 16; if (pvr_hi != 0x3c && pvr_hi != 0x44) { |
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pr_err("Unsupported CPU version "); |
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goto bail_noprops; } /* Look for the powertune data in the device-tree */ |
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g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize); |
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if (!g5_pmode_data) { DBG("No power-mode-data ! "); goto bail_noprops; } g5_pmode_max = psize / sizeof(u32) - 1; |
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if (use_volts_smu) { |
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const struct smu_sdbp_header *shdr; |
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/* Look for the FVT table */ shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL); if (!shdr) goto bail_noprops; g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1]; |
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ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr); g5_fvt_count = ssize / sizeof(*g5_fvt_table); |
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g5_fvt_cur = 0; /* Sanity checking */ if (g5_fvt_count < 1 || g5_pmode_max < 1) goto bail_noprops; g5_switch_volt = g5_smu_switch_volt; volt_method = "SMU"; } else if (use_volts_vdnap) { struct device_node *root; root = of_find_node_by_path("/"); if (root == NULL) { |
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pr_err("Can't find root of device tree "); |
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goto bail_noprops; } pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0"); pfunc_vdnap0_complete = pmf_find_function(root, "slewing-done"); |
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of_node_put(root); |
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if (pfunc_set_vdnap0 == NULL || pfunc_vdnap0_complete == NULL) { |
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pr_err("Can't find required platform function "); |
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goto bail_noprops; } g5_switch_volt = g5_vdnap_switch_volt; volt_method = "GPIO"; } else { g5_switch_volt = g5_dummy_switch_volt; volt_method = "none"; } |
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/* * From what I see, clock-frequency is always the maximal frequency. * The current driver can not slew sysclk yet, so we really only deal * with powertune steps for now. We also only implement full freq and * half freq in this version. So far, I haven't yet seen a machine * supporting anything else. */ |
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valp = of_get_property(cpunode, "clock-frequency", NULL); |
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if (!valp) return -ENODEV; max_freq = (*valp)/1000; g5_cpu_freqs[0].frequency = max_freq; g5_cpu_freqs[1].frequency = max_freq/2; |
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/* Set callbacks */ |
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transition_latency = 12000; |
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g5_switch_freq = g5_scom_switch_freq; g5_query_freq = g5_scom_query_freq; freq_method = "SCOM"; |
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/* Force apply current frequency to make sure everything is in * sync (voltage is right for example). Firmware may leave us with * a strange setting ... */ |
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g5_switch_volt(CPUFREQ_HIGH); msleep(10); g5_pmode_cur = -1; g5_switch_freq(g5_query_freq()); |
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pr_info("Registering G5 CPU frequency driver "); pr_info("Frequency method: %s, Voltage method: %s ", freq_method, volt_method); pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz ", |
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g5_cpu_freqs[1].frequency/1000, g5_cpu_freqs[0].frequency/1000, g5_cpu_freqs[g5_pmode_cur].frequency/1000); rc = cpufreq_register_driver(&g5_cpufreq_driver); /* We keep the CPU node on hold... hopefully, Apple G5 don't have * hotplug CPU with a dynamic device-tree ... */ return rc; bail_noprops: of_node_put(cpunode); return rc; } |
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#endif /* CONFIG_PMAC_SMU */ |
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static int __init g5_pm72_cpufreq_init(struct device_node *cpunode) |
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{ |
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struct device_node *cpuid = NULL, *hwclock = NULL; |
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const u8 *eeprom = NULL; const u32 *valp; |
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u64 max_freq, min_freq, ih, il; int has_volt = 1, rc = 0; |
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DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and" " RackMac3,1... "); |
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/* Lookup the cpuid eeprom node */ cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0"); if (cpuid != NULL) |
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eeprom = of_get_property(cpuid, "cpuid", NULL); |
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if (eeprom == NULL) { |
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pr_err("Can't find cpuid EEPROM ! "); |
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rc = -ENODEV; goto bail; } /* Lookup the i2c hwclock */ |
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for_each_node_by_name(hwclock, "i2c-hwclock") { |
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const char *loc = of_get_property(hwclock, |
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"hwctrl-location", NULL); |
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if (loc == NULL) continue; if (strcmp(loc, "CPU CLOCK")) continue; |
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if (!of_get_property(hwclock, "platform-get-frequency", NULL)) |
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continue; break; } if (hwclock == NULL) { |
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pr_err("Can't find i2c clock chip ! "); |
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rc = -ENODEV; goto bail; } |
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DBG("cpufreq: i2c clock chip found: %pOF ", hwclock); |
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/* Now get all the platform functions */ pfunc_cpu_getfreq = pmf_find_function(hwclock, "get-frequency"); pfunc_cpu_setfreq_high = pmf_find_function(hwclock, "set-frequency-high"); pfunc_cpu_setfreq_low = pmf_find_function(hwclock, "set-frequency-low"); pfunc_slewing_done = pmf_find_function(hwclock, "slewing-done"); pfunc_cpu0_volt_high = pmf_find_function(hwclock, "set-voltage-high-0"); pfunc_cpu0_volt_low = pmf_find_function(hwclock, "set-voltage-low-0"); pfunc_cpu1_volt_high = pmf_find_function(hwclock, "set-voltage-high-1"); pfunc_cpu1_volt_low = pmf_find_function(hwclock, "set-voltage-low-1"); /* Check we have minimum requirements */ if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL || pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) { |
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pr_err("Can't find platform functions ! "); |
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rc = -ENODEV; goto bail; } /* Check that we have complete sets */ if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) { pmf_put_function(pfunc_cpu0_volt_high); pmf_put_function(pfunc_cpu0_volt_low); pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL; has_volt = 0; } if (!has_volt || pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) { pmf_put_function(pfunc_cpu1_volt_high); pmf_put_function(pfunc_cpu1_volt_low); pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL; } /* Note: The device tree also contains a "platform-set-values" * function for which I haven't quite figured out the usage. It * might have to be called on init and/or wakeup, I'm not too sure * but things seem to work fine without it so far ... */ /* Get max frequency from device-tree */ |
e2eb63927
|
553 |
valp = of_get_property(cpunode, "clock-frequency", NULL); |
9a699aefa
|
554 |
if (!valp) { |
1c5864e26
|
555 556 |
pr_err("Can't find CPU frequency ! "); |
9a699aefa
|
557 558 559 560 561 562 563 564 565 566 567 568 |
rc = -ENODEV; goto bail; } max_freq = (*valp)/1000; /* Now calculate reduced frequency by using the cpuid input freq * ratio. This requires 64 bits math unless we are willing to lose * some precision */ ih = *((u32 *)(eeprom + 0x10)); il = *((u32 *)(eeprom + 0x20)); |
7ed14c217
|
569 570 571 |
/* Check for machines with no useful settings */ if (il == ih) { |
1c5864e26
|
572 573 |
pr_warn("No low frequency mode available on this model ! "); |
7ed14c217
|
574 575 576 |
rc = -ENODEV; goto bail; } |
9a699aefa
|
577 578 579 580 581 582 |
min_freq = 0; if (ih != 0 && il != 0) min_freq = (max_freq * il) / ih; /* Sanity check */ if (min_freq >= max_freq || min_freq < 1000) { |
1c5864e26
|
583 584 |
pr_err("Can't calculate low frequency ! "); |
7ed14c217
|
585 |
rc = -ENXIO; |
9a699aefa
|
586 587 588 589 |
goto bail; } g5_cpu_freqs[0].frequency = max_freq; g5_cpu_freqs[1].frequency = min_freq; |
af671d8b2
|
590 591 |
/* Based on a measurement on Xserve G5, rounded up. */ transition_latency = 10 * NSEC_PER_MSEC; |
9a699aefa
|
592 593 594 595 596 597 598 599 600 601 602 603 604 |
/* Set callbacks */ g5_switch_volt = g5_pfunc_switch_volt; g5_switch_freq = g5_pfunc_switch_freq; g5_query_freq = g5_pfunc_query_freq; /* Force apply current frequency to make sure everything is in * sync (voltage is right for example). Firmware may leave us with * a strange setting ... */ g5_switch_volt(CPUFREQ_HIGH); msleep(10); g5_pmode_cur = -1; g5_switch_freq(g5_query_freq()); |
b49c22a6c
|
605 606 607 608 609 610 611 |
pr_info("Registering G5 CPU frequency driver "); pr_info("Frequency method: i2c/pfunc, Voltage method: %s ", has_volt ? "i2c/pfunc" : "none"); pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz ", |
9a699aefa
|
612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 |
g5_cpu_freqs[1].frequency/1000, g5_cpu_freqs[0].frequency/1000, g5_cpu_freqs[g5_pmode_cur].frequency/1000); rc = cpufreq_register_driver(&g5_cpufreq_driver); bail: if (rc != 0) { pmf_put_function(pfunc_cpu_getfreq); pmf_put_function(pfunc_cpu_setfreq_high); pmf_put_function(pfunc_cpu_setfreq_low); pmf_put_function(pfunc_slewing_done); pmf_put_function(pfunc_cpu0_volt_high); pmf_put_function(pfunc_cpu0_volt_low); pmf_put_function(pfunc_cpu1_volt_high); pmf_put_function(pfunc_cpu1_volt_low); } of_node_put(hwclock); of_node_put(cpuid); of_node_put(cpunode); return rc; } |
9a699aefa
|
634 635 |
static int __init g5_cpufreq_init(void) { |
760287ab9
|
636 |
struct device_node *cpunode; |
7ed14c217
|
637 |
int rc = 0; |
9a699aefa
|
638 |
|
760287ab9
|
639 640 641 |
/* Get first CPU node */ cpunode = of_cpu_device_node_get(0); if (cpunode == NULL) { |
1c5864e26
|
642 643 |
pr_err("Can't find any CPU node "); |
9a699aefa
|
644 645 |
return -ENODEV; } |
71a157e8e
|
646 647 648 |
if (of_machine_is_compatible("PowerMac7,2") || of_machine_is_compatible("PowerMac7,3") || of_machine_is_compatible("RackMac3,1")) |
760287ab9
|
649 |
rc = g5_pm72_cpufreq_init(cpunode); |
e272a2853
|
650 |
#ifdef CONFIG_PMAC_SMU |
9a699aefa
|
651 |
else |
760287ab9
|
652 |
rc = g5_neo2_cpufreq_init(cpunode); |
e272a2853
|
653 |
#endif /* CONFIG_PMAC_SMU */ |
9a699aefa
|
654 |
|
9a699aefa
|
655 656 |
return rc; } |
4350147a8
|
657 658 659 660 |
module_init(g5_cpufreq_init); MODULE_LICENSE("GPL"); |