Blame view
include/linux/clk-provider.h
24.5 KB
b2476490e
|
1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
/* * linux/include/linux/clk-provider.h * * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __LINUX_CLK_PROVIDER_H #define __LINUX_CLK_PROVIDER_H #include <linux/clk.h> |
aa514ce34
|
15 |
#include <linux/io.h> |
355bb165c
|
16 |
#include <linux/of.h> |
b2476490e
|
17 18 |
#ifdef CONFIG_COMMON_CLK |
b2476490e
|
19 20 21 22 23 24 25 26 27 28 |
/* * flags used across common struct clk. these flags should only affect the * top-level framework. custom flags for dealing with hardware specifics * belong in struct clk_foo */ #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ |
f7d8caadf
|
29 |
#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
a093bde2b
|
30 |
#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
819c1de34
|
31 |
#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
5279fc402
|
32 |
#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
b2476490e
|
33 |
|
0197b3ea0
|
34 |
struct clk_hw; |
035a61c31
|
35 |
struct clk_core; |
c646cbf10
|
36 |
struct dentry; |
0197b3ea0
|
37 |
|
b2476490e
|
38 39 40 41 42 43 |
/** * struct clk_ops - Callback operations for hardware clocks; these are to * be provided by the clock implementation, and will be called by drivers * through the clk_* api. * * @prepare: Prepare the clock for enabling. This must not return until |
725b418b4
|
44 45 46 47 |
* the clock is fully prepared, and it's safe to call clk_enable. * This callback is intended to allow clock implementations to * do any initialisation that may sleep. Called with * prepare_lock held. |
b2476490e
|
48 49 |
* * @unprepare: Release the clock from its prepared state. This will typically |
725b418b4
|
50 51 |
* undo any work done in the @prepare callback. Called with * prepare_lock held. |
b2476490e
|
52 |
* |
3d6ee287a
|
53 54 55 56 |
* @is_prepared: Queries the hardware to determine if the clock is prepared. * This function is allowed to sleep. Optional, if this op is not * set then the prepare count will be used. * |
3cc8247f1
|
57 58 59 60 |
* @unprepare_unused: Unprepare the clock atomically. Only called from * clk_disable_unused for prepare clocks with special needs. * Called with prepare mutex held. This function may sleep. * |
b2476490e
|
61 |
* @enable: Enable the clock atomically. This must not return until the |
725b418b4
|
62 63 64 |
* clock is generating a valid clock signal, usable by consumer * devices. Called with enable_lock held. This function must not * sleep. |
b2476490e
|
65 66 |
* * @disable: Disable the clock atomically. Called with enable_lock held. |
725b418b4
|
67 |
* This function must not sleep. |
b2476490e
|
68 |
* |
119c71276
|
69 |
* @is_enabled: Queries the hardware to determine if the clock is enabled. |
725b418b4
|
70 71 |
* This function must not sleep. Optional, if this op is not * set then the enable count will be used. |
119c71276
|
72 |
* |
7c045a55c
|
73 74 75 76 77 |
* @disable_unused: Disable the clock atomically. Only called from * clk_disable_unused for gate clocks with special needs. * Called with enable_lock held. This function must not * sleep. * |
7ce3e8ccb
|
78 |
* @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
725b418b4
|
79 80 81 82 |
* parent rate is an input parameter. It is up to the caller to * ensure that the prepare_mutex is held across this call. * Returns the calculated rate. Optional, but recommended - if * this op is not set then clock rate will be initialized to 0. |
b2476490e
|
83 84 |
* * @round_rate: Given a target rate as input, returns the closest rate actually |
54e73016d
|
85 86 |
* supported by the clock. The parent rate is an input/output * parameter. |
b2476490e
|
87 |
* |
71472c0c0
|
88 89 90 91 |
* @determine_rate: Given a target rate as input, returns the closest rate * actually supported by the clock, and optionally the parent clock * that should be used to provide the clock rate. * |
b2476490e
|
92 |
* @set_parent: Change the input source of this clock; for clocks with multiple |
54e73016d
|
93 94 95 96 97 98 |
* possible parents specify a new parent by passing in the index * as a u8 corresponding to the parent in either the .parent_names * or .parents arrays. This function in affect translates an * array index into the value programmed into the hardware. * Returns 0 on success, -EERROR otherwise. * |
b2476490e
|
99 |
* @get_parent: Queries the hardware to determine the parent of a clock. The |
725b418b4
|
100 101 102 103 104 105 106 107 |
* return value is a u8 which specifies the index corresponding to * the parent clock. This index can be applied to either the * .parent_names or .parents arrays. In short, this function * translates the parent value read from hardware into an array * index. Currently only called when the clock is initialized by * __clk_init. This callback is mandatory for clocks with * multiple parents. It is optional (and unnecessary) for clocks * with 0 or 1 parents. |
b2476490e
|
108 |
* |
1c0035d71
|
109 110 111 112 113 |
* @set_rate: Change the rate of this clock. The requested rate is specified * by the second argument, which should typically be the return * of .round_rate call. The third argument gives the parent rate * which is likely helpful for most .set_rate implementation. * Returns 0 on success, -EERROR otherwise. |
b2476490e
|
114 |
* |
3fa2252b7
|
115 116 117 118 119 120 121 122 123 124 125 |
* @set_rate_and_parent: Change the rate and the parent of this clock. The * requested rate is specified by the second argument, which * should typically be the return of .round_rate call. The * third argument gives the parent rate which is likely helpful * for most .set_rate_and_parent implementation. The fourth * argument gives the parent index. This callback is optional (and * unnecessary) for clocks with 0 or 1 parents as well as * for clocks that can tolerate switching the rate and the parent * separately via calls to .set_parent and .set_rate. * Returns 0 on success, -EERROR otherwise. * |
54e73016d
|
126 127 128 129 130 131 132 |
* @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy * is expressed in ppb (parts per billion). The parent accuracy is * an input parameter. * Returns the calculated accuracy. Optional - if this op is not * set then clock accuracy will be initialized to parent accuracy * or 0 (perfect clock) if clock has no parent. * |
9824cf73c
|
133 134 135 136 |
* @get_phase: Queries the hardware to get the current phase of a clock. * Returned values are 0-359 degrees on success, negative * error codes on failure. * |
e59c5371f
|
137 138 139 140 |
* @set_phase: Shift the phase this clock signal in degrees specified * by the second argument. Valid values for degrees are * 0-359. Return 0 on success, otherwise -EERROR. * |
54e73016d
|
141 142 143 144 145 |
* @init: Perform platform-specific initialization magic. * This is not not used by any of the basic clock types. * Please consider other ways of solving initialization problems * before using this callback, as its use is discouraged. * |
c646cbf10
|
146 147 148 149 150 151 |
* @debug_init: Set up type-specific debugfs entries for this clock. This * is called once, after the debugfs directory entry for this * clock has been created. The dentry pointer representing that * directory is provided as an argument. Called with * prepare_lock held. Returns 0 on success, -EERROR otherwise. * |
3fa2252b7
|
152 |
* |
b2476490e
|
153 154 155 156 |
* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow * implementations to split any work between atomic (enable) and sleepable * (prepare) contexts. If enabling a clock requires code that might sleep, * this must be done in clk_prepare. Clock enable code that will never be |
7ce3e8ccb
|
157 |
* called in a sleepable context may be implemented in clk_enable. |
b2476490e
|
158 159 160 161 162 163 164 165 166 |
* * Typically, drivers will call clk_prepare when a clock may be needed later * (eg. when a device is opened), and clk_enable when the clock is actually * required (eg. from an interrupt). Note that clk_prepare MUST have been * called before clk_enable. */ struct clk_ops { int (*prepare)(struct clk_hw *hw); void (*unprepare)(struct clk_hw *hw); |
3d6ee287a
|
167 |
int (*is_prepared)(struct clk_hw *hw); |
3cc8247f1
|
168 |
void (*unprepare_unused)(struct clk_hw *hw); |
b2476490e
|
169 170 171 |
int (*enable)(struct clk_hw *hw); void (*disable)(struct clk_hw *hw); int (*is_enabled)(struct clk_hw *hw); |
7c045a55c
|
172 |
void (*disable_unused)(struct clk_hw *hw); |
b2476490e
|
173 174 |
unsigned long (*recalc_rate)(struct clk_hw *hw, unsigned long parent_rate); |
54e73016d
|
175 176 |
long (*round_rate)(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate); |
1c8e60044
|
177 178 179 180 181 182 |
long (*determine_rate)(struct clk_hw *hw, unsigned long rate, unsigned long min_rate, unsigned long max_rate, unsigned long *best_parent_rate, struct clk_hw **best_parent_hw); |
b2476490e
|
183 184 |
int (*set_parent)(struct clk_hw *hw, u8 index); u8 (*get_parent)(struct clk_hw *hw); |
54e73016d
|
185 186 |
int (*set_rate)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate); |
3fa2252b7
|
187 188 189 |
int (*set_rate_and_parent)(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); |
5279fc402
|
190 191 |
unsigned long (*recalc_accuracy)(struct clk_hw *hw, unsigned long parent_accuracy); |
9824cf73c
|
192 |
int (*get_phase)(struct clk_hw *hw); |
e59c5371f
|
193 |
int (*set_phase)(struct clk_hw *hw, int degrees); |
b2476490e
|
194 |
void (*init)(struct clk_hw *hw); |
c646cbf10
|
195 |
int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); |
b2476490e
|
196 |
}; |
0197b3ea0
|
197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 |
/** * struct clk_init_data - holds init data that's common to all clocks and is * shared between the clock provider and the common clock framework. * * @name: clock name * @ops: operations this clock supports * @parent_names: array of string names for all possible parents * @num_parents: number of possible parents * @flags: framework-level hints and quirks */ struct clk_init_data { const char *name; const struct clk_ops *ops; const char **parent_names; u8 num_parents; unsigned long flags; }; /** * struct clk_hw - handle for traversing from a struct clk to its corresponding * hardware-specific structure. struct clk_hw should be declared within struct * clk_foo and then referenced by the struct clk instance that uses struct * clk_foo's clk_ops * |
035a61c31
|
221 222 223 224 225 |
* @core: pointer to the struct clk_core instance that points back to this * struct clk_hw instance * * @clk: pointer to the per-user struct clk instance that can be used to call * into the clk API |
0197b3ea0
|
226 227 228 229 230 |
* * @init: pointer to struct clk_init_data that contains the init data shared * with the common clock framework. */ struct clk_hw { |
035a61c31
|
231 |
struct clk_core *core; |
0197b3ea0
|
232 |
struct clk *clk; |
dc4cd941c
|
233 |
const struct clk_init_data *init; |
0197b3ea0
|
234 |
}; |
9d9f78ed9
|
235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 |
/* * DOC: Basic clock implementations common to many platforms * * Each basic clock hardware type is comprised of a structure describing the * clock hardware, implementations of the relevant callbacks in struct clk_ops, * unique flags for that hardware type, a registration function and an * alternative macro for static initialization */ /** * struct clk_fixed_rate - fixed-rate clock * @hw: handle between common and hardware-specific interfaces * @fixed_rate: constant frequency of clock */ struct clk_fixed_rate { struct clk_hw hw; unsigned long fixed_rate; |
0903ea601
|
252 |
unsigned long fixed_accuracy; |
9d9f78ed9
|
253 254 |
u8 flags; }; |
bffad66e3
|
255 |
extern const struct clk_ops clk_fixed_rate_ops; |
9d9f78ed9
|
256 257 258 |
struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate); |
0903ea601
|
259 260 261 |
struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy); |
9d9f78ed9
|
262 |
|
015ba4024
|
263 |
void of_fixed_clk_setup(struct device_node *np); |
9d9f78ed9
|
264 265 266 267 268 269 270 271 272 273 274 275 |
/** * struct clk_gate - gating clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling gate * @bit_idx: single bit controlling gate * @flags: hardware-specific flags * @lock: register lock * * Clock which can gate its output. Implements .enable & .disable * * Flags: |
1f73f31ad
|
276 |
* CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
725b418b4
|
277 278 |
* enable the clock. Setting this flag does the opposite: setting the bit * disable the clock and clearing it enables the clock |
045779942
|
279 |
* CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit |
725b418b4
|
280 281 282 |
* of this register, and mask of gate bits are in higher 16-bit of this * register. While setting the gate bits, higher 16-bit should also be * updated to indicate changing gate bits. |
9d9f78ed9
|
283 284 285 286 287 288 289 |
*/ struct clk_gate { struct clk_hw hw; void __iomem *reg; u8 bit_idx; u8 flags; spinlock_t *lock; |
9d9f78ed9
|
290 291 292 |
}; #define CLK_GATE_SET_TO_DISABLE BIT(0) |
045779942
|
293 |
#define CLK_GATE_HIWORD_MASK BIT(1) |
9d9f78ed9
|
294 |
|
bffad66e3
|
295 |
extern const struct clk_ops clk_gate_ops; |
9d9f78ed9
|
296 297 298 299 |
struct clk *clk_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock); |
4e3c021fb
|
300 |
void clk_unregister_gate(struct clk *clk); |
9d9f78ed9
|
301 |
|
357c3f0a6
|
302 303 304 305 |
struct clk_div_table { unsigned int val; unsigned int div; }; |
9d9f78ed9
|
306 307 308 309 310 311 312 |
/** * struct clk_divider - adjustable divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @shift: shift to the divider bit field * @width: width of the divider bit field |
357c3f0a6
|
313 |
* @table: array of value/divider pairs, last entry should have div = 0 |
9d9f78ed9
|
314 315 316 317 318 319 320 |
* @lock: register lock * * Clock with an adjustable divider affecting its output frequency. Implements * .recalc_rate, .set_rate and .round_rate * * Flags: * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the |
725b418b4
|
321 322 |
* register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is * the raw value read from the register, with the value of zero considered |
056b20531
|
323 |
* invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
9d9f78ed9
|
324 |
* CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
725b418b4
|
325 |
* the hardware register |
056b20531
|
326 327 328 329 330 |
* CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. * Some hardware implementations gracefully handle this case and allow a * zero divisor by not modifying their input clock * (divide by one / bypass). |
d57dfe750
|
331 |
* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit |
725b418b4
|
332 333 334 |
* of this register, and mask of divider bits are in higher 16-bit of this * register. While setting the divider bits, higher 16-bit should also be * updated to indicate changing divider bits. |
774b51439
|
335 336 |
* CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded * to the closest integer instead of the up one. |
79c6ab509
|
337 338 |
* CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should * not be changed by the clock framework. |
9d9f78ed9
|
339 340 341 342 343 344 345 |
*/ struct clk_divider { struct clk_hw hw; void __iomem *reg; u8 shift; u8 width; u8 flags; |
357c3f0a6
|
346 |
const struct clk_div_table *table; |
9d9f78ed9
|
347 |
spinlock_t *lock; |
9d9f78ed9
|
348 349 350 351 |
}; #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
056b20531
|
352 |
#define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
d57dfe750
|
353 |
#define CLK_DIVIDER_HIWORD_MASK BIT(3) |
774b51439
|
354 |
#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
79c6ab509
|
355 |
#define CLK_DIVIDER_READ_ONLY BIT(5) |
9d9f78ed9
|
356 |
|
bffad66e3
|
357 |
extern const struct clk_ops clk_divider_ops; |
bca9690b9
|
358 359 360 361 362 363 364 365 366 367 |
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val, const struct clk_div_table *table, unsigned long flags); long divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate, const struct clk_div_table *table, u8 width, unsigned long flags); int divider_get_val(unsigned long rate, unsigned long parent_rate, const struct clk_div_table *table, u8 width, unsigned long flags); |
9d9f78ed9
|
368 369 370 371 |
struct clk *clk_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, spinlock_t *lock); |
357c3f0a6
|
372 373 374 375 376 |
struct clk *clk_register_divider_table(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); |
4e3c021fb
|
377 |
void clk_unregister_divider(struct clk *clk); |
9d9f78ed9
|
378 379 380 381 382 383 384 385 |
/** * struct clk_mux - multiplexer clock * * @hw: handle between common and hardware-specific interfaces * @reg: register controlling multiplexer * @shift: shift to multiplexer bit field * @width: width of mutliplexer bit field |
3566d40c1
|
386 |
* @flags: hardware-specific flags |
9d9f78ed9
|
387 388 389 390 391 392 393 |
* @lock: register lock * * Clock with multiple selectable parents. Implements .get_parent, .set_parent * and .recalc_rate * * Flags: * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 |
1f73f31ad
|
394 |
* CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
ba492e900
|
395 |
* CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this |
725b418b4
|
396 397 398 |
* register, and mask of mux bits are in higher 16-bit of this register. * While setting the mux bits, higher 16-bit should also be updated to * indicate changing mux bits. |
15a02c1f6
|
399 400 |
* CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired * frequency. |
9d9f78ed9
|
401 402 403 404 |
*/ struct clk_mux { struct clk_hw hw; void __iomem *reg; |
ce4f3313b
|
405 406 |
u32 *table; u32 mask; |
9d9f78ed9
|
407 |
u8 shift; |
9d9f78ed9
|
408 409 410 411 412 413 |
u8 flags; spinlock_t *lock; }; #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) |
ba492e900
|
414 |
#define CLK_MUX_HIWORD_MASK BIT(2) |
15a02c1f6
|
415 416 |
#define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */ #define CLK_MUX_ROUND_CLOSEST BIT(4) |
9d9f78ed9
|
417 |
|
bffad66e3
|
418 |
extern const struct clk_ops clk_mux_ops; |
c57acd14a
|
419 |
extern const struct clk_ops clk_mux_ro_ops; |
ce4f3313b
|
420 |
|
9d9f78ed9
|
421 |
struct clk *clk_register_mux(struct device *dev, const char *name, |
d305fb78f
|
422 |
const char **parent_names, u8 num_parents, unsigned long flags, |
9d9f78ed9
|
423 424 |
void __iomem *reg, u8 shift, u8 width, u8 clk_mux_flags, spinlock_t *lock); |
b2476490e
|
425 |
|
ce4f3313b
|
426 427 428 429 |
struct clk *clk_register_mux_table(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
4e3c021fb
|
430 |
void clk_unregister_mux(struct clk *clk); |
79b16641e
|
431 |
void of_fixed_factor_clk_setup(struct device_node *node); |
b2476490e
|
432 |
/** |
f0948f59d
|
433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 |
* struct clk_fixed_factor - fixed multiplier and divider clock * * @hw: handle between common and hardware-specific interfaces * @mult: multiplier * @div: divider * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. * Implements .recalc_rate, .set_rate and .round_rate */ struct clk_fixed_factor { struct clk_hw hw; unsigned int mult; unsigned int div; }; extern struct clk_ops clk_fixed_factor_ops; struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); |
e2d0e90fa
|
454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 |
/** * struct clk_fractional_divider - adjustable fractional divider clock * * @hw: handle between common and hardware-specific interfaces * @reg: register containing the divider * @mshift: shift to the numerator bit field * @mwidth: width of the numerator bit field * @nshift: shift to the denominator bit field * @nwidth: width of the denominator bit field * @lock: register lock * * Clock with adjustable fractional divider affecting its output frequency. */ struct clk_fractional_divider { struct clk_hw hw; void __iomem *reg; u8 mshift; u32 mmask; u8 nshift; u32 nmask; u8 flags; spinlock_t *lock; }; extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, u8 clk_divider_flags, spinlock_t *lock); |
ece70094f
|
484 485 486 487 |
/*** * struct clk_composite - aggregate clock of mux, divider and gate clocks * * @hw: handle between common and hardware-specific interfaces |
d3a1c7be8
|
488 489 490 |
* @mux_hw: handle between composite and hardware-specific mux clock * @rate_hw: handle between composite and hardware-specific rate clock * @gate_hw: handle between composite and hardware-specific gate clock |
ece70094f
|
491 |
* @mux_ops: clock ops for mux |
d3a1c7be8
|
492 |
* @rate_ops: clock ops for rate |
ece70094f
|
493 494 495 496 497 498 499 |
* @gate_ops: clock ops for gate */ struct clk_composite { struct clk_hw hw; struct clk_ops ops; struct clk_hw *mux_hw; |
d3a1c7be8
|
500 |
struct clk_hw *rate_hw; |
ece70094f
|
501 502 503 |
struct clk_hw *gate_hw; const struct clk_ops *mux_ops; |
d3a1c7be8
|
504 |
const struct clk_ops *rate_ops; |
ece70094f
|
505 506 507 508 509 510 |
const struct clk_ops *gate_ops; }; struct clk *clk_register_composite(struct device *dev, const char *name, const char **parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
d3a1c7be8
|
511 |
struct clk_hw *rate_hw, const struct clk_ops *rate_ops, |
ece70094f
|
512 513 |
struct clk_hw *gate_hw, const struct clk_ops *gate_ops, unsigned long flags); |
c873d14d3
|
514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 |
/*** * struct clk_gpio_gate - gpio gated clock * * @hw: handle between common and hardware-specific interfaces * @gpiod: gpio descriptor * * Clock with a gpio control for enabling and disabling the parent clock. * Implements .enable, .disable and .is_enabled */ struct clk_gpio { struct clk_hw hw; struct gpio_desc *gpiod; }; extern const struct clk_ops clk_gpio_gate_ops; struct clk *clk_register_gpio_gate(struct device *dev, const char *name, |
820ad9752
|
531 |
const char *parent_name, unsigned gpio, bool active_low, |
c873d14d3
|
532 533 534 |
unsigned long flags); void of_gpio_clk_gate_setup(struct device_node *node); |
f0948f59d
|
535 |
/** |
b2476490e
|
536 537 |
* clk_register - allocate a new clock, register it and return an opaque cookie * @dev: device that is registering this clock |
b2476490e
|
538 |
* @hw: link to hardware-specific clock data |
b2476490e
|
539 540 541 542 |
* * clk_register is the primary interface for populating the clock tree with new * clock nodes. It returns a pointer to the newly allocated struct clk which * cannot be dereferenced by driver code but may be used in conjuction with the |
d1302a36a
|
543 544 |
* rest of the clock API. In the event of an error clk_register will return an * error code; drivers must test for an error code after calling clk_register. |
b2476490e
|
545 |
*/ |
0197b3ea0
|
546 |
struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
46c8773a5
|
547 |
struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
b2476490e
|
548 |
|
1df5c939f
|
549 |
void clk_unregister(struct clk *clk); |
46c8773a5
|
550 |
void devm_clk_unregister(struct device *dev, struct clk *clk); |
1df5c939f
|
551 |
|
b2476490e
|
552 553 554 555 556 |
/* helper functions */ const char *__clk_get_name(struct clk *clk); struct clk_hw *__clk_get_hw(struct clk *clk); u8 __clk_get_num_parents(struct clk *clk); struct clk *__clk_get_parent(struct clk *clk); |
7ef3dcc81
|
557 |
struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); |
93874681a
|
558 |
unsigned int __clk_get_enable_count(struct clk *clk); |
b2476490e
|
559 560 |
unsigned long __clk_get_rate(struct clk *clk); unsigned long __clk_get_flags(struct clk *clk); |
3d6ee287a
|
561 |
bool __clk_is_prepared(struct clk *clk); |
2ac6b1f50
|
562 |
bool __clk_is_enabled(struct clk *clk); |
b2476490e
|
563 |
struct clk *__clk_lookup(const char *name); |
e366fdd72
|
564 |
long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, |
1c8e60044
|
565 566 |
unsigned long min_rate, unsigned long max_rate, |
e366fdd72
|
567 |
unsigned long *best_parent_rate, |
646cafc6a
|
568 |
struct clk_hw **best_parent_p); |
1c8e60044
|
569 570 571 572 |
unsigned long __clk_determine_rate(struct clk_hw *core, unsigned long rate, unsigned long min_rate, unsigned long max_rate); |
15a02c1f6
|
573 |
long __clk_mux_determine_rate_closest(struct clk_hw *hw, unsigned long rate, |
1c8e60044
|
574 575 |
unsigned long min_rate, unsigned long max_rate, |
15a02c1f6
|
576 577 |
unsigned long *best_parent_rate, struct clk_hw **best_parent_p); |
b2476490e
|
578 |
|
2e65d8bfe
|
579 580 581 582 583 |
static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { dst->clk = src->clk; dst->core = src->core; } |
b2476490e
|
584 585 586 |
/* * FIXME clock api without lock protection */ |
b2476490e
|
587 |
unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); |
766e6a4ec
|
588 589 590 |
struct of_device_id; typedef void (*of_clk_init_cb_t)(struct device_node *); |
0b151debc
|
591 592 593 594 |
struct clk_onecell_data { struct clk **clks; unsigned int clk_num; }; |
819b4861c
|
595 |
extern struct of_device_id __clk_of_table; |
54196ccbe
|
596 |
#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) |
0b151debc
|
597 598 |
#ifdef CONFIG_OF |
766e6a4ec
|
599 600 601 602 603 604 605 |
int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data); void of_clk_del_provider(struct device_node *np); struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data); |
494bfec99
|
606 |
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
f61027426
|
607 |
int of_clk_get_parent_count(struct device_node *np); |
766e6a4ec
|
608 |
const char *of_clk_get_parent_name(struct device_node *np, int index); |
f2f6c2556
|
609 |
|
766e6a4ec
|
610 |
void of_clk_init(const struct of_device_id *matches); |
0b151debc
|
611 |
#else /* !CONFIG_OF */ |
f2f6c2556
|
612 |
|
0b151debc
|
613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 |
static inline int of_clk_add_provider(struct device_node *np, struct clk *(*clk_src_get)(struct of_phandle_args *args, void *data), void *data) { return 0; } #define of_clk_del_provider(np) \ { while (0); } static inline struct clk *of_clk_src_simple_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline struct clk *of_clk_src_onecell_get( struct of_phandle_args *clkspec, void *data) { return ERR_PTR(-ENOENT); } static inline const char *of_clk_get_parent_name(struct device_node *np, int index) { return NULL; } #define of_clk_init(matches) \ { while (0); } #endif /* CONFIG_OF */ |
aa514ce34
|
640 641 642 643 644 |
/* * wrap access to peripherals in accessor routines * for improved portability across platforms */ |
6d8cdb682
|
645 646 647 648 649 650 651 652 653 654 655 656 657 |
#if IS_ENABLED(CONFIG_PPC) static inline u32 clk_readl(u32 __iomem *reg) { return ioread32be(reg); } static inline void clk_writel(u32 val, u32 __iomem *reg) { iowrite32be(val, reg); } #else /* platform dependent I/O accessors */ |
aa514ce34
|
658 659 660 661 662 663 664 665 666 |
static inline u32 clk_readl(u32 __iomem *reg) { return readl(reg); } static inline void clk_writel(u32 val, u32 __iomem *reg) { writel(val, reg); } |
6d8cdb682
|
667 |
#endif /* platform dependent I/O accessors */ |
fb2b3c9f6
|
668 |
#ifdef CONFIG_DEBUG_FS |
61c7cddfa
|
669 |
struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode, |
fb2b3c9f6
|
670 671 |
void *data, const struct file_operations *fops); #endif |
b2476490e
|
672 673 |
#endif /* CONFIG_COMMON_CLK */ #endif /* CLK_PROVIDER_H */ |