/*

   * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation

   * Copyright (c) 2006, 2007  Maciej W. Rozycki

   *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License
   * as published by the Free Software Foundation; either version 2
   * of the License, or (at your option) any later version.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.

   *

   * You should have received a copy of the GNU General Public License
   * along with this program; if not, write to the Free Software
   * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   *
   *
   * This driver is designed for the Broadcom SiByte SOC built-in
   * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.

   *
   * Updated to the driver model and the PHY abstraction layer
   * by Maciej W. Rozycki.

   */

  
  #include <linux/bug.h>

  #include <linux/module.h>
  #include <linux/kernel.h>
  #include <linux/string.h>
  #include <linux/timer.h>
  #include <linux/errno.h>
  #include <linux/ioport.h>
  #include <linux/slab.h>
  #include <linux/interrupt.h>
  #include <linux/netdevice.h>
  #include <linux/etherdevice.h>
  #include <linux/skbuff.h>
  #include <linux/init.h>

  #include <linux/bitops.h>

  #include <linux/err.h>
  #include <linux/ethtool.h>
  #include <linux/mii.h>
  #include <linux/phy.h>
  #include <linux/platform_device.h>

  #include <asm/cache.h>

  #include <asm/io.h>
  #include <asm/processor.h>	/* Processor type for cache alignment. */

  /* Operational parameters that usually are not changed. */
  
  #define CONFIG_SBMAC_COALESCE

  /* Time in jiffies before concluding the transmitter is hung. */
  #define TX_TIMEOUT  (2*HZ)
  
  
  MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  
  /* A few user-configurable values which may be modified when a driver
     module is loaded. */
  
  /* 1 normal messages, 0 quiet .. 7 verbose. */
  static int debug = 1;
  module_param(debug, int, S_IRUGO);
  MODULE_PARM_DESC(debug, "Debug messages");

  #ifdef CONFIG_SBMAC_COALESCE

  static int int_pktcnt_tx = 255;
  module_param(int_pktcnt_tx, int, S_IRUGO);
  MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count");

  static int int_timeout_tx = 255;
  module_param(int_timeout_tx, int, S_IRUGO);
  MODULE_PARM_DESC(int_timeout_tx, "TX timeout value");
  
  static int int_pktcnt_rx = 64;
  module_param(int_pktcnt_rx, int, S_IRUGO);
  MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count");
  
  static int int_timeout_rx = 64;
  module_param(int_timeout_rx, int, S_IRUGO);
  MODULE_PARM_DESC(int_timeout_rx, "RX timeout value");

  #endif

  #include <asm/sibyte/board.h>

  #include <asm/sibyte/sb1250.h>

  #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  #include <asm/sibyte/bcm1480_regs.h>
  #include <asm/sibyte/bcm1480_int.h>

  #define R_MAC_DMA_OODPKTLOST_RX	R_MAC_DMA_OODPKTLOST

  #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)

  #include <asm/sibyte/sb1250_regs.h>

  #include <asm/sibyte/sb1250_int.h>

  #else
  #error invalid SiByte MAC configuation
  #endif

  #include <asm/sibyte/sb1250_scd.h>

  #include <asm/sibyte/sb1250_mac.h>
  #include <asm/sibyte/sb1250_dma.h>

  #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  #define UNIT_INT(n)		(K_BCM1480_INT_MAC_0 + ((n) * 2))
  #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  #define UNIT_INT(n)		(K_INT_MAC_0 + (n))
  #else
  #error invalid SiByte MAC configuation
  #endif

  #ifdef K_INT_PHY
  #define SBMAC_PHY_INT			K_INT_PHY
  #else
  #define SBMAC_PHY_INT			PHY_POLL
  #endif

  /**********************************************************************
   *  Simple types
   ********************************************************************* */

  enum sbmac_speed {
  	sbmac_speed_none = 0,
  	sbmac_speed_10 = SPEED_10,
  	sbmac_speed_100 = SPEED_100,
  	sbmac_speed_1000 = SPEED_1000,
  };

  enum sbmac_duplex {
  	sbmac_duplex_none = -1,
  	sbmac_duplex_half = DUPLEX_HALF,
  	sbmac_duplex_full = DUPLEX_FULL,
  };

  enum sbmac_fc {
  	sbmac_fc_none,
  	sbmac_fc_disabled,
  	sbmac_fc_frame,
  	sbmac_fc_collision,
  	sbmac_fc_carrier,
  };

  enum sbmac_state {
  	sbmac_state_uninit,
  	sbmac_state_off,
  	sbmac_state_on,
  	sbmac_state_broken,
  };

  
  
  /**********************************************************************
   *  Macros
   ********************************************************************* */
  
  
  #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
  			  (d)->sbdma_dscrtable : (d)->f+1)
  
  
  #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)

  #define SBMAC_MAX_TXDESCR	256
  #define SBMAC_MAX_RXDESCR	256

  #define ETHER_ADDR_LEN		6

  #define ENET_PACKET_SIZE	1518
  /*#define ENET_PACKET_SIZE	9216 */

  
  /**********************************************************************
   *  DMA Descriptor structure
   ********************************************************************* */

  struct sbdmadscr {

  	uint64_t  dscr_a;
  	uint64_t  dscr_b;

  };

  
  /**********************************************************************
   *  DMA Controller structure
   ********************************************************************* */

  struct sbmacdma {

  
  	/*

  	 * This stuff is used to identify the channel and the registers
  	 * associated with it.
  	 */

  	struct sbmac_softc	*sbdma_eth;	/* back pointer to associated
  						   MAC */
  	int			sbdma_channel;	/* channel number */
  	int			sbdma_txdir;	/* direction (1=transmit) */
  	int			sbdma_maxdescr;	/* total # of descriptors
  						   in ring */

  #ifdef CONFIG_SBMAC_COALESCE

  	int			sbdma_int_pktcnt;
  						/* # descriptors rx/tx
  						   before interrupt */
  	int			sbdma_int_timeout;
  						/* # usec rx/tx interrupt */

  #endif

  	void __iomem		*sbdma_config0;	/* DMA config register 0 */
  	void __iomem		*sbdma_config1;	/* DMA config register 1 */
  	void __iomem		*sbdma_dscrbase;
  						/* descriptor base address */
  	void __iomem		*sbdma_dscrcnt;	/* descriptor count register */
  	void __iomem		*sbdma_curdscr;	/* current descriptor
  						   address */
  	void __iomem		*sbdma_oodpktlost;
  						/* pkt drop (rx only) */

  	/*
  	 * This stuff is for maintenance of the ring
  	 */

  	void			*sbdma_dscrtable_unaligned;
  	struct sbdmadscr	*sbdma_dscrtable;
  						/* base of descriptor table */
  	struct sbdmadscr	*sbdma_dscrtable_end;
  						/* end of descriptor table */
  	struct sk_buff		**sbdma_ctxtable;
  						/* context table, one
  						   per descr */
  	dma_addr_t		sbdma_dscrtable_phys;
  						/* and also the phys addr */
  	struct sbdmadscr	*sbdma_addptr;	/* next dscr for sw to add */
  	struct sbdmadscr	*sbdma_remptr;	/* next dscr for sw
  						   to remove */
  };

  
  
  /**********************************************************************
   *  Ethernet softc structure
   ********************************************************************* */
  
  struct sbmac_softc {

  	/*
  	 * Linux-specific things
  	 */

  	struct net_device	*sbm_dev;	/* pointer to linux device */
  	struct napi_struct	napi;

  	struct phy_device	*phy_dev;	/* the associated PHY device */

  	struct mii_bus		*mii_bus;	/* the MII bus */

  	int			phy_irq[PHY_MAX_ADDR];

  	spinlock_t		sbm_lock;	/* spin lock */

  	int			sbm_devflags;	/* current device flags */

  	/*
  	 * Controller-specific things
  	 */

  	void __iomem		*sbm_base;	/* MAC's base address */
  	enum sbmac_state	sbm_state;	/* current state */

  	void __iomem		*sbm_macenable;	/* MAC Enable Register */
  	void __iomem		*sbm_maccfg;	/* MAC Config Register */
  	void __iomem		*sbm_fifocfg;	/* FIFO Config Register */
  	void __iomem		*sbm_framecfg;	/* Frame Config Register */
  	void __iomem		*sbm_rxfilter;	/* Receive Filter Register */
  	void __iomem		*sbm_isr;	/* Interrupt Status Register */
  	void __iomem		*sbm_imr;	/* Interrupt Mask Register */
  	void __iomem		*sbm_mdio;	/* MDIO Register */

  	enum sbmac_speed	sbm_speed;	/* current speed */
  	enum sbmac_duplex	sbm_duplex;	/* current duplex */
  	enum sbmac_fc		sbm_fc;		/* cur. flow control setting */

  	int			sbm_pause;	/* current pause setting */
  	int			sbm_link;	/* current link state */

  	unsigned char		sbm_hwaddr[ETHER_ADDR_LEN];

  	struct sbmacdma		sbm_txdma;	/* only channel 0 for now */
  	struct sbmacdma		sbm_rxdma;
  	int			rx_hw_checksum;
  	int			sbe_idx;

  };
  
  
  /**********************************************************************
   *  Externs
   ********************************************************************* */
  
  /**********************************************************************
   *  Prototypes
   ********************************************************************* */

  static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
  			  int txrx, int maxdescr);
  static void sbdma_channel_start(struct sbmacdma *d, int rxtx);

  static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
  			       struct sk_buff *m);

  static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m);
  static void sbdma_emptyring(struct sbmacdma *d);

  static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d);

  static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
  			    int work_to_do, int poll);
  static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
  			     int poll);

  static int sbmac_initctx(struct sbmac_softc *s);
  static void sbmac_channel_start(struct sbmac_softc *s);
  static void sbmac_channel_stop(struct sbmac_softc *s);

  static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *,
  						enum sbmac_state);
  static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff);

  static uint64_t sbmac_addr2reg(unsigned char *ptr);

  static irqreturn_t sbmac_intr(int irq, void *dev_instance);

  static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
  static void sbmac_setmulti(struct sbmac_softc *sc);

  static int sbmac_init(struct platform_device *pldev, long long base);

  static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed);
  static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex,
  			    enum sbmac_fc fc);

  
  static int sbmac_open(struct net_device *dev);

  static void sbmac_tx_timeout (struct net_device *dev);

  static void sbmac_set_rx_mode(struct net_device *dev);
  static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
  static int sbmac_close(struct net_device *dev);

  static int sbmac_poll(struct napi_struct *napi, int budget);

  static void sbmac_mii_poll(struct net_device *dev);

  static int sbmac_mii_probe(struct net_device *dev);

  static void sbmac_mii_sync(void __iomem *sbm_mdio);
  static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,

  			       int bitcnt);

  static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx);
  static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  			   u16 val);

  
  
  /**********************************************************************
   *  Globals
   ********************************************************************* */

  static char sbmac_string[] = "sb1250-mac";

  
  static char sbmac_mdio_string[] = "sb1250-mac-mdio";

  
  
  /**********************************************************************
   *  MDIO constants
   ********************************************************************* */
  
  #define	MII_COMMAND_START	0x01
  #define	MII_COMMAND_READ	0x02
  #define	MII_COMMAND_WRITE	0x01
  #define	MII_COMMAND_ACK		0x02

  #define M_MAC_MDIO_DIR_OUTPUT	0		/* for clarity */
  
  #define ENABLE 		1
  #define DISABLE		0
  
  /**********************************************************************

   *  SBMAC_MII_SYNC(sbm_mdio)

   *

   *  Synchronize with the MII - send a pattern of bits to the MII
   *  that will guarantee that it is ready to accept a command.

   *
   *  Input parameters:

   *  	   sbm_mdio - address of the MAC's MDIO register

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbmac_mii_sync(void __iomem *sbm_mdio)

  {
  	int cnt;
  	uint64_t bits;
  	int mac_mdio_genc;

  	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;

  	bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;

  	__raw_writeq(bits | mac_mdio_genc, sbm_mdio);

  	for (cnt = 0; cnt < 32; cnt++) {

  		__raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
  		__raw_writeq(bits | mac_mdio_genc, sbm_mdio);

  	}
  }
  
  /**********************************************************************

   *  SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt)

   *

   *  Send some bits to the MII.  The bits to be sent are right-
   *  justified in the 'data' parameter.

   *
   *  Input parameters:

   *  	   sbm_mdio - address of the MAC's MDIO register
   *  	   data     - data to send
   *  	   bitcnt   - number of bits to send

   ********************************************************************* */

  static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data,
  			       int bitcnt)

  {
  	int i;
  	uint64_t bits;
  	unsigned int curmask;
  	int mac_mdio_genc;

  	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;

  	bits = M_MAC_MDIO_DIR_OUTPUT;

  	__raw_writeq(bits | mac_mdio_genc, sbm_mdio);

  	curmask = 1 << (bitcnt - 1);

  	for (i = 0; i < bitcnt; i++) {
  		if (data & curmask)
  			bits |= M_MAC_MDIO_OUT;
  		else bits &= ~M_MAC_MDIO_OUT;

  		__raw_writeq(bits | mac_mdio_genc, sbm_mdio);
  		__raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio);
  		__raw_writeq(bits | mac_mdio_genc, sbm_mdio);

  		curmask >>= 1;
  	}
  }
  
  
  
  /**********************************************************************

   *  SBMAC_MII_READ(bus, phyaddr, regidx)

   *  Read a PHY register.

   *
   *  Input parameters:

   *  	   bus     - MDIO bus handle

   *  	   phyaddr - PHY's address

   *  	   regnum  - index of register to read

   *

   *  Return value:

   *  	   value read, or 0xffff if an error occurred.

   ********************************************************************* */

  static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx)

  {

  	struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
  	void __iomem *sbm_mdio = sc->sbm_mdio;

  	int idx;
  	int error;
  	int regval;
  	int mac_mdio_genc;
  
  	/*
  	 * Synchronize ourselves so that the PHY knows the next
  	 * thing coming down is a command
  	 */

  	sbmac_mii_sync(sbm_mdio);

  	/*
  	 * Send the data to the PHY.  The sequence is
  	 * a "start" command (2 bits)
  	 * a "read" command (2 bits)
  	 * the PHY addr (5 bits)
  	 * the register index (5 bits)
  	 */

  	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
  	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2);
  	sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
  	sbmac_mii_senddata(sbm_mdio, regidx, 5);

  	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;

  
  	/*

  	 * Switch the port around without a clock transition.
  	 */

  	__raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);

  	/*
  	 * Send out a clock pulse to signal we want the status
  	 */

  	__raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
  		     sbm_mdio);
  	__raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);

  
  	/*

  	 * If an error occurred, the PHY will signal '1' back
  	 */

  	error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN;

  
  	/*

  	 * Issue an 'idle' clock pulse, but keep the direction
  	 * the same.
  	 */

  	__raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
  		     sbm_mdio);
  	__raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);

  	regval = 0;

  	for (idx = 0; idx < 16; idx++) {
  		regval <<= 1;

  		if (error == 0) {

  			if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN)

  				regval |= 1;
  		}

  		__raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc,
  			     sbm_mdio);
  		__raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio);

  	}

  	/* Switch back to output */

  	__raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);

  	if (error == 0)
  		return regval;

  	return 0xffff;

  }
  
  
  /**********************************************************************

   *  SBMAC_MII_WRITE(bus, phyaddr, regidx, regval)

   *

   *  Write a value to a PHY register.

   *
   *  Input parameters:

   *  	   bus     - MDIO bus handle

   *  	   phyaddr - PHY to use

   *  	   regidx  - register within the PHY
   *  	   regval  - data to write to register

   *

   *  Return value:

   *  	   0 for success

   ********************************************************************* */

  static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  			   u16 regval)

  {

  	struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv;
  	void __iomem *sbm_mdio = sc->sbm_mdio;

  	int mac_mdio_genc;

  	sbmac_mii_sync(sbm_mdio);

  	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2);
  	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2);
  	sbmac_mii_senddata(sbm_mdio, phyaddr, 5);
  	sbmac_mii_senddata(sbm_mdio, regidx, 5);
  	sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2);
  	sbmac_mii_senddata(sbm_mdio, regval, 16);

  	mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC;

  	__raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio);
  
  	return 0;

  }
  
  
  
  /**********************************************************************
   *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)

   *

   *  Initialize a DMA channel context.  Since there are potentially
   *  eight DMA channels per MAC, it's nice to do this in a standard

   *  way.
   *
   *  Input parameters:

   *  	   d - struct sbmacdma (DMA channel context)
   *  	   s - struct sbmac_softc (pointer to a MAC)

   *  	   chan - channel number (0..1 right now)
   *  	   txrx - Identifies DMA_TX or DMA_RX for channel direction
   *      maxdescr - number of descriptors

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan,
  			  int txrx, int maxdescr)

  {

  #ifdef CONFIG_SBMAC_COALESCE
  	int int_pktcnt, int_timeout;
  #endif

  	/*
  	 * Save away interesting stuff in the structure

  	 */

  	d->sbdma_eth       = s;
  	d->sbdma_channel   = chan;
  	d->sbdma_txdir     = txrx;

  #if 0
  	/* RMON clearing */
  	s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
  #endif

  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR);
  	__raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR);

  	/*
  	 * initialize register pointers

  	 */

  
  	d->sbdma_config0 =

  		s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);

  	d->sbdma_config1 =

  		s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);

  	d->sbdma_dscrbase =

  		s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);

  	d->sbdma_dscrcnt =

  		s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);

  	d->sbdma_curdscr =

  		s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);

  	if (d->sbdma_txdir)
  		d->sbdma_oodpktlost = NULL;
  	else
  		d->sbdma_oodpktlost =
  			s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX);

  	/*
  	 * Allocate memory for the ring
  	 */

  	d->sbdma_maxdescr = maxdescr;

  	d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1,
  					       sizeof(*d->sbdma_dscrtable),
  					       GFP_KERNEL);

  
  	/*
  	 * The descriptor table must be aligned to at least 16 bytes or the
  	 * MAC will corrupt it.
  	 */

  	d->sbdma_dscrtable = (struct sbdmadscr *)
  			     ALIGN((unsigned long)d->sbdma_dscrtable_unaligned,
  				   sizeof(*d->sbdma_dscrtable));

  	d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;

  	d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);

  	/*
  	 * And context table
  	 */

  	d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr,

  				    sizeof(*d->sbdma_ctxtable), GFP_KERNEL);

  #ifdef CONFIG_SBMAC_COALESCE
  	/*
  	 * Setup Rx/Tx DMA coalescing defaults
  	 */

  	int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx;

  	if ( int_pktcnt ) {
  		d->sbdma_int_pktcnt = int_pktcnt;
  	} else {
  		d->sbdma_int_pktcnt = 1;
  	}

  	int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx;

  	if ( int_timeout ) {
  		d->sbdma_int_timeout = int_timeout;
  	} else {
  		d->sbdma_int_timeout = 0;
  	}
  #endif
  
  }
  
  /**********************************************************************
   *  SBDMA_CHANNEL_START(d)

   *

   *  Initialize the hardware registers for a DMA channel.

   *
   *  Input parameters:

   *  	   d - DMA channel to init (context must be previously init'd
   *         rxtx - DMA_RX or DMA_TX depending on what type of channel

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbdma_channel_start(struct sbmacdma *d, int rxtx)

  {
  	/*
  	 * Turn on the DMA channel
  	 */

  #ifdef CONFIG_SBMAC_COALESCE

  	__raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
  		       0, d->sbdma_config1);
  	__raw_writeq(M_DMA_EOP_INT_EN |

  		       V_DMA_RINGSZ(d->sbdma_maxdescr) |
  		       V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |

  		       0, d->sbdma_config0);

  #else

  	__raw_writeq(0, d->sbdma_config1);
  	__raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
  		       0, d->sbdma_config0);

  #endif

  	__raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);

  
  	/*
  	 * Initialize ring pointers
  	 */
  
  	d->sbdma_addptr = d->sbdma_dscrtable;
  	d->sbdma_remptr = d->sbdma_dscrtable;
  }
  
  /**********************************************************************
   *  SBDMA_CHANNEL_STOP(d)

   *

   *  Initialize the hardware registers for a DMA channel.

   *
   *  Input parameters:

   *  	   d - DMA channel to init (context must be previously init'd

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbdma_channel_stop(struct sbmacdma *d)

  {
  	/*
  	 * Turn off the DMA channel
  	 */

  	__raw_writeq(0, d->sbdma_config1);

  	__raw_writeq(0, d->sbdma_dscrbase);

  	__raw_writeq(0, d->sbdma_config0);

  	/*
  	 * Zero ring pointers
  	 */

  	d->sbdma_addptr = NULL;
  	d->sbdma_remptr = NULL;

  }

  static inline void sbdma_align_skb(struct sk_buff *skb,
  				   unsigned int power2, unsigned int offset)

  {

  	unsigned char *addr = skb->data;
  	unsigned char *newaddr = PTR_ALIGN(addr, power2);

  	skb_reserve(skb, newaddr - addr + offset);

  }
  
  
  /**********************************************************************
   *  SBDMA_ADD_RCVBUFFER(d,sb)

   *

   *  Add a buffer to the specified DMA channel.   For receive channels,
   *  this queues a buffer for inbound packets.

   *
   *  Input parameters:

   *	   sc - softc structure
   *  	    d - DMA channel descriptor

   * 	   sb - sk_buff to add, or NULL if we should allocate one

   *

   *  Return value:
   *  	   0 if buffer could not be added (ring is full)
   *  	   1 if buffer added successfully
   ********************************************************************* */

  static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d,
  			       struct sk_buff *sb)

  {

  	struct net_device *dev = sc->sbm_dev;

  	struct sbdmadscr *dsc;
  	struct sbdmadscr *nextdsc;

  	struct sk_buff *sb_new = NULL;
  	int pktsize = ENET_PACKET_SIZE;

  	/* get pointer to our current place in the ring */

  	dsc = d->sbdma_addptr;
  	nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);

  	/*
  	 * figure out if the ring is full - if the next descriptor
  	 * is the same as the one that we're going to remove from
  	 * the ring, the ring is full
  	 */

  	if (nextdsc == d->sbdma_remptr) {
  		return -ENOSPC;
  	}

  	/*
  	 * Allocate a sk_buff if we don't already have one.

  	 * If we do have an sk_buff, reset it so that it's empty.
  	 *
  	 * Note: sk_buffs don't seem to be guaranteed to have any sort
  	 * of alignment when they are allocated.  Therefore, allocate enough
  	 * extra space to make sure that:
  	 *
  	 *    1. the data does not start in the middle of a cache line.
  	 *    2. The data does not end in the middle of a cache line

  	 *    3. The buffer can be aligned such that the IP addresses are

  	 *       naturally aligned.
  	 *
  	 *  Remember, the SOCs MAC writes whole cache lines at a time,
  	 *  without reading the old contents first.  So, if the sk_buff's
  	 *  data portion starts in the middle of a cache line, the SOC
  	 *  DMA will trash the beginning (and ending) portions.
  	 */

  	if (sb == NULL) {

  		sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE +
  					       SMP_CACHE_BYTES * 2 +
  					       NET_IP_ALIGN);

  		if (sb_new == NULL) {

  			pr_info("%s: sk_buff allocation failed
  ",

  			       d->sbdma_eth->sbm_dev->name);
  			return -ENOBUFS;
  		}

  		sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN);

  	}
  	else {
  		sb_new = sb;

  		/*

  		 * nothing special to reinit buffer, it's already aligned
  		 * and sb->data already points to a good place.
  		 */
  	}

  	/*

  	 * fill in the descriptor

  	 */

  #ifdef CONFIG_SBMAC_COALESCE
  	/*
  	 * Do not interrupt per DMA transfer.
  	 */

  	dsc->dscr_a = virt_to_phys(sb_new->data) |

  		V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0;

  #else

  	dsc->dscr_a = virt_to_phys(sb_new->data) |

  		V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) |

  		M_DMA_DSCRA_INTERRUPT;
  #endif
  
  	/* receiving: no options */
  	dsc->dscr_b = 0;

  	/*

  	 * fill in the context

  	 */

  	d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;

  
  	/*
  	 * point at next packet

  	 */

  	d->sbdma_addptr = nextdsc;

  
  	/*

  	 * Give the buffer to the DMA engine.
  	 */

  	__raw_writeq(1, d->sbdma_dscrcnt);

  	return 0;					/* we did it */
  }
  
  /**********************************************************************
   *  SBDMA_ADD_TXBUFFER(d,sb)

   *

   *  Add a transmit buffer to the specified DMA channel, causing a
   *  transmit to start.

   *
   *  Input parameters:

   *  	   d - DMA channel descriptor
   * 	   sb - sk_buff to add

   *

   *  Return value:
   *  	   0 transmit queued successfully
   *  	   otherwise error code
   ********************************************************************* */

  static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb)

  {

  	struct sbdmadscr *dsc;
  	struct sbdmadscr *nextdsc;

  	uint64_t phys;
  	uint64_t ncb;
  	int length;

  	/* get pointer to our current place in the ring */

  	dsc = d->sbdma_addptr;
  	nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);

  	/*
  	 * figure out if the ring is full - if the next descriptor
  	 * is the same as the one that we're going to remove from
  	 * the ring, the ring is full
  	 */

  	if (nextdsc == d->sbdma_remptr) {
  		return -ENOSPC;
  	}

  	/*
  	 * Under Linux, it's not necessary to copy/coalesce buffers
  	 * like it is on NetBSD.  We think they're all contiguous,
  	 * but that may not be true for GBE.
  	 */

  	length = sb->len;

  	/*
  	 * fill in the descriptor.  Note that the number of cache
  	 * blocks in the descriptor is the number of blocks
  	 * *spanned*, so we need to add in the offset (if any)
  	 * while doing the calculation.
  	 */

  	phys = virt_to_phys(sb->data);
  	ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));

  	dsc->dscr_a = phys |

  		V_DMA_DSCRA_A_SIZE(ncb) |
  #ifndef CONFIG_SBMAC_COALESCE
  		M_DMA_DSCRA_INTERRUPT |
  #endif
  		M_DMA_ETHTX_SOP;

  	/* transmitting: set outbound options and length */
  
  	dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
  		V_DMA_DSCRB_PKT_SIZE(length);

  	/*

  	 * fill in the context

  	 */

  	d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;

  
  	/*
  	 * point at next packet

  	 */

  	d->sbdma_addptr = nextdsc;

  
  	/*

  	 * Give the buffer to the DMA engine.
  	 */

  	__raw_writeq(1, d->sbdma_dscrcnt);

  	return 0;					/* we did it */
  }
  
  
  
  
  /**********************************************************************
   *  SBDMA_EMPTYRING(d)

   *

   *  Free all allocated sk_buffs on the specified DMA channel;

   *
   *  Input parameters:

   *  	   d  - DMA channel

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbdma_emptyring(struct sbmacdma *d)

  {
  	int idx;
  	struct sk_buff *sb;

  	for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
  		sb = d->sbdma_ctxtable[idx];
  		if (sb) {
  			dev_kfree_skb(sb);
  			d->sbdma_ctxtable[idx] = NULL;
  		}
  	}
  }
  
  
  /**********************************************************************
   *  SBDMA_FILLRING(d)

   *

   *  Fill the specified DMA channel (must be receive channel)
   *  with sk_buffs

   *
   *  Input parameters:

   *	   sc - softc structure
   *  	    d - DMA channel

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d)

  {
  	int idx;

  	for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) {
  		if (sbdma_add_rcvbuffer(sc, d, NULL) != 0)

  			break;
  	}
  }

  #ifdef CONFIG_NET_POLL_CONTROLLER
  static void sbmac_netpoll(struct net_device *netdev)
  {
  	struct sbmac_softc *sc = netdev_priv(netdev);
  	int irq = sc->sbm_dev->irq;
  
  	__raw_writeq(0, sc->sbm_imr);

  	sbmac_intr(irq, netdev);

  
  #ifdef CONFIG_SBMAC_COALESCE
  	__raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
  	((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
  	sc->sbm_imr);
  #else

  	__raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |

  	(M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
  #endif
  }
  #endif

  
  /**********************************************************************

   *  SBDMA_RX_PROCESS(sc,d,work_to_do,poll)

   *
   *  Process "completed" receive buffers on the specified DMA channel.

   *

   *  Input parameters:

   *            sc - softc structure
   *  	       d - DMA channel context
   *    work_to_do - no. of packets to process before enabling interrupt
   *                 again (for NAPI)
   *          poll - 1: using polling (for NAPI)

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d,
  			    int work_to_do, int poll)

  {

  	struct net_device *dev = sc->sbm_dev;

  	int curidx;
  	int hwidx;

  	struct sbdmadscr *dsc;

  	struct sk_buff *sb;
  	int len;

  	int work_done = 0;
  	int dropped = 0;

  	prefetch(d);
  
  again:
  	/* Check if the HW dropped any frames */

  	dev->stats.rx_fifo_errors

  	    += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff;
  	__raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost);
  
  	while (work_to_do-- > 0) {

  		/*

  		 * figure out where we are (as an index) and where
  		 * the hardware is (also as an index)
  		 *

  		 * This could be done faster if (for example) the

  		 * descriptor table was page-aligned and contiguous in
  		 * both virtual and physical memory -- you could then
  		 * just compare the low-order bits of the virtual address
  		 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
  		 */

  		dsc = d->sbdma_remptr;
  		curidx = dsc - d->sbdma_dscrtable;
  
  		prefetch(dsc);
  		prefetch(&d->sbdma_ctxtable[curidx]);

  		hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
  			 d->sbdma_dscrtable_phys) /
  			sizeof(*d->sbdma_dscrtable);

  		/*
  		 * If they're the same, that means we've processed all
  		 * of the descriptors up to (but not including) the one that
  		 * the hardware is working on right now.
  		 */

  		if (curidx == hwidx)

  			goto done;

  		/*
  		 * Otherwise, get the packet's sk_buff ptr back
  		 */

  		sb = d->sbdma_ctxtable[curidx];
  		d->sbdma_ctxtable[curidx] = NULL;

  		len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;

  		/*
  		 * Check packet status.  If good, process it.
  		 * If not, silently drop it and put it back on the
  		 * receive ring.
  		 */

  		if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) {

  			/*
  			 * Add a new buffer to replace the old one.  If we fail
  			 * to allocate a buffer, we're going to drop this
  			 * packet and put it right back on the receive ring.
  			 */

  			if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) ==
  				     -ENOBUFS)) {

  				dev->stats.rx_dropped++;

  				/* Re-add old buffer */
  				sbdma_add_rcvbuffer(sc, d, sb);

  				/* No point in continuing at the moment */
  				printk(KERN_ERR "dropped packet (1)
  ");
  				d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
  				goto done;

  			} else {
  				/*
  				 * Set length into the packet
  				 */
  				skb_put(sb,len);

  				/*
  				 * Buffer has been replaced on the
  				 * receive ring.  Pass the buffer to
  				 * the kernel
  				 */

  				sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
  				/* Check hw IPv4/TCP checksum if supported */
  				if (sc->rx_hw_checksum == ENABLE) {
  					if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
  					    !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
  						sb->ip_summed = CHECKSUM_UNNECESSARY;
  						/* don't need to set sb->csum */
  					} else {
  						sb->ip_summed = CHECKSUM_NONE;
  					}
  				}

  				prefetch(sb->data);
  				prefetch((const void *)(((char *)sb->data)+32));
  				if (poll)
  					dropped = netif_receive_skb(sb);
  				else
  					dropped = netif_rx(sb);
  
  				if (dropped == NET_RX_DROP) {

  					dev->stats.rx_dropped++;

  					d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
  					goto done;
  				}
  				else {

  					dev->stats.rx_bytes += len;
  					dev->stats.rx_packets++;

  				}

  			}
  		} else {
  			/*
  			 * Packet was mangled somehow.  Just drop it and
  			 * put it back on the receive ring.
  			 */

  			dev->stats.rx_errors++;

  			sbdma_add_rcvbuffer(sc, d, sb);

  		}

  
  
  		/*

  		 * .. and advance to the next buffer.
  		 */

  		d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);

  		work_done++;
  	}
  	if (!poll) {
  		work_to_do = 32;
  		goto again; /* collect fifo drop statistics again */

  	}

  done:
  	return work_done;

  }

  /**********************************************************************
   *  SBDMA_TX_PROCESS(sc,d)

   *
   *  Process "completed" transmit buffers on the specified DMA channel.

   *  This is normally called within the interrupt service routine.
   *  Note that this isn't really ideal for priority channels, since

   *  it processes all of the packets on a given channel before
   *  returning.

   *

   *  Input parameters:

   *      sc - softc structure

   *  	 d - DMA channel context
   *    poll - 1: using polling (for NAPI)

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */

  static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d,
  			     int poll)

  {

  	struct net_device *dev = sc->sbm_dev;

  	int curidx;
  	int hwidx;

  	struct sbdmadscr *dsc;

  	struct sk_buff *sb;
  	unsigned long flags;

  	int packets_handled = 0;

  
  	spin_lock_irqsave(&(sc->sbm_lock), flags);

  	if (d->sbdma_remptr == d->sbdma_addptr)
  	  goto end_unlock;

  	hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
  		 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable);

  	for (;;) {

  		/*

  		 * figure out where we are (as an index) and where
  		 * the hardware is (also as an index)
  		 *

  		 * This could be done faster if (for example) the

  		 * descriptor table was page-aligned and contiguous in
  		 * both virtual and physical memory -- you could then
  		 * just compare the low-order bits of the virtual address
  		 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
  		 */

  		curidx = d->sbdma_remptr - d->sbdma_dscrtable;

  
  		/*
  		 * If they're the same, that means we've processed all
  		 * of the descriptors up to (but not including) the one that
  		 * the hardware is working on right now.
  		 */

  		if (curidx == hwidx)
  			break;

  		/*
  		 * Otherwise, get the packet's sk_buff ptr back
  		 */

  		dsc = &(d->sbdma_dscrtable[curidx]);
  		sb = d->sbdma_ctxtable[curidx];
  		d->sbdma_ctxtable[curidx] = NULL;

  		/*
  		 * Stats
  		 */

  		dev->stats.tx_bytes += sb->len;
  		dev->stats.tx_packets++;

  		/*
  		 * for transmits, we just free buffers.
  		 */

  		dev_kfree_skb_irq(sb);

  
  		/*

  		 * .. and advance to the next buffer.
  		 */
  
  		d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);

  		packets_handled++;

  	}

  	/*
  	 * Decide if we should wake up the protocol or not.
  	 * Other drivers seem to do this when we reach a low
  	 * watermark on the transmit queue.
  	 */

  	if (packets_handled)
  		netif_wake_queue(d->sbdma_eth->sbm_dev);

  end_unlock:

  	spin_unlock_irqrestore(&(sc->sbm_lock), flags);

  }
  
  
  
  /**********************************************************************
   *  SBMAC_INITCTX(s)

   *

   *  Initialize an Ethernet context structure - this is called
   *  once per MAC on the 1250.  Memory is allocated here, so don't
   *  call it again from inside the ioctl routines that bring the
   *  interface up/down

   *
   *  Input parameters:

   *  	   s - sbmac context structure

   *

   *  Return value:
   *  	   0
   ********************************************************************* */
  
  static int sbmac_initctx(struct sbmac_softc *s)
  {

  
  	/*
  	 * figure out the addresses of some ports

  	 */

  	s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
  	s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
  	s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
  	s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
  	s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
  	s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
  	s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
  	s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;

  	/*
  	 * Initialize the DMA channels.  Right now, only one per MAC is used
  	 * Note: Only do this _once_, as it allocates memory from the kernel!
  	 */

  	sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
  	sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);

  	/*
  	 * initial state is OFF
  	 */

  	s->sbm_state = sbmac_state_off;

  	return 0;
  }

  static void sbdma_uninitctx(struct sbmacdma *d)

  {

  	if (d->sbdma_dscrtable_unaligned) {
  		kfree(d->sbdma_dscrtable_unaligned);
  		d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL;

  	}

  	if (d->sbdma_ctxtable) {
  		kfree(d->sbdma_ctxtable);
  		d->sbdma_ctxtable = NULL;
  	}
  }
  
  
  static void sbmac_uninitctx(struct sbmac_softc *sc)
  {
  	sbdma_uninitctx(&(sc->sbm_txdma));
  	sbdma_uninitctx(&(sc->sbm_rxdma));
  }
  
  
  /**********************************************************************
   *  SBMAC_CHANNEL_START(s)

   *

   *  Start packet processing on this MAC.

   *
   *  Input parameters:

   *  	   s - sbmac structure

   *

   *  Return value:
   *  	   nothing
   ********************************************************************* */
  
  static void sbmac_channel_start(struct sbmac_softc *s)
  {
  	uint64_t reg;

  	void __iomem *port;

  	uint64_t cfg,fifo,framecfg;
  	int idx, th_value;

  	/*
  	 * Don't do this if running
  	 */
  
  	if (s->sbm_state == sbmac_state_on)
  		return;

  	/*
  	 * Bring the controller out of reset, but leave it off.
  	 */

  	__raw_writeq(0, s->sbm_macenable);

  	/*
  	 * Ignore all received packets
  	 */

  	__raw_writeq(0, s->sbm_rxfilter);

  
  	/*

  	 * Calculate values for various control registers.
  	 */

  	cfg = M_MAC_RETRY_EN |

  		M_MAC_TX_HOLD_SOP_EN |

  		V_MAC_TX_PAUSE_CNT_16K |
  		M_MAC_AP_STAT_EN |
  		M_MAC_FAST_SYNC |
  		M_MAC_SS_EN |
  		0;

  
  	/*

  	 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
  	 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
  	 * Use a larger RD_THRSH for gigabit
  	 */

  	if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)

  		th_value = 28;

  	else
  		th_value = 64;

  
  	fifo = V_MAC_TX_WR_THRSH(4) |	/* Must be '4' or '8' */
  		((s->sbm_speed == sbmac_speed_1000)
  		 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
  		V_MAC_TX_RL_THRSH(4) |
  		V_MAC_RX_PL_THRSH(4) |
  		V_MAC_RX_RD_THRSH(4) |	/* Must be '4' */

  		V_MAC_RX_RL_THRSH(8) |
  		0;
  
  	framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
  		V_MAC_MAX_FRAMESZ_DEFAULT |
  		V_MAC_BACKOFF_SEL(1);
  
  	/*

  	 * Clear out the hash address map

  	 */

  	port = s->sbm_base + R_MAC_HASH_BASE;
  	for (idx = 0; idx < MAC_HASH_COUNT; idx++) {

  		__raw_writeq(0, port);

  		port += sizeof(uint64_t);
  	}

  	/*
  	 * Clear out the exact-match table
  	 */

  	port = s->sbm_base + R_MAC_ADDR_BASE;
  	for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {

  		__raw_writeq(0, port);

  		port += sizeof(uint64_t);
  	}

  	/*
  	 * Clear out the DMA Channel mapping table registers
  	 */

  	port = s->sbm_base + R_MAC_CHUP0_BASE;
  	for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {

  		__raw_writeq(0, port);

  		port += sizeof(uint64_t);
  	}
  
  
  	port = s->sbm_base + R_MAC_CHLO0_BASE;
  	for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {

  		__raw_writeq(0, port);

  		port += sizeof(uint64_t);
  	}

  	/*
  	 * Program the hardware address.  It goes into the hardware-address
  	 * register as well as the first filter register.
  	 */

  	reg = sbmac_addr2reg(s->sbm_hwaddr);