Blame view
drivers/ide/it821x.c
20.4 KB
da9091ee3 [PATCH] ide: it82... |
1 |
/* |
ccd32e221 ide: Switch to a ... |
2 |
* Copyright (C) 2004 Red Hat |
0e9b4e535 it821x: PIO mode ... |
3 |
* Copyright (C) 2007 Bartlomiej Zolnierkiewicz |
da9091ee3 [PATCH] ide: it82... |
4 5 6 7 |
* * May be copied or modified under the terms of the GNU General Public License * Based in part on the ITE vendor provided SCSI driver. * |
f38344b0a it821x: remove de... |
8 9 |
* Documentation: * Datasheet is freely available, some other documents under NDA. |
da9091ee3 [PATCH] ide: it82... |
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 |
* * The ITE8212 isn't exactly a standard IDE controller. It has two * modes. In pass through mode then it is an IDE controller. In its smart * mode its actually quite a capable hardware raid controller disguised * as an IDE controller. Smart mode only understands DMA read/write and * identify, none of the fancier commands apply. The IT8211 is identical * in other respects but lacks the raid mode. * * Errata: * o Rev 0x10 also requires master/slave hold the same DMA timings and * cannot do ATAPI MWDMA. * o The identify data for raid volumes lacks CHS info (technically ok) * but also fails to set the LBA28 and other bits. We fix these in * the IDE probe quirk code. * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode * raid then the controller firmware dies * o Smart mode without RAID doesn't clear all the necessary identify * bits to reduce the command set to the one used * * This has a few impacts on the driver * - In pass through mode we do all the work you would expect * - In smart mode the clocking set up is done by the controller generally * but we must watch the other limits and filter. * - There are a few extra vendor commands that actually talk to the * controller but only work PIO with no IRQ. * * Vendor areas of the identify block in smart mode are used for the * timing and policy set up. Each HDD in raid mode also has a serial * block on the disk. The hardware extra commands are get/set chip status, * rebuild, get rebuild status. * * In Linux the driver supports pass through mode as if the device was * just another IDE controller. If the smart mode is running then * volumes are managed by the controller firmware and each IDE "disk" * is a raid volume. Even more cute - the controller can do automated * hotplug and rebuild. * * The pass through controller itself is a little demented. It has a * flaw that it has a single set of PIO/MWDMA timings per channel so * non UDMA devices restrict each others performance. It also has a * single clock source per channel so mixed UDMA100/133 performance * isn't perfect and we have to pick a clock. Thankfully none of this * matters in smart mode. ATAPI DMA is not currently supported. * * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. * * TODO * - ATAPI UDMA is ok but not MWDMA it seems * - RAID configuration ioctls * - Move to libata once it grows up */ |
da9091ee3 [PATCH] ide: it82... |
61 62 |
#include <linux/types.h> #include <linux/module.h> |
5a0e3ad6a include cleanup: ... |
63 |
#include <linux/slab.h> |
da9091ee3 [PATCH] ide: it82... |
64 |
#include <linux/pci.h> |
da9091ee3 [PATCH] ide: it82... |
65 66 |
#include <linux/ide.h> #include <linux/init.h> |
ced3ec8aa ide: prefix messa... |
67 |
#define DRV_NAME "it821x" |
b94b898f3 it821x: Add ultra... |
68 |
#define QUIRK_VORTEX86 1 |
da9091ee3 [PATCH] ide: it82... |
69 70 71 72 73 74 75 76 77 78 79 |
struct it821x_dev { unsigned int smart:1, /* Are we in smart raid mode */ timing10:1; /* Rev 0x10 */ u8 clock_mode; /* 0, ATA_50 or ATA_66 */ u8 want[2][2]; /* Mode/Pri log for master slave */ /* We need these for switching the clock when DMA goes on/off The high byte is the 66Mhz timing */ u16 pio[2]; /* Cached PIO values */ u16 mwdma[2]; /* Cached MWDMA values */ u16 udma[2]; /* Cached UDMA values (per drive) */ |
b94b898f3 it821x: Add ultra... |
80 |
u16 quirks; |
da9091ee3 [PATCH] ide: it82... |
81 82 83 84 85 86 87 88 89 90 91 |
}; #define ATA_66 0 #define ATA_50 1 #define ATA_ANY 2 #define UDMA_OFF 0 #define MWDMA_OFF 0 /* * We allow users to force the card into non raid mode without |
3a4fa0a25 Fix misspellings ... |
92 |
* flashing the alternative BIOS. This is also necessary right now |
da9091ee3 [PATCH] ide: it82... |
93 94 95 96 97 98 99 100 101 |
* for embedded platforms that cannot run a PC BIOS but are using this * device. */ static int it8212_noraid; /** * it821x_program - program the PIO/MWDMA registers * @drive: drive to tune |
0e9b4e535 it821x: PIO mode ... |
102 |
* @timing: timing info |
da9091ee3 [PATCH] ide: it82... |
103 104 105 106 107 108 109 |
* * Program the PIO/MWDMA timing for this channel according to the * current clock. */ static void it821x_program(ide_drive_t *drive, u16 timing) { |
36501650e ide: keep pointer... |
110 111 |
ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee3 [PATCH] ide: it82... |
112 113 114 115 116 117 118 119 120 |
struct it821x_dev *itdev = ide_get_hwifdata(hwif); int channel = hwif->channel; u8 conf; /* Program PIO/MWDMA timing bits */ if(itdev->clock_mode == ATA_66) conf = timing >> 8; else conf = timing & 0xFF; |
36501650e ide: keep pointer... |
121 122 |
pci_write_config_byte(dev, 0x54 + 4 * channel, conf); |
da9091ee3 [PATCH] ide: it82... |
123 124 125 126 127 |
} /** * it821x_program_udma - program the UDMA registers * @drive: drive to tune |
0e9b4e535 it821x: PIO mode ... |
128 |
* @timing: timing info |
da9091ee3 [PATCH] ide: it82... |
129 130 131 132 133 134 135 |
* * Program the UDMA timing for this drive according to the * current clock. */ static void it821x_program_udma(ide_drive_t *drive, u16 timing) { |
36501650e ide: keep pointer... |
136 137 |
ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee3 [PATCH] ide: it82... |
138 139 |
struct it821x_dev *itdev = ide_get_hwifdata(hwif); int channel = hwif->channel; |
123995b97 ide: use 'drive->... |
140 |
u8 unit = drive->dn & 1, conf; |
da9091ee3 [PATCH] ide: it82... |
141 142 143 144 145 146 |
/* Program UDMA timing bits */ if(itdev->clock_mode == ATA_66) conf = timing >> 8; else conf = timing & 0xFF; |
36501650e ide: keep pointer... |
147 148 149 |
if (itdev->timing10 == 0) pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf); |
da9091ee3 [PATCH] ide: it82... |
150 |
else { |
36501650e ide: keep pointer... |
151 152 |
pci_write_config_byte(dev, 0x56 + 4 * channel, conf); pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf); |
da9091ee3 [PATCH] ide: it82... |
153 154 |
} } |
da9091ee3 [PATCH] ide: it82... |
155 156 |
/** * it821x_clock_strategy |
0e9b4e535 it821x: PIO mode ... |
157 |
* @drive: drive to set up |
da9091ee3 [PATCH] ide: it82... |
158 159 160 161 162 163 164 165 |
* * Select between the 50 and 66Mhz base clocks to get the best * results for this interface. */ static void it821x_clock_strategy(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; |
36501650e ide: keep pointer... |
166 |
struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee3 [PATCH] ide: it82... |
167 |
struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
07af5a5b0 it821x: use ide_g... |
168 |
ide_drive_t *pair = ide_get_pair_dev(drive); |
123995b97 ide: use 'drive->... |
169 170 |
int clock, altclock, sel = 0; u8 unit = drive->dn & 1, v; |
da9091ee3 [PATCH] ide: it82... |
171 |
|
da9091ee3 [PATCH] ide: it82... |
172 173 174 175 176 177 178 |
if(itdev->want[0][0] > itdev->want[1][0]) { clock = itdev->want[0][1]; altclock = itdev->want[1][1]; } else { clock = itdev->want[1][1]; altclock = itdev->want[0][1]; } |
0e9b4e535 it821x: PIO mode ... |
179 180 181 182 183 |
/* * if both clocks can be used for the mode with the higher priority * use the clock needed by the mode with the lower priority */ if (clock == ATA_ANY) |
da9091ee3 [PATCH] ide: it82... |
184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 |
clock = altclock; /* Nobody cares - keep the same clock */ if(clock == ATA_ANY) return; /* No change */ if(clock == itdev->clock_mode) return; /* Load this into the controller ? */ if(clock == ATA_66) itdev->clock_mode = ATA_66; else { itdev->clock_mode = ATA_50; sel = 1; } |
36501650e ide: keep pointer... |
200 201 |
pci_read_config_byte(dev, 0x50, &v); |
da9091ee3 [PATCH] ide: it82... |
202 203 |
v &= ~(1 << (1 + hwif->channel)); v |= sel << (1 + hwif->channel); |
36501650e ide: keep pointer... |
204 |
pci_write_config_byte(dev, 0x50, v); |
da9091ee3 [PATCH] ide: it82... |
205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 |
/* * Reprogram the UDMA/PIO of the pair drive for the switch * MWDMA will be dealt with by the dma switcher */ if(pair && itdev->udma[1-unit] != UDMA_OFF) { it821x_program_udma(pair, itdev->udma[1-unit]); it821x_program(pair, itdev->pio[1-unit]); } /* * Reprogram the UDMA/PIO of our drive for the switch. * MWDMA will be dealt with by the dma switcher */ if(itdev->udma[unit] != UDMA_OFF) { it821x_program_udma(drive, itdev->udma[unit]); it821x_program(drive, itdev->pio[unit]); } } /** |
88b2b32ba ide: move ide_con... |
225 |
* it821x_set_pio_mode - set host controller for PIO mode |
e085b3cae ide: change ->set... |
226 |
* @hwif: port |
88b2b32ba ide: move ide_con... |
227 |
* @drive: drive |
da9091ee3 [PATCH] ide: it82... |
228 |
* |
88b2b32ba ide: move ide_con... |
229 230 |
* Tune the host to the desired PIO mode taking into the consideration * the maximum PIO mode supported by the other device on the cable. |
da9091ee3 [PATCH] ide: it82... |
231 |
*/ |
e085b3cae ide: change ->set... |
232 |
static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
da9091ee3 [PATCH] ide: it82... |
233 |
{ |
da9091ee3 [PATCH] ide: it82... |
234 |
struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
07af5a5b0 it821x: use ide_g... |
235 |
ide_drive_t *pair = ide_get_pair_dev(drive); |
e085b3cae ide: change ->set... |
236 |
const u8 pio = drive->pio_mode - XFER_PIO_0; |
123995b97 ide: use 'drive->... |
237 |
u8 unit = drive->dn & 1, set_pio = pio; |
da9091ee3 [PATCH] ide: it82... |
238 239 |
/* Spec says 89 ref driver uses 88 */ |
88b2b32ba ide: move ide_con... |
240 |
static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; |
da9091ee3 [PATCH] ide: it82... |
241 |
static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; |
0e9b4e535 it821x: PIO mode ... |
242 243 244 245 246 247 |
/* * Compute the best PIO mode we can for a given device. We must * pick a speed that does not cause problems with the other device * on the cable. */ if (pair) { |
f657911d7 it821x: use ->pio... |
248 |
u8 pair_pio = pair->pio_mode - XFER_PIO_0; |
0e9b4e535 it821x: PIO mode ... |
249 250 251 252 |
/* trim PIO to the slowest of the master/slave */ if (pair_pio < set_pio) set_pio = pair_pio; } |
da9091ee3 [PATCH] ide: it82... |
253 |
/* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
0e9b4e535 it821x: PIO mode ... |
254 |
itdev->want[unit][1] = pio_want[set_pio]; |
da9091ee3 [PATCH] ide: it82... |
255 |
itdev->want[unit][0] = 1; /* PIO is lowest priority */ |
88b2b32ba ide: move ide_con... |
256 |
itdev->pio[unit] = pio_timings[set_pio]; |
da9091ee3 [PATCH] ide: it82... |
257 258 259 260 261 262 263 264 265 266 267 268 269 270 |
it821x_clock_strategy(drive); it821x_program(drive, itdev->pio[unit]); } /** * it821x_tune_mwdma - tune a channel for MWDMA * @drive: drive to set up * @mode_wanted: the target operating mode * * Load the timing settings for this device mode into the * controller when doing MWDMA in pass through mode. The caller * must manage the whole lack of per device MWDMA/PIO timings and * the shared MWDMA/PIO timing register. */ |
9892ec549 ide: remove 'byte... |
271 |
static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted) |
da9091ee3 [PATCH] ide: it82... |
272 |
{ |
36501650e ide: keep pointer... |
273 274 |
ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee3 [PATCH] ide: it82... |
275 |
struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif); |
123995b97 ide: use 'drive->... |
276 |
u8 unit = drive->dn & 1, channel = hwif->channel, conf; |
da9091ee3 [PATCH] ide: it82... |
277 278 279 280 281 282 283 284 285 286 |
static u16 dma[] = { 0x8866, 0x3222, 0x3121 }; static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; itdev->want[unit][1] = mwdma_want[mode_wanted]; itdev->want[unit][0] = 2; /* MWDMA is low priority */ itdev->mwdma[unit] = dma[mode_wanted]; itdev->udma[unit] = UDMA_OFF; /* UDMA bits off - Revision 0x10 do them in pairs */ |
36501650e ide: keep pointer... |
287 288 |
pci_read_config_byte(dev, 0x50, &conf); if (itdev->timing10) |
da9091ee3 [PATCH] ide: it82... |
289 290 291 |
conf |= channel ? 0x60: 0x18; else conf |= 1 << (3 + 2 * channel + unit); |
36501650e ide: keep pointer... |
292 |
pci_write_config_byte(dev, 0x50, conf); |
da9091ee3 [PATCH] ide: it82... |
293 294 295 296 297 298 299 300 301 302 303 304 305 306 |
it821x_clock_strategy(drive); /* FIXME: do we need to program this ? */ /* it821x_program(drive, itdev->mwdma[unit]); */ } /** * it821x_tune_udma - tune a channel for UDMA * @drive: drive to set up * @mode_wanted: the target operating mode * * Load the timing settings for this device mode into the * controller when doing UDMA modes in pass through. */ |
9892ec549 ide: remove 'byte... |
307 |
static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted) |
da9091ee3 [PATCH] ide: it82... |
308 |
{ |
36501650e ide: keep pointer... |
309 310 |
ide_hwif_t *hwif = drive->hwif; struct pci_dev *dev = to_pci_dev(hwif->dev); |
da9091ee3 [PATCH] ide: it82... |
311 |
struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
123995b97 ide: use 'drive->... |
312 |
u8 unit = drive->dn & 1, channel = hwif->channel, conf; |
da9091ee3 [PATCH] ide: it82... |
313 314 315 316 317 318 319 320 321 322 323 324 |
static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; itdev->want[unit][1] = udma_want[mode_wanted]; itdev->want[unit][0] = 3; /* UDMA is high priority */ itdev->mwdma[unit] = MWDMA_OFF; itdev->udma[unit] = udma[mode_wanted]; if(mode_wanted >= 5) itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ /* UDMA on. Again revision 0x10 must do the pair */ |
36501650e ide: keep pointer... |
325 326 |
pci_read_config_byte(dev, 0x50, &conf); if (itdev->timing10) |
da9091ee3 [PATCH] ide: it82... |
327 328 329 |
conf &= channel ? 0x9F: 0xE7; else conf &= ~ (1 << (3 + 2 * channel + unit)); |
36501650e ide: keep pointer... |
330 |
pci_write_config_byte(dev, 0x50, conf); |
da9091ee3 [PATCH] ide: it82... |
331 332 333 334 335 336 337 |
it821x_clock_strategy(drive); it821x_program_udma(drive, itdev->udma[unit]); } /** |
da9091ee3 [PATCH] ide: it82... |
338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 |
* it821x_dma_read - DMA hook * @drive: drive for DMA * * The IT821x has a single timing register for MWDMA and for PIO * operations. As we flip back and forth we have to reload the * clock. In addition the rev 0x10 device only works if the same * timing value is loaded into the master and slave UDMA clock * so we must also reload that. * * FIXME: we could figure out in advance if we need to do reloads */ static void it821x_dma_start(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
123995b97 ide: use 'drive->... |
354 |
u8 unit = drive->dn & 1; |
da9091ee3 [PATCH] ide: it82... |
355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 |
if(itdev->mwdma[unit] != MWDMA_OFF) it821x_program(drive, itdev->mwdma[unit]); else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10) it821x_program_udma(drive, itdev->udma[unit]); ide_dma_start(drive); } /** * it821x_dma_write - DMA hook * @drive: drive for DMA stop * * The IT821x has a single timing register for MWDMA and for PIO * operations. As we flip back and forth we have to reload the * clock. */ static int it821x_dma_end(ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; |
da9091ee3 [PATCH] ide: it82... |
374 |
struct it821x_dev *itdev = ide_get_hwifdata(hwif); |
653bcf529 ide: __ide_dma_en... |
375 |
int ret = ide_dma_end(drive); |
123995b97 ide: use 'drive->... |
376 |
u8 unit = drive->dn & 1; |
da9091ee3 [PATCH] ide: it82... |
377 378 379 380 |
if(itdev->mwdma[unit] != MWDMA_OFF) it821x_program(drive, itdev->pio[unit]); return ret; } |
da9091ee3 [PATCH] ide: it82... |
381 |
/** |
88b2b32ba ide: move ide_con... |
382 |
* it821x_set_dma_mode - set host controller for DMA mode |
8776168ca ide: change ->set... |
383 |
* @hwif: port |
88b2b32ba ide: move ide_con... |
384 |
* @drive: drive |
da9091ee3 [PATCH] ide: it82... |
385 |
* |
88b2b32ba ide: move ide_con... |
386 |
* Tune the ITE chipset for the desired DMA mode. |
da9091ee3 [PATCH] ide: it82... |
387 |
*/ |
8776168ca ide: change ->set... |
388 |
static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
da9091ee3 [PATCH] ide: it82... |
389 |
{ |
8776168ca ide: change ->set... |
390 |
const u8 speed = drive->dma_mode; |
88b2b32ba ide: move ide_con... |
391 392 393 394 395 396 397 398 399 |
/* * MWDMA tuning is really hard because our MWDMA and PIO * timings are kept in the same place. We can switch in the * host dma on/off callbacks. */ if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6) it821x_tune_udma(drive, speed - XFER_UDMA_0); else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0); |
da9091ee3 [PATCH] ide: it82... |
400 401 402 |
} /** |
ac95beedf ide: add struct i... |
403 |
* it821x_cable_detect - cable detection |
da9091ee3 [PATCH] ide: it82... |
404 405 406 407 408 409 |
* @hwif: interface to check * * Check for the presence of an ATA66 capable cable on the * interface. Problematic as it seems some cards don't have * the needed logic onboard. */ |
f454cbe8c ide: ->cable_dete... |
410 |
static u8 it821x_cable_detect(ide_hwif_t *hwif) |
da9091ee3 [PATCH] ide: it82... |
411 412 |
{ /* The reference driver also only does disk side */ |
49521f97c ide: add short ca... |
413 |
return ATA_CBL_PATA80; |
da9091ee3 [PATCH] ide: it82... |
414 415 416 |
} /** |
f01393e48 ide: merge ->fixu... |
417 418 |
* it821x_quirkproc - post init callback * @drive: drive |
da9091ee3 [PATCH] ide: it82... |
419 |
* |
f01393e48 ide: merge ->fixu... |
420 |
* This callback is run after the drive has been probed but |
da9091ee3 [PATCH] ide: it82... |
421 422 423 |
* before anything gets attached. It allows drivers to do any * final tuning that is needed, or fixups to work around bugs. */ |
36de99480 ide: ->quirkproc ... |
424 |
static void it821x_quirkproc(ide_drive_t *drive) |
da9091ee3 [PATCH] ide: it82... |
425 |
{ |
f01393e48 ide: merge ->fixu... |
426 |
struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif); |
4dde4492d ide: make drive->... |
427 |
u16 *id = drive->id; |
da9091ee3 [PATCH] ide: it82... |
428 |
|
f01393e48 ide: merge ->fixu... |
429 |
if (!itdev->smart) { |
da9091ee3 [PATCH] ide: it82... |
430 431 432 433 434 435 |
/* * If we are in pass through mode then not much * needs to be done, but we do bother to clear the * IRQ mask as we may well be in PIO (eg rev 0x10) * for now and we know unmasking is safe on this chipset. */ |
97100fc81 ide: add device f... |
436 |
drive->dev_flags |= IDE_DFLAG_UNMASK; |
f01393e48 ide: merge ->fixu... |
437 |
} else { |
da9091ee3 [PATCH] ide: it82... |
438 439 440 441 442 443 |
/* * Perform fixups on smart mode. We need to "lose" some * capabilities the firmware lacks but does not filter, and * also patch up some capability bits that it forgets to set * in RAID mode. */ |
da9091ee3 [PATCH] ide: it82... |
444 |
/* Check for RAID v native */ |
4dde4492d ide: make drive->... |
445 446 |
if (strstr((char *)&id[ATA_ID_PROD], "Integrated Technology Express")) { |
da9091ee3 [PATCH] ide: it82... |
447 448 449 |
/* In raid mode the ident block is slightly buggy We need to set the bits so that the IDE layer knows LBA28. LBA48 and DMA ar valid */ |
48fb2688a ide: remove drive... |
450 |
id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */ |
4dde4492d ide: make drive->... |
451 452 |
id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */ id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */ |
da9091ee3 [PATCH] ide: it82... |
453 454 |
/* Reporting logic */ printk(KERN_INFO "%s: IT8212 %sRAID %d volume", |
4dde4492d ide: make drive->... |
455 456 457 458 459 460 |
drive->name, id[147] ? "Bootable " : "", id[ATA_ID_CSFO]); if (id[ATA_ID_CSFO] != 1) printk(KERN_CONT "(%dK stripe)", id[146]); printk(KERN_CONT ". "); |
da9091ee3 [PATCH] ide: it82... |
461 462 463 |
} else { /* Non RAID volume. Fixups to stop the core code doing unsupported things */ |
4dde4492d ide: make drive->... |
464 465 466 467 468 469 470 471 472 473 474 475 |
id[ATA_ID_FIELD_VALID] &= 3; id[ATA_ID_QUEUE_DEPTH] = 0; id[ATA_ID_COMMAND_SET_1] = 0; id[ATA_ID_COMMAND_SET_2] &= 0xC400; id[ATA_ID_CFSSE] &= 0xC000; id[ATA_ID_CFS_ENABLE_1] = 0; id[ATA_ID_CFS_ENABLE_2] &= 0xC400; id[ATA_ID_CSF_DEFAULT] &= 0xC000; id[127] = 0; id[ATA_ID_DLF] = 0; id[ATA_ID_CSFO] = 0; id[ATA_ID_CFA_POWER] = 0; |
da9091ee3 [PATCH] ide: it82... |
476 477 478 479 |
printk(KERN_INFO "%s: Performing identify fixups. ", drive->name); } |
0380dad45 it821x: RAID mode... |
480 481 482 483 484 485 |
/* * Set MWDMA0 mode as enabled/support - just to tell * IDE core that DMA is supported (it821x hardware * takes care of DMA mode programming). */ |
48fb2688a ide: remove drive... |
486 |
if (ata_id_has_dma(id)) { |
4dde4492d ide: make drive->... |
487 |
id[ATA_ID_MWDMA_MODES] |= 0x0101; |
0380dad45 it821x: RAID mode... |
488 489 |
drive->current_speed = XFER_MW_DMA_0; } |
da9091ee3 [PATCH] ide: it82... |
490 491 492 |
} } |
b5a608fb2 ide: constify ide... |
493 |
static const struct ide_dma_ops it821x_pass_through_dma_ops = { |
84e0f3f6c ide: it821x in pa... |
494 495 |
.dma_host_set = ide_dma_host_set, .dma_setup = ide_dma_setup, |
5e37bdc08 ide: add struct i... |
496 497 |
.dma_start = it821x_dma_start, .dma_end = it821x_dma_end, |
84e0f3f6c ide: it821x in pa... |
498 |
.dma_test_irq = ide_dma_test_irq, |
84e0f3f6c ide: it821x in pa... |
499 |
.dma_lost_irq = ide_dma_lost_irq, |
35c9b4daf ide: add ->dma_cl... |
500 |
.dma_timer_expiry = ide_dma_sff_timer_expiry, |
592b53152 ide: move read_sf... |
501 |
.dma_sff_read_status = ide_dma_sff_read_status, |
5e37bdc08 ide: add struct i... |
502 |
}; |
da9091ee3 [PATCH] ide: it82... |
503 504 505 506 507 508 509 510 |
/** * init_hwif_it821x - set up hwif structs * @hwif: interface to set up * * We do the basic set up of the interface structure. The IT8212 * requires several custom handlers so we override the default * ide DMA handlers appropriately */ |
fe31edc8a Drivers: ide: rem... |
511 |
static void init_hwif_it821x(ide_hwif_t *hwif) |
da9091ee3 [PATCH] ide: it82... |
512 |
{ |
36501650e ide: keep pointer... |
513 |
struct pci_dev *dev = to_pci_dev(hwif->dev); |
1d76d9dc4 it821x: convert t... |
514 515 516 |
struct ide_host *host = pci_get_drvdata(dev); struct it821x_dev *itdevs = host->host_priv; struct it821x_dev *idev = itdevs + hwif->channel; |
da9091ee3 [PATCH] ide: it82... |
517 |
u8 conf; |
da9091ee3 [PATCH] ide: it82... |
518 |
ide_set_hwifdata(hwif, idev); |
36501650e ide: keep pointer... |
519 |
pci_read_config_byte(dev, 0x50, &conf); |
33c1002ed ide: add IDE_HFLA... |
520 |
if (conf & 1) { |
da9091ee3 [PATCH] ide: it82... |
521 |
idev->smart = 1; |
33c1002ed ide: add IDE_HFLA... |
522 |
hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; |
da9091ee3 [PATCH] ide: it82... |
523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 |
/* Long I/O's although allowed in LBA48 space cause the onboard firmware to enter the twighlight zone */ hwif->rqsize = 256; } /* Pull the current clocks from 0x50 also */ if (conf & (1 << (1 + hwif->channel))) idev->clock_mode = ATA_50; else idev->clock_mode = ATA_66; idev->want[0][1] = ATA_ANY; idev->want[1][1] = ATA_ANY; /* * Not in the docs but according to the reference driver |
3a4fa0a25 Fix misspellings ... |
539 |
* this is necessary. |
da9091ee3 [PATCH] ide: it82... |
540 |
*/ |
4a2462693 it821x.c: use dev... |
541 |
if (dev->revision == 0x10) { |
da9091ee3 [PATCH] ide: it82... |
542 |
idev->timing10 = 1; |
33c1002ed ide: add IDE_HFLA... |
543 544 |
hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA; if (idev->smart == 0) |
ced3ec8aa ide: prefix messa... |
545 |
printk(KERN_WARNING DRV_NAME " %s: revision 0x10, " |
28cfd8af5 ide: include PCI ... |
546 547 |
"workarounds activated ", pci_name(dev)); |
da9091ee3 [PATCH] ide: it82... |
548 |
} |
88b2b32ba ide: move ide_con... |
549 |
if (idev->smart == 0) { |
88b2b32ba ide: move ide_con... |
550 |
/* MWDMA/PIO clock switching for pass through mode */ |
5e37bdc08 ide: add struct i... |
551 |
hwif->dma_ops = &it821x_pass_through_dma_ops; |
88b2b32ba ide: move ide_con... |
552 553 |
} else hwif->host_flags |= IDE_HFLAG_NO_SET_MODE; |
da9091ee3 [PATCH] ide: it82... |
554 |
|
9ff6f72f4 ide: remove hwif-... |
555 556 |
if (hwif->dma_base == 0) return; |
da9091ee3 [PATCH] ide: it82... |
557 |
|
5f8b6c348 ide: add ->mwdma_... |
558 559 |
hwif->ultra_mask = ATA_UDMA6; hwif->mwdma_mask = ATA_MWDMA2; |
b94b898f3 it821x: Add ultra... |
560 561 562 563 564 565 |
/* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */ if (idev->quirks & QUIRK_VORTEX86) { if (dev->revision == 0x11) hwif->ultra_mask = 0; } |
da9091ee3 [PATCH] ide: it82... |
566 |
} |
feb22b7f8 ide: add proper P... |
567 |
static void it8212_disable_raid(struct pci_dev *dev) |
da9091ee3 [PATCH] ide: it82... |
568 569 570 571 572 573 574 575 576 577 578 579 580 |
{ /* Reset local CPU, and set BIOS not ready */ pci_write_config_byte(dev, 0x5E, 0x01); /* Set to bypass mode, and reset PCI bus */ pci_write_config_byte(dev, 0x50, 0x00); pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_PARITY | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); pci_write_config_word(dev, 0x40, 0xA0F3); pci_write_config_dword(dev,0x4C, 0x02040204); pci_write_config_byte(dev, 0x42, 0x36); |
0c866b510 [PATCH] ide: set ... |
581 |
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20); |
da9091ee3 [PATCH] ide: it82... |
582 |
} |
2ed0ef543 ide: fix ->init_c... |
583 |
static int init_chipset_it821x(struct pci_dev *dev) |
da9091ee3 [PATCH] ide: it82... |
584 585 586 587 588 589 |
{ u8 conf; static char *mode[2] = { "pass through", "smart" }; /* Force the card into bypass mode if so requested */ if (it8212_noraid) { |
ced3ec8aa ide: prefix messa... |
590 591 |
printk(KERN_INFO DRV_NAME " %s: forcing bypass mode ", |
28cfd8af5 ide: include PCI ... |
592 |
pci_name(dev)); |
da9091ee3 [PATCH] ide: it82... |
593 594 595 |
it8212_disable_raid(dev); } pci_read_config_byte(dev, 0x50, &conf); |
ced3ec8aa ide: prefix messa... |
596 597 |
printk(KERN_INFO DRV_NAME " %s: controller in %s mode ", |
28cfd8af5 ide: include PCI ... |
598 |
pci_name(dev), mode[conf & 1]); |
da9091ee3 [PATCH] ide: it82... |
599 600 |
return 0; } |
ac95beedf ide: add struct i... |
601 602 603 604 605 606 607 |
static const struct ide_port_ops it821x_port_ops = { /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */ .set_pio_mode = it821x_set_pio_mode, .set_dma_mode = it821x_set_dma_mode, .quirkproc = it821x_quirkproc, .cable_detect = it821x_cable_detect, }; |
da9091ee3 [PATCH] ide: it82... |
608 |
|
fe31edc8a Drivers: ide: rem... |
609 |
static const struct ide_port_info it821x_chipset = { |
ced3ec8aa ide: prefix messa... |
610 |
.name = DRV_NAME, |
04ba6e739 it821x: remove DE... |
611 612 613 614 |
.init_chipset = init_chipset_it821x, .init_hwif = init_hwif_it821x, .port_ops = &it821x_port_ops, .pio_mask = ATA_PIO4, |
da9091ee3 [PATCH] ide: it82... |
615 616 617 618 619 620 621 622 623 624 |
}; /** * it821x_init_one - pci layer discovery entry * @dev: PCI device * @id: ident table entry * * Called by the PCI code when it finds an ITE821x controller. * We then use the IDE PCI generic helper to do most of the work. */ |
fe31edc8a Drivers: ide: rem... |
625 |
static int it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
da9091ee3 [PATCH] ide: it82... |
626 |
{ |
1d76d9dc4 it821x: convert t... |
627 628 |
struct it821x_dev *itdevs; int rc; |
eb7a07e8d it821x: fix kzall... |
629 |
|
6396bb221 treewide: kzalloc... |
630 |
itdevs = kcalloc(2, sizeof(*itdevs), GFP_KERNEL); |
1d76d9dc4 it821x: convert t... |
631 |
if (itdevs == NULL) { |
ced3ec8aa ide: prefix messa... |
632 633 |
printk(KERN_ERR DRV_NAME " %s: out of memory ", pci_name(dev)); |
1d76d9dc4 it821x: convert t... |
634 |
return -ENOMEM; |
eb7a07e8d it821x: fix kzall... |
635 |
} |
b94b898f3 it821x: Add ultra... |
636 |
itdevs->quirks = id->driver_data; |
04ba6e739 it821x: remove DE... |
637 |
rc = ide_pci_init_one(dev, &it821x_chipset, itdevs); |
1d76d9dc4 it821x: convert t... |
638 639 |
if (rc) kfree(itdevs); |
eb7a07e8d it821x: fix kzall... |
640 |
|
1d76d9dc4 it821x: convert t... |
641 |
return rc; |
da9091ee3 [PATCH] ide: it82... |
642 |
} |
fe31edc8a Drivers: ide: rem... |
643 |
static void it821x_remove(struct pci_dev *dev) |
87d8b6135 it821x: add ->rem... |
644 645 646 647 648 649 650 |
{ struct ide_host *host = pci_get_drvdata(dev); struct it821x_dev *itdevs = host->host_priv; ide_pci_remove(dev); kfree(itdevs); } |
9cbcc5e3c ide: use PCI_VDEV... |
651 652 653 |
static const struct pci_device_id it821x_pci_tbl[] = { { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 }, { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 }, |
b94b898f3 it821x: Add ultra... |
654 |
{ PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 }, |
da9091ee3 [PATCH] ide: it82... |
655 656 657 658 |
{ 0, }, }; MODULE_DEVICE_TABLE(pci, it821x_pci_tbl); |
a9ab09e26 ide: use unique n... |
659 |
static struct pci_driver it821x_pci_driver = { |
da9091ee3 [PATCH] ide: it82... |
660 661 662 |
.name = "ITE821x IDE", .id_table = it821x_pci_tbl, .probe = it821x_init_one, |
fe31edc8a Drivers: ide: rem... |
663 |
.remove = it821x_remove, |
feb22b7f8 ide: add proper P... |
664 665 |
.suspend = ide_pci_suspend, .resume = ide_pci_resume, |
da9091ee3 [PATCH] ide: it82... |
666 667 668 669 |
}; static int __init it821x_ide_init(void) { |
a9ab09e26 ide: use unique n... |
670 |
return ide_pci_register_driver(&it821x_pci_driver); |
da9091ee3 [PATCH] ide: it82... |
671 |
} |
87d8b6135 it821x: add ->rem... |
672 673 |
static void __exit it821x_ide_exit(void) { |
a9ab09e26 ide: use unique n... |
674 |
pci_unregister_driver(&it821x_pci_driver); |
87d8b6135 it821x: add ->rem... |
675 |
} |
da9091ee3 [PATCH] ide: it82... |
676 |
module_init(it821x_ide_init); |
87d8b6135 it821x: add ->rem... |
677 |
module_exit(it821x_ide_exit); |
da9091ee3 [PATCH] ide: it82... |
678 679 |
module_param_named(noraid, it8212_noraid, int, S_IRUGO); |
da1956655 it821x: do not de... |
680 |
MODULE_PARM_DESC(noraid, "Force card into bypass mode"); |
da9091ee3 [PATCH] ide: it82... |
681 682 683 684 |
MODULE_AUTHOR("Alan Cox"); MODULE_DESCRIPTION("PCI driver module for the ITE 821x"); MODULE_LICENSE("GPL"); |