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drivers/rtc/rtc-ds1307.c
24.5 KB
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/* * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. * * Copyright (C) 2005 James Chapman (ds1337 core) * Copyright (C) 2006 David Brownell |
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* Copyright (C) 2009 Matthias Fuchs (rx8025 support) |
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* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include <linux/module.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/i2c.h> #include <linux/string.h> #include <linux/rtc.h> #include <linux/bcd.h> /* We can't determine type by probing, but if we expect pre-Linux code * to have set the chip up as a clock (turning on the oscillator and * setting the date and time), Linux can ignore the non-clock features. * That's a natural job for a factory or repair bench. |
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*/ enum ds_type { |
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ds_1307, ds_1337, ds_1338, ds_1339, ds_1340, |
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ds_1388, |
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ds_3231, |
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m41t00, |
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mcp7941x, |
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rx_8025, |
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// rs5c372 too? different address... }; |
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/* RTC registers don't differ much, except for the century flag */ #define DS1307_REG_SECS 0x00 /* 00-59 */ # define DS1307_BIT_CH 0x80 |
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# define DS1340_BIT_nEOSC 0x80 |
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# define MCP7941X_BIT_ST 0x80 |
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#define DS1307_REG_MIN 0x01 /* 00-59 */ #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */ |
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# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */ # define DS1307_BIT_PM 0x20 /* in REG_HOUR */ |
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# define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */ # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */ #define DS1307_REG_WDAY 0x03 /* 01-07 */ |
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# define MCP7941X_BIT_VBATEN 0x08 |
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#define DS1307_REG_MDAY 0x04 /* 01-31 */ #define DS1307_REG_MONTH 0x05 /* 01-12 */ # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */ #define DS1307_REG_YEAR 0x06 /* 00-99 */ /* Other registers (control, status, alarms, trickle charge, NVRAM, etc) |
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* start at 7, and they differ a LOT. Only control and status matter for * basic RTC date and time functionality; be careful using them. |
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*/ |
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#define DS1307_REG_CONTROL 0x07 /* or ds1338 */ |
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# define DS1307_BIT_OUT 0x80 |
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# define DS1338_BIT_OSF 0x20 |
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# define DS1307_BIT_SQWE 0x10 # define DS1307_BIT_RS1 0x02 # define DS1307_BIT_RS0 0x01 #define DS1337_REG_CONTROL 0x0e # define DS1337_BIT_nEOSC 0x80 |
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# define DS1339_BIT_BBSQI 0x20 |
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# define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */ |
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# define DS1337_BIT_RS2 0x10 # define DS1337_BIT_RS1 0x08 # define DS1337_BIT_INTCN 0x04 # define DS1337_BIT_A2IE 0x02 # define DS1337_BIT_A1IE 0x01 |
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#define DS1340_REG_CONTROL 0x07 # define DS1340_BIT_OUT 0x80 # define DS1340_BIT_FT 0x40 # define DS1340_BIT_CALIB_SIGN 0x20 # define DS1340_M_CALIBRATION 0x1f |
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#define DS1340_REG_FLAG 0x09 # define DS1340_BIT_OSF 0x80 |
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#define DS1337_REG_STATUS 0x0f # define DS1337_BIT_OSF 0x80 # define DS1337_BIT_A2I 0x02 # define DS1337_BIT_A1I 0x01 |
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#define DS1339_REG_ALARM1_SECS 0x07 |
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#define DS1339_REG_TRICKLE 0x10 |
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#define RX8025_REG_CTRL1 0x0e # define RX8025_BIT_2412 0x20 #define RX8025_REG_CTRL2 0x0f # define RX8025_BIT_PON 0x10 # define RX8025_BIT_VDET 0x40 # define RX8025_BIT_XST 0x20 |
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struct ds1307 { |
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u8 offset; /* register's offset */ |
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u8 regs[11]; |
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enum ds_type type; |
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unsigned long flags; #define HAS_NVRAM 0 /* bit 0 == sysfs file active */ #define HAS_ALARM 1 /* bit 1 == irq claimed */ |
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struct i2c_client *client; |
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struct rtc_device *rtc; |
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struct work_struct work; |
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s32 (*read_block_data)(const struct i2c_client *client, u8 command, |
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u8 length, u8 *values); |
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s32 (*write_block_data)(const struct i2c_client *client, u8 command, |
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u8 length, const u8 *values); |
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}; |
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struct chip_desc { |
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unsigned nvram56:1; unsigned alarm:1; |
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}; |
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static const struct chip_desc chips[] = { [ds_1307] = { |
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.nvram56 = 1, |
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}, [ds_1337] = { |
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.alarm = 1, |
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}, [ds_1338] = { |
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.nvram56 = 1, |
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}, [ds_1339] = { |
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.alarm = 1, |
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}, [ds_1340] = { }, |
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[ds_3231] = { .alarm = 1, }, |
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[m41t00] = { |
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}, |
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[mcp7941x] = { }, |
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[rx_8025] = { |
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}, }; |
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static const struct i2c_device_id ds1307_id[] = { { "ds1307", ds_1307 }, { "ds1337", ds_1337 }, { "ds1338", ds_1338 }, { "ds1339", ds_1339 }, |
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{ "ds1388", ds_1388 }, |
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{ "ds1340", ds_1340 }, |
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{ "ds3231", ds_3231 }, |
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{ "m41t00", m41t00 }, |
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{ "mcp7941x", mcp7941x }, |
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{ "pt7c4338", ds_1307 }, |
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{ "rx8025", rx_8025 }, |
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{ } }; MODULE_DEVICE_TABLE(i2c, ds1307_id); |
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/*----------------------------------------------------------------------*/ |
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#define BLOCK_DATA_MAX_TRIES 10 |
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static s32 ds1307_read_block_data_once(const struct i2c_client *client, u8 command, u8 length, u8 *values) |
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{ s32 i, data; for (i = 0; i < length; i++) { data = i2c_smbus_read_byte_data(client, command + i); if (data < 0) return data; values[i] = data; } return i; } |
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static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command, |
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u8 length, u8 *values) { u8 oldvalues[I2C_SMBUS_BLOCK_MAX]; s32 ret; int tries = 0; dev_dbg(&client->dev, "ds1307_read_block_data (length=%d) ", length); ret = ds1307_read_block_data_once(client, command, length, values); if (ret < 0) return ret; do { if (++tries > BLOCK_DATA_MAX_TRIES) { dev_err(&client->dev, "ds1307_read_block_data failed "); return -EIO; } memcpy(oldvalues, values, length); ret = ds1307_read_block_data_once(client, command, length, values); if (ret < 0) return ret; } while (memcmp(oldvalues, values, length)); return length; } |
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static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command, |
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u8 length, const u8 *values) { u8 currvalues[I2C_SMBUS_BLOCK_MAX]; int tries = 0; dev_dbg(&client->dev, "ds1307_write_block_data (length=%d) ", length); do { s32 i, ret; if (++tries > BLOCK_DATA_MAX_TRIES) { dev_err(&client->dev, "ds1307_write_block_data failed "); return -EIO; } for (i = 0; i < length; i++) { ret = i2c_smbus_write_byte_data(client, command + i, values[i]); if (ret < 0) return ret; } ret = ds1307_read_block_data_once(client, command, length, currvalues); if (ret < 0) return ret; } while (memcmp(currvalues, values, length)); return length; } /*----------------------------------------------------------------------*/ |
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/* * The IRQ logic includes a "real" handler running in IRQ context just * long enough to schedule this workqueue entry. We need a task context * to talk to the RTC, since I2C I/O calls require that; and disable the * IRQ until we clear its status on the chip, so that this handler can * work with any type of triggering (not just falling edge). * * The ds1337 and ds1339 both have two alarms, but we only use the first * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm * signal; ds1339 chips have only one alarm signal. */ static void ds1307_work(struct work_struct *work) { struct ds1307 *ds1307; struct i2c_client *client; struct mutex *lock; int stat, control; ds1307 = container_of(work, struct ds1307, work); client = ds1307->client; lock = &ds1307->rtc->ops_lock; mutex_lock(lock); stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS); if (stat < 0) goto out; if (stat & DS1337_BIT_A1I) { stat &= ~DS1337_BIT_A1I; i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat); control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); if (control < 0) goto out; control &= ~DS1337_BIT_A1IE; i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control); |
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rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF); |
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} out: if (test_bit(HAS_ALARM, &ds1307->flags)) enable_irq(client->irq); mutex_unlock(lock); } static irqreturn_t ds1307_irq(int irq, void *dev_id) { struct i2c_client *client = dev_id; struct ds1307 *ds1307 = i2c_get_clientdata(client); disable_irq_nosync(irq); schedule_work(&ds1307->work); return IRQ_HANDLED; } /*----------------------------------------------------------------------*/ |
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static int ds1307_get_time(struct device *dev, struct rtc_time *t) { struct ds1307 *ds1307 = dev_get_drvdata(dev); int tmp; |
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/* read the RTC date and time registers all at once */ |
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tmp = ds1307->read_block_data(ds1307->client, |
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ds1307->offset, 7, ds1307->regs); |
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if (tmp != 7) { |
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dev_err(dev, "%s error %d ", "read", tmp); return -EIO; } dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x ", "read", ds1307->regs[0], ds1307->regs[1], ds1307->regs[2], ds1307->regs[3], ds1307->regs[4], ds1307->regs[5], ds1307->regs[6]); |
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t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f); t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f); |
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tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f; |
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t->tm_hour = bcd2bin(tmp); t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1; t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f); |
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tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f; |
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t->tm_mon = bcd2bin(tmp) - 1; |
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/* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */ |
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t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100; |
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dev_dbg(dev, "%s secs=%d, mins=%d, " "hours=%d, mday=%d, mon=%d, year=%d, wday=%d ", "read", t->tm_sec, t->tm_min, t->tm_hour, t->tm_mday, t->tm_mon, t->tm_year, t->tm_wday); |
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/* initial clock setting can be undefined */ return rtc_valid_tm(t); |
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} static int ds1307_set_time(struct device *dev, struct rtc_time *t) { struct ds1307 *ds1307 = dev_get_drvdata(dev); int result; int tmp; u8 *buf = ds1307->regs; dev_dbg(dev, "%s secs=%d, mins=%d, " "hours=%d, mday=%d, mon=%d, year=%d, wday=%d ", |
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"write", t->tm_sec, t->tm_min, t->tm_hour, t->tm_mday, t->tm_mon, t->tm_year, t->tm_wday); |
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buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec); buf[DS1307_REG_MIN] = bin2bcd(t->tm_min); buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour); buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1); buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday); buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1); |
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/* assume 20YY not 19YY */ tmp = t->tm_year - 100; |
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buf[DS1307_REG_YEAR] = bin2bcd(tmp); |
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switch (ds1307->type) { case ds_1337: case ds_1339: |
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case ds_3231: |
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buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY; |
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break; case ds_1340: |
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buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN | DS1340_BIT_CENTURY; |
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break; |
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case mcp7941x: buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST; buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN; break; |
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default: break; } |
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dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x ", "write", buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); |
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result = ds1307->write_block_data(ds1307->client, ds1307->offset, 7, buf); |
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if (result < 0) { dev_err(dev, "%s error %d ", "write", result); return result; |
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} return 0; } |
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static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) |
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{ struct i2c_client *client = to_i2c_client(dev); struct ds1307 *ds1307 = i2c_get_clientdata(client); int ret; if (!test_bit(HAS_ALARM, &ds1307->flags)) return -EINVAL; /* read all ALARM1, ALARM2, and status registers at once */ |
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ret = ds1307->read_block_data(client, |
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DS1339_REG_ALARM1_SECS, 9, ds1307->regs); if (ret != 9) { |
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dev_err(dev, "%s error %d ", "alarm read", ret); return -EIO; } dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x ", "alarm read", ds1307->regs[0], ds1307->regs[1], ds1307->regs[2], ds1307->regs[3], ds1307->regs[4], ds1307->regs[5], ds1307->regs[6], ds1307->regs[7], ds1307->regs[8]); /* report alarm time (ALARM1); assume 24 hour and day-of-month modes, * and that all four fields are checked matches */ t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f); t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f); t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f); t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f); t->time.tm_mon = -1; t->time.tm_year = -1; t->time.tm_wday = -1; t->time.tm_yday = -1; t->time.tm_isdst = -1; /* ... and status */ t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE); t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I); dev_dbg(dev, "%s secs=%d, mins=%d, " "hours=%d, mday=%d, enabled=%d, pending=%d ", "alarm read", t->time.tm_sec, t->time.tm_min, t->time.tm_hour, t->time.tm_mday, t->enabled, t->pending); return 0; } |
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static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) |
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{ struct i2c_client *client = to_i2c_client(dev); struct ds1307 *ds1307 = i2c_get_clientdata(client); unsigned char *buf = ds1307->regs; u8 control, status; int ret; if (!test_bit(HAS_ALARM, &ds1307->flags)) return -EINVAL; dev_dbg(dev, "%s secs=%d, mins=%d, " "hours=%d, mday=%d, enabled=%d, pending=%d ", "alarm set", t->time.tm_sec, t->time.tm_min, t->time.tm_hour, t->time.tm_mday, t->enabled, t->pending); /* read current status of both alarms and the chip */ |
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ret = ds1307->read_block_data(client, |
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DS1339_REG_ALARM1_SECS, 9, buf); if (ret != 9) { |
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dev_err(dev, "%s error %d ", "alarm write", ret); return -EIO; } control = ds1307->regs[7]; status = ds1307->regs[8]; dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x ", "alarm set (old status)", ds1307->regs[0], ds1307->regs[1], ds1307->regs[2], ds1307->regs[3], ds1307->regs[4], ds1307->regs[5], ds1307->regs[6], control, status); /* set ALARM1, using 24 hour and day-of-month modes */ |
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buf[0] = bin2bcd(t->time.tm_sec); buf[1] = bin2bcd(t->time.tm_min); buf[2] = bin2bcd(t->time.tm_hour); buf[3] = bin2bcd(t->time.tm_mday); /* set ALARM2 to non-garbage */ buf[4] = 0; buf[5] = 0; buf[6] = 0; /* optionally enable ALARM1 */ buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE); if (t->enabled) { dev_dbg(dev, "alarm IRQ armed "); buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */ } buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I); |
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ret = ds1307->write_block_data(client, |
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DS1339_REG_ALARM1_SECS, 9, buf); if (ret < 0) { |
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dev_err(dev, "can't set alarm time "); |
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return ret; |
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} return 0; } |
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static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) |
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{ struct i2c_client *client = to_i2c_client(dev); struct ds1307 *ds1307 = i2c_get_clientdata(client); int ret; |
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if (!test_bit(HAS_ALARM, &ds1307->flags)) return -ENOTTY; |
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|
515 516 517 |
ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL); if (ret < 0) return ret; |
cb49a5e9e
|
518 |
|
16380c153
|
519 |
if (enabled) |
cb49a5e9e
|
520 |
ret |= DS1337_BIT_A1IE; |
16380c153
|
521 522 |
else ret &= ~DS1337_BIT_A1IE; |
cb49a5e9e
|
523 |
|
16380c153
|
524 525 526 |
ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret); if (ret < 0) return ret; |
cb49a5e9e
|
527 528 529 |
return 0; } |
ff8371ac9
|
530 |
static const struct rtc_class_ops ds13xx_rtc_ops = { |
1abb0dc92
|
531 532 |
.read_time = ds1307_get_time, .set_time = ds1307_set_time, |
74d88eb29
|
533 534 |
.read_alarm = ds1337_read_alarm, .set_alarm = ds1337_set_alarm, |
16380c153
|
535 |
.alarm_irq_enable = ds1307_alarm_irq_enable, |
1abb0dc92
|
536 |
}; |
682d73f68
|
537 538 539 540 541 |
/*----------------------------------------------------------------------*/ #define NVRAM_SIZE 56 static ssize_t |
2c3c8bea6
|
542 543 |
ds1307_nvram_read(struct file *filp, struct kobject *kobj, struct bin_attribute *attr, |
682d73f68
|
544 545 546 547 |
char *buf, loff_t off, size_t count) { struct i2c_client *client; struct ds1307 *ds1307; |
682d73f68
|
548 |
int result; |
fcd8db002
|
549 |
client = kobj_to_i2c_client(kobj); |
682d73f68
|
550 551 552 553 554 555 556 557 |
ds1307 = i2c_get_clientdata(client); if (unlikely(off >= NVRAM_SIZE)) return 0; if ((off + count) > NVRAM_SIZE) count = NVRAM_SIZE - off; if (unlikely(!count)) return count; |
30e7b039b
|
558 |
result = ds1307->read_block_data(client, 8 + off, count, buf); |
fed40b734
|
559 |
if (result < 0) |
682d73f68
|
560 561 |
dev_err(&client->dev, "%s error %d ", "nvram read", result); |
fed40b734
|
562 |
return result; |
682d73f68
|
563 564 565 |
} static ssize_t |
2c3c8bea6
|
566 567 |
ds1307_nvram_write(struct file *filp, struct kobject *kobj, struct bin_attribute *attr, |
682d73f68
|
568 569 570 |
char *buf, loff_t off, size_t count) { struct i2c_client *client; |
30e7b039b
|
571 |
struct ds1307 *ds1307; |
fed40b734
|
572 |
int result; |
682d73f68
|
573 |
|
fcd8db002
|
574 |
client = kobj_to_i2c_client(kobj); |
30e7b039b
|
575 |
ds1307 = i2c_get_clientdata(client); |
682d73f68
|
576 577 578 579 580 581 582 |
if (unlikely(off >= NVRAM_SIZE)) return -EFBIG; if ((off + count) > NVRAM_SIZE) count = NVRAM_SIZE - off; if (unlikely(!count)) return count; |
30e7b039b
|
583 |
result = ds1307->write_block_data(client, 8 + off, count, buf); |
fed40b734
|
584 585 586 587 588 589 |
if (result < 0) { dev_err(&client->dev, "%s error %d ", "nvram write", result); return result; } return count; |
682d73f68
|
590 591 592 593 594 595 |
} static struct bin_attribute nvram = { .attr = { .name = "nvram", .mode = S_IRUGO | S_IWUSR, |
682d73f68
|
596 597 598 599 600 601 602 603 |
}, .read = ds1307_nvram_read, .write = ds1307_nvram_write, .size = NVRAM_SIZE, }; /*----------------------------------------------------------------------*/ |
1abb0dc92
|
604 |
static struct i2c_driver ds1307_driver; |
d2653e927
|
605 606 |
static int __devinit ds1307_probe(struct i2c_client *client, const struct i2c_device_id *id) |
1abb0dc92
|
607 608 609 |
{ struct ds1307 *ds1307; int err = -ENODEV; |
1abb0dc92
|
610 |
int tmp; |
3760f7367
|
611 |
const struct chip_desc *chip = &chips[id->driver_data]; |
c065f35c1
|
612 |
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
cb49a5e9e
|
613 |
int want_irq = false; |
fed40b734
|
614 |
unsigned char *buf; |
97f902b7b
|
615 616 617 618 619 |
static const int bbsqi_bitpos[] = { [ds_1337] = 0, [ds_1339] = DS1339_BIT_BBSQI, [ds_3231] = DS3231_BIT_BBSQW, }; |
1abb0dc92
|
620 |
|
30e7b039b
|
621 622 |
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA) && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) |
c065f35c1
|
623 624 625 626 |
return -EIO; if (!(ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL))) return -ENOMEM; |
045e0e85f
|
627 |
|
1abb0dc92
|
628 |
i2c_set_clientdata(client, ds1307); |
33df2ee1b
|
629 630 631 632 |
ds1307->client = client; ds1307->type = id->driver_data; ds1307->offset = 0; |
fed40b734
|
633 |
buf = ds1307->regs; |
30e7b039b
|
634 635 636 637 638 639 640 |
if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) { ds1307->read_block_data = i2c_smbus_read_i2c_block_data; ds1307->write_block_data = i2c_smbus_write_i2c_block_data; } else { ds1307->read_block_data = ds1307_read_block_data; ds1307->write_block_data = ds1307_write_block_data; } |
045e0e85f
|
641 642 643 644 |
switch (ds1307->type) { case ds_1337: case ds_1339: |
97f902b7b
|
645 |
case ds_3231: |
cb49a5e9e
|
646 647 648 649 650 |
/* has IRQ? */ if (ds1307->client->irq > 0 && chip->alarm) { INIT_WORK(&ds1307->work, ds1307_work); want_irq = true; } |
be5f59f4b
|
651 |
/* get registers that the "rtc" read below won't read... */ |
30e7b039b
|
652 |
tmp = ds1307->read_block_data(ds1307->client, |
fed40b734
|
653 |
DS1337_REG_CONTROL, 2, buf); |
1abb0dc92
|
654 655 656 657 658 659 |
if (tmp != 2) { pr_debug("read error %d ", tmp); err = -EIO; goto exit_free; } |
be5f59f4b
|
660 661 |
/* oscillator off? turn it on, so clock can tick. */ if (ds1307->regs[0] & DS1337_BIT_nEOSC) |
cb49a5e9e
|
662 663 664 |
ds1307->regs[0] &= ~DS1337_BIT_nEOSC; /* Using IRQ? Disable the square wave and both alarms. |
97f902b7b
|
665 666 |
* For some variants, be sure alarms can trigger when we're * running on Vbackup (BBSQI/BBSQW) |
cb49a5e9e
|
667 668 |
*/ if (want_irq) { |
97f902b7b
|
669 670 |
ds1307->regs[0] |= DS1337_BIT_INTCN | bbsqi_bitpos[ds1307->type]; |
cb49a5e9e
|
671 672 673 674 675 |
ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE); } i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ds1307->regs[0]); |
be5f59f4b
|
676 677 678 679 680 681 682 |
/* oscillator fault? clear flag, and warn */ if (ds1307->regs[1] & DS1337_BIT_OSF) { i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, ds1307->regs[1] & ~DS1337_BIT_OSF); dev_warn(&client->dev, "SET TIME! "); |
1abb0dc92
|
683 |
} |
045e0e85f
|
684 |
break; |
a21668581
|
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 |
case rx_8025: tmp = i2c_smbus_read_i2c_block_data(ds1307->client, RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); if (tmp != 2) { pr_debug("read error %d ", tmp); err = -EIO; goto exit_free; } /* oscillator off? turn it on, so clock can tick. */ if (!(ds1307->regs[1] & RX8025_BIT_XST)) { ds1307->regs[1] |= RX8025_BIT_XST; i2c_smbus_write_byte_data(client, RX8025_REG_CTRL2 << 4 | 0x08, ds1307->regs[1]); dev_warn(&client->dev, "oscillator stop detected - SET TIME! "); } if (ds1307->regs[1] & RX8025_BIT_PON) { ds1307->regs[1] &= ~RX8025_BIT_PON; i2c_smbus_write_byte_data(client, RX8025_REG_CTRL2 << 4 | 0x08, ds1307->regs[1]); dev_warn(&client->dev, "power-on detected "); } if (ds1307->regs[1] & RX8025_BIT_VDET) { ds1307->regs[1] &= ~RX8025_BIT_VDET; i2c_smbus_write_byte_data(client, RX8025_REG_CTRL2 << 4 | 0x08, ds1307->regs[1]); dev_warn(&client->dev, "voltage drop detected "); } /* make sure we are running in 24hour mode */ if (!(ds1307->regs[0] & RX8025_BIT_2412)) { u8 hour; /* switch to 24 hour mode */ i2c_smbus_write_byte_data(client, RX8025_REG_CTRL1 << 4 | 0x08, ds1307->regs[0] | RX8025_BIT_2412); tmp = i2c_smbus_read_i2c_block_data(ds1307->client, RX8025_REG_CTRL1 << 4 | 0x08, 2, buf); if (tmp != 2) { pr_debug("read error %d ", tmp); err = -EIO; goto exit_free; } /* correct hour */ hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]); if (hour == 12) hour = 0; if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) hour += 12; i2c_smbus_write_byte_data(client, DS1307_REG_HOUR << 4 | 0x08, hour); } break; |
33df2ee1b
|
756 757 758 |
case ds_1388: ds1307->offset = 1; /* Seconds starts at 1 */ break; |
045e0e85f
|
759 760 761 |
default: break; } |
1abb0dc92
|
762 763 764 |
read_rtc: /* read RTC registers */ |
96fc3a45e
|
765 |
tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf); |
fed40b734
|
766 |
if (tmp != 8) { |
1abb0dc92
|
767 768 769 770 771 772 773 774 775 776 777 |
pr_debug("read error %d ", tmp); err = -EIO; goto exit_free; } /* minimal sanity checking; some chips (like DS1340) don't * specify the extra bits as must-be-zero, but there are * still a few values that are clearly out-of-range. */ tmp = ds1307->regs[DS1307_REG_SECS]; |
045e0e85f
|
778 779 |
switch (ds1307->type) { case ds_1307: |
045e0e85f
|
780 |
case m41t00: |
be5f59f4b
|
781 |
/* clock halted? turn it on, so clock can tick. */ |
045e0e85f
|
782 |
if (tmp & DS1307_BIT_CH) { |
be5f59f4b
|
783 784 785 |
i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); dev_warn(&client->dev, "SET TIME! "); |
045e0e85f
|
786 |
goto read_rtc; |
1abb0dc92
|
787 |
} |
045e0e85f
|
788 |
break; |
be5f59f4b
|
789 790 |
case ds_1338: /* clock halted? turn it on, so clock can tick. */ |
045e0e85f
|
791 |
if (tmp & DS1307_BIT_CH) |
be5f59f4b
|
792 793 794 795 796 |
i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); /* oscillator fault? clear flag, and warn */ if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) { i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL, |
bd16f9ebd
|
797 |
ds1307->regs[DS1307_REG_CONTROL] |
be5f59f4b
|
798 799 800 801 802 |
& ~DS1338_BIT_OSF); dev_warn(&client->dev, "SET TIME! "); goto read_rtc; } |
045e0e85f
|
803 |
break; |
fcd8db002
|
804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 |
case ds_1340: /* clock halted? turn it on, so clock can tick. */ if (tmp & DS1340_BIT_nEOSC) i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0); tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG); if (tmp < 0) { pr_debug("read error %d ", tmp); err = -EIO; goto exit_free; } /* oscillator fault? clear flag, and warn */ if (tmp & DS1340_BIT_OSF) { i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0); dev_warn(&client->dev, "SET TIME! "); } break; |
43fcb8155
|
824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 |
case mcp7941x: /* make sure that the backup battery is enabled */ if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) { i2c_smbus_write_byte_data(client, DS1307_REG_WDAY, ds1307->regs[DS1307_REG_WDAY] | MCP7941X_BIT_VBATEN); } /* clock halted? turn it on, so clock can tick. */ if (!(tmp & MCP7941X_BIT_ST)) { i2c_smbus_write_byte_data(client, DS1307_REG_SECS, MCP7941X_BIT_ST); dev_warn(&client->dev, "SET TIME! "); goto read_rtc; } break; |
a21668581
|
842 |
case rx_8025: |
c065f35c1
|
843 844 |
case ds_1337: case ds_1339: |
33df2ee1b
|
845 |
case ds_1388: |
97f902b7b
|
846 |
case ds_3231: |
045e0e85f
|
847 |
break; |
1abb0dc92
|
848 |
} |
045e0e85f
|
849 |
|
1abb0dc92
|
850 |
tmp = ds1307->regs[DS1307_REG_HOUR]; |
c065f35c1
|
851 852 853 854 855 856 857 |
switch (ds1307->type) { case ds_1340: case m41t00: /* NOTE: ignores century bits; fix before deploying * systems that will run through year 2100. */ break; |
a21668581
|
858 859 |
case rx_8025: break; |
c065f35c1
|
860 861 862 863 864 865 866 |
default: if (!(tmp & DS1307_BIT_12HR)) break; /* Be sure we're in 24 hour mode. Multi-master systems * take note... */ |
fe20ba70a
|
867 |
tmp = bcd2bin(tmp & 0x1f); |
c065f35c1
|
868 869 870 871 |
if (tmp == 12) tmp = 0; if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM) tmp += 12; |
1abb0dc92
|
872 |
i2c_smbus_write_byte_data(client, |
96fc3a45e
|
873 |
ds1307->offset + DS1307_REG_HOUR, |
fe20ba70a
|
874 |
bin2bcd(tmp)); |
1abb0dc92
|
875 |
} |
1abb0dc92
|
876 877 878 879 880 881 882 |
ds1307->rtc = rtc_device_register(client->name, &client->dev, &ds13xx_rtc_ops, THIS_MODULE); if (IS_ERR(ds1307->rtc)) { err = PTR_ERR(ds1307->rtc); dev_err(&client->dev, "unable to register the class device "); |
c065f35c1
|
883 |
goto exit_free; |
1abb0dc92
|
884 |
} |
cb49a5e9e
|
885 |
if (want_irq) { |
43d15bcd4
|
886 |
err = request_irq(client->irq, ds1307_irq, IRQF_SHARED, |
cb49a5e9e
|
887 888 889 890 891 892 893 |
ds1307->rtc->name, client); if (err) { dev_err(&client->dev, "unable to request IRQ! "); goto exit_irq; } |
26b3c01f7
|
894 895 |
device_set_wakeup_capable(&client->dev, 1); |
cb49a5e9e
|
896 897 898 899 |
set_bit(HAS_ALARM, &ds1307->flags); dev_dbg(&client->dev, "got IRQ %d ", client->irq); } |
682d73f68
|
900 901 902 |
if (chip->nvram56) { err = sysfs_create_bin_file(&client->dev.kobj, &nvram); if (err == 0) { |
cb49a5e9e
|
903 |
set_bit(HAS_NVRAM, &ds1307->flags); |
682d73f68
|
904 905 906 907 |
dev_info(&client->dev, "56 bytes nvram "); } } |
1abb0dc92
|
908 |
return 0; |
cb49a5e9e
|
909 |
exit_irq: |
72445af88
|
910 |
rtc_device_unregister(ds1307->rtc); |
1abb0dc92
|
911 912 |
exit_free: kfree(ds1307); |
1abb0dc92
|
913 914 |
return err; } |
c065f35c1
|
915 |
static int __devexit ds1307_remove(struct i2c_client *client) |
1abb0dc92
|
916 |
{ |
cb49a5e9e
|
917 918 919 920 921 922 |
struct ds1307 *ds1307 = i2c_get_clientdata(client); if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) { free_irq(client->irq, client); cancel_work_sync(&ds1307->work); } |
1abb0dc92
|
923 |
|
cb49a5e9e
|
924 |
if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) |
682d73f68
|
925 |
sysfs_remove_bin_file(&client->dev.kobj, &nvram); |
1abb0dc92
|
926 |
rtc_device_unregister(ds1307->rtc); |
1abb0dc92
|
927 928 929 930 931 932 |
kfree(ds1307); return 0; } static struct i2c_driver ds1307_driver = { .driver = { |
c065f35c1
|
933 |
.name = "rtc-ds1307", |
1abb0dc92
|
934 935 |
.owner = THIS_MODULE, }, |
c065f35c1
|
936 937 |
.probe = ds1307_probe, .remove = __devexit_p(ds1307_remove), |
3760f7367
|
938 |
.id_table = ds1307_id, |
1abb0dc92
|
939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 |
}; static int __init ds1307_init(void) { return i2c_add_driver(&ds1307_driver); } module_init(ds1307_init); static void __exit ds1307_exit(void) { i2c_del_driver(&ds1307_driver); } module_exit(ds1307_exit); MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips"); MODULE_LICENSE("GPL"); |