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arch/arm/mach-omap2/clock3xxx_data.c
110 KB
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/* * OMAP3 clock data * |
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* Copyright (C) 2007-2010 Texas Instruments, Inc. |
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* Copyright (C) 2007-2011 Nokia Corporation |
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* * Written by Paul Walmsley * With many device clock fixes by Kevin Hilman and Jouni Högander * DPLL bypass clock support added by Roman Tereshonkov * */ /* * Virtual clocks are introduced as convenient tools. * They are sources for other clocks and not supposed * to be requested from drivers directly. */ |
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#include <linux/kernel.h> #include <linux/clk.h> |
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#include <linux/list.h> |
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#include <plat/clkdev_omap.h> #include "clock.h" |
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#include "clock3xxx.h" |
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#include "clock34xx.h" |
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#include "clock36xx.h" #include "clock3517.h" |
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#include "cm2xxx_3xxx.h" |
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#include "cm-regbits-34xx.h" |
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#include "prm2xxx_3xxx.h" |
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#include "prm-regbits-34xx.h" |
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#include "control.h" |
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/* * clocks */ #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR /* Maximum DPLL multiplier, divider values for OMAP3 */ |
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#define OMAP3_MAX_DPLL_MULT 2047 |
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#define OMAP3630_MAX_JTYPE_DPLL_MULT 4095 |
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#define OMAP3_MAX_DPLL_DIV 128 /* * DPLL1 supplies clock to the MPU. * DPLL2 supplies clock to the IVA2. * DPLL3 supplies CORE domain clocks. * DPLL4 supplies peripheral clocks. * DPLL5 supplies other peripheral clocks (USBHOST, USIM). */ /* Forward declarations for DPLL bypass clocks */ static struct clk dpll1_fck; static struct clk dpll2_fck; /* PRM CLOCKS */ /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ static struct clk omap_32k_fck = { .name = "omap_32k_fck", .ops = &clkops_null, .rate = 32768, |
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}; static struct clk secure_32k_fck = { .name = "secure_32k_fck", .ops = &clkops_null, .rate = 32768, |
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}; /* Virtual source clocks for osc_sys_ck */ static struct clk virt_12m_ck = { .name = "virt_12m_ck", .ops = &clkops_null, .rate = 12000000, |
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}; static struct clk virt_13m_ck = { .name = "virt_13m_ck", .ops = &clkops_null, .rate = 13000000, |
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}; static struct clk virt_16_8m_ck = { .name = "virt_16_8m_ck", .ops = &clkops_null, .rate = 16800000, |
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}; static struct clk virt_19_2m_ck = { .name = "virt_19_2m_ck", .ops = &clkops_null, .rate = 19200000, |
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}; static struct clk virt_26m_ck = { .name = "virt_26m_ck", .ops = &clkops_null, .rate = 26000000, |
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}; static struct clk virt_38_4m_ck = { .name = "virt_38_4m_ck", .ops = &clkops_null, .rate = 38400000, |
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}; static const struct clksel_rate osc_sys_12m_rates[] = { |
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{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; static const struct clksel_rate osc_sys_13m_rates[] = { |
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{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; static const struct clksel_rate osc_sys_16_8m_rates[] = { |
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{ .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, |
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{ .div = 0 } }; static const struct clksel_rate osc_sys_19_2m_rates[] = { |
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{ .div = 1, .val = 2, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; static const struct clksel_rate osc_sys_26m_rates[] = { |
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{ .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; static const struct clksel_rate osc_sys_38_4m_rates[] = { |
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{ .div = 1, .val = 4, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; static const struct clksel osc_sys_clksel[] = { { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, { .parent = NULL }, }; /* Oscillator clock */ /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ static struct clk osc_sys_ck = { .name = "osc_sys_ck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP3430_PRM_CLKSEL, .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, .clksel = osc_sys_clksel, /* REVISIT: deal with autoextclkmode? */ |
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.recalc = &omap2_clksel_recalc, }; static const struct clksel_rate div2_rates[] = { |
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{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; static const struct clksel sys_clksel[] = { { .parent = &osc_sys_ck, .rates = div2_rates }, { .parent = NULL } }; /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ static struct clk sys_ck = { .name = "sys_ck", .ops = &clkops_null, .parent = &osc_sys_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, .clksel_mask = OMAP_SYSCLKDIV_MASK, .clksel = sys_clksel, .recalc = &omap2_clksel_recalc, }; static struct clk sys_altclk = { .name = "sys_altclk", .ops = &clkops_null, }; /* Optional external clock input for some McBSPs */ static struct clk mcbsp_clks = { .name = "mcbsp_clks", .ops = &clkops_null, }; /* PRM EXTERNAL CLOCK OUTPUT */ static struct clk sys_clkout1 = { .name = "sys_clkout1", .ops = &clkops_omap2_dflt, .parent = &osc_sys_ck, .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, .recalc = &followparent_recalc, }; /* DPLLS */ /* CM CLOCKS */ static const struct clksel_rate div16_dpll_rates[] = { |
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{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, |
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{ .div = 0 } }; |
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static const struct clksel_rate dpll4_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 5, .val = 5, .flags = RATE_IN_3XXX }, { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, { .div = 7, .val = 7, .flags = RATE_IN_3XXX }, { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, { .div = 9, .val = 9, .flags = RATE_IN_3XXX }, { .div = 10, .val = 10, .flags = RATE_IN_3XXX }, { .div = 11, .val = 11, .flags = RATE_IN_3XXX }, { .div = 12, .val = 12, .flags = RATE_IN_3XXX }, { .div = 13, .val = 13, .flags = RATE_IN_3XXX }, { .div = 14, .val = 14, .flags = RATE_IN_3XXX }, { .div = 15, .val = 15, .flags = RATE_IN_3XXX }, { .div = 16, .val = 16, .flags = RATE_IN_3XXX }, |
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{ .div = 17, .val = 17, .flags = RATE_IN_36XX }, { .div = 18, .val = 18, .flags = RATE_IN_36XX }, { .div = 19, .val = 19, .flags = RATE_IN_36XX }, { .div = 20, .val = 20, .flags = RATE_IN_36XX }, { .div = 21, .val = 21, .flags = RATE_IN_36XX }, { .div = 22, .val = 22, .flags = RATE_IN_36XX }, { .div = 23, .val = 23, .flags = RATE_IN_36XX }, { .div = 24, .val = 24, .flags = RATE_IN_36XX }, { .div = 25, .val = 25, .flags = RATE_IN_36XX }, { .div = 26, .val = 26, .flags = RATE_IN_36XX }, { .div = 27, .val = 27, .flags = RATE_IN_36XX }, { .div = 28, .val = 28, .flags = RATE_IN_36XX }, { .div = 29, .val = 29, .flags = RATE_IN_36XX }, { .div = 30, .val = 30, .flags = RATE_IN_36XX }, { .div = 31, .val = 31, .flags = RATE_IN_36XX }, { .div = 32, .val = 32, .flags = RATE_IN_36XX }, { .div = 0 } }; |
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/* DPLL1 */ /* MPU clock source */ /* Type: DPLL */ static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, .clk_bypass = &dpll1_fck, .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, |
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}; static struct clk dpll1_ck = { .name = "dpll1_ck", |
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.ops = &clkops_omap3_noncore_dpll_ops, |
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.parent = &sys_ck, .dpll_data = &dpll1_dd, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .clkdm_name = "dpll1_clkdm", .recalc = &omap3_dpll_recalc, }; /* * This virtual clock provides the CLKOUTX2 output from the DPLL if the * DPLL isn't bypassed. */ static struct clk dpll1_x2_ck = { .name = "dpll1_x2_ck", .ops = &clkops_null, .parent = &dpll1_ck, .clkdm_name = "dpll1_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ static const struct clksel div16_dpll1_x2m2_clksel[] = { { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, { .parent = NULL } }; /* * Does not exist in the TRM - needed to separate the M2 divider from * bypass selection in mpu_ck */ static struct clk dpll1_x2m2_ck = { .name = "dpll1_x2m2_ck", .ops = &clkops_null, .parent = &dpll1_x2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll1_x2m2_clksel, .clkdm_name = "dpll1_clkdm", .recalc = &omap2_clksel_recalc, }; /* DPLL2 */ /* IVA2 clock source */ /* Type: DPLL */ static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, .clk_bypass = &dpll2_fck, .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | (1 << DPLL_LOW_POWER_BYPASS), .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, |
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}; static struct clk dpll2_ck = { .name = "dpll2_ck", |
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.ops = &clkops_omap3_noncore_dpll_ops, |
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.parent = &sys_ck, .dpll_data = &dpll2_dd, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .clkdm_name = "dpll2_clkdm", .recalc = &omap3_dpll_recalc, }; static const struct clksel div16_dpll2_m2x2_clksel[] = { { .parent = &dpll2_ck, .rates = div16_dpll_rates }, { .parent = NULL } }; /* * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT * or CLKOUTX2. CLKOUT seems most plausible. */ static struct clk dpll2_m2_ck = { .name = "dpll2_m2_ck", .ops = &clkops_null, .parent = &dpll2_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL), .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, .clksel = div16_dpll2_m2x2_clksel, .clkdm_name = "dpll2_clkdm", .recalc = &omap2_clksel_recalc, }; /* * DPLL3 * Source clock for all interfaces and for some device fclks * REVISIT: Also supports fast relock bypass - not included below */ static struct dpll_data dpll3_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, .clk_bypass = &sys_ck, .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, |
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}; static struct clk dpll3_ck = { .name = "dpll3_ck", |
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.ops = &clkops_omap3_core_dpll_ops, |
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.parent = &sys_ck, .dpll_data = &dpll3_dd, .round_rate = &omap2_dpll_round_rate, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_dpll_recalc, }; /* * This virtual clock provides the CLKOUTX2 output from the DPLL if the * DPLL isn't bypassed */ static struct clk dpll3_x2_ck = { .name = "dpll3_x2_ck", .ops = &clkops_null, .parent = &dpll3_ck, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; static const struct clksel_rate div31_dpll3_rates[] = { |
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{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, |
553d239aa OMAP3: clock: cla... |
448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 |
{ .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX }, { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX }, |
82e9bd588 OMAP3 clock: conv... |
477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 |
{ .div = 0 }, }; static const struct clksel div31_dpll3m2_clksel[] = { { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, { .parent = NULL } }; /* DPLL3 output M2 - primary control point for CORE speed */ static struct clk dpll3_m2_ck = { .name = "dpll3_m2_ck", .ops = &clkops_null, .parent = &dpll3_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, .clksel = div31_dpll3m2_clksel, .clkdm_name = "dpll3_clkdm", .round_rate = &omap2_clksel_round_rate, .set_rate = &omap3_core_dpll_m2_set_rate, .recalc = &omap2_clksel_recalc, }; static struct clk core_ck = { .name = "core_ck", .ops = &clkops_null, .parent = &dpll3_m2_ck, .recalc = &followparent_recalc, }; static struct clk dpll3_m2x2_ck = { .name = "dpll3_m2x2_ck", .ops = &clkops_null, .parent = &dpll3_m2_ck, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static const struct clksel div16_dpll3_clksel[] = { { .parent = &dpll3_ck, .rates = div16_dpll_rates }, { .parent = NULL } }; /* This virtual clock is the source for dpll3_m3x2_ck */ static struct clk dpll3_m3_ck = { .name = "dpll3_m3_ck", .ops = &clkops_null, .parent = &dpll3_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL3_MASK, .clksel = div16_dpll3_clksel, .clkdm_name = "dpll3_clkdm", .recalc = &omap2_clksel_recalc, }; /* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll3_m3x2_ck = { .name = "dpll3_m3x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll3_m3_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, .flags = INVERT_ENABLE, .clkdm_name = "dpll3_clkdm", .recalc = &omap3_clkoutx2_recalc, }; static struct clk emu_core_alwon_ck = { .name = "emu_core_alwon_ck", .ops = &clkops_null, .parent = &dpll3_m3x2_ck, .clkdm_name = "dpll3_clkdm", .recalc = &followparent_recalc, }; /* DPLL4 */ /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ /* Type: DPLL */ |
358965d7b OMAP3 clock: intr... |
557 |
static struct dpll_data dpll4_dd; |
2a9f5a4d4 OMAP3 clock: remo... |
558 |
|
358965d7b OMAP3 clock: intr... |
559 |
static struct dpll_data dpll4_dd_34xx __initdata = { |
82e9bd588 OMAP3 clock: conv... |
560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 |
.mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, .clk_bypass = &sys_ck, .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, |
82e9bd588 OMAP3 clock: conv... |
579 |
}; |
358965d7b OMAP3 clock: intr... |
580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 |
static struct dpll_data dpll4_dd_3630 __initdata = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK, .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, .clk_bypass = &sys_ck, .clk_ref = &sys_ck, .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
a36795c12 OMAP: clock: fix ... |
596 597 |
.dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK, .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK, |
358965d7b OMAP3 clock: intr... |
598 599 600 |
.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, |
358965d7b OMAP3 clock: intr... |
601 602 |
.flags = DPLL_J_TYPE }; |
82e9bd588 OMAP3 clock: conv... |
603 604 |
static struct clk dpll4_ck = { .name = "dpll4_ck", |
657ebfadc OMAP3/4 clock: sp... |
605 |
.ops = &clkops_omap3_noncore_dpll_ops, |
82e9bd588 OMAP3 clock: conv... |
606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 |
.parent = &sys_ck, .dpll_data = &dpll4_dd, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_dpll4_set_rate, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_dpll_recalc, }; /* * This virtual clock provides the CLKOUTX2 output from the DPLL if the * DPLL isn't bypassed -- * XXX does this serve any downstream clocks? */ static struct clk dpll4_x2_ck = { .name = "dpll4_x2_ck", .ops = &clkops_null, .parent = &dpll4_ck, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; |
2a9f5a4d4 OMAP3 clock: remo... |
626 627 |
static const struct clksel dpll4_clksel[] = { { .parent = &dpll4_ck, .rates = dpll4_rates }, |
678bc9a2e OMAP3 clock: Intr... |
628 629 |
{ .parent = NULL } }; |
82e9bd588 OMAP3 clock: conv... |
630 |
/* This virtual clock is the source for dpll4_m2x2_ck */ |
2a9f5a4d4 OMAP3 clock: remo... |
631 |
static struct clk dpll4_m2_ck = { |
678bc9a2e OMAP3 clock: Intr... |
632 633 634 635 636 637 |
.name = "dpll4_m2_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), .clksel_mask = OMAP3630_DIV_96M_MASK, |
2a9f5a4d4 OMAP3 clock: remo... |
638 |
.clksel = dpll4_clksel, |
678bc9a2e OMAP3 clock: Intr... |
639 640 641 |
.clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 |
/* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m2x2_ck = { .name = "dpll4_m2x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m2_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_96M_SHIFT, .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and * CM_96K_(F)CLK. */ |
7356f0b26 OMAP3 clock: add ... |
660 661 662 663 |
/* Adding 192MHz Clock node needed by SGX */ static struct clk omap_192m_alwon_fck = { .name = "omap_192m_alwon_fck", |
82e9bd588 OMAP3 clock: conv... |
664 665 666 667 |
.ops = &clkops_null, .parent = &dpll4_m2x2_ck, .recalc = &followparent_recalc, }; |
7356f0b26 OMAP3 clock: add ... |
668 669 |
static const struct clksel_rate omap_96m_alwon_fck_rates[] = { { .div = 1, .val = 1, .flags = RATE_IN_36XX }, |
d74b49497 OMAP2+ clock: rem... |
670 |
{ .div = 2, .val = 2, .flags = RATE_IN_36XX }, |
7356f0b26 OMAP3 clock: add ... |
671 672 673 674 675 676 |
{ .div = 0 } }; static const struct clksel omap_96m_alwon_fck_clksel[] = { { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates }, { .parent = NULL } |
82e9bd588 OMAP3 clock: conv... |
677 678 679 |
}; static const struct clksel_rate omap_96m_dpll_rates[] = { |
63405360f OMAP3 clock: rena... |
680 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
681 682 683 684 |
{ .div = 0 } }; static const struct clksel_rate omap_96m_sys_rates[] = { |
63405360f OMAP3 clock: rena... |
685 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
686 687 |
{ .div = 0 } }; |
7356f0b26 OMAP3 clock: add ... |
688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 |
static struct clk omap_96m_alwon_fck = { .name = "omap_96m_alwon_fck", .ops = &clkops_null, .parent = &dpll4_m2x2_ck, .recalc = &followparent_recalc, }; static struct clk omap_96m_alwon_fck_3630 = { .name = "omap_96m_alwon_fck", .parent = &omap_192m_alwon_fck, .init = &omap2_init_clksel_parent, .ops = &clkops_null, .recalc = &omap2_clksel_recalc, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3630_CLKSEL_96M_MASK, .clksel = omap_96m_alwon_fck_clksel }; static struct clk cm_96m_fck = { .name = "cm_96m_fck", .ops = &clkops_null, .parent = &omap_96m_alwon_fck, .recalc = &followparent_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 |
static const struct clksel omap_96m_fck_clksel[] = { { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, { .parent = &sys_ck, .rates = omap_96m_sys_rates }, { .parent = NULL } }; static struct clk omap_96m_fck = { .name = "omap_96m_fck", .ops = &clkops_null, .parent = &sys_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_96M_MASK, .clksel = omap_96m_fck_clksel, .recalc = &omap2_clksel_recalc, }; /* This virtual clock is the source for dpll4_m3x2_ck */ |
2a9f5a4d4 OMAP3 clock: remo... |
730 |
static struct clk dpll4_m3_ck = { |
82e9bd588 OMAP3 clock: conv... |
731 732 733 734 735 736 |
.name = "dpll4_m3_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_TV_MASK, |
2a9f5a4d4 OMAP3 clock: remo... |
737 |
.clksel = dpll4_clksel, |
678bc9a2e OMAP3 clock: Intr... |
738 739 740 |
.clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
741 742 743 744 745 |
/* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m3x2_ck = { .name = "dpll4_m3x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m3_ck, |
82e9bd588 OMAP3 clock: conv... |
746 747 748 749 750 751 752 753 |
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
63405360f OMAP3 clock: rena... |
754 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
755 756 757 758 |
{ .div = 0 } }; static const struct clksel_rate omap_54m_alt_rates[] = { |
63405360f OMAP3 clock: rena... |
759 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 |
{ .div = 0 } }; static const struct clksel omap_54m_clksel[] = { { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, { .parent = NULL } }; static struct clk omap_54m_fck = { .name = "omap_54m_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_54M_MASK, .clksel = omap_54m_clksel, .recalc = &omap2_clksel_recalc, }; static const struct clksel_rate omap_48m_cm96m_rates[] = { |
63405360f OMAP3 clock: rena... |
780 |
{ .div = 2, .val = 0, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
781 782 783 784 |
{ .div = 0 } }; static const struct clksel_rate omap_48m_alt_rates[] = { |
63405360f OMAP3 clock: rena... |
785 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 |
{ .div = 0 } }; static const struct clksel omap_48m_clksel[] = { { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, { .parent = NULL } }; static struct clk omap_48m_fck = { .name = "omap_48m_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_SOURCE_48M_MASK, .clksel = omap_48m_clksel, .recalc = &omap2_clksel_recalc, }; static struct clk omap_12m_fck = { .name = "omap_12m_fck", .ops = &clkops_null, .parent = &omap_48m_fck, .fixed_div = 4, |
e9b98f604 OMAP clock: make ... |
810 |
.recalc = &omap_fixed_divisor_recalc, |
82e9bd588 OMAP3 clock: conv... |
811 |
}; |
2a9f5a4d4 OMAP3 clock: remo... |
812 813 |
/* This virtual clock is the source for dpll4_m4x2_ck */ static struct clk dpll4_m4_ck = { |
82e9bd588 OMAP3 clock: conv... |
814 815 816 817 818 819 |
.name = "dpll4_m4_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, |
2a9f5a4d4 OMAP3 clock: remo... |
820 |
.clksel = dpll4_clksel, |
678bc9a2e OMAP3 clock: Intr... |
821 822 823 824 825 |
.clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, .set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate, }; |
82e9bd588 OMAP3 clock: conv... |
826 827 828 829 830 831 |
/* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m4x2_ck = { .name = "dpll4_m4x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m4_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
d54a45e25 OMAP3: clock: fix... |
832 |
.enable_bit = OMAP3430_PWRDN_DSS1_SHIFT, |
82e9bd588 OMAP3 clock: conv... |
833 834 835 836 837 838 |
.flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* This virtual clock is the source for dpll4_m5x2_ck */ |
2a9f5a4d4 OMAP3 clock: remo... |
839 |
static struct clk dpll4_m5_ck = { |
82e9bd588 OMAP3 clock: conv... |
840 841 842 843 844 845 |
.name = "dpll4_m5_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, |
2a9f5a4d4 OMAP3 clock: remo... |
846 |
.clksel = dpll4_clksel, |
678bc9a2e OMAP3 clock: Intr... |
847 |
.clkdm_name = "dpll4_clkdm", |
e8d373779 OMAP3: clock: add... |
848 849 |
.set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate, |
678bc9a2e OMAP3 clock: Intr... |
850 851 |
.recalc = &omap2_clksel_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
852 853 854 855 856 857 858 859 860 861 862 863 864 |
/* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m5x2_ck = { .name = "dpll4_m5x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m5_ck, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; /* This virtual clock is the source for dpll4_m6x2_ck */ |
2a9f5a4d4 OMAP3 clock: remo... |
865 |
static struct clk dpll4_m6_ck = { |
82e9bd588 OMAP3 clock: conv... |
866 867 868 869 870 871 |
.name = "dpll4_m6_ck", .ops = &clkops_null, .parent = &dpll4_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_DIV_DPLL4_MASK, |
2a9f5a4d4 OMAP3 clock: remo... |
872 |
.clksel = dpll4_clksel, |
678bc9a2e OMAP3 clock: Intr... |
873 874 875 |
.clkdm_name = "dpll4_clkdm", .recalc = &omap2_clksel_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
876 877 878 879 880 |
/* The PWRDN bit is apparently only available on 3430ES2 and above */ static struct clk dpll4_m6x2_ck = { .name = "dpll4_m6x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m6_ck, |
82e9bd588 OMAP3 clock: conv... |
881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 |
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, .flags = INVERT_ENABLE, .clkdm_name = "dpll4_clkdm", .recalc = &omap3_clkoutx2_recalc, }; static struct clk emu_per_alwon_ck = { .name = "emu_per_alwon_ck", .ops = &clkops_null, .parent = &dpll4_m6x2_ck, .clkdm_name = "dpll4_clkdm", .recalc = &followparent_recalc, }; /* DPLL5 */ /* Supplies 120MHz clock, USIM source clock */ /* Type: DPLL */ /* 3430ES2 only */ static struct dpll_data dpll5_dd = { .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, .clk_bypass = &sys_ck, .clk_ref = &sys_ck, .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, .max_multiplier = OMAP3_MAX_DPLL_MULT, .min_divider = 1, .max_divider = OMAP3_MAX_DPLL_DIV, |
82e9bd588 OMAP3 clock: conv... |
920 921 922 923 |
}; static struct clk dpll5_ck = { .name = "dpll5_ck", |
657ebfadc OMAP3/4 clock: sp... |
924 |
.ops = &clkops_omap3_noncore_dpll_ops, |
82e9bd588 OMAP3 clock: conv... |
925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 |
.parent = &sys_ck, .dpll_data = &dpll5_dd, .round_rate = &omap2_dpll_round_rate, .set_rate = &omap3_noncore_dpll_set_rate, .clkdm_name = "dpll5_clkdm", .recalc = &omap3_dpll_recalc, }; static const struct clksel div16_dpll5_clksel[] = { { .parent = &dpll5_ck, .rates = div16_dpll_rates }, { .parent = NULL } }; static struct clk dpll5_m2_ck = { .name = "dpll5_m2_ck", .ops = &clkops_null, .parent = &dpll5_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), .clksel_mask = OMAP3430ES2_DIV_120M_MASK, .clksel = div16_dpll5_clksel, .clkdm_name = "dpll5_clkdm", .recalc = &omap2_clksel_recalc, }; /* CM EXTERNAL CLOCK OUTPUTS */ static const struct clksel_rate clkout2_src_core_rates[] = { |
63405360f OMAP3 clock: rena... |
953 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
954 955 956 957 |
{ .div = 0 } }; static const struct clksel_rate clkout2_src_sys_rates[] = { |
63405360f OMAP3 clock: rena... |
958 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
959 960 961 962 |
{ .div = 0 } }; static const struct clksel_rate clkout2_src_96m_rates[] = { |
63405360f OMAP3 clock: rena... |
963 |
{ .div = 1, .val = 2, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
964 965 966 967 |
{ .div = 0 } }; static const struct clksel_rate clkout2_src_54m_rates[] = { |
63405360f OMAP3 clock: rena... |
968 |
{ .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 |
{ .div = 0 } }; static const struct clksel clkout2_src_clksel[] = { { .parent = &core_ck, .rates = clkout2_src_core_rates }, { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, { .parent = NULL } }; static struct clk clkout2_src_ck = { .name = "clkout2_src_ck", .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, .enable_reg = OMAP3430_CM_CLKOUT_CTRL, .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, .clksel = clkout2_src_clksel, .clkdm_name = "core_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel_rate sys_clkout2_rates[] = { |
63405360f OMAP3 clock: rena... |
994 995 996 997 998 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, { .div = 4, .val = 2, .flags = RATE_IN_3XXX }, { .div = 8, .val = 3, .flags = RATE_IN_3XXX }, { .div = 16, .val = 4, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 |
{ .div = 0 }, }; static const struct clksel sys_clkout2_clksel[] = { { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, { .parent = NULL }, }; static struct clk sys_clkout2 = { .name = "sys_clkout2", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, .clksel = sys_clkout2_clksel, .recalc = &omap2_clksel_recalc, |
71ee297a9 OMAP3 clock: add ... |
1015 1016 |
.round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate |
82e9bd588 OMAP3 clock: conv... |
1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 |
}; /* CM OUTPUT CLOCKS */ static struct clk corex2_fck = { .name = "corex2_fck", .ops = &clkops_null, .parent = &dpll3_m2x2_ck, .recalc = &followparent_recalc, }; /* DPLL power domain clock controls */ static const struct clksel_rate div4_rates[] = { |
63405360f OMAP3 clock: rena... |
1031 1032 1033 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 |
{ .div = 0 } }; static const struct clksel div4_core_clksel[] = { { .parent = &core_ck, .rates = div4_rates }, { .parent = NULL } }; /* * REVISIT: Are these in DPLL power domain or CM power domain? docs * may be inconsistent here? */ static struct clk dpll1_fck = { .name = "dpll1_fck", .ops = &clkops_null, .parent = &core_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, .clksel = div4_core_clksel, .recalc = &omap2_clksel_recalc, }; static struct clk mpu_ck = { .name = "mpu_ck", .ops = &clkops_null, .parent = &dpll1_x2m2_ck, .clkdm_name = "mpu_clkdm", .recalc = &followparent_recalc, }; /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ static const struct clksel_rate arm_fck_rates[] = { |
63405360f OMAP3 clock: rena... |
1067 1068 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, { .div = 2, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 |
{ .div = 0 }, }; static const struct clksel arm_fck_clksel[] = { { .parent = &mpu_ck, .rates = arm_fck_rates }, { .parent = NULL } }; static struct clk arm_fck = { .name = "arm_fck", .ops = &clkops_null, .parent = &mpu_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, .clksel = arm_fck_clksel, .clkdm_name = "mpu_clkdm", .recalc = &omap2_clksel_recalc, }; /* XXX What about neon_clkdm ? */ /* * REVISIT: This clock is never specifically defined in the 3430 TRM, * although it is referenced - so this is a guess */ static struct clk emu_mpu_alwon_ck = { .name = "emu_mpu_alwon_ck", .ops = &clkops_null, .parent = &mpu_ck, .recalc = &followparent_recalc, }; static struct clk dpll2_fck = { .name = "dpll2_fck", .ops = &clkops_null, .parent = &core_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, .clksel = div4_core_clksel, .recalc = &omap2_clksel_recalc, }; static struct clk iva2_ck = { .name = "iva2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll2_m2_ck, |
82e9bd588 OMAP3 clock: conv... |
1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 |
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, .clkdm_name = "iva2_clkdm", .recalc = &followparent_recalc, }; /* Common interface clocks */ static const struct clksel div2_core_clksel[] = { { .parent = &core_ck, .rates = div2_rates }, { .parent = NULL } }; static struct clk l3_ick = { .name = "l3_ick", .ops = &clkops_null, .parent = &core_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L3_MASK, .clksel = div2_core_clksel, .clkdm_name = "core_l3_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel div2_l3_clksel[] = { { .parent = &l3_ick, .rates = div2_rates }, { .parent = NULL } }; static struct clk l4_ick = { .name = "l4_ick", .ops = &clkops_null, .parent = &l3_ick, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_L4_MASK, .clksel = div2_l3_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel div2_l4_clksel[] = { { .parent = &l4_ick, .rates = div2_rates }, { .parent = NULL } }; static struct clk rm_ick = { .name = "rm_ick", .ops = &clkops_null, .parent = &l4_ick, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_RM_MASK, .clksel = div2_l4_clksel, .recalc = &omap2_clksel_recalc, }; /* GFX power domain */ /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ static const struct clksel gfx_l3_clksel[] = { { .parent = &l3_ick, .rates = gfx_l3_rates }, { .parent = NULL } }; |
ec538e30f OMAP3: clock: use... |
1184 1185 1186 1187 |
/* * Virtual parent clock for gfx_l3_ick and gfx_l3_fck * This interface clock does not have a CM_AUTOIDLE bit */ |
82e9bd588 OMAP3 clock: conv... |
1188 1189 1190 1191 |
static struct clk gfx_l3_ck = { .name = "gfx_l3_ck", .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, |
82e9bd588 OMAP3 clock: conv... |
1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 |
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, .recalc = &followparent_recalc, }; static struct clk gfx_l3_fck = { .name = "gfx_l3_fck", .ops = &clkops_null, .parent = &gfx_l3_ck, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), .clksel_mask = OMAP_CLKSEL_GFX_MASK, .clksel = gfx_l3_clksel, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gfx_l3_ick = { .name = "gfx_l3_ick", .ops = &clkops_null, .parent = &gfx_l3_ck, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; static struct clk gfx_cg1_ck = { .name = "gfx_cg1_ck", .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_2D_SHIFT, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; static struct clk gfx_cg2_ck = { .name = "gfx_cg2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &gfx_l3_fck, /* REVISIT: correct? */ .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES1_EN_3D_SHIFT, .clkdm_name = "gfx_3430es1_clkdm", .recalc = &followparent_recalc, }; /* SGX power domain - 3430ES2 only */ static const struct clksel_rate sgx_core_rates[] = { |
7356f0b26 OMAP3 clock: add ... |
1240 |
{ .div = 2, .val = 5, .flags = RATE_IN_36XX }, |
63405360f OMAP3 clock: rena... |
1241 1242 1243 |
{ .div = 3, .val = 0, .flags = RATE_IN_3XXX }, { .div = 4, .val = 1, .flags = RATE_IN_3XXX }, { .div = 6, .val = 2, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1244 1245 |
{ .div = 0 }, }; |
7356f0b26 OMAP3 clock: add ... |
1246 |
static const struct clksel_rate sgx_192m_rates[] = { |
d74b49497 OMAP2+ clock: rem... |
1247 |
{ .div = 1, .val = 4, .flags = RATE_IN_36XX }, |
7356f0b26 OMAP3 clock: add ... |
1248 1249 1250 1251 |
{ .div = 0 }, }; static const struct clksel_rate sgx_corex2_rates[] = { |
d74b49497 OMAP2+ clock: rem... |
1252 |
{ .div = 3, .val = 6, .flags = RATE_IN_36XX }, |
7356f0b26 OMAP3 clock: add ... |
1253 1254 1255 |
{ .div = 5, .val = 7, .flags = RATE_IN_36XX }, { .div = 0 }, }; |
82e9bd588 OMAP3 clock: conv... |
1256 |
static const struct clksel_rate sgx_96m_rates[] = { |
63405360f OMAP3 clock: rena... |
1257 |
{ .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1258 1259 1260 1261 1262 1263 |
{ .div = 0 }, }; static const struct clksel sgx_clksel[] = { { .parent = &core_ck, .rates = sgx_core_rates }, { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
7356f0b26 OMAP3 clock: add ... |
1264 1265 1266 |
{ .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates }, { .parent = &corex2_fck, .rates = sgx_corex2_rates }, { .parent = NULL } |
82e9bd588 OMAP3 clock: conv... |
1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 |
}; static struct clk sgx_fck = { .name = "sgx_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, .clksel = sgx_clksel, .clkdm_name = "sgx_clkdm", .recalc = &omap2_clksel_recalc, |
7356f0b26 OMAP3 clock: add ... |
1280 1281 |
.set_rate = &omap2_clksel_set_rate, .round_rate = &omap2_clksel_round_rate |
82e9bd588 OMAP3 clock: conv... |
1282 |
}; |
ec538e30f OMAP3: clock: use... |
1283 |
/* This interface clock does not have a CM_AUTOIDLE bit */ |
82e9bd588 OMAP3 clock: conv... |
1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 |
static struct clk sgx_ick = { .name = "sgx_ick", .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, .clkdm_name = "sgx_clkdm", .recalc = &followparent_recalc, }; /* CORE power domain */ static struct clk d2d_26m_fck = { .name = "d2d_26m_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, .clkdm_name = "d2d_clkdm", .recalc = &followparent_recalc, }; static struct clk modem_fck = { .name = "modem_fck", |
ec538e30f OMAP3: clock: use... |
1308 |
.ops = &clkops_omap2_mdmclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1309 1310 1311 1312 1313 1314 1315 1316 1317 |
.parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MODEM_SHIFT, .clkdm_name = "d2d_clkdm", .recalc = &followparent_recalc, }; static struct clk sad2d_ick = { .name = "sad2d_ick", |
ec538e30f OMAP3: clock: use... |
1318 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1319 1320 1321 1322 1323 1324 1325 1326 1327 |
.parent = &l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SAD2D_SHIFT, .clkdm_name = "d2d_clkdm", .recalc = &followparent_recalc, }; static struct clk mad2d_ick = { .name = "mad2d_ick", |
ec538e30f OMAP3: clock: use... |
1328 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 |
.parent = &l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430_EN_MAD2D_SHIFT, .clkdm_name = "d2d_clkdm", .recalc = &followparent_recalc, }; static const struct clksel omap343x_gpt_clksel[] = { { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, { .parent = &sys_ck, .rates = gpt_sys_rates }, { .parent = NULL} }; static struct clk gpt10_fck = { .name = "gpt10_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt11_fck = { .name = "gpt11_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk cpefuse_fck = { .name = "cpefuse_fck", .ops = &clkops_omap2_dflt, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, .recalc = &followparent_recalc, }; static struct clk ts_fck = { .name = "ts_fck", .ops = &clkops_omap2_dflt, .parent = &omap_32k_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_TS_SHIFT, .recalc = &followparent_recalc, }; static struct clk usbtll_fck = { .name = "usbtll_fck", |
25499d935 OMAP3: wait on ID... |
1390 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 |
.parent = &dpll5_m2_ck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .recalc = &followparent_recalc, }; /* CORE 96M FCLK-derived clocks */ static struct clk core_96m_fck = { .name = "core_96m_fck", .ops = &clkops_null, .parent = &omap_96m_fck, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs3_fck = { |
b92c170d0 OMAP clock: drop ... |
1408 |
.name = "mmchs3_fck", |
82e9bd588 OMAP3 clock: conv... |
1409 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1410 1411 1412 1413 1414 1415 1416 1417 |
.parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs2_fck = { |
b92c170d0 OMAP clock: drop ... |
1418 |
.name = "mmchs2_fck", |
82e9bd588 OMAP3 clock: conv... |
1419 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 |
.parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mspro_fck = { .name = "mspro_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs1_fck = { |
b92c170d0 OMAP clock: drop ... |
1438 |
.name = "mmchs1_fck", |
82e9bd588 OMAP3 clock: conv... |
1439 1440 1441 1442 1443 1444 1445 1446 1447 |
.ops = &clkops_omap2_dflt_wait, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c3_fck = { |
b92c170d0 OMAP clock: drop ... |
1448 |
.name = "i2c3_fck", |
82e9bd588 OMAP3 clock: conv... |
1449 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1450 1451 1452 1453 1454 1455 1456 1457 |
.parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c2_fck = { |
b92c170d0 OMAP clock: drop ... |
1458 |
.name = "i2c2_fck", |
82e9bd588 OMAP3 clock: conv... |
1459 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1460 1461 1462 1463 1464 1465 1466 1467 |
.parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c1_fck = { |
b92c170d0 OMAP clock: drop ... |
1468 |
.name = "i2c1_fck", |
82e9bd588 OMAP3 clock: conv... |
1469 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 |
.parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; /* * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. */ static const struct clksel_rate common_mcbsp_96m_rates[] = { |
63405360f OMAP3 clock: rena... |
1482 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1483 1484 1485 1486 |
{ .div = 0 } }; static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { |
63405360f OMAP3 clock: rena... |
1487 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 |
{ .div = 0 } }; static const struct clksel mcbsp_15_clksel[] = { { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, { .parent = NULL } }; static struct clk mcbsp5_fck = { |
b92c170d0 OMAP clock: drop ... |
1498 |
.name = "mcbsp5_fck", |
82e9bd588 OMAP3 clock: conv... |
1499 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 |
.init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, .clksel = mcbsp_15_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp1_fck = { |
b92c170d0 OMAP clock: drop ... |
1511 |
.name = "mcbsp1_fck", |
82e9bd588 OMAP3 clock: conv... |
1512 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 |
.init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, .clksel = mcbsp_15_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; /* CORE_48M_FCK-derived clocks */ static struct clk core_48m_fck = { .name = "core_48m_fck", .ops = &clkops_null, .parent = &omap_48m_fck, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi4_fck = { |
b92c170d0 OMAP clock: drop ... |
1534 |
.name = "mcspi4_fck", |
82e9bd588 OMAP3 clock: conv... |
1535 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1536 1537 1538 1539 |
.parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .recalc = &followparent_recalc, |
b183aaf72 OMAP3: clock: Upd... |
1540 |
.clkdm_name = "core_l4_clkdm", |
82e9bd588 OMAP3 clock: conv... |
1541 1542 1543 |
}; static struct clk mcspi3_fck = { |
b92c170d0 OMAP clock: drop ... |
1544 |
.name = "mcspi3_fck", |
82e9bd588 OMAP3 clock: conv... |
1545 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1546 1547 1548 1549 |
.parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .recalc = &followparent_recalc, |
b183aaf72 OMAP3: clock: Upd... |
1550 |
.clkdm_name = "core_l4_clkdm", |
82e9bd588 OMAP3 clock: conv... |
1551 1552 1553 |
}; static struct clk mcspi2_fck = { |
b92c170d0 OMAP clock: drop ... |
1554 |
.name = "mcspi2_fck", |
82e9bd588 OMAP3 clock: conv... |
1555 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1556 1557 1558 1559 |
.parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .recalc = &followparent_recalc, |
b183aaf72 OMAP3: clock: Upd... |
1560 |
.clkdm_name = "core_l4_clkdm", |
82e9bd588 OMAP3 clock: conv... |
1561 1562 1563 |
}; static struct clk mcspi1_fck = { |
b92c170d0 OMAP clock: drop ... |
1564 |
.name = "mcspi1_fck", |
82e9bd588 OMAP3 clock: conv... |
1565 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1566 1567 1568 1569 |
.parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .recalc = &followparent_recalc, |
b183aaf72 OMAP3: clock: Upd... |
1570 |
.clkdm_name = "core_l4_clkdm", |
82e9bd588 OMAP3 clock: conv... |
1571 1572 1573 1574 1575 1576 1577 1578 |
}; static struct clk uart2_fck = { .name = "uart2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, |
9b5bc5fa4 OMAP3: clock: add... |
1579 |
.clkdm_name = "core_l4_clkdm", |
82e9bd588 OMAP3 clock: conv... |
1580 1581 1582 1583 1584 1585 1586 1587 1588 |
.recalc = &followparent_recalc, }; static struct clk uart1_fck = { .name = "uart1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, |
9b5bc5fa4 OMAP3: clock: add... |
1589 |
.clkdm_name = "core_l4_clkdm", |
82e9bd588 OMAP3 clock: conv... |
1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 |
.recalc = &followparent_recalc, }; static struct clk fshostusb_fck = { .name = "fshostusb_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, .recalc = &followparent_recalc, }; /* CORE_12M_FCK based clocks */ static struct clk core_12m_fck = { .name = "core_12m_fck", .ops = &clkops_null, .parent = &omap_12m_fck, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk hdq_fck = { .name = "hdq_fck", .ops = &clkops_omap2_dflt_wait, .parent = &core_12m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, .recalc = &followparent_recalc, }; /* DPLL3-derived clock */ static const struct clksel_rate ssi_ssr_corex2_rates[] = { |
63405360f OMAP3 clock: rena... |
1624 1625 1626 1627 1628 1629 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 |
{ .div = 0 } }; static const struct clksel ssi_ssr_clksel[] = { { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, { .parent = NULL } }; static struct clk ssi_ssr_fck_3430es1 = { .name = "ssi_ssr_fck", .ops = &clkops_omap2_dflt, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk ssi_ssr_fck_3430es2 = { .name = "ssi_ssr_fck", .ops = &clkops_omap3430es2_ssi_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, .clksel = ssi_ssr_clksel, .clkdm_name = "core_l4_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk ssi_sst_fck_3430es1 = { .name = "ssi_sst_fck", .ops = &clkops_null, .parent = &ssi_ssr_fck_3430es1, .fixed_div = 2, |
e9b98f604 OMAP clock: make ... |
1669 |
.recalc = &omap_fixed_divisor_recalc, |
82e9bd588 OMAP3 clock: conv... |
1670 1671 1672 1673 1674 1675 1676 |
}; static struct clk ssi_sst_fck_3430es2 = { .name = "ssi_sst_fck", .ops = &clkops_null, .parent = &ssi_ssr_fck_3430es2, .fixed_div = 2, |
e9b98f604 OMAP clock: make ... |
1677 |
.recalc = &omap_fixed_divisor_recalc, |
82e9bd588 OMAP3 clock: conv... |
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 |
}; /* CORE_L3_ICK based clocks */ /* * XXX must add clk_enable/clk_disable for these if standard code won't * handle it */ static struct clk core_l3_ick = { .name = "core_l3_ick", .ops = &clkops_null, .parent = &l3_ick, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk hsotgusb_ick_3430es1 = { .name = "hsotgusb_ick", |
ec538e30f OMAP3: clock: use... |
1698 |
.ops = &clkops_omap2_iclk_dflt, |
82e9bd588 OMAP3 clock: conv... |
1699 1700 1701 1702 1703 1704 1705 1706 1707 |
.parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk hsotgusb_ick_3430es2 = { .name = "hsotgusb_ick", |
ec538e30f OMAP3: clock: use... |
1708 |
.ops = &clkops_omap3430es2_iclk_hsotgusb_wait, |
82e9bd588 OMAP3 clock: conv... |
1709 1710 1711 1712 1713 1714 |
.parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; |
ec538e30f OMAP3: clock: use... |
1715 |
/* This interface clock does not have a CM_AUTOIDLE bit */ |
82e9bd588 OMAP3 clock: conv... |
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 |
static struct clk sdrc_ick = { .name = "sdrc_ick", .ops = &clkops_omap2_dflt_wait, .parent = &core_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SDRC_SHIFT, .flags = ENABLE_ON_INIT, .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; static struct clk gpmc_fck = { .name = "gpmc_fck", .ops = &clkops_null, .parent = &core_l3_ick, .flags = ENABLE_ON_INIT, /* huh? */ .clkdm_name = "core_l3_clkdm", .recalc = &followparent_recalc, }; /* SECURITY_L3_ICK based clocks */ static struct clk security_l3_ick = { .name = "security_l3_ick", .ops = &clkops_null, .parent = &l3_ick, .recalc = &followparent_recalc, }; static struct clk pka_ick = { .name = "pka_ick", |
ec538e30f OMAP3: clock: use... |
1747 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 |
.parent = &security_l3_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_PKA_SHIFT, .recalc = &followparent_recalc, }; /* CORE_L4_ICK based clocks */ static struct clk core_l4_ick = { .name = "core_l4_ick", .ops = &clkops_null, .parent = &l4_ick, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk usbtll_ick = { .name = "usbtll_ick", |
ec538e30f OMAP3: clock: use... |
1766 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1767 1768 1769 1770 1771 1772 1773 1774 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs3_ick = { |
b92c170d0 OMAP clock: drop ... |
1775 |
.name = "mmchs3_ick", |
ec538e30f OMAP3: clock: use... |
1776 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; /* Intersystem Communication Registers - chassis mode only */ static struct clk icr_ick = { .name = "icr_ick", |
ec538e30f OMAP3: clock: use... |
1787 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1788 1789 1790 1791 1792 1793 1794 1795 1796 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_ICR_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk aes2_ick = { .name = "aes2_ick", |
ec538e30f OMAP3: clock: use... |
1797 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1798 1799 1800 1801 1802 1803 1804 1805 1806 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_AES2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk sha12_ick = { .name = "sha12_ick", |
ec538e30f OMAP3: clock: use... |
1807 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1808 1809 1810 1811 1812 1813 1814 1815 1816 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SHA12_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk des2_ick = { .name = "des2_ick", |
ec538e30f OMAP3: clock: use... |
1817 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1818 1819 1820 1821 1822 1823 1824 1825 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_DES2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs2_ick = { |
b92c170d0 OMAP clock: drop ... |
1826 |
.name = "mmchs2_ick", |
ec538e30f OMAP3: clock: use... |
1827 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1828 1829 1830 1831 1832 1833 1834 1835 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mmchs1_ick = { |
b92c170d0 OMAP clock: drop ... |
1836 |
.name = "mmchs1_ick", |
ec538e30f OMAP3: clock: use... |
1837 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1838 1839 1840 1841 1842 1843 1844 1845 1846 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MMC1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mspro_ick = { .name = "mspro_ick", |
ec538e30f OMAP3: clock: use... |
1847 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1848 1849 1850 1851 1852 1853 1854 1855 1856 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MSPRO_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk hdq_ick = { .name = "hdq_ick", |
ec538e30f OMAP3: clock: use... |
1857 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1858 1859 1860 1861 1862 1863 1864 1865 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_HDQ_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi4_ick = { |
b92c170d0 OMAP clock: drop ... |
1866 |
.name = "mcspi4_ick", |
ec538e30f OMAP3: clock: use... |
1867 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1868 1869 1870 1871 1872 1873 1874 1875 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi3_ick = { |
b92c170d0 OMAP clock: drop ... |
1876 |
.name = "mcspi3_ick", |
ec538e30f OMAP3: clock: use... |
1877 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1878 1879 1880 1881 1882 1883 1884 1885 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi2_ick = { |
b92c170d0 OMAP clock: drop ... |
1886 |
.name = "mcspi2_ick", |
ec538e30f OMAP3: clock: use... |
1887 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1888 1889 1890 1891 1892 1893 1894 1895 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcspi1_ick = { |
b92c170d0 OMAP clock: drop ... |
1896 |
.name = "mcspi1_ick", |
ec538e30f OMAP3: clock: use... |
1897 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1898 1899 1900 1901 1902 1903 1904 1905 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c3_ick = { |
b92c170d0 OMAP clock: drop ... |
1906 |
.name = "i2c3_ick", |
ec538e30f OMAP3: clock: use... |
1907 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1908 1909 1910 1911 1912 1913 1914 1915 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C3_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c2_ick = { |
b92c170d0 OMAP clock: drop ... |
1916 |
.name = "i2c2_ick", |
ec538e30f OMAP3: clock: use... |
1917 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1918 1919 1920 1921 1922 1923 1924 1925 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk i2c1_ick = { |
b92c170d0 OMAP clock: drop ... |
1926 |
.name = "i2c1_ick", |
ec538e30f OMAP3: clock: use... |
1927 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1928 1929 1930 1931 1932 1933 1934 1935 1936 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_I2C1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk uart2_ick = { .name = "uart2_ick", |
ec538e30f OMAP3: clock: use... |
1937 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1938 1939 1940 1941 1942 1943 1944 1945 1946 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART2_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk uart1_ick = { .name = "uart1_ick", |
ec538e30f OMAP3: clock: use... |
1947 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1948 1949 1950 1951 1952 1953 1954 1955 1956 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_UART1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt11_ick = { .name = "gpt11_ick", |
ec538e30f OMAP3: clock: use... |
1957 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1958 1959 1960 1961 1962 1963 1964 1965 1966 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT11_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt10_ick = { .name = "gpt10_ick", |
ec538e30f OMAP3: clock: use... |
1967 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1968 1969 1970 1971 1972 1973 1974 1975 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_GPT10_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp5_ick = { |
b92c170d0 OMAP clock: drop ... |
1976 |
.name = "mcbsp5_ick", |
ec538e30f OMAP3: clock: use... |
1977 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1978 1979 1980 1981 1982 1983 1984 1985 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp1_ick = { |
b92c170d0 OMAP clock: drop ... |
1986 |
.name = "mcbsp1_ick", |
ec538e30f OMAP3: clock: use... |
1987 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1988 1989 1990 1991 1992 1993 1994 1995 1996 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk fac_ick = { .name = "fac_ick", |
ec538e30f OMAP3: clock: use... |
1997 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
1998 1999 2000 2001 2002 2003 2004 2005 2006 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk mailboxes_ick = { .name = "mailboxes_ick", |
ec538e30f OMAP3: clock: use... |
2007 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2008 2009 2010 2011 2012 2013 2014 2015 2016 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk omapctrl_ick = { .name = "omapctrl_ick", |
ec538e30f OMAP3: clock: use... |
2017 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, .flags = ENABLE_ON_INIT, .recalc = &followparent_recalc, }; /* SSI_L4_ICK based clocks */ static struct clk ssi_l4_ick = { .name = "ssi_l4_ick", .ops = &clkops_null, .parent = &l4_ick, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk ssi_ick_3430es1 = { .name = "ssi_ick", |
ec538e30f OMAP3: clock: use... |
2037 |
.ops = &clkops_omap2_iclk_dflt, |
82e9bd588 OMAP3 clock: conv... |
2038 2039 2040 2041 2042 2043 2044 2045 2046 |
.parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; static struct clk ssi_ick_3430es2 = { .name = "ssi_ick", |
ec538e30f OMAP3: clock: use... |
2047 |
.ops = &clkops_omap3430es2_iclk_ssi_wait, |
82e9bd588 OMAP3 clock: conv... |
2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 |
.parent = &ssi_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430_EN_SSI_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; /* REVISIT: Technically the TRM claims that this is CORE_CLK based, * but l4_ick makes more sense to me */ static const struct clksel usb_l4_clksel[] = { { .parent = &l4_ick, .rates = div2_rates }, { .parent = NULL }, }; static struct clk usb_l4_ick = { .name = "usb_l4_ick", |
ec538e30f OMAP3: clock: use... |
2065 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 |
.parent = &l4_ick, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, .clksel = usb_l4_clksel, .recalc = &omap2_clksel_recalc, }; /* SECURITY_L4_ICK2 based clocks */ static struct clk security_l4_ick2 = { .name = "security_l4_ick2", .ops = &clkops_null, .parent = &l4_ick, .recalc = &followparent_recalc, }; static struct clk aes1_ick = { .name = "aes1_ick", |
ec538e30f OMAP3: clock: use... |
2087 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2088 2089 2090 2091 2092 2093 2094 2095 |
.parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_AES1_SHIFT, .recalc = &followparent_recalc, }; static struct clk rng_ick = { .name = "rng_ick", |
ec538e30f OMAP3: clock: use... |
2096 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2097 2098 2099 2100 2101 2102 2103 2104 |
.parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_RNG_SHIFT, .recalc = &followparent_recalc, }; static struct clk sha11_ick = { .name = "sha11_ick", |
ec538e30f OMAP3: clock: use... |
2105 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2106 2107 2108 2109 2110 2111 2112 2113 |
.parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_SHA11_SHIFT, .recalc = &followparent_recalc, }; static struct clk des1_ick = { .name = "des1_ick", |
ec538e30f OMAP3: clock: use... |
2114 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 |
.parent = &security_l4_ick2, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), .enable_bit = OMAP3430_EN_DES1_SHIFT, .recalc = &followparent_recalc, }; /* DSS */ static struct clk dss1_alwon_fck_3430es1 = { .name = "dss1_alwon_fck", .ops = &clkops_omap2_dflt, .parent = &dpll4_m4x2_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss1_alwon_fck_3430es2 = { .name = "dss1_alwon_fck", .ops = &clkops_omap3430es2_dss_usbhost_wait, .parent = &dpll4_m4x2_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS1_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss_tv_fck = { .name = "dss_tv_fck", .ops = &clkops_omap2_dflt, .parent = &omap_54m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss_96m_fck = { .name = "dss_96m_fck", .ops = &clkops_omap2_dflt, .parent = &omap_96m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_TV_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss2_alwon_fck = { .name = "dss2_alwon_fck", .ops = &clkops_omap2_dflt, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_DSS2_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss_ick_3430es1 = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", |
ec538e30f OMAP3: clock: use... |
2175 |
.ops = &clkops_omap2_iclk_dflt, |
82e9bd588 OMAP3 clock: conv... |
2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 |
.parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; static struct clk dss_ick_3430es2 = { /* Handles both L3 and L4 clocks */ .name = "dss_ick", |
ec538e30f OMAP3: clock: use... |
2186 |
.ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, |
82e9bd588 OMAP3 clock: conv... |
2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 |
.parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, .clkdm_name = "dss_clkdm", .recalc = &followparent_recalc, }; /* CAM */ static struct clk cam_mclk = { .name = "cam_mclk", .ops = &clkops_omap2_dflt, .parent = &dpll4_m5x2_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; static struct clk cam_ick = { /* Handles both L3 and L4 clocks */ .name = "cam_ick", |
ec538e30f OMAP3: clock: use... |
2209 |
.ops = &clkops_omap2_iclk_dflt, |
82e9bd588 OMAP3 clock: conv... |
2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 |
.parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_CAM_SHIFT, .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; static struct clk csi2_96m_fck = { .name = "csi2_96m_fck", .ops = &clkops_omap2_dflt, .parent = &core_96m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_CSI2_SHIFT, .clkdm_name = "cam_clkdm", .recalc = &followparent_recalc, }; /* USBHOST - 3430ES2 only */ static struct clk usbhost_120m_fck = { .name = "usbhost_120m_fck", .ops = &clkops_omap2_dflt, .parent = &dpll5_m2_ck, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; static struct clk usbhost_48m_fck = { .name = "usbhost_48m_fck", .ops = &clkops_omap3430es2_dss_usbhost_wait, .parent = &omap_48m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; static struct clk usbhost_ick = { /* Handles both L3 and L4 clocks */ .name = "usbhost_ick", |
ec538e30f OMAP3: clock: use... |
2252 |
.ops = &clkops_omap3430es2_iclk_dss_usbhost_wait, |
82e9bd588 OMAP3 clock: conv... |
2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 |
.parent = &l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, .clkdm_name = "usbhost_clkdm", .recalc = &followparent_recalc, }; /* WKUP */ static const struct clksel_rate usim_96m_rates[] = { |
63405360f OMAP3 clock: rena... |
2263 2264 2265 2266 |
{ .div = 2, .val = 3, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 8, .val = 5, .flags = RATE_IN_3XXX }, { .div = 10, .val = 6, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2267 2268 2269 2270 |
{ .div = 0 }, }; static const struct clksel_rate usim_120m_rates[] = { |
63405360f OMAP3 clock: rena... |
2271 2272 2273 2274 |
{ .div = 4, .val = 7, .flags = RATE_IN_3XXX }, { .div = 8, .val = 8, .flags = RATE_IN_3XXX }, { .div = 16, .val = 9, .flags = RATE_IN_3XXX }, { .div = 20, .val = 10, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 |
{ .div = 0 }, }; static const struct clksel usim_clksel[] = { { .parent = &omap_96m_fck, .rates = usim_96m_rates }, { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, { .parent = &sys_ck, .rates = div2_rates }, { .parent = NULL }, }; /* 3430ES2 only */ static struct clk usim_fck = { .name = "usim_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, .clksel = usim_clksel, .recalc = &omap2_clksel_recalc, }; /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ static struct clk gpt1_fck = { .name = "gpt1_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "wkup_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk wkup_32k_fck = { .name = "wkup_32k_fck", .ops = &clkops_null, .parent = &omap_32k_fck, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio1_dbck = { .name = "gpio1_dbck", .ops = &clkops_omap2_dflt, .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt2_fck = { .name = "wdt2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &wkup_32k_fck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wkup_l4_ick = { .name = "wkup_l4_ick", .ops = &clkops_null, .parent = &sys_ck, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; /* 3430ES2 only */ /* Never specifically named in the TRM, so we have to infer a likely name */ static struct clk usim_ick = { .name = "usim_ick", |
ec538e30f OMAP3: clock: use... |
2352 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2353 2354 2355 2356 2357 2358 2359 2360 2361 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt2_ick = { .name = "wdt2_ick", |
ec538e30f OMAP3: clock: use... |
2362 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2363 2364 2365 2366 2367 2368 2369 2370 2371 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT2_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt1_ick = { .name = "wdt1_ick", |
ec538e30f OMAP3: clock: use... |
2372 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2373 2374 2375 2376 2377 2378 2379 2380 2381 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT1_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio1_ick = { .name = "gpio1_ick", |
ec538e30f OMAP3: clock: use... |
2382 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2383 2384 2385 2386 2387 2388 2389 2390 2391 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO1_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk omap_32ksync_ick = { .name = "omap_32ksync_ick", |
ec538e30f OMAP3: clock: use... |
2392 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; /* XXX This clock no longer exists in 3430 TRM rev F */ static struct clk gpt12_ick = { .name = "gpt12_ick", |
ec538e30f OMAP3: clock: use... |
2403 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2404 2405 2406 2407 2408 2409 2410 2411 2412 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT12_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt1_ick = { .name = "gpt1_ick", |
ec538e30f OMAP3: clock: use... |
2413 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 |
.parent = &wkup_l4_ick, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT1_SHIFT, .clkdm_name = "wkup_clkdm", .recalc = &followparent_recalc, }; /* PER clock domain */ static struct clk per_96m_fck = { .name = "per_96m_fck", .ops = &clkops_null, .parent = &omap_96m_alwon_fck, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk per_48m_fck = { .name = "per_48m_fck", .ops = &clkops_null, .parent = &omap_48m_fck, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk uart3_fck = { .name = "uart3_fck", .ops = &clkops_omap2_dflt_wait, .parent = &per_48m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; |
a0edcdbe5 OMAP clock: Add u... |
2450 2451 2452 2453 2454 2455 2456 2457 2458 |
static struct clk uart4_fck = { .name = "uart4_fck", .ops = &clkops_omap2_dflt_wait, .parent = &per_48m_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3630_EN_UART4_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; |
4bf90f657 ARM: OMAP: hwmod ... |
2459 2460 2461 2462 2463 2464 2465 2466 2467 |
static struct clk uart4_fck_am35xx = { .name = "uart4_fck", .ops = &clkops_omap2_dflt_wait, .parent = &per_48m_fck, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), .enable_bit = OMAP3430_EN_UART4_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 |
static struct clk gpt2_fck = { .name = "gpt2_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt3_fck = { .name = "gpt3_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt4_fck = { .name = "gpt4_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt5_fck = { .name = "gpt5_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt6_fck = { .name = "gpt6_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt7_fck = { .name = "gpt7_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt8_fck = { .name = "gpt8_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk gpt9_fck = { .name = "gpt9_fck", .ops = &clkops_omap2_dflt_wait, .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, .clksel = omap343x_gpt_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk per_32k_alwon_fck = { .name = "per_32k_alwon_fck", .ops = &clkops_null, .parent = &omap_32k_fck, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio6_dbck = { .name = "gpio6_dbck", .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio5_dbck = { .name = "gpio5_dbck", .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio4_dbck = { .name = "gpio4_dbck", .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio3_dbck = { .name = "gpio3_dbck", .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio2_dbck = { .name = "gpio2_dbck", .ops = &clkops_omap2_dflt, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt3_fck = { .name = "wdt3_fck", .ops = &clkops_omap2_dflt_wait, .parent = &per_32k_alwon_fck, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk per_l4_ick = { .name = "per_l4_ick", .ops = &clkops_null, .parent = &l4_ick, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio6_ick = { .name = "gpio6_ick", |
ec538e30f OMAP3: clock: use... |
2650 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2651 2652 2653 2654 2655 2656 2657 2658 2659 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO6_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio5_ick = { .name = "gpio5_ick", |
ec538e30f OMAP3: clock: use... |
2660 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2661 2662 2663 2664 2665 2666 2667 2668 2669 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO5_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio4_ick = { .name = "gpio4_ick", |
ec538e30f OMAP3: clock: use... |
2670 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2671 2672 2673 2674 2675 2676 2677 2678 2679 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO4_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio3_ick = { .name = "gpio3_ick", |
ec538e30f OMAP3: clock: use... |
2680 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2681 2682 2683 2684 2685 2686 2687 2688 2689 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpio2_ick = { .name = "gpio2_ick", |
ec538e30f OMAP3: clock: use... |
2690 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2691 2692 2693 2694 2695 2696 2697 2698 2699 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPIO2_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk wdt3_ick = { .name = "wdt3_ick", |
ec538e30f OMAP3: clock: use... |
2700 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2701 2702 2703 2704 2705 2706 2707 2708 2709 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_WDT3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk uart3_ick = { .name = "uart3_ick", |
ec538e30f OMAP3: clock: use... |
2710 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2711 2712 2713 2714 2715 2716 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_UART3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; |
a0edcdbe5 OMAP clock: Add u... |
2717 2718 |
static struct clk uart4_ick = { .name = "uart4_ick", |
ec538e30f OMAP3: clock: use... |
2719 |
.ops = &clkops_omap2_iclk_dflt_wait, |
a0edcdbe5 OMAP clock: Add u... |
2720 2721 2722 2723 2724 2725 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3630_EN_UART4_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; |
82e9bd588 OMAP3 clock: conv... |
2726 2727 |
static struct clk gpt9_ick = { .name = "gpt9_ick", |
ec538e30f OMAP3: clock: use... |
2728 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2729 2730 2731 2732 2733 2734 2735 2736 2737 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT9_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt8_ick = { .name = "gpt8_ick", |
ec538e30f OMAP3: clock: use... |
2738 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2739 2740 2741 2742 2743 2744 2745 2746 2747 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT8_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt7_ick = { .name = "gpt7_ick", |
ec538e30f OMAP3: clock: use... |
2748 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2749 2750 2751 2752 2753 2754 2755 2756 2757 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT7_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt6_ick = { .name = "gpt6_ick", |
ec538e30f OMAP3: clock: use... |
2758 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2759 2760 2761 2762 2763 2764 2765 2766 2767 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT6_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt5_ick = { .name = "gpt5_ick", |
ec538e30f OMAP3: clock: use... |
2768 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2769 2770 2771 2772 2773 2774 2775 2776 2777 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT5_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt4_ick = { .name = "gpt4_ick", |
ec538e30f OMAP3: clock: use... |
2778 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2779 2780 2781 2782 2783 2784 2785 2786 2787 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT4_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt3_ick = { .name = "gpt3_ick", |
ec538e30f OMAP3: clock: use... |
2788 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2789 2790 2791 2792 2793 2794 2795 2796 2797 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk gpt2_ick = { .name = "gpt2_ick", |
ec538e30f OMAP3: clock: use... |
2798 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2799 2800 2801 2802 2803 2804 2805 2806 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_GPT2_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp2_ick = { |
b92c170d0 OMAP clock: drop ... |
2807 |
.name = "mcbsp2_ick", |
ec538e30f OMAP3: clock: use... |
2808 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2809 2810 2811 2812 2813 2814 2815 2816 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp3_ick = { |
b92c170d0 OMAP clock: drop ... |
2817 |
.name = "mcbsp3_ick", |
ec538e30f OMAP3: clock: use... |
2818 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2819 2820 2821 2822 2823 2824 2825 2826 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static struct clk mcbsp4_ick = { |
b92c170d0 OMAP clock: drop ... |
2827 |
.name = "mcbsp4_ick", |
ec538e30f OMAP3: clock: use... |
2828 |
.ops = &clkops_omap2_iclk_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2829 2830 2831 2832 2833 2834 2835 2836 |
.parent = &per_l4_ick, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, .clkdm_name = "per_clkdm", .recalc = &followparent_recalc, }; static const struct clksel mcbsp_234_clksel[] = { |
073463ca4 OMAP3 clock: McBS... |
2837 |
{ .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, |
82e9bd588 OMAP3 clock: conv... |
2838 2839 2840 2841 2842 |
{ .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, { .parent = NULL } }; static struct clk mcbsp2_fck = { |
b92c170d0 OMAP clock: drop ... |
2843 |
.name = "mcbsp2_fck", |
82e9bd588 OMAP3 clock: conv... |
2844 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 |
.init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, .clksel = mcbsp_234_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp3_fck = { |
b92c170d0 OMAP clock: drop ... |
2856 |
.name = "mcbsp3_fck", |
82e9bd588 OMAP3 clock: conv... |
2857 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 |
.init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, .clksel = mcbsp_234_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk mcbsp4_fck = { |
b92c170d0 OMAP clock: drop ... |
2869 |
.name = "mcbsp4_fck", |
82e9bd588 OMAP3 clock: conv... |
2870 |
.ops = &clkops_omap2_dflt_wait, |
82e9bd588 OMAP3 clock: conv... |
2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 |
.init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, .clksel = mcbsp_234_clksel, .clkdm_name = "per_clkdm", .recalc = &omap2_clksel_recalc, }; /* EMU clocks */ /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ static const struct clksel_rate emu_src_sys_rates[] = { |
63405360f OMAP3 clock: rena... |
2886 |
{ .div = 1, .val = 0, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2887 2888 2889 2890 |
{ .div = 0 }, }; static const struct clksel_rate emu_src_core_rates[] = { |
63405360f OMAP3 clock: rena... |
2891 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2892 2893 2894 2895 |
{ .div = 0 }, }; static const struct clksel_rate emu_src_per_rates[] = { |
63405360f OMAP3 clock: rena... |
2896 |
{ .div = 1, .val = 2, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2897 2898 2899 2900 |
{ .div = 0 }, }; static const struct clksel_rate emu_src_mpu_rates[] = { |
63405360f OMAP3 clock: rena... |
2901 |
{ .div = 1, .val = 3, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 |
{ .div = 0 }, }; static const struct clksel emu_src_clksel[] = { { .parent = &sys_ck, .rates = emu_src_sys_rates }, { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, { .parent = NULL }, }; /* * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only * to switch the source of some of the EMU clocks. * XXX Are there CLKEN bits for these EMU clks? */ static struct clk emu_src_ck = { .name = "emu_src_ck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_MUX_CTRL_MASK, .clksel = emu_src_clksel, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel_rate pclk_emu_rates[] = { |
63405360f OMAP3 clock: rena... |
2930 2931 2932 2933 |
{ .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, { .div = 6, .val = 6, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 |
{ .div = 0 }, }; static const struct clksel pclk_emu_clksel[] = { { .parent = &emu_src_ck, .rates = pclk_emu_rates }, { .parent = NULL }, }; static struct clk pclk_fck = { .name = "pclk_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, .clksel = pclk_emu_clksel, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel_rate pclkx2_emu_rates[] = { |
63405360f OMAP3 clock: rena... |
2954 2955 2956 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 3, .val = 3, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 |
{ .div = 0 }, }; static const struct clksel pclkx2_emu_clksel[] = { { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, { .parent = NULL }, }; static struct clk pclkx2_fck = { .name = "pclkx2_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, .clksel = pclkx2_emu_clksel, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel atclk_emu_clksel[] = { { .parent = &emu_src_ck, .rates = div2_rates }, { .parent = NULL }, }; static struct clk atclk_fck = { .name = "atclk_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, .clksel = atclk_emu_clksel, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static struct clk traceclk_src_fck = { .name = "traceclk_src_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, .clksel = emu_src_clksel, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; static const struct clksel_rate traceclk_rates[] = { |
63405360f OMAP3 clock: rena... |
3004 3005 3006 |
{ .div = 1, .val = 1, .flags = RATE_IN_3XXX }, { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, { .div = 4, .val = 4, .flags = RATE_IN_3XXX }, |
82e9bd588 OMAP3 clock: conv... |
3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 |
{ .div = 0 }, }; static const struct clksel traceclk_clksel[] = { { .parent = &traceclk_src_fck, .rates = traceclk_rates }, { .parent = NULL }, }; static struct clk traceclk_fck = { .name = "traceclk_fck", .ops = &clkops_null, .init = &omap2_init_clksel_parent, .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, .clksel = traceclk_clksel, .clkdm_name = "emu_clkdm", .recalc = &omap2_clksel_recalc, }; /* SR clocks */ /* SmartReflex fclk (VDD1) */ static struct clk sr1_fck = { .name = "sr1_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR1_SHIFT, |
ae4b4fc1b OMAP3: clock data... |
3035 |
.clkdm_name = "wkup_clkdm", |
82e9bd588 OMAP3 clock: conv... |
3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 |
.recalc = &followparent_recalc, }; /* SmartReflex fclk (VDD2) */ static struct clk sr2_fck = { .name = "sr2_fck", .ops = &clkops_omap2_dflt_wait, .parent = &sys_ck, .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), .enable_bit = OMAP3430_EN_SR2_SHIFT, |
ae4b4fc1b OMAP3: clock data... |
3046 |
.clkdm_name = "wkup_clkdm", |
82e9bd588 OMAP3 clock: conv... |
3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 |
.recalc = &followparent_recalc, }; static struct clk sr_l4_ick = { .name = "sr_l4_ick", .ops = &clkops_null, /* RMK: missing? */ .parent = &l4_ick, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; /* SECURE_32K_FCK clocks */ static struct clk gpt12_fck = { .name = "gpt12_fck", .ops = &clkops_null, .parent = &secure_32k_fck, |
e21757a05 OMAP3: clock: ind... |
3064 |
.clkdm_name = "wkup_clkdm", |
82e9bd588 OMAP3 clock: conv... |
3065 3066 3067 3068 3069 3070 3071 |
.recalc = &followparent_recalc, }; static struct clk wdt1_fck = { .name = "wdt1_fck", .ops = &clkops_null, .parent = &secure_32k_fck, |
e21757a05 OMAP3: clock: ind... |
3072 |
.clkdm_name = "wkup_clkdm", |
82e9bd588 OMAP3 clock: conv... |
3073 3074 |
.recalc = &followparent_recalc, }; |
3cc4a2fc2 AM35xx: Add clock... |
3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 |
/* Clocks for AM35XX */ static struct clk ipss_ick = { .name = "ipss_ick", .ops = &clkops_am35xx_ipss_wait, .parent = &core_l3_ick, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = AM35XX_EN_IPSS_SHIFT, .recalc = &followparent_recalc, }; static struct clk emac_ick = { .name = "emac_ick", .ops = &clkops_am35xx_ipss_module_wait, .parent = &ipss_ick, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, .recalc = &followparent_recalc, }; static struct clk rmii_ck = { .name = "rmii_ck", .ops = &clkops_null, |
3cc4a2fc2 AM35xx: Add clock... |
3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 |
.rate = 50000000, }; static struct clk emac_fck = { .name = "emac_fck", .ops = &clkops_omap2_dflt, .parent = &rmii_ck, .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, .recalc = &followparent_recalc, }; static struct clk hsotgusb_ick_am35xx = { .name = "hsotgusb_ick", .ops = &clkops_am35xx_ipss_module_wait, .parent = &ipss_ick, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, .recalc = &followparent_recalc, }; static struct clk hsotgusb_fck_am35xx = { .name = "hsotgusb_fck", .ops = &clkops_omap2_dflt, .parent = &sys_ck, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, .recalc = &followparent_recalc, }; static struct clk hecc_ck = { .name = "hecc_ck", .ops = &clkops_am35xx_ipss_module_wait, .parent = &sys_ck, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, .recalc = &followparent_recalc, }; static struct clk vpfe_ick = { .name = "vpfe_ick", .ops = &clkops_am35xx_ipss_module_wait, .parent = &ipss_ick, .clkdm_name = "core_l3_clkdm", .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, .recalc = &followparent_recalc, }; static struct clk pclk_ck = { .name = "pclk_ck", .ops = &clkops_null, |
3cc4a2fc2 AM35xx: Add clock... |
3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 |
.rate = 27000000, }; static struct clk vpfe_fck = { .name = "vpfe_fck", .ops = &clkops_omap2_dflt, .parent = &pclk_ck, .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), .enable_bit = AM35XX_VPFE_FCLK_SHIFT, .recalc = &followparent_recalc, }; /* * The UART1/2 functional clock acts as the functional * clock for UART4. No separate fclk control available. */ static struct clk uart4_ick_am35xx = { .name = "uart4_ick", |
ec538e30f OMAP3: clock: use... |
3172 |
.ops = &clkops_omap2_iclk_dflt_wait, |
3cc4a2fc2 AM35xx: Add clock... |
3173 3174 3175 3176 3177 3178 |
.parent = &core_l4_ick, .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_bit = AM35XX_EN_UART4_SHIFT, .clkdm_name = "core_l4_clkdm", .recalc = &followparent_recalc, }; |
3126c7bc4 ARM: AMBA: Add pc... |
3179 3180 3181 3182 |
static struct clk dummy_apb_pclk = { .name = "apb_pclk", .ops = &clkops_null, }; |
82e9bd588 OMAP3 clock: conv... |
3183 3184 3185 3186 |
/* * clkdev */ |
ced825293 AM35xx: Clock tab... |
3187 3188 |
/* XXX At some point we should rename this file to clock3xxx_data.c */ static struct omap_clk omap3xxx_clks[] = { |
3126c7bc4 ARM: AMBA: Add pc... |
3189 |
CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3190 3191 3192 |
CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3193 |
CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3194 3195 3196 3197 3198 3199 |
CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), |
829e5b127 OMAP3xxx: clock: ... |
3200 3201 3202 3203 3204 |
CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX), CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX), CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX), CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX), CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3205 3206 3207 3208 3209 |
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3210 3211 |
CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX), CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 |
CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), CLK(NULL, "core_ck", &core_ck, CK_3XXX), CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX), CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX), CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX), CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX), CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX), CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX), CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX), |
7356f0b26 OMAP3 clock: add ... |
3222 |
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX), |
ced825293 AM35xx: Clock tab... |
3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 |
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX), CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX), CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX), CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX), CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX), CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX), CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX), CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX), CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX), CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX), CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX), CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX), CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX), CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX), CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3240 3241 |
CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3242 3243 3244 3245 3246 3247 3248 |
CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3249 3250 |
CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3251 3252 3253 |
CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), |
82e9bd588 OMAP3 clock: conv... |
3254 3255 3256 3257 3258 |
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3259 3260 |
CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX), CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX), |
82e9bd588 OMAP3 clock: conv... |
3261 |
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3262 3263 3264 |
CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX), CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX), CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3265 3266 |
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3267 3268 3269 |
CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
a6d3a6622 ARM: OMAP: USB: d... |
3270 |
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
829e5b127 OMAP3xxx: clock: ... |
3271 3272 |
CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3273 |
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), |
bf1e0776c OMAP: omap_device... |
3274 3275 |
CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3276 |
CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), |
bf1e0776c OMAP: omap_device... |
3277 3278 3279 3280 3281 3282 |
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX), CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX), CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX), CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX), CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX), CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3283 |
CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), |
bf1e0776c OMAP: omap_device... |
3284 3285 3286 3287 |
CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX), CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX), CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX), CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3288 3289 |
CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX), CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX), |
82e9bd588 OMAP3 clock: conv... |
3290 |
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), |
ced825293 AM35xx: Clock tab... |
3291 |
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), |
bf1e0776c OMAP: omap_device... |
3292 |
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), |
82e9bd588 OMAP3 clock: conv... |
3293 |
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3294 |
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX), |
82e9bd588 OMAP3 clock: conv... |
3295 |
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3296 |
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3297 |
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), |
034917612 usb: musb: move c... |
3298 |
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), |
3e5b08cbb Merge branch 'usb... |
3299 |
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3300 3301 |
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3302 3303 |
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX), CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3304 |
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3305 |
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
a6d3a6622 ARM: OMAP: USB: d... |
3306 |
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
0005ae73c OMAP: hsmmc: Rena... |
3307 |
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
553d239aa OMAP3: clock: cla... |
3308 3309 3310 3311 |
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), |
0005ae73c OMAP: hsmmc: Rena... |
3312 3313 |
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3314 |
CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3315 3316 3317 3318 3319 |
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), |
f7bb0d9ab I2C: i2c-omap: Ch... |
3320 3321 3322 |
CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX), CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX), CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3323 3324 3325 3326 3327 3328 |
CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX), CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), |
82e9bd588 OMAP3 clock: conv... |
3329 |
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3330 |
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3331 |
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3332 |
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX), |
82e9bd588 OMAP3 clock: conv... |
3333 |
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3334 |
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX), |
82e9bd588 OMAP3 clock: conv... |
3335 |
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), |
553d239aa OMAP3: clock: cla... |
3336 3337 3338 3339 3340 |
CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX), CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX), CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), |
bf1e0776c OMAP: omap_device... |
3341 3342 3343 3344 3345 |
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX), CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX), CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX), |
8b9cb3a8f OMAP2, 3: DSS2: M... |
3346 3347 |
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
553d239aa OMAP3: clock: cla... |
3348 3349 3350 3351 3352 3353 |
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
a6d3a6622 ARM: OMAP: USB: d... |
3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 |
CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK("usbhs_omap", "utmi_p1_gfclk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "utmi_p2_gfclk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX), CLK("usbhs_omap", "init_60m_fclk", &dummy_ck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3364 |
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3365 3366 3367 |
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), |
bf1e0776c OMAP: omap_device... |
3368 |
CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3369 3370 |
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX), CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3371 3372 3373 3374 3375 3376 |
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), |
829e5b127 OMAP3xxx: clock: ... |
3377 3378 3379 |
CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX), CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX), CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3380 3381 3382 |
CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), |
a0edcdbe5 OMAP clock: Add u... |
3383 |
CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX), |
4bf90f657 ARM: OMAP: hwmod ... |
3384 |
CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_3505 | CK_3517), |
ced825293 AM35xx: Clock tab... |
3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 |
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX), CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX), CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX), CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX), CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX), CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX), CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX), CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX), CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX), CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX), CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX), CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX), CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), |
a0edcdbe5 OMAP clock: Add u... |
3408 |
CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX), |
ced825293 AM35xx: Clock tab... |
3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 |
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX), CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX), CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX), CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX), CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX), CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX), CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX), CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX), |
bf1e0776c OMAP: omap_device... |
3420 3421 3422 |
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX), CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX), CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX), |
ced825293 AM35xx: Clock tab... |
3423 3424 3425 3426 3427 3428 |
CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX), CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX), CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX), CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), |
553d239aa OMAP3: clock: cla... |
3429 3430 3431 |
CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX), CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX), CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX), |
ced825293 AM35xx: Clock tab... |
3432 3433 3434 |
CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), |
3cc4a2fc2 AM35xx: Add clock... |
3435 3436 3437 |
CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), |
b98dd73c6 OMAP3: clock data... |
3438 3439 |
CLK("davinci_emac", "emac_clk", &emac_ick, CK_AM35XX), CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), |
3cc4a2fc2 AM35xx: Add clock... |
3440 3441 |
CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), |
034917612 usb: musb: move c... |
3442 3443 |
CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), |
3cc4a2fc2 AM35xx: Add clock... |
3444 3445 |
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), |
318c3e15c ARM: OMAP2+: dmti... |
3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 |
CLK("omap_timer.1", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.2", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.3", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.4", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.5", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.6", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.7", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.8", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.9", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.10", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.11", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.12", "32k_ck", &omap_32k_fck, CK_3XXX), CLK("omap_timer.1", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.2", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.3", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.4", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.5", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.6", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.7", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.8", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.9", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.10", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.11", "sys_ck", &sys_ck, CK_3XXX), CLK("omap_timer.12", "sys_ck", &sys_ck, CK_3XXX), |
82e9bd588 OMAP3 clock: conv... |
3470 |
}; |
e80a9729b OMAP2/3/4 clock: ... |
3471 |
int __init omap3xxx_clk_init(void) |
82e9bd588 OMAP3 clock: conv... |
3472 |
{ |
82e9bd588 OMAP3 clock: conv... |
3473 |
struct omap_clk *c; |
553d239aa OMAP3: clock: cla... |
3474 |
u32 cpu_clkflg = 0; |
82e9bd588 OMAP3 clock: conv... |
3475 |
|
1f1b0353a OMAP3: id: remove... |
3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 |
/* * 3505 must be tested before 3517, since 3517 returns true * for both AM3517 chips and AM3517 family chips, which * includes 3505. Unfortunately there's no obvious family * test for 3517/3505 :-( */ if (cpu_is_omap3505()) { cpu_mask = RATE_IN_34XX; cpu_clkflg = CK_3505; } else if (cpu_is_omap3517()) { |
553d239aa OMAP3: clock: cla... |
3486 3487 |
cpu_mask = RATE_IN_34XX; cpu_clkflg = CK_3517; |
8098bb0d8 OMAP3: Fix a cpu ... |
3488 |
} else if (cpu_is_omap3505()) { |
553d239aa OMAP3: clock: cla... |
3489 3490 3491 3492 3493 |
cpu_mask = RATE_IN_34XX; cpu_clkflg = CK_3505; } else if (cpu_is_omap3630()) { cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); cpu_clkflg = CK_36XX; |
01001712c TI816X: Update co... |
3494 3495 3496 |
} else if (cpu_is_ti816x()) { cpu_mask = RATE_IN_TI816X; cpu_clkflg = CK_TI816X; |
1e6cb146c ARM: OMAP: am33xx... |
3497 3498 |
} else if (cpu_is_am33xx()) { cpu_mask = RATE_IN_AM33XX; |
4390f5b2c ARM: OMAP: TI814X... |
3499 3500 |
} else if (cpu_is_ti814x()) { cpu_mask = RATE_IN_TI814X; |
8098bb0d8 OMAP3: Fix a cpu ... |
3501 |
} else if (cpu_is_omap34xx()) { |
82e9bd588 OMAP3 clock: conv... |
3502 |
if (omap_rev() == OMAP3430_REV_ES1_0) { |
553d239aa OMAP3: clock: cla... |
3503 3504 |
cpu_mask = RATE_IN_3430ES1; cpu_clkflg = CK_3430ES1; |
82e9bd588 OMAP3 clock: conv... |
3505 |
} else { |
553d239aa OMAP3: clock: cla... |
3506 3507 3508 3509 3510 3511 |
/* * Assume that anything that we haven't matched yet * has 3430ES2-type clocks. */ cpu_mask = RATE_IN_3430ES2PLUS; cpu_clkflg = CK_3430ES2PLUS; |
82e9bd588 OMAP3 clock: conv... |
3512 |
} |
553d239aa OMAP3: clock: cla... |
3513 3514 3515 |
} else { WARN(1, "clock: could not identify OMAP3 variant "); |
82e9bd588 OMAP3 clock: conv... |
3516 |
} |
63405360f OMAP3 clock: rena... |
3517 |
|
7356f0b26 OMAP3 clock: add ... |
3518 3519 |
if (omap3_has_192mhz_clk()) omap_96m_alwon_fck = omap_96m_alwon_fck_3630; |
82e9bd588 OMAP3 clock: conv... |
3520 |
|
a7e069fc5 OMAP3630: Clock: ... |
3521 |
if (cpu_is_omap3630()) { |
678bc9a2e OMAP3 clock: Intr... |
3522 3523 3524 |
/* * XXX This type of dynamic rewriting of the clock tree is * deprecated and should be revised soon. |
2a9f5a4d4 OMAP3 clock: remo... |
3525 |
* |
a7e069fc5 OMAP3630: Clock: ... |
3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 |
* For 3630: override clkops_omap2_dflt_wait for the * clocks affected from PWRDN reset Limitation */ dpll3_m3x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; dpll4_m2x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; dpll4_m3x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; dpll4_m4x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; dpll4_m5x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; dpll4_m6x2_ck.ops = &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore; } |
2a9f5a4d4 OMAP3 clock: remo... |
3542 3543 3544 3545 |
/* * XXX This type of dynamic rewriting of the clock tree is * deprecated and should be revised soon. */ |
358965d7b OMAP3 clock: intr... |
3546 3547 3548 3549 |
if (cpu_is_omap3630()) dpll4_dd = dpll4_dd_3630; else dpll4_dd = dpll4_dd_34xx; |
82e9bd588 OMAP3 clock: conv... |
3550 |
clk_init(&omap2_clk_functions); |
657ebfadc OMAP3/4 clock: sp... |
3551 3552 |
for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) |
82e9bd588 OMAP3 clock: conv... |
3553 |
clk_preinit(c->lk.clk); |
657ebfadc OMAP3/4 clock: sp... |
3554 3555 |
for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks); c++) |
82e9bd588 OMAP3 clock: conv... |
3556 3557 3558 3559 3560 |
if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); clk_register(c->lk.clk); omap2_init_clk_clkdm(c->lk.clk); } |
c6461f5c5 OMAP2+: clock: di... |
3561 3562 |
/* Disable autoidle on all clocks; let the PM code enable it later */ omap_clk_disable_autoidle_all(); |
82e9bd588 OMAP3 clock: conv... |
3563 |
recalculate_root_clocks(); |
553d239aa OMAP3: clock: cla... |
3564 3565 3566 3567 |
pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz ", (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); |
82e9bd588 OMAP3 clock: conv... |
3568 3569 3570 3571 3572 3573 3574 3575 |
/* * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ clk_enable_init_clocks(); /* |
c6461f5c5 OMAP2+: clock: di... |
3576 3577 |
* Lock DPLL5 -- here only until other device init code can * handle this |
82e9bd588 OMAP3 clock: conv... |
3578 |
*/ |
a920360f0 ARM: OMAP: TI81XX... |
3579 |
if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0)) |
82e9bd588 OMAP3 clock: conv... |
3580 3581 3582 3583 3584 3585 3586 3587 |
omap3_clk_lock_dpll5(); /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ sdrc_ick_p = clk_get(NULL, "sdrc_ick"); arm_fck_p = clk_get(NULL, "arm_fck"); return 0; } |