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arch/blackfin/Kconfig 30.1 KB
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  config SYMBOL_PREFIX
  	string
  	default "_"
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  config MMU
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  	def_bool n
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  config FPU
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  	def_bool n
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  config RWSEM_GENERIC_SPINLOCK
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  	def_bool y
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  config RWSEM_XCHGADD_ALGORITHM
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  	def_bool n
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  config BLACKFIN
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  	def_bool y
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  	select HAVE_ARCH_KGDB
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  	select HAVE_ARCH_TRACEHOOK
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  	select HAVE_DYNAMIC_FTRACE
  	select HAVE_FTRACE_MCOUNT_RECORD
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  	select HAVE_FUNCTION_GRAPH_TRACER
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  	select HAVE_FUNCTION_TRACER
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  	select HAVE_FUNCTION_TRACE_MCOUNT_TEST
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  	select HAVE_IDE
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  	select HAVE_IRQ_WORK
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  	select HAVE_KERNEL_GZIP if RAMKERNEL
  	select HAVE_KERNEL_BZIP2 if RAMKERNEL
  	select HAVE_KERNEL_LZMA if RAMKERNEL
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  	select HAVE_KERNEL_LZO if RAMKERNEL
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  	select HAVE_OPROFILE
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  	select HAVE_PERF_EVENTS
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  	select ARCH_WANT_OPTIONAL_GPIOLIB
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  	select HAVE_GENERIC_HARDIRQS
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  	select GENERIC_ATOMIC64
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  	select GENERIC_IRQ_PROBE
  	select IRQ_PER_CPU if SMP
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  config GENERIC_CSUM
  	def_bool y
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  config GENERIC_BUG
  	def_bool y
  	depends on BUG
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  config ZONE_DMA
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  	def_bool y
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  config GENERIC_GPIO
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  	def_bool y
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  config FORCE_MAX_ZONEORDER
  	int
  	default "14"
  
  config GENERIC_CALIBRATE_DELAY
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  	def_bool y
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  config LOCKDEP_SUPPORT
  	def_bool y
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  config STACKTRACE_SUPPORT
  	def_bool y
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  config TRACE_IRQFLAGS_SUPPORT
  	def_bool y
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  source "init/Kconfig"
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  source "kernel/Kconfig.preempt"
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  source "kernel/Kconfig.freezer"
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  menu "Blackfin Processor Options"
  
  comment "Processor and Board Settings"
  
  choice
  	prompt "CPU"
  	default BF533
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  config BF512
  	bool "BF512"
  	help
  	  BF512 Processor Support.
  
  config BF514
  	bool "BF514"
  	help
  	  BF514 Processor Support.
  
  config BF516
  	bool "BF516"
  	help
  	  BF516 Processor Support.
  
  config BF518
  	bool "BF518"
  	help
  	  BF518 Processor Support.
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  config BF522
  	bool "BF522"
  	help
  	  BF522 Processor Support.
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  config BF523
  	bool "BF523"
  	help
  	  BF523 Processor Support.
  
  config BF524
  	bool "BF524"
  	help
  	  BF524 Processor Support.
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  config BF525
  	bool "BF525"
  	help
  	  BF525 Processor Support.
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  config BF526
  	bool "BF526"
  	help
  	  BF526 Processor Support.
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  config BF527
  	bool "BF527"
  	help
  	  BF527 Processor Support.
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  config BF531
  	bool "BF531"
  	help
  	  BF531 Processor Support.
  
  config BF532
  	bool "BF532"
  	help
  	  BF532 Processor Support.
  
  config BF533
  	bool "BF533"
  	help
  	  BF533 Processor Support.
  
  config BF534
  	bool "BF534"
  	help
  	  BF534 Processor Support.
  
  config BF536
  	bool "BF536"
  	help
  	  BF536 Processor Support.
  
  config BF537
  	bool "BF537"
  	help
  	  BF537 Processor Support.
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  config BF538
  	bool "BF538"
  	help
  	  BF538 Processor Support.
  
  config BF539
  	bool "BF539"
  	help
  	  BF539 Processor Support.
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  config BF542_std
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  	bool "BF542"
  	help
  	  BF542 Processor Support.
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  config BF542M
  	bool "BF542m"
  	help
  	  BF542 Processor Support.
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  config BF544_std
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  	bool "BF544"
  	help
  	  BF544 Processor Support.
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  config BF544M
  	bool "BF544m"
  	help
  	  BF544 Processor Support.
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  config BF547_std
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  	bool "BF547"
  	help
  	  BF547 Processor Support.
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  config BF547M
  	bool "BF547m"
  	help
  	  BF547 Processor Support.
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  config BF548_std
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  	bool "BF548"
  	help
  	  BF548 Processor Support.
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  config BF548M
  	bool "BF548m"
  	help
  	  BF548 Processor Support.
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  config BF549_std
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  	bool "BF549"
  	help
  	  BF549 Processor Support.
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  config BF549M
  	bool "BF549m"
  	help
  	  BF549 Processor Support.
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  config BF561
  	bool "BF561"
  	help
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  	  BF561 Processor Support.
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  endchoice
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  config SMP
  	depends on BF561
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  	select TICKSOURCE_CORETMR
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  	bool "Symmetric multi-processing support"
  	---help---
  	  This enables support for systems with more than one CPU,
  	  like the dual core BF561. If you have a system with only one
  	  CPU, say N. If you have a system with more than one CPU, say Y.
  
  	  If you don't know what to do here, say N.
  
  config NR_CPUS
  	int
  	depends on SMP
  	default 2 if BF561
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  config HOTPLUG_CPU
  	bool "Support for hot-pluggable CPUs"
  	depends on SMP && HOTPLUG
  	default y
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  config BF_REV_MIN
  	int
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  	default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
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  	default 2 if (BF537 || BF536 || BF534)
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  	default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
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  	default 4 if (BF538 || BF539)
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  config BF_REV_MAX
  	int
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  	default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  	default 3 if (BF537 || BF536 || BF534 || BF54xM)
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  	default 5 if (BF561 || BF538 || BF539)
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  	default 6 if (BF533 || BF532 || BF531)
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  choice
  	prompt "Silicon Rev"
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  	default BF_REV_0_0 if (BF51x || BF52x)
  	default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
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  	default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
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  config BF_REV_0_0
  	bool "0.0"
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  	depends on (BF51x || BF52x || (BF54x && !BF54xM))
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  config BF_REV_0_1
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  	bool "0.1"
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  	depends on (BF51x || BF52x || (BF54x && !BF54xM))
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  config BF_REV_0_2
  	bool "0.2"
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  	depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
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  config BF_REV_0_3
  	bool "0.3"
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  	depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
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  config BF_REV_0_4
  	bool "0.4"
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  	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
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  config BF_REV_0_5
  	bool "0.5"
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  	depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
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  config BF_REV_0_6
  	bool "0.6"
  	depends on (BF533 || BF532 || BF531)
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  config BF_REV_ANY
  	bool "any"
  
  config BF_REV_NONE
  	bool "none"
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  endchoice
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  config BF53x
  	bool
  	depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  	default y
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  config MEM_MT48LC64M4A2FB_7E
  	bool
  	depends on (BFIN533_STAMP)
  	default y
  
  config MEM_MT48LC16M16A2TG_75
  	bool
  	depends on (BFIN533_EZKIT || BFIN561_EZKIT \
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  		|| BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
  		|| BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
  		|| BFIN527_BLUETECHNIX_CM)
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  	default y
  
  config MEM_MT48LC32M8A2_75
  	bool
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  	depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
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  	default y
  
  config MEM_MT48LC8M32B2B5_7
  	bool
  	depends on (BFIN561_BLUETECHNIX_CM)
  	default y
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  config MEM_MT48LC32M16A2TG_75
  	bool
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  	depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
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  	default y
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  config MEM_MT48H32M16LFCJ_75
  	bool
  	depends on (BFIN526_EZBRD)
  	default y
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  source "arch/blackfin/mach-bf518/Kconfig"
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  source "arch/blackfin/mach-bf527/Kconfig"
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  source "arch/blackfin/mach-bf533/Kconfig"
  source "arch/blackfin/mach-bf561/Kconfig"
  source "arch/blackfin/mach-bf537/Kconfig"
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  source "arch/blackfin/mach-bf538/Kconfig"
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  source "arch/blackfin/mach-bf548/Kconfig"
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  menu "Board customizations"
  
  config CMDLINE_BOOL
  	bool "Default bootloader kernel arguments"
  
  config CMDLINE
  	string "Initial kernel command string"
  	depends on CMDLINE_BOOL
  	default "console=ttyBF0,57600"
  	help
  	  If you don't have a boot loader capable of passing a command line string
  	  to the kernel, you may specify one here. As a minimum, you should specify
  	  the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
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  config BOOT_LOAD
  	hex "Kernel load address for booting"
  	default "0x1000"
  	range 0x1000 0x20000000
  	help
  	  This option allows you to set the load address of the kernel.
  	  This can be useful if you are on a board which has a small amount
  	  of memory or you wish to reserve some memory at the beginning of
  	  the address space.
  
  	  Note that you need to keep this value above 4k (0x1000) as this
  	  memory region is used to capture NULL pointer references as well
  	  as some core kernel functions.
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  config ROM_BASE
  	hex "Kernel ROM Base"
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  	depends on ROMKERNEL
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  	default "0x20040040"
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  	range 0x20000000 0x20400000 if !(BF54x || BF561)
  	range 0x20000000 0x30000000 if (BF54x || BF561)
  	help
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  	  Make sure your ROM base does not include any file-header
  	  information that is prepended to the kernel.
  
  	  For example, the bootable U-Boot format (created with
  	  mkimage) has a 64 byte header (0x40).  So while the image
  	  you write to flash might start at say 0x20080000, you have
  	  to add 0x40 to get the kernel's ROM base as it will come
  	  after the header.
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  comment "Clock/PLL Setup"
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  config CLKIN_HZ
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  	int "Frequency of the crystal on the board in Hz"
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  	default "10000000" if BFIN532_IP0X
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  	default "11059200" if BFIN533_STAMP
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  	default "24576000" if PNAV10
  	default "25000000" # most people use this
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  	default "27000000" if BFIN533_EZKIT
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  	default "30000000" if BFIN561_EZKIT
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  	default "24000000" if BFIN527_AD7160EVAL
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  	help
  	  The frequency of CLKIN crystal oscillator on the board in Hz.
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  	  Warning: This value should match the crystal on the board. Otherwise,
  	  peripherals won't work properly.
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  config BFIN_KERNEL_CLOCK
  	bool "Re-program Clocks while Kernel boots?"
  	default n
  	help
  	  This option decides if kernel clocks are re-programed from the
  	  bootloader settings. If the clocks are not set, the SDRAM settings
  	  are also not changed, and the Bootloader does 100% of the hardware
  	  configuration.
  
  config PLL_BYPASS
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  	bool "Bypass PLL"
  	depends on BFIN_KERNEL_CLOCK
  	default n
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  config CLKIN_HALF
  	bool "Half Clock In"
  	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  	default n
  	help
  	  If this is set the clock will be divided by 2, before it goes to the PLL.
  
  config VCO_MULT
  	int "VCO Multiplier"
  	depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  	range 1 64
  	default "22" if BFIN533_EZKIT
  	default "45" if BFIN533_STAMP
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  	default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
f16295e7e   Robin Getz   Blackfin arch: Fi...
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  	default "22" if BFIN533_BLUETECHNIX_CM
605843446   Harald Krapfenbauer   Blackfin: cm-bf53...
403
  	default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
f16295e7e   Robin Getz   Blackfin arch: Fi...
404
  	default "20" if BFIN561_EZKIT
2f6f4bcdd   Bryan Wu   Blackfin arch: ad...
405
  	default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
8effc4a68   Michael Hennerich   Blackfin: ad7160e...
406
  	default "25" if BFIN527_AD7160EVAL
f16295e7e   Robin Getz   Blackfin arch: Fi...
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
  	help
  	  This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  	  PLL Frequency = (Crystal Frequency) * (this setting)
  
  choice
  	prompt "Core Clock Divider"
  	depends on BFIN_KERNEL_CLOCK
  	default CCLK_DIV_1
  	help
  	  This sets the frequency of the core. It can be 1, 2, 4 or 8
  	  Core Frequency = (PLL frequency) / (this setting)
  
  config CCLK_DIV_1
  	bool "1"
  
  config CCLK_DIV_2
  	bool "2"
  
  config CCLK_DIV_4
  	bool "4"
  
  config CCLK_DIV_8
  	bool "8"
  endchoice
  
  config SCLK_DIV
  	int "System Clock Divider"
  	depends on BFIN_KERNEL_CLOCK
  	range 1 15
5f004c200   Mike Frysinger   [Blackfin] arch: ...
436
  	default 5
f16295e7e   Robin Getz   Blackfin arch: Fi...
437
438
439
440
  	help
  	  This sets the frequency of the system clock (including SDRAM or DDR).
  	  This can be between 1 and 15
  	  System Clock = (PLL frequency) / (this setting)
5f004c200   Mike Frysinger   [Blackfin] arch: ...
441
442
443
444
445
446
447
448
449
450
451
452
  choice
  	prompt "DDR SDRAM Chip Type"
  	depends on BFIN_KERNEL_CLOCK
  	depends on BF54x
  	default MEM_MT46V32M16_5B
  
  config MEM_MT46V32M16_6T
  	bool "MT46V32M16_6T"
  
  config MEM_MT46V32M16_5B
  	bool "MT46V32M16_5B"
  endchoice
73feb5c09   Michael Hennerich   Blackfin arch: fi...
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
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477
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486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
  choice
  	prompt "DDR/SDRAM Timing"
  	depends on BFIN_KERNEL_CLOCK
  	default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  	help
  	  This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  	  The calculated SDRAM timing parameters may not be 100%
  	  accurate - This option is therefore marked experimental.
  
  config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  	bool "Calculate Timings (EXPERIMENTAL)"
  	depends on EXPERIMENTAL
  
  config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  	bool "Provide accurate Timings based on target SCLK"
  	help
  	  Please consult the Blackfin Hardware Reference Manuals as well
  	  as the memory device datasheet.
  	  http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  endchoice
  
  menu "Memory Init Control"
  	depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  
  config MEM_DDRCTL0
  	depends on BF54x
  	hex "DDRCTL0"
  	default 0x0
  
  config MEM_DDRCTL1
  	depends on BF54x
  	hex "DDRCTL1"
  	default 0x0
  
  config MEM_DDRCTL2
  	depends on BF54x
  	hex "DDRCTL2"
  	default 0x0
  
  config MEM_EBIU_DDRQUE
  	depends on BF54x
  	hex "DDRQUE"
  	default 0x0
  
  config MEM_SDRRC
  	depends on !BF54x
  	hex "SDRRC"
  	default 0x0
  
  config MEM_SDGCTL
  	depends on !BF54x
  	hex "SDGCTL"
  	default 0x0
  endmenu
f16295e7e   Robin Getz   Blackfin arch: Fi...
507
508
509
510
511
  #
  # Max & Min Speeds for various Chips
  #
  config MAX_VCO_HZ
  	int
2f6f4bcdd   Bryan Wu   Blackfin arch: ad...
512
513
514
515
  	default 400000000 if BF512
  	default 400000000 if BF514
  	default 400000000 if BF516
  	default 400000000 if BF518
7b06263bd   Mike Frysinger   Blackfin: fix BF5...
516
517
  	default 400000000 if BF522
  	default 600000000 if BF523
1545a1111   Mike Frysinger   [Blackfin] arch: ...
518
  	default 400000000 if BF524
f16295e7e   Robin Getz   Blackfin arch: Fi...
519
  	default 600000000 if BF525
1545a1111   Mike Frysinger   [Blackfin] arch: ...
520
  	default 400000000 if BF526
f16295e7e   Robin Getz   Blackfin arch: Fi...
521
522
523
524
525
526
527
  	default 600000000 if BF527
  	default 400000000 if BF531
  	default 400000000 if BF532
  	default 750000000 if BF533
  	default 500000000 if BF534
  	default 400000000 if BF536
  	default 600000000 if BF537
f72eecb97   Robin Getz   Blackfin arch: Up...
528
529
  	default 533333333 if BF538
  	default 533333333 if BF539
f16295e7e   Robin Getz   Blackfin arch: Fi...
530
  	default 600000000 if BF542
f72eecb97   Robin Getz   Blackfin arch: Up...
531
  	default 533333333 if BF544
1545a1111   Mike Frysinger   [Blackfin] arch: ...
532
533
  	default 600000000 if BF547
  	default 600000000 if BF548
f72eecb97   Robin Getz   Blackfin arch: Up...
534
  	default 533333333 if BF549
f16295e7e   Robin Getz   Blackfin arch: Fi...
535
536
537
538
539
540
541
542
  	default 600000000 if BF561
  
  config MIN_VCO_HZ
  	int
  	default 50000000
  
  config MAX_SCLK_HZ
  	int
f72eecb97   Robin Getz   Blackfin arch: Up...
543
  	default 133333333
f16295e7e   Robin Getz   Blackfin arch: Fi...
544
545
546
547
548
549
550
551
  
  config MIN_SCLK_HZ
  	int
  	default 27000000
  
  comment "Kernel Timer/Scheduler"
  
  source kernel/Kconfig.hz
8b5f79f9d   Vitja Makarov   [Blackfin] arch: ...
552
553
  config GENERIC_CLOCKEVENTS
  	bool "Generic clock events"
8b5f79f9d   Vitja Makarov   [Blackfin] arch: ...
554
  	default y
0d152c27e   Yi Li   Blackfin: SMP: ma...
555
  menu "Clock event device"
1fa9be72b   Graf Yang   Blackfin: add sup...
556
  	depends on GENERIC_CLOCKEVENTS
1fa9be72b   Graf Yang   Blackfin: add sup...
557
  config TICKSOURCE_GPTMR0
0d152c27e   Yi Li   Blackfin: SMP: ma...
558
559
  	bool "GPTimer0"
  	depends on !SMP
1fa9be72b   Graf Yang   Blackfin: add sup...
560
  	select BFIN_GPTIMERS
1fa9be72b   Graf Yang   Blackfin: add sup...
561
562
  
  config TICKSOURCE_CORETMR
0d152c27e   Yi Li   Blackfin: SMP: ma...
563
564
565
  	bool "Core timer"
  	default y
  endmenu
1fa9be72b   Graf Yang   Blackfin: add sup...
566

0d152c27e   Yi Li   Blackfin: SMP: ma...
567
  menu "Clock souce"
8b5f79f9d   Vitja Makarov   [Blackfin] arch: ...
568
  	depends on GENERIC_CLOCKEVENTS
0d152c27e   Yi Li   Blackfin: SMP: ma...
569
570
571
  config CYCLES_CLOCKSOURCE
  	bool "CYCLES"
  	default y
8b5f79f9d   Vitja Makarov   [Blackfin] arch: ...
572
  	depends on !BFIN_SCRATCH_REG_CYCLES
1fa9be72b   Graf Yang   Blackfin: add sup...
573
  	depends on !SMP
8b5f79f9d   Vitja Makarov   [Blackfin] arch: ...
574
575
576
577
578
579
  	help
  	  If you say Y here, you will enable support for using the 'cycles'
  	  registers as a clock source.  Doing so means you will be unable to
  	  safely write to the 'cycles' register during runtime.  You will
  	  still be able to read it (such as for performance monitoring), but
  	  writing the registers will most likely crash the kernel.
1fa9be72b   Graf Yang   Blackfin: add sup...
580
  config GPTMR0_CLOCKSOURCE
0d152c27e   Yi Li   Blackfin: SMP: ma...
581
  	bool "GPTimer0"
3aca47c02   Mike Frysinger   Blackfin: fix GPT...
582
  	select BFIN_GPTIMERS
1fa9be72b   Graf Yang   Blackfin: add sup...
583
  	depends on !TICKSOURCE_GPTMR0
0d152c27e   Yi Li   Blackfin: SMP: ma...
584
  endmenu
1fa9be72b   Graf Yang   Blackfin: add sup...
585

10f03f1a2   John Stultz   Blackfin: convert...
586
587
588
  config ARCH_USES_GETTIMEOFFSET
  	depends on !GENERIC_CLOCKEVENTS
  	def_bool y
8b5f79f9d   Vitja Makarov   [Blackfin] arch: ...
589
  source kernel/time/Kconfig
5f004c200   Mike Frysinger   [Blackfin] arch: ...
590
  comment "Misc"
971d5bc4e   Sonic Zhang   [Blackfin] arch: ...
591

f0b5d12f2   Mike Frysinger   Blackfin arch: al...
592
593
594
595
596
597
598
599
600
601
602
603
604
605
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609
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611
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619
620
621
622
623
624
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626
627
628
629
630
631
632
633
634
635
636
  choice
  	prompt "Blackfin Exception Scratch Register"
  	default BFIN_SCRATCH_REG_RETN
  	help
  	  Select the resource to reserve for the Exception handler:
  	    - RETN: Non-Maskable Interrupt (NMI)
  	    - RETE: Exception Return (JTAG/ICE)
  	    - CYCLES: Performance counter
  
  	  If you are unsure, please select "RETN".
  
  config BFIN_SCRATCH_REG_RETN
  	bool "RETN"
  	help
  	  Use the RETN register in the Blackfin exception handler
  	  as a stack scratch register.  This means you cannot
  	  safely use NMI on the Blackfin while running Linux, but
  	  you can debug the system with a JTAG ICE and use the
  	  CYCLES performance registers.
  
  	  If you are unsure, please select "RETN".
  
  config BFIN_SCRATCH_REG_RETE
  	bool "RETE"
  	help
  	  Use the RETE register in the Blackfin exception handler
  	  as a stack scratch register.  This means you cannot
  	  safely use a JTAG ICE while debugging a Blackfin board,
  	  but you can safely use the CYCLES performance registers
  	  and the NMI.
  
  	  If you are unsure, please select "RETN".
  
  config BFIN_SCRATCH_REG_CYCLES
  	bool "CYCLES"
  	help
  	  Use the CYCLES register in the Blackfin exception handler
  	  as a stack scratch register.  This means you cannot
  	  safely use the CYCLES performance registers on a Blackfin
  	  board at anytime, but you can debug the system with a JTAG
  	  ICE and use the NMI.
  
  	  If you are unsure, please select "RETN".
  
  endchoice
1394f0322   Bryan Wu   blackfin architec...
637
638
639
640
  endmenu
  
  
  menu "Blackfin Kernel Optimizations"
1394f0322   Bryan Wu   blackfin architec...
641
642
643
644
645
  comment "Memory Optimizations"
  
  config I_ENTRY_L1
  	bool "Locate interrupt entry code in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
646
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
647
  	help
01dd2fbf0   Matt LaPlante   typo fixes
648
649
  	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
650
651
  
  config EXCPT_IRQ_SYSC_L1
01dd2fbf0   Matt LaPlante   typo fixes
652
  	bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
1394f0322   Bryan Wu   blackfin architec...
653
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
654
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
655
  	help
01dd2fbf0   Matt LaPlante   typo fixes
656
  	  If enabled, the entire ASM lowlevel exception and interrupt entry code
cfefe3c68   Michael Hennerich   [Blackfin] arch: ...
657
  	  (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
01dd2fbf0   Matt LaPlante   typo fixes
658
  	  (less latency)
1394f0322   Bryan Wu   blackfin architec...
659
660
661
662
  
  config DO_IRQ_L1
  	bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
663
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
664
  	help
01dd2fbf0   Matt LaPlante   typo fixes
665
666
  	  If enabled, the frequently called do_irq dispatcher function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
667
668
669
670
  
  config CORE_TIMER_IRQ_L1
  	bool "Locate frequently called timer_interrupt() function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
671
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
672
  	help
01dd2fbf0   Matt LaPlante   typo fixes
673
674
  	  If enabled, the frequently called timer_interrupt() function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
675
676
677
678
  
  config IDLE_L1
  	bool "Locate frequently idle function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
679
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
680
  	help
01dd2fbf0   Matt LaPlante   typo fixes
681
682
  	  If enabled, the frequently called idle function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
683
684
685
686
  
  config SCHEDULE_L1
  	bool "Locate kernel schedule function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
687
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
688
  	help
01dd2fbf0   Matt LaPlante   typo fixes
689
690
  	  If enabled, the frequently called kernel schedule is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
691
692
693
694
  
  config ARITHMETIC_OPS_L1
  	bool "Locate kernel owned arithmetic functions in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
695
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
696
  	help
01dd2fbf0   Matt LaPlante   typo fixes
697
698
  	  If enabled, arithmetic functions are linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
699
700
701
702
  
  config ACCESS_OK_L1
  	bool "Locate access_ok function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
703
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
704
  	help
01dd2fbf0   Matt LaPlante   typo fixes
705
706
  	  If enabled, the access_ok function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
707
708
709
710
  
  config MEMSET_L1
  	bool "Locate memset function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
711
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
712
  	help
01dd2fbf0   Matt LaPlante   typo fixes
713
714
  	  If enabled, the memset function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
715
716
717
718
  
  config MEMCPY_L1
  	bool "Locate memcpy function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
719
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
720
  	help
01dd2fbf0   Matt LaPlante   typo fixes
721
722
  	  If enabled, the memcpy function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
723

479ba6035   Robin Getz   Blackfin: move st...
724
725
726
  config STRCMP_L1
  	bool "locate strcmp function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
727
  	depends on !SMP
479ba6035   Robin Getz   Blackfin: move st...
728
729
730
731
732
733
734
  	help
  	  If enabled, the strcmp function is linked
  	  into L1 instruction memory (less latency).
  
  config STRNCMP_L1
  	bool "locate strncmp function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
735
  	depends on !SMP
479ba6035   Robin Getz   Blackfin: move st...
736
737
738
739
740
741
742
  	help
  	  If enabled, the strncmp function is linked
  	  into L1 instruction memory (less latency).
  
  config STRCPY_L1
  	bool "locate strcpy function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
743
  	depends on !SMP
479ba6035   Robin Getz   Blackfin: move st...
744
745
746
747
748
749
750
  	help
  	  If enabled, the strcpy function is linked
  	  into L1 instruction memory (less latency).
  
  config STRNCPY_L1
  	bool "locate strncpy function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
751
  	depends on !SMP
479ba6035   Robin Getz   Blackfin: move st...
752
753
754
  	help
  	  If enabled, the strncpy function is linked
  	  into L1 instruction memory (less latency).
1394f0322   Bryan Wu   blackfin architec...
755
756
757
  config SYS_BFIN_SPINLOCK_L1
  	bool "Locate sys_bfin_spinlock function in L1 Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
758
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
759
  	help
01dd2fbf0   Matt LaPlante   typo fixes
760
761
  	  If enabled, sys_bfin_spinlock function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
762
763
764
765
  
  config IP_CHECKSUM_L1
  	bool "Locate IP Checksum function in L1 Memory"
  	default n
820b127da   Mike Frysinger   Blackfin: split o...
766
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
767
  	help
01dd2fbf0   Matt LaPlante   typo fixes
768
769
  	  If enabled, the IP Checksum function is linked
  	  into L1 instruction memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
770
771
772
  
  config CACHELINE_ALIGNED_L1
  	bool "Locate cacheline_aligned data to L1 Data Memory"
157cc5aad   Michael Hennerich   Blackfin arch: Di...
773
774
  	default y if !BF54x
  	default n if BF54x
820b127da   Mike Frysinger   Blackfin: split o...
775
  	depends on !SMP && !BF531
1394f0322   Bryan Wu   blackfin architec...
776
  	help
692105b8a   Matt LaPlante   trivial: fix typo...
777
  	  If enabled, cacheline_aligned data is linked
01dd2fbf0   Matt LaPlante   typo fixes
778
  	  into L1 data memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
779
780
781
782
  
  config SYSCALL_TAB_L1
  	bool "Locate Syscall Table L1 Data Memory"
  	default n
820b127da   Mike Frysinger   Blackfin: split o...
783
  	depends on !SMP && !BF531
1394f0322   Bryan Wu   blackfin architec...
784
  	help
01dd2fbf0   Matt LaPlante   typo fixes
785
786
  	  If enabled, the Syscall LUT is linked
  	  into L1 data memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
787
788
789
790
  
  config CPLB_SWITCH_TAB_L1
  	bool "Locate CPLB Switch Tables L1 Data Memory"
  	default n
820b127da   Mike Frysinger   Blackfin: split o...
791
  	depends on !SMP && !BF531
1394f0322   Bryan Wu   blackfin architec...
792
  	help
01dd2fbf0   Matt LaPlante   typo fixes
793
794
  	  If enabled, the CPLB Switch Tables are linked
  	  into L1 data memory. (less latency)
1394f0322   Bryan Wu   blackfin architec...
795

820b127da   Mike Frysinger   Blackfin: split o...
796
797
  config ICACHE_FLUSH_L1
  	bool "Locate icache flush funcs in L1 Inst Memory"
74181295f   Mike Frysinger   Blackfin: allow c...
798
799
  	default y
  	help
820b127da   Mike Frysinger   Blackfin: split o...
800
  	  If enabled, the Blackfin icache flushing functions are linked
74181295f   Mike Frysinger   Blackfin: allow c...
801
802
803
804
805
806
  	  into L1 instruction memory.
  
  	  Note that this might be required to address anomalies, but
  	  these functions are pretty small, so it shouldn't be too bad.
  	  If you are using a processor affected by an anomaly, the build
  	  system will double check for you and prevent it.
820b127da   Mike Frysinger   Blackfin: split o...
807
808
809
810
811
812
813
  config DCACHE_FLUSH_L1
  	bool "Locate dcache flush funcs in L1 Inst Memory"
  	default y
  	depends on !SMP
  	help
  	  If enabled, the Blackfin dcache flushing functions are linked
  	  into L1 instruction memory.
ca87b7ad0   Graf Yang   Blackfin arch: ad...
814
815
816
  config APP_STACK_L1
  	bool "Support locating application stack in L1 Scratch Memory"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
817
  	depends on !SMP
ca87b7ad0   Graf Yang   Blackfin arch: ad...
818
819
820
821
822
  	help
  	  If enabled the application stack can be located in L1
  	  scratch memory (less latency).
  
  	  Currently only works with FLAT binaries.
6ad2b84cf   Mike Frysinger   Blackfin arch: ad...
823
824
825
  config EXCEPTION_L1_SCRATCH
  	bool "Locate exception stack in L1 Scratch Memory"
  	default n
820b127da   Mike Frysinger   Blackfin: split o...
826
  	depends on !SMP && !APP_STACK_L1
6ad2b84cf   Mike Frysinger   Blackfin arch: ad...
827
828
829
830
831
832
  	help
  	  Whenever an exception occurs, use the L1 Scratch memory for
  	  stack storage.  You cannot place the stacks of FLAT binaries
  	  in L1 when using this option.
  
  	  If you don't use L1 Scratch, then you should say Y here.
251383c7c   Robin Getz   Blackfin arch: Al...
833
834
835
836
  comment "Speed Optimizations"
  config BFIN_INS_LOWOVERHEAD
  	bool "ins[bwl] low overhead, higher interrupt latency"
  	default y
820b127da   Mike Frysinger   Blackfin: split o...
837
  	depends on !SMP
251383c7c   Robin Getz   Blackfin arch: Al...
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
  	help
  	  Reads on the Blackfin are speculative. In Blackfin terms, this means
  	  they can be interrupted at any time (even after they have been issued
  	  on to the external bus), and re-issued after the interrupt occurs.
  	  For memory - this is not a big deal, since memory does not change if
  	  it sees a read.
  
  	  If a FIFO is sitting on the end of the read, it will see two reads,
  	  when the core only sees one since the FIFO receives both the read
  	  which is cancelled (and not delivered to the core) and the one which
  	  is re-issued (which is delivered to the core).
  
  	  To solve this, interrupts are turned off before reads occur to
  	  I/O space. This option controls which the overhead/latency of
  	  controlling interrupts during this time
  	   "n" turns interrupts off every read
  		(higher overhead, but lower interrupt latency)
  	   "y" turns interrupts off every loop
  		(low overhead, but longer interrupt latency)
  
  	  default behavior is to leave this set to on (type "Y"). If you are experiencing
  	  interrupt latency issues, it is safe and OK to turn this off.
1394f0322   Bryan Wu   blackfin architec...
860
  endmenu
1394f0322   Bryan Wu   blackfin architec...
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
  choice
  	prompt "Kernel executes from"
  	help
  	  Choose the memory type that the kernel will be running in.
  
  config RAMKERNEL
  	bool "RAM"
  	help
  	  The kernel will be resident in RAM when running.
  
  config ROMKERNEL
  	bool "ROM"
  	help
  	  The kernel will be resident in FLASH/ROM when running.
  
  endchoice
56b4f07a0   Mike Frysinger   Blackfin: glue XI...
877
878
879
880
881
  # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
  config XIP_KERNEL
  	bool
  	default y
  	depends on ROMKERNEL
1394f0322   Bryan Wu   blackfin architec...
882
  source "mm/Kconfig"
780431e39   Mike Frysinger   Blackfin arch: cl...
883
884
885
886
887
888
889
890
  config BFIN_GPTIMERS
  	tristate "Enable Blackfin General Purpose Timers API"
  	default n
  	help
  	  Enable support for the General Purpose Timers API.  If you
  	  are unsure, say N.
  
  	  To compile this driver as a module, choose M here: the module
4737f0978   Pavel Machek   trivial: Kconfig:...
891
  	  will be called gptimers.
780431e39   Mike Frysinger   Blackfin arch: cl...
892

006669ec2   Mike Frysinger   Blackfin: pwm: im...
893
894
895
896
897
898
899
900
901
  config HAVE_PWM
  	tristate "Enable PWM API support"
  	depends on BFIN_GPTIMERS
  	help
  	  Enable support for the Pulse Width Modulation framework (as
  	  found in linux/pwm.h).
  
  	  To compile this driver as a module, choose M here: the module
  	  will be called pwm.
1394f0322   Bryan Wu   blackfin architec...
902
  choice
d292b0003   Mike Frysinger   Blackfin arch: dr...
903
  	prompt "Uncached DMA region"
1394f0322   Bryan Wu   blackfin architec...
904
  	default DMA_UNCACHED_1M
86ad79321   Cliff Cai   Blackfin arch: en...
905
906
  config DMA_UNCACHED_4M
  	bool "Enable 4M DMA region"
1394f0322   Bryan Wu   blackfin architec...
907
908
909
910
  config DMA_UNCACHED_2M
  	bool "Enable 2M DMA region"
  config DMA_UNCACHED_1M
  	bool "Enable 1M DMA region"
c45c06596   Barry Song   Blackfin: support...
911
912
913
914
915
916
  config DMA_UNCACHED_512K
  	bool "Enable 512K DMA region"
  config DMA_UNCACHED_256K
  	bool "Enable 256K DMA region"
  config DMA_UNCACHED_128K
  	bool "Enable 128K DMA region"
1394f0322   Bryan Wu   blackfin architec...
917
918
919
920
921
922
  config DMA_UNCACHED_NONE
  	bool "Disable DMA region"
  endchoice
  
  
  comment "Cache Support"
41ba653f2   Jie Zhang   Blackfin: decoupl...
923

3bebca2d2   Robin Getz   Blackfin arch: to...
924
  config BFIN_ICACHE
1394f0322   Bryan Wu   blackfin architec...
925
  	bool "Enable ICACHE"
41ba653f2   Jie Zhang   Blackfin: decoupl...
926
  	default y
41ba653f2   Jie Zhang   Blackfin: decoupl...
927
928
929
930
931
932
933
934
935
  config BFIN_EXTMEM_ICACHEABLE
  	bool "Enable ICACHE for external memory"
  	depends on BFIN_ICACHE
  	default y
  config BFIN_L2_ICACHEABLE
  	bool "Enable ICACHE for L2 SRAM"
  	depends on BFIN_ICACHE
  	depends on BF54x || BF561
  	default n
3bebca2d2   Robin Getz   Blackfin arch: to...
936
  config BFIN_DCACHE
1394f0322   Bryan Wu   blackfin architec...
937
  	bool "Enable DCACHE"
41ba653f2   Jie Zhang   Blackfin: decoupl...
938
  	default y
3bebca2d2   Robin Getz   Blackfin arch: to...
939
  config BFIN_DCACHE_BANKA
1394f0322   Bryan Wu   blackfin architec...
940
  	bool "Enable only 16k BankA DCACHE - BankB is SRAM"
3bebca2d2   Robin Getz   Blackfin arch: to...
941
  	depends on BFIN_DCACHE && !BF531
1394f0322   Bryan Wu   blackfin architec...
942
  	default n
41ba653f2   Jie Zhang   Blackfin: decoupl...
943
944
  config BFIN_EXTMEM_DCACHEABLE
  	bool "Enable DCACHE for external memory"
3bebca2d2   Robin Getz   Blackfin arch: to...
945
  	depends on BFIN_DCACHE
41ba653f2   Jie Zhang   Blackfin: decoupl...
946
947
948
949
950
951
952
  	default y
  choice
  	prompt "External memory DCACHE policy"
  	depends on BFIN_EXTMEM_DCACHEABLE
  	default BFIN_EXTMEM_WRITEBACK if !SMP
  	default BFIN_EXTMEM_WRITETHROUGH if SMP
  config BFIN_EXTMEM_WRITEBACK
1394f0322   Bryan Wu   blackfin architec...
953
  	bool "Write back"
46fa5eece   Graf Yang   Blackfin arch: SM...
954
  	depends on !SMP
1394f0322   Bryan Wu   blackfin architec...
955
956
957
958
959
960
961
962
963
964
965
966
967
968
  	help
  	  Write Back Policy:
  	    Cached data will be written back to SDRAM only when needed.
  	    This can give a nice increase in performance, but beware of
  	    broken drivers that do not properly invalidate/flush their
  	    cache.
  
  	  Write Through Policy:
  	    Cached data will always be written back to SDRAM when the
  	    cache is updated.  This is a completely safe setting, but
  	    performance is worse than Write Back.
  
  	  If you are unsure of the options and you want to be safe,
  	  then go with Write Through.
41ba653f2   Jie Zhang   Blackfin: decoupl...
969
  config BFIN_EXTMEM_WRITETHROUGH
1394f0322   Bryan Wu   blackfin architec...
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
  	bool "Write through"
  	help
  	  Write Back Policy:
  	    Cached data will be written back to SDRAM only when needed.
  	    This can give a nice increase in performance, but beware of
  	    broken drivers that do not properly invalidate/flush their
  	    cache.
  
  	  Write Through Policy:
  	    Cached data will always be written back to SDRAM when the
  	    cache is updated.  This is a completely safe setting, but
  	    performance is worse than Write Back.
  
  	  If you are unsure of the options and you want to be safe,
  	  then go with Write Through.
  
  endchoice
41ba653f2   Jie Zhang   Blackfin: decoupl...
987
988
989
  config BFIN_L2_DCACHEABLE
  	bool "Enable DCACHE for L2 SRAM"
  	depends on BFIN_DCACHE
9c954f894   Sonic Zhang   Blackfin: unify d...
990
  	depends on (BF54x || BF561) && !SMP
41ba653f2   Jie Zhang   Blackfin: decoupl...
991
  	default n
5ba766752   Graf Yang   Blackfin: work ar...
992
  choice
41ba653f2   Jie Zhang   Blackfin: decoupl...
993
994
995
996
  	prompt "L2 SRAM DCACHE policy"
  	depends on BFIN_L2_DCACHEABLE
  	default BFIN_L2_WRITEBACK
  config BFIN_L2_WRITEBACK
5ba766752   Graf Yang   Blackfin: work ar...
997
  	bool "Write back"
5ba766752   Graf Yang   Blackfin: work ar...
998

41ba653f2   Jie Zhang   Blackfin: decoupl...
999
  config BFIN_L2_WRITETHROUGH
5ba766752   Graf Yang   Blackfin: work ar...
1000
  	bool "Write through"
5ba766752   Graf Yang   Blackfin: work ar...
1001
  endchoice
f099f39ac   Sonic Zhang   Blackfin arch: Ma...
1002

41ba653f2   Jie Zhang   Blackfin: decoupl...
1003
1004
  
  comment "Memory Protection Unit"
b97b8a998   Bernd Schmidt   [Blackfin] arch: ...
1005
1006
1007
1008
1009
1010
1011
  config MPU
  	bool "Enable the memory protection unit (EXPERIMENTAL)"
  	default n
  	help
  	  Use the processor's MPU to protect applications from accessing
  	  memory they do not own.  This comes at a performance penalty
  	  and is recommended only for debugging.
692105b8a   Matt LaPlante   trivial: fix typo...
1012
  comment "Asynchronous Memory Configuration"
1394f0322   Bryan Wu   blackfin architec...
1013

ddf416b2b   Mike Frysinger   Blackfin arch: fi...
1014
  menu "EBIU_AMGCTL Global Control"
1394f0322   Bryan Wu   blackfin architec...
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
  config C_AMCKEN
  	bool "Enable CLKOUT"
  	default y
  
  config C_CDPRIO
  	bool "DMA has priority over core for ext. accesses"
  	default n
  
  config C_B0PEN
  	depends on BF561
  	bool "Bank 0 16 bit packing enable"
  	default y
  
  config C_B1PEN
  	depends on BF561
  	bool "Bank 1 16 bit packing enable"
  	default y
  
  config C_B2PEN
  	depends on BF561
  	bool "Bank 2 16 bit packing enable"
  	default y
  
  config C_B3PEN
  	depends on BF561
  	bool "Bank 3 16 bit packing enable"
  	default n
  
  choice
692105b8a   Matt LaPlante   trivial: fix typo...
1044
  	prompt "Enable Asynchronous Memory Banks"
1394f0322   Bryan Wu   blackfin architec...
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
  	default C_AMBEN_ALL
  
  config C_AMBEN
  	bool "Disable All Banks"
  
  config C_AMBEN_B0
  	bool "Enable Bank 0"
  
  config C_AMBEN_B0_B1
  	bool "Enable Bank 0 & 1"
  
  config C_AMBEN_B0_B1_B2
  	bool "Enable Bank 0 & 1 & 2"
  
  config C_AMBEN_ALL
  	bool "Enable All Banks"
  endchoice
  endmenu
  
  menu "EBIU_AMBCTL Control"
  config BANK_0
c8342f872   Mike Frysinger   Blackfin: add som...
1066
  	hex "Bank 0 (AMBCTL0.L)"
1394f0322   Bryan Wu   blackfin architec...
1067
  	default 0x7BB0
c8342f872   Mike Frysinger   Blackfin: add som...
1068
1069
1070
  	help
  	  These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  	  used to control the Asynchronous Memory Bank 0 settings.
1394f0322   Bryan Wu   blackfin architec...
1071
1072
  
  config BANK_1
c8342f872   Mike Frysinger   Blackfin: add som...
1073
  	hex "Bank 1 (AMBCTL0.H)"
1394f0322   Bryan Wu   blackfin architec...
1074
  	default 0x7BB0
197fba568   Michael Hennerich   [Blackfin] arch: ...
1075
  	default 0x5558 if BF54x
c8342f872   Mike Frysinger   Blackfin: add som...
1076
1077
1078
  	help
  	  These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  	  used to control the Asynchronous Memory Bank 1 settings.
1394f0322   Bryan Wu   blackfin architec...
1079
1080
  
  config BANK_2
c8342f872   Mike Frysinger   Blackfin: add som...
1081
  	hex "Bank 2 (AMBCTL1.L)"
1394f0322   Bryan Wu   blackfin architec...
1082
  	default 0x7BB0
c8342f872   Mike Frysinger   Blackfin: add som...
1083
1084
1085
  	help
  	  These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  	  used to control the Asynchronous Memory Bank 2 settings.
1394f0322   Bryan Wu   blackfin architec...
1086
1087
  
  config BANK_3
c8342f872   Mike Frysinger   Blackfin: add som...
1088
  	hex "Bank 3 (AMBCTL1.H)"
1394f0322   Bryan Wu   blackfin architec...
1089
  	default 0x99B3
c8342f872   Mike Frysinger   Blackfin: add som...
1090
1091
1092
  	help
  	  These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  	  used to control the Asynchronous Memory Bank 3 settings.
1394f0322   Bryan Wu   blackfin architec...
1093
  endmenu
e40540b30   Sonic Zhang   Blackfin arch: fi...
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
  config EBIU_MBSCTLVAL
  	hex "EBIU Bank Select Control Register"
  	depends on BF54x
  	default 0
  
  config EBIU_MODEVAL
  	hex "Flash Memory Mode Control Register"
  	depends on BF54x
  	default 1
  
  config EBIU_FCTLVAL
  	hex "Flash Memory Bank Control Register"
  	depends on BF54x
  	default 6
1394f0322   Bryan Wu   blackfin architec...
1108
1109
1110
1111
1112
1113
1114
  endmenu
  
  #############################################################################
  menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  
  config PCI
  	bool "PCI support"
a95ca3b2b   Adrian Bunk   Blackfin arch: le...
1115
  	depends on BROKEN
1394f0322   Bryan Wu   blackfin architec...
1116
1117
1118
1119
  	help
  	  Support for PCI bus.
  
  source "drivers/pci/Kconfig"
1394f0322   Bryan Wu   blackfin architec...
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
  source "drivers/pcmcia/Kconfig"
  
  source "drivers/pci/hotplug/Kconfig"
  
  endmenu
  
  menu "Executable file formats"
  
  source "fs/Kconfig.binfmt"
  
  endmenu
  
  menu "Power management options"
ad46163ac   Graf Yang   Blackfin: SMP por...
1133

1394f0322   Bryan Wu   blackfin architec...
1134
  source "kernel/power/Kconfig"
f4cb57007   Johannes Berg   Suspend: Clean up...
1135
1136
  config ARCH_SUSPEND_POSSIBLE
  	def_bool y
f4cb57007   Johannes Berg   Suspend: Clean up...
1137

1394f0322   Bryan Wu   blackfin architec...
1138
  choice
1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1139
  	prompt "Standby Power Saving Mode"
1394f0322   Bryan Wu   blackfin architec...
1140
  	depends on PM
cfefe3c68   Michael Hennerich   [Blackfin] arch: ...
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
  	default PM_BFIN_SLEEP_DEEPER
  config  PM_BFIN_SLEEP_DEEPER
  	bool "Sleep Deeper"
  	help
  	  Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  	  power dissipation by disabling the clock to the processor core (CCLK).
  	  Furthermore, Standby sets the internal power supply voltage (VDDINT)
  	  to 0.85 V to provide the greatest power savings, while preserving the
  	  processor state.
  	  The PLL and system clock (SCLK) continue to operate at a very low
  	  frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  	  the SDRAM is put into Self Refresh Mode. Typically an external event
  	  such as GPIO interrupt or RTC activity wakes up the processor.
  	  Various Peripherals such as UART, SPORT, PPI may not function as
  	  normal during Sleep Deeper, due to the reduced SCLK frequency.
  	  When in the sleep mode, system DMA access to L1 memory is not supported.
1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1157
  	  If unsure, select "Sleep Deeper".
cfefe3c68   Michael Hennerich   [Blackfin] arch: ...
1158
1159
1160
1161
1162
1163
1164
  config  PM_BFIN_SLEEP
  	bool "Sleep"
  	help
  	  Sleep Mode (High Power Savings) - The sleep mode reduces power
  	  dissipation by disabling the clock to the processor core (CCLK).
  	  The PLL and system clock (SCLK), however, continue to operate in
  	  this mode. Typically an external event or RTC activity will wake
1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1165
1166
1167
1168
  	  up the processor. When in the sleep mode, system DMA access to L1
  	  memory is not supported.
  
  	  If unsure, select "Sleep Deeper".
cfefe3c68   Michael Hennerich   [Blackfin] arch: ...
1169
  endchoice
1394f0322   Bryan Wu   blackfin architec...
1170

1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1171
1172
  comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  	depends on PM
1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1173
1174
  config PM_BFIN_WAKE_PH6
  	bool "Allow Wake-Up from on-chip PHY or PH6 GP"
2f6f4bcdd   Bryan Wu   Blackfin arch: ad...
1175
  	depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1176
1177
1178
  	default n
  	help
  	  Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1efc80b53   Michael Hennerich   Blackfin arch: Fu...
1179
1180
1181
1182
1183
1184
  config PM_BFIN_WAKE_GP
  	bool "Allow Wake-Up from GPIOs"
  	depends on PM && BF54x
  	default n
  	help
  	  Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
199862892   Michael Hennerich   Blackfin arch: PM...
1185
1186
1187
1188
1189
  	  (all processors, except ADSP-BF549). This option sets
  	  the general-purpose wake-up enable (GPWE) control bit to enable
  	  wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  	  On ADSP-BF549 this option enables the the same functionality on the
  	  /MRXON pin also PH7.
1394f0322   Bryan Wu   blackfin architec...
1190
  endmenu
1394f0322   Bryan Wu   blackfin architec...
1191
1192
1193
  menu "CPU Frequency scaling"
  
  source "drivers/cpufreq/Kconfig"
5ad2ca5fb   Michael Hennerich   Blackfin arch: Fi...
1194
1195
1196
1197
1198
  config BFIN_CPU_FREQ
  	bool
  	depends on CPU_FREQ
  	select CPU_FREQ_TABLE
  	default y
14b03204c   Michael Hennerich   [Blackfin] arch: ...
1199
1200
  config CPU_VOLTAGE
  	bool "CPU Voltage scaling"
73feb5c09   Michael Hennerich   Blackfin arch: fi...
1201
  	depends on EXPERIMENTAL
14b03204c   Michael Hennerich   [Blackfin] arch: ...
1202
1203
1204
1205
1206
  	depends on CPU_FREQ
  	default n
  	help
  	  Say Y here if you want CPU voltage scaling according to the CPU frequency.
  	  This option violates the PLL BYPASS recommendation in the Blackfin Processor
73feb5c09   Michael Hennerich   Blackfin arch: fi...
1207
  	  manuals. There is a theoretical risk that during VDDINT transitions
14b03204c   Michael Hennerich   [Blackfin] arch: ...
1208
  	  the PLL may unlock.
1394f0322   Bryan Wu   blackfin architec...
1209
  endmenu
1394f0322   Bryan Wu   blackfin architec...
1210
1211
1212
  source "net/Kconfig"
  
  source "drivers/Kconfig"
872d024b4   Mike Frysinger   Blackfin: pull in...
1213
  source "drivers/firmware/Kconfig"
1394f0322   Bryan Wu   blackfin architec...
1214
  source "fs/Kconfig"
74ce8322b   Mike Frysinger   Blackfin arch: sp...
1215
  source "arch/blackfin/Kconfig.debug"
1394f0322   Bryan Wu   blackfin architec...
1216
1217
1218
1219
1220
1221
  
  source "security/Kconfig"
  
  source "crypto/Kconfig"
  
  source "lib/Kconfig"