Blame view
arch/mn10300/mm/cache.inc
2.65 KB
b75bb2365 MN10300: The icac... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 |
/* MN10300 CPU core caching macros -*- asm -*- * * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. * Written by David Howells (dhowells@redhat.com) * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public Licence * as published by the Free Software Foundation; either version * 2 of the Licence, or (at your option) any later version. */ ############################################################################### # # Invalidate the instruction cache. # A0: Should hold CHCTR # D0: Should have been read from CHCTR # D1: Will be clobbered # # On some cores it is necessary to disable the icache whilst we do this. # ############################################################################### .macro invalidate_icache,disable_irq #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) .if \disable_irq # don't want an interrupt routine seeing a disabled cache mov epsw,d1 and ~EPSW_IE,epsw or EPSW_NMID,epsw nop nop .endif # disable the icache and ~CHCTR_ICEN,d0 movhu d0,(a0) # and wait for it to calm down setlb movhu (a0),d0 btst CHCTR_ICBUSY,d0 lne # invalidate or CHCTR_ICINV,d0 movhu d0,(a0) # wait for the cache to finish setlb movhu (a0),d0 btst CHCTR_ICBUSY,d0 lne # and reenable it or CHCTR_ICEN,d0 movhu d0,(a0) movhu (a0),d0 .if \disable_irq LOCAL_IRQ_RESTORE(d1) .endif #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ # invalidate or CHCTR_ICINV,d0 movhu d0,(a0) movhu (a0),d0 #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ .endm ############################################################################### # # Invalidate the data cache. # A0: Should hold CHCTR # D0: Should have been read from CHCTR # D1: Will be clobbered # # On some cores it is necessary to disable the dcache whilst we do this. # ############################################################################### .macro invalidate_dcache,disable_irq #if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3) .if \disable_irq # don't want an interrupt routine seeing a disabled cache mov epsw,d1 and ~EPSW_IE,epsw or EPSW_NMID,epsw nop nop .endif # disable the dcache and ~CHCTR_DCEN,d0 movhu d0,(a0) # and wait for it to calm down setlb movhu (a0),d0 btst CHCTR_DCBUSY,d0 lne # invalidate or CHCTR_DCINV,d0 movhu d0,(a0) # wait for the cache to finish setlb movhu (a0),d0 btst CHCTR_DCBUSY,d0 lne # and reenable it or CHCTR_DCEN,d0 movhu d0,(a0) movhu (a0),d0 .if \disable_irq LOCAL_IRQ_RESTORE(d1) .endif #else /* CONFIG_AM33_2 || CONFIG_AM33_3 */ # invalidate or CHCTR_DCINV,d0 movhu d0,(a0) movhu (a0),d0 #endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */ .endm |