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arch/powerpc/sysdev/dart_iommu.c
11.8 KB
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/* |
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* arch/powerpc/sysdev/dart_iommu.c |
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* |
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
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* Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, * IBM Corporation |
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* * Based on pSeries_iommu.c: * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
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* |
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* Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. * |
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* |
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* This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ |
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#include <linux/init.h> #include <linux/types.h> |
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#include <linux/mm.h> #include <linux/spinlock.h> #include <linux/string.h> #include <linux/pci.h> #include <linux/dma-mapping.h> #include <linux/vmalloc.h> |
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#include <linux/suspend.h> |
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#include <linux/memblock.h> |
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#include <linux/gfp.h> |
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#include <asm/io.h> #include <asm/prom.h> |
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#include <asm/iommu.h> #include <asm/pci-bridge.h> #include <asm/machdep.h> #include <asm/abs_addr.h> #include <asm/cacheflush.h> |
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#include <asm/ppc-pci.h> |
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|
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#include "dart.h" |
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/* Physical base address and size of the DART table */ unsigned long dart_tablebase; /* exported to htab_initialize */ static unsigned long dart_tablesize; /* Virtual base address of the DART table */ static u32 *dart_vbase; |
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#ifdef CONFIG_PM static u32 *dart_copy; #endif |
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/* Mapped base address for the dart */ |
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static unsigned int __iomem *dart; |
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/* Dummy val that entries are set to when unused */ static unsigned int dart_emptyval; |
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static struct iommu_table iommu_table_dart; static int iommu_table_dart_inited; |
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static int dart_dirty; |
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static int dart_is_u4; |
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|
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#define DART_U4_BYPASS_BASE 0x8000000000ull |
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#define DBG(...) static inline void dart_tlb_invalidate_all(void) { unsigned long l = 0; |
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unsigned int reg, inv_bit; |
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unsigned long limit; DBG("dart: flush "); /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the * control register and wait for it to clear. * * Gotcha: Sometimes, the DART won't detect that the bit gets * set. If so, clear it and set it again. |
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*/ |
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limit = 0; |
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inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
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retry: |
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l = 0; |
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reg = DART_IN(DART_CNTL); reg |= inv_bit; DART_OUT(DART_CNTL, reg); while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) |
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l++; |
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if (l == (1L << limit)) { |
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if (limit < 4) { limit++; |
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reg = DART_IN(DART_CNTL); reg &= ~inv_bit; |
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DART_OUT(DART_CNTL, reg); |
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goto retry; } else |
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panic("DART: TLB did not flush after waiting a long " |
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"time. Buggy U3 ?"); } } |
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static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) { unsigned int reg; unsigned int l, limit; reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | (bus_rpn & DART_CNTL_U4_IONE_MASK); DART_OUT(DART_CNTL, reg); limit = 0; wait_more: l = 0; while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { rmb(); l++; } if (l == (1L << limit)) { if (limit < 4) { limit++; goto wait_more; } else panic("DART: TLB did not flush after waiting a long " "time. Buggy U4 ?"); } } |
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static void dart_flush(struct iommu_table *tbl) { |
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mb(); |
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if (dart_dirty) { |
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dart_tlb_invalidate_all(); |
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dart_dirty = 0; } |
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} |
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static int dart_build(struct iommu_table *tbl, long index, |
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long npages, unsigned long uaddr, |
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enum dma_data_direction direction, struct dma_attrs *attrs) |
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{ unsigned int *dp; unsigned int rpn; |
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long l; |
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DBG("dart: build at: %lx, %lx, addr: %x ", index, npages, uaddr); dp = ((unsigned int*)tbl->it_base) + index; |
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|
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/* On U3, all memory is contiguous, so we can move this |
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* out of the loop. */ |
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l = npages; while (l--) { |
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rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; |
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*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); |
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uaddr += DART_PAGE_SIZE; |
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} |
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/* make sure all updates have reached memory */ mb(); in_be32((unsigned __iomem *)dp); mb(); |
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if (dart_is_u4) { rpn = index; |
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while (npages--) dart_tlb_invalidate_one(rpn++); } else { dart_dirty = 1; } |
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return 0; |
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} static void dart_free(struct iommu_table *tbl, long index, long npages) { unsigned int *dp; |
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|
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/* We don't worry about flushing the TLB cache. The only drawback of * not doing it is that we won't catch buggy device drivers doing * bad DMAs, but then no 32-bit architecture ever does either. */ DBG("dart: free at: %lx, %lx ", index, npages); dp = ((unsigned int *)tbl->it_base) + index; |
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|
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while (npages--) *(dp++) = dart_emptyval; } |
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static int __init dart_init(struct device_node *dart_node) |
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{ |
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unsigned int i; |
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unsigned long tmp, base, size; struct resource r; |
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if (dart_tablebase == 0 || dart_tablesize == 0) { |
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printk(KERN_INFO "DART: table not allocated, using " "direct DMA "); |
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return -ENODEV; } |
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if (of_address_to_resource(dart_node, 0, &r)) panic("DART: can't get register base ! "); |
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/* Make sure nothing from the DART range remains in the CPU cache * from a previous mapping that existed before the kernel took * over */ |
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flush_dcache_phys_range(dart_tablebase, dart_tablebase + dart_tablesize); |
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/* Allocate a spare page to map all invalid DART pages. We need to do * that to work around what looks like a problem with the HT bridge * prefetching into invalid pages and corrupting data */ |
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tmp = memblock_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
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dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & DARTMAP_RPNMASK); |
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|
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/* Map in DART registers */ |
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dart = ioremap(r.start, resource_size(&r)); |
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if (dart == NULL) |
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panic("DART: Cannot map registers!"); |
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|
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/* Map in DART table */ |
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dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); /* Fill initial table */ for (i = 0; i < dart_tablesize/4; i++) dart_vbase[i] = dart_emptyval; /* Initialize DART with table base and enable it. */ |
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base = dart_tablebase >> DART_PAGE_SHIFT; size = dart_tablesize >> DART_PAGE_SHIFT; if (dart_is_u4) { |
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size &= DART_SIZE_U4_SIZE_MASK; |
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DART_OUT(DART_BASE_U4, base); DART_OUT(DART_SIZE_U4, size); DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); } else { |
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size &= DART_CNTL_U3_SIZE_MASK; |
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DART_OUT(DART_CNTL, DART_CNTL_U3_ENABLE | (base << DART_CNTL_U3_BASE_SHIFT) | (size << DART_CNTL_U3_SIZE_SHIFT)); } |
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/* Invalidate DART to get rid of possible stale TLBs */ dart_tlb_invalidate_all(); |
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printk(KERN_INFO "DART IOMMU initialized for %s type chipset ", dart_is_u4 ? "U4" : "U3"); |
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return 0; } |
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static void iommu_table_dart_setup(void) |
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{ |
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iommu_table_dart.it_busno = 0; iommu_table_dart.it_offset = 0; |
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/* it_size is in number of entries */ |
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iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
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/* Initialize the common IOMMU code */ |
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iommu_table_dart.it_base = (unsigned long)dart_vbase; iommu_table_dart.it_index = 0; iommu_table_dart.it_blocksize = 1; |
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iommu_init_table(&iommu_table_dart, -1); |
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/* Reserve the last page of the DART to avoid possible prefetch * past the DART mapped area */ |
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set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
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} |
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static void dma_dev_setup_dart(struct device *dev) |
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{ |
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/* We only have one iommu table on the mac for now, which makes * things simple. Setup all PCI devices to point to this table |
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*/ |
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if (get_dma_ops(dev) == &dma_direct_ops) set_dma_offset(dev, DART_U4_BYPASS_BASE); else set_iommu_table_base(dev, &iommu_table_dart); } static void pci_dma_dev_setup_dart(struct pci_dev *dev) { dma_dev_setup_dart(&dev->dev); |
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} |
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static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
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{ |
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if (!iommu_table_dart_inited) { iommu_table_dart_inited = 1; iommu_table_dart_setup(); |
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} |
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} |
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static bool dart_device_on_pcie(struct device *dev) { struct device_node *np = of_node_get(dev->of_node); while(np) { if (of_device_is_compatible(np, "U4-pcie") || of_device_is_compatible(np, "u4-pcie")) { of_node_put(np); return true; } np = of_get_next_parent(np); } return false; } static int dart_dma_set_mask(struct device *dev, u64 dma_mask) { if (!dev->dma_mask || !dma_supported(dev, dma_mask)) return -EIO; /* U4 supports a DART bypass, we use it for 64-bit capable * devices to improve performances. However, that only works * for devices connected to U4 own PCIe interface, not bridged * through hypertransport. We need the device to support at * least 40 bits of addresses. */ if (dart_device_on_pcie(dev) && dma_mask >= DMA_BIT_MASK(40)) { dev_info(dev, "Using 64-bit DMA iommu bypass "); set_dma_ops(dev, &dma_direct_ops); } else { dev_info(dev, "Using 32-bit DMA via iommu "); set_dma_ops(dev, &dma_iommu_ops); } dma_dev_setup_dart(dev); *dev->dma_mask = dma_mask; return 0; } |
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void __init iommu_init_early_dart(void) |
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{ struct device_node *dn; /* Find the DART in the device-tree */ dn = of_find_compatible_node(NULL, "dart", "u3-dart"); |
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if (dn == NULL) { dn = of_find_compatible_node(NULL, "dart", "u4-dart"); if (dn == NULL) |
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return; /* use default direct_dma_ops */ |
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dart_is_u4 = 1; } |
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|
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/* Initialize the DART HW */ if (dart_init(dn) != 0) goto bail; |
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/* Setup low level TCE operations for the core IOMMU code */ ppc_md.tce_build = dart_build; ppc_md.tce_free = dart_free; ppc_md.tce_flush = dart_flush; |
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/* Setup bypass if supported */ if (dart_is_u4) ppc_md.dma_set_mask = dart_dma_set_mask; |
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|
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; /* Setup pci_dma ops */ set_pci_dma_ops(&dma_iommu_ops); return; |
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bail: /* If init failed, use direct iommu and null setup functions */ |
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ppc_md.pci_dma_dev_setup = NULL; ppc_md.pci_dma_bus_setup = NULL; |
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/* Setup pci_dma ops */ |
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set_pci_dma_ops(&dma_direct_ops); |
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} |
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#ifdef CONFIG_PM static void iommu_dart_save(void) { memcpy(dart_copy, dart_vbase, 2*1024*1024); } static void iommu_dart_restore(void) { memcpy(dart_vbase, dart_copy, 2*1024*1024); dart_tlb_invalidate_all(); } static int __init iommu_init_late_dart(void) { unsigned long tbasepfn; struct page *p; /* if no dart table exists then we won't need to save it * and the area has also not been reserved */ if (!dart_tablebase) return 0; tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT; register_nosave_region_late(tbasepfn, tbasepfn + ((1<<24) >> PAGE_SHIFT)); /* For suspend we need to copy the dart contents because * it is not part of the regular mapping (see above) and * thus not saved automatically. The memory for this copy * must be allocated early because we need 2 MB. */ p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT); BUG_ON(!p); dart_copy = page_address(p); ppc_md.iommu_save = iommu_dart_save; ppc_md.iommu_restore = iommu_dart_restore; return 0; } late_initcall(iommu_init_late_dart); #endif |
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|
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void __init alloc_dart_table(void) |
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{ |
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/* Only reserve DART space if machine has more than 1GB of RAM |
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* or if requested with iommu=on on cmdline. |
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* * 1GB of RAM is picked as limit because some default devices * (i.e. Airport Extreme) have 30 bit address range limits. |
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*/ |
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if (iommu_is_off) return; |
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439 |
if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull) |
1da177e4c Linux-2.6.12-rc2 |
440 441 442 443 444 445 446 447 |
return; /* 512 pages (2MB) is max DART tablesize. */ dart_tablesize = 1UL << 21; /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we * will blow up an entire large page anyway in the kernel mapping */ dart_tablebase = (unsigned long) |
95f72d1ed lmb: rename to me... |
448 |
abs_to_virt(memblock_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); |
1da177e4c Linux-2.6.12-rc2 |
449 |
|
1beb6a7d6 [PATCH] powerpc: ... |
450 451 |
printk(KERN_INFO "DART table allocated at: %lx ", dart_tablebase); |
1da177e4c Linux-2.6.12-rc2 |
452 |
} |