Blame view
arch/powerpc/sysdev/uic.c
8.52 KB
e58923ed1 [POWERPC] Add arc... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 |
/* * arch/powerpc/sysdev/uic.c * * IBM PowerPC 4xx Universal Interrupt Controller * * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ #include <linux/kernel.h> #include <linux/init.h> #include <linux/errno.h> #include <linux/reboot.h> #include <linux/slab.h> #include <linux/stddef.h> #include <linux/sched.h> #include <linux/signal.h> |
e58923ed1 [POWERPC] Add arc... |
21 22 23 24 25 |
#include <linux/device.h> #include <linux/bootmem.h> #include <linux/spinlock.h> #include <linux/irq.h> #include <linux/interrupt.h> |
868afce21 [POWERPC] Fix irq... |
26 |
#include <linux/kernel_stat.h> |
e58923ed1 [POWERPC] Add arc... |
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 |
#include <asm/irq.h> #include <asm/io.h> #include <asm/prom.h> #include <asm/dcr.h> #define NR_UIC_INTS 32 #define UIC_SR 0x0 #define UIC_ER 0x2 #define UIC_CR 0x3 #define UIC_PR 0x4 #define UIC_TR 0x5 #define UIC_MSR 0x6 #define UIC_VR 0x7 #define UIC_VCR 0x8 |
e58923ed1 [POWERPC] Add arc... |
42 43 44 45 46 |
struct uic *primary_uic; struct uic { int index; int dcrbase; |
bccc2f7b4 locking, powerpc:... |
47 |
raw_spinlock_t lock; |
e58923ed1 [POWERPC] Add arc... |
48 49 50 |
/* The remapper for this UIC */ struct irq_host *irqhost; |
e58923ed1 [POWERPC] Add arc... |
51 |
}; |
42a07ae29 powerpc: sysdev/u... |
52 |
static void uic_unmask_irq(struct irq_data *d) |
e58923ed1 [POWERPC] Add arc... |
53 |
{ |
42a07ae29 powerpc: sysdev/u... |
54 |
struct uic *uic = irq_data_get_irq_chip_data(d); |
476eb4912 powerpc/irq: Stop... |
55 |
unsigned int src = irqd_to_hwirq(d); |
e58923ed1 [POWERPC] Add arc... |
56 |
unsigned long flags; |
c80905637 [POWERPC] 4xx: ma... |
57 |
u32 er, sr; |
e58923ed1 [POWERPC] Add arc... |
58 |
|
c80905637 [POWERPC] 4xx: ma... |
59 |
sr = 1 << (31-src); |
bccc2f7b4 locking, powerpc:... |
60 |
raw_spin_lock_irqsave(&uic->lock, flags); |
c80905637 [POWERPC] 4xx: ma... |
61 |
/* ack level-triggered interrupts here */ |
1ac06cdad powerpc: uic: Cle... |
62 |
if (irqd_is_level_type(d)) |
c80905637 [POWERPC] 4xx: ma... |
63 |
mtdcr(uic->dcrbase + UIC_SR, sr); |
e58923ed1 [POWERPC] Add arc... |
64 |
er = mfdcr(uic->dcrbase + UIC_ER); |
c80905637 [POWERPC] 4xx: ma... |
65 |
er |= sr; |
e58923ed1 [POWERPC] Add arc... |
66 |
mtdcr(uic->dcrbase + UIC_ER, er); |
bccc2f7b4 locking, powerpc:... |
67 |
raw_spin_unlock_irqrestore(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
68 |
} |
42a07ae29 powerpc: sysdev/u... |
69 |
static void uic_mask_irq(struct irq_data *d) |
e58923ed1 [POWERPC] Add arc... |
70 |
{ |
42a07ae29 powerpc: sysdev/u... |
71 |
struct uic *uic = irq_data_get_irq_chip_data(d); |
476eb4912 powerpc/irq: Stop... |
72 |
unsigned int src = irqd_to_hwirq(d); |
e58923ed1 [POWERPC] Add arc... |
73 74 |
unsigned long flags; u32 er; |
bccc2f7b4 locking, powerpc:... |
75 |
raw_spin_lock_irqsave(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
76 77 78 |
er = mfdcr(uic->dcrbase + UIC_ER); er &= ~(1 << (31 - src)); mtdcr(uic->dcrbase + UIC_ER, er); |
bccc2f7b4 locking, powerpc:... |
79 |
raw_spin_unlock_irqrestore(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
80 |
} |
42a07ae29 powerpc: sysdev/u... |
81 |
static void uic_ack_irq(struct irq_data *d) |
e58923ed1 [POWERPC] Add arc... |
82 |
{ |
42a07ae29 powerpc: sysdev/u... |
83 |
struct uic *uic = irq_data_get_irq_chip_data(d); |
476eb4912 powerpc/irq: Stop... |
84 |
unsigned int src = irqd_to_hwirq(d); |
e58923ed1 [POWERPC] Add arc... |
85 |
unsigned long flags; |
bccc2f7b4 locking, powerpc:... |
86 |
raw_spin_lock_irqsave(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
87 |
mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); |
bccc2f7b4 locking, powerpc:... |
88 |
raw_spin_unlock_irqrestore(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
89 |
} |
42a07ae29 powerpc: sysdev/u... |
90 |
static void uic_mask_ack_irq(struct irq_data *d) |
b8b799a49 [POWERPC] 4xx: UI... |
91 |
{ |
42a07ae29 powerpc: sysdev/u... |
92 |
struct uic *uic = irq_data_get_irq_chip_data(d); |
476eb4912 powerpc/irq: Stop... |
93 |
unsigned int src = irqd_to_hwirq(d); |
b8b799a49 [POWERPC] 4xx: UI... |
94 95 96 97 |
unsigned long flags; u32 er, sr; sr = 1 << (31-src); |
bccc2f7b4 locking, powerpc:... |
98 |
raw_spin_lock_irqsave(&uic->lock, flags); |
b8b799a49 [POWERPC] 4xx: UI... |
99 100 101 |
er = mfdcr(uic->dcrbase + UIC_ER); er &= ~sr; mtdcr(uic->dcrbase + UIC_ER, er); |
c80905637 [POWERPC] 4xx: ma... |
102 103 104 105 106 107 108 109 |
/* On the UIC, acking (i.e. clearing the SR bit) * a level irq will have no effect if the interrupt * is still asserted by the device, even if * the interrupt is already masked. Therefore * we only ack the egde interrupts here, while * level interrupts are ack'ed after the actual * isr call in the uic_unmask_irq() */ |
1ac06cdad powerpc: uic: Cle... |
110 |
if (!irqd_is_level_type(d)) |
c80905637 [POWERPC] 4xx: ma... |
111 |
mtdcr(uic->dcrbase + UIC_SR, sr); |
bccc2f7b4 locking, powerpc:... |
112 |
raw_spin_unlock_irqrestore(&uic->lock, flags); |
b8b799a49 [POWERPC] 4xx: UI... |
113 |
} |
42a07ae29 powerpc: sysdev/u... |
114 |
static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
e58923ed1 [POWERPC] Add arc... |
115 |
{ |
42a07ae29 powerpc: sysdev/u... |
116 |
struct uic *uic = irq_data_get_irq_chip_data(d); |
476eb4912 powerpc/irq: Stop... |
117 |
unsigned int src = irqd_to_hwirq(d); |
e58923ed1 [POWERPC] Add arc... |
118 119 120 121 122 123 |
unsigned long flags; int trigger, polarity; u32 tr, pr, mask; switch (flow_type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_NONE: |
42a07ae29 powerpc: sysdev/u... |
124 |
uic_mask_irq(d); |
e58923ed1 [POWERPC] Add arc... |
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 |
return 0; case IRQ_TYPE_EDGE_RISING: trigger = 1; polarity = 1; break; case IRQ_TYPE_EDGE_FALLING: trigger = 1; polarity = 0; break; case IRQ_TYPE_LEVEL_HIGH: trigger = 0; polarity = 1; break; case IRQ_TYPE_LEVEL_LOW: trigger = 0; polarity = 0; break; default: return -EINVAL; } mask = ~(1 << (31 - src)); |
bccc2f7b4 locking, powerpc:... |
144 |
raw_spin_lock_irqsave(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
145 146 147 148 149 150 151 |
tr = mfdcr(uic->dcrbase + UIC_TR); pr = mfdcr(uic->dcrbase + UIC_PR); tr = (tr & mask) | (trigger << (31-src)); pr = (pr & mask) | (polarity << (31-src)); mtdcr(uic->dcrbase + UIC_PR, pr); mtdcr(uic->dcrbase + UIC_TR, tr); |
bccc2f7b4 locking, powerpc:... |
152 |
raw_spin_unlock_irqrestore(&uic->lock, flags); |
e58923ed1 [POWERPC] Add arc... |
153 154 155 156 157 |
return 0; } static struct irq_chip uic_irq_chip = { |
fc380c0c8 powerpc: Remove w... |
158 |
.name = "UIC", |
42a07ae29 powerpc: sysdev/u... |
159 160 161 162 163 |
.irq_unmask = uic_unmask_irq, .irq_mask = uic_mask_irq, .irq_mask_ack = uic_mask_ack_irq, .irq_ack = uic_ack_irq, .irq_set_type = uic_set_irq_type, |
e58923ed1 [POWERPC] Add arc... |
164 |
}; |
e58923ed1 [POWERPC] Add arc... |
165 166 167 168 |
static int uic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { struct uic *uic = h->host_data; |
ec775d0e7 powerpc: Convert ... |
169 |
irq_set_chip_data(virq, uic); |
e58923ed1 [POWERPC] Add arc... |
170 171 |
/* Despite the name, handle_level_irq() works for both level * and edge irqs on UIC. FIXME: check this is correct */ |
ec775d0e7 powerpc: Convert ... |
172 |
irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); |
e58923ed1 [POWERPC] Add arc... |
173 174 |
/* Set default irq type */ |
ec775d0e7 powerpc: Convert ... |
175 |
irq_set_irq_type(virq, IRQ_TYPE_NONE); |
e58923ed1 [POWERPC] Add arc... |
176 177 178 179 180 |
return 0; } static int uic_host_xlate(struct irq_host *h, struct device_node *ct, |
40d50cf7c powerpc: Make "in... |
181 |
const u32 *intspec, unsigned int intsize, |
e58923ed1 [POWERPC] Add arc... |
182 183 184 185 186 187 188 189 190 191 192 |
irq_hw_number_t *out_hwirq, unsigned int *out_type) { /* UIC intspecs must have 2 cells */ BUG_ON(intsize != 2); *out_hwirq = intspec[0]; *out_type = intspec[1]; return 0; } static struct irq_host_ops uic_host_ops = { |
e58923ed1 [POWERPC] Add arc... |
193 194 195 |
.map = uic_host_map, .xlate = uic_host_xlate, }; |
5aac48dc1 [POWERPC] 4xx: re... |
196 |
void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) |
e58923ed1 [POWERPC] Add arc... |
197 |
{ |
ec775d0e7 powerpc: Convert ... |
198 |
struct irq_chip *chip = irq_desc_get_chip(desc); |
1ac06cdad powerpc: uic: Cle... |
199 |
struct irq_data *idata = irq_desc_get_irq_data(desc); |
ec775d0e7 powerpc: Convert ... |
200 |
struct uic *uic = irq_get_handler_data(virq); |
e58923ed1 [POWERPC] Add arc... |
201 202 203 |
u32 msr; int src; int subvirq; |
239007b84 genirq: Convert i... |
204 |
raw_spin_lock(&desc->lock); |
1ac06cdad powerpc: uic: Cle... |
205 206 |
if (irqd_is_level_type(idata)) chip->irq_mask(idata); |
5aac48dc1 [POWERPC] 4xx: re... |
207 |
else |
1ac06cdad powerpc: uic: Cle... |
208 |
chip->irq_mask_ack(idata); |
239007b84 genirq: Convert i... |
209 |
raw_spin_unlock(&desc->lock); |
5aac48dc1 [POWERPC] 4xx: re... |
210 |
|
e58923ed1 [POWERPC] Add arc... |
211 |
msr = mfdcr(uic->dcrbase + UIC_MSR); |
553fdff63 [POWERPC] Improve... |
212 |
if (!msr) /* spurious interrupt */ |
5aac48dc1 [POWERPC] 4xx: re... |
213 |
goto uic_irq_ret; |
553fdff63 [POWERPC] Improve... |
214 |
|
e58923ed1 [POWERPC] Add arc... |
215 216 217 218 |
src = 32 - ffs(msr); subvirq = irq_linear_revmap(uic->irqhost, src); generic_handle_irq(subvirq); |
5aac48dc1 [POWERPC] 4xx: re... |
219 |
uic_irq_ret: |
239007b84 genirq: Convert i... |
220 |
raw_spin_lock(&desc->lock); |
1ac06cdad powerpc: uic: Cle... |
221 222 223 224 |
if (irqd_is_level_type(idata)) chip->irq_ack(idata); if (!irqd_irq_disabled(idata) && chip->irq_unmask) chip->irq_unmask(idata); |
239007b84 genirq: Convert i... |
225 |
raw_spin_unlock(&desc->lock); |
e58923ed1 [POWERPC] Add arc... |
226 227 228 229 230 231 232 |
} static struct uic * __init uic_init_one(struct device_node *node) { struct uic *uic; const u32 *indexp, *dcrreg; int len; |
55b61fec2 [POWERPC] Rename ... |
233 |
BUG_ON(! of_device_is_compatible(node, "ibm,uic")); |
e58923ed1 [POWERPC] Add arc... |
234 |
|
ea96025a2 powerpc: Don't us... |
235 |
uic = kzalloc(sizeof(*uic), GFP_KERNEL); |
e58923ed1 [POWERPC] Add arc... |
236 237 |
if (! uic) return NULL; /* FIXME: panic? */ |
bccc2f7b4 locking, powerpc:... |
238 |
raw_spin_lock_init(&uic->lock); |
12d371a69 [POWERPC] get_pro... |
239 |
indexp = of_get_property(node, "cell-index", &len); |
e58923ed1 [POWERPC] Add arc... |
240 241 242 243 244 245 246 |
if (!indexp || (len != sizeof(u32))) { printk(KERN_ERR "uic: Device node %s has missing or invalid " "cell-index property ", node->full_name); return NULL; } uic->index = *indexp; |
12d371a69 [POWERPC] get_pro... |
247 |
dcrreg = of_get_property(node, "dcr-reg", &len); |
e58923ed1 [POWERPC] Add arc... |
248 249 250 251 252 253 254 |
if (!dcrreg || (len != 2*sizeof(u32))) { printk(KERN_ERR "uic: Device node %s has missing or invalid " "dcr-reg property ", node->full_name); return NULL; } uic->dcrbase = *dcrreg; |
19fc65b52 powerpc: Fix irq_... |
255 |
uic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, |
52964f87c [POWERPC] Add an ... |
256 |
NR_UIC_INTS, &uic_host_ops, -1); |
19fc65b52 powerpc: Fix irq_... |
257 |
if (! uic->irqhost) |
e58923ed1 [POWERPC] Add arc... |
258 |
return NULL; /* FIXME: panic? */ |
e58923ed1 [POWERPC] Add arc... |
259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 |
uic->irqhost->host_data = uic; /* Start with all interrupts disabled, level and non-critical */ mtdcr(uic->dcrbase + UIC_ER, 0); mtdcr(uic->dcrbase + UIC_CR, 0); mtdcr(uic->dcrbase + UIC_TR, 0); /* Clear any pending interrupts, in case the firmware left some */ mtdcr(uic->dcrbase + UIC_SR, 0xffffffff); printk ("UIC%d (%d IRQ sources) at DCR 0x%x ", uic->index, NR_UIC_INTS, uic->dcrbase); return uic; } void __init uic_init_tree(void) { struct device_node *np; struct uic *uic; const u32 *interrupts; /* First locate and initialize the top-level UIC */ |
26cb7d8bb [POWERPC] Use for... |
283 |
for_each_compatible_node(np, NULL, "ibm,uic") { |
12d371a69 [POWERPC] get_pro... |
284 |
interrupts = of_get_property(np, "interrupts", NULL); |
26cb7d8bb [POWERPC] Use for... |
285 |
if (!interrupts) |
e58923ed1 [POWERPC] Add arc... |
286 |
break; |
e58923ed1 [POWERPC] Add arc... |
287 288 289 290 291 |
} BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the * top-level interrupt controller */ primary_uic = uic_init_one(np); |
26cb7d8bb [POWERPC] Use for... |
292 |
if (!primary_uic) |
e58923ed1 [POWERPC] Add arc... |
293 294 295 296 297 298 299 |
panic("Unable to initialize primary UIC %s ", np->full_name); irq_set_default_host(primary_uic->irqhost); of_node_put(np); /* The scan again for cascaded UICs */ |
26cb7d8bb [POWERPC] Use for... |
300 |
for_each_compatible_node(np, NULL, "ibm,uic") { |
12d371a69 [POWERPC] get_pro... |
301 |
interrupts = of_get_property(np, "interrupts", NULL); |
e58923ed1 [POWERPC] Add arc... |
302 303 304 |
if (interrupts) { /* Secondary UIC */ int cascade_virq; |
e58923ed1 [POWERPC] Add arc... |
305 306 307 308 309 310 311 312 |
uic = uic_init_one(np); if (! uic) panic("Unable to initialize a secondary UIC %s ", np->full_name); cascade_virq = irq_of_parse_and_map(np, 0); |
ec775d0e7 powerpc: Convert ... |
313 314 |
irq_set_handler_data(cascade_virq, uic); irq_set_chained_handler(cascade_virq, uic_irq_cascade); |
e58923ed1 [POWERPC] Add arc... |
315 316 317 |
/* FIXME: setup critical cascade?? */ } |
e58923ed1 [POWERPC] Add arc... |
318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 |
} } /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */ unsigned int uic_get_irq(void) { u32 msr; int src; BUG_ON(! primary_uic); msr = mfdcr(primary_uic->dcrbase + UIC_MSR); src = 32 - ffs(msr); return irq_linear_revmap(primary_uic->irqhost, src); } |