Blame view
arch/xtensa/kernel/vmlinux.lds.S
6.98 KB
5a0015d62 [PATCH] xtensa: A... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 |
/* * arch/xtensa/kernel/vmlinux.lds.S * * Xtensa linker script * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2001 - 2005 Tensilica Inc. * * Chris Zankel <chris@zankel.net> * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca> * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> */ #include <asm-generic/vmlinux.lds.h> |
cd3db323e xtensa: Cleanup l... |
18 19 |
#include <asm/page.h> #include <asm/thread_info.h> |
5a0015d62 [PATCH] xtensa: A... |
20 |
|
367b8112f xtensa: move head... |
21 |
#include <variant/core.h> |
6770fa020 xtensa: let platf... |
22 |
#include <platform/hardware.h> |
5a0015d62 [PATCH] xtensa: A... |
23 24 |
OUTPUT_ARCH(xtensa) ENTRY(_start) |
173d66813 [PATCH] xtensa: r... |
25 |
#ifdef __XTENSA_EB__ |
5a0015d62 [PATCH] xtensa: A... |
26 27 28 29 |
jiffies = jiffies_64 + 4; #else jiffies = jiffies_64; #endif |
6770fa020 xtensa: let platf... |
30 |
#ifndef KERNELOFFSET |
173d66813 [PATCH] xtensa: r... |
31 |
#define KERNELOFFSET 0xd0001000 |
6770fa020 xtensa: let platf... |
32 |
#endif |
5a0015d62 [PATCH] xtensa: A... |
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 |
/* Note: In the following macros, it would be nice to specify only the vector name and section kind and construct "sym" and "section" using CPP concatenation, but that does not work reliably. Concatenating a string with "." produces an invalid token. CPP will not print a warning because it thinks this is an assembly file, but it leaves them as multiple tokens and there may or may not be whitespace between them. */ /* Macro for a relocation entry */ #define RELOCATE_ENTRY(sym, section) \ LONG(sym ## _start); \ LONG(sym ## _end); \ LONG(LOADADDR(section)) /* Macro to define a section for a vector. * * Use of the MIN function catches the types of errors illustrated in * the following example: * * Assume the section .DoubleExceptionVector.literal is completely * full. Then a programmer adds code to .DoubleExceptionVector.text * that produces another literal. The final literal position will * overlay onto the first word of the adjacent code section * .DoubleExceptionVector.text. (In practice, the literals will * overwrite the code, and the first few instructions will be * garbage.) */ #define SECTION_VECTOR(sym, section, addr, max_prevsec_size, prevsec) \ section addr : AT((MIN(LOADADDR(prevsec) + max_prevsec_size, \ LOADADDR(prevsec) + SIZEOF(prevsec)) + 3) & ~ 3) \ { \ . = ALIGN(4); \ sym ## _start = ABSOLUTE(.); \ *(section) \ sym ## _end = ABSOLUTE(.); \ } /* * Mapping of input sections to output sections when linking. */ SECTIONS { |
173d66813 [PATCH] xtensa: r... |
79 |
. = KERNELOFFSET; |
5a0015d62 [PATCH] xtensa: A... |
80 81 82 83 84 85 86 87 |
/* .text section */ _text = .; _stext = .; _ftext = .; .text : { |
0ebdcb4d0 xtensa: convert t... |
88 89 |
/* The HEAD_TEXT section must be the first section! */ HEAD_TEXT |
78f3cdfa2 xtensa: Fix linke... |
90 |
TEXT_TEXT |
5a0015d62 [PATCH] xtensa: A... |
91 |
VMLINUX_SYMBOL(__sched_text_start) = .; |
813e67836 [PATCH] xtensa: r... |
92 |
*(.sched.literal .sched.text) |
5a0015d62 [PATCH] xtensa: A... |
93 94 |
VMLINUX_SYMBOL(__sched_text_end) = .; VMLINUX_SYMBOL(__lock_text_start) = .; |
813e67836 [PATCH] xtensa: r... |
95 |
*(.spinlock.literal .spinlock.text) |
5a0015d62 [PATCH] xtensa: A... |
96 97 98 99 |
VMLINUX_SYMBOL(__lock_text_end) = .; } _etext = .; |
de4f6e5b4 [XTENSA] clean-up... |
100 |
PROVIDE (etext = .); |
5a0015d62 [PATCH] xtensa: A... |
101 102 103 104 105 106 |
. = ALIGN(16); RODATA /* Relocation table */ |
5a0015d62 [PATCH] xtensa: A... |
107 |
.fixup : { *(.fixup) } |
cd3db323e xtensa: Cleanup l... |
108 |
EXCEPTION_TABLE(16) |
5a0015d62 [PATCH] xtensa: A... |
109 |
/* Data section */ |
5a0015d62 [PATCH] xtensa: A... |
110 |
_fdata = .; |
cd3db323e xtensa: Cleanup l... |
111 |
RW_DATA_SECTION(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, THREAD_SIZE) |
5a0015d62 [PATCH] xtensa: A... |
112 |
_edata = .; |
5a0015d62 [PATCH] xtensa: A... |
113 |
/* Initialization code and data: */ |
cd3db323e xtensa: Cleanup l... |
114 |
. = ALIGN(PAGE_SIZE); |
5a0015d62 [PATCH] xtensa: A... |
115 |
__init_begin = .; |
cd3db323e xtensa: Cleanup l... |
116 |
INIT_TEXT_SECTION(PAGE_SIZE) |
5a0015d62 [PATCH] xtensa: A... |
117 118 119 |
.init.data : { |
01ba2bdc6 all archs: consol... |
120 |
INIT_DATA |
5a0015d62 [PATCH] xtensa: A... |
121 122 123 124 |
. = ALIGN(0x4); __tagtable_begin = .; *(.taglist) __tagtable_end = .; |
de4f6e5b4 [XTENSA] clean-up... |
125 126 127 128 129 130 131 132 133 134 135 136 137 138 |
. = ALIGN(16); __boot_reloc_table_start = ABSOLUTE(.); RELOCATE_ENTRY(_WindowVectors_text, .WindowVectors.text); RELOCATE_ENTRY(_KernelExceptionVector_text, .KernelExceptionVector.text); RELOCATE_ENTRY(_UserExceptionVector_text, .UserExceptionVector.text); RELOCATE_ENTRY(_DoubleExceptionVector_literal, .DoubleExceptionVector.literal); RELOCATE_ENTRY(_DoubleExceptionVector_text, .DoubleExceptionVector.text); |
6d15d1096 [XTENSA] Add miss... |
139 140 |
RELOCATE_ENTRY(_DebugInterruptVector_text, .DebugInterruptVector.text); |
de4f6e5b4 [XTENSA] clean-up... |
141 142 |
__boot_reloc_table_end = ABSOLUTE(.) ; |
5a0015d62 [PATCH] xtensa: A... |
143 |
|
cd3db323e xtensa: Cleanup l... |
144 145 146 147 148 |
INIT_SETUP(XCHAL_ICACHE_LINESIZE) INIT_CALLS CON_INITCALL SECURITY_INITCALL INIT_RAM_FS |
5a0015d62 [PATCH] xtensa: A... |
149 |
} |
de4f6e5b4 [XTENSA] clean-up... |
150 |
|
0415b00d1 percpu: Always al... |
151 |
PERCPU_SECTION(XCHAL_ICACHE_LINESIZE) |
de4f6e5b4 [XTENSA] clean-up... |
152 |
|
5a0015d62 [PATCH] xtensa: A... |
153 154 155 156 157 158 159 160 161 162 163 164 165 |
/* We need this dummy segment here */ . = ALIGN(4); .dummy : { LONG(0) } /* The vectors are relocated to the real position at startup time */ SECTION_VECTOR (_WindowVectors_text, .WindowVectors.text, XCHAL_WINDOW_VECTORS_VADDR, 4, .dummy) SECTION_VECTOR (_DebugInterruptVector_literal, .DebugInterruptVector.literal, |
173d66813 [PATCH] xtensa: r... |
166 |
XCHAL_DEBUG_VECTOR_VADDR - 4, |
5a0015d62 [PATCH] xtensa: A... |
167 168 169 170 |
SIZEOF(.WindowVectors.text), .WindowVectors.text) SECTION_VECTOR (_DebugInterruptVector_text, .DebugInterruptVector.text, |
173d66813 [PATCH] xtensa: r... |
171 |
XCHAL_DEBUG_VECTOR_VADDR, |
5a0015d62 [PATCH] xtensa: A... |
172 173 174 175 |
4, .DebugInterruptVector.literal) SECTION_VECTOR (_KernelExceptionVector_literal, .KernelExceptionVector.literal, |
173d66813 [PATCH] xtensa: r... |
176 |
XCHAL_KERNEL_VECTOR_VADDR - 4, |
5a0015d62 [PATCH] xtensa: A... |
177 178 179 180 |
SIZEOF(.DebugInterruptVector.text), .DebugInterruptVector.text) SECTION_VECTOR (_KernelExceptionVector_text, .KernelExceptionVector.text, |
173d66813 [PATCH] xtensa: r... |
181 |
XCHAL_KERNEL_VECTOR_VADDR, |
5a0015d62 [PATCH] xtensa: A... |
182 183 184 185 |
4, .KernelExceptionVector.literal) SECTION_VECTOR (_UserExceptionVector_literal, .UserExceptionVector.literal, |
173d66813 [PATCH] xtensa: r... |
186 |
XCHAL_USER_VECTOR_VADDR - 4, |
5a0015d62 [PATCH] xtensa: A... |
187 188 189 190 |
SIZEOF(.KernelExceptionVector.text), .KernelExceptionVector.text) SECTION_VECTOR (_UserExceptionVector_text, .UserExceptionVector.text, |
173d66813 [PATCH] xtensa: r... |
191 |
XCHAL_USER_VECTOR_VADDR, |
5a0015d62 [PATCH] xtensa: A... |
192 193 194 195 196 197 198 199 200 201 202 203 204 205 |
4, .UserExceptionVector.literal) SECTION_VECTOR (_DoubleExceptionVector_literal, .DoubleExceptionVector.literal, XCHAL_DOUBLEEXC_VECTOR_VADDR - 16, SIZEOF(.UserExceptionVector.text), .UserExceptionVector.text) SECTION_VECTOR (_DoubleExceptionVector_text, .DoubleExceptionVector.text, XCHAL_DOUBLEEXC_VECTOR_VADDR, 32, .DoubleExceptionVector.literal) . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3; |
cd3db323e xtensa: Cleanup l... |
206 |
. = ALIGN(PAGE_SIZE); |
5a0015d62 [PATCH] xtensa: A... |
207 208 |
__init_end = .; |
cd3db323e xtensa: Cleanup l... |
209 |
BSS_SECTION(0, 8192, 0) |
de4f6e5b4 [XTENSA] clean-up... |
210 |
|
5a0015d62 [PATCH] xtensa: A... |
211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 |
_end = .; /* only used by the boot loader */ . = ALIGN(0x10); .bootstrap : { *(.bootstrap.literal .bootstrap.text .bootstrap.data) } . = ALIGN(0x1000); __initrd_start = .; .initrd : { *(.initrd) } __initrd_end = .; .ResetVector.text XCHAL_RESET_VECTOR_VADDR : { *(.ResetVector.text) } |
de4f6e5b4 [XTENSA] clean-up... |
227 228 |
.xt.lit : { *(.xt.lit) } .xt.prop : { *(.xt.prop) } |
5a0015d62 [PATCH] xtensa: A... |
229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 |
.debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } .xt.insn 0 : { *(.xt.insn) *(.gnu.linkonce.x*) } .xt.lit 0 : { *(.xt.lit) *(.gnu.linkonce.p*) } |
023bf6f1b linker script: un... |
259 260 261 262 |
/* Sections to be discarded */ DISCARDS /DISCARD/ : { *(.exit.literal) } |
5a0015d62 [PATCH] xtensa: A... |
263 |
} |