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sound/sparc/dbri.c
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/* * Driver for DBRI sound chip found on Sparcs. |
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* Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net) |
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* |
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* Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl) * |
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* Based entirely upon drivers/sbus/audio/dbri.c which is: * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de) * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org) * |
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* This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO * on Sun SPARCStation 10, 20, LX and Voyager models. |
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* * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel * data time multiplexer with ISDN support (aka T7259) * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel. * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?). * Documentation: |
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* - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from |
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* Sparc Technology Business (courtesy of Sun Support) * - Data sheet of the T7903, a newer but very similar ISA bus equivalent |
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* available from the Lucent (formerly AT&T microelectronics) home |
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* page. * - http://www.freesoft.org/Linux/DBRI/ * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec * Interfaces: CHI, Audio In & Out, 2 bits parallel * Documentation: from the Crystal Semiconductor home page. * * The DBRI is a 32 pipe machine, each pipe can transfer some bits between |
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* memory and a serial device (long pipes, no. 0-15) or between two serial * devices (short pipes, no. 16-31), or simply send a fixed data to a serial |
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* device (short pipes). |
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* A timeslot defines the bit-offset and no. of bits read from a serial device. |
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* The timeslots are linked to 6 circular lists, one for each direction for * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes * (the second one is a monitor/tee pipe, valid only for serial input). * * The mmcodec is connected via the CHI bus and needs the data & some |
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* parameters (volume, output selection) time multiplexed in 8 byte |
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* chunks. It also has a control mode, which serves for audio format setting. * * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on |
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* the same CHI bus, so I thought perhaps it is possible to use the on-board * & the speakerbox codec simultaneously, giving 2 (not very independent :-) |
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* audio devices. But the SUN HW group decided against it, at least on my * LX the speakerbox connector has at least 1 pin missing and 1 wrongly * connected. |
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* * I've tried to stick to the following function naming conventions: * snd_* ALSA stuff |
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* cs4215_* CS4215 codec specific stuff |
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* dbri_* DBRI high-level stuff * other DBRI low-level stuff |
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*/ |
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#include <linux/interrupt.h> #include <linux/delay.h> |
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#include <linux/irq.h> #include <linux/io.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/gfp.h> |
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#include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/info.h> #include <sound/control.h> #include <sound/initval.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/atomic.h> |
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#include <linux/module.h> |
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MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets"); MODULE_DESCRIPTION("Sun DBRI"); MODULE_LICENSE("GPL"); MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}"); static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ |
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/* Enable this card */ |
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static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; |
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module_param_array(index, int, NULL, 0444); MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard."); module_param_array(id, charp, NULL, 0444); MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard."); module_param_array(enable, bool, NULL, 0444); MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard."); |
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#undef DBRI_DEBUG |
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#define D_INT (1<<0) #define D_GEN (1<<1) #define D_CMD (1<<2) #define D_MM (1<<3) #define D_USR (1<<4) #define D_DESC (1<<5) |
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static int dbri_debug; |
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module_param(dbri_debug, int, 0644); |
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MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard."); #ifdef DBRI_DEBUG static char *cmds[] = { "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS", "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV" }; |
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#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x) |
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#else |
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#define dprintk(a, x...) do { } while (0) |
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#endif /* DBRI_DEBUG */ |
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#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \ (intr << 27) | \ value) |
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/*************************************************************************** CS4215 specific definitions and structures ****************************************************************************/ struct cs4215 { __u8 data[4]; /* Data mode: Time slots 5-8 */ __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */ __u8 onboard; __u8 offset; /* Bit offset from frame sync to time slot 1 */ volatile __u32 status; volatile __u32 version; __u8 precision; /* In bits, either 8 or 16 */ __u8 channels; /* 1 or 2 */ }; /* |
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* Control mode first |
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*/ /* Time Slot 1, Status register */ #define CS4215_CLB (1<<2) /* Control Latch Bit */ #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */ /* 0: line: 2.8V, speaker 8V */ #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */ #define CS4215_RSRVD_1 (1<<5) /* Time Slot 2, Data Format Register */ #define CS4215_DFR_LINEAR16 0 #define CS4215_DFR_ULAW 1 #define CS4215_DFR_ALAW 2 #define CS4215_DFR_LINEAR8 3 #define CS4215_DFR_STEREO (1<<2) static struct { unsigned short freq; unsigned char xtal; unsigned char csval; } CS4215_FREQ[] = { { 8000, (1 << 4), (0 << 3) }, { 16000, (1 << 4), (1 << 3) }, { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */ { 32000, (1 << 4), (3 << 3) }, /* { NA, (1 << 4), (4 << 3) }, */ /* { NA, (1 << 4), (5 << 3) }, */ { 48000, (1 << 4), (6 << 3) }, { 9600, (1 << 4), (7 << 3) }, |
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{ 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */ |
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{ 11025, (2 << 4), (1 << 3) }, { 18900, (2 << 4), (2 << 3) }, { 22050, (2 << 4), (3 << 3) }, { 37800, (2 << 4), (4 << 3) }, { 44100, (2 << 4), (5 << 3) }, { 33075, (2 << 4), (6 << 3) }, { 6615, (2 << 4), (7 << 3) }, { 0, 0, 0} }; #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */ #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */ /* Time Slot 3, Serial Port Control register */ #define CS4215_XEN (1<<0) /* 0: Enable serial output */ #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */ #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */ #define CS4215_BSEL_128 (1<<2) #define CS4215_BSEL_256 (2<<2) #define CS4215_MCK_MAST (0<<4) /* Master clock */ #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */ #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */ #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */ #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */ /* Time Slot 4, Test Register */ #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */ #define CS4215_ENL (1<<1) /* Enable Loopback Testing */ /* Time Slot 5, Parallel Port Register */ /* Read only here and the same as the in data mode */ /* Time Slot 6, Reserved */ /* Time Slot 7, Version Register */ #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */ /* Time Slot 8, Reserved */ /* * Data mode */ /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */ /* Time Slot 5, Output Setting */ #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */ #define CS4215_LE (1<<6) /* Line Out Enable */ #define CS4215_HE (1<<7) /* Headphone Enable */ /* Time Slot 6, Output Setting */ #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */ #define CS4215_SE (1<<6) /* Speaker Enable */ #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */ /* Time Slot 7, Input Setting */ #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */ #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */ |
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#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */ |
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#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */ #define CS4215_PIO1 (1<<7) /* Time Slot 8, Input Setting */ #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */ #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */ /*************************************************************************** DBRI specific definitions and structures ****************************************************************************/ /* DBRI main registers */ |
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#define REG0 0x00 /* Status and Control */ #define REG1 0x04 /* Mode and Interrupt */ #define REG2 0x08 /* Parallel IO */ #define REG3 0x0c /* Test */ #define REG8 0x20 /* Command Queue Pointer */ #define REG9 0x24 /* Interrupt Queue Pointer */ |
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#define DBRI_NO_CMDS 64 |
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#define DBRI_INT_BLK 64 #define DBRI_NO_DESCS 64 #define DBRI_NO_PIPES 32 |
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#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1) |
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#define DBRI_REC 0 #define DBRI_PLAY 1 #define DBRI_NO_STREAMS 2 /* One transmit/receive descriptor */ |
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/* When ba != 0 descriptor is used */ |
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struct dbri_mem { volatile __u32 word1; |
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__u32 ba; /* Transmit/Receive Buffer Address */ __u32 nda; /* Next Descriptor Address */ |
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volatile __u32 word4; }; /* This structure is in a DMA region where it can accessed by both * the CPU and the DBRI */ struct dbri_dma { |
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s32 cmd[DBRI_NO_CMDS]; /* Place for commands */ |
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volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */ |
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struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */ }; #define dbri_dma_off(member, elem) \ ((u32)(unsigned long) \ (&(((struct dbri_dma *)0)->member[elem]))) enum in_or_out { PIPEinput, PIPEoutput }; struct dbri_pipe { u32 sdp; /* SDP command word */ |
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int nextpipe; /* Next pipe in linked list */ |
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int length; /* Length of timeslot (bits) */ int first_desc; /* Index of first descriptor */ int desc; /* Index of active descriptor */ volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */ }; |
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/* Per stream (playback or record) information */ |
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struct dbri_streaminfo { struct snd_pcm_substream *substream; |
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u32 dvma_buffer; /* Device view of ALSA DMA buffer */ |
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int size; /* Size of DMA buffer */ size_t offset; /* offset in user buffer */ int pipe; /* Data pipe used */ int left_gain; /* mixer elements */ int right_gain; |
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}; |
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/* This structure holds the information for both chips (DBRI & CS4215) */ |
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struct snd_dbri { |
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int regs_size, irq; /* Needed for unload */ |
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struct platform_device *op; /* OF device info */ |
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spinlock_t lock; |
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struct dbri_dma *dma; /* Pointer to our DMA block */ |
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u32 dma_dvma; /* DBRI visible DMA address */ void __iomem *regs; /* dbri HW regs */ |
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int dbri_irqp; /* intr queue pointer */ |
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struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ |
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int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */ |
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spinlock_t cmdlock; /* Protects cmd queue accesses */ s32 *cmdptr; /* Pointer to the last queued cmd */ |
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int chi_bpf; struct cs4215 mm; /* mmcodec special info */ /* per stream (playback/record) info */ struct dbri_streaminfo stream_info[DBRI_NO_STREAMS]; |
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}; |
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#define DBRI_MAX_VOLUME 63 /* Output volume */ #define DBRI_MAX_GAIN 15 /* Input gain */ |
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/* DBRI Reg0 - Status Control Register - defines. (Page 17) */ #define D_P (1<<15) /* Program command & queue pointer valid */ #define D_G (1<<14) /* Allow 4-Word SBus Burst */ #define D_S (1<<13) /* Allow 16-Word SBus Burst */ #define D_E (1<<12) /* Allow 8-Word SBus Burst */ #define D_X (1<<7) /* Sanity Timer Disable */ #define D_T (1<<6) /* Permit activation of the TE interface */ #define D_N (1<<5) /* Permit activation of the NT interface */ #define D_C (1<<4) /* Permit activation of the CHI interface */ #define D_F (1<<3) /* Force Sanity Timer Time-Out */ #define D_D (1<<2) /* Disable Master Mode */ #define D_H (1<<1) /* Halt for Analysis */ #define D_R (1<<0) /* Soft Reset */ /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */ #define D_LITTLE_END (1<<8) /* Byte Order */ #define D_BIG_END (0<<8) /* Byte Order */ |
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#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */ #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */ #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */ #define D_MBE (1<<1) /* Burst Error on SBus (read only) */ #define D_IR (1<<0) /* Interrupt Indicator (read only) */ |
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/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */ #define D_ENPIO3 (1<<7) /* Enable Pin 3 */ #define D_ENPIO2 (1<<6) /* Enable Pin 2 */ #define D_ENPIO1 (1<<5) /* Enable Pin 1 */ #define D_ENPIO0 (1<<4) /* Enable Pin 0 */ #define D_ENPIO (0xf0) /* Enable all the pins */ #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */ #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */ #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */ #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */ /* DBRI Commands (Page 20) */ #define D_WAIT 0x0 /* Stop execution */ #define D_PAUSE 0x1 /* Flush long pipes */ #define D_JUMP 0x2 /* New command queue */ #define D_IIQ 0x3 /* Initialize Interrupt Queue */ #define D_REX 0x4 /* Report command execution via interrupt */ #define D_SDP 0x5 /* Setup Data Pipe */ #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */ #define D_DTS 0x7 /* Define Time Slot */ #define D_SSP 0x8 /* Set short Data Pipe */ #define D_CHI 0x9 /* Set CHI Global Mode */ #define D_NT 0xa /* NT Command */ #define D_TE 0xb /* TE Command */ #define D_CDEC 0xc /* Codec setup */ #define D_TEST 0xd /* No comment */ #define D_CDM 0xe /* CHI Data mode command */ /* Special bits for some commands */ |
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#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */ |
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/* Setup Data Pipe */ /* IRM */ |
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#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */ |
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#define D_SDP_CHANGE (2<<18) /* Report any changes */ #define D_SDP_EVERY (3<<18) /* Report any changes */ #define D_SDP_EOL (1<<17) /* EOL interrupt enable */ #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */ /* Pipe data MODE */ #define D_SDP_MEM (0<<13) /* To/from memory */ #define D_SDP_HDLC (2<<13) #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */ #define D_SDP_SER (4<<13) /* Serial to serial */ #define D_SDP_FIXED (6<<13) /* Short only */ #define D_SDP_MODE(v) ((v)&(7<<13)) #define D_SDP_TO_SER (1<<12) /* Direction */ #define D_SDP_FROM_SER (0<<12) /* Direction */ #define D_SDP_MSB (1<<11) /* Bit order within Byte */ #define D_SDP_LSB (0<<11) /* Bit order within Byte */ #define D_SDP_P (1<<10) /* Pointer Valid */ #define D_SDP_A (1<<8) /* Abort */ #define D_SDP_C (1<<7) /* Clear */ /* Define Time Slot */ #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */ #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */ #define D_DTS_INS (1<<15) /* Insert Time Slot */ #define D_DTS_DEL (0<<15) /* Delete Time Slot */ #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */ #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */ /* Time Slot defines */ #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */ #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */ #define D_TS_DI (1<<13) /* Data Invert */ #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */ #define D_TS_MONITOR (2<<10) /* Monitor pipe */ #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */ #define D_TS_ANCHOR (7<<10) /* Starting short pipes */ #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */ |
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#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */ |
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/* Concentration Highway Interface Modes */ #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */ #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */ #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */ #define D_CHI_OD (1<<13) /* Open Drain Enable */ #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */ #define D_CHI_FD (1<<11) /* Frame Drive */ #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */ /* NT: These are here for completeness */ #define D_NT_FBIT (1<<17) /* Frame Bit */ #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */ #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */ #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */ |
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#define D_NT_ISNT (1<<13) /* Configure interface as NT */ |
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430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 |
#define D_NT_FT (1<<12) /* Fixed Timing */ #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */ #define D_NT_IFA (1<<10) /* Inhibit Final Activation */ #define D_NT_ACT (1<<9) /* Activate Interface */ #define D_NT_MFE (1<<8) /* Multiframe Enable */ #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */ #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */ #define D_NT_FACT (1<<1) /* Force Activation */ #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */ /* Codec Setup */ #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */ #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */ #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */ /* Test */ #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */ #define D_TEST_SIZE(v) ((v)<<11) /* */ #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */ |
098ccbc55 [ALSA] dbri: driv... |
449 |
#define D_TEST_PROC 0x6 /* Microprocessor test */ |
1bd9debf2 [ALSA] Add DBRI d... |
450 451 452 453 454 455 456 457 |
#define D_TEST_SER 0x7 /* Serial-Controller test */ #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */ #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */ #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */ #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */ #define D_TEST_DUMP 0xe /* ROM Dump */ /* CHI Data Mode */ |
098ccbc55 [ALSA] dbri: driv... |
458 459 460 461 462 463 |
#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */ #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */ #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */ #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */ #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */ #define D_CDM_REN (1 << 0) /* Receive Highway Enable */ |
1bd9debf2 [ALSA] Add DBRI d... |
464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 |
/* The Interrupts */ #define D_INTR_BRDY 1 /* Buffer Ready for processing */ #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */ #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */ #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */ #define D_INTR_EOL 5 /* End of List */ #define D_INTR_CMDI 6 /* Command has bean read */ #define D_INTR_XCMP 8 /* Transmission of frame complete */ #define D_INTR_SBRI 9 /* BRI status change info */ #define D_INTR_FXDT 10 /* Fixed data change */ #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */ #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */ #define D_INTR_DBYT 12 /* Dropped by frame slip */ #define D_INTR_RBYT 13 /* Repeated by frame slip */ #define D_INTR_LINT 14 /* Lost Interrupt */ #define D_INTR_UNDR 15 /* DMA underrun */ #define D_INTR_TE 32 #define D_INTR_NT 34 #define D_INTR_CHI 36 #define D_INTR_CMD 38 |
098ccbc55 [ALSA] dbri: driv... |
486 487 488 |
#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f) #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf) #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf) |
1bd9debf2 [ALSA] Add DBRI d... |
489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 |
#define D_INTR_GETVAL(v) ((v) & 0xffff) #define D_INTR_GETRVAL(v) ((v) & 0xfffff) #define D_P_0 0 /* TE receive anchor */ #define D_P_1 1 /* TE transmit anchor */ #define D_P_2 2 /* NT transmit anchor */ #define D_P_3 3 /* NT receive anchor */ #define D_P_4 4 /* CHI send data */ #define D_P_5 5 /* CHI receive data */ #define D_P_6 6 /* */ #define D_P_7 7 /* */ #define D_P_8 8 /* */ #define D_P_9 9 /* */ #define D_P_10 10 /* */ #define D_P_11 11 /* */ #define D_P_12 12 /* */ #define D_P_13 13 /* */ #define D_P_14 14 /* */ #define D_P_15 15 /* */ #define D_P_16 16 /* CHI anchor pipe */ #define D_P_17 17 /* CHI send */ #define D_P_18 18 /* CHI receive */ #define D_P_19 19 /* CHI receive */ #define D_P_20 20 /* CHI receive */ #define D_P_21 21 /* */ #define D_P_22 22 /* */ #define D_P_23 23 /* */ #define D_P_24 24 /* */ #define D_P_25 25 /* */ #define D_P_26 26 /* */ #define D_P_27 27 /* */ #define D_P_28 28 /* */ #define D_P_29 29 /* */ #define D_P_30 30 /* */ #define D_P_31 31 /* */ /* Transmit descriptor defines */ |
098ccbc55 [ALSA] dbri: driv... |
526 527 528 529 530 531 532 533 534 535 536 537 |
#define DBRI_TD_F (1 << 31) /* End of Frame */ #define DBRI_TD_D (1 << 30) /* Do not append CRC */ #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */ #define DBRI_TD_B (1 << 15) /* Final interrupt */ #define DBRI_TD_M (1 << 14) /* Marker interrupt */ #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */ #define DBRI_TD_FCNT(v) (v) /* Flag Count */ #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */ #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */ #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */ #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */ /* Maximum buffer size per TD: almost 8KB */ |
1be54c824 [ALSA] sparc dbri... |
538 |
#define DBRI_TD_MAXCNT ((1 << 13) - 4) |
1bd9debf2 [ALSA] Add DBRI d... |
539 540 |
/* Receive descriptor defines */ |
098ccbc55 [ALSA] dbri: driv... |
541 542 543 544 545 546 547 548 549 550 551 |
#define DBRI_RD_F (1 << 31) /* End of Frame */ #define DBRI_RD_C (1 << 30) /* Completed buffer */ #define DBRI_RD_B (1 << 15) /* Final interrupt */ #define DBRI_RD_M (1 << 14) /* Marker interrupt */ #define DBRI_RD_BCNT(v) (v) /* Buffer size */ #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */ #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */ #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */ #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */ #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */ #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */ |
1bd9debf2 [ALSA] Add DBRI d... |
552 553 554 555 |
/* stream_info[] access */ /* Translate the ALSA direction into the array index */ #define DBRI_STREAMNO(substream) \ |
098ccbc55 [ALSA] dbri: driv... |
556 |
(substream->stream == \ |
cf68d212d [ALSA] dbri: more... |
557 |
SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC) |
1bd9debf2 [ALSA] Add DBRI d... |
558 559 |
/* Return a pointer to dbri_streaminfo */ |
098ccbc55 [ALSA] dbri: driv... |
560 561 |
#define DBRI_STREAM(dbri, substream) \ &dbri->stream_info[DBRI_STREAMNO(substream)] |
1bd9debf2 [ALSA] Add DBRI d... |
562 |
|
1bd9debf2 [ALSA] Add DBRI d... |
563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 |
/* * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr. * So we have to reverse the bits. Note: not all bit lengths are supported */ static __u32 reverse_bytes(__u32 b, int len) { switch (len) { case 32: b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16); case 16: b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8); case 8: b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4); case 4: b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2); case 2: b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1); case 1: case 0: break; default: printk(KERN_ERR "DBRI reverse_bytes: unsupported length "); }; return b; } /* **************************************************************************** ************** DBRI initialization and command synchronization ************* **************************************************************************** Commands are sent to the DBRI by building a list of them in memory, then writing the address of the first list item to DBRI register 8. |
4338829e0 [ALSA] Several fi... |
598 599 |
The list is terminated with a WAIT command, which generates a CPU interrupt to signal completion. |
1bd9debf2 [ALSA] Add DBRI d... |
600 601 |
Since the DBRI can run in parallel with the CPU, several means of |
cf68d212d [ALSA] dbri: more... |
602 603 |
synchronization present themselves. The method implemented here uses the dbri_cmdwait() to wait for execution of batch of sent commands. |
1bd9debf2 [ALSA] Add DBRI d... |
604 |
|
098ccbc55 [ALSA] dbri: driv... |
605 |
A circular command buffer is used here. A new command is being added |
aaad3653a [ALSA] sparc dbri... |
606 |
while another can be executed. The scheme works by adding two WAIT commands |
1be54c824 [ALSA] sparc dbri... |
607 608 |
after each sent batch of commands. When the next batch is prepared it is added after the WAIT commands then the WAITs are replaced with single JUMP |
098ccbc55 [ALSA] dbri: driv... |
609 610 |
command to the new batch. The the DBRI is forced to reread the last WAIT command (replaced by the JUMP by then). If the DBRI is still executing |
1be54c824 [ALSA] sparc dbri... |
611 |
previous commands the request to reread the WAIT command is ignored. |
1bd9debf2 [ALSA] Add DBRI d... |
612 |
|
1bd9debf2 [ALSA] Add DBRI d... |
613 |
Every time a routine wants to write commands to the DBRI, it must |
098ccbc55 [ALSA] dbri: driv... |
614 615 616 |
first call dbri_cmdlock() and get pointer to a free space in dbri->dma->cmd buffer. After this, the commands can be written to the buffer, and dbri_cmdsend() is called with the final pointer value |
1be54c824 [ALSA] sparc dbri... |
617 |
to send them to the DBRI. |
1bd9debf2 [ALSA] Add DBRI d... |
618 619 |
*/ |
aaad3653a [ALSA] sparc dbri... |
620 |
#define MAXLOOPS 20 |
1be54c824 [ALSA] sparc dbri... |
621 622 623 624 |
/* * Wait for the current command string to execute */ static void dbri_cmdwait(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
625 |
{ |
4338829e0 [ALSA] Several fi... |
626 |
int maxloops = MAXLOOPS; |
ea543f1ee [ALSA] sparc dbri... |
627 |
unsigned long flags; |
4338829e0 [ALSA] Several fi... |
628 |
|
4338829e0 [ALSA] Several fi... |
629 |
/* Delay if previous commands are still being processed */ |
ea543f1ee [ALSA] sparc dbri... |
630 631 632 |
spin_lock_irqsave(&dbri->lock, flags); while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) { spin_unlock_irqrestore(&dbri->lock, flags); |
4338829e0 [ALSA] Several fi... |
633 |
msleep_interruptible(1); |
ea543f1ee [ALSA] sparc dbri... |
634 635 636 |
spin_lock_irqsave(&dbri->lock, flags); } spin_unlock_irqrestore(&dbri->lock, flags); |
1be54c824 [ALSA] sparc dbri... |
637 |
|
cf68d212d [ALSA] dbri: more... |
638 |
if (maxloops == 0) |
1be54c824 [ALSA] sparc dbri... |
639 640 |
printk(KERN_ERR "DBRI: Chip never completed command buffer "); |
cf68d212d [ALSA] dbri: more... |
641 |
else |
4338829e0 [ALSA] Several fi... |
642 643 644 |
dprintk(D_CMD, "Chip completed command buffer (%d) ", MAXLOOPS - maxloops - 1); |
1be54c824 [ALSA] sparc dbri... |
645 646 |
} /* |
cf68d212d [ALSA] dbri: more... |
647 |
* Lock the command queue and return pointer to space for len cmd words |
1be54c824 [ALSA] sparc dbri... |
648 649 |
* It locks the cmdlock spinlock. */ |
098ccbc55 [ALSA] dbri: driv... |
650 |
static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len) |
1be54c824 [ALSA] sparc dbri... |
651 652 653 654 655 656 657 658 659 660 |
{ /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */ len += 2; spin_lock(&dbri->cmdlock); if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2) return dbri->cmdptr + 2; else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma) return dbri->dma->cmd; else printk(KERN_ERR "DBRI: no space for commands."); |
4338829e0 [ALSA] Several fi... |
661 |
|
ae97dd9af [PATCH] NULL nois... |
662 |
return NULL; |
1bd9debf2 [ALSA] Add DBRI d... |
663 |
} |
1be54c824 [ALSA] sparc dbri... |
664 |
/* |
beb7dd86a Fix misspellings ... |
665 |
* Send prepared cmd string. It works by writing a JUMP cmd into |
1be54c824 [ALSA] sparc dbri... |
666 |
* the last WAIT cmd and force DBRI to reread the cmd. |
ab93c7ae5 [ALSA] sparc dbri... |
667 |
* The JUMP cmd points to the new cmd string. |
1be54c824 [ALSA] sparc dbri... |
668 |
* It also releases the cmdlock spinlock. |
ea543f1ee [ALSA] sparc dbri... |
669 |
* |
ca4058708 [ALSA] sparc dbri... |
670 |
* Lock must be held before calling this. |
1be54c824 [ALSA] sparc dbri... |
671 |
*/ |
098ccbc55 [ALSA] dbri: driv... |
672 |
static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len) |
1bd9debf2 [ALSA] Add DBRI d... |
673 |
{ |
1be54c824 [ALSA] sparc dbri... |
674 675 |
s32 tmp, addr; static int wait_id = 0; |
1bd9debf2 [ALSA] Add DBRI d... |
676 |
|
1be54c824 [ALSA] sparc dbri... |
677 678 679 680 |
wait_id++; wait_id &= 0xffff; /* restrict it to a 16 bit counter. */ *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id); *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id); |
1bd9debf2 [ALSA] Add DBRI d... |
681 |
|
1be54c824 [ALSA] sparc dbri... |
682 683 684 685 |
/* Replace the last command with JUMP */ addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32); *(dbri->cmdptr+1) = addr; *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
686 |
|
1be54c824 [ALSA] sparc dbri... |
687 |
#ifdef DBRI_DEBUG |
ab93c7ae5 [ALSA] sparc dbri... |
688 689 |
if (cmd > dbri->cmdptr) { s32 *ptr; |
aaad3653a [ALSA] sparc dbri... |
690 |
for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++) |
098ccbc55 [ALSA] dbri: driv... |
691 692 693 |
dprintk(D_CMD, "cmd: %lx:%08x ", (unsigned long)ptr, *ptr); |
ab93c7ae5 [ALSA] sparc dbri... |
694 695 |
} else { s32 *ptr = dbri->cmdptr; |
1be54c824 [ALSA] sparc dbri... |
696 697 |
dprintk(D_CMD, "cmd: %lx:%08x ", (unsigned long)ptr, *ptr); |
ab93c7ae5 [ALSA] sparc dbri... |
698 |
ptr++; |
1be54c824 [ALSA] sparc dbri... |
699 700 |
dprintk(D_CMD, "cmd: %lx:%08x ", (unsigned long)ptr, *ptr); |
098ccbc55 [ALSA] dbri: driv... |
701 702 703 704 |
for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) dprintk(D_CMD, "cmd: %lx:%08x ", (unsigned long)ptr, *ptr); |
1be54c824 [ALSA] sparc dbri... |
705 706 |
} #endif |
4338829e0 [ALSA] Several fi... |
707 |
|
1be54c824 [ALSA] sparc dbri... |
708 709 710 711 |
/* Reread the last command */ tmp = sbus_readl(dbri->regs + REG0); tmp |= D_P; sbus_writel(tmp, dbri->regs + REG0); |
1bd9debf2 [ALSA] Add DBRI d... |
712 |
|
1be54c824 [ALSA] sparc dbri... |
713 714 |
dbri->cmdptr = cmd; spin_unlock(&dbri->cmdlock); |
1bd9debf2 [ALSA] Add DBRI d... |
715 716 717 |
} /* Lock must be held when calling this */ |
098ccbc55 [ALSA] dbri: driv... |
718 |
static void dbri_reset(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
719 720 |
{ int i; |
d1fdf07e2 [ALSA] sparc dbri... |
721 |
u32 tmp; |
1bd9debf2 [ALSA] Add DBRI d... |
722 723 724 725 726 727 728 729 730 731 |
dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x ", sbus_readl(dbri->regs + REG0), sbus_readl(dbri->regs + REG2), sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9)); sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */ for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++) udelay(10); |
d1fdf07e2 [ALSA] sparc dbri... |
732 733 734 735 736 737 738 |
/* A brute approach - DBRI falls back to working burst size by itself * On SS20 D_S does not work, so do not try so high. */ tmp = sbus_readl(dbri->regs + REG0); tmp |= D_G | D_E; tmp &= ~D_S; sbus_writel(tmp, dbri->regs + REG0); |
1bd9debf2 [ALSA] Add DBRI d... |
739 740 741 |
} /* Lock must not be held before calling this */ |
afeacfd5f [ALSA] dbri: conv... |
742 |
static void __devinit dbri_initialize(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
743 |
{ |
1be54c824 [ALSA] sparc dbri... |
744 |
s32 *cmd; |
d1fdf07e2 [ALSA] sparc dbri... |
745 |
u32 dma_addr; |
1bd9debf2 [ALSA] Add DBRI d... |
746 747 748 749 750 751 |
unsigned long flags; int n; spin_lock_irqsave(&dbri->lock, flags); dbri_reset(dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
752 753 754 |
/* Initialize pipes */ for (n = 0; n < DBRI_NO_PIPES; n++) dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; |
1be54c824 [ALSA] sparc dbri... |
755 |
spin_lock_init(&dbri->cmdlock); |
1bd9debf2 [ALSA] Add DBRI d... |
756 |
/* |
098ccbc55 [ALSA] dbri: driv... |
757 |
* Initialize the interrupt ring buffer. |
1bd9debf2 [ALSA] Add DBRI d... |
758 759 |
*/ dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0); |
6fb982803 [ALSA] sparc dbri... |
760 761 762 763 764 |
dbri->dma->intr[0] = dma_addr; dbri->dbri_irqp = 1; /* * Set up the interrupt queue */ |
1be54c824 [ALSA] sparc dbri... |
765 766 |
spin_lock(&dbri->cmdlock); cmd = dbri->cmdptr = dbri->dma->cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
767 768 |
*(cmd++) = DBRI_CMD(D_IIQ, 0, 0); *(cmd++) = dma_addr; |
1be54c824 [ALSA] sparc dbri... |
769 770 771 772 773 774 775 |
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); dbri->cmdptr = cmd; *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); *(cmd++) = DBRI_CMD(D_WAIT, 1, 0); dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0); sbus_writel(dma_addr, dbri->regs + REG8); spin_unlock(&dbri->cmdlock); |
1bd9debf2 [ALSA] Add DBRI d... |
776 |
|
1bd9debf2 [ALSA] Add DBRI d... |
777 |
spin_unlock_irqrestore(&dbri->lock, flags); |
ea543f1ee [ALSA] sparc dbri... |
778 |
dbri_cmdwait(dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 |
} /* **************************************************************************** ************************** DBRI data pipe management *********************** **************************************************************************** While DBRI control functions use the command and interrupt buffers, the main data path takes the form of data pipes, which can be short (command and interrupt driven), or long (attached to DMA buffers). These functions provide a rudimentary means of setting up and managing the DBRI's pipes, but the calling functions have to make sure they respect the pipes' linked list ordering, among other things. The transmit and receive functions here interface closely with the transmit and receive interrupt code. */ |
cf68d212d [ALSA] dbri: more... |
795 |
static inline int pipe_active(struct snd_dbri *dbri, int pipe) |
1bd9debf2 [ALSA] Add DBRI d... |
796 797 798 799 800 801 802 803 804 |
{ return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1)); } /* reset_pipe(dbri, pipe) * * Called on an in-use pipe to clear anything being transmitted or received * Lock must be held before calling this. */ |
098ccbc55 [ALSA] dbri: driv... |
805 |
static void reset_pipe(struct snd_dbri *dbri, int pipe) |
1bd9debf2 [ALSA] Add DBRI d... |
806 807 808 |
{ int sdp; int desc; |
1be54c824 [ALSA] sparc dbri... |
809 |
s32 *cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
810 |
|
470f1f1a1 [ALSA] sparc dbri... |
811 |
if (pipe < 0 || pipe > DBRI_MAX_PIPE) { |
098ccbc55 [ALSA] dbri: driv... |
812 813 814 |
printk(KERN_ERR "DBRI: reset_pipe called with " "illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
815 816 817 818 819 |
return; } sdp = dbri->pipes[pipe].sdp; if (sdp == 0) { |
098ccbc55 [ALSA] dbri: driv... |
820 821 822 |
printk(KERN_ERR "DBRI: reset_pipe called " "on uninitialized pipe "); |
1bd9debf2 [ALSA] Add DBRI d... |
823 824 |
return; } |
1be54c824 [ALSA] sparc dbri... |
825 |
cmd = dbri_cmdlock(dbri, 3); |
1bd9debf2 [ALSA] Add DBRI d... |
826 827 |
*(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P); *(cmd++) = 0; |
1be54c824 [ALSA] sparc dbri... |
828 829 |
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); dbri_cmdsend(dbri, cmd, 3); |
1bd9debf2 [ALSA] Add DBRI d... |
830 831 |
desc = dbri->pipes[pipe].first_desc; |
098ccbc55 [ALSA] dbri: driv... |
832 |
if (desc >= 0) |
1be54c824 [ALSA] sparc dbri... |
833 |
do { |
098ccbc55 [ALSA] dbri: driv... |
834 835 |
dbri->dma->desc[desc].ba = 0; dbri->dma->desc[desc].nda = 0; |
1be54c824 [ALSA] sparc dbri... |
836 837 |
desc = dbri->next_desc[desc]; } while (desc != -1 && desc != dbri->pipes[pipe].first_desc); |
1bd9debf2 [ALSA] Add DBRI d... |
838 839 840 841 |
dbri->pipes[pipe].desc = -1; dbri->pipes[pipe].first_desc = -1; } |
ea543f1ee [ALSA] sparc dbri... |
842 843 844 |
/* * Lock must be held before calling this. */ |
098ccbc55 [ALSA] dbri: driv... |
845 |
static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp) |
1bd9debf2 [ALSA] Add DBRI d... |
846 |
{ |
470f1f1a1 [ALSA] sparc dbri... |
847 |
if (pipe < 0 || pipe > DBRI_MAX_PIPE) { |
098ccbc55 [ALSA] dbri: driv... |
848 849 850 |
printk(KERN_ERR "DBRI: setup_pipe called " "with illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
851 852 853 854 |
return; } if ((sdp & 0xf800) != sdp) { |
098ccbc55 [ALSA] dbri: driv... |
855 856 857 |
printk(KERN_ERR "DBRI: setup_pipe called " "with strange SDP value "); |
1bd9debf2 [ALSA] Add DBRI d... |
858 859 860 861 862 863 864 865 866 867 868 869 870 |
/* sdp &= 0xf800; */ } /* If this is a fixed receive pipe, arrange for an interrupt * every time its data changes */ if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER)) sdp |= D_SDP_CHANGE; sdp |= D_PIPE(pipe); dbri->pipes[pipe].sdp = sdp; dbri->pipes[pipe].desc = -1; dbri->pipes[pipe].first_desc = -1; |
1bd9debf2 [ALSA] Add DBRI d... |
871 872 873 |
reset_pipe(dbri, pipe); } |
ea543f1ee [ALSA] sparc dbri... |
874 875 876 |
/* * Lock must be held before calling this. */ |
098ccbc55 [ALSA] dbri: driv... |
877 |
static void link_time_slot(struct snd_dbri *dbri, int pipe, |
294a30dc8 [ALSA] sparc dbri... |
878 |
int prevpipe, int nextpipe, |
1bd9debf2 [ALSA] Add DBRI d... |
879 880 |
int length, int cycle) { |
1be54c824 [ALSA] sparc dbri... |
881 |
s32 *cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
882 |
int val; |
1bd9debf2 [ALSA] Add DBRI d... |
883 |
|
098ccbc55 [ALSA] dbri: driv... |
884 |
if (pipe < 0 || pipe > DBRI_MAX_PIPE |
294a30dc8 [ALSA] sparc dbri... |
885 886 |
|| prevpipe < 0 || prevpipe > DBRI_MAX_PIPE || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { |
098ccbc55 [ALSA] dbri: driv... |
887 |
printk(KERN_ERR |
4338829e0 [ALSA] Several fi... |
888 889 |
"DBRI: link_time_slot called with illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
890 891 |
return; } |
098ccbc55 [ALSA] dbri: driv... |
892 |
if (dbri->pipes[pipe].sdp == 0 |
294a30dc8 [ALSA] sparc dbri... |
893 894 |
|| dbri->pipes[prevpipe].sdp == 0 || dbri->pipes[nextpipe].sdp == 0) { |
098ccbc55 [ALSA] dbri: driv... |
895 896 897 |
printk(KERN_ERR "DBRI: link_time_slot called " "on uninitialized pipe "); |
1bd9debf2 [ALSA] Add DBRI d... |
898 899 |
return; } |
294a30dc8 [ALSA] sparc dbri... |
900 |
dbri->pipes[prevpipe].nextpipe = pipe; |
1bd9debf2 [ALSA] Add DBRI d... |
901 |
dbri->pipes[pipe].nextpipe = nextpipe; |
1bd9debf2 [ALSA] Add DBRI d... |
902 |
dbri->pipes[pipe].length = length; |
1be54c824 [ALSA] sparc dbri... |
903 |
cmd = dbri_cmdlock(dbri, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
904 |
|
294a30dc8 [ALSA] sparc dbri... |
905 906 907 908 909 910 911 912 913 914 |
if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { /* Deal with CHI special case: * "If transmission on edges 0 or 1 is desired, then cycle n * (where n = # of bit times per frame...) must be used." * - DBRI data sheet, page 11 */ if (prevpipe == 16 && cycle == 0) cycle = dbri->chi_bpf; val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe; |
1bd9debf2 [ALSA] Add DBRI d... |
915 |
*(cmd++) = DBRI_CMD(D_DTS, 0, val); |
294a30dc8 [ALSA] sparc dbri... |
916 |
*(cmd++) = 0; |
1bd9debf2 [ALSA] Add DBRI d... |
917 918 |
*(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); |
1bd9debf2 [ALSA] Add DBRI d... |
919 |
} else { |
294a30dc8 [ALSA] sparc dbri... |
920 |
val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe; |
1bd9debf2 [ALSA] Add DBRI d... |
921 |
*(cmd++) = DBRI_CMD(D_DTS, 0, val); |
1bd9debf2 [ALSA] Add DBRI d... |
922 923 |
*(cmd++) = D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe); |
294a30dc8 [ALSA] sparc dbri... |
924 |
*(cmd++) = 0; |
1bd9debf2 [ALSA] Add DBRI d... |
925 |
} |
1be54c824 [ALSA] sparc dbri... |
926 |
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
927 |
|
1be54c824 [ALSA] sparc dbri... |
928 |
dbri_cmdsend(dbri, cmd, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
929 |
} |
ea543f1ee [ALSA] sparc dbri... |
930 931 932 933 |
#if 0 /* * Lock must be held before calling this. */ |
098ccbc55 [ALSA] dbri: driv... |
934 |
static void unlink_time_slot(struct snd_dbri *dbri, int pipe, |
1bd9debf2 [ALSA] Add DBRI d... |
935 936 937 |
enum in_or_out direction, int prevpipe, int nextpipe) { |
1be54c824 [ALSA] sparc dbri... |
938 |
s32 *cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
939 |
int val; |
098ccbc55 [ALSA] dbri: driv... |
940 |
if (pipe < 0 || pipe > DBRI_MAX_PIPE |
1be54c824 [ALSA] sparc dbri... |
941 942 |
|| prevpipe < 0 || prevpipe > DBRI_MAX_PIPE || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) { |
098ccbc55 [ALSA] dbri: driv... |
943 |
printk(KERN_ERR |
4338829e0 [ALSA] Several fi... |
944 945 |
"DBRI: unlink_time_slot called with illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
946 947 |
return; } |
1be54c824 [ALSA] sparc dbri... |
948 |
cmd = dbri_cmdlock(dbri, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
949 950 951 952 953 954 955 956 957 958 959 960 |
if (direction == PIPEinput) { val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe; *(cmd++) = DBRI_CMD(D_DTS, 0, val); *(cmd++) = D_TS_NEXT(nextpipe); *(cmd++) = 0; } else { val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe; *(cmd++) = DBRI_CMD(D_DTS, 0, val); *(cmd++) = 0; *(cmd++) = D_TS_NEXT(nextpipe); } |
1be54c824 [ALSA] sparc dbri... |
961 |
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
962 |
|
1be54c824 [ALSA] sparc dbri... |
963 |
dbri_cmdsend(dbri, cmd, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
964 |
} |
ea543f1ee [ALSA] sparc dbri... |
965 |
#endif |
1bd9debf2 [ALSA] Add DBRI d... |
966 967 968 969 970 971 972 973 974 975 976 977 978 |
/* xmit_fixed() / recv_fixed() * * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not * expected to change much, and which we don't need to buffer. * The DBRI only interrupts us when the data changes (receive pipes), * or only changes the data when this function is called (transmit pipes). * Only short pipes (numbers 16-31) can be used in fixed data mode. * * These function operate on a 32-bit field, no matter how large * the actual time slot is. The interrupt handler takes care of bit * ordering and alignment. An 8-bit time slot will always end up * in the low-order 8 bits, filled either MSB-first or LSB-first, |
ea543f1ee [ALSA] sparc dbri... |
979 980 981 |
* depending on the settings passed to setup_pipe(). * * Lock must not be held before calling it. |
1bd9debf2 [ALSA] Add DBRI d... |
982 |
*/ |
098ccbc55 [ALSA] dbri: driv... |
983 |
static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data) |
1bd9debf2 [ALSA] Add DBRI d... |
984 |
{ |
1be54c824 [ALSA] sparc dbri... |
985 |
s32 *cmd; |
ea543f1ee [ALSA] sparc dbri... |
986 |
unsigned long flags; |
1bd9debf2 [ALSA] Add DBRI d... |
987 |
|
470f1f1a1 [ALSA] sparc dbri... |
988 |
if (pipe < 16 || pipe > DBRI_MAX_PIPE) { |
4338829e0 [ALSA] Several fi... |
989 990 |
printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
991 992 993 994 |
return; } if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) { |
098ccbc55 [ALSA] dbri: driv... |
995 996 997 |
printk(KERN_ERR "DBRI: xmit_fixed: " "Uninitialized pipe %d ", pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
998 999 1000 1001 |
return; } if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { |
4338829e0 [ALSA] Several fi... |
1002 1003 |
printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d ", pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
1004 1005 1006 1007 |
return; } if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) { |
098ccbc55 [ALSA] dbri: driv... |
1008 1009 1010 |
printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d ", pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
1011 1012 1013 1014 1015 1016 1017 |
return; } /* DBRI short pipes always transmit LSB first */ if (dbri->pipes[pipe].sdp & D_SDP_MSB) data = reverse_bytes(data, dbri->pipes[pipe].length); |
1be54c824 [ALSA] sparc dbri... |
1018 |
cmd = dbri_cmdlock(dbri, 3); |
1bd9debf2 [ALSA] Add DBRI d... |
1019 1020 1021 |
*(cmd++) = DBRI_CMD(D_SSP, 0, pipe); *(cmd++) = data; |
1be54c824 [ALSA] sparc dbri... |
1022 |
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
1023 |
|
ea543f1ee [ALSA] sparc dbri... |
1024 |
spin_lock_irqsave(&dbri->lock, flags); |
1be54c824 [ALSA] sparc dbri... |
1025 |
dbri_cmdsend(dbri, cmd, 3); |
ea543f1ee [ALSA] sparc dbri... |
1026 |
spin_unlock_irqrestore(&dbri->lock, flags); |
1be54c824 [ALSA] sparc dbri... |
1027 |
dbri_cmdwait(dbri); |
ea543f1ee [ALSA] sparc dbri... |
1028 |
|
1bd9debf2 [ALSA] Add DBRI d... |
1029 |
} |
098ccbc55 [ALSA] dbri: driv... |
1030 |
static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr) |
1bd9debf2 [ALSA] Add DBRI d... |
1031 |
{ |
470f1f1a1 [ALSA] sparc dbri... |
1032 |
if (pipe < 16 || pipe > DBRI_MAX_PIPE) { |
098ccbc55 [ALSA] dbri: driv... |
1033 1034 1035 |
printk(KERN_ERR "DBRI: recv_fixed called with " "illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
1036 1037 1038 1039 |
return; } if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) { |
098ccbc55 [ALSA] dbri: driv... |
1040 1041 1042 |
printk(KERN_ERR "DBRI: recv_fixed called on " "non-fixed pipe %d ", pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
1043 1044 1045 1046 |
return; } if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) { |
098ccbc55 [ALSA] dbri: driv... |
1047 1048 1049 |
printk(KERN_ERR "DBRI: recv_fixed called on " "transmit pipe %d ", pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 |
return; } dbri->pipes[pipe].recv_fixed_ptr = ptr; } /* setup_descs() * * Setup transmit/receive data on a "long" pipe - i.e, one associated * with a DMA buffer. * * Only pipe numbers 0-15 can be used in this mode. * * This function takes a stream number pointing to a data buffer, * and work by building chains of descriptors which identify the * data buffers. Buffers too large for a single descriptor will * be spread across multiple descriptors. |
1be54c824 [ALSA] sparc dbri... |
1067 1068 |
* * All descriptors create a ring buffer. |
ea543f1ee [ALSA] sparc dbri... |
1069 1070 |
* * Lock must be held before calling this. |
1bd9debf2 [ALSA] Add DBRI d... |
1071 |
*/ |
098ccbc55 [ALSA] dbri: driv... |
1072 |
static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period) |
1bd9debf2 [ALSA] Add DBRI d... |
1073 |
{ |
475675d69 [ALSA] Remove xxx... |
1074 |
struct dbri_streaminfo *info = &dbri->stream_info[streamno]; |
1bd9debf2 [ALSA] Add DBRI d... |
1075 |
__u32 dvma_buffer; |
99dabfe71 [ALSA] dbri sparc... |
1076 |
int desc; |
1bd9debf2 [ALSA] Add DBRI d... |
1077 1078 1079 1080 1081 |
int len; int first_desc = -1; int last_desc = -1; if (info->pipe < 0 || info->pipe > 15) { |
4338829e0 [ALSA] Several fi... |
1082 1083 |
printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number "); |
1bd9debf2 [ALSA] Add DBRI d... |
1084 1085 1086 1087 |
return -2; } if (dbri->pipes[info->pipe].sdp == 0) { |
4338829e0 [ALSA] Several fi... |
1088 1089 |
printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d ", |
1bd9debf2 [ALSA] Add DBRI d... |
1090 1091 1092 1093 1094 1095 1096 1097 1098 |
info->pipe); return -2; } dvma_buffer = info->dvma_buffer; len = info->size; if (streamno == DBRI_PLAY) { if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) { |
098ccbc55 [ALSA] dbri: driv... |
1099 1100 1101 |
printk(KERN_ERR "DBRI: setup_descs: " "Called on receive pipe %d ", info->pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
1102 1103 1104 1105 |
return -2; } } else { if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) { |
098ccbc55 [ALSA] dbri: driv... |
1106 |
printk(KERN_ERR |
4338829e0 [ALSA] Several fi... |
1107 1108 |
"DBRI: setup_descs: Called on transmit pipe %d ", |
1bd9debf2 [ALSA] Add DBRI d... |
1109 1110 1111 |
info->pipe); return -2; } |
098ccbc55 [ALSA] dbri: driv... |
1112 1113 1114 |
/* Should be able to queue multiple buffers * to receive on a pipe */ |
1bd9debf2 [ALSA] Add DBRI d... |
1115 |
if (pipe_active(dbri, info->pipe)) { |
098ccbc55 [ALSA] dbri: driv... |
1116 1117 1118 |
printk(KERN_ERR "DBRI: recv_on_pipe: " "Called on active pipe %d ", info->pipe); |
1bd9debf2 [ALSA] Add DBRI d... |
1119 1120 1121 1122 1123 1124 |
return -2; } /* Make sure buffer size is multiple of four */ len &= ~3; } |
99dabfe71 [ALSA] dbri sparc... |
1125 1126 |
/* Free descriptors if pipe has any */ desc = dbri->pipes[info->pipe].first_desc; |
098ccbc55 [ALSA] dbri: driv... |
1127 |
if (desc >= 0) |
99dabfe71 [ALSA] dbri sparc... |
1128 |
do { |
098ccbc55 [ALSA] dbri: driv... |
1129 1130 |
dbri->dma->desc[desc].ba = 0; dbri->dma->desc[desc].nda = 0; |
99dabfe71 [ALSA] dbri sparc... |
1131 |
desc = dbri->next_desc[desc]; |
098ccbc55 [ALSA] dbri: driv... |
1132 1133 |
} while (desc != -1 && desc != dbri->pipes[info->pipe].first_desc); |
99dabfe71 [ALSA] dbri sparc... |
1134 1135 1136 1137 1138 |
dbri->pipes[info->pipe].desc = -1; dbri->pipes[info->pipe].first_desc = -1; desc = 0; |
1bd9debf2 [ALSA] Add DBRI d... |
1139 1140 1141 1142 |
while (len > 0) { int mylen; for (; desc < DBRI_NO_DESCS; desc++) { |
c27354460 [ALSA] sparc dbri... |
1143 |
if (!dbri->dma->desc[desc].ba) |
1bd9debf2 [ALSA] Add DBRI d... |
1144 1145 |
break; } |
cf68d212d [ALSA] dbri: more... |
1146 |
|
1bd9debf2 [ALSA] Add DBRI d... |
1147 |
if (desc == DBRI_NO_DESCS) { |
4338829e0 [ALSA] Several fi... |
1148 1149 |
printk(KERN_ERR "DBRI: setup_descs: No descriptors "); |
1bd9debf2 [ALSA] Add DBRI d... |
1150 1151 |
return -1; } |
1be54c824 [ALSA] sparc dbri... |
1152 1153 1154 |
if (len > DBRI_TD_MAXCNT) mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */ else |
1bd9debf2 [ALSA] Add DBRI d... |
1155 |
mylen = len; |
1be54c824 [ALSA] sparc dbri... |
1156 1157 |
if (mylen > period) |
1bd9debf2 [ALSA] Add DBRI d... |
1158 |
mylen = period; |
1bd9debf2 [ALSA] Add DBRI d... |
1159 |
|
c27354460 [ALSA] sparc dbri... |
1160 |
dbri->next_desc[desc] = -1; |
1bd9debf2 [ALSA] Add DBRI d... |
1161 1162 1163 1164 |
dbri->dma->desc[desc].ba = dvma_buffer; dbri->dma->desc[desc].nda = 0; if (streamno == DBRI_PLAY) { |
1bd9debf2 [ALSA] Add DBRI d... |
1165 1166 |
dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen); dbri->dma->desc[desc].word4 = 0; |
098ccbc55 [ALSA] dbri: driv... |
1167 |
dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B; |
1bd9debf2 [ALSA] Add DBRI d... |
1168 |
} else { |
1bd9debf2 [ALSA] Add DBRI d... |
1169 1170 1171 1172 |
dbri->dma->desc[desc].word1 = 0; dbri->dma->desc[desc].word4 = DBRI_RD_B | DBRI_RD_BCNT(mylen); } |
1be54c824 [ALSA] sparc dbri... |
1173 |
if (first_desc == -1) |
1bd9debf2 [ALSA] Add DBRI d... |
1174 |
first_desc = desc; |
1be54c824 [ALSA] sparc dbri... |
1175 |
else { |
c27354460 [ALSA] sparc dbri... |
1176 |
dbri->next_desc[last_desc] = desc; |
1bd9debf2 [ALSA] Add DBRI d... |
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 |
dbri->dma->desc[last_desc].nda = dbri->dma_dvma + dbri_dma_off(desc, desc); } last_desc = desc; dvma_buffer += mylen; len -= mylen; } if (first_desc == -1 || last_desc == -1) { |
098ccbc55 [ALSA] dbri: driv... |
1187 1188 1189 |
printk(KERN_ERR "DBRI: setup_descs: " " Not enough descriptors available "); |
1bd9debf2 [ALSA] Add DBRI d... |
1190 1191 |
return -1; } |
aaad3653a [ALSA] sparc dbri... |
1192 1193 1194 |
dbri->dma->desc[last_desc].nda = dbri->dma_dvma + dbri_dma_off(desc, first_desc); dbri->next_desc[last_desc] = first_desc; |
1bd9debf2 [ALSA] Add DBRI d... |
1195 1196 |
dbri->pipes[info->pipe].first_desc = first_desc; dbri->pipes[info->pipe].desc = first_desc; |
1be54c824 [ALSA] sparc dbri... |
1197 |
#ifdef DBRI_DEBUG |
098ccbc55 [ALSA] dbri: driv... |
1198 |
for (desc = first_desc; desc != -1;) { |
1bd9debf2 [ALSA] Add DBRI d... |
1199 1200 1201 1202 1203 1204 |
dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x ", desc, dbri->dma->desc[desc].word1, dbri->dma->desc[desc].ba, dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4); |
1be54c824 [ALSA] sparc dbri... |
1205 |
desc = dbri->next_desc[desc]; |
098ccbc55 [ALSA] dbri: driv... |
1206 |
if (desc == first_desc) |
1be54c824 [ALSA] sparc dbri... |
1207 |
break; |
1bd9debf2 [ALSA] Add DBRI d... |
1208 |
} |
1be54c824 [ALSA] sparc dbri... |
1209 |
#endif |
1bd9debf2 [ALSA] Add DBRI d... |
1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 |
return 0; } /* **************************************************************************** ************************** DBRI - CHI interface **************************** **************************************************************************** The CHI is a four-wire (clock, frame sync, data in, data out) time-division multiplexed serial interface which the DBRI can operate in either master (give clock/frame sync) or slave (take clock/frame sync) mode. */ enum master_or_slave { CHImaster, CHIslave }; |
ea543f1ee [ALSA] sparc dbri... |
1225 1226 1227 |
/* * Lock must not be held before calling it. */ |
098ccbc55 [ALSA] dbri: driv... |
1228 1229 |
static void reset_chi(struct snd_dbri *dbri, enum master_or_slave master_or_slave, |
1bd9debf2 [ALSA] Add DBRI d... |
1230 1231 |
int bits_per_frame) { |
1be54c824 [ALSA] sparc dbri... |
1232 |
s32 *cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
1233 |
int val; |
1bd9debf2 [ALSA] Add DBRI d... |
1234 |
|
1be54c824 [ALSA] sparc dbri... |
1235 |
/* Set CHI Anchor: Pipe 16 */ |
1bd9debf2 [ALSA] Add DBRI d... |
1236 |
|
1be54c824 [ALSA] sparc dbri... |
1237 |
cmd = dbri_cmdlock(dbri, 4); |
098ccbc55 [ALSA] dbri: driv... |
1238 |
val = D_DTS_VO | D_DTS_VI | D_DTS_INS |
1be54c824 [ALSA] sparc dbri... |
1239 1240 1241 1242 1243 1244 |
| D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16); *(cmd++) = DBRI_CMD(D_DTS, 0, val); *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16); *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); dbri_cmdsend(dbri, cmd, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
1245 |
|
1be54c824 [ALSA] sparc dbri... |
1246 1247 |
dbri->pipes[16].sdp = 1; dbri->pipes[16].nextpipe = 16; |
1bd9debf2 [ALSA] Add DBRI d... |
1248 |
|
1be54c824 [ALSA] sparc dbri... |
1249 |
cmd = dbri_cmdlock(dbri, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 |
if (master_or_slave == CHIslave) { /* Setup DBRI for CHI Slave - receive clock, frame sync (FS) * * CHICM = 0 (slave mode, 8 kHz frame rate) * IR = give immediate CHI status interrupt * EN = give CHI status interrupt upon change */ *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0)); } else { /* Setup DBRI for CHI Master - generate clock, FS * |
098ccbc55 [ALSA] dbri: driv... |
1262 1263 1264 |
* BPF = bits per 8 kHz frame * 12.288 MHz / CHICM_divisor = clock rate * FD = 1 - drive CHIFS on rising edge of CHICK |
1bd9debf2 [ALSA] Add DBRI d... |
1265 1266 1267 1268 1269 |
*/ int clockrate = bits_per_frame * 8; int divisor = 12288 / clockrate; if (divisor > 255 || divisor * clockrate != 12288) |
098ccbc55 [ALSA] dbri: driv... |
1270 1271 1272 |
printk(KERN_ERR "DBRI: illegal bits_per_frame " "in setup_chi "); |
1bd9debf2 [ALSA] Add DBRI d... |
1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 |
*(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD | D_CHI_BPF(bits_per_frame)); } dbri->chi_bpf = bits_per_frame; /* CHI Data Mode * * RCE = 0 - receive on falling edge of CHICK * XCE = 1 - transmit on rising edge of CHICK * XEN = 1 - enable transmitter * REN = 1 - enable receiver */ *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN); |
1be54c824 [ALSA] sparc dbri... |
1290 |
*(cmd++) = DBRI_CMD(D_PAUSE, 0, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
1291 |
|
1be54c824 [ALSA] sparc dbri... |
1292 |
dbri_cmdsend(dbri, cmd, 4); |
1bd9debf2 [ALSA] Add DBRI d... |
1293 1294 1295 1296 1297 1298 1299 1300 1301 |
} /* **************************************************************************** *********************** CS4215 audio codec management ********************** **************************************************************************** In the standard SPARC audio configuration, the CS4215 codec is attached to the DBRI via the CHI interface and few of the DBRI's PIO pins. |
ea543f1ee [ALSA] sparc dbri... |
1302 |
* Lock must not be held before calling it. |
1bd9debf2 [ALSA] Add DBRI d... |
1303 |
*/ |
afeacfd5f [ALSA] dbri: conv... |
1304 |
static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
1305 |
{ |
ea543f1ee [ALSA] sparc dbri... |
1306 1307 1308 |
unsigned long flags; spin_lock_irqsave(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 |
/* * Data mode: * Pipe 4: Send timeslots 1-4 (audio data) * Pipe 20: Send timeslots 5-8 (part of ctrl data) * Pipe 6: Receive timeslots 1-4 (audio data) * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via * interrupt, and the rest of the data (slot 5 and 8) is * not relevant for us (only for doublechecking). * * Control mode: |
098ccbc55 [ALSA] dbri: driv... |
1319 |
* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) |
1bd9debf2 [ALSA] Add DBRI d... |
1320 |
* Pipe 18: Receive timeslot 1 (clb). |
098ccbc55 [ALSA] dbri: driv... |
1321 |
* Pipe 19: Receive timeslot 7 (version). |
1bd9debf2 [ALSA] Add DBRI d... |
1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 |
*/ setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB); setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB); setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB); setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB); |
ea543f1ee [ALSA] sparc dbri... |
1332 |
spin_unlock_irqrestore(&dbri->lock, flags); |
1be54c824 [ALSA] sparc dbri... |
1333 1334 |
dbri_cmdwait(dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
1335 |
} |
afeacfd5f [ALSA] dbri: conv... |
1336 |
static __devinit int cs4215_init_data(struct cs4215 *mm) |
1bd9debf2 [ALSA] Add DBRI d... |
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 |
{ /* * No action, memory resetting only. * * Data Time Slot 5-8 * Speaker,Line and Headphone enable. Gain set to the half. * Input is mike. */ mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE; mm->data[1] = CS4215_RO(0x20) | CS4215_SE; mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1; mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf); /* * Control Time Slot 1-4 * 0: Default I/O voltage scale * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled * 2: Serial enable, CHI master, 128 bits per frame, clock 1 * 3: Tests disabled */ mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB; mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval; mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal; mm->ctrl[3] = 0; mm->status = 0; mm->version = 0xff; mm->precision = 8; /* For ULAW */ |
1be54c824 [ALSA] sparc dbri... |
1365 |
mm->channels = 1; |
1bd9debf2 [ALSA] Add DBRI d... |
1366 1367 1368 |
return 0; } |
098ccbc55 [ALSA] dbri: driv... |
1369 |
static void cs4215_setdata(struct snd_dbri *dbri, int muted) |
1bd9debf2 [ALSA] Add DBRI d... |
1370 1371 1372 1373 1374 1375 1376 1377 |
{ if (muted) { dbri->mm.data[0] |= 63; dbri->mm.data[1] |= 63; dbri->mm.data[2] &= ~15; dbri->mm.data[3] &= ~15; } else { /* Start by setting the playback attenuation. */ |
475675d69 [ALSA] Remove xxx... |
1378 |
struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; |
470f1f1a1 [ALSA] sparc dbri... |
1379 1380 |
int left_gain = info->left_gain & 0x3f; int right_gain = info->right_gain & 0x3f; |
1bd9debf2 [ALSA] Add DBRI d... |
1381 |
|
1bd9debf2 [ALSA] Add DBRI d... |
1382 1383 1384 1385 1386 1387 1388 |
dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */ dbri->mm.data[1] &= ~0x3f; dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain); dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain); /* Now set the recording gain. */ info = &dbri->stream_info[DBRI_REC]; |
470f1f1a1 [ALSA] sparc dbri... |
1389 1390 |
left_gain = info->left_gain & 0xf; right_gain = info->right_gain & 0xf; |
1bd9debf2 [ALSA] Add DBRI d... |
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 |
dbri->mm.data[2] |= CS4215_LG(left_gain); dbri->mm.data[3] |= CS4215_RG(right_gain); } xmit_fixed(dbri, 20, *(int *)dbri->mm.data); } /* * Set the CS4215 to data mode. */ |
098ccbc55 [ALSA] dbri: driv... |
1401 |
static void cs4215_open(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
1402 1403 1404 |
{ int data_width; u32 tmp; |
ea543f1ee [ALSA] sparc dbri... |
1405 |
unsigned long flags; |
1bd9debf2 [ALSA] Add DBRI d... |
1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 |
dprintk(D_MM, "cs4215_open: %d channels, %d bits ", dbri->mm.channels, dbri->mm.precision); /* Temporarily mute outputs, and wait 1/8000 sec (125 us) * to make sure this takes. This avoids clicking noises. */ cs4215_setdata(dbri, 1); udelay(125); /* * Data mode: * Pipe 4: Send timeslots 1-4 (audio data) * Pipe 20: Send timeslots 5-8 (part of ctrl data) * Pipe 6: Receive timeslots 1-4 (audio data) * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via * interrupt, and the rest of the data (slot 5 and 8) is * not relevant for us (only for doublechecking). * * Just like in control mode, the time slots are all offset by eight * bits. The CS4215, it seems, observes TSIN (the delayed signal) * even if it's the CHI master. Don't ask me... */ |
ea543f1ee [ALSA] sparc dbri... |
1431 |
spin_lock_irqsave(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 |
tmp = sbus_readl(dbri->regs + REG0); tmp &= ~(D_C); /* Disable CHI */ sbus_writel(tmp, dbri->regs + REG0); /* Switch CS4215 to data mode - set PIO3 to 1 */ sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 | (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2); reset_chi(dbri, CHIslave, 128); /* Note: this next doesn't work for 8-bit stereo, because the two * channels would be on timeslots 1 and 3, with 2 and 4 idle. * (See CS4215 datasheet Fig 15) * * DBRI non-contiguous mode would be required to make this work. */ data_width = dbri->mm.channels * dbri->mm.precision; |
294a30dc8 [ALSA] sparc dbri... |
1449 1450 1451 1452 |
link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset); link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32); link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset); link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40); |
1bd9debf2 [ALSA] Add DBRI d... |
1453 1454 1455 1456 1457 |
/* FIXME: enable CHI after _setdata? */ tmp = sbus_readl(dbri->regs + REG0); tmp |= D_C; /* Enable CHI */ sbus_writel(tmp, dbri->regs + REG0); |
ea543f1ee [ALSA] sparc dbri... |
1458 |
spin_unlock_irqrestore(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1459 1460 1461 1462 1463 1464 1465 |
cs4215_setdata(dbri, 0); } /* * Send the control information (i.e. audio format) */ |
098ccbc55 [ALSA] dbri: driv... |
1466 |
static int cs4215_setctrl(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
1467 1468 1469 |
{ int i, val; u32 tmp; |
ea543f1ee [ALSA] sparc dbri... |
1470 |
unsigned long flags; |
1bd9debf2 [ALSA] Add DBRI d... |
1471 1472 1473 1474 1475 1476 |
/* FIXME - let the CPU do something useful during these delays */ /* Temporarily mute outputs, and wait 1/8000 sec (125 us) * to make sure this takes. This avoids clicking noises. */ |
1bd9debf2 [ALSA] Add DBRI d... |
1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 |
cs4215_setdata(dbri, 1); udelay(125); /* * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec */ val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2); sbus_writel(val, dbri->regs + REG2); dprintk(D_MM, "cs4215_setctrl: reg2=0x%x ", val); udelay(34); /* In Control mode, the CS4215 is a slave device, so the DBRI must * operate as CHI master, supplying clocking and frame synchronization. * * In Data mode, however, the CS4215 must be CHI master to insure * that its data stream is synchronous with its codec. * * The upshot of all this? We start by putting the DBRI into master * mode, program the CS4215 in Control mode, then switch the CS4215 * into Data mode and put the DBRI into slave mode. Various timing * requirements must be observed along the way. * * Oh, and one more thing, on a SPARCStation 20 (and maybe * others?), the addressing of the CS4215's time slots is * offset by eight bits, so we add eight to all the "cycle" * values in the Define Time Slot (DTS) commands. This is * done in hardware by a TI 248 that delays the DBRI->4215 * frame sync signal by eight clock cycles. Anybody know why? */ |
ea543f1ee [ALSA] sparc dbri... |
1508 |
spin_lock_irqsave(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1509 1510 1511 1512 1513 1514 1515 1516 |
tmp = sbus_readl(dbri->regs + REG0); tmp &= ~D_C; /* Disable CHI */ sbus_writel(tmp, dbri->regs + REG0); reset_chi(dbri, CHImaster, 128); /* * Control mode: |
098ccbc55 [ALSA] dbri: driv... |
1517 |
* Pipe 17: Send timeslots 1-4 (slots 5-8 are read only) |
1bd9debf2 [ALSA] Add DBRI d... |
1518 |
* Pipe 18: Receive timeslot 1 (clb). |
098ccbc55 [ALSA] dbri: driv... |
1519 |
* Pipe 19: Receive timeslot 7 (version). |
1bd9debf2 [ALSA] Add DBRI d... |
1520 |
*/ |
294a30dc8 [ALSA] sparc dbri... |
1521 1522 1523 |
link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset); link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset); link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48); |
ea543f1ee [ALSA] sparc dbri... |
1524 |
spin_unlock_irqrestore(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1525 1526 1527 1528 |
/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */ dbri->mm.ctrl[0] &= ~CS4215_CLB; xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); |
ea543f1ee [ALSA] sparc dbri... |
1529 |
spin_lock_irqsave(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1530 1531 1532 |
tmp = sbus_readl(dbri->regs + REG0); tmp |= D_C; /* Enable CHI */ sbus_writel(tmp, dbri->regs + REG0); |
ea543f1ee [ALSA] sparc dbri... |
1533 |
spin_unlock_irqrestore(&dbri->lock, flags); |
1bd9debf2 [ALSA] Add DBRI d... |
1534 |
|
098ccbc55 [ALSA] dbri: driv... |
1535 |
for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) |
4338829e0 [ALSA] Several fi... |
1536 |
msleep_interruptible(1); |
098ccbc55 [ALSA] dbri: driv... |
1537 |
|
1bd9debf2 [ALSA] Add DBRI d... |
1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 |
if (i == 0) { dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x) ", dbri->mm.status); return -1; } /* Disable changes to our copy of the version number, as we are about * to leave control mode. */ recv_fixed(dbri, 19, NULL); /* Terminate CS4215 control mode - data sheet says * "Set CLB=1 and send two more frames of valid control info" */ dbri->mm.ctrl[0] |= CS4215_CLB; xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl); /* Two frames of control info @ 8kHz frame rate = 250 us delay */ udelay(250); cs4215_setdata(dbri, 0); return 0; } /* * Setup the codec with the sampling rate, audio format and number of * channels. * As part of the process we resend the settings for the data * timeslots as well. */ |
098ccbc55 [ALSA] dbri: driv... |
1570 |
static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate, |
1bd9debf2 [ALSA] Add DBRI d... |
1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 |
snd_pcm_format_t format, unsigned int channels) { int freq_idx; int ret = 0; /* Lookup index for this rate */ for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) { if (CS4215_FREQ[freq_idx].freq == rate) break; } if (CS4215_FREQ[freq_idx].freq != rate) { printk(KERN_WARNING "DBRI: Unsupported rate %d Hz ", rate); return -1; } switch (format) { case SNDRV_PCM_FORMAT_MU_LAW: dbri->mm.ctrl[1] = CS4215_DFR_ULAW; dbri->mm.precision = 8; break; case SNDRV_PCM_FORMAT_A_LAW: dbri->mm.ctrl[1] = CS4215_DFR_ALAW; dbri->mm.precision = 8; break; case SNDRV_PCM_FORMAT_U8: dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8; dbri->mm.precision = 8; break; case SNDRV_PCM_FORMAT_S16_BE: dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16; dbri->mm.precision = 16; break; default: printk(KERN_WARNING "DBRI: Unsupported format %d ", format); return -1; } /* Add rate parameters */ dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval; dbri->mm.ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal; dbri->mm.channels = channels; |
ab93c7ae5 [ALSA] sparc dbri... |
1616 |
if (channels == 2) |
1bd9debf2 [ALSA] Add DBRI d... |
1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 |
dbri->mm.ctrl[1] |= CS4215_DFR_STEREO; ret = cs4215_setctrl(dbri); if (ret == 0) cs4215_open(dbri); /* set codec to data mode */ return ret; } /* * */ |
afeacfd5f [ALSA] dbri: conv... |
1629 |
static __devinit int cs4215_init(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 |
{ u32 reg2 = sbus_readl(dbri->regs + REG2); dprintk(D_MM, "cs4215_init: reg2=0x%x ", reg2); /* Look for the cs4215 chips */ if (reg2 & D_PIO2) { dprintk(D_MM, "Onboard CS4215 detected "); dbri->mm.onboard = 1; } if (reg2 & D_PIO0) { dprintk(D_MM, "Speakerbox detected "); dbri->mm.onboard = 0; if (reg2 & D_PIO2) { printk(KERN_INFO "DBRI: Using speakerbox / " "ignoring onboard mmcodec. "); sbus_writel(D_ENPIO2, dbri->regs + REG2); } } if (!(reg2 & (D_PIO0 | D_PIO2))) { printk(KERN_ERR "DBRI: no mmcodec found. "); return -EIO; } cs4215_setup_pipes(dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 |
cs4215_init_data(&dbri->mm); /* Enable capture of the status & version timeslots. */ recv_fixed(dbri, 18, &dbri->mm.status); recv_fixed(dbri, 19, &dbri->mm.version); dbri->mm.offset = dbri->mm.onboard ? 0 : 8; if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) { dprintk(D_MM, "CS4215 failed probe at offset %d ", dbri->mm.offset); return -EIO; } dprintk(D_MM, "Found CS4215 at offset %d ", dbri->mm.offset); return 0; } /* **************************************************************************** *************************** DBRI interrupt handler ************************* **************************************************************************** The DBRI communicates with the CPU mainly via a circular interrupt buffer. When an interrupt is signaled, the CPU walks through the buffer and calls dbri_process_one_interrupt() for each interrupt word. Complicated interrupts are handled by dedicated functions (which appear first in this file). Any pending interrupts can be serviced by calling dbri_process_interrupt_buffer(), which works even if the CPU's |
1be54c824 [ALSA] sparc dbri... |
1691 |
interrupts are disabled. |
1bd9debf2 [ALSA] Add DBRI d... |
1692 1693 1694 1695 1696 |
*/ /* xmit_descs() * |
098ccbc55 [ALSA] dbri: driv... |
1697 |
* Starts transmitting the current TD's for recording/playing. |
1bd9debf2 [ALSA] Add DBRI d... |
1698 1699 |
* For playback, ALSA has filled the DMA memory with new data (we hope). */ |
1be54c824 [ALSA] sparc dbri... |
1700 |
static void xmit_descs(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
1701 |
{ |
475675d69 [ALSA] Remove xxx... |
1702 |
struct dbri_streaminfo *info; |
1be54c824 [ALSA] sparc dbri... |
1703 |
s32 *cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
1704 1705 1706 1707 1708 |
unsigned long flags; int first_td; if (dbri == NULL) return; /* Disabled */ |
1bd9debf2 [ALSA] Add DBRI d... |
1709 1710 |
info = &dbri->stream_info[DBRI_REC]; spin_lock_irqsave(&dbri->lock, flags); |
1be54c824 [ALSA] sparc dbri... |
1711 |
if (info->pipe >= 0) { |
1bd9debf2 [ALSA] Add DBRI d... |
1712 1713 1714 1715 1716 1717 |
first_td = dbri->pipes[info->pipe].first_desc; dprintk(D_DESC, "xmit_descs rec @ TD %d ", first_td); /* Stream could be closed by the time we run. */ |
aaad3653a [ALSA] sparc dbri... |
1718 1719 1720 1721 1722 |
if (first_td >= 0) { cmd = dbri_cmdlock(dbri, 2); *(cmd++) = DBRI_CMD(D_SDP, 0, dbri->pipes[info->pipe].sdp | D_SDP_P | D_SDP_EVERY | D_SDP_C); |
098ccbc55 [ALSA] dbri: driv... |
1723 1724 |
*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); |
aaad3653a [ALSA] sparc dbri... |
1725 |
dbri_cmdsend(dbri, cmd, 2); |
1bd9debf2 [ALSA] Add DBRI d... |
1726 |
|
aaad3653a [ALSA] sparc dbri... |
1727 1728 1729 |
/* Reset our admin of the pipe. */ dbri->pipes[info->pipe].desc = first_td; } |
1bd9debf2 [ALSA] Add DBRI d... |
1730 |
} |
1bd9debf2 [ALSA] Add DBRI d... |
1731 |
info = &dbri->stream_info[DBRI_PLAY]; |
1bd9debf2 [ALSA] Add DBRI d... |
1732 |
|
1be54c824 [ALSA] sparc dbri... |
1733 |
if (info->pipe >= 0) { |
1bd9debf2 [ALSA] Add DBRI d... |
1734 1735 1736 1737 1738 1739 |
first_td = dbri->pipes[info->pipe].first_desc; dprintk(D_DESC, "xmit_descs play @ TD %d ", first_td); /* Stream could be closed by the time we run. */ |
1be54c824 [ALSA] sparc dbri... |
1740 1741 1742 1743 1744 |
if (first_td >= 0) { cmd = dbri_cmdlock(dbri, 2); *(cmd++) = DBRI_CMD(D_SDP, 0, dbri->pipes[info->pipe].sdp | D_SDP_P | D_SDP_EVERY | D_SDP_C); |
098ccbc55 [ALSA] dbri: driv... |
1745 1746 |
*(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td); |
1be54c824 [ALSA] sparc dbri... |
1747 |
dbri_cmdsend(dbri, cmd, 2); |
1bd9debf2 [ALSA] Add DBRI d... |
1748 |
|
aaad3653a [ALSA] sparc dbri... |
1749 |
/* Reset our admin of the pipe. */ |
1be54c824 [ALSA] sparc dbri... |
1750 1751 |
dbri->pipes[info->pipe].desc = first_td; } |
1bd9debf2 [ALSA] Add DBRI d... |
1752 |
} |
ea543f1ee [ALSA] sparc dbri... |
1753 |
|
1bd9debf2 [ALSA] Add DBRI d... |
1754 1755 |
spin_unlock_irqrestore(&dbri->lock, flags); } |
1bd9debf2 [ALSA] Add DBRI d... |
1756 1757 1758 1759 1760 |
/* transmission_complete_intr() * * Called by main interrupt handler when DBRI signals transmission complete * on a pipe (interrupt triggered by the B bit in a transmit descriptor). * |
4338829e0 [ALSA] Several fi... |
1761 1762 |
* Walks through the pipe's list of transmit buffer descriptors and marks * them as available. Stops when the first descriptor is found without |
1bd9debf2 [ALSA] Add DBRI d... |
1763 |
* TBC (Transmit Buffer Complete) set, or we've run through them all. |
4338829e0 [ALSA] Several fi... |
1764 |
* |
ab93c7ae5 [ALSA] sparc dbri... |
1765 1766 1767 |
* The DMA buffers are not released. They form a ring buffer and * they are filled by ALSA while others are transmitted by DMA. * |
1bd9debf2 [ALSA] Add DBRI d... |
1768 |
*/ |
098ccbc55 [ALSA] dbri: driv... |
1769 |
static void transmission_complete_intr(struct snd_dbri *dbri, int pipe) |
1bd9debf2 [ALSA] Add DBRI d... |
1770 |
{ |
cf68d212d [ALSA] dbri: more... |
1771 1772 |
struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY]; int td = dbri->pipes[pipe].desc; |
1bd9debf2 [ALSA] Add DBRI d... |
1773 |
int status; |
1bd9debf2 [ALSA] Add DBRI d... |
1774 1775 1776 1777 1778 1779 1780 1781 |
while (td >= 0) { if (td >= DBRI_NO_DESCS) { printk(KERN_ERR "DBRI: invalid td on pipe %d ", pipe); return; } status = DBRI_TD_STATUS(dbri->dma->desc[td].word4); |
098ccbc55 [ALSA] dbri: driv... |
1782 |
if (!(status & DBRI_TD_TBC)) |
1bd9debf2 [ALSA] Add DBRI d... |
1783 |
break; |
1bd9debf2 [ALSA] Add DBRI d... |
1784 1785 1786 1787 1788 |
dprintk(D_INT, "TD %d, status 0x%02x ", td, status); dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */ |
1be54c824 [ALSA] sparc dbri... |
1789 |
info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1); |
1bd9debf2 [ALSA] Add DBRI d... |
1790 |
|
c27354460 [ALSA] sparc dbri... |
1791 |
td = dbri->next_desc[td]; |
1bd9debf2 [ALSA] Add DBRI d... |
1792 1793 1794 1795 |
dbri->pipes[pipe].desc = td; } /* Notify ALSA */ |
cf68d212d [ALSA] dbri: more... |
1796 1797 1798 |
spin_unlock(&dbri->lock); snd_pcm_period_elapsed(info->substream); spin_lock(&dbri->lock); |
1bd9debf2 [ALSA] Add DBRI d... |
1799 |
} |
098ccbc55 [ALSA] dbri: driv... |
1800 |
static void reception_complete_intr(struct snd_dbri *dbri, int pipe) |
1bd9debf2 [ALSA] Add DBRI d... |
1801 |
{ |
475675d69 [ALSA] Remove xxx... |
1802 |
struct dbri_streaminfo *info; |
1bd9debf2 [ALSA] Add DBRI d... |
1803 1804 1805 1806 1807 1808 1809 1810 |
int rd = dbri->pipes[pipe].desc; s32 status; if (rd < 0 || rd >= DBRI_NO_DESCS) { printk(KERN_ERR "DBRI: invalid rd on pipe %d ", pipe); return; } |
c27354460 [ALSA] sparc dbri... |
1811 |
dbri->pipes[pipe].desc = dbri->next_desc[rd]; |
1bd9debf2 [ALSA] Add DBRI d... |
1812 1813 1814 1815 1816 |
status = dbri->dma->desc[rd].word1; dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */ info = &dbri->stream_info[DBRI_REC]; info->offset += DBRI_RD_CNT(status); |
1bd9debf2 [ALSA] Add DBRI d... |
1817 1818 1819 1820 1821 1822 |
/* FIXME: Check status */ dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d ", rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status)); |
1bd9debf2 [ALSA] Add DBRI d... |
1823 |
/* Notify ALSA */ |
cf68d212d [ALSA] dbri: more... |
1824 1825 1826 |
spin_unlock(&dbri->lock); snd_pcm_period_elapsed(info->substream); spin_lock(&dbri->lock); |
1bd9debf2 [ALSA] Add DBRI d... |
1827 |
} |
098ccbc55 [ALSA] dbri: driv... |
1828 |
static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x) |
1bd9debf2 [ALSA] Add DBRI d... |
1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 |
{ int val = D_INTR_GETVAL(x); int channel = D_INTR_GETCHAN(x); int command = D_INTR_GETCMD(x); int code = D_INTR_GETCODE(x); #ifdef DBRI_DEBUG int rval = D_INTR_GETRVAL(x); #endif if (channel == D_INTR_CMD) { dprintk(D_CMD, "INTR: Command: %-5s Value:%d ", cmds[command], val); } else { dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x ", channel, code, rval); } |
1bd9debf2 [ALSA] Add DBRI d... |
1847 |
switch (code) { |
1be54c824 [ALSA] sparc dbri... |
1848 1849 1850 1851 1852 |
case D_INTR_CMDI: if (command != D_WAIT) printk(KERN_ERR "DBRI: Command read interrupt "); break; |
1bd9debf2 [ALSA] Add DBRI d... |
1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 |
case D_INTR_BRDY: reception_complete_intr(dbri, channel); break; case D_INTR_XCMP: case D_INTR_MINT: transmission_complete_intr(dbri, channel); break; case D_INTR_UNDR: /* UNDR - Transmission underrun * resend SDP command with clear pipe bit (C) set */ { |
1be54c824 [ALSA] sparc dbri... |
1865 1866 1867 1868 1869 |
/* FIXME: do something useful in case of underrun */ printk(KERN_ERR "DBRI: Underrun error "); #if 0 s32 *cmd; |
1bd9debf2 [ALSA] Add DBRI d... |
1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 |
int pipe = channel; int td = dbri->pipes[pipe].desc; dbri->dma->desc[td].word4 = 0; cmd = dbri_cmdlock(dbri, NoGetLock); *(cmd++) = DBRI_CMD(D_SDP, 0, dbri->pipes[pipe].sdp | D_SDP_P | D_SDP_C | D_SDP_2SAME); *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td); dbri_cmdsend(dbri, cmd); |
1be54c824 [ALSA] sparc dbri... |
1880 |
#endif |
1bd9debf2 [ALSA] Add DBRI d... |
1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 |
} break; case D_INTR_FXDT: /* FXDT - Fixed data change */ if (dbri->pipes[channel].sdp & D_SDP_MSB) val = reverse_bytes(val, dbri->pipes[channel].length); if (dbri->pipes[channel].recv_fixed_ptr) *(dbri->pipes[channel].recv_fixed_ptr) = val; break; default: if (channel != D_INTR_CMD) printk(KERN_WARNING "DBRI: Ignored Interrupt: %d (0x%x) ", code, x); } } /* dbri_process_interrupt_buffer advances through the DBRI's interrupt * buffer until it finds a zero word (indicating nothing more to do * right now). Non-zero words require processing and are handed off |
1be54c824 [ALSA] sparc dbri... |
1902 |
* to dbri_process_one_interrupt AFTER advancing the pointer. |
1bd9debf2 [ALSA] Add DBRI d... |
1903 |
*/ |
098ccbc55 [ALSA] dbri: driv... |
1904 |
static void dbri_process_interrupt_buffer(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
1905 1906 1907 1908 1909 1910 |
{ s32 x; while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) { dbri->dma->intr[dbri->dbri_irqp] = 0; dbri->dbri_irqp++; |
6fb982803 [ALSA] sparc dbri... |
1911 |
if (dbri->dbri_irqp == DBRI_INT_BLK) |
1bd9debf2 [ALSA] Add DBRI d... |
1912 |
dbri->dbri_irqp = 1; |
1bd9debf2 [ALSA] Add DBRI d... |
1913 1914 1915 1916 |
dbri_process_one_interrupt(dbri, x); } } |
7d12e780e IRQ: Maintain reg... |
1917 |
static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id) |
1bd9debf2 [ALSA] Add DBRI d... |
1918 |
{ |
475675d69 [ALSA] Remove xxx... |
1919 |
struct snd_dbri *dbri = dev_id; |
1bd9debf2 [ALSA] Add DBRI d... |
1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 |
static int errcnt = 0; int x; if (dbri == NULL) return IRQ_NONE; spin_lock(&dbri->lock); /* * Read it, so the interrupt goes away. */ x = sbus_readl(dbri->regs + REG1); if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) { u32 tmp; if (x & D_MRR) printk(KERN_ERR "DBRI: Multiple Error Ack on SBus reg1=0x%x ", x); if (x & D_MLE) printk(KERN_ERR "DBRI: Multiple Late Error on SBus reg1=0x%x ", x); if (x & D_LBG) printk(KERN_ERR "DBRI: Lost Bus Grant on SBus reg1=0x%x ", x); if (x & D_MBE) printk(KERN_ERR "DBRI: Burst Error on SBus reg1=0x%x ", x); /* Some of these SBus errors cause the chip's SBus circuitry * to be disabled, so just re-enable and try to keep going. * * The only one I've seen is MRR, which will be triggered * if you let a transmit pipe underrun, then try to CDP it. * |
4338829e0 [ALSA] Several fi... |
1960 |
* If these things persist, we reset the chip. |
1bd9debf2 [ALSA] Add DBRI d... |
1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 |
*/ if ((++errcnt) % 10 == 0) { dprintk(D_INT, "Interrupt errors exceeded. "); dbri_reset(dbri); } else { tmp = sbus_readl(dbri->regs + REG0); tmp &= ~(D_D); sbus_writel(tmp, dbri->regs + REG0); } } dbri_process_interrupt_buffer(dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
1974 1975 1976 1977 1978 1979 1980 1981 |
spin_unlock(&dbri->lock); return IRQ_HANDLED; } /**************************************************************************** PCM Interface ****************************************************************************/ |
475675d69 [ALSA] Remove xxx... |
1982 |
static struct snd_pcm_hardware snd_dbri_pcm_hw = { |
cf68d212d [ALSA] dbri: more... |
1983 1984 1985 |
.info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | |
2008f137e ALSA: Add missing... |
1986 1987 |
SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH, |
098ccbc55 [ALSA] dbri: driv... |
1988 1989 1990 1991 1992 |
.formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_BE, .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512, |
ab93c7ae5 [ALSA] sparc dbri... |
1993 |
.rate_min = 5512, |
1bd9debf2 [ALSA] Add DBRI d... |
1994 1995 1996 |
.rate_max = 48000, .channels_min = 1, .channels_max = 2, |
cf68d212d [ALSA] dbri: more... |
1997 |
.buffer_bytes_max = 64 * 1024, |
1bd9debf2 [ALSA] Add DBRI d... |
1998 1999 2000 2001 2002 |
.period_bytes_min = 1, .period_bytes_max = DBRI_TD_MAXCNT, .periods_min = 1, .periods_max = 1024, }; |
ab93c7ae5 [ALSA] sparc dbri... |
2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 |
static int snd_hw_rule_format(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); struct snd_mask fmt; snd_mask_any(&fmt); if (c->min > 1) { fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE; return snd_mask_refine(f, &fmt); } return 0; } static int snd_hw_rule_channels(struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) { struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); struct snd_interval ch; snd_interval_any(&ch); if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) { |
098ccbc55 [ALSA] dbri: driv... |
2029 2030 |
ch.min = 1; ch.max = 1; |
ab93c7ae5 [ALSA] sparc dbri... |
2031 2032 2033 2034 2035 |
ch.integer = 1; return snd_interval_refine(c, &ch); } return 0; } |
475675d69 [ALSA] Remove xxx... |
2036 |
static int snd_dbri_open(struct snd_pcm_substream *substream) |
1bd9debf2 [ALSA] Add DBRI d... |
2037 |
{ |
475675d69 [ALSA] Remove xxx... |
2038 2039 2040 |
struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct snd_pcm_runtime *runtime = substream->runtime; struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2041 2042 2043 2044 2045 2046 2047 2048 |
unsigned long flags; dprintk(D_USR, "open audio output. "); runtime->hw = snd_dbri_pcm_hw; spin_lock_irqsave(&dbri->lock, flags); info->substream = substream; |
1bd9debf2 [ALSA] Add DBRI d... |
2049 2050 2051 2052 |
info->offset = 0; info->dvma_buffer = 0; info->pipe = -1; spin_unlock_irqrestore(&dbri->lock, flags); |
098ccbc55 [ALSA] dbri: driv... |
2053 |
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, |
ae97dd9af [PATCH] NULL nois... |
2054 |
snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT, |
ab93c7ae5 [ALSA] sparc dbri... |
2055 |
-1); |
098ccbc55 [ALSA] dbri: driv... |
2056 2057 |
snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT, snd_hw_rule_channels, NULL, |
ab93c7ae5 [ALSA] sparc dbri... |
2058 2059 |
SNDRV_PCM_HW_PARAM_CHANNELS, -1); |
098ccbc55 [ALSA] dbri: driv... |
2060 |
|
1bd9debf2 [ALSA] Add DBRI d... |
2061 2062 2063 2064 |
cs4215_open(dbri); return 0; } |
475675d69 [ALSA] Remove xxx... |
2065 |
static int snd_dbri_close(struct snd_pcm_substream *substream) |
1bd9debf2 [ALSA] Add DBRI d... |
2066 |
{ |
475675d69 [ALSA] Remove xxx... |
2067 2068 |
struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2069 2070 2071 2072 |
dprintk(D_USR, "close audio output. "); info->substream = NULL; |
1bd9debf2 [ALSA] Add DBRI d... |
2073 2074 2075 2076 |
info->offset = 0; return 0; } |
475675d69 [ALSA] Remove xxx... |
2077 2078 |
static int snd_dbri_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) |
1bd9debf2 [ALSA] Add DBRI d... |
2079 |
{ |
475675d69 [ALSA] Remove xxx... |
2080 2081 2082 |
struct snd_pcm_runtime *runtime = substream->runtime; struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 |
int direction; int ret; /* set sampling rate, audio format and number of channels */ ret = cs4215_prepare(dbri, params_rate(hw_params), params_format(hw_params), params_channels(hw_params)); if (ret != 0) return ret; if ((ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) { |
4338829e0 [ALSA] Several fi... |
2095 2096 |
printk(KERN_ERR "malloc_pages failed with %d ", ret); |
1bd9debf2 [ALSA] Add DBRI d... |
2097 2098 2099 2100 2101 2102 2103 |
return ret; } /* hw_params can get called multiple times. Only map the DMA once. */ if (info->dvma_buffer == 0) { if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
738f2b7b8 sparc: Convert al... |
2104 |
direction = DMA_TO_DEVICE; |
1bd9debf2 [ALSA] Add DBRI d... |
2105 |
else |
738f2b7b8 sparc: Convert al... |
2106 |
direction = DMA_FROM_DEVICE; |
1bd9debf2 [ALSA] Add DBRI d... |
2107 |
|
7a715f460 sparc: Make SBUS ... |
2108 |
info->dvma_buffer = |
2bd320f89 dbri: Convert to ... |
2109 |
dma_map_single(&dbri->op->dev, |
738f2b7b8 sparc: Convert al... |
2110 2111 2112 |
runtime->dma_area, params_buffer_bytes(hw_params), direction); |
1bd9debf2 [ALSA] Add DBRI d... |
2113 2114 2115 2116 2117 2118 2119 2120 |
} direction = params_buffer_bytes(hw_params); dprintk(D_USR, "hw_params: %d bytes, dvma=%x ", direction, info->dvma_buffer); return 0; } |
475675d69 [ALSA] Remove xxx... |
2121 |
static int snd_dbri_hw_free(struct snd_pcm_substream *substream) |
1bd9debf2 [ALSA] Add DBRI d... |
2122 |
{ |
475675d69 [ALSA] Remove xxx... |
2123 2124 |
struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2125 |
int direction; |
99dabfe71 [ALSA] dbri sparc... |
2126 |
|
1bd9debf2 [ALSA] Add DBRI d... |
2127 2128 2129 2130 2131 2132 2133 |
dprintk(D_USR, "hw_free. "); /* hw_free can get called multiple times. Only unmap the DMA once. */ if (info->dvma_buffer) { if (DBRI_STREAMNO(substream) == DBRI_PLAY) |
738f2b7b8 sparc: Convert al... |
2134 |
direction = DMA_TO_DEVICE; |
1bd9debf2 [ALSA] Add DBRI d... |
2135 |
else |
738f2b7b8 sparc: Convert al... |
2136 |
direction = DMA_FROM_DEVICE; |
1bd9debf2 [ALSA] Add DBRI d... |
2137 |
|
2bd320f89 dbri: Convert to ... |
2138 |
dma_unmap_single(&dbri->op->dev, info->dvma_buffer, |
738f2b7b8 sparc: Convert al... |
2139 |
substream->runtime->buffer_size, direction); |
1bd9debf2 [ALSA] Add DBRI d... |
2140 2141 |
info->dvma_buffer = 0; } |
99dabfe71 [ALSA] dbri sparc... |
2142 2143 2144 2145 |
if (info->pipe != -1) { reset_pipe(dbri, info->pipe); info->pipe = -1; } |
1bd9debf2 [ALSA] Add DBRI d... |
2146 2147 2148 |
return snd_pcm_lib_free_pages(substream); } |
475675d69 [ALSA] Remove xxx... |
2149 |
static int snd_dbri_prepare(struct snd_pcm_substream *substream) |
1bd9debf2 [ALSA] Add DBRI d... |
2150 |
{ |
475675d69 [ALSA] Remove xxx... |
2151 2152 |
struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2153 2154 2155 2156 2157 |
int ret; info->size = snd_pcm_lib_buffer_bytes(substream); if (DBRI_STREAMNO(substream) == DBRI_PLAY) info->pipe = 4; /* Send pipe */ |
1be54c824 [ALSA] sparc dbri... |
2158 |
else |
1bd9debf2 [ALSA] Add DBRI d... |
2159 |
info->pipe = 6; /* Receive pipe */ |
1bd9debf2 [ALSA] Add DBRI d... |
2160 2161 |
spin_lock_irq(&dbri->lock); |
aaad3653a [ALSA] sparc dbri... |
2162 |
info->offset = 0; |
1bd9debf2 [ALSA] Add DBRI d... |
2163 |
|
098ccbc55 [ALSA] dbri: driv... |
2164 |
/* Setup the all the transmit/receive descriptors to cover the |
1bd9debf2 [ALSA] Add DBRI d... |
2165 2166 2167 2168 |
* whole DMA buffer. */ ret = setup_descs(dbri, DBRI_STREAMNO(substream), snd_pcm_lib_period_bytes(substream)); |
1bd9debf2 [ALSA] Add DBRI d... |
2169 2170 2171 2172 2173 2174 |
spin_unlock_irq(&dbri->lock); dprintk(D_USR, "prepare audio output. %d bytes ", info->size); return ret; } |
475675d69 [ALSA] Remove xxx... |
2175 |
static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd) |
1bd9debf2 [ALSA] Add DBRI d... |
2176 |
{ |
475675d69 [ALSA] Remove xxx... |
2177 2178 |
struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2179 2180 2181 2182 2183 2184 2185 |
int ret = 0; switch (cmd) { case SNDRV_PCM_TRIGGER_START: dprintk(D_USR, "start audio, period is %d bytes ", (int)snd_pcm_lib_period_bytes(substream)); |
1be54c824 [ALSA] sparc dbri... |
2186 2187 |
/* Re-submit the TDs. */ xmit_descs(dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
2188 2189 2190 2191 |
break; case SNDRV_PCM_TRIGGER_STOP: dprintk(D_USR, "stop audio. "); |
1bd9debf2 [ALSA] Add DBRI d... |
2192 2193 2194 2195 2196 2197 2198 2199 |
reset_pipe(dbri, info->pipe); break; default: ret = -EINVAL; } return ret; } |
475675d69 [ALSA] Remove xxx... |
2200 |
static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream) |
1bd9debf2 [ALSA] Add DBRI d... |
2201 |
{ |
475675d69 [ALSA] Remove xxx... |
2202 2203 |
struct snd_dbri *dbri = snd_pcm_substream_chip(substream); struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream); |
1bd9debf2 [ALSA] Add DBRI d... |
2204 2205 2206 2207 |
snd_pcm_uframes_t ret; ret = bytes_to_frames(substream->runtime, info->offset) % substream->runtime->buffer_size; |
1be54c824 [ALSA] sparc dbri... |
2208 2209 2210 |
dprintk(D_USR, "I/O pointer: %ld frames of %ld. ", ret, substream->runtime->buffer_size); |
1bd9debf2 [ALSA] Add DBRI d... |
2211 2212 |
return ret; } |
475675d69 [ALSA] Remove xxx... |
2213 |
static struct snd_pcm_ops snd_dbri_ops = { |
1bd9debf2 [ALSA] Add DBRI d... |
2214 2215 2216 2217 2218 2219 2220 2221 2222 |
.open = snd_dbri_open, .close = snd_dbri_close, .ioctl = snd_pcm_lib_ioctl, .hw_params = snd_dbri_hw_params, .hw_free = snd_dbri_hw_free, .prepare = snd_dbri_prepare, .trigger = snd_dbri_trigger, .pointer = snd_dbri_pointer, }; |
afeacfd5f [ALSA] dbri: conv... |
2223 |
static int __devinit snd_dbri_pcm(struct snd_card *card) |
1bd9debf2 [ALSA] Add DBRI d... |
2224 |
{ |
475675d69 [ALSA] Remove xxx... |
2225 |
struct snd_pcm *pcm; |
1bd9debf2 [ALSA] Add DBRI d... |
2226 |
int err; |
afeacfd5f [ALSA] dbri: conv... |
2227 |
if ((err = snd_pcm_new(card, |
1bd9debf2 [ALSA] Add DBRI d... |
2228 2229 2230 2231 2232 |
/* ID */ "sun_dbri", /* device */ 0, /* playback count */ 1, /* capture count */ 1, &pcm)) < 0) return err; |
1bd9debf2 [ALSA] Add DBRI d... |
2233 2234 2235 |
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops); snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops); |
afeacfd5f [ALSA] dbri: conv... |
2236 |
pcm->private_data = card->private_data; |
1bd9debf2 [ALSA] Add DBRI d... |
2237 |
pcm->info_flags = 0; |
afeacfd5f [ALSA] dbri: conv... |
2238 |
strcpy(pcm->name, card->shortname); |
1bd9debf2 [ALSA] Add DBRI d... |
2239 2240 2241 2242 |
if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, snd_dma_continuous_data(GFP_KERNEL), |
098ccbc55 [ALSA] dbri: driv... |
2243 |
64 * 1024, 64 * 1024)) < 0) |
1bd9debf2 [ALSA] Add DBRI d... |
2244 |
return err; |
1bd9debf2 [ALSA] Add DBRI d... |
2245 2246 2247 2248 2249 2250 2251 |
return 0; } /***************************************************************************** Mixer interface *****************************************************************************/ |
475675d69 [ALSA] Remove xxx... |
2252 2253 |
static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1bd9debf2 [ALSA] Add DBRI d... |
2254 2255 2256 2257 |
{ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 2; uinfo->value.integer.min = 0; |
cf68d212d [ALSA] dbri: more... |
2258 |
if (kcontrol->private_value == DBRI_PLAY) |
1bd9debf2 [ALSA] Add DBRI d... |
2259 |
uinfo->value.integer.max = DBRI_MAX_VOLUME; |
cf68d212d [ALSA] dbri: more... |
2260 |
else |
1bd9debf2 [ALSA] Add DBRI d... |
2261 |
uinfo->value.integer.max = DBRI_MAX_GAIN; |
1bd9debf2 [ALSA] Add DBRI d... |
2262 2263 |
return 0; } |
475675d69 [ALSA] Remove xxx... |
2264 2265 |
static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1bd9debf2 [ALSA] Add DBRI d... |
2266 |
{ |
475675d69 [ALSA] Remove xxx... |
2267 2268 |
struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); struct dbri_streaminfo *info; |
5e246b850 ALSA: Kill snd_as... |
2269 2270 2271 |
if (snd_BUG_ON(!dbri)) return -EINVAL; |
1bd9debf2 [ALSA] Add DBRI d... |
2272 |
info = &dbri->stream_info[kcontrol->private_value]; |
1bd9debf2 [ALSA] Add DBRI d... |
2273 2274 2275 2276 2277 |
ucontrol->value.integer.value[0] = info->left_gain; ucontrol->value.integer.value[1] = info->right_gain; return 0; } |
475675d69 [ALSA] Remove xxx... |
2278 2279 |
static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1bd9debf2 [ALSA] Add DBRI d... |
2280 |
{ |
475675d69 [ALSA] Remove xxx... |
2281 |
struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
098ccbc55 [ALSA] dbri: driv... |
2282 2283 |
struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value]; |
3b8924677 [ALSA] Check valu... |
2284 |
unsigned int vol[2]; |
1bd9debf2 [ALSA] Add DBRI d... |
2285 |
int changed = 0; |
3b8924677 [ALSA] Check valu... |
2286 2287 2288 2289 2290 2291 2292 2293 2294 |
vol[0] = ucontrol->value.integer.value[0]; vol[1] = ucontrol->value.integer.value[1]; if (kcontrol->private_value == DBRI_PLAY) { if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME) return -EINVAL; } else { if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN) return -EINVAL; } |
4581aa36f [ALSA] dbri - Fix... |
2295 2296 |
if (info->left_gain != vol[0]) { info->left_gain = vol[0]; |
1bd9debf2 [ALSA] Add DBRI d... |
2297 2298 |
changed = 1; } |
4581aa36f [ALSA] dbri - Fix... |
2299 2300 |
if (info->right_gain != vol[1]) { info->right_gain = vol[1]; |
1bd9debf2 [ALSA] Add DBRI d... |
2301 2302 |
changed = 1; } |
cf68d212d [ALSA] dbri: more... |
2303 |
if (changed) { |
1bd9debf2 [ALSA] Add DBRI d... |
2304 2305 2306 |
/* First mute outputs, and wait 1/8000 sec (125 us) * to make sure this takes. This avoids clicking noises. */ |
1bd9debf2 [ALSA] Add DBRI d... |
2307 2308 2309 |
cs4215_setdata(dbri, 1); udelay(125); cs4215_setdata(dbri, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
2310 2311 2312 |
} return changed; } |
475675d69 [ALSA] Remove xxx... |
2313 2314 |
static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) |
1bd9debf2 [ALSA] Add DBRI d... |
2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 |
{ int mask = (kcontrol->private_value >> 16) & 0xff; uinfo->type = (mask == 1) ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = 1; uinfo->value.integer.min = 0; uinfo->value.integer.max = mask; return 0; } |
475675d69 [ALSA] Remove xxx... |
2325 2326 |
static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1bd9debf2 [ALSA] Add DBRI d... |
2327 |
{ |
475675d69 [ALSA] Remove xxx... |
2328 |
struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
1bd9debf2 [ALSA] Add DBRI d... |
2329 2330 2331 2332 |
int elem = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0xff; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 1; |
5e246b850 ALSA: Kill snd_as... |
2333 2334 2335 |
if (snd_BUG_ON(!dbri)) return -EINVAL; |
1bd9debf2 [ALSA] Add DBRI d... |
2336 |
|
098ccbc55 [ALSA] dbri: driv... |
2337 |
if (elem < 4) |
1bd9debf2 [ALSA] Add DBRI d... |
2338 2339 |
ucontrol->value.integer.value[0] = (dbri->mm.data[elem] >> shift) & mask; |
098ccbc55 [ALSA] dbri: driv... |
2340 |
else |
1bd9debf2 [ALSA] Add DBRI d... |
2341 2342 |
ucontrol->value.integer.value[0] = (dbri->mm.ctrl[elem - 4] >> shift) & mask; |
1bd9debf2 [ALSA] Add DBRI d... |
2343 |
|
098ccbc55 [ALSA] dbri: driv... |
2344 |
if (invert == 1) |
1bd9debf2 [ALSA] Add DBRI d... |
2345 2346 |
ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0]; |
1bd9debf2 [ALSA] Add DBRI d... |
2347 2348 |
return 0; } |
475675d69 [ALSA] Remove xxx... |
2349 2350 |
static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) |
1bd9debf2 [ALSA] Add DBRI d... |
2351 |
{ |
475675d69 [ALSA] Remove xxx... |
2352 |
struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol); |
1bd9debf2 [ALSA] Add DBRI d... |
2353 2354 2355 2356 2357 2358 |
int elem = kcontrol->private_value & 0xff; int shift = (kcontrol->private_value >> 8) & 0xff; int mask = (kcontrol->private_value >> 16) & 0xff; int invert = (kcontrol->private_value >> 24) & 1; int changed = 0; unsigned short val; |
5e246b850 ALSA: Kill snd_as... |
2359 2360 2361 |
if (snd_BUG_ON(!dbri)) return -EINVAL; |
1bd9debf2 [ALSA] Add DBRI d... |
2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 |
val = (ucontrol->value.integer.value[0] & mask); if (invert == 1) val = mask - val; val <<= shift; if (elem < 4) { dbri->mm.data[elem] = (dbri->mm.data[elem] & ~(mask << shift)) | val; changed = (val != dbri->mm.data[elem]); } else { dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] & ~(mask << shift)) | val; changed = (val != dbri->mm.ctrl[elem - 4]); } dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, " "mixer-value=%ld, mm-value=0x%x ", mask, changed, ucontrol->value.integer.value[0], dbri->mm.data[elem & 3]); if (changed) { /* First mute outputs, and wait 1/8000 sec (125 us) * to make sure this takes. This avoids clicking noises. */ |
1bd9debf2 [ALSA] Add DBRI d... |
2388 2389 2390 |
cs4215_setdata(dbri, 1); udelay(125); cs4215_setdata(dbri, 0); |
1bd9debf2 [ALSA] Add DBRI d... |
2391 2392 2393 2394 2395 2396 2397 2398 |
} return changed; } /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control timeslots. Shift is the bit offset in the timeslot, mask defines the number of bits. invert is a boolean for use with attenuation. */ |
098ccbc55 [ALSA] dbri: driv... |
2399 2400 2401 2402 2403 2404 |
#define CS4215_SINGLE(xname, entry, shift, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ .info = snd_cs4215_info_single, \ .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \ .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \ ((invert) << 24) }, |
1bd9debf2 [ALSA] Add DBRI d... |
2405 |
|
475675d69 [ALSA] Remove xxx... |
2406 |
static struct snd_kcontrol_new dbri_controls[] __devinitdata = { |
1bd9debf2 [ALSA] Add DBRI d... |
2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 |
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Playback Volume", .info = snd_cs4215_info_volume, .get = snd_cs4215_get_volume, .put = snd_cs4215_put_volume, .private_value = DBRI_PLAY, }, CS4215_SINGLE("Headphone switch", 0, 7, 1, 0) CS4215_SINGLE("Line out switch", 0, 6, 1, 0) CS4215_SINGLE("Speaker switch", 1, 6, 1, 0) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Capture Volume", .info = snd_cs4215_info_volume, .get = snd_cs4215_get_volume, .put = snd_cs4215_put_volume, .private_value = DBRI_REC, }, /* FIXME: mic/line switch */ CS4215_SINGLE("Line in switch", 2, 4, 1, 0) CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0) CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1) CS4215_SINGLE("Mic boost", 4, 4, 1, 1) }; |
afeacfd5f [ALSA] dbri: conv... |
2432 |
static int __devinit snd_dbri_mixer(struct snd_card *card) |
1bd9debf2 [ALSA] Add DBRI d... |
2433 |
{ |
1bd9debf2 [ALSA] Add DBRI d... |
2434 |
int idx, err; |
afeacfd5f [ALSA] dbri: conv... |
2435 |
struct snd_dbri *dbri; |
1bd9debf2 [ALSA] Add DBRI d... |
2436 |
|
5e246b850 ALSA: Kill snd_as... |
2437 2438 |
if (snd_BUG_ON(!card || !card->private_data)) return -EINVAL; |
afeacfd5f [ALSA] dbri: conv... |
2439 |
dbri = card->private_data; |
1bd9debf2 [ALSA] Add DBRI d... |
2440 |
|
1bd9debf2 [ALSA] Add DBRI d... |
2441 |
strcpy(card->mixername, card->shortname); |
6c2d8b5dc [PATCH] sound/spa... |
2442 |
for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) { |
cf68d212d [ALSA] dbri: more... |
2443 2444 2445 |
err = snd_ctl_add(card, snd_ctl_new1(&dbri_controls[idx], dbri)); if (err < 0) |
1bd9debf2 [ALSA] Add DBRI d... |
2446 2447 2448 2449 2450 2451 |
return err; } for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) { dbri->stream_info[idx].left_gain = 0; dbri->stream_info[idx].right_gain = 0; |
1bd9debf2 [ALSA] Add DBRI d... |
2452 2453 2454 2455 2456 2457 2458 2459 |
} return 0; } /**************************************************************************** /proc interface ****************************************************************************/ |
098ccbc55 [ALSA] dbri: driv... |
2460 2461 |
static void dbri_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) |
1bd9debf2 [ALSA] Add DBRI d... |
2462 |
{ |
475675d69 [ALSA] Remove xxx... |
2463 |
struct snd_dbri *dbri = entry->private_data; |
1bd9debf2 [ALSA] Add DBRI d... |
2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 |
snd_iprintf(buffer, "REG0: 0x%x ", sbus_readl(dbri->regs + REG0)); snd_iprintf(buffer, "REG2: 0x%x ", sbus_readl(dbri->regs + REG2)); snd_iprintf(buffer, "REG8: 0x%x ", sbus_readl(dbri->regs + REG8)); snd_iprintf(buffer, "REG9: 0x%x ", sbus_readl(dbri->regs + REG9)); } #ifdef DBRI_DEBUG |
098ccbc55 [ALSA] dbri: driv... |
2476 |
static void dbri_debug_read(struct snd_info_entry *entry, |
475675d69 [ALSA] Remove xxx... |
2477 |
struct snd_info_buffer *buffer) |
1bd9debf2 [ALSA] Add DBRI d... |
2478 |
{ |
475675d69 [ALSA] Remove xxx... |
2479 |
struct snd_dbri *dbri = entry->private_data; |
1bd9debf2 [ALSA] Add DBRI d... |
2480 2481 2482 |
int pipe; snd_iprintf(buffer, "debug=%d ", dbri_debug); |
1bd9debf2 [ALSA] Add DBRI d... |
2483 2484 2485 2486 2487 |
for (pipe = 0; pipe < 32; pipe++) { if (pipe_active(dbri, pipe)) { struct dbri_pipe *pptr = &dbri->pipes[pipe]; snd_iprintf(buffer, "Pipe %d: %s SDP=0x%x desc=%d, " |
294a30dc8 [ALSA] sparc dbri... |
2488 2489 |
"len=%d next %d ", |
1bd9debf2 [ALSA] Add DBRI d... |
2490 |
pipe, |
cf68d212d [ALSA] dbri: more... |
2491 2492 |
(pptr->sdp & D_SDP_TO_SER) ? "output" : "input", |
5fc3a2b25 [ALSA] sparc dbri... |
2493 |
pptr->sdp, pptr->desc, |
294a30dc8 [ALSA] sparc dbri... |
2494 |
pptr->length, pptr->nextpipe); |
1bd9debf2 [ALSA] Add DBRI d... |
2495 2496 2497 |
} } } |
1bd9debf2 [ALSA] Add DBRI d... |
2498 |
#endif |
e7bd3de08 ALSA: make sparc/... |
2499 |
static void __devinit snd_dbri_proc(struct snd_card *card) |
1bd9debf2 [ALSA] Add DBRI d... |
2500 |
{ |
afeacfd5f [ALSA] dbri: conv... |
2501 |
struct snd_dbri *dbri = card->private_data; |
475675d69 [ALSA] Remove xxx... |
2502 |
struct snd_info_entry *entry; |
1bd9debf2 [ALSA] Add DBRI d... |
2503 |
|
afeacfd5f [ALSA] dbri: conv... |
2504 |
if (!snd_card_proc_new(card, "regs", &entry)) |
bf850204a [ALSA] Remove unn... |
2505 |
snd_info_set_text_ops(entry, dbri, dbri_regs_read); |
1bd9debf2 [ALSA] Add DBRI d... |
2506 2507 |
#ifdef DBRI_DEBUG |
afeacfd5f [ALSA] dbri: conv... |
2508 |
if (!snd_card_proc_new(card, "debug", &entry)) { |
bf850204a [ALSA] Remove unn... |
2509 |
snd_info_set_text_ops(entry, dbri, dbri_debug_read); |
8cb7b63f5 [ALSA] dbri - Don... |
2510 2511 |
entry->mode = S_IFREG | S_IRUGO; /* Readable only. */ } |
1bd9debf2 [ALSA] Add DBRI d... |
2512 2513 2514 2515 2516 2517 2518 2519 |
#endif } /* **************************************************************************** **************************** Initialization ******************************** **************************************************************************** */ |
098ccbc55 [ALSA] dbri: driv... |
2520 |
static void snd_dbri_free(struct snd_dbri *dbri); |
1bd9debf2 [ALSA] Add DBRI d... |
2521 |
|
afeacfd5f [ALSA] dbri: conv... |
2522 |
static int __devinit snd_dbri_create(struct snd_card *card, |
2dc115813 of/device: Replac... |
2523 |
struct platform_device *op, |
2bd320f89 dbri: Convert to ... |
2524 |
int irq, int dev) |
1bd9debf2 [ALSA] Add DBRI d... |
2525 |
{ |
475675d69 [ALSA] Remove xxx... |
2526 |
struct snd_dbri *dbri = card->private_data; |
1bd9debf2 [ALSA] Add DBRI d... |
2527 2528 2529 |
int err; spin_lock_init(&dbri->lock); |
2bd320f89 dbri: Convert to ... |
2530 |
dbri->op = op; |
afeacfd5f [ALSA] dbri: conv... |
2531 |
dbri->irq = irq; |
1bd9debf2 [ALSA] Add DBRI d... |
2532 |
|
2bd320f89 dbri: Convert to ... |
2533 |
dbri->dma = dma_alloc_coherent(&op->dev, |
738f2b7b8 sparc: Convert al... |
2534 2535 |
sizeof(struct dbri_dma), &dbri->dma_dvma, GFP_ATOMIC); |
be3766493 dbri: check dma_a... |
2536 2537 |
if (!dbri->dma) return -ENOMEM; |
1bd9debf2 [ALSA] Add DBRI d... |
2538 2539 2540 2541 2542 2543 2544 |
memset((void *)dbri->dma, 0, sizeof(struct dbri_dma)); dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x) ", dbri->dma, dbri->dma_dvma); /* Map the registers into memory. */ |
2bd320f89 dbri: Convert to ... |
2545 2546 2547 |
dbri->regs_size = resource_size(&op->resource[0]); dbri->regs = of_ioremap(&op->resource[0], 0, dbri->regs_size, "DBRI Registers"); |
1bd9debf2 [ALSA] Add DBRI d... |
2548 2549 2550 |
if (!dbri->regs) { printk(KERN_ERR "DBRI: could not allocate registers "); |
2bd320f89 dbri: Convert to ... |
2551 |
dma_free_coherent(&op->dev, sizeof(struct dbri_dma), |
738f2b7b8 sparc: Convert al... |
2552 |
(void *)dbri->dma, dbri->dma_dvma); |
1bd9debf2 [ALSA] Add DBRI d... |
2553 2554 |
return -EIO; } |
65ca68b30 [PATCH] irq-flags... |
2555 |
err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED, |
1bd9debf2 [ALSA] Add DBRI d... |
2556 2557 2558 2559 |
"DBRI audio", dbri); if (err) { printk(KERN_ERR "DBRI: Can't get irq %d ", dbri->irq); |
2bd320f89 dbri: Convert to ... |
2560 2561 |
of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size); dma_free_coherent(&op->dev, sizeof(struct dbri_dma), |
738f2b7b8 sparc: Convert al... |
2562 |
(void *)dbri->dma, dbri->dma_dvma); |
1bd9debf2 [ALSA] Add DBRI d... |
2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 |
return err; } /* Do low level initialization of the DBRI and CS4215 chips */ dbri_initialize(dbri); err = cs4215_init(dbri); if (err) { snd_dbri_free(dbri); return err; } |
1bd9debf2 [ALSA] Add DBRI d... |
2573 2574 |
return 0; } |
098ccbc55 [ALSA] dbri: driv... |
2575 |
static void snd_dbri_free(struct snd_dbri *dbri) |
1bd9debf2 [ALSA] Add DBRI d... |
2576 2577 2578 2579 2580 2581 2582 2583 2584 |
{ dprintk(D_GEN, "snd_dbri_free "); dbri_reset(dbri); if (dbri->irq) free_irq(dbri->irq, dbri); if (dbri->regs) |
2bd320f89 dbri: Convert to ... |
2585 |
of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size); |
1bd9debf2 [ALSA] Add DBRI d... |
2586 2587 |
if (dbri->dma) |
2bd320f89 dbri: Convert to ... |
2588 |
dma_free_coherent(&dbri->op->dev, |
738f2b7b8 sparc: Convert al... |
2589 2590 |
sizeof(struct dbri_dma), (void *)dbri->dma, dbri->dma_dvma); |
1bd9debf2 [ALSA] Add DBRI d... |
2591 |
} |
f07eb223a dt/sound: Elimina... |
2592 |
static int __devinit dbri_probe(struct platform_device *op) |
1bd9debf2 [ALSA] Add DBRI d... |
2593 |
{ |
475675d69 [ALSA] Remove xxx... |
2594 |
struct snd_dbri *dbri; |
1bd9debf2 [ALSA] Add DBRI d... |
2595 |
struct resource *rp; |
475675d69 [ALSA] Remove xxx... |
2596 |
struct snd_card *card; |
1bd9debf2 [ALSA] Add DBRI d... |
2597 |
static int dev = 0; |
2bd320f89 dbri: Convert to ... |
2598 |
int irq; |
1bd9debf2 [ALSA] Add DBRI d... |
2599 |
int err; |
1bd9debf2 [ALSA] Add DBRI d... |
2600 2601 2602 2603 2604 2605 |
if (dev >= SNDRV_CARDS) return -ENODEV; if (!enable[dev]) { dev++; return -ENOENT; } |
1636f8ac2 sparc/of: Move of... |
2606 |
irq = op->archdata.irqs[0]; |
afeacfd5f [ALSA] dbri: conv... |
2607 2608 2609 |
if (irq <= 0) { printk(KERN_ERR "DBRI-%d: No IRQ. ", dev); |
4338829e0 [ALSA] Several fi... |
2610 2611 |
return -ENODEV; } |
1bd9debf2 [ALSA] Add DBRI d... |
2612 |
|
bd7dd77c2 ALSA: Convert to ... |
2613 2614 2615 2616 |
err = snd_card_create(index[dev], id[dev], THIS_MODULE, sizeof(struct snd_dbri), &card); if (err < 0) return err; |
1bd9debf2 [ALSA] Add DBRI d... |
2617 2618 2619 |
strcpy(card->driver, "DBRI"); strcpy(card->shortname, "Sun DBRI"); |
2bd320f89 dbri: Convert to ... |
2620 |
rp = &op->resource[0]; |
5863aa651 [PATCH] sparc: re... |
2621 |
sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d", |
1bd9debf2 [ALSA] Add DBRI d... |
2622 |
card->shortname, |
afeacfd5f [ALSA] dbri: conv... |
2623 |
rp->flags & 0xffL, (unsigned long long)rp->start, irq); |
1bd9debf2 [ALSA] Add DBRI d... |
2624 |
|
2bd320f89 dbri: Convert to ... |
2625 |
err = snd_dbri_create(card, op, irq, dev); |
afeacfd5f [ALSA] dbri: conv... |
2626 |
if (err < 0) { |
1bd9debf2 [ALSA] Add DBRI d... |
2627 2628 2629 |
snd_card_free(card); return err; } |
475675d69 [ALSA] Remove xxx... |
2630 |
dbri = card->private_data; |
afeacfd5f [ALSA] dbri: conv... |
2631 |
err = snd_dbri_pcm(card); |
cf68d212d [ALSA] dbri: more... |
2632 |
if (err < 0) |
16dab54b8 [ALSA] Add snd_ca... |
2633 |
goto _err; |
1bd9debf2 [ALSA] Add DBRI d... |
2634 |
|
afeacfd5f [ALSA] dbri: conv... |
2635 |
err = snd_dbri_mixer(card); |
cf68d212d [ALSA] dbri: more... |
2636 |
if (err < 0) |
16dab54b8 [ALSA] Add snd_ca... |
2637 |
goto _err; |
1bd9debf2 [ALSA] Add DBRI d... |
2638 2639 |
/* /proc file handling */ |
afeacfd5f [ALSA] dbri: conv... |
2640 |
snd_dbri_proc(card); |
2bd320f89 dbri: Convert to ... |
2641 |
dev_set_drvdata(&op->dev, card); |
1bd9debf2 [ALSA] Add DBRI d... |
2642 |
|
098ccbc55 [ALSA] dbri: driv... |
2643 2644 |
err = snd_card_register(card); if (err < 0) |
16dab54b8 [ALSA] Add snd_ca... |
2645 |
goto _err; |
1bd9debf2 [ALSA] Add DBRI d... |
2646 2647 2648 2649 |
printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d) ", dev, dbri->regs, |
61c7a080a of: Always use 's... |
2650 |
dbri->irq, op->dev.of_node->name[9], dbri->mm.version); |
1bd9debf2 [ALSA] Add DBRI d... |
2651 2652 2653 |
dev++; return 0; |
16dab54b8 [ALSA] Add snd_ca... |
2654 |
|
098ccbc55 [ALSA] dbri: driv... |
2655 |
_err: |
16dab54b8 [ALSA] Add snd_ca... |
2656 2657 2658 |
snd_dbri_free(dbri); snd_card_free(card); return err; |
1bd9debf2 [ALSA] Add DBRI d... |
2659 |
} |
2dc115813 of/device: Replac... |
2660 |
static int __devexit dbri_remove(struct platform_device *op) |
1bd9debf2 [ALSA] Add DBRI d... |
2661 |
{ |
2bd320f89 dbri: Convert to ... |
2662 |
struct snd_card *card = dev_get_drvdata(&op->dev); |
1bd9debf2 [ALSA] Add DBRI d... |
2663 |
|
afeacfd5f [ALSA] dbri: conv... |
2664 2665 |
snd_dbri_free(card->private_data); snd_card_free(card); |
1bd9debf2 [ALSA] Add DBRI d... |
2666 |
|
2bd320f89 dbri: Convert to ... |
2667 |
dev_set_drvdata(&op->dev, NULL); |
afeacfd5f [ALSA] dbri: conv... |
2668 2669 |
return 0; |
1bd9debf2 [ALSA] Add DBRI d... |
2670 |
} |
fd098316e sparc: Annotate o... |
2671 |
static const struct of_device_id dbri_match[] = { |
afeacfd5f [ALSA] dbri: conv... |
2672 2673 2674 2675 2676 2677 2678 2679 |
{ .name = "SUNW,DBRIe", }, { .name = "SUNW,DBRIf", }, {}, }; |
1bd9debf2 [ALSA] Add DBRI d... |
2680 |
|
afeacfd5f [ALSA] dbri: conv... |
2681 |
MODULE_DEVICE_TABLE(of, dbri_match); |
1bd9debf2 [ALSA] Add DBRI d... |
2682 |
|
f07eb223a dt/sound: Elimina... |
2683 |
static struct platform_driver dbri_sbus_driver = { |
4018294b5 of: Remove duplic... |
2684 2685 2686 2687 2688 |
.driver = { .name = "dbri", .owner = THIS_MODULE, .of_match_table = dbri_match, }, |
afeacfd5f [ALSA] dbri: conv... |
2689 2690 2691 |
.probe = dbri_probe, .remove = __devexit_p(dbri_remove), }; |
a09452eeb ALSA: convert sou... |
2692 |
module_platform_driver(dbri_sbus_driver); |