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drivers/dma/pxa_dma.c
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// SPDX-License-Identifier: GPL-2.0-only |
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/* * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr> |
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*/ #include <linux/err.h> #include <linux/module.h> #include <linux/init.h> #include <linux/types.h> #include <linux/interrupt.h> #include <linux/dma-mapping.h> #include <linux/slab.h> #include <linux/dmaengine.h> #include <linux/platform_device.h> #include <linux/device.h> #include <linux/platform_data/mmp_dma.h> #include <linux/dmapool.h> #include <linux/of_device.h> #include <linux/of_dma.h> #include <linux/of.h> |
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#include <linux/wait.h> |
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#include <linux/dma/pxa-dma.h> #include "dmaengine.h" #include "virt-dma.h" #define DCSR(n) (0x0000 + ((n) << 2)) #define DALGN(n) 0x00a0 #define DINT 0x00f0 #define DDADR(n) (0x0200 + ((n) << 4)) #define DSADR(n) (0x0204 + ((n) << 4)) #define DTADR(n) (0x0208 + ((n) << 4)) #define DCMD(n) (0x020c + ((n) << 4)) #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */ #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */ #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */ #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */ #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ #define DDADR_STOP BIT(0) /* Stop (read / write) */ #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */ #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */ #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */ #define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */ #define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ #define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ #define PDMA_ALIGNMENT 3 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1)) struct pxad_desc_hw { u32 ddadr; /* Points to the next descriptor + flags */ u32 dsadr; /* DSADR value for the current transfer */ u32 dtadr; /* DTADR value for the current transfer */ u32 dcmd; /* DCMD value for the current transfer */ } __aligned(16); struct pxad_desc_sw { struct virt_dma_desc vd; /* Virtual descriptor */ int nb_desc; /* Number of hw. descriptors */ size_t len; /* Number of bytes xfered */ dma_addr_t first; /* First descriptor's addr */ /* At least one descriptor has an src/dst address not multiple of 8 */ bool misaligned; bool cyclic; struct dma_pool *desc_pool; /* Channel's used allocator */ struct pxad_desc_hw *hw_desc[]; /* DMA coherent descriptors */ }; struct pxad_phy { int idx; void __iomem *base; struct pxad_chan *vchan; }; struct pxad_chan { struct virt_dma_chan vc; /* Virtual channel */ u32 drcmr; /* Requestor of the channel */ enum pxad_chan_prio prio; /* Required priority of phy */ /* * At least one desc_sw in submitted or issued transfers on this channel * has one address such as: addr % 8 != 0. This implies the DALGN * setting on the phy. */ bool misaligned; struct dma_slave_config cfg; /* Runtime config */ /* protected by vc->lock */ struct pxad_phy *phy; struct dma_pool *desc_pool; /* Descriptors pool */ |
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dma_cookie_t bus_error; |
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wait_queue_head_t wq_state; |
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}; struct pxad_device { struct dma_device slave; int nr_chans; |
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int nr_requestors; |
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void __iomem *base; struct pxad_phy *phys; spinlock_t phy_lock; /* Phy association */ |
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#ifdef CONFIG_DEBUG_FS struct dentry *dbgfs_root; |
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struct dentry **dbgfs_chan; #endif |
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}; #define tx_to_pxad_desc(tx) \ container_of(tx, struct pxad_desc_sw, async_tx) #define to_pxad_chan(dchan) \ container_of(dchan, struct pxad_chan, vc.chan) #define to_pxad_dev(dmadev) \ container_of(dmadev, struct pxad_device, slave) #define to_pxad_sw_desc(_vd) \ container_of((_vd), struct pxad_desc_sw, vd) #define _phy_readl_relaxed(phy, _reg) \ readl_relaxed((phy)->base + _reg((phy)->idx)) #define phy_readl_relaxed(phy, _reg) \ ({ \ u32 _v; \ _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \ dev_vdbg(&phy->vchan->vc.chan.dev->device, \ "%s(): readl(%s): 0x%08x ", __func__, #_reg, \ _v); \ _v; \ }) #define phy_writel(phy, val, _reg) \ do { \ writel((val), (phy)->base + _reg((phy)->idx)); \ dev_vdbg(&phy->vchan->vc.chan.dev->device, \ "%s(): writel(0x%08x, %s) ", \ __func__, (u32)(val), #_reg); \ } while (0) #define phy_writel_relaxed(phy, val, _reg) \ do { \ writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ dev_vdbg(&phy->vchan->vc.chan.dev->device, \ "%s(): writel_relaxed(0x%08x, %s) ", \ __func__, (u32)(val), #_reg); \ } while (0) static unsigned int pxad_drcmr(unsigned int line) { if (line < 64) return 0x100 + line * 4; return 0x1000 + line * 4; } |
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static bool pxad_filter_fn(struct dma_chan *chan, void *param); |
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/* * Debug fs */ #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> #include <linux/uaccess.h> #include <linux/seq_file.h> |
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static int requester_chan_show(struct seq_file *s, void *p) |
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{ |
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struct pxad_phy *phy = s->private; int i; u32 drcmr; |
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seq_printf(s, "DMA channel %d requester : ", phy->idx); |
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for (i = 0; i < 70; i++) { drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); if ((drcmr & DRCMR_CHLNUM) == phy->idx) |
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seq_printf(s, "\tRequester %d (MAPVLD=%d) ", i, !!(drcmr & DRCMR_MAPVLD)); |
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} |
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return 0; |
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} static inline int dbg_burst_from_dcmd(u32 dcmd) { int burst = (dcmd >> 16) & 0x3; return burst ? 4 << burst : 0; } static int is_phys_valid(unsigned long addr) { return pfn_valid(__phys_to_pfn(addr)); } #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "") #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "") |
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static int descriptors_show(struct seq_file *s, void *p) |
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{ struct pxad_phy *phy = s->private; int i, max_show = 20, burst, width; u32 dcmd; unsigned long phys_desc, ddadr; struct pxad_desc_hw *desc; phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR); seq_printf(s, "DMA channel %d descriptors : ", phy->idx); seq_printf(s, "[%03d] First descriptor unknown ", 0); for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) { desc = phys_to_virt(phys_desc); dcmd = desc->dcmd; burst = dbg_burst_from_dcmd(dcmd); width = (1 << ((dcmd >> 14) & 0x3)) >> 1; seq_printf(s, "[%03d] Desc at %08lx(virt %p) ", i, phys_desc, desc); seq_printf(s, "\tDDADR = %08x ", desc->ddadr); seq_printf(s, "\tDSADR = %08x ", desc->dsadr); seq_printf(s, "\tDTADR = %08x ", desc->dtadr); seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d) ", dcmd, PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR), PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG), PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN), PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH); phys_desc = desc->ddadr; } if (i == max_show) seq_printf(s, "[%03d] Desc at %08lx ... max display reached ", i, phys_desc); else seq_printf(s, "[%03d] Desc at %08lx is %s ", i, phys_desc, phys_desc == DDADR_STOP ? "DDADR_STOP" : "invalid"); return 0; } |
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static int chan_state_show(struct seq_file *s, void *p) |
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{ struct pxad_phy *phy = s->private; u32 dcsr, dcmd; int burst, width; static const char * const str_prio[] = { "high", "normal", "low", "invalid" }; dcsr = _phy_readl_relaxed(phy, DCSR); dcmd = _phy_readl_relaxed(phy, DCMD); burst = dbg_burst_from_dcmd(dcmd); width = (1 << ((dcmd >> 14) & 0x3)) >> 1; seq_printf(s, "DMA channel %d ", phy->idx); seq_printf(s, "\tPriority : %s ", str_prio[(phy->idx & 0xf) / 4]); seq_printf(s, "\tUnaligned transfer bit: %s ", _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ? "yes" : "no"); seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s) ", dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC), PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN), PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN), PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST), PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR), PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE), PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR), PXA_DCSR_STR(BUSERR)); seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d) ", dcmd, PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR), PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG), PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN), PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH); seq_printf(s, "\tDSADR = %08x ", _phy_readl_relaxed(phy, DSADR)); seq_printf(s, "\tDTADR = %08x ", _phy_readl_relaxed(phy, DTADR)); seq_printf(s, "\tDDADR = %08x ", _phy_readl_relaxed(phy, DDADR)); return 0; } |
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static int state_show(struct seq_file *s, void *p) |
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{ struct pxad_device *pdev = s->private; /* basic device status */ seq_puts(s, "DMA engine status "); seq_printf(s, "\tChannel number: %d ", pdev->nr_chans); return 0; } |
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DEFINE_SHOW_ATTRIBUTE(state); DEFINE_SHOW_ATTRIBUTE(chan_state); DEFINE_SHOW_ATTRIBUTE(descriptors); DEFINE_SHOW_ATTRIBUTE(requester_chan); |
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static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev, int ch, struct dentry *chandir) { char chan_name[11]; |
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struct dentry *chan; |
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void *dt; scnprintf(chan_name, sizeof(chan_name), "%d", ch); chan = debugfs_create_dir(chan_name, chandir); dt = (void *)&pdev->phys[ch]; |
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debugfs_create_file("state", 0400, chan, dt, &chan_state_fops); debugfs_create_file("descriptors", 0400, chan, dt, &descriptors_fops); debugfs_create_file("requesters", 0400, chan, dt, &requester_chan_fops); |
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return chan; |
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} static void pxad_init_debugfs(struct pxad_device *pdev) { int i; struct dentry *chandir; |
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pdev->dbgfs_chan = |
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kmalloc_array(pdev->nr_chans, sizeof(struct dentry *), |
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GFP_KERNEL); if (!pdev->dbgfs_chan) |
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return; pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL); debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops); |
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chandir = debugfs_create_dir("channels", pdev->dbgfs_root); |
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for (i = 0; i < pdev->nr_chans; i++) |
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pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir); |
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} static void pxad_cleanup_debugfs(struct pxad_device *pdev) { debugfs_remove_recursive(pdev->dbgfs_root); } #else static inline void pxad_init_debugfs(struct pxad_device *pdev) {} static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {} #endif |
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static struct pxad_phy *lookup_phy(struct pxad_chan *pchan) { int prio, i; struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device); struct pxad_phy *phy, *found = NULL; unsigned long flags; /* * dma channel priorities * ch 0 - 3, 16 - 19 <--> (0) * ch 4 - 7, 20 - 23 <--> (1) * ch 8 - 11, 24 - 27 <--> (2) * ch 12 - 15, 28 - 31 <--> (3) */ spin_lock_irqsave(&pdev->phy_lock, flags); for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) { for (i = 0; i < pdev->nr_chans; i++) { if (prio != (i & 0xf) >> 2) continue; phy = &pdev->phys[i]; if (!phy->vchan) { phy->vchan = pchan; found = phy; goto out_unlock; } } } out_unlock: spin_unlock_irqrestore(&pdev->phy_lock, flags); dev_dbg(&pchan->vc.chan.dev->device, "%s(): phy=%p(%d) ", __func__, found, found ? found->idx : -1); return found; } static void pxad_free_phy(struct pxad_chan *chan) { struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); unsigned long flags; u32 reg; dev_dbg(&chan->vc.chan.dev->device, "%s(): freeing ", __func__); if (!chan->phy) return; /* clear the channel mapping in DRCMR */ |
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if (chan->drcmr <= pdev->nr_requestors) { |
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reg = pxad_drcmr(chan->drcmr); writel_relaxed(0, chan->phy->base + reg); } |
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spin_lock_irqsave(&pdev->phy_lock, flags); chan->phy->vchan = NULL; chan->phy = NULL; spin_unlock_irqrestore(&pdev->phy_lock, flags); } static bool is_chan_running(struct pxad_chan *chan) { u32 dcsr; struct pxad_phy *phy = chan->phy; if (!phy) return false; dcsr = phy_readl_relaxed(phy, DCSR); return dcsr & PXA_DCSR_RUN; } static bool is_running_chan_misaligned(struct pxad_chan *chan) { u32 dalgn; BUG_ON(!chan->phy); dalgn = phy_readl_relaxed(chan->phy, DALGN); return dalgn & (BIT(chan->phy->idx)); } static void phy_enable(struct pxad_phy *phy, bool misaligned) { |
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struct pxad_device *pdev; |
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u32 reg, dalgn; if (!phy->vchan) return; dev_dbg(&phy->vchan->vc.chan.dev->device, "%s(); phy=%p(%d) misaligned=%d ", __func__, phy, phy->idx, misaligned); |
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pdev = to_pxad_dev(phy->vchan->vc.chan.device); if (phy->vchan->drcmr <= pdev->nr_requestors) { |
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reg = pxad_drcmr(phy->vchan->drcmr); writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); } |
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dalgn = phy_readl_relaxed(phy, DALGN); if (misaligned) dalgn |= BIT(phy->idx); else dalgn &= ~BIT(phy->idx); phy_writel_relaxed(phy, dalgn, DALGN); phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR | PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR); } static void phy_disable(struct pxad_phy *phy) { u32 dcsr; if (!phy) return; dcsr = phy_readl_relaxed(phy, DCSR); dev_dbg(&phy->vchan->vc.chan.dev->device, "%s(): phy=%p(%d) ", __func__, phy, phy->idx); phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR); } static void pxad_launch_chan(struct pxad_chan *chan, struct pxad_desc_sw *desc) { dev_dbg(&chan->vc.chan.dev->device, "%s(): desc=%p ", __func__, desc); if (!chan->phy) { chan->phy = lookup_phy(chan); if (!chan->phy) { dev_dbg(&chan->vc.chan.dev->device, "%s(): no free dma channel ", __func__); return; } } |
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chan->bus_error = 0; |
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/* * Program the descriptor's address into the DMA controller, * then start the DMA transaction */ phy_writel(chan->phy, desc->first, DDADR); phy_enable(chan->phy, chan->misaligned); |
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wake_up(&chan->wq_state); |
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} static void set_updater_desc(struct pxad_desc_sw *sw_desc, unsigned long flags) { struct pxad_desc_hw *updater = sw_desc->hw_desc[sw_desc->nb_desc - 1]; dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr; updater->ddadr = DDADR_STOP; updater->dsadr = dma; updater->dtadr = dma + 8; updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 | (PXA_DCMD_LENGTH & sizeof(u32)); if (flags & DMA_PREP_INTERRUPT) updater->dcmd |= PXA_DCMD_ENDIRQEN; |
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if (sw_desc->cyclic) sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first; |
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} static bool is_desc_completed(struct virt_dma_desc *vd) { struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); struct pxad_desc_hw *updater = sw_desc->hw_desc[sw_desc->nb_desc - 1]; return updater->dtadr != (updater->dsadr + 8); } static void pxad_desc_chain(struct virt_dma_desc *vd1, struct virt_dma_desc *vd2) { struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1); struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2); dma_addr_t dma_to_chain; dma_to_chain = desc2->first; desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain; } static bool pxad_try_hotchain(struct virt_dma_chan *vc, struct virt_dma_desc *vd) { struct virt_dma_desc *vd_last_issued = NULL; struct pxad_chan *chan = to_pxad_chan(&vc->chan); /* * Attempt to hot chain the tx if the phy is still running. This is * considered successful only if either the channel is still running * after the chaining, or if the chained transfer is completed after * having been hot chained. * A change of alignment is not allowed, and forbids hotchaining. */ if (is_chan_running(chan)) { BUG_ON(list_empty(&vc->desc_issued)); if (!is_running_chan_misaligned(chan) && to_pxad_sw_desc(vd)->misaligned) return false; vd_last_issued = list_entry(vc->desc_issued.prev, struct virt_dma_desc, node); pxad_desc_chain(vd_last_issued, vd); |
76507fdfc dmaengine: pxa_dm... |
597 |
if (is_chan_running(chan) || is_desc_completed(vd)) |
a57e16cf0 dmaengine: pxa: a... |
598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 |
return true; } return false; } static unsigned int clear_chan_irq(struct pxad_phy *phy) { u32 dcsr; u32 dint = readl(phy->base + DINT); if (!(dint & BIT(phy->idx))) return PXA_DCSR_RUN; /* clear irq */ dcsr = phy_readl_relaxed(phy, DCSR); phy_writel(phy, dcsr, DCSR); if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) dev_warn(&phy->vchan->vc.chan.dev->device, "%s(chan=%p): PXA_DCSR_BUSERR ", __func__, &phy->vchan); return dcsr & ~PXA_DCSR_RUN; } static irqreturn_t pxad_chan_handler(int irq, void *dev_id) { struct pxad_phy *phy = dev_id; struct pxad_chan *chan = phy->vchan; struct virt_dma_desc *vd, *tmp; unsigned int dcsr; unsigned long flags; |
06777c4ec dmaengine: pxa_dm... |
631 |
bool vd_completed; |
e093bf60c dmaengine: pxa: h... |
632 |
dma_cookie_t last_started = 0; |
a57e16cf0 dmaengine: pxa: a... |
633 634 635 636 637 638 639 640 641 |
BUG_ON(!chan); dcsr = clear_chan_irq(phy); if (dcsr & PXA_DCSR_RUN) return IRQ_NONE; spin_lock_irqsave(&chan->vc.lock, flags); list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { |
06777c4ec dmaengine: pxa_dm... |
642 |
vd_completed = is_desc_completed(vd); |
a57e16cf0 dmaengine: pxa: a... |
643 |
dev_dbg(&chan->vc.chan.dev->device, |
06777c4ec dmaengine: pxa_dm... |
644 645 646 647 |
"%s(): checking txd %p[%x]: completed=%d dcsr=0x%x ", __func__, vd, vd->tx.cookie, vd_completed, dcsr); |
e093bf60c dmaengine: pxa: h... |
648 |
last_started = vd->tx.cookie; |
f16921275 dmaengine: pxa_dm... |
649 650 651 652 |
if (to_pxad_sw_desc(vd)->cyclic) { vchan_cyclic_callback(vd); break; } |
06777c4ec dmaengine: pxa_dm... |
653 |
if (vd_completed) { |
a57e16cf0 dmaengine: pxa: a... |
654 655 656 657 658 659 |
list_del(&vd->node); vchan_cookie_complete(vd); } else { break; } } |
e093bf60c dmaengine: pxa: h... |
660 661 662 663 664 665 |
if (dcsr & PXA_DCSR_BUSERR) { chan->bus_error = last_started; phy_disable(phy); } if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { |
a57e16cf0 dmaengine: pxa: a... |
666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 |
dev_dbg(&chan->vc.chan.dev->device, "%s(): channel stopped, submitted_empty=%d issued_empty=%d", __func__, list_empty(&chan->vc.desc_submitted), list_empty(&chan->vc.desc_issued)); phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR); if (list_empty(&chan->vc.desc_issued)) { chan->misaligned = !list_empty(&chan->vc.desc_submitted); } else { vd = list_first_entry(&chan->vc.desc_issued, struct virt_dma_desc, node); pxad_launch_chan(chan, to_pxad_sw_desc(vd)); } } spin_unlock_irqrestore(&chan->vc.lock, flags); |
7d6046632 dmaengine: pxa_dm... |
683 |
wake_up(&chan->wq_state); |
a57e16cf0 dmaengine: pxa: a... |
684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 |
return IRQ_HANDLED; } static irqreturn_t pxad_int_handler(int irq, void *dev_id) { struct pxad_device *pdev = dev_id; struct pxad_phy *phy; u32 dint = readl(pdev->base + DINT); int i, ret = IRQ_NONE; while (dint) { i = __ffs(dint); dint &= (dint - 1); phy = &pdev->phys[i]; if (pxad_chan_handler(irq, phy) == IRQ_HANDLED) ret = IRQ_HANDLED; } return ret; } static int pxad_alloc_chan_resources(struct dma_chan *dchan) { struct pxad_chan *chan = to_pxad_chan(dchan); struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); if (chan->desc_pool) return 1; chan->desc_pool = dma_pool_create(dma_chan_name(dchan), pdev->slave.dev, sizeof(struct pxad_desc_hw), __alignof__(struct pxad_desc_hw), 0); if (!chan->desc_pool) { dev_err(&chan->vc.chan.dev->device, "%s(): unable to allocate descriptor pool ", __func__); return -ENOMEM; } return 1; } static void pxad_free_chan_resources(struct dma_chan *dchan) { struct pxad_chan *chan = to_pxad_chan(dchan); vchan_free_chan_resources(&chan->vc); dma_pool_destroy(chan->desc_pool); chan->desc_pool = NULL; |
88a0513cf dmaengine: pxa: a... |
737 738 |
chan->drcmr = U32_MAX; chan->prio = PXAD_PRIO_LOWEST; |
a57e16cf0 dmaengine: pxa: a... |
739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 |
} static void pxad_free_desc(struct virt_dma_desc *vd) { int i; dma_addr_t dma; struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); BUG_ON(sw_desc->nb_desc == 0); for (i = sw_desc->nb_desc - 1; i >= 0; i--) { if (i > 0) dma = sw_desc->hw_desc[i - 1]->ddadr; else dma = sw_desc->first; dma_pool_free(sw_desc->desc_pool, sw_desc->hw_desc[i], dma); } sw_desc->nb_desc = 0; kfree(sw_desc); } static struct pxad_desc_sw * pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc) { struct pxad_desc_sw *sw_desc; dma_addr_t dma; int i; sw_desc = kzalloc(sizeof(*sw_desc) + nb_hw_desc * sizeof(struct pxad_desc_hw *), GFP_NOWAIT); if (!sw_desc) return NULL; sw_desc->desc_pool = chan->desc_pool; for (i = 0; i < nb_hw_desc; i++) { sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool, GFP_NOWAIT, &dma); if (!sw_desc->hw_desc[i]) { dev_err(&chan->vc.chan.dev->device, "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p ", __func__, i, sw_desc->desc_pool); goto err; } if (i == 0) sw_desc->first = dma; else sw_desc->hw_desc[i - 1]->ddadr = dma; sw_desc->nb_desc++; } return sw_desc; err: pxad_free_desc(&sw_desc->vd); return NULL; } static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx) { struct virt_dma_chan *vc = to_virt_chan(tx->chan); struct pxad_chan *chan = to_pxad_chan(&vc->chan); struct virt_dma_desc *vd_chained = NULL, *vd = container_of(tx, struct virt_dma_desc, tx); dma_cookie_t cookie; unsigned long flags; set_updater_desc(to_pxad_sw_desc(vd), tx->flags); spin_lock_irqsave(&vc->lock, flags); cookie = dma_cookie_assign(tx); if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { list_move_tail(&vd->node, &vc->desc_issued); dev_dbg(&chan->vc.chan.dev->device, "%s(): txd %p[%x]: submitted (hot linked) ", __func__, vd, cookie); goto out; } /* * Fallback to placing the tx in the submitted queue */ if (!list_empty(&vc->desc_submitted)) { vd_chained = list_entry(vc->desc_submitted.prev, struct virt_dma_desc, node); /* * Only chain the descriptors if no new misalignment is * introduced. If a new misalignment is chained, let the channel * stop, and be relaunched in misalign mode from the irq * handler. */ if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) pxad_desc_chain(vd_chained, vd); else vd_chained = NULL; } dev_dbg(&chan->vc.chan.dev->device, "%s(): txd %p[%x]: submitted (%s linked) ", __func__, vd, cookie, vd_chained ? "cold" : "not"); list_move_tail(&vd->node, &vc->desc_submitted); chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; out: spin_unlock_irqrestore(&vc->lock, flags); return cookie; } static void pxad_issue_pending(struct dma_chan *dchan) { struct pxad_chan *chan = to_pxad_chan(dchan); struct virt_dma_desc *vd_first; unsigned long flags; spin_lock_irqsave(&chan->vc.lock, flags); if (list_empty(&chan->vc.desc_submitted)) goto out; vd_first = list_first_entry(&chan->vc.desc_submitted, struct virt_dma_desc, node); dev_dbg(&chan->vc.chan.dev->device, "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); vchan_issue_pending(&chan->vc); if (!pxad_try_hotchain(&chan->vc, vd_first)) pxad_launch_chan(chan, to_pxad_sw_desc(vd_first)); out: spin_unlock_irqrestore(&chan->vc.lock, flags); } static inline struct dma_async_tx_descriptor * pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd, unsigned long tx_flags) { struct dma_async_tx_descriptor *tx; struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc); |
aebf5a67d dmaengine: pxa_dm... |
878 |
INIT_LIST_HEAD(&vd->node); |
a57e16cf0 dmaengine: pxa: a... |
879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 |
tx = vchan_tx_prep(vc, vd, tx_flags); tx->tx_submit = pxad_tx_submit; dev_dbg(&chan->vc.chan.dev->device, "%s(): vc=%p txd=%p[%x] flags=0x%lx ", __func__, vc, vd, vd->tx.cookie, tx_flags); return tx; } static void pxad_get_config(struct pxad_chan *chan, enum dma_transfer_direction dir, u32 *dcmd, u32 *dev_src, u32 *dev_dst) { u32 maxburst = 0, dev_addr = 0; enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; |
6bab1c6af dmaengine: pxa_dm... |
896 |
struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); |
a57e16cf0 dmaengine: pxa: a... |
897 898 |
*dcmd = 0; |
0e95fb9ce dmaengine: pxa_dm... |
899 |
if (dir == DMA_DEV_TO_MEM) { |
a57e16cf0 dmaengine: pxa: a... |
900 901 902 903 |
maxburst = chan->cfg.src_maxburst; width = chan->cfg.src_addr_width; dev_addr = chan->cfg.src_addr; *dev_src = dev_addr; |
e87ffbdf0 dmaengine: pxa_dm... |
904 |
*dcmd |= PXA_DCMD_INCTRGADDR; |
6bab1c6af dmaengine: pxa_dm... |
905 |
if (chan->drcmr <= pdev->nr_requestors) |
e87ffbdf0 dmaengine: pxa_dm... |
906 |
*dcmd |= PXA_DCMD_FLOWSRC; |
a57e16cf0 dmaengine: pxa: a... |
907 |
} |
0e95fb9ce dmaengine: pxa_dm... |
908 |
if (dir == DMA_MEM_TO_DEV) { |
a57e16cf0 dmaengine: pxa: a... |
909 910 911 912 |
maxburst = chan->cfg.dst_maxburst; width = chan->cfg.dst_addr_width; dev_addr = chan->cfg.dst_addr; *dev_dst = dev_addr; |
e87ffbdf0 dmaengine: pxa_dm... |
913 |
*dcmd |= PXA_DCMD_INCSRCADDR; |
6bab1c6af dmaengine: pxa_dm... |
914 |
if (chan->drcmr <= pdev->nr_requestors) |
e87ffbdf0 dmaengine: pxa_dm... |
915 |
*dcmd |= PXA_DCMD_FLOWTRG; |
a57e16cf0 dmaengine: pxa: a... |
916 |
} |
0e95fb9ce dmaengine: pxa_dm... |
917 |
if (dir == DMA_MEM_TO_MEM) |
a57e16cf0 dmaengine: pxa: a... |
918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 |
*dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR | PXA_DCMD_INCSRCADDR; dev_dbg(&chan->vc.chan.dev->device, "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d ", __func__, dev_addr, maxburst, width, dir); if (width == DMA_SLAVE_BUSWIDTH_1_BYTE) *dcmd |= PXA_DCMD_WIDTH1; else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES) *dcmd |= PXA_DCMD_WIDTH2; else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES) *dcmd |= PXA_DCMD_WIDTH4; if (maxburst == 8) *dcmd |= PXA_DCMD_BURST8; else if (maxburst == 16) *dcmd |= PXA_DCMD_BURST16; else if (maxburst == 32) *dcmd |= PXA_DCMD_BURST32; /* FIXME: drivers should be ported over to use the filter * function. Once that's done, the following two lines can * be removed. */ if (chan->cfg.slave_id) chan->drcmr = chan->cfg.slave_id; } static struct dma_async_tx_descriptor * pxad_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, size_t len, unsigned long flags) { struct pxad_chan *chan = to_pxad_chan(dchan); struct pxad_desc_sw *sw_desc; struct pxad_desc_hw *hw_desc; u32 dcmd; unsigned int i, nb_desc = 0; size_t copy; if (!dchan || !len) return NULL; dev_dbg(&chan->vc.chan.dev->device, "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx ", __func__, (unsigned long)dma_dst, (unsigned long)dma_src, len, flags); pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL); nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES); sw_desc = pxad_alloc_desc(chan, nb_desc + 1); if (!sw_desc) return NULL; sw_desc->len = len; if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) || !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT)) sw_desc->misaligned = true; i = 0; do { hw_desc = sw_desc->hw_desc[i++]; copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES); hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy); hw_desc->dsadr = dma_src; hw_desc->dtadr = dma_dst; len -= copy; dma_src += copy; dma_dst += copy; } while (len); set_updater_desc(sw_desc, flags); return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); } static struct dma_async_tx_descriptor * pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, enum dma_transfer_direction dir, unsigned long flags, void *context) { struct pxad_chan *chan = to_pxad_chan(dchan); struct pxad_desc_sw *sw_desc; size_t len, avail; struct scatterlist *sg; dma_addr_t dma; u32 dcmd, dsadr = 0, dtadr = 0; unsigned int nb_desc = 0, i, j = 0; if ((sgl == NULL) || (sg_len == 0)) return NULL; pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); dev_dbg(&chan->vc.chan.dev->device, "%s(): dir=%d flags=%lx ", __func__, dir, flags); for_each_sg(sgl, sg, sg_len, i) nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES); sw_desc = pxad_alloc_desc(chan, nb_desc + 1); if (!sw_desc) return NULL; for_each_sg(sgl, sg, sg_len, i) { dma = sg_dma_address(sg); avail = sg_dma_len(sg); sw_desc->len += avail; do { len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES); if (dma & 0x7) sw_desc->misaligned = true; sw_desc->hw_desc[j]->dcmd = dcmd | (PXA_DCMD_LENGTH & len); sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma; sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma; dma += len; avail -= len; } while (avail); } set_updater_desc(sw_desc, flags); return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); } static struct dma_async_tx_descriptor * pxad_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t buf_addr, size_t len, size_t period_len, enum dma_transfer_direction dir, unsigned long flags) { struct pxad_chan *chan = to_pxad_chan(dchan); struct pxad_desc_sw *sw_desc; struct pxad_desc_hw **phw_desc; dma_addr_t dma; u32 dcmd, dsadr = 0, dtadr = 0; unsigned int nb_desc = 0; if (!dchan || !len || !period_len) return NULL; if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) { dev_err(&chan->vc.chan.dev->device, "Unsupported direction for cyclic DMA "); return NULL; } /* the buffer length must be a multiple of period_len */ if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES || !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT)) return NULL; pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); |
f16921275 dmaengine: pxa_dm... |
1073 |
dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len); |
a57e16cf0 dmaengine: pxa: a... |
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 |
dev_dbg(&chan->vc.chan.dev->device, "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx ", __func__, (unsigned long)buf_addr, len, period_len, dir, flags); nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES); nb_desc *= DIV_ROUND_UP(len, period_len); sw_desc = pxad_alloc_desc(chan, nb_desc + 1); if (!sw_desc) return NULL; sw_desc->cyclic = true; sw_desc->len = len; phw_desc = sw_desc->hw_desc; dma = buf_addr; do { phw_desc[0]->dsadr = dsadr ? dsadr : dma; phw_desc[0]->dtadr = dtadr ? dtadr : dma; phw_desc[0]->dcmd = dcmd; phw_desc++; dma += period_len; len -= period_len; } while (len); set_updater_desc(sw_desc, flags); return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); } static int pxad_config(struct dma_chan *dchan, struct dma_slave_config *cfg) { struct pxad_chan *chan = to_pxad_chan(dchan); if (!dchan) return -EINVAL; chan->cfg = *cfg; return 0; } static int pxad_terminate_all(struct dma_chan *dchan) { struct pxad_chan *chan = to_pxad_chan(dchan); struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); struct virt_dma_desc *vd = NULL; unsigned long flags; struct pxad_phy *phy; LIST_HEAD(head); dev_dbg(&chan->vc.chan.dev->device, "%s(): vchan %p: terminate all ", __func__, &chan->vc); spin_lock_irqsave(&chan->vc.lock, flags); vchan_get_all_descriptors(&chan->vc, &head); list_for_each_entry(vd, &head, node) { dev_dbg(&chan->vc.chan.dev->device, "%s(): cancelling txd %p[%x] (completed=%d)", __func__, vd, vd->tx.cookie, is_desc_completed(vd)); } phy = chan->phy; if (phy) { phy_disable(chan->phy); pxad_free_phy(chan); chan->phy = NULL; spin_lock(&pdev->phy_lock); phy->vchan = NULL; spin_unlock(&pdev->phy_lock); } spin_unlock_irqrestore(&chan->vc.lock, flags); vchan_dma_desc_free_list(&chan->vc, &head); return 0; } static unsigned int pxad_residue(struct pxad_chan *chan, dma_cookie_t cookie) { struct virt_dma_desc *vd = NULL; struct pxad_desc_sw *sw_desc = NULL; struct pxad_desc_hw *hw_desc = NULL; u32 curr, start, len, end, residue = 0; unsigned long flags; bool passed = false; int i; /* * If the channel does not have a phy pointer anymore, it has already * been completed. Therefore, its residue is 0. */ if (!chan->phy) return 0; spin_lock_irqsave(&chan->vc.lock, flags); vd = vchan_find_desc(&chan->vc, cookie); if (!vd) goto out; sw_desc = to_pxad_sw_desc(vd); if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) curr = phy_readl_relaxed(chan->phy, DSADR); else curr = phy_readl_relaxed(chan->phy, DTADR); |
7b09a1bba dmaengine: pxa_dm... |
1180 1181 1182 1183 1184 1185 1186 1187 1188 |
/* * curr has to be actually read before checking descriptor * completion, so that a curr inside a status updater * descriptor implies the following test returns true, and * preventing reordering of curr load and the test. */ rmb(); if (is_desc_completed(vd)) goto out; |
a57e16cf0 dmaengine: pxa: a... |
1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 |
for (i = 0; i < sw_desc->nb_desc - 1; i++) { hw_desc = sw_desc->hw_desc[i]; if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) start = hw_desc->dsadr; else start = hw_desc->dtadr; len = hw_desc->dcmd & PXA_DCMD_LENGTH; end = start + len; /* * 'passed' will be latched once we found the descriptor * which lies inside the boundaries of the curr * pointer. All descriptors that occur in the list * _after_ we found that partially handled descriptor * are still to be processed and are hence added to the * residual bytes counter. */ if (passed) { residue += len; } else if (curr >= start && curr <= end) { residue += end - curr; passed = true; } } if (!passed) residue = sw_desc->len; out: spin_unlock_irqrestore(&chan->vc.lock, flags); dev_dbg(&chan->vc.chan.dev->device, "%s(): txd %p[%x] sw_desc=%p: %d ", __func__, vd, cookie, sw_desc, residue); return residue; } static enum dma_status pxad_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct pxad_chan *chan = to_pxad_chan(dchan); enum dma_status ret; |
e093bf60c dmaengine: pxa: h... |
1232 1233 |
if (cookie == chan->bus_error) return DMA_ERROR; |
a57e16cf0 dmaengine: pxa: a... |
1234 1235 1236 1237 1238 1239 |
ret = dma_cookie_status(dchan, cookie, txstate); if (likely(txstate && (ret != DMA_ERROR))) dma_set_residue(txstate, pxad_residue(chan, cookie)); return ret; } |
7d6046632 dmaengine: pxa_dm... |
1240 1241 1242 1243 1244 1245 1246 |
static void pxad_synchronize(struct dma_chan *dchan) { struct pxad_chan *chan = to_pxad_chan(dchan); wait_event(chan->wq_state, !is_chan_running(chan)); vchan_synchronize(&chan->vc); } |
a57e16cf0 dmaengine: pxa: a... |
1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 |
static void pxad_free_channels(struct dma_device *dmadev) { struct pxad_chan *c, *cn; list_for_each_entry_safe(c, cn, &dmadev->channels, vc.chan.device_node) { list_del(&c->vc.chan.device_node); tasklet_kill(&c->vc.task); } } static int pxad_remove(struct platform_device *op) { struct pxad_device *pdev = platform_get_drvdata(op); |
c01d1b515 dmaengine: pxa_dm... |
1261 |
pxad_cleanup_debugfs(pdev); |
a57e16cf0 dmaengine: pxa: a... |
1262 |
pxad_free_channels(&pdev->slave); |
a57e16cf0 dmaengine: pxa: a... |
1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 |
return 0; } static int pxad_init_phys(struct platform_device *op, struct pxad_device *pdev, unsigned int nb_phy_chans) { int irq0, irq, nr_irq = 0, i, ret; struct pxad_phy *phy; irq0 = platform_get_irq(op, 0); if (irq0 < 0) return irq0; pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans, sizeof(pdev->phys[0]), GFP_KERNEL); if (!pdev->phys) return -ENOMEM; for (i = 0; i < nb_phy_chans; i++) if (platform_get_irq(op, i) > 0) nr_irq++; for (i = 0; i < nb_phy_chans; i++) { phy = &pdev->phys[i]; phy->base = pdev->base; phy->idx = i; irq = platform_get_irq(op, i); if ((nr_irq > 1) && (irq > 0)) ret = devm_request_irq(&op->dev, irq, pxad_chan_handler, IRQF_SHARED, "pxa-dma", phy); if ((nr_irq == 1) && (i == 0)) ret = devm_request_irq(&op->dev, irq0, pxad_int_handler, IRQF_SHARED, "pxa-dma", pdev); if (ret) { dev_err(pdev->slave.dev, "%s(): can't request irq %d:%d ", __func__, irq, ret); return ret; } } return 0; } |
4e0def887 dmaengine: pxa_dm... |
1310 |
static const struct of_device_id pxad_dt_ids[] = { |
a57e16cf0 dmaengine: pxa: a... |
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 |
{ .compatible = "marvell,pdma-1.0", }, {} }; MODULE_DEVICE_TABLE(of, pxad_dt_ids); static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { struct pxad_device *d = ofdma->of_dma_data; struct dma_chan *chan; chan = dma_get_any_slave_channel(&d->slave); if (!chan) return NULL; to_pxad_chan(chan)->drcmr = dma_spec->args[0]; to_pxad_chan(chan)->prio = dma_spec->args[1]; return chan; } static int pxad_init_dmadev(struct platform_device *op, struct pxad_device *pdev, |
6bab1c6af dmaengine: pxa_dm... |
1334 1335 |
unsigned int nr_phy_chans, unsigned int nr_requestors) |
a57e16cf0 dmaengine: pxa: a... |
1336 1337 1338 1339 1340 1341 |
{ int ret; unsigned int i; struct pxad_chan *c; pdev->nr_chans = nr_phy_chans; |
6bab1c6af dmaengine: pxa_dm... |
1342 |
pdev->nr_requestors = nr_requestors; |
a57e16cf0 dmaengine: pxa: a... |
1343 1344 1345 1346 1347 1348 |
INIT_LIST_HEAD(&pdev->slave.channels); pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources; pdev->slave.device_free_chan_resources = pxad_free_chan_resources; pdev->slave.device_tx_status = pxad_tx_status; pdev->slave.device_issue_pending = pxad_issue_pending; pdev->slave.device_config = pxad_config; |
7d6046632 dmaengine: pxa_dm... |
1349 |
pdev->slave.device_synchronize = pxad_synchronize; |
a57e16cf0 dmaengine: pxa: a... |
1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 |
pdev->slave.device_terminate_all = pxad_terminate_all; if (op->dev.coherent_dma_mask) dma_set_mask(&op->dev, op->dev.coherent_dma_mask); else dma_set_mask(&op->dev, DMA_BIT_MASK(32)); ret = pxad_init_phys(op, pdev, nr_phy_chans); if (ret) return ret; for (i = 0; i < nr_phy_chans; i++) { c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL); if (!c) return -ENOMEM; |
88a0513cf dmaengine: pxa: a... |
1365 1366 1367 |
c->drcmr = U32_MAX; c->prio = PXAD_PRIO_LOWEST; |
a57e16cf0 dmaengine: pxa: a... |
1368 1369 |
c->vc.desc_free = pxad_free_desc; vchan_init(&c->vc, &pdev->slave); |
7d6046632 dmaengine: pxa_dm... |
1370 |
init_waitqueue_head(&c->wq_state); |
a57e16cf0 dmaengine: pxa: a... |
1371 |
} |
d72c5f985 dmaengine: pxa_dm... |
1372 |
return dmaenginem_async_device_register(&pdev->slave); |
a57e16cf0 dmaengine: pxa: a... |
1373 1374 1375 1376 1377 1378 |
} static int pxad_probe(struct platform_device *op) { struct pxad_device *pdev; const struct of_device_id *of_id; |
420c0117d dmaengine: pxa: u... |
1379 |
const struct dma_slave_map *slave_map = NULL; |
a57e16cf0 dmaengine: pxa: a... |
1380 1381 |
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); struct resource *iores; |
420c0117d dmaengine: pxa: u... |
1382 |
int ret, dma_channels = 0, nb_requestors = 0, slave_map_cnt = 0; |
a57e16cf0 dmaengine: pxa: a... |
1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 |
const enum dma_slave_buswidth widths = DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES; pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); if (!pdev) return -ENOMEM; spin_lock_init(&pdev->phy_lock); iores = platform_get_resource(op, IORESOURCE_MEM, 0); pdev->base = devm_ioremap_resource(&op->dev, iores); if (IS_ERR(pdev->base)) return PTR_ERR(pdev->base); of_id = of_match_device(pxad_dt_ids, &op->dev); |
6bab1c6af dmaengine: pxa_dm... |
1399 |
if (of_id) { |
a57e16cf0 dmaengine: pxa: a... |
1400 1401 |
of_property_read_u32(op->dev.of_node, "#dma-channels", &dma_channels); |
6bab1c6af dmaengine: pxa_dm... |
1402 1403 1404 1405 1406 1407 1408 |
ret = of_property_read_u32(op->dev.of_node, "#dma-requests", &nb_requestors); if (ret) { dev_warn(pdev->slave.dev, "#dma-requests set to default 32 as missing in OF: %d", ret); nb_requestors = 32; |
a436ff1e9 dmaengine: pxa: f... |
1409 |
} |
6bab1c6af dmaengine: pxa_dm... |
1410 |
} else if (pdata && pdata->dma_channels) { |
a57e16cf0 dmaengine: pxa: a... |
1411 |
dma_channels = pdata->dma_channels; |
6bab1c6af dmaengine: pxa_dm... |
1412 |
nb_requestors = pdata->nb_requestors; |
420c0117d dmaengine: pxa: u... |
1413 1414 |
slave_map = pdata->slave_map; slave_map_cnt = pdata->slave_map_cnt; |
6bab1c6af dmaengine: pxa_dm... |
1415 |
} else { |
a57e16cf0 dmaengine: pxa: a... |
1416 |
dma_channels = 32; /* default 32 channel */ |
6bab1c6af dmaengine: pxa_dm... |
1417 |
} |
a57e16cf0 dmaengine: pxa: a... |
1418 1419 1420 1421 1422 1423 1424 1425 |
dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask); dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask); dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask); dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask); pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy; pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg; pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic; |
420c0117d dmaengine: pxa: u... |
1426 1427 1428 |
pdev->slave.filter.map = slave_map; pdev->slave.filter.mapcnt = slave_map_cnt; pdev->slave.filter.fn = pxad_filter_fn; |
a57e16cf0 dmaengine: pxa: a... |
1429 1430 1431 1432 1433 1434 |
pdev->slave.copy_align = PDMA_ALIGNMENT; pdev->slave.src_addr_widths = widths; pdev->slave.dst_addr_widths = widths; pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
d3651b8e5 dmaengine: pxa_dm... |
1435 |
pdev->slave.descriptor_reuse = true; |
a57e16cf0 dmaengine: pxa: a... |
1436 1437 |
pdev->slave.dev = &op->dev; |
6bab1c6af dmaengine: pxa_dm... |
1438 |
ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors); |
a57e16cf0 dmaengine: pxa: a... |
1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 |
if (ret) { dev_err(pdev->slave.dev, "unable to register "); return ret; } if (op->dev.of_node) { /* Device-tree DMA controller registration */ ret = of_dma_controller_register(op->dev.of_node, pxad_dma_xlate, pdev); if (ret < 0) { dev_err(pdev->slave.dev, "of_dma_controller_register failed "); return ret; } } platform_set_drvdata(op, pdev); |
c01d1b515 dmaengine: pxa_dm... |
1458 |
pxad_init_debugfs(pdev); |
6bab1c6af dmaengine: pxa_dm... |
1459 1460 1461 |
dev_info(pdev->slave.dev, "initialized %d channels on %d requestors ", dma_channels, nb_requestors); |
a57e16cf0 dmaengine: pxa: a... |
1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 |
return 0; } static const struct platform_device_id pxad_id_table[] = { { "pxa-dma", }, { }, }; static struct platform_driver pxad_driver = { .driver = { .name = "pxa-dma", .of_match_table = pxad_dt_ids, }, .id_table = pxad_id_table, .probe = pxad_probe, .remove = pxad_remove, }; |
c2a70a319 dmaengine: pxa: m... |
1479 |
static bool pxad_filter_fn(struct dma_chan *chan, void *param) |
a57e16cf0 dmaengine: pxa: a... |
1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 |
{ struct pxad_chan *c = to_pxad_chan(chan); struct pxad_param *p = param; if (chan->device->dev->driver != &pxad_driver.driver) return false; c->drcmr = p->drcmr; c->prio = p->prio; return true; } |
a57e16cf0 dmaengine: pxa: a... |
1492 1493 1494 1495 1496 1497 |
module_platform_driver(pxad_driver); MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver"); MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); MODULE_LICENSE("GPL v2"); |