/*
   * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
   *
   * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
   *
   * Contributors (thanks, all!)
   *
   *	David Eger:
   *	Overhaul for Linux 2.6
   *
   *      Jeff Rugen:
   *      Major contributions;  Motorola PowerStack (PPC and PCI) support,
   *      GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
   *
   *	Geert Uytterhoeven:
   *	Excellent code review.
   *
   *	Lars Hecking:
   *	Amiga updates and testing.
   *
   * Original cirrusfb author:  Frank Neumann
   *
   * Based on retz3fb.c and cirrusfb.c:
   *      Copyright (C) 1997 Jes Sorensen
   *      Copyright (C) 1996 Frank Neumann
   *
   ***************************************************************
   *
   * Format this code with GNU indent '-kr -i8 -pcs' options.
   *
   * This file is subject to the terms and conditions of the GNU General Public
   * License.  See the file COPYING in the main directory of this archive
   * for more details.
   *
   */

  #include <linux/module.h>
  #include <linux/kernel.h>
  #include <linux/errno.h>
  #include <linux/string.h>
  #include <linux/mm.h>

  #include <linux/delay.h>
  #include <linux/fb.h>
  #include <linux/init.h>

  #include <asm/pgtable.h>
  
  #ifdef CONFIG_ZORRO
  #include <linux/zorro.h>
  #endif
  #ifdef CONFIG_PCI
  #include <linux/pci.h>
  #endif
  #ifdef CONFIG_AMIGA
  #include <asm/amigahw.h>
  #endif
  #ifdef CONFIG_PPC_PREP

  #include <asm/machdep.h>

  #define isPReP machine_is(prep)

  #else
  #define isPReP 0
  #endif

  #include <video/vga.h>
  #include <video/cirrus.h>

  /*****************************************************************
   *
   * debugging and utility macros
   *
   */

  /* disable runtime assertions? */
  /* #define CIRRUSFB_NDEBUG */

  /* debugging assertions */
  #ifndef CIRRUSFB_NDEBUG
  #define assert(expr) \

  	if (!(expr)) { \
  		printk("Assertion failed! %s,%s,%s,line=%d
  ", \

  		#expr, __FILE__, __func__, __LINE__); \

  	}

  #else
  #define assert(expr)
  #endif

  #define MB_ (1024 * 1024)

  /*****************************************************************
   *
   * chipset information
   *
   */
  
  /* board types */

  enum cirrus_board {

  	BT_NONE = 0,

  	BT_SD64,	/* GD5434 */
  	BT_PICCOLO,	/* GD5426 */
  	BT_PICASSO,	/* GD5426 or GD5428 */
  	BT_SPECTRUM,	/* GD5426 or GD5428 */

  	BT_PICASSO4,	/* GD5446 */
  	BT_ALPINE,	/* GD543x/4x */
  	BT_GD5480,

  	BT_LAGUNA,	/* GD5462/64 */
  	BT_LAGUNAB,	/* GD5465 */

  };

  /*
   * per-board-type information, used for enumerating and abstracting
   * chip-specific information

   * NOTE: MUST be in the same order as enum cirrus_board in order to

   * use direct indexing on this array
   * NOTE: '__initdata' cannot be used as some of this info
   * is required at runtime.  Maybe separate into an init-only and
   * a run-time table?
   */
  static const struct cirrusfb_board_info_rec {
  	char *name;		/* ASCII name of chipset */
  	long maxclock[5];		/* maximum video clock */
  	/* for  1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */

  	bool init_sr07 : 1; /* init SR07 during init_vgachip() */
  	bool init_sr1f : 1; /* write SR1F during init_vgachip() */

  	/* construct bit 19 of screen start address */
  	bool scrn_start_bit19 : 1;

  
  	/* initial SR07 value, then for each mode */
  	unsigned char sr07;
  	unsigned char sr07_1bpp;
  	unsigned char sr07_1bpp_mux;
  	unsigned char sr07_8bpp;
  	unsigned char sr07_8bpp_mux;
  
  	unsigned char sr1f;	/* SR1F VGA initial register value */
  } cirrusfb_board_info[] = {
  	[BT_SD64] = {
  		.name			= "CL SD64",
  		.maxclock		= {
  			/* guess */
  			/* the SD64/P4 have a higher max. videoclock */

  			135100, 135100, 85500, 85500, 0

  		},

  		.init_sr07		= true,
  		.init_sr1f		= true,
  		.scrn_start_bit19	= true,

  		.sr07			= 0xF0,
  		.sr07_1bpp		= 0xF0,

  		.sr07_1bpp_mux		= 0xF6,

  		.sr07_8bpp		= 0xF1,

  		.sr07_8bpp_mux		= 0xF7,

  		.sr1f			= 0x1E

  	},
  	[BT_PICCOLO] = {
  		.name			= "CL Piccolo",
  		.maxclock		= {
  			/* guess */
  			90000, 90000, 90000, 90000, 90000
  		},

  		.init_sr07		= true,
  		.init_sr1f		= true,
  		.scrn_start_bit19	= false,

  		.sr07			= 0x80,
  		.sr07_1bpp		= 0x80,
  		.sr07_8bpp		= 0x81,
  		.sr1f			= 0x22
  	},
  	[BT_PICASSO] = {
  		.name			= "CL Picasso",
  		.maxclock		= {
  			/* guess */
  			90000, 90000, 90000, 90000, 90000
  		},

  		.init_sr07		= true,
  		.init_sr1f		= true,
  		.scrn_start_bit19	= false,

  		.sr07			= 0x20,
  		.sr07_1bpp		= 0x20,
  		.sr07_8bpp		= 0x21,
  		.sr1f			= 0x22
  	},
  	[BT_SPECTRUM] = {
  		.name			= "CL Spectrum",
  		.maxclock		= {
  			/* guess */
  			90000, 90000, 90000, 90000, 90000
  		},

  		.init_sr07		= true,
  		.init_sr1f		= true,
  		.scrn_start_bit19	= false,

  		.sr07			= 0x80,
  		.sr07_1bpp		= 0x80,
  		.sr07_8bpp		= 0x81,
  		.sr1f			= 0x22
  	},
  	[BT_PICASSO4] = {
  		.name			= "CL Picasso4",
  		.maxclock		= {
  			135100, 135100, 85500, 85500, 0
  		},

  		.init_sr07		= true,
  		.init_sr1f		= false,
  		.scrn_start_bit19	= true,

  		.sr07			= 0xA0,
  		.sr07_1bpp		= 0xA0,
  		.sr07_1bpp_mux		= 0xA6,
  		.sr07_8bpp		= 0xA1,
  		.sr07_8bpp_mux		= 0xA7,

  		.sr1f			= 0
  	},
  	[BT_ALPINE] = {
  		.name			= "CL Alpine",
  		.maxclock		= {
  			/* for the GD5430.  GD5446 can do more... */
  			85500, 85500, 50000, 28500, 0
  		},

  		.init_sr07		= true,
  		.init_sr1f		= true,
  		.scrn_start_bit19	= true,

  		.sr07			= 0xA0,

  		.sr07_1bpp		= 0xA0,
  		.sr07_1bpp_mux		= 0xA6,

  		.sr07_8bpp		= 0xA1,
  		.sr07_8bpp_mux		= 0xA7,
  		.sr1f			= 0x1C
  	},
  	[BT_GD5480] = {
  		.name			= "CL GD5480",
  		.maxclock		= {
  			135100, 200000, 200000, 135100, 135100
  		},

  		.init_sr07		= true,
  		.init_sr1f		= true,
  		.scrn_start_bit19	= true,

  		.sr07			= 0x10,
  		.sr07_1bpp		= 0x11,
  		.sr07_8bpp		= 0x11,
  		.sr1f			= 0x1C
  	},
  	[BT_LAGUNA] = {
  		.name			= "CL Laguna",
  		.maxclock		= {

  			/* taken from X11 code */
  			170000, 170000, 170000, 170000, 135100,
  		},
  		.init_sr07		= false,
  		.init_sr1f		= false,
  		.scrn_start_bit19	= true,
  	},
  	[BT_LAGUNAB] = {
  		.name			= "CL Laguna AGP",
  		.maxclock		= {
  			/* taken from X11 code */
  			170000, 250000, 170000, 170000, 135100,

  		},

  		.init_sr07		= false,
  		.init_sr1f		= false,
  		.scrn_start_bit19	= true,

  	}
  };

  #ifdef CONFIG_PCI
  #define CHIP(id, btype) \

  	{ PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }

  
  static struct pci_device_id cirrusfb_pci_table[] = {

  	CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),

  	CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
  	CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),

  	CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
  	CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
  	CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
  	CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
  	CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
  	CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
  	CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */

  	CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/

  	{ 0, }
  };
  MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
  #undef CHIP
  #endif /* CONFIG_PCI */

  #ifdef CONFIG_ZORRO

  struct zorrocl {
  	enum cirrus_board type;	/* Board type */
  	u32 regoffset;		/* Offset of registers in first Zorro device */
  	u32 ramsize;		/* Size of video RAM in first Zorro device */
  				/* If zero, use autoprobe on RAM device */
  	u32 ramoffset;		/* Offset of video RAM in first Zorro device */
  	zorro_id ramid;		/* Zorro ID of RAM device */

  	zorro_id ramid2;	/* Zorro ID of optional second RAM device */

  };
  
  static const struct zorrocl zcl_sd64 __devinitconst = {
  	.type		= BT_SD64,
  	.ramid		= ZORRO_PROD_HELFRICH_SD64_RAM,
  };
  
  static const struct zorrocl zcl_piccolo __devinitconst = {
  	.type		= BT_PICCOLO,
  	.ramid		= ZORRO_PROD_HELFRICH_PICCOLO_RAM,
  };
  
  static const struct zorrocl zcl_picasso __devinitconst = {
  	.type		= BT_PICASSO,
  	.ramid		= ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
  };
  
  static const struct zorrocl zcl_spectrum __devinitconst = {
  	.type		= BT_SPECTRUM,
  	.ramid		= ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
  };
  
  static const struct zorrocl zcl_picasso4_z3 __devinitconst = {
  	.type		= BT_PICASSO4,
  	.regoffset	= 0x00600000,
  	.ramsize	= 4 * MB_,

  	.ramoffset	= 0x01000000,	/* 0x02000000 for 64 MiB boards */

  };

  static const struct zorrocl zcl_picasso4_z2 __devinitconst = {
  	.type		= BT_PICASSO4,
  	.regoffset	= 0x10000,
  	.ramid		= ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
  	.ramid2		= ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
  };

  
  static const struct zorro_device_id cirrusfb_zorro_table[] __devinitconst = {

  	{

  		.id		= ZORRO_PROD_HELFRICH_SD64_REG,
  		.driver_data	= (unsigned long)&zcl_sd64,

  	}, {

  		.id		= ZORRO_PROD_HELFRICH_PICCOLO_REG,
  		.driver_data	= (unsigned long)&zcl_piccolo,

  	}, {

  		.id	= ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
  		.driver_data	= (unsigned long)&zcl_picasso,

  	}, {

  		.id		= ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
  		.driver_data	= (unsigned long)&zcl_spectrum,

  	}, {
  		.id		= ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,

  		.driver_data	= (unsigned long)&zcl_picasso4_z3,

  	}, {
  		.id		= ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
  		.driver_data	= (unsigned long)&zcl_picasso4_z2,

  	},
  	{ 0 }
  };

  MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);

  #endif /* CONFIG_ZORRO */

  #ifdef CIRRUSFB_DEBUG

  enum cirrusfb_dbg_reg_class {

  	CRT,
  	SEQ

  };

  #endif		/* CIRRUSFB_DEBUG */

  
  /* info about board */
  struct cirrusfb_info {

  	u8 __iomem *regbase;

  	u8 __iomem *laguna_mmio;

  	enum cirrus_board btype;

  	unsigned char SFR;	/* Shadow of special function register */

  	int multiplexing;

  	int doubleVCLK;

  	int blank_mode;

  	u32 pseudo_palette[16];

  	void (*unmap)(struct fb_info *info);

  };

  static bool noaccel __devinitdata;

  static char *mode_option __devinitdata = "640x480@60";

  
  /****************************************************************************/
  /**** BEGIN PROTOTYPES ******************************************************/

  /*--- Interface used by the world ------------------------------------------*/

  static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
  				struct fb_info *info);

  /*--- Internal routines ----------------------------------------------------*/

  static void init_vgachip(struct fb_info *info);

  static void switch_monitor(struct cirrusfb_info *cinfo, int on);
  static void WGen(const struct cirrusfb_info *cinfo,
  		 int regnum, unsigned char val);
  static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
  static void AttrOn(const struct cirrusfb_info *cinfo);
  static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
  static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
  static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
  static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
  		  unsigned char red, unsigned char green, unsigned char blue);

  #if 0

  static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
  		  unsigned char *red, unsigned char *green,
  		  unsigned char *blue);

  #endif

  static void cirrusfb_WaitBLT(u8 __iomem *regbase);
  static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
  			    u_short curx, u_short cury,
  			    u_short destx, u_short desty,
  			    u_short width, u_short height,
  			    u_short line_length);
  static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
  			      u_short x, u_short y,
  			      u_short width, u_short height,

  			      u32 fg_color, u32 bg_color,
  			      u_short line_length, u_char blitmode);

  static void bestclock(long freq, int *nom, int *den, int *div);

  
  #ifdef CIRRUSFB_DEBUG

  static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
  static void cirrusfb_dbg_print_regs(struct fb_info *info,
  				    caddr_t regbase,

  				    enum cirrusfb_dbg_reg_class reg_class, ...);

  #endif /* CIRRUSFB_DEBUG */
  
  /*** END   PROTOTYPES ********************************************************/
  /*****************************************************************************/
  /*** BEGIN Interface Used by the World ***************************************/

  static inline int is_laguna(const struct cirrusfb_info *cinfo)
  {
  	return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
  }

  static int opencount;

  
  /*--- Open /dev/fbx ---------------------------------------------------------*/

  static int cirrusfb_open(struct fb_info *info, int user)

  {
  	if (opencount++ == 0)

  		switch_monitor(info->par, 1);

  	return 0;
  }
  
  /*--- Close /dev/fbx --------------------------------------------------------*/

  static int cirrusfb_release(struct fb_info *info, int user)

  {
  	if (--opencount == 0)

  		switch_monitor(info->par, 0);

  	return 0;
  }
  
  /**** END   Interface used by the World *************************************/
  /****************************************************************************/
  /**** BEGIN Hardware specific Routines **************************************/

  /* Check if the MCLK is not a better clock source */

  static int cirrusfb_check_mclk(struct fb_info *info, long freq)

  {

  	struct cirrusfb_info *cinfo = info->par;

  	long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;

  	/* Read MCLK value */
  	mclk = (14318 * mclk) >> 3;

  	dev_dbg(info->device, "Read MCLK of %ld kHz
  ", mclk);

  
  	/* Determine if we should use MCLK instead of VCLK, and if so, what we

  	 * should divide it by to get VCLK
  	 */
  
  	if (abs(freq - mclk) < 250) {

  		dev_dbg(info->device, "Using VCLK = MCLK
  ");

  		return 1;
  	} else if (abs(freq - (mclk / 2)) < 250) {

  		dev_dbg(info->device, "Using VCLK = MCLK/2
  ");

  		return 2;

  	}

  	return 0;

  }

  static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
  				   struct fb_info *info)
  {
  	long freq;
  	long maxclock;
  	struct cirrusfb_info *cinfo = info->par;
  	unsigned maxclockidx = var->bits_per_pixel >> 3;
  
  	/* convert from ps to kHz */
  	freq = PICOS2KHZ(var->pixclock);
  
  	dev_dbg(info->device, "desired pixclock: %ld kHz
  ", freq);
  
  	maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
  	cinfo->multiplexing = 0;
  
  	/* If the frequency is greater than we can support, we might be able
  	 * to use multiplexing for the video mode */
  	if (freq > maxclock) {

  		dev_err(info->device,
  			"Frequency greater than maxclock (%ld kHz)
  ",
  			maxclock);
  		return -EINVAL;
  	}
  	/*
  	 * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
  	 * pixel clock
  	 */
  	if (var->bits_per_pixel == 8) {

  		switch (cinfo->btype) {
  		case BT_ALPINE:

  		case BT_SD64:

  		case BT_PICASSO4:
  			if (freq > 85500)
  				cinfo->multiplexing = 1;
  			break;

  		case BT_GD5480:

  			if (freq > 135100)
  				cinfo->multiplexing = 1;

  			break;
  
  		default:

  			break;

  		}
  	}

  
  	/* If we have a 1MB 5434, we need to put ourselves in a mode where

  	 * the VCLK is double the pixel clock. */

  	cinfo->doubleVCLK = 0;
  	if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
  	    var->bits_per_pixel == 16) {
  		cinfo->doubleVCLK = 1;

  	}

  	return 0;
  }

  static int cirrusfb_check_var(struct fb_var_screeninfo *var,
  			      struct fb_info *info)
  {

  	int yres;
  	/* memory size in pixels */
  	unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;

  	struct cirrusfb_info *cinfo = info->par;

  
  	switch (var->bits_per_pixel) {

  	case 1:

  		var->red.offset = 0;
  		var->red.length = 1;

  		var->green = var->red;
  		var->blue = var->red;

  		break;
  
  	case 8:
  		var->red.offset = 0;

  		var->red.length = 8;

  		var->green = var->red;
  		var->blue = var->red;

  		break;
  
  	case 16:

  		if (isPReP) {

  			var->red.offset = 2;
  			var->green.offset = -3;
  			var->blue.offset = 8;
  		} else {

  			var->red.offset = 11;

  			var->green.offset = 5;
  			var->blue.offset = 0;
  		}
  		var->red.length = 5;

  		var->green.length = 6;

  		var->blue.length = 5;
  		break;

  	case 24:

  		if (isPReP) {

  			var->red.offset = 0;
  			var->green.offset = 8;
  			var->blue.offset = 16;

  		} else {
  			var->red.offset = 16;
  			var->green.offset = 8;
  			var->blue.offset = 0;
  		}
  		var->red.length = 8;
  		var->green.length = 8;
  		var->blue.length = 8;
  		break;
  
  	default:

  		dev_dbg(info->device,
  			"Unsupported bpp size: %d
  ", var->bits_per_pixel);

  		return -EINVAL;

  	}

  	if (var->xres_virtual < var->xres)
  		var->xres_virtual = var->xres;
  	/* use highest possible virtual resolution */
  	if (var->yres_virtual == -1) {
  		var->yres_virtual = pixels / var->xres_virtual;
  
  		dev_info(info->device,
  			 "virtual resolution set to maximum of %dx%d
  ",
  			 var->xres_virtual, var->yres_virtual);
  	}
  	if (var->yres_virtual < var->yres)
  		var->yres_virtual = var->yres;
  
  	if (var->xres_virtual * var->yres_virtual > pixels) {
  		dev_err(info->device, "mode %dx%dx%d rejected... "
  		      "virtual resolution too high to fit into video memory!
  ",
  			var->xres_virtual, var->yres_virtual,
  			var->bits_per_pixel);
  		return -EINVAL;
  	}

  	if (var->xoffset < 0)
  		var->xoffset = 0;
  	if (var->yoffset < 0)
  		var->yoffset = 0;
  
  	/* truncate xoffset and yoffset to maximum if too high */
  	if (var->xoffset > var->xres_virtual - var->xres)
  		var->xoffset = var->xres_virtual - var->xres - 1;
  	if (var->yoffset > var->yres_virtual - var->yres)
  		var->yoffset = var->yres_virtual - var->yres - 1;

  	var->red.msb_right =
  	    var->green.msb_right =
  	    var->blue.msb_right =
  	    var->transp.offset =
  	    var->transp.length =
  	    var->transp.msb_right = 0;
  
  	yres = var->yres;
  	if (var->vmode & FB_VMODE_DOUBLE)
  		yres *= 2;
  	else if (var->vmode & FB_VMODE_INTERLACED)
  		yres = (yres + 1) / 2;
  
  	if (yres >= 1280) {

  		dev_err(info->device, "ERROR: VerticalTotal >= 1280; "

  			"special treatment required! (TODO)
  ");

  		return -EINVAL;
  	}

  	if (cirrusfb_check_pixclock(var, info))
  		return -EINVAL;

  	if (!is_laguna(cinfo))
  		var->accel_flags = FB_ACCELF_TEXT;

  	return 0;
  }

  static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)

  {

  	struct cirrusfb_info *cinfo = info->par;

  	unsigned char old1f, old1e;

  	assert(cinfo != NULL);

  	old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
  
  	if (div) {

  		dev_dbg(info->device, "Set %s as pixclock source.
  ",
  			(div == 2) ? "MCLK/2" : "MCLK");

  		old1f |= 0x40;
  		old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
  		if (div == 2)
  			old1e |= 1;

  		vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);

  	}

  	vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);

  }
  
  /*************************************************************************
  	cirrusfb_set_par_foo()
  
  	actually writes the values for a new video mode into the hardware,
  **************************************************************************/

  static int cirrusfb_set_par_foo(struct fb_info *info)

  {
  	struct cirrusfb_info *cinfo = info->par;
  	struct fb_var_screeninfo *var = &info->var;

  	u8 __iomem *regbase = cinfo->regbase;
  	unsigned char tmp;

  	int pitch;

  	const struct cirrusfb_board_info_rec *bi;

  	int hdispend, hsyncstart, hsyncend, htotal;
  	int yres, vdispend, vsyncstart, vsyncend, vtotal;

  	long freq;
  	int nom, den, div;

  	unsigned int control = 0, format = 0, threshold = 0;

  	dev_dbg(info->device, "Requested mode: %dx%dx%d
  ",

  	       var->xres, var->yres, var->bits_per_pixel);

  	switch (var->bits_per_pixel) {
  	case 1:
  		info->fix.line_length = var->xres_virtual / 8;
  		info->fix.visual = FB_VISUAL_MONO10;
  		break;

  	case 8:
  		info->fix.line_length = var->xres_virtual;
  		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  		break;
  
  	case 16:

  	case 24:

  		info->fix.line_length = var->xres_virtual *
  					var->bits_per_pixel >> 3;
  		info->fix.visual = FB_VISUAL_TRUECOLOR;
  		break;

  	}

  	info->fix.type = FB_TYPE_PACKED_PIXELS;
  
  	init_vgachip(info);

  
  	bi = &cirrusfb_board_info[cinfo->btype];

  	hsyncstart = var->xres + var->right_margin;
  	hsyncend = hsyncstart + var->hsync_len;

  	htotal = (hsyncend + var->left_margin) / 8;
  	hdispend = var->xres / 8;
  	hsyncstart = hsyncstart / 8;
  	hsyncend = hsyncend / 8;

  	vdispend = var->yres;
  	vsyncstart = vdispend + var->lower_margin;

  	vsyncend = vsyncstart + var->vsync_len;
  	vtotal = vsyncend + var->upper_margin;

  
  	if (var->vmode & FB_VMODE_DOUBLE) {

  		vdispend *= 2;

  		vsyncstart *= 2;
  		vsyncend *= 2;
  		vtotal *= 2;
  	} else if (var->vmode & FB_VMODE_INTERLACED) {

  		vdispend = (vdispend + 1) / 2;

  		vsyncstart = (vsyncstart + 1) / 2;
  		vsyncend = (vsyncend + 1) / 2;
  		vtotal = (vtotal + 1) / 2;
  	}

  	yres = vdispend;

  	if (yres >= 1024) {
  		vtotal /= 2;
  		vsyncstart /= 2;
  		vsyncend /= 2;
  		vdispend /= 2;
  	}

  
  	vdispend -= 1;
  	vsyncstart -= 1;
  	vsyncend -= 1;
  	vtotal -= 2;

  	if (cinfo->multiplexing) {

  		htotal /= 2;
  		hsyncstart /= 2;
  		hsyncend /= 2;
  		hdispend /= 2;
  	}

  
  	htotal -= 5;
  	hdispend -= 1;
  	hsyncstart += 1;
  	hsyncend += 1;

  	/* unlock register VGA_CRTC_H_TOTAL..CRT7 */

  	vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);	/* previously: 0x00) */

  
  	/* if debugging is enabled, all parameters get output before writing */

  	dev_dbg(info->device, "CRT0: %d
  ", htotal);

  	vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);

  	dev_dbg(info->device, "CRT1: %d
  ", hdispend);

  	vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);

  	dev_dbg(info->device, "CRT2: %d
  ", var->xres / 8);

  	vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);

  	/*  + 128: Compatible read */

  	dev_dbg(info->device, "CRT3: 128+%d
  ", (htotal + 5) % 32);

  	vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,

  		 128 + ((htotal + 5) % 32));

  	dev_dbg(info->device, "CRT4: %d
  ", hsyncstart);

  	vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);

  	tmp = hsyncend % 32;
  	if ((htotal + 5) & 32)

  		tmp += 128;

  	dev_dbg(info->device, "CRT5: %d
  ", tmp);

  	vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);

  	dev_dbg(info->device, "CRT6: %d
  ", vtotal & 0xff);

  	vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);

  
  	tmp = 16;		/* LineCompare bit #9 */

  	if (vtotal & 256)

  		tmp |= 1;

  	if (vdispend & 256)

  		tmp |= 2;

  	if (vsyncstart & 256)

  		tmp |= 4;

  	if ((vdispend + 1) & 256)

  		tmp |= 8;

  	if (vtotal & 512)

  		tmp |= 32;

  	if (vdispend & 512)

  		tmp |= 64;

  	if (vsyncstart & 512)

  		tmp |= 128;

  	dev_dbg(info->device, "CRT7: %d
  ", tmp);

  	vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);

  
  	tmp = 0x40;		/* LineCompare bit #8 */

  	if ((vdispend + 1) & 512)

  		tmp |= 0x20;
  	if (var->vmode & FB_VMODE_DOUBLE)
  		tmp |= 0x80;

  	dev_dbg(info->device, "CRT9: %d
  ", tmp);

  	vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);

  	dev_dbg(info->device, "CRT10: %d
  ", vsyncstart & 0xff);

  	vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);

  	dev_dbg(info->device, "CRT11: 64+32+%d
  ", vsyncend % 16);

  	vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);

  	dev_dbg(info->device, "CRT12: %d
  ", vdispend & 0xff);

  	vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);

  	dev_dbg(info->device, "CRT15: %d
  ", (vdispend + 1) & 0xff);

  	vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);

  	dev_dbg(info->device, "CRT16: %d
  ", vtotal & 0xff);

  	vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);

  	dev_dbg(info->device, "CRT18: 0xff
  ");

  	vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);

  
  	tmp = 0;
  	if (var->vmode & FB_VMODE_INTERLACED)
  		tmp |= 1;

  	if ((htotal + 5) & 64)

  		tmp |= 16;

  	if ((htotal + 5) & 128)

  		tmp |= 32;

  	if (vtotal & 256)

  		tmp |= 64;

  	if (vtotal & 512)

  		tmp |= 128;

  	dev_dbg(info->device, "CRT1a: %d
  ", tmp);

  	vga_wcrt(regbase, CL_CRT1A, tmp);

  	freq = PICOS2KHZ(var->pixclock);

  	if (var->bits_per_pixel == 24)
  		if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
  			freq *= 3;

  	if (cinfo->multiplexing)
  		freq /= 2;

  	if (cinfo->doubleVCLK)
  		freq *= 2;

  	bestclock(freq, &nom, &den, &div);

  	dev_dbg(info->device, "VCLK freq: %ld kHz  nom: %d  den: %d  div: %d
  ",
  		freq, nom, den, div);

  	/* set VCLK0 */
  	/* hardware RefClock: 14.31818 MHz */
  	/* formula: VClk = (OSC * N) / (D * (1+P)) */
  	/* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */

  	if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
  	    cinfo->btype == BT_SD64) {

  		/* if freq is close to mclk or mclk/2 select mclk
  		 * as clock source
  		 */

  		int divMCLK = cirrusfb_check_mclk(info, freq);

  		if (divMCLK)

  			nom = 0;

  		cirrusfb_set_mclk_as_source(info, divMCLK);

  	}

  	if (is_laguna(cinfo)) {

  		long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
  		unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
  		unsigned short tile_control;

  		if (cinfo->btype == BT_LAGUNAB) {
  			tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
  			tile_control &= ~0x80;
  			fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
  		}

  
  		fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
  		fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
  		control = fb_readw(cinfo->laguna_mmio + 0x402);
  		threshold = fb_readw(cinfo->laguna_mmio + 0xea);
  		control &= ~0x6800;
  		format = 0;

  		threshold &= 0xffc0 & 0x3fbf;

  	}

  	if (nom) {

  		tmp = den << 1;
  		if (div != 0)
  			tmp |= 1;

  		/* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
  		if ((cinfo->btype == BT_SD64) ||
  		    (cinfo->btype == BT_ALPINE) ||
  		    (cinfo->btype == BT_GD5480))
  			tmp |= 0x80;

  		/* Laguna chipset has reversed clock registers */

  		if (is_laguna(cinfo)) {

  			vga_wseq(regbase, CL_SEQRE, tmp);
  			vga_wseq(regbase, CL_SEQR1E, nom);
  		} else {

  			vga_wseq(regbase, CL_SEQRE, nom);
  			vga_wseq(regbase, CL_SEQR1E, tmp);

  		}

  	}

  	if (yres >= 1024)

  		/* 1280x1024 */

  		vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);

  	else
  		/* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
  		 * address wrap, no compat. */

  		vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);

  	/* don't know if it would hurt to also program this if no interlaced */
  	/* mode is used, but I feel better this way.. :-) */
  	if (var->vmode & FB_VMODE_INTERLACED)

  		vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);

  	else

  		vga_wcrt(regbase, VGA_CRTC_REGS, 0x00);	/* interlace control */

  	/* adjust horizontal/vertical sync type (low/high), use VCLK3 */

  	/* enable display memory & CRTC I/O address for color mode */

  	tmp = 0x03 | 0xc;

  	if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  		tmp |= 0x40;
  	if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  		tmp |= 0x80;

  	WGen(cinfo, VGA_MIS_W, tmp);

  	/* text cursor on and start line */
  	vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
  	/* text cursor end line */
  	vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);

  
  	/******************************************************
  	 *
  	 * 1 bpp
  	 *
  	 */
  
  	/* programming for different color depths */
  	if (var->bits_per_pixel == 1) {

  		dev_dbg(info->device, "preparing for 1 bit deep display
  ");

  		vga_wgfx(regbase, VGA_GFX_MODE, 0);	/* mode register */

  
  		/* SR07 */
  		switch (cinfo->btype) {
  		case BT_SD64:
  		case BT_PICCOLO:
  		case BT_PICASSO:
  		case BT_SPECTRUM:
  		case BT_PICASSO4:
  		case BT_ALPINE:
  		case BT_GD5480:

  			vga_wseq(regbase, CL_SEQR7,

  				 cinfo->multiplexing ?

  					bi->sr07_1bpp_mux : bi->sr07_1bpp);
  			break;
  
  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			vga_wseq(regbase, CL_SEQR7,
  				vga_rseq(regbase, CL_SEQR7) & ~0x01);

  			break;
  
  		default:

  			dev_warn(info->device, "unknown Board
  ");

  			break;
  		}
  
  		/* Extended Sequencer Mode */
  		switch (cinfo->btype) {

  
  		case BT_PICCOLO:

  		case BT_SPECTRUM:

  			/* evtl d0 bei 1 bit? avoid FIFO underruns..? */
  			vga_wseq(regbase, CL_SEQRF, 0xb0);

  			break;
  
  		case BT_PICASSO:

  			/* ## vorher d0 avoid FIFO underruns..? */
  			vga_wseq(regbase, CL_SEQRF, 0xd0);

  			break;

  		case BT_SD64:

  		case BT_PICASSO4:
  		case BT_ALPINE:
  		case BT_GD5480:
  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			/* do nothing */
  			break;
  
  		default:

  			dev_warn(info->device, "unknown Board
  ");

  			break;
  		}

  		/* pixel mask: pass-through for first plane */
  		WGen(cinfo, VGA_PEL_MSK, 0x01);

  		if (cinfo->multiplexing)

  			/* hidden dac reg: 1280x1024 */
  			WHDR(cinfo, 0x4a);

  		else

  			/* hidden dac: nothing */
  			WHDR(cinfo, 0);
  		/* memory mode: odd/even, ext. memory */
  		vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
  		/* plane mask: only write to first plane */
  		vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);

  	}
  
  	/******************************************************
  	 *
  	 * 8 bpp
  	 *
  	 */
  
  	else if (var->bits_per_pixel == 8) {

  		dev_dbg(info->device, "preparing for 8 bit deep display
  ");

  		switch (cinfo->btype) {
  		case BT_SD64:
  		case BT_PICCOLO:
  		case BT_PICASSO:
  		case BT_SPECTRUM:
  		case BT_PICASSO4:
  		case BT_ALPINE:
  		case BT_GD5480:

  			vga_wseq(regbase, CL_SEQR7,

  				  cinfo->multiplexing ?

  					bi->sr07_8bpp_mux : bi->sr07_8bpp);
  			break;
  
  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			vga_wseq(regbase, CL_SEQR7,
  				vga_rseq(regbase, CL_SEQR7) | 0x01);

  			threshold |= 0x10;

  			break;
  
  		default:

  			dev_warn(info->device, "unknown Board
  ");

  			break;
  		}
  
  		switch (cinfo->btype) {

  		case BT_PICCOLO:

  		case BT_PICASSO:

  		case BT_SPECTRUM:

  			/* Fast Page-Mode writes */
  			vga_wseq(regbase, CL_SEQRF, 0xb0);

  			break;
  
  		case BT_PICASSO4:
  #ifdef CONFIG_ZORRO

  			/* ### INCOMPLETE!! */
  			vga_wseq(regbase, CL_SEQRF, 0xb8);

  #endif

  		case BT_ALPINE:

  		case BT_SD64:

  		case BT_GD5480:
  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			/* do nothing */
  			break;
  
  		default:

  			dev_warn(info->device, "unknown board
  ");

  			break;
  		}

  		/* mode register: 256 color mode */
  		vga_wgfx(regbase, VGA_GFX_MODE, 64);

  		if (cinfo->multiplexing)

  			/* hidden dac reg: 1280x1024 */
  			WHDR(cinfo, 0x4a);

  		else

  			/* hidden dac: nothing */
  			WHDR(cinfo, 0);

  	}
  
  	/******************************************************
  	 *
  	 * 16 bpp
  	 *
  	 */
  
  	else if (var->bits_per_pixel == 16) {

  		dev_dbg(info->device, "preparing for 16 bit deep display
  ");

  		switch (cinfo->btype) {

  		case BT_PICCOLO:

  		case BT_SPECTRUM:

  			vga_wseq(regbase, CL_SEQR7, 0x87);
  			/* Fast Page-Mode writes */
  			vga_wseq(regbase, CL_SEQRF, 0xb0);

  			break;
  
  		case BT_PICASSO:

  			vga_wseq(regbase, CL_SEQR7, 0x27);
  			/* Fast Page-Mode writes */
  			vga_wseq(regbase, CL_SEQRF, 0xb0);

  			break;

  		case BT_SD64:

  		case BT_PICASSO4:

  		case BT_ALPINE:

  			/* Extended Sequencer Mode: 256c col. mode */

  			vga_wseq(regbase, CL_SEQR7,
  					cinfo->doubleVCLK ? 0xa3 : 0xa7);

  			break;
  
  		case BT_GD5480:

  			vga_wseq(regbase, CL_SEQR7, 0x17);

  			/* We already set SRF and SR1F */
  			break;
  
  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			vga_wseq(regbase, CL_SEQR7,
  				vga_rseq(regbase, CL_SEQR7) & ~0x01);

  			control |= 0x2000;
  			format |= 0x1400;
  			threshold |= 0x10;

  			break;
  
  		default:

  			dev_warn(info->device, "unknown Board
  ");

  			break;
  		}

  		/* mode register: 256 color mode */
  		vga_wgfx(regbase, VGA_GFX_MODE, 64);

  #ifdef CONFIG_PCI

  		WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);

  #elif defined(CONFIG_ZORRO)
  		/* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */

  		WHDR(cinfo, 0xa0);	/* hidden dac reg: nothing special */

  #endif

  	}
  
  	/******************************************************
  	 *

  	 * 24 bpp

  	 *
  	 */

  	else if (var->bits_per_pixel == 24) {
  		dev_dbg(info->device, "preparing for 24 bit deep display
  ");

  		switch (cinfo->btype) {

  		case BT_PICCOLO:

  		case BT_SPECTRUM:

  			vga_wseq(regbase, CL_SEQR7, 0x85);
  			/* Fast Page-Mode writes */
  			vga_wseq(regbase, CL_SEQRF, 0xb0);

  			break;
  
  		case BT_PICASSO:

  			vga_wseq(regbase, CL_SEQR7, 0x25);
  			/* Fast Page-Mode writes */
  			vga_wseq(regbase, CL_SEQRF, 0xb0);

  			break;

  		case BT_SD64:

  		case BT_PICASSO4:

  		case BT_ALPINE:

  			/* Extended Sequencer Mode: 256c col. mode */

  			vga_wseq(regbase, CL_SEQR7, 0xa5);

  			break;
  
  		case BT_GD5480:

  			vga_wseq(regbase, CL_SEQR7, 0x15);

  			/* We already set SRF and SR1F */
  			break;
  
  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			vga_wseq(regbase, CL_SEQR7,
  				vga_rseq(regbase, CL_SEQR7) & ~0x01);

  			control |= 0x4000;
  			format |= 0x2400;

  			threshold |= 0x20;

  			break;
  
  		default:

  			dev_warn(info->device, "unknown Board
  ");

  			break;
  		}

  		/* mode register: 256 color mode */
  		vga_wgfx(regbase, VGA_GFX_MODE, 64);

  		/* hidden dac reg: 8-8-8 mode (24 or 32) */
  		WHDR(cinfo, 0xc5);

  	}
  
  	/******************************************************
  	 *
  	 * unknown/unsupported bpp
  	 *
  	 */

  	else

  		dev_err(info->device,
  			"What's this? requested color depth == %d.
  ",

  			var->bits_per_pixel);

  	pitch = info->fix.line_length >> 3;
  	vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);

  	tmp = 0x22;

  	if (pitch & 0x100)

  		tmp |= 0x10;	/* offset overflow bit */

  	/* screen start addr #16-18, fastpagemode cycles */
  	vga_wcrt(regbase, CL_CRT1B, tmp);

  	/* screen start address bit 19 */
  	if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)

  		vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);

  	if (is_laguna(cinfo)) {

  		tmp = 0;
  		if ((htotal + 5) & 256)
  			tmp |= 128;
  		if (hdispend & 256)
  			tmp |= 64;
  		if (hsyncstart & 256)
  			tmp |= 48;
  		if (vtotal & 1024)
  			tmp |= 8;
  		if (vdispend & 1024)
  			tmp |= 4;
  		if (vsyncstart & 1024)
  			tmp |= 3;
  
  		vga_wcrt(regbase, CL_CRT1E, tmp);
  		dev_dbg(info->device, "CRT1e: %d
  ", tmp);
  	}

  	/* pixel panning */
  	vga_wattr(regbase, CL_AR33, 0);

  
  	/* [ EGS: SetOffset(); ] */
  	/* From SetOffset(): Turn on VideoEnable bit in Attribute controller */

  	AttrOn(cinfo);

  	if (is_laguna(cinfo)) {

  		/* no tiles */
  		fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
  		fb_writew(format, cinfo->laguna_mmio + 0xc0);
  		fb_writew(threshold, cinfo->laguna_mmio + 0xea);
  	}

  	/* finally, turn on everything - turn off "FullBandwidth" bit */
  	/* also, set "DotClock%2" bit where requested */
  	tmp = 0x01;
  
  /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
      if (var->vmode & FB_VMODE_CLOCK_HALVE)
  	tmp |= 0x08;
  */

  	vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);

  	dev_dbg(info->device, "CL_SEQR1: %d
  ", tmp);

  #ifdef CIRRUSFB_DEBUG

  	cirrusfb_dbg_reg_dump(info, NULL);

  #endif

  	return 0;
  }
  
  /* for some reason incomprehensible to me, cirrusfb requires that you write
   * the registers twice for the settings to take..grr. -dte */

  static int cirrusfb_set_par(struct fb_info *info)

  {

  	cirrusfb_set_par_foo(info);
  	return cirrusfb_set_par_foo(info);

  }

  static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
  			      unsigned blue, unsigned transp,
  			      struct fb_info *info)

  {
  	struct cirrusfb_info *cinfo = info->par;
  
  	if (regno > 255)
  		return -EINVAL;
  
  	if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
  		u32 v;
  		red >>= (16 - info->var.red.length);
  		green >>= (16 - info->var.green.length);
  		blue >>= (16 - info->var.blue.length);

  		if (regno >= 16)

  			return 1;
  		v = (red << info->var.red.offset) |
  		    (green << info->var.green.offset) |
  		    (blue << info->var.blue.offset);

  		cinfo->pseudo_palette[regno] = v;

  		return 0;
  	}

  	if (info->var.bits_per_pixel == 8)
  		WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);

  
  	return 0;
  
  }
  
  /*************************************************************************
  	cirrusfb_pan_display()
  
  	performs display panning - provided hardware permits this
  **************************************************************************/

  static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
  				struct fb_info *info)

  {

  	int xoffset;

  	unsigned long base;

  	unsigned char tmp, xpix;

  	struct cirrusfb_info *cinfo = info->par;

  	/* no range checks for xoffset and yoffset,   */
  	/* as fb_pan_display has already done this */
  	if (var->vmode & FB_VMODE_YWRAP)
  		return -EINVAL;

  	xoffset = var->xoffset * info->var.bits_per_pixel / 8;

  	base = var->yoffset * info->fix.line_length + xoffset;

  
  	if (info->var.bits_per_pixel == 1) {
  		/* base is already correct */
  		xpix = (unsigned char) (var->xoffset % 8);
  	} else {
  		base /= 4;
  		xpix = (unsigned char) ((xoffset % 4) * 2);
  	}

  	if (!is_laguna(cinfo))

  		cirrusfb_WaitBLT(cinfo->regbase);

  
  	/* lower 8 + 8 bits of screen start address */

  	vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
  	vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);

  	/* 0xf2 is %11110010, exclude tmp bits */
  	tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;

  	/* construct bits 16, 17 and 18 of screen start address */
  	if (base & 0x10000)
  		tmp |= 0x01;
  	if (base & 0x20000)
  		tmp |= 0x04;
  	if (base & 0x40000)
  		tmp |= 0x08;

  	vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);

  
  	/* construct bit 19 of screen start address */

  	if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {

  		tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
  		if (is_laguna(cinfo))
  			tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
  		else
  			tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);

  		vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
  	}

  	/* write pixel panning value to AR33; this does not quite work in 8bpp
  	 *
  	 * ### Piccolo..? Will this work?
  	 */

  	if (info->var.bits_per_pixel == 1)

  		vga_wattr(cinfo->regbase, CL_AR33, xpix);

  	return 0;

  }

  static int cirrusfb_blank(int blank_mode, struct fb_info *info)

  {
  	/*

  	 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
  	 * then the caller blanks by setting the CLUT (Color Look Up Table)
  	 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
  	 * failed due to e.g. a video mode which doesn't support it.
  	 * Implements VESA suspend and powerdown modes on hardware that
  	 * supports disabling hsync/vsync:
  	 *   blank_mode == 2: suspend vsync
  	 *   blank_mode == 3: suspend hsync
  	 *   blank_mode == 4: powerdown

  	 */
  	unsigned char val;
  	struct cirrusfb_info *cinfo = info->par;
  	int current_mode = cinfo->blank_mode;

  	dev_dbg(info->device, "ENTER, blank mode = %d
  ", blank_mode);

  
  	if (info->state != FBINFO_STATE_RUNNING ||
  	    current_mode == blank_mode) {

  		dev_dbg(info->device, "EXIT, returning 0
  ");

  		return 0;
  	}
  
  	/* Undo current */
  	if (current_mode == FB_BLANK_NORMAL ||

  	    current_mode == FB_BLANK_UNBLANK)

  		/* clear "FullBandwidth" bit */

  		val = 0;
  	else

  		/* set "FullBandwidth" bit */

  		val = 0x20;
  
  	val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
  	vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);

  
  	switch (blank_mode) {
  	case FB_BLANK_UNBLANK:
  	case FB_BLANK_NORMAL:

  		val = 0x00;

  		break;
  	case FB_BLANK_VSYNC_SUSPEND:

  		val = 0x04;

  		break;
  	case FB_BLANK_HSYNC_SUSPEND:

  		val = 0x02;

  		break;
  	case FB_BLANK_POWERDOWN:

  		val = 0x06;

  		break;
  	default:

  		dev_dbg(info->device, "EXIT, returning 1
  ");

  		return 1;
  	}

  	vga_wgfx(cinfo->regbase, CL_GRE, val);

  	cinfo->blank_mode = blank_mode;

  	dev_dbg(info->device, "EXIT, returning 0
  ");

  
  	/* Let fbcon do a soft blank for us */
  	return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
  }

  /**** END   Hardware specific Routines **************************************/
  /****************************************************************************/
  /**** BEGIN Internal Routines ***********************************************/

  static void init_vgachip(struct fb_info *info)

  {

  	struct cirrusfb_info *cinfo = info->par;

  	const struct cirrusfb_board_info_rec *bi;

  	assert(cinfo != NULL);

  
  	bi = &cirrusfb_board_info[cinfo->btype];
  
  	/* reset board globally */
  	switch (cinfo->btype) {
  	case BT_PICCOLO:

  		WSFR(cinfo, 0x01);
  		udelay(500);
  		WSFR(cinfo, 0x51);
  		udelay(500);

  		break;
  	case BT_PICASSO:

  		WSFR2(cinfo, 0xff);
  		udelay(500);

  		break;
  	case BT_SD64:
  	case BT_SPECTRUM:

  		WSFR(cinfo, 0x1f);
  		udelay(500);
  		WSFR(cinfo, 0x4f);
  		udelay(500);

  		break;
  	case BT_PICASSO4:

  		/* disable flickerfixer */
  		vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
  		mdelay(100);

  		/* mode */
  		vga_wgfx(cinfo->regbase, CL_GR31, 0x00);

  	case BT_GD5480:  /* fall through */

  		/* from Klaus' NetBSD driver: */
  		vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);

  	case BT_ALPINE:  /* fall through */
  		/* put blitter into 542x compat */
  		vga_wgfx(cinfo->regbase, CL_GR33, 0x00);

  		break;

  	case BT_LAGUNA:

  	case BT_LAGUNAB:

  		/* Nothing to do to reset the board. */
  		break;
  
  	default:

  		dev_err(info->device, "Warning: Unknown board type
  ");

  		break;
  	}

  	/* make sure RAM size set by this point */
  	assert(info->screen_size > 0);

  
  	/* the P4 is not fully initialized here; I rely on it having been */
  	/* inited under AmigaOS already, which seems to work just fine    */

  	/* (Klaus advised to do it this way)			      */

  
  	if (cinfo->btype != BT_PICASSO4) {

  		WGen(cinfo, CL_VSSM, 0x10);	/* EGS: 0x16 */
  		WGen(cinfo, CL_POS102, 0x01);
  		WGen(cinfo, CL_VSSM, 0x08);	/* EGS: 0x0e */

  
  		if (cinfo->btype != BT_SD64)

  			WGen(cinfo, CL_VSSM2, 0x01);

  		/* reset sequencer logic */

  		vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);

  		/* FullBandwidth (video off) and 8/9 dot clock */
  		vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);

  		/* "magic cookie" - doesn't make any sense to me.. */
  /*      vga_wgfx(cinfo->regbase, CL_GRA, 0xce);   */
  		/* unlock all extension registers */
  		vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);

  		switch (cinfo->btype) {
  		case BT_GD5480:

  			vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);

  			break;
  		case BT_ALPINE:

  		case BT_LAGUNA:

  		case BT_LAGUNAB:

  			break;
  		case BT_SD64:

  #ifdef CONFIG_ZORRO

  			vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);

  #endif

  			break;
  		default:

  			vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
  			vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);

  			break;
  		}
  	}

  	/* plane mask: nothing */
  	vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
  	/* character map select: doesn't even matter in gx mode */
  	vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);

  	/* memory mode: chain4, ext. memory */
  	vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);

  
  	/* controller-internal base address of video memory */
  	if (bi->init_sr07)

  		vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);

  	/*  vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
  	/* EEPROM control: shouldn't be necessary to write to this at all.. */

  	/* graphics cursor X position (incomplete; position gives rem. 3 bits */
  	vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
  	/* graphics cursor Y position (..."... ) */
  	vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
  	/* graphics cursor attributes */
  	vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
  	/* graphics cursor pattern address */
  	vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);

  
  	/* writing these on a P4 might give problems..  */
  	if (cinfo->btype != BT_PICASSO4) {

  		/* configuration readback and ext. color */
  		vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
  		/* signature generator */
  		vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);

  	}

  	/* Screen A preset row scan: none */
  	vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
  	/* Text cursor start: disable text cursor */
  	vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
  	/* Text cursor end: - */
  	vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);