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drivers/ide/pdc202xx_old.c
10.1 KB
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/* |
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* Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org> |
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* Copyright (C) 2006-2007, 2009 MontaVista Software, Inc. |
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* Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz |
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* |
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* Portions Copyright (C) 1999 Promise Technology, Inc. * Author: Frank Tiernan (frankt@promise.com) * Released under terms of General Public License */ |
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#include <linux/types.h> #include <linux/module.h> #include <linux/kernel.h> #include <linux/delay.h> |
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#include <linux/blkdev.h> |
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#include <linux/pci.h> #include <linux/init.h> #include <linux/ide.h> #include <asm/io.h> |
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#define DRV_NAME "pdc202xx_old" |
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static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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u8 drive_pci = 0x60 + (drive->dn << 2); |
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const u8 speed = drive->dma_mode; |
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u8 AP = 0, BP = 0, CP = 0; |
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u8 TA = 0, TB = 0, TC = 0; |
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pci_read_config_byte(dev, drive_pci, &AP); pci_read_config_byte(dev, drive_pci + 1, &BP); pci_read_config_byte(dev, drive_pci + 2, &CP); |
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switch(speed) { |
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case XFER_UDMA_5: case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; case XFER_UDMA_3: case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; case XFER_UDMA_0: case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; |
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case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break; |
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case XFER_PIO_4: TA = 0x01; TB = 0x04; break; case XFER_PIO_3: TA = 0x02; TB = 0x06; break; case XFER_PIO_2: TA = 0x03; TB = 0x08; break; case XFER_PIO_1: TA = 0x05; TB = 0x0C; break; case XFER_PIO_0: default: TA = 0x09; TB = 0x13; break; } if (speed < XFER_SW_DMA_0) { |
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/* * preserve SYNC_INT / ERDDY_EN bits while clearing * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A */ AP &= ~0x3f; |
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if (ide_pio_need_iordy(drive, speed - XFER_PIO_0)) |
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AP |= 0x20; /* set IORDY_EN bit */ if (drive->media == ide_disk) AP |= 0x10; /* set Prefetch_EN bit */ /* clear PB[4:0] bits of register B */ BP &= ~0x1f; pci_write_config_byte(dev, drive_pci, AP | TA); pci_write_config_byte(dev, drive_pci + 1, BP | TB); |
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} else { |
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/* clear MB[2:0] bits of register B */ BP &= ~0xe0; /* clear MC[3:0] bits of register C */ CP &= ~0x0f; pci_write_config_byte(dev, drive_pci + 1, BP | TB); pci_write_config_byte(dev, drive_pci + 2, CP | TC); |
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} |
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} |
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static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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drive->dma_mode = drive->pio_mode; pdc202xx_set_mode(hwif, drive); |
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} |
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static int pdc202xx_test_irq(ide_hwif_t *hwif) { struct pci_dev *dev = to_pci_dev(hwif->dev); unsigned long high_16 = pci_resource_start(dev, 4); u8 sc1d = inb(high_16 + 0x1d); if (hwif->channel) { /* * bit 7: error, bit 6: interrupting, * bit 5: FIFO full, bit 4: FIFO empty */ |
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return (sc1d & 0x40) ? 1 : 0; |
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} else { /* * bit 3: error, bit 2: interrupting, * bit 1: FIFO full, bit 0: FIFO empty */ |
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return (sc1d & 0x04) ? 1 : 0; |
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} } |
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static u8 pdc2026x_cable_detect(ide_hwif_t *hwif) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10); |
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pci_read_config_word(dev, 0x50, &CIS); |
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return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; |
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} /* * Set the control register to use the 66MHz system * clock for UDMA 3/4/5 mode operation when necessary. * |
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* FIXME: this register is shared by both channels, some locking is needed * |
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* It may also be possible to leave the 66MHz clock on * and readjust the timing parameters. */ static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif) { |
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unsigned long clock_reg = hwif->extra_base + 0x01; |
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u8 clock = inb(clock_reg); |
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outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg); |
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} static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif) { |
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unsigned long clock_reg = hwif->extra_base + 0x01; |
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u8 clock = inb(clock_reg); |
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outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg); |
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} |
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static void pdc2026x_init_hwif(ide_hwif_t *hwif) { pdc_old_disable_66MHz_clock(hwif); } |
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static void pdc202xx_dma_start(ide_drive_t *drive) |
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{ if (drive->current_speed > XFER_UDMA_2) pdc_old_enable_66MHz_clock(drive->hwif); |
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if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { |
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ide_hwif_t *hwif = drive->hwif; |
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struct request *rq = hwif->rq; |
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unsigned long high_16 = hwif->extra_base - 16; |
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unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); u32 word_count = 0; |
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u8 clock = inb(high_16 + 0x11); |
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outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11); |
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word_count = (blk_rq_sectors(rq) << 8); |
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word_count = (rq_data_dir(rq) == READ) ? word_count | 0x05000000 : word_count | 0x06000000; |
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outl(word_count, atapi_reg); |
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} ide_dma_start(drive); } |
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static int pdc202xx_dma_end(ide_drive_t *drive) |
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{ |
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if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) { |
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ide_hwif_t *hwif = drive->hwif; |
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unsigned long high_16 = hwif->extra_base - 16; |
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unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20); u8 clock = 0; |
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outl(0, atapi_reg); /* zero out extra */ clock = inb(high_16 + 0x11); outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11); |
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} if (drive->current_speed > XFER_UDMA_2) pdc_old_disable_66MHz_clock(drive->hwif); |
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return ide_dma_end(drive); |
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} |
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static int init_chipset_pdc202xx(struct pci_dev *dev) |
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{ |
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unsigned long dmabase = pci_resource_start(dev, 4); |
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u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0; |
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if (dmabase == 0) goto out; |
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udma_speed_flag = inb(dmabase | 0x1f); primary_mode = inb(dmabase | 0x1a); secondary_mode = inb(dmabase | 0x1b); |
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printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \ "Primary %s Mode " \ |
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"Secondary %s Mode. ", pci_name(dev), |
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(udma_speed_flag & 1) ? "EN" : "DIS", (primary_mode & 1) ? "MASTER" : "PCI", (secondary_mode & 1) ? "MASTER" : "PCI" ); |
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if (!(udma_speed_flag & 1)) { printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ", |
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pci_name(dev), udma_speed_flag, |
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(udma_speed_flag|1)); |
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outb(udma_speed_flag | 1, dmabase | 0x1f); printk("%sACTIVE ", (inb(dmabase | 0x1f) & 1) ? "" : "IN"); |
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} |
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out: |
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return 0; |
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} |
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static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev, const char *name) |
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{ if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) { u8 irq = 0, irq2 = 0; pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); /* 0xbc */ pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); if (irq != irq2) { pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */ |
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printk(KERN_INFO "%s %s: PCI config space interrupt " "mirror fixed ", name, pci_name(dev)); |
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} } |
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} |
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#define IDE_HFLAGS_PDC202XX \ (IDE_HFLAG_ERROR_STOPS_FIFO | \ |
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IDE_HFLAG_OFF_BOARD) |
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static const struct ide_port_ops pdc20246_port_ops = { .set_pio_mode = pdc202xx_set_pio_mode, .set_dma_mode = pdc202xx_set_mode, |
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.test_irq = pdc202xx_test_irq, |
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}; static const struct ide_port_ops pdc2026x_port_ops = { .set_pio_mode = pdc202xx_set_pio_mode, .set_dma_mode = pdc202xx_set_mode, |
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.test_irq = pdc202xx_test_irq, |
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.cable_detect = pdc2026x_cable_detect, }; |
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static const struct ide_dma_ops pdc2026x_dma_ops = { .dma_host_set = ide_dma_host_set, .dma_setup = ide_dma_setup, |
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.dma_start = pdc202xx_dma_start, .dma_end = pdc202xx_dma_end, |
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.dma_test_irq = ide_dma_test_irq, |
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.dma_lost_irq = ide_dma_lost_irq, |
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.dma_timer_expiry = ide_dma_sff_timer_expiry, |
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.dma_sff_read_status = ide_dma_sff_read_status, |
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}; |
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#define DECLARE_PDC2026X_DEV(udma, sectors) \ |
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{ \ |
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.name = DRV_NAME, \ |
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.init_chipset = init_chipset_pdc202xx, \ |
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.init_hwif = pdc2026x_init_hwif, \ |
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.port_ops = &pdc2026x_port_ops, \ |
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.dma_ops = &pdc2026x_dma_ops, \ |
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.host_flags = IDE_HFLAGS_PDC202XX, \ |
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.pio_mask = ATA_PIO4, \ .mwdma_mask = ATA_MWDMA2, \ .udma_mask = udma, \ |
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.max_sectors = sectors, \ |
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} |
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static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = { |
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{ /* 0: PDC20246 */ .name = DRV_NAME, |
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.init_chipset = init_chipset_pdc202xx, |
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.port_ops = &pdc20246_port_ops, |
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.dma_ops = &sff_dma_ops, |
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.host_flags = IDE_HFLAGS_PDC202XX, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA2, |
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}, |
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/* 1: PDC2026{2,3} */ DECLARE_PDC2026X_DEV(ATA_UDMA4, 0), |
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/* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */ DECLARE_PDC2026X_DEV(ATA_UDMA5, 256), |
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}; /** * pdc202xx_init_one - called when a PDC202xx is found * @dev: the pdc202xx device * @id: the matching pci id * * Called when the PCI registration layer (or the IDE initialization) * finds a device matching our IDE device tables. */ static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) { |
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const struct ide_port_info *d; |
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u8 idx = id->driver_data; d = &pdc202xx_chipsets[idx]; |
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if (idx < 2) |
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pdc202ata4_fixup_irq(dev, d->name); |
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if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) { |
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struct pci_dev *bridge = dev->bus->self; |
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if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL && (bridge->device == PCI_DEVICE_ID_INTEL_I960 || bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) { |
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printk(KERN_INFO DRV_NAME " %s: skipping Promise " |
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"PDC20265 attached to I2O RAID controller ", pci_name(dev)); |
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return -ENODEV; } } |
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return ide_pci_init_one(dev, d, NULL); |
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} |
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static const struct pci_device_id pdc202xx_pci_tbl[] = { { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, |
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{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, |
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{ 0, }, }; MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl); |
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static struct pci_driver pdc202xx_pci_driver = { |
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.name = "Promise_Old_IDE", .id_table = pdc202xx_pci_tbl, .probe = pdc202xx_init_one, |
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.remove = ide_pci_remove, |
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.suspend = ide_pci_suspend, .resume = ide_pci_resume, |
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}; |
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static int __init pdc202xx_ide_init(void) |
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{ |
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return ide_pci_register_driver(&pdc202xx_pci_driver); |
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} |
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static void __exit pdc202xx_ide_exit(void) { |
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pci_unregister_driver(&pdc202xx_pci_driver); |
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} |
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module_init(pdc202xx_ide_init); |
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module_exit(pdc202xx_ide_exit); |
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|
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MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz"); |
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MODULE_DESCRIPTION("PCI driver module for older Promise IDE"); MODULE_LICENSE("GPL"); |