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drivers/mailbox/omap-mailbox.c
21.6 KB
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// SPDX-License-Identifier: GPL-2.0 |
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/* * OMAP mailbox driver * |
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* Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
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* Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com |
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* |
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* Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
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* Suman Anna <s-anna@ti.com> |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/spinlock.h> #include <linux/mutex.h> |
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#include <linux/slab.h> |
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#include <linux/kfifo.h> #include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> #include <linux/pm_runtime.h> |
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#include <linux/omap-mailbox.h> |
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#include <linux/mailbox_controller.h> #include <linux/mailbox_client.h> |
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#include "mailbox.h" |
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#define MAILBOX_REVISION 0x000 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) #define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) #define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) #define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ OMAP2_MAILBOX_IRQSTATUS(u)) #define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ OMAP2_MAILBOX_IRQENABLE(u)) #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ : OMAP2_MAILBOX_IRQENABLE(u)) #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) |
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/* Interrupt register configuration types */ #define MBOX_INTR_CFG_TYPE1 0 #define MBOX_INTR_CFG_TYPE2 1 |
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struct omap_mbox_fifo { unsigned long msg; unsigned long fifo_stat; unsigned long msg_stat; |
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unsigned long irqenable; unsigned long irqstatus; |
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unsigned long irqdisable; |
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u32 intr_bit; |
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}; struct omap_mbox_queue { spinlock_t lock; struct kfifo fifo; struct work_struct work; |
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struct omap_mbox *mbox; bool full; }; |
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struct omap_mbox_match_data { u32 intr_type; }; |
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struct omap_mbox_device { struct device *dev; struct mutex cfg_lock; void __iomem *mbox_base; |
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u32 *irq_ctx; |
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u32 num_users; u32 num_fifos; |
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u32 intr_type; |
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struct omap_mbox **mboxes; |
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struct mbox_controller controller; |
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struct list_head elem; }; |
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struct omap_mbox_fifo_info { int tx_id; int tx_usr; int tx_irq; int rx_id; int rx_usr; int rx_irq; const char *name; |
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bool send_no_irq; |
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}; |
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struct omap_mbox { const char *name; int irq; |
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struct omap_mbox_queue *rxq; |
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struct device *dev; |
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struct omap_mbox_device *parent; |
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struct omap_mbox_fifo tx_fifo; struct omap_mbox_fifo rx_fifo; |
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u32 intr_type; |
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struct mbox_chan *chan; |
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bool send_no_irq; |
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}; |
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/* global variables for the mailbox devices */ static DEFINE_MUTEX(omap_mbox_devices_lock); static LIST_HEAD(omap_mbox_devices); |
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static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; module_param(mbox_kfifo_size, uint, S_IRUGO); MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); |
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static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan) { if (!chan || !chan->con_priv) return NULL; return (struct omap_mbox *)chan->con_priv; } |
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static inline unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) |
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{ |
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return __raw_readl(mdev->mbox_base + ofs); |
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} |
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static inline void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) |
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{ |
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__raw_writel(val, mdev->mbox_base + ofs); |
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} |
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/* Mailbox FIFO handle functions */ |
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static u32 mbox_fifo_read(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
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return mbox_read_reg(mbox->parent, fifo->msg); |
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} |
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static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
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mbox_write_reg(mbox->parent, msg, fifo->msg); |
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} |
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static int mbox_fifo_empty(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
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return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); |
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} |
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static int mbox_fifo_full(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
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return mbox_read_reg(mbox->parent, fifo->fifo_stat); |
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} /* Mailbox IRQ handle functions */ |
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static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? &mbox->tx_fifo : &mbox->rx_fifo; u32 bit = fifo->intr_bit; u32 irqstatus = fifo->irqstatus; |
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mbox_write_reg(mbox->parent, bit, irqstatus); |
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/* Flush posted write for irq status to avoid spurious interrupts */ |
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mbox_read_reg(mbox->parent, irqstatus); |
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} |
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static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? &mbox->tx_fifo : &mbox->rx_fifo; u32 bit = fifo->intr_bit; u32 irqenable = fifo->irqenable; u32 irqstatus = fifo->irqstatus; |
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u32 enable = mbox_read_reg(mbox->parent, irqenable); u32 status = mbox_read_reg(mbox->parent, irqstatus); |
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return (int)(enable & status & bit); |
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} |
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static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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u32 l; struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? &mbox->tx_fifo : &mbox->rx_fifo; u32 bit = fifo->intr_bit; u32 irqenable = fifo->irqenable; |
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l = mbox_read_reg(mbox->parent, irqenable); |
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l |= bit; |
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mbox_write_reg(mbox->parent, l, irqenable); |
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} |
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static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? &mbox->tx_fifo : &mbox->rx_fifo; u32 bit = fifo->intr_bit; u32 irqdisable = fifo->irqdisable; |
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/* * Read and update the interrupt configuration register for pre-OMAP4. * OMAP4 and later SoCs have a dedicated interrupt disabling register. */ |
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if (!mbox->intr_type) |
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bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; |
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mbox_write_reg(mbox->parent, bit, irqdisable); |
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} |
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void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
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if (WARN_ON(!mbox)) return; |
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_omap_mbox_enable_irq(mbox, irq); } EXPORT_SYMBOL(omap_mbox_enable_irq); |
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void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) { struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); if (WARN_ON(!mbox)) return; _omap_mbox_disable_irq(mbox, irq); |
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} |
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EXPORT_SYMBOL(omap_mbox_disable_irq); |
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/* * Message receiver(workqueue) */ static void mbox_rx_work(struct work_struct *work) { struct omap_mbox_queue *mq = container_of(work, struct omap_mbox_queue, work); |
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mbox_msg_t data; u32 msg; |
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int len; while (kfifo_len(&mq->fifo) >= sizeof(msg)) { len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); WARN_ON(len != sizeof(msg)); |
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data = msg; |
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mbox_chan_received_data(mq->mbox->chan, (void *)data); |
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spin_lock_irq(&mq->lock); if (mq->full) { mq->full = false; |
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_omap_mbox_enable_irq(mq->mbox, IRQ_RX); |
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} spin_unlock_irq(&mq->lock); |
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} } /* * Mailbox interrupt handler */ |
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static void __mbox_tx_interrupt(struct omap_mbox *mbox) { |
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_omap_mbox_disable_irq(mbox, IRQ_TX); |
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ack_mbox_irq(mbox, IRQ_TX); |
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mbox_chan_txdone(mbox->chan, 0); |
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} static void __mbox_rx_interrupt(struct omap_mbox *mbox) { |
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struct omap_mbox_queue *mq = mbox->rxq; |
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u32 msg; |
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int len; |
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while (!mbox_fifo_empty(mbox)) { |
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if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { |
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_omap_mbox_disable_irq(mbox, IRQ_RX); |
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mq->full = true; |
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goto nomem; |
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} |
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msg = mbox_fifo_read(mbox); |
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len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); WARN_ON(len != sizeof(msg)); |
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} /* no more messages in the fifo. clear IRQ source. */ ack_mbox_irq(mbox, IRQ_RX); |
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nomem: |
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schedule_work(&mbox->rxq->work); |
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} static irqreturn_t mbox_interrupt(int irq, void *p) { |
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struct omap_mbox *mbox = p; |
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if (is_mbox_irq(mbox, IRQ_TX)) __mbox_tx_interrupt(mbox); if (is_mbox_irq(mbox, IRQ_RX)) __mbox_rx_interrupt(mbox); return IRQ_HANDLED; } |
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static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
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void (*work)(struct work_struct *)) |
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{ |
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struct omap_mbox_queue *mq; |
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if (!work) return NULL; |
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mq = kzalloc(sizeof(*mq), GFP_KERNEL); |
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if (!mq) return NULL; spin_lock_init(&mq->lock); |
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if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) |
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goto error; |
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INIT_WORK(&mq->work, work); |
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return mq; |
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error: kfree(mq); return NULL; } static void mbox_queue_free(struct omap_mbox_queue *q) { |
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kfifo_free(&q->fifo); |
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kfree(q); } |
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static int omap_mbox_startup(struct omap_mbox *mbox) |
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{ |
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int ret = 0; |
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struct omap_mbox_queue *mq; |
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mq = mbox_queue_alloc(mbox, mbox_rx_work); if (!mq) return -ENOMEM; mbox->rxq = mq; mq->mbox = mbox; ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, mbox->name, mbox); if (unlikely(ret)) { pr_err("failed to register mailbox interrupt:%d ", ret); goto fail_request_irq; } |
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if (mbox->send_no_irq) mbox->chan->txdone_method = TXDONE_BY_ACK; |
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_omap_mbox_enable_irq(mbox, IRQ_RX); |
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return 0; |
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fail_request_irq: mbox_queue_free(mbox->rxq); |
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return ret; } static void omap_mbox_fini(struct omap_mbox *mbox) { |
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_omap_mbox_disable_irq(mbox, IRQ_RX); free_irq(mbox->irq, mbox); flush_work(&mbox->rxq->work); mbox_queue_free(mbox->rxq); |
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} |
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static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev, const char *mbox_name) |
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{ |
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struct omap_mbox *_mbox, *mbox = NULL; |
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struct omap_mbox **mboxes = mdev->mboxes; int i; |
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if (!mboxes) |
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return NULL; |
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for (i = 0; (_mbox = mboxes[i]); i++) { |
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if (!strcmp(_mbox->name, mbox_name)) { |
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mbox = _mbox; |
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break; |
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} } |
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return mbox; } |
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struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl, const char *chan_name) |
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{ |
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struct device *dev = cl->dev; |
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struct omap_mbox *mbox = NULL; struct omap_mbox_device *mdev; |
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struct mbox_chan *chan; unsigned long flags; |
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int ret; |
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if (!dev) return ERR_PTR(-ENODEV); if (dev->of_node) { pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage ", __func__); return ERR_PTR(-ENODEV); } |
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mutex_lock(&omap_mbox_devices_lock); list_for_each_entry(mdev, &omap_mbox_devices, elem) { |
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mbox = omap_mbox_device_find(mdev, chan_name); |
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if (mbox) break; } mutex_unlock(&omap_mbox_devices_lock); |
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if (!mbox || !mbox->chan) |
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return ERR_PTR(-ENOENT); |
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chan = mbox->chan; spin_lock_irqsave(&chan->lock, flags); chan->msg_free = 0; chan->msg_count = 0; chan->active_req = NULL; chan->cl = cl; init_completion(&chan->tx_complete); spin_unlock_irqrestore(&chan->lock, flags); |
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ret = chan->mbox->ops->startup(chan); |
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if (ret) { |
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pr_err("Unable to startup the chan (%d) ", ret); mbox_free_channel(chan); chan = ERR_PTR(ret); |
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} |
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return chan; |
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} |
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EXPORT_SYMBOL(omap_mbox_request_channel); |
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static struct class omap_mbox_class = { .name = "mbox", }; |
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static int omap_mbox_register(struct omap_mbox_device *mdev) |
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{ |
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int ret; int i; |
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struct omap_mbox **mboxes; |
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446 |
if (!mdev || !mdev->mboxes) |
340a614ac
|
447 |
return -EINVAL; |
340a614ac
|
448 |
|
72c1c8179
|
449 |
mboxes = mdev->mboxes; |
9c80c8cd7
|
450 451 |
for (i = 0; mboxes[i]; i++) { struct omap_mbox *mbox = mboxes[i]; |
2665a4c1d
|
452 |
|
8841a66aa
|
453 454 |
mbox->dev = device_create(&omap_mbox_class, mdev->dev, 0, mbox, "%s", mbox->name); |
9c80c8cd7
|
455 456 457 458 459 |
if (IS_ERR(mbox->dev)) { ret = PTR_ERR(mbox->dev); goto err_out; } } |
72c1c8179
|
460 461 462 463 |
mutex_lock(&omap_mbox_devices_lock); list_add(&mdev->elem, &omap_mbox_devices); mutex_unlock(&omap_mbox_devices_lock); |
a3abf4363
|
464 |
ret = devm_mbox_controller_register(mdev->dev, &mdev->controller); |
f48cca877
|
465 |
|
9c80c8cd7
|
466 |
err_out: |
8841a66aa
|
467 468 469 470 |
if (ret) { while (i--) device_unregister(mboxes[i]->dev); } |
340a614ac
|
471 472 |
return ret; } |
340a614ac
|
473 |
|
72c1c8179
|
474 |
static int omap_mbox_unregister(struct omap_mbox_device *mdev) |
340a614ac
|
475 |
{ |
9c80c8cd7
|
476 |
int i; |
72c1c8179
|
477 |
struct omap_mbox **mboxes; |
340a614ac
|
478 |
|
72c1c8179
|
479 |
if (!mdev || !mdev->mboxes) |
9c80c8cd7
|
480 |
return -EINVAL; |
72c1c8179
|
481 482 483 484 485 |
mutex_lock(&omap_mbox_devices_lock); list_del(&mdev->elem); mutex_unlock(&omap_mbox_devices_lock); mboxes = mdev->mboxes; |
9c80c8cd7
|
486 487 |
for (i = 0; mboxes[i]; i++) device_unregister(mboxes[i]->dev); |
9c80c8cd7
|
488 |
return 0; |
340a614ac
|
489 |
} |
5040f5343
|
490 |
|
8841a66aa
|
491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 |
static int omap_mbox_chan_startup(struct mbox_chan *chan) { struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); struct omap_mbox_device *mdev = mbox->parent; int ret = 0; mutex_lock(&mdev->cfg_lock); pm_runtime_get_sync(mdev->dev); ret = omap_mbox_startup(mbox); if (ret) pm_runtime_put_sync(mdev->dev); mutex_unlock(&mdev->cfg_lock); return ret; } static void omap_mbox_chan_shutdown(struct mbox_chan *chan) { struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); struct omap_mbox_device *mdev = mbox->parent; mutex_lock(&mdev->cfg_lock); omap_mbox_fini(mbox); pm_runtime_put_sync(mdev->dev); mutex_unlock(&mdev->cfg_lock); } |
9c1f2a5dc
|
516 |
static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg) |
8841a66aa
|
517 |
{ |
8841a66aa
|
518 |
int ret = -EBUSY; |
8e3c59521
|
519 520 |
if (!mbox_fifo_full(mbox)) { _omap_mbox_enable_irq(mbox, IRQ_RX); |
9c1f2a5dc
|
521 |
mbox_fifo_write(mbox, msg); |
8e3c59521
|
522 523 524 525 526 527 528 529 530 531 |
ret = 0; _omap_mbox_disable_irq(mbox, IRQ_RX); /* we must read and ack the interrupt directly from here */ mbox_fifo_read(mbox); ack_mbox_irq(mbox, IRQ_RX); } return ret; } |
9c1f2a5dc
|
532 |
static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg) |
8e3c59521
|
533 534 |
{ int ret = -EBUSY; |
8841a66aa
|
535 536 |
if (!mbox_fifo_full(mbox)) { |
9c1f2a5dc
|
537 |
mbox_fifo_write(mbox, msg); |
8841a66aa
|
538 539 540 541 542 543 544 |
ret = 0; } /* always enable the interrupt */ _omap_mbox_enable_irq(mbox, IRQ_TX); return ret; } |
8e3c59521
|
545 546 547 548 |
static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) { struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); int ret; |
9c1f2a5dc
|
549 |
u32 msg = omap_mbox_message(data); |
8e3c59521
|
550 551 552 553 554 |
if (!mbox) return -EINVAL; if (mbox->send_no_irq) |
9c1f2a5dc
|
555 |
ret = omap_mbox_chan_send_noirq(mbox, msg); |
8e3c59521
|
556 |
else |
9c1f2a5dc
|
557 |
ret = omap_mbox_chan_send(mbox, msg); |
8e3c59521
|
558 559 560 |
return ret; } |
05ae79756
|
561 |
static const struct mbox_chan_ops omap_mbox_chan_ops = { |
8841a66aa
|
562 563 564 565 |
.startup = omap_mbox_chan_startup, .send_data = omap_mbox_chan_send_data, .shutdown = omap_mbox_chan_shutdown, }; |
af1d2f5cb
|
566 567 568 569 |
#ifdef CONFIG_PM_SLEEP static int omap_mbox_suspend(struct device *dev) { struct omap_mbox_device *mdev = dev_get_drvdata(dev); |
9f0cee984
|
570 |
u32 usr, fifo, reg; |
af1d2f5cb
|
571 572 573 |
if (pm_runtime_status_suspended(dev)) return 0; |
9f0cee984
|
574 575 576 577 578 579 580 581 |
for (fifo = 0; fifo < mdev->num_fifos; fifo++) { if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) { dev_err(mdev->dev, "fifo %d has unexpected unread messages ", fifo); return -EBUSY; } } |
af1d2f5cb
|
582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 |
for (usr = 0; usr < mdev->num_users; usr++) { reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg); } return 0; } static int omap_mbox_resume(struct device *dev) { struct omap_mbox_device *mdev = dev_get_drvdata(dev); u32 usr, reg; if (pm_runtime_status_suspended(dev)) return 0; for (usr = 0; usr < mdev->num_users; usr++) { reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); mbox_write_reg(mdev, mdev->irq_ctx[usr], reg); } return 0; } #endif static const struct dev_pm_ops omap_mbox_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume) }; |
ea2ec1e80
|
610 611 |
static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 }; static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 }; |
75288cc66
|
612 613 614 |
static const struct of_device_id omap_mailbox_of_match[] = { { .compatible = "ti,omap2-mailbox", |
ea2ec1e80
|
615 |
.data = &omap2_data, |
75288cc66
|
616 617 618 |
}, { .compatible = "ti,omap3-mailbox", |
ea2ec1e80
|
619 |
.data = &omap2_data, |
75288cc66
|
620 621 622 |
}, { .compatible = "ti,omap4-mailbox", |
ea2ec1e80
|
623 |
.data = &omap4_data, |
75288cc66
|
624 625 |
}, { |
9c1f2a5dc
|
626 627 628 629 |
.compatible = "ti,am654-mailbox", .data = &omap4_data, }, { |
75288cc66
|
630 631 632 633 |
/* end */ }, }; MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); |
8841a66aa
|
634 635 636 637 638 639 640 641 642 643 |
static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, const struct of_phandle_args *sp) { phandle phandle = sp->args[0]; struct device_node *node; struct omap_mbox_device *mdev; struct omap_mbox *mbox; mdev = container_of(controller, struct omap_mbox_device, controller); if (WARN_ON(!mdev)) |
2d805fc1c
|
644 |
return ERR_PTR(-EINVAL); |
8841a66aa
|
645 646 647 648 649 650 |
node = of_find_node_by_phandle(phandle); if (!node) { pr_err("%s: could not find node phandle 0x%x ", __func__, phandle); |
2d805fc1c
|
651 |
return ERR_PTR(-ENODEV); |
8841a66aa
|
652 653 654 655 |
} mbox = omap_mbox_device_find(mdev, node->name); of_node_put(node); |
2d805fc1c
|
656 |
return mbox ? mbox->chan : ERR_PTR(-ENOENT); |
8841a66aa
|
657 |
} |
5040f5343
|
658 659 660 661 |
static int omap_mbox_probe(struct platform_device *pdev) { struct resource *mem; int ret; |
8841a66aa
|
662 |
struct mbox_chan *chnls; |
5040f5343
|
663 |
struct omap_mbox **list, *mbox, *mboxblk; |
75288cc66
|
664 |
struct omap_mbox_fifo_info *finfo, *finfoblk; |
72c1c8179
|
665 |
struct omap_mbox_device *mdev; |
be3322eb7
|
666 |
struct omap_mbox_fifo *fifo; |
75288cc66
|
667 668 |
struct device_node *node = pdev->dev.of_node; struct device_node *child; |
ea2ec1e80
|
669 |
const struct omap_mbox_match_data *match_data; |
75288cc66
|
670 671 672 |
u32 intr_type, info_count; u32 num_users, num_fifos; u32 tmp[3]; |
5040f5343
|
673 674 |
u32 l; int i; |
4899f78a3
|
675 676 677 |
if (!node) { pr_err("%s: only DT-based devices are supported ", __func__); |
5040f5343
|
678 679 |
return -ENODEV; } |
ea2ec1e80
|
680 681 |
match_data = of_device_get_match_data(&pdev->dev); if (!match_data) |
4899f78a3
|
682 |
return -ENODEV; |
ea2ec1e80
|
683 |
intr_type = match_data->intr_type; |
75288cc66
|
684 |
|
4899f78a3
|
685 686 |
if (of_property_read_u32(node, "ti,mbox-num-users", &num_users)) return -ENODEV; |
75288cc66
|
687 |
|
4899f78a3
|
688 689 |
if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos)) return -ENODEV; |
75288cc66
|
690 |
|
4899f78a3
|
691 692 693 694 695 |
info_count = of_get_available_child_count(node); if (!info_count) { dev_err(&pdev->dev, "no available mbox devices found "); return -ENODEV; |
75288cc66
|
696 |
} |
a86854d0c
|
697 |
finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk), |
75288cc66
|
698 699 700 701 702 703 704 |
GFP_KERNEL); if (!finfoblk) return -ENOMEM; finfo = finfoblk; child = NULL; for (i = 0; i < info_count; i++, finfo++) { |
4899f78a3
|
705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 |
child = of_get_next_available_child(node, child); ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp, ARRAY_SIZE(tmp)); if (ret) return ret; finfo->tx_id = tmp[0]; finfo->tx_irq = tmp[1]; finfo->tx_usr = tmp[2]; ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp, ARRAY_SIZE(tmp)); if (ret) return ret; finfo->rx_id = tmp[0]; finfo->rx_irq = tmp[1]; finfo->rx_usr = tmp[2]; finfo->name = child->name; if (of_find_property(child, "ti,mbox-send-noirq", NULL)) finfo->send_no_irq = true; |
75288cc66
|
726 727 728 729 |
if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos || finfo->tx_usr >= num_users || finfo->rx_usr >= num_users) return -EINVAL; } |
72c1c8179
|
730 731 732 733 734 735 736 737 |
mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); if (!mdev) return -ENOMEM; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(mdev->mbox_base)) return PTR_ERR(mdev->mbox_base); |
a86854d0c
|
738 |
mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32), |
af1d2f5cb
|
739 740 741 |
GFP_KERNEL); if (!mdev->irq_ctx) return -ENOMEM; |
5040f5343
|
742 |
/* allocate one extra for marking end of list */ |
a86854d0c
|
743 |
list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list), |
5040f5343
|
744 745 746 |
GFP_KERNEL); if (!list) return -ENOMEM; |
a86854d0c
|
747 |
chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls), |
8841a66aa
|
748 749 750 |
GFP_KERNEL); if (!chnls) return -ENOMEM; |
a86854d0c
|
751 |
mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox), |
5040f5343
|
752 753 754 |
GFP_KERNEL); if (!mboxblk) return -ENOMEM; |
5040f5343
|
755 |
mbox = mboxblk; |
75288cc66
|
756 757 |
finfo = finfoblk; for (i = 0; i < info_count; i++, finfo++) { |
be3322eb7
|
758 |
fifo = &mbox->tx_fifo; |
75288cc66
|
759 760 761 762 763 764 |
fifo->msg = MAILBOX_MESSAGE(finfo->tx_id); fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id); fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id); fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr); fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr); fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr); |
be3322eb7
|
765 766 |
fifo = &mbox->rx_fifo; |
75288cc66
|
767 768 769 770 771 772 |
fifo->msg = MAILBOX_MESSAGE(finfo->rx_id); fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id); fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id); fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr); fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr); fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr); |
be3322eb7
|
773 |
|
8e3c59521
|
774 |
mbox->send_no_irq = finfo->send_no_irq; |
be3322eb7
|
775 |
mbox->intr_type = intr_type; |
72c1c8179
|
776 |
mbox->parent = mdev; |
75288cc66
|
777 778 |
mbox->name = finfo->name; mbox->irq = platform_get_irq(pdev, finfo->tx_irq); |
5040f5343
|
779 780 |
if (mbox->irq < 0) return mbox->irq; |
8841a66aa
|
781 782 |
mbox->chan = &chnls[i]; chnls[i].con_priv = mbox; |
5040f5343
|
783 784 |
list[i] = mbox++; } |
72c1c8179
|
785 786 |
mutex_init(&mdev->cfg_lock); mdev->dev = &pdev->dev; |
75288cc66
|
787 788 |
mdev->num_users = num_users; mdev->num_fifos = num_fifos; |
2240f8aef
|
789 |
mdev->intr_type = intr_type; |
72c1c8179
|
790 |
mdev->mboxes = list; |
8841a66aa
|
791 |
|
9c1f2a5dc
|
792 793 794 795 |
/* * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready * IRQ and is needed to run the Tx state machine */ |
8841a66aa
|
796 797 798 799 800 801 |
mdev->controller.txdone_irq = true; mdev->controller.dev = mdev->dev; mdev->controller.ops = &omap_mbox_chan_ops; mdev->controller.chans = chnls; mdev->controller.num_chans = info_count; mdev->controller.of_xlate = omap_mbox_of_xlate; |
72c1c8179
|
802 |
ret = omap_mbox_register(mdev); |
5040f5343
|
803 804 |
if (ret) return ret; |
72c1c8179
|
805 806 |
platform_set_drvdata(pdev, mdev); pm_runtime_enable(mdev->dev); |
5040f5343
|
807 |
|
72c1c8179
|
808 |
ret = pm_runtime_get_sync(mdev->dev); |
5040f5343
|
809 |
if (ret < 0) { |
72c1c8179
|
810 |
pm_runtime_put_noidle(mdev->dev); |
5040f5343
|
811 812 813 814 815 816 817 |
goto unregister; } /* * just print the raw revision register, the format is not * uniform across all SoCs */ |
72c1c8179
|
818 819 820 |
l = mbox_read_reg(mdev, MAILBOX_REVISION); dev_info(mdev->dev, "omap mailbox rev 0x%x ", l); |
5040f5343
|
821 |
|
72c1c8179
|
822 |
ret = pm_runtime_put_sync(mdev->dev); |
5040f5343
|
823 824 |
if (ret < 0) goto unregister; |
75288cc66
|
825 |
devm_kfree(&pdev->dev, finfoblk); |
5040f5343
|
826 827 828 |
return 0; unregister: |
72c1c8179
|
829 830 |
pm_runtime_disable(mdev->dev); omap_mbox_unregister(mdev); |
5040f5343
|
831 832 833 834 835 |
return ret; } static int omap_mbox_remove(struct platform_device *pdev) { |
72c1c8179
|
836 837 838 839 |
struct omap_mbox_device *mdev = platform_get_drvdata(pdev); pm_runtime_disable(mdev->dev); omap_mbox_unregister(mdev); |
5040f5343
|
840 841 842 843 844 845 846 847 848 |
return 0; } static struct platform_driver omap_mbox_driver = { .probe = omap_mbox_probe, .remove = omap_mbox_remove, .driver = { .name = "omap-mailbox", |
af1d2f5cb
|
849 |
.pm = &omap_mbox_pm_ops, |
75288cc66
|
850 |
.of_match_table = of_match_ptr(omap_mailbox_of_match), |
5040f5343
|
851 852 |
}, }; |
340a614ac
|
853 |
|
c7c158e57
|
854 |
static int __init omap_mbox_init(void) |
340a614ac
|
855 |
{ |
6b2339859
|
856 857 858 859 860 |
int err; err = class_register(&omap_mbox_class); if (err) return err; |
b5bebe410
|
861 |
/* kfifo size sanity check: alignment and minimal size */ |
9c1f2a5dc
|
862 863 |
mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32)); mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32)); |
b5bebe410
|
864 |
|
1f90a2162
|
865 866 867 868 869 |
err = platform_driver_register(&omap_mbox_driver); if (err) class_unregister(&omap_mbox_class); return err; |
340a614ac
|
870 |
} |
6b2339859
|
871 |
subsys_initcall(omap_mbox_init); |
340a614ac
|
872 |
|
c7c158e57
|
873 |
static void __exit omap_mbox_exit(void) |
340a614ac
|
874 |
{ |
5040f5343
|
875 |
platform_driver_unregister(&omap_mbox_driver); |
6b2339859
|
876 |
class_unregister(&omap_mbox_class); |
340a614ac
|
877 |
} |
c7c158e57
|
878 |
module_exit(omap_mbox_exit); |
340a614ac
|
879 |
|
f48cca877
|
880 881 |
MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); |
f375325a0
|
882 883 |
MODULE_AUTHOR("Toshihiro Kobayashi"); MODULE_AUTHOR("Hiroshi DOYU"); |