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drivers/dma/coh901318.c
39 KB
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/* * driver/dma/coh901318.c * * Copyright (C) 2007-2009 ST-Ericsson * License terms: GNU General Public License (GPL) version 2 * DMA driver for COH 901 318 * Author: Per Friden <per.friden@stericsson.com> */ #include <linux/init.h> #include <linux/module.h> #include <linux/kernel.h> /* printk() */ #include <linux/fs.h> /* everything... */ |
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#include <linux/scatterlist.h> |
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#include <linux/slab.h> /* kmalloc() */ #include <linux/dmaengine.h> #include <linux/platform_device.h> #include <linux/device.h> #include <linux/irqreturn.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/uaccess.h> #include <linux/debugfs.h> #include <mach/coh901318.h> #include "coh901318_lli.h" #define COHC_2_DEV(cohc) (&cohc->chan.dev->device) #ifdef VERBOSE_DEBUG #define COH_DBG(x) ({ if (1) x; 0; }) #else #define COH_DBG(x) ({ if (0) x; 0; }) #endif struct coh901318_desc { struct dma_async_tx_descriptor desc; struct list_head node; struct scatterlist *sg; unsigned int sg_len; |
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struct coh901318_lli *lli; |
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enum dma_data_direction dir; |
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unsigned long flags; |
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u32 head_config; u32 head_ctrl; |
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}; struct coh901318_base { struct device *dev; void __iomem *virtbase; struct coh901318_pool pool; struct powersave pm; struct dma_device dma_slave; struct dma_device dma_memcpy; struct coh901318_chan *chans; struct coh901318_platform *platform; }; struct coh901318_chan { spinlock_t lock; int allocated; int completed; int id; int stopped; struct work_struct free_work; struct dma_chan chan; struct tasklet_struct tasklet; struct list_head active; struct list_head queue; struct list_head free; unsigned long nbr_active_done; unsigned long busy; |
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|
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u32 runtime_addr; u32 runtime_ctrl; |
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struct coh901318_base *base; }; static void coh901318_list_print(struct coh901318_chan *cohc, struct coh901318_lli *lli) { |
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struct coh901318_lli *l = lli; |
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int i = 0; |
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while (l) { |
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dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x" |
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", dst 0x%x, link 0x%x virt_link_addr 0x%p ", |
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i, l, l->control, l->src_addr, l->dst_addr, |
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l->link_addr, l->virt_link_addr); |
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i++; |
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l = l->virt_link_addr; |
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} } #ifdef CONFIG_DEBUG_FS #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y) static struct coh901318_base *debugfs_dma_base; static struct dentry *dma_dentry; static int coh901318_debugfs_open(struct inode *inode, struct file *file) { file->private_data = inode->i_private; return 0; } static int coh901318_debugfs_read(struct file *file, char __user *buf, size_t count, loff_t *f_pos) { u64 started_channels = debugfs_dma_base->pm.started_channels; int pool_count = debugfs_dma_base->pool.debugfs_pool_counter; int i; int ret = 0; char *dev_buf; char *tmp; int dev_size; dev_buf = kmalloc(4*1024, GFP_KERNEL); if (dev_buf == NULL) goto err_kmalloc; tmp = dev_buf; |
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tmp += sprintf(tmp, "DMA -- enabled dma channels "); |
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for (i = 0; i < debugfs_dma_base->platform->max_channels; i++) if (started_channels & (1 << i)) tmp += sprintf(tmp, "channel %d ", i); tmp += sprintf(tmp, "Pool alloc nbr %d ", pool_count); dev_size = tmp - dev_buf; /* No more to read if offset != 0 */ if (*f_pos > dev_size) goto out; if (count > dev_size - *f_pos) count = dev_size - *f_pos; if (copy_to_user(buf, dev_buf + *f_pos, count)) ret = -EINVAL; ret = count; *f_pos += count; out: kfree(dev_buf); return ret; err_kmalloc: return 0; } static const struct file_operations coh901318_debugfs_status_operations = { .owner = THIS_MODULE, .open = coh901318_debugfs_open, .read = coh901318_debugfs_read, |
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.llseek = default_llseek, |
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}; static int __init init_coh901318_debugfs(void) { dma_dentry = debugfs_create_dir("dma", NULL); (void) debugfs_create_file("status", S_IFREG | S_IRUGO, dma_dentry, NULL, &coh901318_debugfs_status_operations); return 0; } static void __exit exit_coh901318_debugfs(void) { debugfs_remove_recursive(dma_dentry); } module_init(init_coh901318_debugfs); module_exit(exit_coh901318_debugfs); #else #define COH901318_DEBUGFS_ASSIGN(x, y) #endif /* CONFIG_DEBUG_FS */ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan) { return container_of(chan, struct coh901318_chan, chan); } static inline dma_addr_t cohc_dev_addr(struct coh901318_chan *cohc) { |
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/* Runtime supplied address will take precedence */ if (cohc->runtime_addr) return cohc->runtime_addr; |
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return cohc->base->platform->chan_conf[cohc->id].dev_addr; } static inline const struct coh901318_params * cohc_chan_param(struct coh901318_chan *cohc) { return &cohc->base->platform->chan_conf[cohc->id].param; } static inline const struct coh_dma_channel * cohc_chan_conf(struct coh901318_chan *cohc) { return &cohc->base->platform->chan_conf[cohc->id]; } static void enable_powersave(struct coh901318_chan *cohc) { unsigned long flags; struct powersave *pm = &cohc->base->pm; spin_lock_irqsave(&pm->lock, flags); pm->started_channels &= ~(1ULL << cohc->id); if (!pm->started_channels) { /* DMA no longer intends to access memory */ cohc->base->platform->access_memory_state(cohc->base->dev, false); } spin_unlock_irqrestore(&pm->lock, flags); } static void disable_powersave(struct coh901318_chan *cohc) { unsigned long flags; struct powersave *pm = &cohc->base->pm; spin_lock_irqsave(&pm->lock, flags); if (!pm->started_channels) { /* DMA intends to access memory */ cohc->base->platform->access_memory_state(cohc->base->dev, true); } pm->started_channels |= (1ULL << cohc->id); spin_unlock_irqrestore(&pm->lock, flags); } static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control) { int channel = cohc->id; void __iomem *virtbase = cohc->base->virtbase; writel(control, virtbase + COH901318_CX_CTRL + COH901318_CX_CTRL_SPACING * channel); return 0; } static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf) { int channel = cohc->id; void __iomem *virtbase = cohc->base->virtbase; writel(conf, virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING*channel); return 0; } static int coh901318_start(struct coh901318_chan *cohc) { u32 val; int channel = cohc->id; void __iomem *virtbase = cohc->base->virtbase; disable_powersave(cohc); val = readl(virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING * channel); /* Enable channel */ val |= COH901318_CX_CFG_CH_ENABLE; writel(val, virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING * channel); return 0; } static int coh901318_prep_linked_list(struct coh901318_chan *cohc, |
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struct coh901318_lli *lli) |
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{ int channel = cohc->id; void __iomem *virtbase = cohc->base->virtbase; BUG_ON(readl(virtbase + COH901318_CX_STAT + COH901318_CX_STAT_SPACING*channel) & COH901318_CX_STAT_ACTIVE); |
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writel(lli->src_addr, |
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virtbase + COH901318_CX_SRC_ADDR + COH901318_CX_SRC_ADDR_SPACING * channel); |
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writel(lli->dst_addr, virtbase + |
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COH901318_CX_DST_ADDR + COH901318_CX_DST_ADDR_SPACING * channel); |
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writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR + |
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COH901318_CX_LNK_ADDR_SPACING * channel); |
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writel(lli->control, virtbase + COH901318_CX_CTRL + |
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COH901318_CX_CTRL_SPACING * channel); return 0; } static dma_cookie_t coh901318_assign_cookie(struct coh901318_chan *cohc, struct coh901318_desc *cohd) { dma_cookie_t cookie = cohc->chan.cookie; if (++cookie < 0) cookie = 1; cohc->chan.cookie = cookie; cohd->desc.cookie = cookie; return cookie; } static struct coh901318_desc * coh901318_desc_get(struct coh901318_chan *cohc) { struct coh901318_desc *desc; if (list_empty(&cohc->free)) { /* alloc new desc because we're out of used ones * TODO: alloc a pile of descs instead of just one, * avoid many small allocations. */ |
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desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT); |
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if (desc == NULL) goto out; INIT_LIST_HEAD(&desc->node); |
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dma_async_tx_descriptor_init(&desc->desc, &cohc->chan); |
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} else { /* Reuse an old desc. */ desc = list_first_entry(&cohc->free, struct coh901318_desc, node); list_del(&desc->node); |
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/* Initialize it a bit so it's not insane */ desc->sg = NULL; desc->sg_len = 0; desc->desc.callback = NULL; desc->desc.callback_param = NULL; |
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} out: return desc; } static void coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd) { list_add_tail(&cohd->node, &cohc->free); } /* call with irq lock held */ static void coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc) { list_add_tail(&desc->node, &cohc->active); |
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} static struct coh901318_desc * coh901318_first_active_get(struct coh901318_chan *cohc) { struct coh901318_desc *d; if (list_empty(&cohc->active)) return NULL; d = list_first_entry(&cohc->active, struct coh901318_desc, node); return d; } static void coh901318_desc_remove(struct coh901318_desc *cohd) { list_del(&cohd->node); } static void coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc) { list_add_tail(&desc->node, &cohc->queue); } static struct coh901318_desc * coh901318_first_queued(struct coh901318_chan *cohc) { struct coh901318_desc *d; if (list_empty(&cohc->queue)) return NULL; d = list_first_entry(&cohc->queue, struct coh901318_desc, node); return d; } |
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static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli) { struct coh901318_lli *lli = in_lli; u32 bytes = 0; while (lli) { bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK; lli = lli->virt_link_addr; } return bytes; } |
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/* |
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* Get the number of bytes left to transfer on this channel, * it is unwise to call this before stopping the channel for * absolute measures, but for a rough guess you can still call * it. |
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*/ |
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static u32 coh901318_get_bytes_left(struct dma_chan *chan) |
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{ |
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struct coh901318_chan *cohc = to_coh901318_chan(chan); |
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struct coh901318_desc *cohd; struct list_head *pos; unsigned long flags; u32 left = 0; int i = 0; |
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spin_lock_irqsave(&cohc->lock, flags); |
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/* * If there are many queued jobs, we iterate and add the * size of them all. We take a special look on the first * job though, since it is probably active. */ list_for_each(pos, &cohc->active) { /* * The first job in the list will be working on the * hardware. The job can be stopped but still active, * so that the transfer counter is somewhere inside * the buffer. */ cohd = list_entry(pos, struct coh901318_desc, node); if (i == 0) { struct coh901318_lli *lli; dma_addr_t ladd; /* Read current transfer count value */ left = readl(cohc->base->virtbase + COH901318_CX_CTRL + COH901318_CX_CTRL_SPACING * cohc->id) & COH901318_CX_CTRL_TC_VALUE_MASK; /* See if the transfer is linked... */ ladd = readl(cohc->base->virtbase + COH901318_CX_LNK_ADDR + COH901318_CX_LNK_ADDR_SPACING * cohc->id) & ~COH901318_CX_LNK_LINK_IMMEDIATE; /* Single transaction */ if (!ladd) continue; /* * Linked transaction, follow the lli, find the * currently processing lli, and proceed to the next */ lli = cohd->lli; while (lli && lli->link_addr != ladd) lli = lli->virt_link_addr; if (lli) lli = lli->virt_link_addr; /* * Follow remaining lli links around to count the total * number of bytes left */ left += coh901318_get_bytes_in_lli(lli); } else { left += coh901318_get_bytes_in_lli(cohd->lli); } i++; } /* Also count bytes in the queued jobs */ list_for_each(pos, &cohc->queue) { cohd = list_entry(pos, struct coh901318_desc, node); left += coh901318_get_bytes_in_lli(cohd->lli); } |
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spin_unlock_irqrestore(&cohc->lock, flags); |
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return left; |
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} |
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/* * Pauses a transfer without losing data. Enables power save. * Use this function in conjunction with coh901318_resume. */ static void coh901318_pause(struct dma_chan *chan) |
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{ u32 val; unsigned long flags; struct coh901318_chan *cohc = to_coh901318_chan(chan); int channel = cohc->id; void __iomem *virtbase = cohc->base->virtbase; spin_lock_irqsave(&cohc->lock, flags); /* Disable channel in HW */ val = readl(virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING * channel); |
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/* Stopping infinite transfer */ |
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if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 && (val & COH901318_CX_CFG_CH_ENABLE)) cohc->stopped = 1; val &= ~COH901318_CX_CFG_CH_ENABLE; /* Enable twice, HW bug work around */ writel(val, virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING * channel); writel(val, virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING * channel); /* Spin-wait for it to actually go inactive */ while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING * channel) & COH901318_CX_STAT_ACTIVE) cpu_relax(); /* Check if we stopped an active job */ if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING * channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0) cohc->stopped = 1; enable_powersave(cohc); spin_unlock_irqrestore(&cohc->lock, flags); } |
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/* Resumes a transfer that has been stopped via 300_dma_stop(..). |
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Power save is handled. */ |
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static void coh901318_resume(struct dma_chan *chan) |
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{ u32 val; unsigned long flags; struct coh901318_chan *cohc = to_coh901318_chan(chan); int channel = cohc->id; spin_lock_irqsave(&cohc->lock, flags); disable_powersave(cohc); if (cohc->stopped) { /* Enable channel in HW */ val = readl(cohc->base->virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING * channel); val |= COH901318_CX_CFG_CH_ENABLE; writel(val, cohc->base->virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING*channel); cohc->stopped = 0; } spin_unlock_irqrestore(&cohc->lock, flags); } |
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bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) { unsigned int ch_nr = (unsigned int) chan_id; if (ch_nr == to_coh901318_chan(chan)->id) return true; return false; } EXPORT_SYMBOL(coh901318_filter_id); /* * DMA channel allocation */ static int coh901318_config(struct coh901318_chan *cohc, struct coh901318_params *param) { unsigned long flags; const struct coh901318_params *p; int channel = cohc->id; void __iomem *virtbase = cohc->base->virtbase; spin_lock_irqsave(&cohc->lock, flags); if (param) p = param; else p = &cohc->base->platform->chan_conf[channel].param; /* Clear any pending BE or TC interrupt */ if (channel < 32) { writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1); writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1); } else { writel(1 << (channel - 32), virtbase + COH901318_BE_INT_CLEAR2); writel(1 << (channel - 32), virtbase + COH901318_TC_INT_CLEAR2); } coh901318_set_conf(cohc, p->config); coh901318_set_ctrl(cohc, p->ctrl_lli_last); spin_unlock_irqrestore(&cohc->lock, flags); return 0; } /* must lock when calling this function * start queued jobs, if any * TODO: start all queued jobs in one go * * Returns descriptor if queued job is started otherwise NULL. * If the queue is empty NULL is returned. */ static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc) { |
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struct coh901318_desc *cohd; |
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/* * start queued jobs, if any |
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* TODO: transmit all queued jobs in one go */ |
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cohd = coh901318_first_queued(cohc); |
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if (cohd != NULL) { |
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/* Remove from queue */ |
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coh901318_desc_remove(cohd); |
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/* initiate DMA job */ cohc->busy = 1; |
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coh901318_desc_submit(cohc, cohd); |
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/* Program the transaction head */ coh901318_set_conf(cohc, cohd->head_config); coh901318_set_ctrl(cohc, cohd->head_ctrl); |
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coh901318_prep_linked_list(cohc, cohd->lli); |
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/* start dma job on this channel */ |
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coh901318_start(cohc); } |
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return cohd; |
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} |
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/* * This tasklet is called from the interrupt handler to * handle each descriptor (DMA job) that is sent to a channel. */ |
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static void dma_tasklet(unsigned long data) { struct coh901318_chan *cohc = (struct coh901318_chan *) data; struct coh901318_desc *cohd_fin; unsigned long flags; dma_async_tx_callback callback; void *callback_param; |
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dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d" " nbr_active_done %ld ", __func__, cohc->id, cohc->nbr_active_done); |
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spin_lock_irqsave(&cohc->lock, flags); |
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/* get first active descriptor entry from list */ |
61f135b92 Add COH 901 318 D... |
685 |
cohd_fin = coh901318_first_active_get(cohc); |
61f135b92 Add COH 901 318 D... |
686 687 |
if (cohd_fin == NULL) goto err; |
0b58828c9 DMAENGINE: COH 90... |
688 689 690 |
/* locate callback to client */ callback = cohd_fin->desc.callback; callback_param = cohd_fin->desc.callback_param; |
61f135b92 Add COH 901 318 D... |
691 |
|
0b58828c9 DMAENGINE: COH 90... |
692 693 |
/* sign this job as completed on the channel */ cohc->completed = cohd_fin->desc.cookie; |
61f135b92 Add COH 901 318 D... |
694 |
|
0b58828c9 DMAENGINE: COH 90... |
695 |
/* release the lli allocation and remove the descriptor */ |
cecd87da8 DMAENGINE: COH 90... |
696 |
coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli); |
61f135b92 Add COH 901 318 D... |
697 |
|
0b58828c9 DMAENGINE: COH 90... |
698 699 700 |
/* return desc to free-list */ coh901318_desc_remove(cohd_fin); coh901318_desc_free(cohc, cohd_fin); |
61f135b92 Add COH 901 318 D... |
701 |
|
0b58828c9 DMAENGINE: COH 90... |
702 |
spin_unlock_irqrestore(&cohc->lock, flags); |
61f135b92 Add COH 901 318 D... |
703 |
|
0b58828c9 DMAENGINE: COH 90... |
704 705 706 |
/* Call the callback when we're done */ if (callback) callback(callback_param); |
61f135b92 Add COH 901 318 D... |
707 |
|
0b58828c9 DMAENGINE: COH 90... |
708 |
spin_lock_irqsave(&cohc->lock, flags); |
61f135b92 Add COH 901 318 D... |
709 |
|
848ad1212 DMAENGINE: COH 90... |
710 711 712 713 714 715 716 |
/* * If another interrupt fired while the tasklet was scheduling, * we don't get called twice, so we have this number of active * counter that keep track of the number of IRQs expected to * be handled for this channel. If there happen to be more than * one IRQ to be ack:ed, we simply schedule this tasklet again. */ |
0b58828c9 DMAENGINE: COH 90... |
717 |
cohc->nbr_active_done--; |
61f135b92 Add COH 901 318 D... |
718 |
if (cohc->nbr_active_done) { |
848ad1212 DMAENGINE: COH 90... |
719 720 721 |
dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs " "came in while we were scheduling this tasklet "); |
61f135b92 Add COH 901 318 D... |
722 723 724 725 726 |
if (cohc_chan_conf(cohc)->priority_high) tasklet_hi_schedule(&cohc->tasklet); else tasklet_schedule(&cohc->tasklet); } |
61f135b92 Add COH 901 318 D... |
727 |
|
0b58828c9 DMAENGINE: COH 90... |
728 |
spin_unlock_irqrestore(&cohc->lock, flags); |
61f135b92 Add COH 901 318 D... |
729 730 731 732 733 734 735 736 737 738 739 740 741 |
return; err: spin_unlock_irqrestore(&cohc->lock, flags); dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc ", __func__); } /* called from interrupt context */ static void dma_tc_handle(struct coh901318_chan *cohc) { |
cecd87da8 DMAENGINE: COH 90... |
742 743 744 745 746 747 748 749 |
/* * If the channel is not allocated, then we shouldn't have * any TC interrupts on it. */ if (!cohc->allocated) { dev_err(COHC_2_DEV(cohc), "spurious interrupt from " "unallocated channel "); |
61f135b92 Add COH 901 318 D... |
750 |
return; |
cecd87da8 DMAENGINE: COH 90... |
751 |
} |
61f135b92 Add COH 901 318 D... |
752 |
|
0b58828c9 DMAENGINE: COH 90... |
753 |
spin_lock(&cohc->lock); |
61f135b92 Add COH 901 318 D... |
754 |
|
cecd87da8 DMAENGINE: COH 90... |
755 756 757 758 759 760 761 762 763 764 |
/* * When we reach this point, at least one queue item * should have been moved over from cohc->queue to * cohc->active and run to completion, that is why we're * getting a terminal count interrupt is it not? * If you get this BUG() the most probable cause is that * the individual nodes in the lli chain have IRQ enabled, * so check your platform config for lli chain ctrl. */ BUG_ON(list_empty(&cohc->active)); |
61f135b92 Add COH 901 318 D... |
765 |
cohc->nbr_active_done++; |
cecd87da8 DMAENGINE: COH 90... |
766 767 768 769 |
/* * This attempt to take a job from cohc->queue, put it * into cohc->active and start it. */ |
0b58828c9 DMAENGINE: COH 90... |
770 |
if (coh901318_queue_start(cohc) == NULL) |
61f135b92 Add COH 901 318 D... |
771 |
cohc->busy = 0; |
0b58828c9 DMAENGINE: COH 90... |
772 |
spin_unlock(&cohc->lock); |
cecd87da8 DMAENGINE: COH 90... |
773 774 775 776 |
/* * This tasklet will remove items from cohc->active * and thus terminates them. */ |
61f135b92 Add COH 901 318 D... |
777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 |
if (cohc_chan_conf(cohc)->priority_high) tasklet_hi_schedule(&cohc->tasklet); else tasklet_schedule(&cohc->tasklet); } static irqreturn_t dma_irq_handler(int irq, void *dev_id) { u32 status1; u32 status2; int i; int ch; struct coh901318_base *base = dev_id; struct coh901318_chan *cohc; void __iomem *virtbase = base->virtbase; status1 = readl(virtbase + COH901318_INT_STATUS1); status2 = readl(virtbase + COH901318_INT_STATUS2); if (unlikely(status1 == 0 && status2 == 0)) { dev_warn(base->dev, "spurious DMA IRQ from no channel! "); return IRQ_HANDLED; } /* TODO: consider handle IRQ in tasklet here to * minimize interrupt latency */ /* Check the first 32 DMA channels for IRQ */ while (status1) { /* Find first bit set, return as a number. */ i = ffs(status1) - 1; ch = i; cohc = &base->chans[ch]; spin_lock(&cohc->lock); /* Mask off this bit */ status1 &= ~(1 << i); /* Check the individual channel bits */ if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) { dev_crit(COHC_2_DEV(cohc), "DMA bus error on channel %d! ", ch); BUG_ON(1); /* Clear BE interrupt */ __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1); } else { /* Caused by TC, really? */ if (unlikely(!test_bit(i, virtbase + COH901318_TC_INT_STATUS1))) { dev_warn(COHC_2_DEV(cohc), "ignoring interrupt not caused by terminal count on channel %d ", ch); /* Clear TC interrupt */ BUG_ON(1); __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); } else { /* Enable powersave if transfer has finished */ if (!(readl(virtbase + COH901318_CX_STAT + COH901318_CX_STAT_SPACING*ch) & COH901318_CX_STAT_ENABLED)) { enable_powersave(cohc); } /* Must clear TC interrupt before calling * dma_tc_handle |
bc0b44c35 coh901318.c: Chan... |
845 |
* in case tc_handle initiate a new dma job |
61f135b92 Add COH 901 318 D... |
846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 |
*/ __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1); dma_tc_handle(cohc); } } spin_unlock(&cohc->lock); } /* Check the remaining 32 DMA channels for IRQ */ while (status2) { /* Find first bit set, return as a number. */ i = ffs(status2) - 1; ch = i + 32; cohc = &base->chans[ch]; spin_lock(&cohc->lock); /* Mask off this bit */ status2 &= ~(1 << i); /* Check the individual channel bits */ if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) { dev_crit(COHC_2_DEV(cohc), "DMA bus error on channel %d! ", ch); /* Clear BE interrupt */ BUG_ON(1); __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2); } else { /* Caused by TC, really? */ if (unlikely(!test_bit(i, virtbase + COH901318_TC_INT_STATUS2))) { dev_warn(COHC_2_DEV(cohc), "ignoring interrupt not caused by terminal count on channel %d ", ch); /* Clear TC interrupt */ __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); BUG_ON(1); } else { /* Enable powersave if transfer has finished */ if (!(readl(virtbase + COH901318_CX_STAT + COH901318_CX_STAT_SPACING*ch) & COH901318_CX_STAT_ENABLED)) { enable_powersave(cohc); } /* Must clear TC interrupt before calling * dma_tc_handle |
bc0b44c35 coh901318.c: Chan... |
892 |
* in case tc_handle initiate a new dma job |
61f135b92 Add COH 901 318 D... |
893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 |
*/ __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2); dma_tc_handle(cohc); } } spin_unlock(&cohc->lock); } return IRQ_HANDLED; } static int coh901318_alloc_chan_resources(struct dma_chan *chan) { struct coh901318_chan *cohc = to_coh901318_chan(chan); |
84c8447c5 DMAENGINE: COH 90... |
908 |
unsigned long flags; |
61f135b92 Add COH 901 318 D... |
909 910 911 912 913 914 915 |
dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d ", __func__, cohc->id); if (chan->client_count > 1) return -EBUSY; |
84c8447c5 DMAENGINE: COH 90... |
916 |
spin_lock_irqsave(&cohc->lock, flags); |
61f135b92 Add COH 901 318 D... |
917 918 919 920 |
coh901318_config(cohc, NULL); cohc->allocated = 1; cohc->completed = chan->cookie = 1; |
84c8447c5 DMAENGINE: COH 90... |
921 |
spin_unlock_irqrestore(&cohc->lock, flags); |
61f135b92 Add COH 901 318 D... |
922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 |
return 1; } static void coh901318_free_chan_resources(struct dma_chan *chan) { struct coh901318_chan *cohc = to_coh901318_chan(chan); int channel = cohc->id; unsigned long flags; spin_lock_irqsave(&cohc->lock, flags); /* Disable HW */ writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG + COH901318_CX_CFG_SPACING*channel); writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL + COH901318_CX_CTRL_SPACING*channel); cohc->allocated = 0; spin_unlock_irqrestore(&cohc->lock, flags); |
058276303 DMAENGINE: extend... |
943 |
chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
61f135b92 Add COH 901 318 D... |
944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 |
} static dma_cookie_t coh901318_tx_submit(struct dma_async_tx_descriptor *tx) { struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc, desc); struct coh901318_chan *cohc = to_coh901318_chan(tx->chan); unsigned long flags; spin_lock_irqsave(&cohc->lock, flags); tx->cookie = coh901318_assign_cookie(cohc, cohd); coh901318_desc_queue(cohc, cohd); spin_unlock_irqrestore(&cohc->lock, flags); return tx->cookie; } static struct dma_async_tx_descriptor * coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t size, unsigned long flags) { |
cecd87da8 DMAENGINE: COH 90... |
970 |
struct coh901318_lli *lli; |
61f135b92 Add COH 901 318 D... |
971 972 973 974 975 |
struct coh901318_desc *cohd; unsigned long flg; struct coh901318_chan *cohc = to_coh901318_chan(chan); int lli_len; u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; |
b87108a77 DMAENGINE: COH 90... |
976 |
int ret; |
61f135b92 Add COH 901 318 D... |
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 |
spin_lock_irqsave(&cohc->lock, flg); dev_vdbg(COHC_2_DEV(cohc), "[%s] channel %d src 0x%x dest 0x%x size %d ", __func__, cohc->id, src, dest, size); if (flags & DMA_PREP_INTERRUPT) /* Trigger interrupt after last lli */ ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT; if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size) lli_len++; |
cecd87da8 DMAENGINE: COH 90... |
992 |
lli = coh901318_lli_alloc(&cohc->base->pool, lli_len); |
61f135b92 Add COH 901 318 D... |
993 |
|
cecd87da8 DMAENGINE: COH 90... |
994 |
if (lli == NULL) |
61f135b92 Add COH 901 318 D... |
995 |
goto err; |
b87108a77 DMAENGINE: COH 90... |
996 |
ret = coh901318_lli_fill_memcpy( |
cecd87da8 DMAENGINE: COH 90... |
997 |
&cohc->base->pool, lli, src, size, dest, |
b87108a77 DMAENGINE: COH 90... |
998 999 1000 1001 |
cohc_chan_param(cohc)->ctrl_lli_chained, ctrl_last); if (ret) goto err; |
61f135b92 Add COH 901 318 D... |
1002 |
|
cecd87da8 DMAENGINE: COH 90... |
1003 |
COH_DBG(coh901318_list_print(cohc, lli)); |
61f135b92 Add COH 901 318 D... |
1004 |
|
b87108a77 DMAENGINE: COH 90... |
1005 1006 |
/* Pick a descriptor to handle this transfer */ cohd = coh901318_desc_get(cohc); |
cecd87da8 DMAENGINE: COH 90... |
1007 |
cohd->lli = lli; |
b87108a77 DMAENGINE: COH 90... |
1008 |
cohd->flags = flags; |
61f135b92 Add COH 901 318 D... |
1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 |
cohd->desc.tx_submit = coh901318_tx_submit; spin_unlock_irqrestore(&cohc->lock, flg); return &cohd->desc; err: spin_unlock_irqrestore(&cohc->lock, flg); return NULL; } static struct dma_async_tx_descriptor * coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_data_direction direction, unsigned long flags) { struct coh901318_chan *cohc = to_coh901318_chan(chan); |
cecd87da8 DMAENGINE: COH 90... |
1025 |
struct coh901318_lli *lli; |
61f135b92 Add COH 901 318 D... |
1026 |
struct coh901318_desc *cohd; |
516fd4305 DMAENGINE: COH 90... |
1027 |
const struct coh901318_params *params; |
61f135b92 Add COH 901 318 D... |
1028 1029 1030 1031 1032 1033 1034 |
struct scatterlist *sg; int len = 0; int size; int i; u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained; u32 ctrl = cohc_chan_param(cohc)->ctrl_lli; u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last; |
516fd4305 DMAENGINE: COH 90... |
1035 |
u32 config; |
61f135b92 Add COH 901 318 D... |
1036 |
unsigned long flg; |
0b58828c9 DMAENGINE: COH 90... |
1037 |
int ret; |
61f135b92 Add COH 901 318 D... |
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 |
if (!sgl) goto out; if (sgl->length == 0) goto out; spin_lock_irqsave(&cohc->lock, flg); dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d ", __func__, sg_len, direction); if (flags & DMA_PREP_INTERRUPT) /* Trigger interrupt after last lli */ ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE; |
516fd4305 DMAENGINE: COH 90... |
1053 1054 |
params = cohc_chan_param(cohc); config = params->config; |
128f904ac DMAENGINE: add ru... |
1055 1056 1057 1058 1059 1060 1061 1062 |
/* * Add runtime-specific control on top, make * sure the bits you set per peripheral channel are * cleared in the default config from the platform. */ ctrl_chained |= cohc->runtime_ctrl; ctrl_last |= cohc->runtime_ctrl; ctrl |= cohc->runtime_ctrl; |
516fd4305 DMAENGINE: COH 90... |
1063 |
|
61f135b92 Add COH 901 318 D... |
1064 1065 1066 |
if (direction == DMA_TO_DEVICE) { u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE | COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE; |
516fd4305 DMAENGINE: COH 90... |
1067 |
config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY; |
61f135b92 Add COH 901 318 D... |
1068 1069 1070 1071 1072 1073 |
ctrl_chained |= tx_flags; ctrl_last |= tx_flags; ctrl |= tx_flags; } else if (direction == DMA_FROM_DEVICE) { u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST | COH901318_CX_CTRL_DST_ADDR_INC_ENABLE; |
516fd4305 DMAENGINE: COH 90... |
1074 |
config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY; |
61f135b92 Add COH 901 318 D... |
1075 1076 1077 1078 1079 |
ctrl_chained |= rx_flags; ctrl_last |= rx_flags; ctrl |= rx_flags; } else goto err_direction; |
61f135b92 Add COH 901 318 D... |
1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 |
/* The dma only supports transmitting packages up to * MAX_DMA_PACKET_SIZE. Calculate to total number of * dma elemts required to send the entire sg list */ for_each_sg(sgl, sg, sg_len, i) { unsigned int factor; size = sg_dma_len(sg); if (size <= MAX_DMA_PACKET_SIZE) { len++; continue; } factor = size >> MAX_DMA_PACKET_SIZE_SHIFT; if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size) factor++; len += factor; } |
848ad1212 DMAENGINE: COH 90... |
1099 1100 |
pr_debug("Allocate %d lli:s for this transfer ", len); |
cecd87da8 DMAENGINE: COH 90... |
1101 |
lli = coh901318_lli_alloc(&cohc->base->pool, len); |
61f135b92 Add COH 901 318 D... |
1102 |
|
cecd87da8 DMAENGINE: COH 90... |
1103 |
if (lli == NULL) |
61f135b92 Add COH 901 318 D... |
1104 |
goto err_dma_alloc; |
cecd87da8 DMAENGINE: COH 90... |
1105 1106 |
/* initiate allocated lli list */ ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len, |
0b58828c9 DMAENGINE: COH 90... |
1107 1108 1109 1110 1111 1112 1113 |
cohc_dev_addr(cohc), ctrl_chained, ctrl, ctrl_last, direction, COH901318_CX_CTRL_TC_IRQ_ENABLE); if (ret) goto err_lli_fill; |
61f135b92 Add COH 901 318 D... |
1114 |
|
128f904ac DMAENGINE: add ru... |
1115 |
|
cecd87da8 DMAENGINE: COH 90... |
1116 |
COH_DBG(coh901318_list_print(cohc, lli)); |
61f135b92 Add COH 901 318 D... |
1117 |
|
b87108a77 DMAENGINE: COH 90... |
1118 1119 |
/* Pick a descriptor to handle this transfer */ cohd = coh901318_desc_get(cohc); |
b89243dd0 dmaengine/coh9013... |
1120 1121 1122 1123 1124 1125 1126 |
cohd->head_config = config; /* * Set the default head ctrl for the channel to the one from the * lli, things may have changed due to odd buffer alignment * etc. */ cohd->head_ctrl = lli->control; |
b87108a77 DMAENGINE: COH 90... |
1127 1128 1129 |
cohd->dir = direction; cohd->flags = flags; cohd->desc.tx_submit = coh901318_tx_submit; |
cecd87da8 DMAENGINE: COH 90... |
1130 |
cohd->lli = lli; |
b87108a77 DMAENGINE: COH 90... |
1131 |
|
61f135b92 Add COH 901 318 D... |
1132 1133 1134 |
spin_unlock_irqrestore(&cohc->lock, flg); return &cohd->desc; |
0b58828c9 DMAENGINE: COH 90... |
1135 |
err_lli_fill: |
61f135b92 Add COH 901 318 D... |
1136 1137 |
err_dma_alloc: err_direction: |
61f135b92 Add COH 901 318 D... |
1138 1139 1140 1141 1142 1143 |
spin_unlock_irqrestore(&cohc->lock, flg); out: return NULL; } static enum dma_status |
079344818 DMAENGINE: generi... |
1144 1145 |
coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) |
61f135b92 Add COH 901 318 D... |
1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 |
{ struct coh901318_chan *cohc = to_coh901318_chan(chan); dma_cookie_t last_used; dma_cookie_t last_complete; int ret; last_complete = cohc->completed; last_used = chan->cookie; ret = dma_async_is_complete(cookie, last_complete, last_used); |
bca346920 dmaengine: provid... |
1156 1157 |
dma_set_tx_state(txstate, last_complete, last_used, coh901318_get_bytes_left(chan)); |
079344818 DMAENGINE: generi... |
1158 1159 |
if (ret == DMA_IN_PROGRESS && cohc->stopped) ret = DMA_PAUSED; |
61f135b92 Add COH 901 318 D... |
1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 |
return ret; } static void coh901318_issue_pending(struct dma_chan *chan) { struct coh901318_chan *cohc = to_coh901318_chan(chan); unsigned long flags; spin_lock_irqsave(&cohc->lock, flags); |
cecd87da8 DMAENGINE: COH 90... |
1171 1172 1173 1174 1175 1176 |
/* * Busy means that pending jobs are already being processed, * and then there is no point in starting the queue: the * terminal count interrupt on the channel will take the next * job on the queue and execute it anyway. */ |
61f135b92 Add COH 901 318 D... |
1177 1178 1179 1180 1181 |
if (!cohc->busy) coh901318_queue_start(cohc); spin_unlock_irqrestore(&cohc->lock, flags); } |
128f904ac DMAENGINE: add ru... |
1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 |
/* * Here we wrap in the runtime dma control interface */ struct burst_table { int burst_8bit; int burst_16bit; int burst_32bit; u32 reg; }; static const struct burst_table burst_sizes[] = { { .burst_8bit = 64, .burst_16bit = 32, .burst_32bit = 16, .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES, }, { .burst_8bit = 48, .burst_16bit = 24, .burst_32bit = 12, .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES, }, { .burst_8bit = 32, .burst_16bit = 16, .burst_32bit = 8, .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES, }, { .burst_8bit = 16, .burst_16bit = 8, .burst_32bit = 4, .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES, }, { .burst_8bit = 8, .burst_16bit = 4, .burst_32bit = 2, .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES, }, { .burst_8bit = 4, .burst_16bit = 2, .burst_32bit = 1, .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES, }, { .burst_8bit = 2, .burst_16bit = 1, .burst_32bit = 0, .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES, }, { .burst_8bit = 1, .burst_16bit = 0, .burst_32bit = 0, .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE, }, }; static void coh901318_dma_set_runtimeconfig(struct dma_chan *chan, struct dma_slave_config *config) { struct coh901318_chan *cohc = to_coh901318_chan(chan); dma_addr_t addr; enum dma_slave_buswidth addr_width; u32 maxburst; u32 runtime_ctrl = 0; int i = 0; /* We only support mem to per or per to mem transfers */ if (config->direction == DMA_FROM_DEVICE) { addr = config->src_addr; addr_width = config->src_addr_width; maxburst = config->src_maxburst; } else if (config->direction == DMA_TO_DEVICE) { addr = config->dst_addr; addr_width = config->dst_addr_width; maxburst = config->dst_maxburst; } else { dev_err(COHC_2_DEV(cohc), "illegal channel mode "); return; } dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers ", addr_width); switch (addr_width) { case DMA_SLAVE_BUSWIDTH_1_BYTE: runtime_ctrl |= COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS; while (i < ARRAY_SIZE(burst_sizes)) { if (burst_sizes[i].burst_8bit <= maxburst) break; i++; } break; case DMA_SLAVE_BUSWIDTH_2_BYTES: runtime_ctrl |= COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS; while (i < ARRAY_SIZE(burst_sizes)) { if (burst_sizes[i].burst_16bit <= maxburst) break; i++; } break; case DMA_SLAVE_BUSWIDTH_4_BYTES: /* Direction doesn't matter here, it's 32/32 bits */ runtime_ctrl |= COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS; while (i < ARRAY_SIZE(burst_sizes)) { if (burst_sizes[i].burst_32bit <= maxburst) break; i++; } break; default: dev_err(COHC_2_DEV(cohc), "bad runtimeconfig: alien address width "); return; } runtime_ctrl |= burst_sizes[i].reg; dev_dbg(COHC_2_DEV(cohc), "selected burst size %d bytes for address width %d bytes, maxburst %d ", burst_sizes[i].burst_8bit, addr_width, maxburst); cohc->runtime_addr = addr; cohc->runtime_ctrl = runtime_ctrl; } |
c3635c78e DMAENGINE: generi... |
1325 |
static int |
058276303 DMAENGINE: extend... |
1326 1327 |
coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) |
61f135b92 Add COH 901 318 D... |
1328 1329 1330 1331 1332 |
{ unsigned long flags; struct coh901318_chan *cohc = to_coh901318_chan(chan); struct coh901318_desc *cohd; void __iomem *virtbase = cohc->base->virtbase; |
128f904ac DMAENGINE: add ru... |
1333 1334 1335 1336 1337 1338 1339 |
if (cmd == DMA_SLAVE_CONFIG) { struct dma_slave_config *config = (struct dma_slave_config *) arg; coh901318_dma_set_runtimeconfig(chan, config); return 0; } |
c3635c78e DMAENGINE: generi... |
1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 |
if (cmd == DMA_PAUSE) { coh901318_pause(chan); return 0; } if (cmd == DMA_RESUME) { coh901318_resume(chan); return 0; } if (cmd != DMA_TERMINATE_ALL) return -ENXIO; |
61f135b92 Add COH 901 318 D... |
1352 |
|
c3635c78e DMAENGINE: generi... |
1353 1354 |
/* The remainder of this function terminates the transfer */ coh901318_pause(chan); |
61f135b92 Add COH 901 318 D... |
1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 |
spin_lock_irqsave(&cohc->lock, flags); /* Clear any pending BE or TC interrupt */ if (cohc->id < 32) { writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1); writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1); } else { writel(1 << (cohc->id - 32), virtbase + COH901318_BE_INT_CLEAR2); writel(1 << (cohc->id - 32), virtbase + COH901318_TC_INT_CLEAR2); } enable_powersave(cohc); while ((cohd = coh901318_first_active_get(cohc))) { /* release the lli allocation*/ |
cecd87da8 DMAENGINE: COH 90... |
1372 |
coh901318_lli_free(&cohc->base->pool, &cohd->lli); |
61f135b92 Add COH 901 318 D... |
1373 |
|
61f135b92 Add COH 901 318 D... |
1374 |
/* return desc to free-list */ |
848ad1212 DMAENGINE: COH 90... |
1375 |
coh901318_desc_remove(cohd); |
61f135b92 Add COH 901 318 D... |
1376 1377 1378 1379 1380 |
coh901318_desc_free(cohc, cohd); } while ((cohd = coh901318_first_queued(cohc))) { /* release the lli allocation*/ |
cecd87da8 DMAENGINE: COH 90... |
1381 |
coh901318_lli_free(&cohc->base->pool, &cohd->lli); |
61f135b92 Add COH 901 318 D... |
1382 |
|
61f135b92 Add COH 901 318 D... |
1383 |
/* return desc to free-list */ |
848ad1212 DMAENGINE: COH 90... |
1384 |
coh901318_desc_remove(cohd); |
61f135b92 Add COH 901 318 D... |
1385 1386 1387 1388 1389 1390 |
coh901318_desc_free(cohc, cohd); } cohc->nbr_active_done = 0; cohc->busy = 0; |
61f135b92 Add COH 901 318 D... |
1391 1392 |
spin_unlock_irqrestore(&cohc->lock, flags); |
c3635c78e DMAENGINE: generi... |
1393 1394 |
return 0; |
61f135b92 Add COH 901 318 D... |
1395 |
} |
128f904ac DMAENGINE: add ru... |
1396 |
|
61f135b92 Add COH 901 318 D... |
1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 |
void coh901318_base_init(struct dma_device *dma, const int *pick_chans, struct coh901318_base *base) { int chans_i; int i = 0; struct coh901318_chan *cohc; INIT_LIST_HEAD(&dma->channels); for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) { for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) { cohc = &base->chans[i]; cohc->base = base; cohc->chan.device = dma; cohc->id = i; /* TODO: do we really need this lock if only one * client is connected to each channel? */ spin_lock_init(&cohc->lock); |
61f135b92 Add COH 901 318 D... |
1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 |
cohc->nbr_active_done = 0; cohc->busy = 0; INIT_LIST_HEAD(&cohc->free); INIT_LIST_HEAD(&cohc->active); INIT_LIST_HEAD(&cohc->queue); tasklet_init(&cohc->tasklet, dma_tasklet, (unsigned long) cohc); list_add_tail(&cohc->chan.device_node, &dma->channels); } } } static int __init coh901318_probe(struct platform_device *pdev) { int err = 0; struct coh901318_platform *pdata; struct coh901318_base *base; int irq; struct resource *io; io = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!io) goto err_get_resource; /* Map DMA controller registers to virtual memory */ if (request_mem_region(io->start, resource_size(io), pdev->dev.driver->name) == NULL) { err = -EBUSY; goto err_request_mem; } pdata = pdev->dev.platform_data; if (!pdata) goto err_no_platformdata; base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) + pdata->max_channels * sizeof(struct coh901318_chan), GFP_KERNEL); if (!base) goto err_alloc_coh_dma_channels; base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4); base->virtbase = ioremap(io->start, resource_size(io)); if (!base->virtbase) { err = -ENOMEM; goto err_no_ioremap; } base->dev = &pdev->dev; base->platform = pdata; spin_lock_init(&base->pm.lock); base->pm.started_channels = 0; COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base); platform_set_drvdata(pdev, base); irq = platform_get_irq(pdev, 0); if (irq < 0) goto err_no_irq; err = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "coh901318", base); if (err) { dev_crit(&pdev->dev, "Cannot allocate IRQ for DMA controller! "); goto err_request_irq; } err = coh901318_pool_create(&base->pool, &pdev->dev, sizeof(struct coh901318_lli), 32); if (err) goto err_pool_create; /* init channels for device transfers */ coh901318_base_init(&base->dma_slave, base->platform->chans_slave, base); dma_cap_zero(base->dma_slave.cap_mask); dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources; base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources; base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg; |
079344818 DMAENGINE: generi... |
1511 |
base->dma_slave.device_tx_status = coh901318_tx_status; |
61f135b92 Add COH 901 318 D... |
1512 |
base->dma_slave.device_issue_pending = coh901318_issue_pending; |
c3635c78e DMAENGINE: generi... |
1513 |
base->dma_slave.device_control = coh901318_control; |
61f135b92 Add COH 901 318 D... |
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 |
base->dma_slave.dev = &pdev->dev; err = dma_async_device_register(&base->dma_slave); if (err) goto err_register_slave; /* init channels for memcpy */ coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy, base); dma_cap_zero(base->dma_memcpy.cap_mask); dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources; base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources; base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy; |
079344818 DMAENGINE: generi... |
1531 |
base->dma_memcpy.device_tx_status = coh901318_tx_status; |
61f135b92 Add COH 901 318 D... |
1532 |
base->dma_memcpy.device_issue_pending = coh901318_issue_pending; |
c3635c78e DMAENGINE: generi... |
1533 |
base->dma_memcpy.device_control = coh901318_control; |
61f135b92 Add COH 901 318 D... |
1534 |
base->dma_memcpy.dev = &pdev->dev; |
516fd4305 DMAENGINE: COH 90... |
1535 1536 1537 1538 1539 |
/* * This controller can only access address at even 32bit boundaries, * i.e. 2^2 */ base->dma_memcpy.copy_align = 2; |
61f135b92 Add COH 901 318 D... |
1540 1541 1542 1543 |
err = dma_async_device_register(&base->dma_memcpy); if (err) goto err_register_memcpy; |
848ad1212 DMAENGINE: COH 90... |
1544 1545 |
dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x ", |
61f135b92 Add COH 901 318 D... |
1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 |
(u32) base->virtbase); return err; err_register_memcpy: dma_async_device_unregister(&base->dma_slave); err_register_slave: coh901318_pool_destroy(&base->pool); err_pool_create: free_irq(platform_get_irq(pdev, 0), base); err_request_irq: err_no_irq: iounmap(base->virtbase); err_no_ioremap: kfree(base); err_alloc_coh_dma_channels: err_no_platformdata: release_mem_region(pdev->resource->start, resource_size(pdev->resource)); err_request_mem: err_get_resource: return err; } static int __exit coh901318_remove(struct platform_device *pdev) { struct coh901318_base *base = platform_get_drvdata(pdev); dma_async_device_unregister(&base->dma_memcpy); dma_async_device_unregister(&base->dma_slave); coh901318_pool_destroy(&base->pool); free_irq(platform_get_irq(pdev, 0), base); |
61f135b92 Add COH 901 318 D... |
1578 |
iounmap(base->virtbase); |
0794ec8ce drivers/dma: Corr... |
1579 |
kfree(base); |
61f135b92 Add COH 901 318 D... |
1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 |
release_mem_region(pdev->resource->start, resource_size(pdev->resource)); return 0; } static struct platform_driver coh901318_driver = { .remove = __exit_p(coh901318_remove), .driver = { .name = "coh901318", }, }; int __init coh901318_init(void) { return platform_driver_probe(&coh901318_driver, coh901318_probe); } |
a0eb221a4 dmaengine: move l... |
1597 |
subsys_initcall(coh901318_init); |
61f135b92 Add COH 901 318 D... |
1598 1599 1600 1601 1602 1603 1604 1605 1606 |
void __exit coh901318_exit(void) { platform_driver_unregister(&coh901318_driver); } module_exit(coh901318_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Per Friden"); |