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drivers/regulator/tps65910-regulator.c
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// SPDX-License-Identifier: GPL-2.0-or-later |
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/* * tps65910.c -- TI tps65910 * * Copyright 2010 Texas Instruments Inc. * * Author: Graeme Gregory <gg@slimlogic.co.uk> * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> |
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*/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/err.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> #include <linux/regulator/driver.h> #include <linux/regulator/machine.h> |
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#include <linux/slab.h> #include <linux/gpio.h> #include <linux/mfd/tps65910.h> |
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#include <linux/regulator/of_regulator.h> |
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#define TPS65910_SUPPLY_STATE_ENABLED 0x1 |
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#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \ TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \ |
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TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \ TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) |
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/* supported VIO voltages in microvolts */ static const unsigned int VIO_VSEL_table[] = { 1500000, 1800000, 2500000, 3300000, |
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}; |
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/* VSEL tables for TPS65910 specific LDOs and dcdc's */ |
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/* supported VRTC voltages in microvolts */ static const unsigned int VRTC_VSEL_table[] = { 1800000, }; |
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/* supported VDD3 voltages in microvolts */ static const unsigned int VDD3_VSEL_table[] = { 5000000, |
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}; |
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/* supported VDIG1 voltages in microvolts */ static const unsigned int VDIG1_VSEL_table[] = { 1200000, 1500000, 1800000, 2700000, |
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}; |
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/* supported VDIG2 voltages in microvolts */ static const unsigned int VDIG2_VSEL_table[] = { 1000000, 1100000, 1200000, 1800000, |
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}; |
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/* supported VPLL voltages in microvolts */ static const unsigned int VPLL_VSEL_table[] = { 1000000, 1100000, 1800000, 2500000, |
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}; |
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/* supported VDAC voltages in microvolts */ static const unsigned int VDAC_VSEL_table[] = { 1800000, 2600000, 2800000, 2850000, |
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}; |
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/* supported VAUX1 voltages in microvolts */ static const unsigned int VAUX1_VSEL_table[] = { 1800000, 2500000, 2800000, 2850000, |
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}; |
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/* supported VAUX2 voltages in microvolts */ static const unsigned int VAUX2_VSEL_table[] = { 1800000, 2800000, 2900000, 3300000, |
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}; |
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/* supported VAUX33 voltages in microvolts */ static const unsigned int VAUX33_VSEL_table[] = { 1800000, 2000000, 2800000, 3300000, |
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}; |
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/* supported VMMC voltages in microvolts */ static const unsigned int VMMC_VSEL_table[] = { 1800000, 2800000, 3000000, 3300000, |
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}; |
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/* supported BBCH voltages in microvolts */ static const unsigned int VBB_VSEL_table[] = { 3000000, 2520000, 3150000, 5000000, }; |
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struct tps_info { const char *name; |
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const char *vin_name; |
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u8 n_voltages; |
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const unsigned int *voltage_table; |
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int enable_time_us; |
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}; static struct tps_info tps65910_regs[] = { { |
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.name = "vrtc", |
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.vin_name = "vcc7", |
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.n_voltages = ARRAY_SIZE(VRTC_VSEL_table), .voltage_table = VRTC_VSEL_table, |
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.enable_time_us = 2200, |
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}, { |
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.name = "vio", |
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.vin_name = "vccio", |
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.n_voltages = ARRAY_SIZE(VIO_VSEL_table), .voltage_table = VIO_VSEL_table, |
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.enable_time_us = 350, |
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}, { |
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.name = "vdd1", |
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.vin_name = "vcc1", |
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.enable_time_us = 350, |
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}, { |
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.name = "vdd2", |
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.vin_name = "vcc2", |
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.enable_time_us = 350, |
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}, { |
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.name = "vdd3", |
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.n_voltages = ARRAY_SIZE(VDD3_VSEL_table), .voltage_table = VDD3_VSEL_table, |
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.enable_time_us = 200, |
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}, { |
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.name = "vdig1", |
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.vin_name = "vcc6", |
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.n_voltages = ARRAY_SIZE(VDIG1_VSEL_table), .voltage_table = VDIG1_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vdig2", |
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.vin_name = "vcc6", |
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.n_voltages = ARRAY_SIZE(VDIG2_VSEL_table), .voltage_table = VDIG2_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vpll", |
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.vin_name = "vcc5", |
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.n_voltages = ARRAY_SIZE(VPLL_VSEL_table), .voltage_table = VPLL_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vdac", |
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.vin_name = "vcc5", |
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.n_voltages = ARRAY_SIZE(VDAC_VSEL_table), .voltage_table = VDAC_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vaux1", |
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.vin_name = "vcc4", |
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.n_voltages = ARRAY_SIZE(VAUX1_VSEL_table), .voltage_table = VAUX1_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vaux2", |
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.vin_name = "vcc4", |
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.n_voltages = ARRAY_SIZE(VAUX2_VSEL_table), .voltage_table = VAUX2_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vaux33", |
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.vin_name = "vcc3", |
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.n_voltages = ARRAY_SIZE(VAUX33_VSEL_table), .voltage_table = VAUX33_VSEL_table, |
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.enable_time_us = 100, |
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}, { |
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.name = "vmmc", |
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.vin_name = "vcc3", |
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.n_voltages = ARRAY_SIZE(VMMC_VSEL_table), .voltage_table = VMMC_VSEL_table, |
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.enable_time_us = 100, |
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}, |
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{ .name = "vbb", .vin_name = "vcc7", .n_voltages = ARRAY_SIZE(VBB_VSEL_table), .voltage_table = VBB_VSEL_table, }, |
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}; |
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static struct tps_info tps65911_regs[] = { { |
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.name = "vrtc", |
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.vin_name = "vcc7", |
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.enable_time_us = 2200, |
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}, { |
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.name = "vio", |
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.vin_name = "vccio", |
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.n_voltages = ARRAY_SIZE(VIO_VSEL_table), .voltage_table = VIO_VSEL_table, |
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.enable_time_us = 350, |
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}, { |
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.name = "vdd1", |
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.vin_name = "vcc1", |
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.n_voltages = 0x4C, |
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.enable_time_us = 350, |
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}, { |
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.name = "vdd2", |
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.vin_name = "vcc2", |
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.n_voltages = 0x4C, |
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.enable_time_us = 350, |
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}, { |
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.name = "vddctrl", |
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.n_voltages = 0x44, |
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.enable_time_us = 900, |
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}, { |
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.name = "ldo1", |
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.vin_name = "vcc6", |
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.n_voltages = 0x33, |
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.enable_time_us = 420, |
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}, { |
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.name = "ldo2", |
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.vin_name = "vcc6", |
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.n_voltages = 0x33, |
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.enable_time_us = 420, |
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}, { |
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.name = "ldo3", |
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.vin_name = "vcc5", |
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.n_voltages = 0x1A, |
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.enable_time_us = 230, |
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}, { |
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.name = "ldo4", |
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.vin_name = "vcc5", |
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.n_voltages = 0x33, |
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.enable_time_us = 230, |
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}, { |
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.name = "ldo5", |
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.vin_name = "vcc4", |
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.n_voltages = 0x1A, |
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.enable_time_us = 230, |
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}, { |
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.name = "ldo6", |
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.vin_name = "vcc3", |
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.n_voltages = 0x1A, |
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.enable_time_us = 230, |
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}, { |
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.name = "ldo7", |
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.vin_name = "vcc3", |
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.n_voltages = 0x1A, |
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.enable_time_us = 230, |
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}, { |
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.name = "ldo8", |
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.vin_name = "vcc3", |
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.n_voltages = 0x1A, |
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.enable_time_us = 230, |
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}, }; |
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#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits)) static unsigned int tps65910_ext_sleep_control[] = { 0, EXT_CONTROL_REG_BITS(VIO, 1, 0), EXT_CONTROL_REG_BITS(VDD1, 1, 1), EXT_CONTROL_REG_BITS(VDD2, 1, 2), EXT_CONTROL_REG_BITS(VDD3, 1, 3), EXT_CONTROL_REG_BITS(VDIG1, 0, 1), EXT_CONTROL_REG_BITS(VDIG2, 0, 2), EXT_CONTROL_REG_BITS(VPLL, 0, 6), EXT_CONTROL_REG_BITS(VDAC, 0, 7), EXT_CONTROL_REG_BITS(VAUX1, 0, 3), EXT_CONTROL_REG_BITS(VAUX2, 0, 4), EXT_CONTROL_REG_BITS(VAUX33, 0, 5), EXT_CONTROL_REG_BITS(VMMC, 0, 0), }; static unsigned int tps65911_ext_sleep_control[] = { 0, EXT_CONTROL_REG_BITS(VIO, 1, 0), EXT_CONTROL_REG_BITS(VDD1, 1, 1), EXT_CONTROL_REG_BITS(VDD2, 1, 2), EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3), EXT_CONTROL_REG_BITS(LDO1, 0, 1), EXT_CONTROL_REG_BITS(LDO2, 0, 2), EXT_CONTROL_REG_BITS(LDO3, 0, 7), EXT_CONTROL_REG_BITS(LDO4, 0, 6), EXT_CONTROL_REG_BITS(LDO5, 0, 3), EXT_CONTROL_REG_BITS(LDO6, 0, 0), EXT_CONTROL_REG_BITS(LDO7, 0, 5), EXT_CONTROL_REG_BITS(LDO8, 0, 4), }; |
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struct tps65910_reg { |
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struct regulator_desc *desc; |
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struct tps65910 *mfd; |
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struct regulator_dev **rdev; struct tps_info **info; |
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int num_regulators; |
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int mode; |
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int (*get_ctrl_reg)(int); |
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unsigned int *ext_sleep_control; unsigned int board_ext_control[TPS65910_NUM_REGS]; |
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}; |
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static int tps65910_get_ctrl_register(int id) { switch (id) { case TPS65910_REG_VRTC: return TPS65910_VRTC; case TPS65910_REG_VIO: return TPS65910_VIO; case TPS65910_REG_VDD1: return TPS65910_VDD1; case TPS65910_REG_VDD2: return TPS65910_VDD2; case TPS65910_REG_VDD3: return TPS65910_VDD3; case TPS65910_REG_VDIG1: return TPS65910_VDIG1; case TPS65910_REG_VDIG2: return TPS65910_VDIG2; case TPS65910_REG_VPLL: return TPS65910_VPLL; case TPS65910_REG_VDAC: return TPS65910_VDAC; case TPS65910_REG_VAUX1: return TPS65910_VAUX1; case TPS65910_REG_VAUX2: return TPS65910_VAUX2; case TPS65910_REG_VAUX33: return TPS65910_VAUX33; case TPS65910_REG_VMMC: return TPS65910_VMMC; |
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case TPS65910_REG_VBB: return TPS65910_BBCH; |
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default: return -EINVAL; } } |
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static int tps65911_get_ctrl_register(int id) { switch (id) { case TPS65910_REG_VRTC: return TPS65910_VRTC; case TPS65910_REG_VIO: return TPS65910_VIO; case TPS65910_REG_VDD1: return TPS65910_VDD1; case TPS65910_REG_VDD2: return TPS65910_VDD2; case TPS65911_REG_VDDCTRL: return TPS65911_VDDCTRL; case TPS65911_REG_LDO1: return TPS65911_LDO1; case TPS65911_REG_LDO2: return TPS65911_LDO2; case TPS65911_REG_LDO3: return TPS65911_LDO3; case TPS65911_REG_LDO4: return TPS65911_LDO4; case TPS65911_REG_LDO5: return TPS65911_LDO5; case TPS65911_REG_LDO6: return TPS65911_LDO6; case TPS65911_REG_LDO7: return TPS65911_LDO7; case TPS65911_REG_LDO8: return TPS65911_LDO8; default: return -EINVAL; } } |
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static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode) { struct tps65910_reg *pmic = rdev_get_drvdata(dev); struct tps65910 *mfd = pmic->mfd; int reg, value, id = rdev_get_id(dev); |
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reg = pmic->get_ctrl_reg(id); |
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if (reg < 0) return reg; switch (mode) { case REGULATOR_MODE_NORMAL: |
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return tps65910_reg_update_bits(pmic->mfd, reg, LDO_ST_MODE_BIT | LDO_ST_ON_BIT, LDO_ST_ON_BIT); |
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case REGULATOR_MODE_IDLE: value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT; |
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return tps65910_reg_set_bits(mfd, reg, value); |
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case REGULATOR_MODE_STANDBY: |
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return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT); |
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} return -EINVAL; } static unsigned int tps65910_get_mode(struct regulator_dev *dev) { struct tps65910_reg *pmic = rdev_get_drvdata(dev); |
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int ret, reg, value, id = rdev_get_id(dev); |
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reg = pmic->get_ctrl_reg(id); |
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if (reg < 0) return reg; |
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ret = tps65910_reg_read(pmic->mfd, reg, &value); if (ret < 0) return ret; |
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if (!(value & LDO_ST_ON_BIT)) |
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return REGULATOR_MODE_STANDBY; else if (value & LDO_ST_MODE_BIT) return REGULATOR_MODE_IDLE; else return REGULATOR_MODE_NORMAL; } |
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static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev) |
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{ struct tps65910_reg *pmic = rdev_get_drvdata(dev); |
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int ret, id = rdev_get_id(dev); |
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int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0; |
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switch (id) { case TPS65910_REG_VDD1: |
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ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel); if (ret < 0) return ret; ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult); if (ret < 0) return ret; |
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mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT; |
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ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel); if (ret < 0) return ret; |
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sr = opvsel & VDD1_OP_CMD_MASK; opvsel &= VDD1_OP_SEL_MASK; srvsel &= VDD1_SR_SEL_MASK; |
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vselmax = 75; |
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break; case TPS65910_REG_VDD2: |
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ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel); if (ret < 0) return ret; ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult); if (ret < 0) return ret; |
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|
445 |
mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT; |
faa95fde4
|
446 447 448 |
ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel); if (ret < 0) return ret; |
518fb721d
|
449 450 451 |
sr = opvsel & VDD2_OP_CMD_MASK; opvsel &= VDD2_OP_SEL_MASK; srvsel &= VDD2_SR_SEL_MASK; |
a320e3c3d
|
452 453 454 |
vselmax = 75; break; case TPS65911_REG_VDDCTRL: |
faa95fde4
|
455 456 457 458 459 460 461 462 |
ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP, &opvsel); if (ret < 0) return ret; ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR, &srvsel); if (ret < 0) return ret; |
a320e3c3d
|
463 464 465 466 |
sr = opvsel & VDDCTRL_OP_CMD_MASK; opvsel &= VDDCTRL_OP_SEL_MASK; srvsel &= VDDCTRL_SR_SEL_MASK; vselmax = 64; |
518fb721d
|
467 468 469 470 471 |
break; } /* multiplier 0 == 1 but 2,3 normal */ if (!mult) |
4b5792704
|
472 |
mult = 1; |
518fb721d
|
473 474 |
if (sr) { |
a320e3c3d
|
475 476 477 478 479 |
/* normalise to valid range */ if (srvsel < 3) srvsel = 3; if (srvsel > vselmax) srvsel = vselmax; |
18039e0f1
|
480 |
return srvsel - 3; |
518fb721d
|
481 |
} else { |
a320e3c3d
|
482 483 484 485 486 |
/* normalise to valid range*/ if (opvsel < 3) opvsel = 3; if (opvsel > vselmax) opvsel = vselmax; |
18039e0f1
|
487 |
return opvsel - 3; |
518fb721d
|
488 |
} |
18039e0f1
|
489 |
return -EINVAL; |
518fb721d
|
490 |
} |
1f904fd1c
|
491 |
static int tps65910_get_voltage_sel(struct regulator_dev *dev) |
518fb721d
|
492 493 |
{ struct tps65910_reg *pmic = rdev_get_drvdata(dev); |
faa95fde4
|
494 |
int ret, reg, value, id = rdev_get_id(dev); |
518fb721d
|
495 |
|
a320e3c3d
|
496 |
reg = pmic->get_ctrl_reg(id); |
518fb721d
|
497 498 |
if (reg < 0) return reg; |
faa95fde4
|
499 500 501 |
ret = tps65910_reg_read(pmic->mfd, reg, &value); if (ret < 0) return ret; |
518fb721d
|
502 503 504 505 506 507 508 509 510 511 512 513 514 515 |
switch (id) { case TPS65910_REG_VIO: case TPS65910_REG_VDIG1: case TPS65910_REG_VDIG2: case TPS65910_REG_VPLL: case TPS65910_REG_VDAC: case TPS65910_REG_VAUX1: case TPS65910_REG_VAUX2: case TPS65910_REG_VAUX33: case TPS65910_REG_VMMC: value &= LDO_SEL_MASK; value >>= LDO_SEL_SHIFT; break; |
03746dcbd
|
516 517 518 519 |
case TPS65910_REG_VBB: value &= BBCH_BBSEL_MASK; value >>= BBCH_BBSEL_SHIFT; break; |
518fb721d
|
520 521 522 |
default: return -EINVAL; } |
1f904fd1c
|
523 |
return value; |
518fb721d
|
524 525 526 527 |
} static int tps65910_get_voltage_vdd3(struct regulator_dev *dev) { |
d9fe28f96
|
528 |
return dev->desc->volt_table[0]; |
518fb721d
|
529 |
} |
1f904fd1c
|
530 |
static int tps65911_get_voltage_sel(struct regulator_dev *dev) |
a320e3c3d
|
531 532 |
{ struct tps65910_reg *pmic = rdev_get_drvdata(dev); |
faa95fde4
|
533 534 |
int ret, id = rdev_get_id(dev); unsigned int value, reg; |
a320e3c3d
|
535 536 |
reg = pmic->get_ctrl_reg(id); |
faa95fde4
|
537 538 539 |
ret = tps65910_reg_read(pmic->mfd, reg, &value); if (ret < 0) return ret; |
a320e3c3d
|
540 541 542 543 544 545 546 |
switch (id) { case TPS65911_REG_LDO1: case TPS65911_REG_LDO2: case TPS65911_REG_LDO4: value &= LDO1_SEL_MASK; value >>= LDO_SEL_SHIFT; |
a320e3c3d
|
547 548 549 550 551 552 553 554 |
break; case TPS65911_REG_LDO3: case TPS65911_REG_LDO5: case TPS65911_REG_LDO6: case TPS65911_REG_LDO7: case TPS65911_REG_LDO8: value &= LDO3_SEL_MASK; value >>= LDO_SEL_SHIFT; |
a320e3c3d
|
555 556 |
break; case TPS65910_REG_VIO: |
e882eae80
|
557 558 |
value &= LDO_SEL_MASK; value >>= LDO_SEL_SHIFT; |
1f904fd1c
|
559 |
break; |
a320e3c3d
|
560 561 562 |
default: return -EINVAL; } |
1f904fd1c
|
563 |
return value; |
a320e3c3d
|
564 |
} |
94732b97c
|
565 566 |
static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev, unsigned selector) |
518fb721d
|
567 568 569 |
{ struct tps65910_reg *pmic = rdev_get_drvdata(dev); int id = rdev_get_id(dev), vsel; |
a320e3c3d
|
570 |
int dcdc_mult = 0; |
518fb721d
|
571 |
|
a320e3c3d
|
572 573 |
switch (id) { case TPS65910_REG_VDD1: |
780dc9ba4
|
574 |
dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3d
|
575 576 |
if (dcdc_mult == 1) dcdc_mult--; |
780dc9ba4
|
577 |
vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
518fb721d
|
578 |
|
faa95fde4
|
579 580 581 582 |
tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1, VDD1_VGAIN_SEL_MASK, dcdc_mult << VDD1_VGAIN_SEL_SHIFT); tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel); |
a320e3c3d
|
583 584 |
break; case TPS65910_REG_VDD2: |
780dc9ba4
|
585 |
dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3d
|
586 587 |
if (dcdc_mult == 1) dcdc_mult--; |
780dc9ba4
|
588 |
vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3; |
a320e3c3d
|
589 |
|
faa95fde4
|
590 591 592 593 |
tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2, VDD1_VGAIN_SEL_MASK, dcdc_mult << VDD2_VGAIN_SEL_SHIFT); tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel); |
a320e3c3d
|
594 595 |
break; case TPS65911_REG_VDDCTRL: |
c4632aed3
|
596 |
vsel = selector + 3; |
faa95fde4
|
597 |
tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel); |
518fb721d
|
598 599 600 601 |
} return 0; } |
94732b97c
|
602 603 |
static int tps65910_set_voltage_sel(struct regulator_dev *dev, unsigned selector) |
518fb721d
|
604 605 606 |
{ struct tps65910_reg *pmic = rdev_get_drvdata(dev); int reg, id = rdev_get_id(dev); |
a320e3c3d
|
607 |
reg = pmic->get_ctrl_reg(id); |
518fb721d
|
608 609 610 611 612 613 614 615 616 617 618 619 620 |
if (reg < 0) return reg; switch (id) { case TPS65910_REG_VIO: case TPS65910_REG_VDIG1: case TPS65910_REG_VDIG2: case TPS65910_REG_VPLL: case TPS65910_REG_VDAC: case TPS65910_REG_VAUX1: case TPS65910_REG_VAUX2: case TPS65910_REG_VAUX33: case TPS65910_REG_VMMC: |
faa95fde4
|
621 622 |
return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, selector << LDO_SEL_SHIFT); |
03746dcbd
|
623 624 625 |
case TPS65910_REG_VBB: return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK, selector << BBCH_BBSEL_SHIFT); |
518fb721d
|
626 627 628 629 |
} return -EINVAL; } |
94732b97c
|
630 631 |
static int tps65911_set_voltage_sel(struct regulator_dev *dev, unsigned selector) |
a320e3c3d
|
632 633 634 635 636 637 638 639 640 641 642 643 |
{ struct tps65910_reg *pmic = rdev_get_drvdata(dev); int reg, id = rdev_get_id(dev); reg = pmic->get_ctrl_reg(id); if (reg < 0) return reg; switch (id) { case TPS65911_REG_LDO1: case TPS65911_REG_LDO2: case TPS65911_REG_LDO4: |
faa95fde4
|
644 645 |
return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK, selector << LDO_SEL_SHIFT); |
a320e3c3d
|
646 647 648 649 650 |
case TPS65911_REG_LDO3: case TPS65911_REG_LDO5: case TPS65911_REG_LDO6: case TPS65911_REG_LDO7: case TPS65911_REG_LDO8: |
faa95fde4
|
651 652 |
return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK, selector << LDO_SEL_SHIFT); |
e882eae80
|
653 |
case TPS65910_REG_VIO: |
faa95fde4
|
654 655 |
return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK, selector << LDO_SEL_SHIFT); |
03746dcbd
|
656 657 658 |
case TPS65910_REG_VBB: return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK, selector << BBCH_BBSEL_SHIFT); |
a320e3c3d
|
659 660 661 662 |
} return -EINVAL; } |
518fb721d
|
663 664 665 |
static int tps65910_list_voltage_dcdc(struct regulator_dev *dev, unsigned selector) { |
a320e3c3d
|
666 |
int volt, mult = 1, id = rdev_get_id(dev); |
518fb721d
|
667 |
|
a320e3c3d
|
668 669 670 |
switch (id) { case TPS65910_REG_VDD1: case TPS65910_REG_VDD2: |
780dc9ba4
|
671 |
mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1; |
a320e3c3d
|
672 |
volt = VDD1_2_MIN_VOLT + |
4b5792704
|
673 |
(selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET; |
d04156bca
|
674 |
break; |
a320e3c3d
|
675 676 |
case TPS65911_REG_VDDCTRL: volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET); |
d04156bca
|
677 678 679 680 |
break; default: BUG(); return -EINVAL; |
a320e3c3d
|
681 |
} |
518fb721d
|
682 683 684 |
return volt * 100 * mult; } |
a320e3c3d
|
685 686 687 688 |
static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector) { struct tps65910_reg *pmic = rdev_get_drvdata(dev); int step_mv = 0, id = rdev_get_id(dev); |
4b5792704
|
689 |
switch (id) { |
a320e3c3d
|
690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 |
case TPS65911_REG_LDO1: case TPS65911_REG_LDO2: case TPS65911_REG_LDO4: /* The first 5 values of the selector correspond to 1V */ if (selector < 5) selector = 0; else selector -= 4; step_mv = 50; break; case TPS65911_REG_LDO3: case TPS65911_REG_LDO5: case TPS65911_REG_LDO6: case TPS65911_REG_LDO7: case TPS65911_REG_LDO8: /* The first 3 values of the selector correspond to 1V */ if (selector < 3) selector = 0; else selector -= 2; step_mv = 100; break; case TPS65910_REG_VIO: |
d9fe28f96
|
715 |
return pmic->info[id]->voltage_table[selector]; |
a320e3c3d
|
716 717 718 719 720 721 |
default: return -EINVAL; } return (LDO_MIN_VOLT + selector * step_mv) * 1000; } |
518fb721d
|
722 723 |
/* Regulator ops (except VRTC) */ static struct regulator_ops tps65910_ops_dcdc = { |
a40a9c436
|
724 725 726 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, |
518fb721d
|
727 728 |
.set_mode = tps65910_set_mode, .get_mode = tps65910_get_mode, |
18039e0f1
|
729 |
.get_voltage_sel = tps65910_get_voltage_dcdc_sel, |
94732b97c
|
730 |
.set_voltage_sel = tps65910_set_voltage_dcdc_sel, |
01bc3a140
|
731 |
.set_voltage_time_sel = regulator_set_voltage_time_sel, |
518fb721d
|
732 |
.list_voltage = tps65910_list_voltage_dcdc, |
9fa8175f0
|
733 |
.map_voltage = regulator_map_voltage_ascend, |
518fb721d
|
734 735 736 |
}; static struct regulator_ops tps65910_ops_vdd3 = { |
a40a9c436
|
737 738 739 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, |
518fb721d
|
740 741 742 |
.set_mode = tps65910_set_mode, .get_mode = tps65910_get_mode, .get_voltage = tps65910_get_voltage_vdd3, |
d9fe28f96
|
743 |
.list_voltage = regulator_list_voltage_table, |
9fa8175f0
|
744 |
.map_voltage = regulator_map_voltage_ascend, |
518fb721d
|
745 |
}; |
03746dcbd
|
746 747 748 749 750 751 752 753 754 755 756 |
static struct regulator_ops tps65910_ops_vbb = { .is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, .set_mode = tps65910_set_mode, .get_mode = tps65910_get_mode, .get_voltage_sel = tps65910_get_voltage_sel, .set_voltage_sel = tps65910_set_voltage_sel, .list_voltage = regulator_list_voltage_table, .map_voltage = regulator_map_voltage_iterate, }; |
518fb721d
|
757 |
static struct regulator_ops tps65910_ops = { |
a40a9c436
|
758 759 760 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, |
518fb721d
|
761 762 |
.set_mode = tps65910_set_mode, .get_mode = tps65910_get_mode, |
1f904fd1c
|
763 |
.get_voltage_sel = tps65910_get_voltage_sel, |
94732b97c
|
764 |
.set_voltage_sel = tps65910_set_voltage_sel, |
d9fe28f96
|
765 |
.list_voltage = regulator_list_voltage_table, |
9fa8175f0
|
766 |
.map_voltage = regulator_map_voltage_ascend, |
518fb721d
|
767 |
}; |
a320e3c3d
|
768 |
static struct regulator_ops tps65911_ops = { |
a40a9c436
|
769 770 771 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, |
a320e3c3d
|
772 773 |
.set_mode = tps65910_set_mode, .get_mode = tps65910_get_mode, |
1f904fd1c
|
774 |
.get_voltage_sel = tps65911_get_voltage_sel, |
94732b97c
|
775 |
.set_voltage_sel = tps65911_set_voltage_sel, |
a320e3c3d
|
776 |
.list_voltage = tps65911_list_voltage, |
9fa8175f0
|
777 |
.map_voltage = regulator_map_voltage_ascend, |
a320e3c3d
|
778 |
}; |
1e0c66f49
|
779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 |
static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic, int id, int ext_sleep_config) { struct tps65910 *mfd = pmic->mfd; u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF; u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF); int ret; /* * Regulator can not be control from multiple external input EN1, EN2 * and EN3 together. */ if (ext_sleep_config & EXT_SLEEP_CONTROL) { int en_count; en_count = ((ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0); en_count += ((ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0); en_count += ((ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0); |
f30b0716f
|
799 800 |
en_count += ((ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0); |
1e0c66f49
|
801 802 803 804 805 806 807 808 809 810 811 812 |
if (en_count > 1) { dev_err(mfd->dev, "External sleep control flag is not proper "); return -EINVAL; } } pmic->board_ext_control[id] = ext_sleep_config; /* External EN1 control */ if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) |
3f7e82759
|
813 |
ret = tps65910_reg_set_bits(mfd, |
1e0c66f49
|
814 815 |
TPS65910_EN1_LDO_ASS + regoffs, bit_pos); else |
3f7e82759
|
816 |
ret = tps65910_reg_clear_bits(mfd, |
1e0c66f49
|
817 818 819 820 821 822 823 824 825 826 |
TPS65910_EN1_LDO_ASS + regoffs, bit_pos); if (ret < 0) { dev_err(mfd->dev, "Error in configuring external control EN1 "); return ret; } /* External EN2 control */ if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) |
3f7e82759
|
827 |
ret = tps65910_reg_set_bits(mfd, |
1e0c66f49
|
828 829 |
TPS65910_EN2_LDO_ASS + regoffs, bit_pos); else |
3f7e82759
|
830 |
ret = tps65910_reg_clear_bits(mfd, |
1e0c66f49
|
831 832 833 834 835 836 837 838 839 840 841 842 |
TPS65910_EN2_LDO_ASS + regoffs, bit_pos); if (ret < 0) { dev_err(mfd->dev, "Error in configuring external control EN2 "); return ret; } /* External EN3 control for TPS65910 LDO only */ if ((tps65910_chip_id(mfd) == TPS65910) && (id >= TPS65910_REG_VDIG1)) { if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) |
3f7e82759
|
843 |
ret = tps65910_reg_set_bits(mfd, |
1e0c66f49
|
844 845 |
TPS65910_EN3_LDO_ASS + regoffs, bit_pos); else |
3f7e82759
|
846 |
ret = tps65910_reg_clear_bits(mfd, |
1e0c66f49
|
847 848 849 850 851 852 853 854 855 856 857 858 |
TPS65910_EN3_LDO_ASS + regoffs, bit_pos); if (ret < 0) { dev_err(mfd->dev, "Error in configuring external control EN3 "); return ret; } } /* Return if no external control is selected */ if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) { /* Clear all sleep controls */ |
3f7e82759
|
859 |
ret = tps65910_reg_clear_bits(mfd, |
1e0c66f49
|
860 861 |
TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); if (!ret) |
3f7e82759
|
862 |
ret = tps65910_reg_clear_bits(mfd, |
1e0c66f49
|
863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 |
TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); if (ret < 0) dev_err(mfd->dev, "Error in configuring SLEEP register "); return ret; } /* * For regulator that has separate operational and sleep register make * sure that operational is used and clear sleep register to turn * regulator off when external control is inactive */ if ((id == TPS65910_REG_VDD1) || (id == TPS65910_REG_VDD2) || ((id == TPS65911_REG_VDDCTRL) && (tps65910_chip_id(mfd) == TPS65911))) { int op_reg_add = pmic->get_ctrl_reg(id) + 1; int sr_reg_add = pmic->get_ctrl_reg(id) + 2; |
faa95fde4
|
882 883 884 885 886 887 888 889 |
int opvsel, srvsel; ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel); if (ret < 0) return ret; ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel); if (ret < 0) return ret; |
1e0c66f49
|
890 891 |
if (opvsel & VDD1_OP_CMD_MASK) { u8 reg_val = srvsel & VDD1_OP_SEL_MASK; |
faa95fde4
|
892 893 894 |
ret = tps65910_reg_write(pmic->mfd, op_reg_add, reg_val); |
1e0c66f49
|
895 896 897 898 899 900 901 |
if (ret < 0) { dev_err(mfd->dev, "Error in configuring op register "); return ret; } } |
faa95fde4
|
902 |
ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0); |
1e0c66f49
|
903 |
if (ret < 0) { |
6d3be300c
|
904 905 |
dev_err(mfd->dev, "Error in setting sr register "); |
1e0c66f49
|
906 907 908 |
return ret; } } |
3f7e82759
|
909 |
ret = tps65910_reg_clear_bits(mfd, |
1e0c66f49
|
910 |
TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos); |
f30b0716f
|
911 912 |
if (!ret) { if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) |
3f7e82759
|
913 |
ret = tps65910_reg_set_bits(mfd, |
f30b0716f
|
914 915 |
TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); else |
3f7e82759
|
916 |
ret = tps65910_reg_clear_bits(mfd, |
f30b0716f
|
917 918 |
TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos); } |
1e0c66f49
|
919 920 921 922 |
if (ret < 0) dev_err(mfd->dev, "Error in configuring SLEEP register "); |
f30b0716f
|
923 |
|
1e0c66f49
|
924 925 |
return ret; } |
6790178f5
|
926 927 928 |
#ifdef CONFIG_OF static struct of_regulator_match tps65910_matches[] = { |
33a6943d2
|
929 930 931 932 933 934 935 936 937 938 939 940 941 |
{ .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] }, { .name = "vio", .driver_data = (void *) &tps65910_regs[1] }, { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] }, { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] }, { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] }, { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] }, { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] }, { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] }, { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] }, { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] }, { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] }, { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] }, { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] }, |
03746dcbd
|
942 |
{ .name = "vbb", .driver_data = (void *) &tps65910_regs[13] }, |
6790178f5
|
943 944 945 |
}; static struct of_regulator_match tps65911_matches[] = { |
33a6943d2
|
946 947 948 949 950 951 952 953 954 955 956 957 958 |
{ .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] }, { .name = "vio", .driver_data = (void *) &tps65911_regs[1] }, { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] }, { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] }, { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] }, { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] }, { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] }, { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] }, { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] }, { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] }, { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] }, { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] }, { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] }, |
6790178f5
|
959 960 961 |
}; static struct tps65910_board *tps65910_parse_dt_reg_data( |
84df8c124
|
962 963 |
struct platform_device *pdev, struct of_regulator_match **tps65910_reg_matches) |
6790178f5
|
964 965 966 |
{ struct tps65910_board *pmic_plat_data; struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); |
c92f5dd2c
|
967 |
struct device_node *np, *regulators; |
6790178f5
|
968 969 970 971 972 973 |
struct of_regulator_match *matches; unsigned int prop; int idx = 0, ret, count; pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data), GFP_KERNEL); |
bcb2c0d69
|
974 |
if (!pmic_plat_data) |
6790178f5
|
975 |
return NULL; |
6790178f5
|
976 |
|
b8b27a44d
|
977 |
np = pdev->dev.parent->of_node; |
4ae1ff7fe
|
978 |
regulators = of_get_child_by_name(np, "regulators"); |
92ab953bd
|
979 980 981 982 983 |
if (!regulators) { dev_err(&pdev->dev, "regulator node not found "); return NULL; } |
6790178f5
|
984 985 986 987 988 989 990 991 992 993 994 |
switch (tps65910_chip_id(tps65910)) { case TPS65910: count = ARRAY_SIZE(tps65910_matches); matches = tps65910_matches; break; case TPS65911: count = ARRAY_SIZE(tps65911_matches); matches = tps65911_matches; break; default: |
c92f5dd2c
|
995 |
of_node_put(regulators); |
7e9a57e62
|
996 997 |
dev_err(&pdev->dev, "Invalid tps chip version "); |
6790178f5
|
998 999 |
return NULL; } |
08337fdac
|
1000 |
ret = of_regulator_match(&pdev->dev, regulators, matches, count); |
c92f5dd2c
|
1001 |
of_node_put(regulators); |
6790178f5
|
1002 1003 1004 1005 1006 1007 |
if (ret < 0) { dev_err(&pdev->dev, "Error parsing regulator init data: %d ", ret); return NULL; } |
84df8c124
|
1008 |
*tps65910_reg_matches = matches; |
6790178f5
|
1009 |
for (idx = 0; idx < count; idx++) { |
23b113483
|
1010 |
if (!matches[idx].of_node) |
6790178f5
|
1011 1012 1013 1014 1015 1016 1017 1018 1019 |
continue; pmic_plat_data->tps65910_pmic_init_data[idx] = matches[idx].init_data; ret = of_property_read_u32(matches[idx].of_node, "ti,regulator-ext-sleep-control", &prop); if (!ret) pmic_plat_data->regulator_ext_sleep_control[idx] = prop; |
19228a6a5
|
1020 |
|
6790178f5
|
1021 1022 1023 1024 1025 1026 |
} return pmic_plat_data; } #else static inline struct tps65910_board *tps65910_parse_dt_reg_data( |
84df8c124
|
1027 1028 |
struct platform_device *pdev, struct of_regulator_match **tps65910_reg_matches) |
6790178f5
|
1029 |
{ |
84df8c124
|
1030 |
*tps65910_reg_matches = NULL; |
74ea0e599
|
1031 |
return NULL; |
6790178f5
|
1032 1033 |
} #endif |
a5023574d
|
1034 |
static int tps65910_probe(struct platform_device *pdev) |
518fb721d
|
1035 1036 |
{ struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent); |
c172708d3
|
1037 |
struct regulator_config config = { }; |
a320e3c3d
|
1038 |
struct tps_info *info; |
518fb721d
|
1039 1040 1041 |
struct regulator_dev *rdev; struct tps65910_reg *pmic; struct tps65910_board *pmic_plat_data; |
84df8c124
|
1042 |
struct of_regulator_match *tps65910_reg_matches = NULL; |
518fb721d
|
1043 1044 1045 |
int i, err; pmic_plat_data = dev_get_platdata(tps65910->dev); |
6790178f5
|
1046 |
if (!pmic_plat_data && tps65910->dev->of_node) |
84df8c124
|
1047 1048 |
pmic_plat_data = tps65910_parse_dt_reg_data(pdev, &tps65910_reg_matches); |
6790178f5
|
1049 |
|
7e9a57e62
|
1050 1051 1052 |
if (!pmic_plat_data) { dev_err(&pdev->dev, "Platform data not found "); |
518fb721d
|
1053 |
return -EINVAL; |
7e9a57e62
|
1054 |
} |
518fb721d
|
1055 |
|
9eb0c4218
|
1056 |
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); |
bcb2c0d69
|
1057 |
if (!pmic) |
518fb721d
|
1058 |
return -ENOMEM; |
518fb721d
|
1059 1060 1061 1062 |
pmic->mfd = tps65910; platform_set_drvdata(pdev, pmic); /* Give control of all register to control port */ |
cd07e3701
|
1063 |
err = tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL, |
518fb721d
|
1064 |
DEVCTRL_SR_CTL_I2C_SEL_MASK); |
cd07e3701
|
1065 1066 |
if (err < 0) return err; |
518fb721d
|
1067 |
|
4b5792704
|
1068 |
switch (tps65910_chip_id(tps65910)) { |
a320e3c3d
|
1069 |
case TPS65910: |
fe953904f
|
1070 |
BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs)); |
a320e3c3d
|
1071 |
pmic->get_ctrl_reg = &tps65910_get_ctrl_register; |
39aa9b6e3
|
1072 |
pmic->num_regulators = ARRAY_SIZE(tps65910_regs); |
1e0c66f49
|
1073 |
pmic->ext_sleep_control = tps65910_ext_sleep_control; |
a320e3c3d
|
1074 |
info = tps65910_regs; |
8f9165c98
|
1075 1076 1077 1078 1079 1080 |
/* Work around silicon erratum SWCZ010: output programmed * voltage level can go higher than expected or crash * Workaround: use no synchronization of DCDC clocks */ tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL, DCDCCTRL_DCDCCKSYNC_MASK); |
d04156bca
|
1081 |
break; |
a320e3c3d
|
1082 |
case TPS65911: |
fe953904f
|
1083 |
BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs)); |
a320e3c3d
|
1084 |
pmic->get_ctrl_reg = &tps65911_get_ctrl_register; |
39aa9b6e3
|
1085 |
pmic->num_regulators = ARRAY_SIZE(tps65911_regs); |
1e0c66f49
|
1086 |
pmic->ext_sleep_control = tps65911_ext_sleep_control; |
a320e3c3d
|
1087 |
info = tps65911_regs; |
d04156bca
|
1088 |
break; |
a320e3c3d
|
1089 |
default: |
7e9a57e62
|
1090 1091 |
dev_err(&pdev->dev, "Invalid tps chip version "); |
a320e3c3d
|
1092 1093 |
return -ENODEV; } |
a86854d0c
|
1094 1095 1096 1097 |
pmic->desc = devm_kcalloc(&pdev->dev, pmic->num_regulators, sizeof(struct regulator_desc), GFP_KERNEL); |
bcb2c0d69
|
1098 |
if (!pmic->desc) |
68d8c1cd5
|
1099 |
return -ENOMEM; |
39aa9b6e3
|
1100 |
|
a86854d0c
|
1101 1102 1103 1104 |
pmic->info = devm_kcalloc(&pdev->dev, pmic->num_regulators, sizeof(struct tps_info *), GFP_KERNEL); |
bcb2c0d69
|
1105 |
if (!pmic->info) |
68d8c1cd5
|
1106 |
return -ENOMEM; |
39aa9b6e3
|
1107 |
|
a86854d0c
|
1108 1109 1110 1111 |
pmic->rdev = devm_kcalloc(&pdev->dev, pmic->num_regulators, sizeof(struct regulator_dev *), GFP_KERNEL); |
bcb2c0d69
|
1112 |
if (!pmic->rdev) |
68d8c1cd5
|
1113 |
return -ENOMEM; |
39aa9b6e3
|
1114 |
|
fe953904f
|
1115 |
for (i = 0; i < pmic->num_regulators; i++, info++) { |
518fb721d
|
1116 1117 1118 1119 |
/* Register the regulators */ pmic->info[i] = info; pmic->desc[i].name = info->name; |
d2cfdb055
|
1120 |
pmic->desc[i].supply_name = info->vin_name; |
77fa44d0e
|
1121 |
pmic->desc[i].id = i; |
7d38a3cb9
|
1122 |
pmic->desc[i].n_voltages = info->n_voltages; |
94f48ab32
|
1123 |
pmic->desc[i].enable_time = info->enable_time_us; |
518fb721d
|
1124 |
|
a320e3c3d
|
1125 |
if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) { |
518fb721d
|
1126 |
pmic->desc[i].ops = &tps65910_ops_dcdc; |
780dc9ba4
|
1127 1128 |
pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE * VDD1_2_NUM_VOLT_COARSE; |
01bc3a140
|
1129 |
pmic->desc[i].ramp_delay = 12500; |
a320e3c3d
|
1130 |
} else if (i == TPS65910_REG_VDD3) { |
01bc3a140
|
1131 |
if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3d
|
1132 |
pmic->desc[i].ops = &tps65910_ops_vdd3; |
d9fe28f96
|
1133 |
pmic->desc[i].volt_table = info->voltage_table; |
01bc3a140
|
1134 |
} else { |
a320e3c3d
|
1135 |
pmic->desc[i].ops = &tps65910_ops_dcdc; |
01bc3a140
|
1136 1137 |
pmic->desc[i].ramp_delay = 5000; } |
03746dcbd
|
1138 1139 1140 1141 |
} else if (i == TPS65910_REG_VBB && tps65910_chip_id(tps65910) == TPS65910) { pmic->desc[i].ops = &tps65910_ops_vbb; pmic->desc[i].volt_table = info->voltage_table; |
a320e3c3d
|
1142 |
} else { |
d9fe28f96
|
1143 |
if (tps65910_chip_id(tps65910) == TPS65910) { |
a320e3c3d
|
1144 |
pmic->desc[i].ops = &tps65910_ops; |
d9fe28f96
|
1145 1146 |
pmic->desc[i].volt_table = info->voltage_table; } else { |
a320e3c3d
|
1147 |
pmic->desc[i].ops = &tps65911_ops; |
d9fe28f96
|
1148 |
} |
a320e3c3d
|
1149 |
} |
518fb721d
|
1150 |
|
1e0c66f49
|
1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 |
err = tps65910_set_ext_sleep_config(pmic, i, pmic_plat_data->regulator_ext_sleep_control[i]); /* * Failing on regulator for configuring externally control * is not a serious issue, just throw warning. */ if (err < 0) dev_warn(tps65910->dev, "Failed to initialise ext control config "); |
518fb721d
|
1161 1162 |
pmic->desc[i].type = REGULATOR_VOLTAGE; pmic->desc[i].owner = THIS_MODULE; |
a40a9c436
|
1163 |
pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i); |
b8903eb98
|
1164 |
pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED; |
518fb721d
|
1165 |
|
c172708d3
|
1166 |
config.dev = tps65910->dev; |
23b113483
|
1167 |
config.init_data = pmic_plat_data->tps65910_pmic_init_data[i]; |
c172708d3
|
1168 |
config.driver_data = pmic; |
a40a9c436
|
1169 |
config.regmap = tps65910->regmap; |
c172708d3
|
1170 |
|
84df8c124
|
1171 1172 |
if (tps65910_reg_matches) config.of_node = tps65910_reg_matches[i].of_node; |
6790178f5
|
1173 |
|
95095e422
|
1174 1175 |
rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i], &config); |
518fb721d
|
1176 1177 1178 1179 1180 |
if (IS_ERR(rdev)) { dev_err(tps65910->dev, "failed to register %s regulator ", pdev->name); |
95095e422
|
1181 |
return PTR_ERR(rdev); |
518fb721d
|
1182 1183 1184 1185 1186 1187 |
} /* Save regulator for cleanup */ pmic->rdev[i] = rdev; } return 0; |
518fb721d
|
1188 |
} |
1e0c66f49
|
1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 |
static void tps65910_shutdown(struct platform_device *pdev) { struct tps65910_reg *pmic = platform_get_drvdata(pdev); int i; /* * Before bootloader jumps to kernel, it makes sure that required * external control signals are in desired state so that given rails * can be configure accordingly. * If rails are configured to be controlled from external control * then before shutting down/rebooting the system, the external * control configuration need to be remove from the rails so that * its output will be available as per register programming even * if external controls are removed. This is require when the POR * value of the control signals are not in active state and before * bootloader initializes it, the system requires the rail output * to be active for booting. */ for (i = 0; i < pmic->num_regulators; i++) { int err; if (!pmic->rdev[i]) continue; err = tps65910_set_ext_sleep_config(pmic, i, 0); if (err < 0) dev_err(&pdev->dev, "Error in clearing external control "); } } |
518fb721d
|
1219 1220 1221 |
static struct platform_driver tps65910_driver = { .driver = { .name = "tps65910-pmic", |
518fb721d
|
1222 1223 |
}, .probe = tps65910_probe, |
1e0c66f49
|
1224 |
.shutdown = tps65910_shutdown, |
518fb721d
|
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 |
}; static int __init tps65910_init(void) { return platform_driver_register(&tps65910_driver); } subsys_initcall(tps65910_init); static void __exit tps65910_cleanup(void) { platform_driver_unregister(&tps65910_driver); } module_exit(tps65910_cleanup); MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); |
ae0e65443
|
1240 |
MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver"); |
518fb721d
|
1241 1242 |
MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:tps65910-pmic"); |