Blame view
drivers/clocksource/timer-cadence-ttc.c
14.3 KB
9c92ab619 treewide: Replace... |
1 |
// SPDX-License-Identifier: GPL-2.0-only |
b85a3ef4a ARM: Xilinx: Addi... |
2 |
/* |
9e09dc5f7 arm: zynq: Do not... |
3 |
* This file contains driver for the Cadence Triple Timer Counter Rev 06 |
b85a3ef4a ARM: Xilinx: Addi... |
4 |
* |
e932900a3 arm: zynq: Use st... |
5 |
* Copyright (C) 2011-2013 Xilinx |
b85a3ef4a ARM: Xilinx: Addi... |
6 7 |
* * based on arch/mips/kernel/time.c timer driver |
b85a3ef4a ARM: Xilinx: Addi... |
8 |
*/ |
e932900a3 arm: zynq: Use st... |
9 |
#include <linux/clk.h> |
b85a3ef4a ARM: Xilinx: Addi... |
10 |
#include <linux/interrupt.h> |
b85a3ef4a ARM: Xilinx: Addi... |
11 |
#include <linux/clockchips.h> |
459fa246d clocksource: Expl... |
12 |
#include <linux/clocksource.h> |
91dc985c5 ARM: zynq: add cl... |
13 14 15 |
#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/slab.h> |
3d77b30ef clocksource: cade... |
16 |
#include <linux/sched_clock.h> |
b85a3ef4a ARM: Xilinx: Addi... |
17 |
|
b85a3ef4a ARM: Xilinx: Addi... |
18 |
/* |
4e2bec0c3 clocksource: cade... |
19 |
* This driver configures the 2 16/32-bit count-up timers as follows: |
e932900a3 arm: zynq: Use st... |
20 21 22 23 24 25 26 27 28 29 30 31 32 33 |
* * T1: Timer 1, clocksource for generic timekeeping * T2: Timer 2, clockevent source for hrtimers * T3: Timer 3, <unused> * * The input frequency to the timer module for emulation is 2.5MHz which is * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, * the timers are clocked at 78.125KHz (12.8 us resolution). * The input frequency to the timer module in silicon is configurable and * obtained from device tree. The pre-scaler of 32 is used. */ /* |
b85a3ef4a ARM: Xilinx: Addi... |
34 35 36 |
* Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 */ |
9e09dc5f7 arm: zynq: Do not... |
37 38 39 40 41 42 |
#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ |
f184c5caa arm: zynq: timer:... |
43 |
|
9e09dc5f7 arm: zynq: Do not... |
44 |
#define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
b85a3ef4a ARM: Xilinx: Addi... |
45 |
|
30e1e2859 arm: zynq: Migrat... |
46 |
#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
b3e90722f clocksource/caden... |
47 48 |
#define TTC_CLK_CNTRL_PSV_MASK 0x1e #define TTC_CLK_CNTRL_PSV_SHIFT 1 |
30e1e2859 arm: zynq: Migrat... |
49 |
|
03377e585 arm: zynq: timer:... |
50 51 |
/* * Setup the timers to use pre-scaling, using a fixed value for now that will |
91dc985c5 ARM: zynq: add cl... |
52 53 54 55 56 57 |
* work across most input frequency, but it may need to be more dynamic */ #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ #define PRESCALE 2048 /* The exponent must match this */ #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) #define CLK_CNTRL_PRESCALE_EN 1 |
e932900a3 arm: zynq: Use st... |
58 |
#define CNT_CNTRL_RESET (1 << 4) |
b85a3ef4a ARM: Xilinx: Addi... |
59 |
|
b3e90722f clocksource/caden... |
60 |
#define MAX_F_ERR 50 |
b85a3ef4a ARM: Xilinx: Addi... |
61 |
/** |
9e09dc5f7 arm: zynq: Do not... |
62 |
* struct ttc_timer - This definition defines local timer structure |
b85a3ef4a ARM: Xilinx: Addi... |
63 64 |
* * @base_addr: Base address of timer |
c1dcc927d clocksource: cade... |
65 |
* @freq: Timer input clock frequency |
e932900a3 arm: zynq: Use st... |
66 67 68 |
* @clk: Associated clock source * @clk_rate_change_nb Notifier block for clock rate changes */ |
9e09dc5f7 arm: zynq: Do not... |
69 |
struct ttc_timer { |
e932900a3 arm: zynq: Use st... |
70 |
void __iomem *base_addr; |
c1dcc927d clocksource: cade... |
71 |
unsigned long freq; |
e932900a3 arm: zynq: Use st... |
72 73 |
struct clk *clk; struct notifier_block clk_rate_change_nb; |
91dc985c5 ARM: zynq: add cl... |
74 |
}; |
9e09dc5f7 arm: zynq: Do not... |
75 76 |
#define to_ttc_timer(x) \ container_of(x, struct ttc_timer, clk_rate_change_nb) |
e932900a3 arm: zynq: Use st... |
77 |
|
9e09dc5f7 arm: zynq: Do not... |
78 |
struct ttc_timer_clocksource { |
b3e90722f clocksource/caden... |
79 80 |
u32 scale_clk_ctrl_reg_old; u32 scale_clk_ctrl_reg_new; |
9e09dc5f7 arm: zynq: Do not... |
81 |
struct ttc_timer ttc; |
91dc985c5 ARM: zynq: add cl... |
82 |
struct clocksource cs; |
b85a3ef4a ARM: Xilinx: Addi... |
83 |
}; |
9e09dc5f7 arm: zynq: Do not... |
84 85 |
#define to_ttc_timer_clksrc(x) \ container_of(x, struct ttc_timer_clocksource, cs) |
91dc985c5 ARM: zynq: add cl... |
86 |
|
9e09dc5f7 arm: zynq: Do not... |
87 88 |
struct ttc_timer_clockevent { struct ttc_timer ttc; |
91dc985c5 ARM: zynq: add cl... |
89 |
struct clock_event_device ce; |
91dc985c5 ARM: zynq: add cl... |
90 |
}; |
9e09dc5f7 arm: zynq: Do not... |
91 92 |
#define to_ttc_timer_clkevent(x) \ container_of(x, struct ttc_timer_clockevent, ce) |
b85a3ef4a ARM: Xilinx: Addi... |
93 |
|
3d77b30ef clocksource: cade... |
94 |
static void __iomem *ttc_sched_clock_val_reg; |
b85a3ef4a ARM: Xilinx: Addi... |
95 |
/** |
9e09dc5f7 arm: zynq: Do not... |
96 |
* ttc_set_interval - Set the timer interval value |
b85a3ef4a ARM: Xilinx: Addi... |
97 98 99 100 |
* * @timer: Pointer to the timer instance * @cycles: Timer interval ticks **/ |
9e09dc5f7 arm: zynq: Do not... |
101 |
static void ttc_set_interval(struct ttc_timer *timer, |
b85a3ef4a ARM: Xilinx: Addi... |
102 103 104 105 106 |
unsigned long cycles) { u32 ctrl_reg; /* Disable the counter, set the counter value and re-enable counter */ |
87ab4361b clocksource: cade... |
107 |
ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
9e09dc5f7 arm: zynq: Do not... |
108 |
ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
87ab4361b clocksource: cade... |
109 |
writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4a ARM: Xilinx: Addi... |
110 |
|
87ab4361b clocksource: cade... |
111 |
writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
b85a3ef4a ARM: Xilinx: Addi... |
112 |
|
03377e585 arm: zynq: timer:... |
113 114 115 116 |
/* * Reset the counter (0x10) so that it starts from 0, one-shot * mode makes this needed for timing to be right. */ |
91dc985c5 ARM: zynq: add cl... |
117 |
ctrl_reg |= CNT_CNTRL_RESET; |
9e09dc5f7 arm: zynq: Do not... |
118 |
ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
87ab4361b clocksource: cade... |
119 |
writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
b85a3ef4a ARM: Xilinx: Addi... |
120 121 122 |
} /** |
9e09dc5f7 arm: zynq: Do not... |
123 |
* ttc_clock_event_interrupt - Clock event timer interrupt handler |
b85a3ef4a ARM: Xilinx: Addi... |
124 125 |
* * @irq: IRQ number of the Timer |
9e09dc5f7 arm: zynq: Do not... |
126 |
* @dev_id: void pointer to the ttc_timer instance |
b85a3ef4a ARM: Xilinx: Addi... |
127 128 129 |
* * returns: Always IRQ_HANDLED - success **/ |
9e09dc5f7 arm: zynq: Do not... |
130 |
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
b85a3ef4a ARM: Xilinx: Addi... |
131 |
{ |
9e09dc5f7 arm: zynq: Do not... |
132 133 |
struct ttc_timer_clockevent *ttce = dev_id; struct ttc_timer *timer = &ttce->ttc; |
b85a3ef4a ARM: Xilinx: Addi... |
134 135 |
/* Acknowledge the interrupt and call event handler */ |
87ab4361b clocksource: cade... |
136 |
readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); |
b85a3ef4a ARM: Xilinx: Addi... |
137 |
|
9e09dc5f7 arm: zynq: Do not... |
138 |
ttce->ce.event_handler(&ttce->ce); |
b85a3ef4a ARM: Xilinx: Addi... |
139 140 141 |
return IRQ_HANDLED; } |
b85a3ef4a ARM: Xilinx: Addi... |
142 |
/** |
9e09dc5f7 arm: zynq: Do not... |
143 |
* __ttc_clocksource_read - Reads the timer counter register |
b85a3ef4a ARM: Xilinx: Addi... |
144 145 146 |
* * returns: Current timer counter register value **/ |
a5a1d1c29 clocksource: Use ... |
147 |
static u64 __ttc_clocksource_read(struct clocksource *cs) |
b85a3ef4a ARM: Xilinx: Addi... |
148 |
{ |
9e09dc5f7 arm: zynq: Do not... |
149 |
struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
b85a3ef4a ARM: Xilinx: Addi... |
150 |
|
a5a1d1c29 clocksource: Use ... |
151 |
return (u64)readl_relaxed(timer->base_addr + |
9e09dc5f7 arm: zynq: Do not... |
152 |
TTC_COUNT_VAL_OFFSET); |
b85a3ef4a ARM: Xilinx: Addi... |
153 |
} |
dfded0090 clocksource: cade... |
154 |
static u64 notrace ttc_sched_clock_read(void) |
3d77b30ef clocksource: cade... |
155 |
{ |
87ab4361b clocksource: cade... |
156 |
return readl_relaxed(ttc_sched_clock_val_reg); |
3d77b30ef clocksource: cade... |
157 |
} |
b85a3ef4a ARM: Xilinx: Addi... |
158 |
/** |
9e09dc5f7 arm: zynq: Do not... |
159 |
* ttc_set_next_event - Sets the time interval for next event |
b85a3ef4a ARM: Xilinx: Addi... |
160 161 162 163 164 165 |
* * @cycles: Timer interval ticks * @evt: Address of clock event instance * * returns: Always 0 - success **/ |
9e09dc5f7 arm: zynq: Do not... |
166 |
static int ttc_set_next_event(unsigned long cycles, |
b85a3ef4a ARM: Xilinx: Addi... |
167 168 |
struct clock_event_device *evt) { |
9e09dc5f7 arm: zynq: Do not... |
169 170 |
struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; |
b85a3ef4a ARM: Xilinx: Addi... |
171 |
|
9e09dc5f7 arm: zynq: Do not... |
172 |
ttc_set_interval(timer, cycles); |
b85a3ef4a ARM: Xilinx: Addi... |
173 174 175 176 |
return 0; } /** |
5c0a4bbef clockevents/drive... |
177 |
* ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer |
b85a3ef4a ARM: Xilinx: Addi... |
178 |
* |
b85a3ef4a ARM: Xilinx: Addi... |
179 180 |
* @evt: Address of clock event instance **/ |
5c0a4bbef clockevents/drive... |
181 |
static int ttc_shutdown(struct clock_event_device *evt) |
b85a3ef4a ARM: Xilinx: Addi... |
182 |
{ |
9e09dc5f7 arm: zynq: Do not... |
183 184 |
struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; |
b85a3ef4a ARM: Xilinx: Addi... |
185 |
u32 ctrl_reg; |
5c0a4bbef clockevents/drive... |
186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 |
ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); return 0; } static int ttc_set_periodic(struct clock_event_device *evt) { struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ)); return 0; } static int ttc_resume(struct clock_event_device *evt) { struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); struct ttc_timer *timer = &ttce->ttc; u32 ctrl_reg; ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); return 0; |
b85a3ef4a ARM: Xilinx: Addi... |
212 |
} |
9e09dc5f7 arm: zynq: Do not... |
213 |
static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
e932900a3 arm: zynq: Use st... |
214 215 216 |
unsigned long event, void *data) { struct clk_notifier_data *ndata = data; |
9e09dc5f7 arm: zynq: Do not... |
217 218 219 |
struct ttc_timer *ttc = to_ttc_timer(nb); struct ttc_timer_clocksource *ttccs = container_of(ttc, struct ttc_timer_clocksource, ttc); |
e932900a3 arm: zynq: Use st... |
220 221 |
switch (event) { |
b3e90722f clocksource/caden... |
222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 |
case PRE_RATE_CHANGE: { u32 psv; unsigned long factor, rate_low, rate_high; if (ndata->new_rate > ndata->old_rate) { factor = DIV_ROUND_CLOSEST(ndata->new_rate, ndata->old_rate); rate_low = ndata->old_rate; rate_high = ndata->new_rate; } else { factor = DIV_ROUND_CLOSEST(ndata->old_rate, ndata->new_rate); rate_low = ndata->new_rate; rate_high = ndata->old_rate; } if (!is_power_of_2(factor)) return NOTIFY_BAD; if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR) return NOTIFY_BAD; factor = __ilog2_u32(factor); |
e932900a3 arm: zynq: Use st... |
246 |
/* |
b3e90722f clocksource/caden... |
247 248 |
* store timer clock ctrl register so we can restore it in case * of an abort. |
e932900a3 arm: zynq: Use st... |
249 |
*/ |
b3e90722f clocksource/caden... |
250 |
ttccs->scale_clk_ctrl_reg_old = |
87ab4361b clocksource: cade... |
251 252 |
readl_relaxed(ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
b3e90722f clocksource/caden... |
253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 |
psv = (ttccs->scale_clk_ctrl_reg_old & TTC_CLK_CNTRL_PSV_MASK) >> TTC_CLK_CNTRL_PSV_SHIFT; if (ndata->new_rate < ndata->old_rate) psv -= factor; else psv += factor; /* prescaler within legal range? */ if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT)) return NOTIFY_BAD; ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old & ~TTC_CLK_CNTRL_PSV_MASK; ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT; /* scale down: adjust divider in post-change notification */ if (ndata->new_rate < ndata->old_rate) return NOTIFY_DONE; /* scale up: adjust divider now - before frequency change */ |
87ab4361b clocksource: cade... |
276 277 |
writel_relaxed(ttccs->scale_clk_ctrl_reg_new, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
b3e90722f clocksource/caden... |
278 279 280 281 282 283 284 285 |
break; } case POST_RATE_CHANGE: /* scale up: pre-change notification did the adjustment */ if (ndata->new_rate > ndata->old_rate) return NOTIFY_OK; /* scale down: adjust divider now - after frequency change */ |
87ab4361b clocksource: cade... |
286 287 |
writel_relaxed(ttccs->scale_clk_ctrl_reg_new, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
b3e90722f clocksource/caden... |
288 |
break; |
e932900a3 arm: zynq: Use st... |
289 |
case ABORT_RATE_CHANGE: |
b3e90722f clocksource/caden... |
290 291 292 293 294 |
/* we have to undo the adjustment in case we scale up */ if (ndata->new_rate < ndata->old_rate) return NOTIFY_OK; /* restore original register value */ |
87ab4361b clocksource: cade... |
295 296 |
writel_relaxed(ttccs->scale_clk_ctrl_reg_old, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
b3e90722f clocksource/caden... |
297 |
/* fall through */ |
e932900a3 arm: zynq: Use st... |
298 299 300 |
default: return NOTIFY_DONE; } |
b3e90722f clocksource/caden... |
301 302 |
return NOTIFY_DONE; |
e932900a3 arm: zynq: Use st... |
303 |
} |
70504f311 clocksource/drive... |
304 |
static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base, |
4e2bec0c3 clocksource: cade... |
305 |
u32 timer_width) |
91dc985c5 ARM: zynq: add cl... |
306 |
{ |
9e09dc5f7 arm: zynq: Do not... |
307 |
struct ttc_timer_clocksource *ttccs; |
91dc985c5 ARM: zynq: add cl... |
308 |
int err; |
91dc985c5 ARM: zynq: add cl... |
309 310 |
ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); |
70504f311 clocksource/drive... |
311 312 |
if (!ttccs) return -ENOMEM; |
91dc985c5 ARM: zynq: add cl... |
313 |
|
9e09dc5f7 arm: zynq: Do not... |
314 |
ttccs->ttc.clk = clk; |
91dc985c5 ARM: zynq: add cl... |
315 |
|
9e09dc5f7 arm: zynq: Do not... |
316 |
err = clk_prepare_enable(ttccs->ttc.clk); |
70504f311 clocksource/drive... |
317 |
if (err) { |
c5263bb8b arm: zynq: Move t... |
318 |
kfree(ttccs); |
70504f311 clocksource/drive... |
319 |
return err; |
c5263bb8b arm: zynq: Move t... |
320 |
} |
91dc985c5 ARM: zynq: add cl... |
321 |
|
c1dcc927d clocksource: cade... |
322 |
ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); |
9e09dc5f7 arm: zynq: Do not... |
323 324 325 |
ttccs->ttc.clk_rate_change_nb.notifier_call = ttc_rate_change_clocksource_cb; ttccs->ttc.clk_rate_change_nb.next = NULL; |
70504f311 clocksource/drive... |
326 327 328 329 |
err = clk_notifier_register(ttccs->ttc.clk, &ttccs->ttc.clk_rate_change_nb); if (err) |
e932900a3 arm: zynq: Use st... |
330 331 |
pr_warn("Unable to register clock notifier. "); |
91dc985c5 ARM: zynq: add cl... |
332 |
|
9e09dc5f7 arm: zynq: Do not... |
333 334 |
ttccs->ttc.base_addr = base; ttccs->cs.name = "ttc_clocksource"; |
91dc985c5 ARM: zynq: add cl... |
335 |
ttccs->cs.rating = 200; |
9e09dc5f7 arm: zynq: Do not... |
336 |
ttccs->cs.read = __ttc_clocksource_read; |
4e2bec0c3 clocksource: cade... |
337 |
ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width); |
91dc985c5 ARM: zynq: add cl... |
338 |
ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
e932900a3 arm: zynq: Use st... |
339 340 341 342 343 |
/* * Setup the clock source counter to be an incrementing counter * with no interrupt and it rolls over at 0xFFFF. Pre-scale * it by 32 also. Let it start running now. */ |
87ab4361b clocksource: cade... |
344 345 |
writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f7 arm: zynq: Do not... |
346 |
ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361b clocksource: cade... |
347 |
writel_relaxed(CNT_CNTRL_RESET, |
9e09dc5f7 arm: zynq: Do not... |
348 |
ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
91dc985c5 ARM: zynq: add cl... |
349 |
|
c1dcc927d clocksource: cade... |
350 |
err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); |
70504f311 clocksource/drive... |
351 |
if (err) { |
c5263bb8b arm: zynq: Move t... |
352 |
kfree(ttccs); |
70504f311 clocksource/drive... |
353 |
return err; |
c5263bb8b arm: zynq: Move t... |
354 |
} |
3d77b30ef clocksource: cade... |
355 356 |
ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; |
4e2bec0c3 clocksource: cade... |
357 358 |
sched_clock_register(ttc_sched_clock_read, timer_width, ttccs->ttc.freq / PRESCALE); |
70504f311 clocksource/drive... |
359 360 |
return 0; |
91dc985c5 ARM: zynq: add cl... |
361 |
} |
9e09dc5f7 arm: zynq: Do not... |
362 |
static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
e932900a3 arm: zynq: Use st... |
363 364 365 |
unsigned long event, void *data) { struct clk_notifier_data *ndata = data; |
9e09dc5f7 arm: zynq: Do not... |
366 367 368 |
struct ttc_timer *ttc = to_ttc_timer(nb); struct ttc_timer_clockevent *ttcce = container_of(ttc, struct ttc_timer_clockevent, ttc); |
e932900a3 arm: zynq: Use st... |
369 370 371 |
switch (event) { case POST_RATE_CHANGE: |
c1dcc927d clocksource: cade... |
372 373 |
/* update cached frequency */ ttc->freq = ndata->new_rate; |
5f0ba3b46 clocksource/caden... |
374 |
clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE); |
e932900a3 arm: zynq: Use st... |
375 |
/* fall through */ |
e932900a3 arm: zynq: Use st... |
376 377 378 379 380 381 |
case PRE_RATE_CHANGE: case ABORT_RATE_CHANGE: default: return NOTIFY_DONE; } } |
70504f311 clocksource/drive... |
382 383 |
static int __init ttc_setup_clockevent(struct clk *clk, void __iomem *base, u32 irq) |
91dc985c5 ARM: zynq: add cl... |
384 |
{ |
9e09dc5f7 arm: zynq: Do not... |
385 |
struct ttc_timer_clockevent *ttcce; |
e932900a3 arm: zynq: Use st... |
386 |
int err; |
91dc985c5 ARM: zynq: add cl... |
387 388 |
ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); |
70504f311 clocksource/drive... |
389 390 |
if (!ttcce) return -ENOMEM; |
91dc985c5 ARM: zynq: add cl... |
391 |
|
9e09dc5f7 arm: zynq: Do not... |
392 |
ttcce->ttc.clk = clk; |
91dc985c5 ARM: zynq: add cl... |
393 |
|
9e09dc5f7 arm: zynq: Do not... |
394 |
err = clk_prepare_enable(ttcce->ttc.clk); |
70504f311 clocksource/drive... |
395 |
if (err) { |
c5263bb8b arm: zynq: Move t... |
396 |
kfree(ttcce); |
70504f311 clocksource/drive... |
397 |
return err; |
c5263bb8b arm: zynq: Move t... |
398 |
} |
91dc985c5 ARM: zynq: add cl... |
399 |
|
9e09dc5f7 arm: zynq: Do not... |
400 401 402 |
ttcce->ttc.clk_rate_change_nb.notifier_call = ttc_rate_change_clockevent_cb; ttcce->ttc.clk_rate_change_nb.next = NULL; |
70504f311 clocksource/drive... |
403 404 405 406 |
err = clk_notifier_register(ttcce->ttc.clk, &ttcce->ttc.clk_rate_change_nb); if (err) { |
e932900a3 arm: zynq: Use st... |
407 408 |
pr_warn("Unable to register clock notifier. "); |
70504f311 clocksource/drive... |
409 410 |
return err; } |
c1dcc927d clocksource: cade... |
411 |
ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); |
91dc985c5 ARM: zynq: add cl... |
412 |
|
9e09dc5f7 arm: zynq: Do not... |
413 414 |
ttcce->ttc.base_addr = base; ttcce->ce.name = "ttc_clockevent"; |
91dc985c5 ARM: zynq: add cl... |
415 |
ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
9e09dc5f7 arm: zynq: Do not... |
416 |
ttcce->ce.set_next_event = ttc_set_next_event; |
5c0a4bbef clockevents/drive... |
417 418 419 420 |
ttcce->ce.set_state_shutdown = ttc_shutdown; ttcce->ce.set_state_periodic = ttc_set_periodic; ttcce->ce.set_state_oneshot = ttc_shutdown; ttcce->ce.tick_resume = ttc_resume; |
91dc985c5 ARM: zynq: add cl... |
421 422 |
ttcce->ce.rating = 200; ttcce->ce.irq = irq; |
87e4ee759 arm: zynq: timer:... |
423 |
ttcce->ce.cpumask = cpu_possible_mask; |
91dc985c5 ARM: zynq: add cl... |
424 |
|
e932900a3 arm: zynq: Use st... |
425 426 427 428 429 |
/* * Setup the clock event timer to be an interval timer which * is prescaled by 32 using the interval interrupt. Leave it * disabled for now. */ |
87ab4361b clocksource: cade... |
430 431 |
writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
9e09dc5f7 arm: zynq: Do not... |
432 |
ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
87ab4361b clocksource: cade... |
433 |
writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); |
91dc985c5 ARM: zynq: add cl... |
434 |
|
9e09dc5f7 arm: zynq: Do not... |
435 |
err = request_irq(irq, ttc_clock_event_interrupt, |
38c30a842 clocksource: misc... |
436 |
IRQF_TIMER, ttcce->ce.name, ttcce); |
70504f311 clocksource/drive... |
437 |
if (err) { |
c5263bb8b arm: zynq: Move t... |
438 |
kfree(ttcce); |
70504f311 clocksource/drive... |
439 |
return err; |
c5263bb8b arm: zynq: Move t... |
440 |
} |
91dc985c5 ARM: zynq: add cl... |
441 442 |
clockevents_config_and_register(&ttcce->ce, |
c1dcc927d clocksource: cade... |
443 |
ttcce->ttc.freq / PRESCALE, 1, 0xfffe); |
70504f311 clocksource/drive... |
444 445 |
return 0; |
91dc985c5 ARM: zynq: add cl... |
446 |
} |
b85a3ef4a ARM: Xilinx: Addi... |
447 |
/** |
9e09dc5f7 arm: zynq: Do not... |
448 |
* ttc_timer_init - Initialize the timer |
b85a3ef4a ARM: Xilinx: Addi... |
449 450 451 |
* * Initializes the timer hardware and register the clock source and clock event * timers with Linux kernal timer framework |
e932900a3 arm: zynq: Use st... |
452 |
*/ |
70504f311 clocksource/drive... |
453 |
static int __init ttc_timer_init(struct device_node *timer) |
e932900a3 arm: zynq: Use st... |
454 455 456 |
{ unsigned int irq; void __iomem *timer_baseaddr; |
30e1e2859 arm: zynq: Migrat... |
457 |
struct clk *clk_cs, *clk_ce; |
c5263bb8b arm: zynq: Move t... |
458 |
static int initialized; |
70504f311 clocksource/drive... |
459 |
int clksel, ret; |
4e2bec0c3 clocksource: cade... |
460 |
u32 timer_width = 16; |
c5263bb8b arm: zynq: Move t... |
461 462 |
if (initialized) |
70504f311 clocksource/drive... |
463 |
return 0; |
c5263bb8b arm: zynq: Move t... |
464 465 |
initialized = 1; |
e932900a3 arm: zynq: Use st... |
466 467 468 469 470 471 472 473 474 475 |
/* * Get the 1st Triple Timer Counter (TTC) block from the device tree * and use it. Note that the event timer uses the interrupt and it's the * 2nd TTC hence the irq_of_parse_and_map(,1) */ timer_baseaddr = of_iomap(timer, 0); if (!timer_baseaddr) { pr_err("ERROR: invalid timer base address "); |
70504f311 clocksource/drive... |
476 |
return -ENXIO; |
e932900a3 arm: zynq: Use st... |
477 478 479 480 481 482 |
} irq = irq_of_parse_and_map(timer, 1); if (irq <= 0) { pr_err("ERROR: invalid interrupt number "); |
70504f311 clocksource/drive... |
483 |
return -EINVAL; |
e932900a3 arm: zynq: Use st... |
484 |
} |
4e2bec0c3 clocksource: cade... |
485 |
of_property_read_u32(timer, "timer-width", &timer_width); |
87ab4361b clocksource: cade... |
486 |
clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
30e1e2859 arm: zynq: Migrat... |
487 488 489 490 491 |
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); clk_cs = of_clk_get(timer, clksel); if (IS_ERR(clk_cs)) { pr_err("ERROR: timer input clock not found "); |
70504f311 clocksource/drive... |
492 |
return PTR_ERR(clk_cs); |
30e1e2859 arm: zynq: Migrat... |
493 |
} |
87ab4361b clocksource: cade... |
494 |
clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); |
30e1e2859 arm: zynq: Migrat... |
495 496 497 |
clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); clk_ce = of_clk_get(timer, clksel); if (IS_ERR(clk_ce)) { |
e932900a3 arm: zynq: Use st... |
498 499 |
pr_err("ERROR: timer input clock not found "); |
34c720a91 clocksource/drive... |
500 |
return PTR_ERR(clk_ce); |
e932900a3 arm: zynq: Use st... |
501 |
} |
70504f311 clocksource/drive... |
502 503 504 505 506 507 508 |
ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); if (ret) return ret; ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); if (ret) return ret; |
e932900a3 arm: zynq: Use st... |
509 |
|
2a4849d26 clocksource: Conv... |
510 511 |
pr_info("%pOFn #0 at %p, irq=%d ", timer, timer_baseaddr, irq); |
70504f311 clocksource/drive... |
512 513 |
return 0; |
e932900a3 arm: zynq: Use st... |
514 |
} |
172733959 clocksource/drive... |
515 |
TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |