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include/linux/ide.h
45.5 KB
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#ifndef _IDE_H #define _IDE_H /* * linux/include/linux/ide.h * * Copyright (C) 1994-2002 Linus Torvalds & authors */ |
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#include <linux/init.h> #include <linux/ioport.h> |
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#include <linux/ata.h> |
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#include <linux/blkdev.h> #include <linux/proc_fs.h> #include <linux/interrupt.h> #include <linux/bitops.h> #include <linux/bio.h> |
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#include <linux/pci.h> |
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#include <linux/completion.h> |
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#include <linux/pm.h> |
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#include <linux/mutex.h> |
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/* for request_sense */ #include <linux/cdrom.h> |
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#include <asm/byteorder.h> #include <asm/io.h> |
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#if defined(CONFIG_CRIS) || defined(CONFIG_FRV) || defined(CONFIG_MN10300) |
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# define SUPPORT_VLB_SYNC 0 #else # define SUPPORT_VLB_SYNC 1 |
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#endif |
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/* * Probably not wise to fiddle with these */ |
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#define IDE_DEFAULT_MAX_FAILURES 1 |
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#define ERROR_MAX 8 /* Max read/write errors per sector */ #define ERROR_RESET 3 /* Reset controller every 4th retry */ #define ERROR_RECAL 1 /* Recalibrate every 2nd retry */ |
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struct device; |
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/* IDE-specific values for req->cmd_type */ enum ata_cmd_type_bits { REQ_TYPE_ATA_TASKFILE = REQ_TYPE_DRV_PRIV + 1, REQ_TYPE_ATA_PC, |
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REQ_TYPE_ATA_SENSE, /* sense request */ |
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REQ_TYPE_ATA_PM_SUSPEND,/* suspend request */ REQ_TYPE_ATA_PM_RESUME, /* resume request */ |
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}; |
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#define ata_pm_request(rq) \ ((rq)->cmd_type == REQ_TYPE_ATA_PM_SUSPEND || \ (rq)->cmd_type == REQ_TYPE_ATA_PM_RESUME) |
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/* Error codes returned in rq->errors to the higher part of the driver. */ enum { IDE_DRV_ERROR_GENERAL = 101, IDE_DRV_ERROR_FILEMARK = 102, IDE_DRV_ERROR_EOD = 103, }; |
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/* * Definitions for accessing IDE controller registers */ #define IDE_NR_PORTS (10) |
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struct ide_io_ports { unsigned long data_addr; union { unsigned long error_addr; /* read: error */ unsigned long feature_addr; /* write: feature */ }; unsigned long nsect_addr; unsigned long lbal_addr; unsigned long lbam_addr; unsigned long lbah_addr; unsigned long device_addr; union { unsigned long status_addr; /* read: status */ unsigned long command_addr; /* write: command */ }; unsigned long ctl_addr; unsigned long irq_addr; }; |
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#define OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good)) |
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#define BAD_R_STAT (ATA_BUSY | ATA_ERR) #define BAD_W_STAT (BAD_R_STAT | ATA_DF) #define BAD_STAT (BAD_R_STAT | ATA_DRQ) #define DRIVE_READY (ATA_DRDY | ATA_DSC) #define BAD_CRC (ATA_ABORTED | ATA_ICRC) |
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#define SATA_NR_PORTS (3) /* 16 possible ?? */ #define SATA_STATUS_OFFSET (0) |
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#define SATA_ERROR_OFFSET (1) |
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#define SATA_CONTROL_OFFSET (2) |
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/* * Our Physical Region Descriptor (PRD) table should be large enough * to handle the biggest I/O request we are likely to see. Since requests * can have no more than 256 sectors, and since the typical blocksize is * two or more sectors, we could get by with a limit of 128 entries here for * the usual worst case. Most requests seem to include some contiguous blocks, * further reducing the number of table entries required. * * The driver reverts to PIO mode for individual requests that exceed * this limit (possible with 512 byte blocksizes, eg. MSDOS f/s), so handling * 100% of all crazy scenarios here is not necessary. * * As it turns out though, we must allocate a full 4KB page for this, * so the two PRD tables (ide0 & ide1) will each get half of that, * allowing each to have about 256 entries (8 bytes each) from this. */ #define PRD_BYTES 8 #define PRD_ENTRIES 256 /* * Some more useful definitions */ #define PARTN_BITS 6 /* number of minor dev bits for partitions */ #define MAX_DRIVES 2 /* per interface; 2 assumed by lots of code */ #define SECTOR_SIZE 512 |
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/* * Timeouts for various operations: */ |
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enum { |
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/* spec allows up to 20ms, but CF cards and SSD drives need more */ WAIT_DRQ = 1 * HZ, /* 1s */ |
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/* some laptops are very slow */ WAIT_READY = 5 * HZ, /* 5s */ /* should be less than 3ms (?), if all ATAPI CD is closed at boot */ WAIT_PIDENTIFY = 10 * HZ, /* 10s */ /* worst case when spinning up */ WAIT_WORSTCASE = 30 * HZ, /* 30s */ /* maximum wait for an IRQ to happen */ WAIT_CMD = 10 * HZ, /* 10s */ /* Some drives require a longer IRQ timeout. */ WAIT_FLOPPY_CMD = 50 * HZ, /* 50s */ /* * Some drives (for example, Seagate STT3401A Travan) require a very * long timeout, because they don't return an interrupt or clear their * BSY bit until after the command completes (even retension commands). */ WAIT_TAPE_CMD = 900 * HZ, /* 900s */ /* minimum sleep time */ WAIT_MIN_SLEEP = HZ / 50, /* 20ms */ }; |
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/* |
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* Op codes for special requests to be handled by ide_special_rq(). * Values should be in the range of 0x20 to 0x3f. */ #define REQ_DRIVE_RESET 0x20 |
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#define REQ_DEVSET_EXEC 0x21 |
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#define REQ_PARK_HEADS 0x22 #define REQ_UNPARK_HEADS 0x23 |
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/* |
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* hwif_chipset_t is used to keep track of the specific hardware * chipset used by each IDE interface, if known. */ |
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enum { ide_unknown, ide_generic, ide_pci, |
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ide_cmd640, ide_dtc2278, ide_ali14xx, ide_qd65xx, ide_umc8672, ide_ht6560b, |
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ide_4drives, ide_pmac, ide_acorn, |
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ide_au1xxx, ide_palm3710 |
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}; typedef u8 hwif_chipset_t; |
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/* * Structure to hold all information about the location of this port */ |
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struct ide_hw { |
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union { struct ide_io_ports io_ports; unsigned long io_ports_array[IDE_NR_PORTS]; }; |
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int irq; /* our irq number */ |
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struct device *dev, *parent; |
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unsigned long config; |
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}; |
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static inline void ide_std_init_ports(struct ide_hw *hw, |
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unsigned long io_addr, unsigned long ctl_addr) { unsigned int i; |
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for (i = 0; i <= 7; i++) hw->io_ports_array[i] = io_addr++; |
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hw->io_ports.ctl_addr = ctl_addr; |
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} |
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#define MAX_HWIFS 10 |
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/* * Now for the data we need to maintain per-drive: ide_drive_t */ #define ide_scsi 0x21 #define ide_disk 0x20 #define ide_optical 0x7 #define ide_cdrom 0x5 #define ide_tape 0x1 #define ide_floppy 0x0 /* * Special Driver Flags |
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*/ |
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enum { IDE_SFLAG_SET_GEOMETRY = (1 << 0), IDE_SFLAG_RECALIBRATE = (1 << 1), IDE_SFLAG_SET_MULTMODE = (1 << 2), }; |
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/* |
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* Status returned from various ide_ functions */ typedef enum { ide_stopped, /* no drive operation was started */ ide_started, /* a drive operation was started, handler was set */ } ide_startstop_t; |
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enum { |
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IDE_VALID_ERROR = (1 << 1), IDE_VALID_FEATURE = IDE_VALID_ERROR, IDE_VALID_NSECT = (1 << 2), IDE_VALID_LBAL = (1 << 3), IDE_VALID_LBAM = (1 << 4), IDE_VALID_LBAH = (1 << 5), IDE_VALID_DEVICE = (1 << 6), IDE_VALID_LBA = IDE_VALID_LBAL | IDE_VALID_LBAM | IDE_VALID_LBAH, IDE_VALID_OUT_TF = IDE_VALID_FEATURE | IDE_VALID_NSECT | IDE_VALID_LBA, IDE_VALID_IN_TF = IDE_VALID_NSECT | IDE_VALID_LBA, IDE_VALID_OUT_HOB = IDE_VALID_OUT_TF, IDE_VALID_IN_HOB = IDE_VALID_ERROR | IDE_VALID_NSECT | IDE_VALID_LBA, }; enum { |
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IDE_TFLAG_LBA48 = (1 << 0), |
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IDE_TFLAG_WRITE = (1 << 1), IDE_TFLAG_CUSTOM_HANDLER = (1 << 2), IDE_TFLAG_DMA_PIO_FALLBACK = (1 << 3), |
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/* force 16-bit I/O operations */ |
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IDE_TFLAG_IO_16BIT = (1 << 4), |
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/* struct ide_cmd was allocated using kmalloc() */ |
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IDE_TFLAG_DYN = (1 << 5), IDE_TFLAG_FS = (1 << 6), IDE_TFLAG_MULTI_PIO = (1 << 7), |
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IDE_TFLAG_SET_XFER = (1 << 8), |
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}; enum { IDE_FTFLAG_FLAGGED = (1 << 0), IDE_FTFLAG_SET_IN_FLAGS = (1 << 1), IDE_FTFLAG_OUT_DATA = (1 << 2), IDE_FTFLAG_IN_DATA = (1 << 3), |
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}; struct ide_taskfile { |
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u8 data; /* 0: data byte (for TASKFILE ioctl) */ union { /* 1: */ u8 error; /* read: error */ u8 feature; /* write: feature */ |
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}; |
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u8 nsect; /* 2: number of sectors */ u8 lbal; /* 3: LBA low */ u8 lbam; /* 4: LBA mid */ u8 lbah; /* 5: LBA high */ u8 device; /* 6: device select */ union { /* 7: */ u8 status; /* read: status */ |
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u8 command; /* write: command */ }; }; |
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struct ide_cmd { |
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struct ide_taskfile tf; struct ide_taskfile hob; |
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struct { struct { u8 tf; u8 hob; } out, in; } valid; |
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u16 tf_flags; |
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u8 ftf_flags; /* for TASKFILE ioctl */ |
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int protocol; |
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int sg_nents; /* number of sg entries */ int orig_sg_nents; int sg_dma_direction; /* DMA transfer direction */ |
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unsigned int nbytes; |
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unsigned int nleft; |
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unsigned int last_xfer_len; |
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struct scatterlist *cursg; unsigned int cursg_ofs; |
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struct request *rq; /* copy of request */ |
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}; |
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/* ATAPI packet command flags */ enum { /* set when an error is considered normal - no retry (ide-tape) */ PC_FLAG_ABORT = (1 << 0), PC_FLAG_SUPPRESS_ERROR = (1 << 1), PC_FLAG_WAIT_FOR_DSC = (1 << 2), PC_FLAG_DMA_OK = (1 << 3), PC_FLAG_DMA_IN_PROGRESS = (1 << 4), PC_FLAG_DMA_ERROR = (1 << 5), PC_FLAG_WRITING = (1 << 6), |
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}; |
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#define ATAPI_WAIT_PC (60 * HZ) |
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struct ide_atapi_pc { /* actual packet bytes */ u8 c[12]; /* incremented on each retry */ int retries; int error; /* bytes to transfer */ int req_xfer; |
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/* the corresponding request */ struct request *rq; unsigned long flags; /* * those are more or less driver-specific and some of them are subject * to change/removal later. */ |
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unsigned long timeout; }; |
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struct ide_devset; |
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struct ide_driver; |
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#ifdef CONFIG_BLK_DEV_IDEACPI struct ide_acpi_drive_link; struct ide_acpi_hwif_link; #endif |
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struct ide_drive_s; struct ide_disk_ops { int (*check)(struct ide_drive_s *, const char *); int (*get_capacity)(struct ide_drive_s *); |
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void (*unlock_native_capacity)(struct ide_drive_s *); |
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void (*setup)(struct ide_drive_s *); void (*flush)(struct ide_drive_s *); int (*init_media)(struct ide_drive_s *, struct gendisk *); int (*set_doorlock)(struct ide_drive_s *, struct gendisk *, int); ide_startstop_t (*do_request)(struct ide_drive_s *, struct request *, sector_t); |
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int (*ioctl)(struct ide_drive_s *, struct block_device *, fmode_t, unsigned int, unsigned long); |
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}; |
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/* ATAPI device flags */ enum { IDE_AFLAG_DRQ_INTERRUPT = (1 << 0), |
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/* ide-cd */ |
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/* Drive cannot eject the disc. */ |
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IDE_AFLAG_NO_EJECT = (1 << 1), |
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/* Drive is a pre ATAPI 1.2 drive. */ |
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IDE_AFLAG_PRE_ATAPI12 = (1 << 2), |
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/* TOC addresses are in BCD. */ |
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IDE_AFLAG_TOCADDR_AS_BCD = (1 << 3), |
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/* TOC track numbers are in BCD. */ |
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IDE_AFLAG_TOCTRACKS_AS_BCD = (1 << 4), |
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/* Saved TOC information is current. */ |
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IDE_AFLAG_TOC_VALID = (1 << 6), |
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/* We think that the drive door is locked. */ |
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IDE_AFLAG_DOOR_LOCKED = (1 << 7), |
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/* SET_CD_SPEED command is unsupported. */ |
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IDE_AFLAG_NO_SPEED_SELECT = (1 << 8), IDE_AFLAG_VERTOS_300_SSD = (1 << 9), IDE_AFLAG_VERTOS_600_ESD = (1 << 10), IDE_AFLAG_SANYO_3CD = (1 << 11), IDE_AFLAG_FULL_CAPS_PAGE = (1 << 12), IDE_AFLAG_PLAY_AUDIO_OK = (1 << 13), IDE_AFLAG_LE_SPEED_FIELDS = (1 << 14), |
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/* ide-floppy */ |
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/* Avoid commands not supported in Clik drive */ |
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IDE_AFLAG_CLIK_DRIVE = (1 << 15), |
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/* Requires BH algorithm for packets */ |
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IDE_AFLAG_ZIP_DRIVE = (1 << 16), |
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/* Supports format progress report */ |
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IDE_AFLAG_SRFP = (1 << 17), |
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/* ide-tape */ |
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IDE_AFLAG_IGNORE_DSC = (1 << 18), |
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/* 0 When the tape position is unknown */ |
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IDE_AFLAG_ADDRESS_VALID = (1 << 19), |
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/* Device already opened */ |
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IDE_AFLAG_BUSY = (1 << 20), |
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/* Attempt to auto-detect the current user block size */ |
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IDE_AFLAG_DETECT_BS = (1 << 21), |
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/* Currently on a filemark */ |
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IDE_AFLAG_FILEMARK = (1 << 22), |
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/* 0 = no tape is loaded, so we don't rewind after ejecting */ |
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IDE_AFLAG_MEDIUM_PRESENT = (1 << 23), |
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IDE_AFLAG_NO_AUTOCLOSE = (1 << 24), |
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}; |
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/* device flags */ enum { /* restore settings after device reset */ IDE_DFLAG_KEEP_SETTINGS = (1 << 0), /* device is using DMA for read/write */ IDE_DFLAG_USING_DMA = (1 << 1), /* okay to unmask other IRQs */ IDE_DFLAG_UNMASK = (1 << 2), /* don't attempt flushes */ IDE_DFLAG_NOFLUSH = (1 << 3), /* DSC overlap */ IDE_DFLAG_DSC_OVERLAP = (1 << 4), /* give potential excess bandwidth */ IDE_DFLAG_NICE1 = (1 << 5), /* device is physically present */ IDE_DFLAG_PRESENT = (1 << 6), |
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/* disable Host Protected Area */ IDE_DFLAG_NOHPA = (1 << 7), |
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/* id read from device (synthetic if not set) */ IDE_DFLAG_ID_READ = (1 << 8), IDE_DFLAG_NOPROBE = (1 << 9), /* need to do check_media_change() */ IDE_DFLAG_REMOVABLE = (1 << 10), /* needed for removable devices */ IDE_DFLAG_ATTACH = (1 << 11), IDE_DFLAG_FORCED_GEOM = (1 << 12), /* disallow setting unmask bit */ IDE_DFLAG_NO_UNMASK = (1 << 13), /* disallow enabling 32-bit I/O */ IDE_DFLAG_NO_IO_32BIT = (1 << 14), /* for removable only: door lock/unlock works */ IDE_DFLAG_DOORLOCKING = (1 << 15), /* disallow DMA */ IDE_DFLAG_NODMA = (1 << 16), |
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/* powermanagement told us not to do anything, so sleep nicely */ |
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IDE_DFLAG_BLOCKED = (1 << 17), |
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/* sleeping & sleep field valid */ |
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IDE_DFLAG_SLEEPING = (1 << 18), IDE_DFLAG_POST_RESET = (1 << 19), IDE_DFLAG_UDMA33_WARNED = (1 << 20), IDE_DFLAG_LBA48 = (1 << 21), |
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/* status of write cache */ |
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IDE_DFLAG_WCACHE = (1 << 22), |
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/* used for ignoring ATA_DF */ |
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IDE_DFLAG_NOWERR = (1 << 23), |
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/* retrying in PIO */ |
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IDE_DFLAG_DMA_PIO_RETRY = (1 << 24), IDE_DFLAG_LBA = (1 << 25), |
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/* don't unload heads */ |
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IDE_DFLAG_NO_UNLOAD = (1 << 26), |
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/* heads unloaded, please don't reset port */ |
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IDE_DFLAG_PARKED = (1 << 27), IDE_DFLAG_MEDIA_CHANGED = (1 << 28), |
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/* write protect */ |
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IDE_DFLAG_WP = (1 << 29), IDE_DFLAG_FORMAT_IN_PROGRESS = (1 << 30), |
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IDE_DFLAG_NIEN_QUIRK = (1 << 31), |
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}; |
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struct ide_drive_s { |
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char name[4]; /* drive name, such as "hda" */ char driver_req[10]; /* requests specific driver */ |
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struct request_queue *queue; /* request queue */ |
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struct request *rq; /* current request */ |
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void *driver_data; /* extra driver data */ |
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u16 *id; /* identification info */ |
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#ifdef CONFIG_IDE_PROC_FS |
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struct proc_dir_entry *proc; /* /proc/ide/ directory entry */ |
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const struct ide_proc_devset *settings; /* /proc/ide/ drive settings */ |
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#endif |
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struct hwif_s *hwif; /* actually (ide_hwif_t *) */ |
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const struct ide_disk_ops *disk_ops; |
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unsigned long dev_flags; |
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unsigned long sleep; /* sleep until this time */ |
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unsigned long timeout; /* max time to wait for irq */ |
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u8 special_flags; /* special action flags */ |
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491 |
u8 select; /* basic drive/head select reg value */ |
1da177e4c
|
492 |
u8 retry_pio; /* retrying dma capable host in pio */ |
1da177e4c
|
493 |
u8 waiting_for_dma; /* dma currently in progress */ |
0a9b6f886
|
494 |
u8 dma; /* atapi dma flag */ |
1da177e4c
|
495 |
|
1da177e4c
|
496 |
u8 init_speed; /* transfer rate set at boot */ |
1da177e4c
|
497 |
u8 current_speed; /* current transfer rate set */ |
513daadd1
|
498 |
u8 desired_speed; /* desired transfer rate set */ |
d2d4e780a
|
499 |
u8 pio_mode; /* for ->set_pio_mode _only_ */ |
54a4ec469
|
500 501 |
u8 dma_mode; /* for ->set_dma_mode _only_ */ u8 dn; /* now wide spread use */ |
1da177e4c
|
502 503 |
u8 acoustic; /* acoustic management */ u8 media; /* disk, cdrom, tape, floppy, ... */ |
1da177e4c
|
504 505 506 |
u8 ready_stat; /* min status value for drive ready */ u8 mult_count; /* current multiple sector setting */ u8 mult_req; /* requested multiple sector setting */ |
1da177e4c
|
507 |
u8 io_32bit; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */ |
3a7d24841
|
508 |
u8 bad_wstat; /* used for ignoring ATA_DF */ |
1da177e4c
|
509 510 511 512 |
u8 head; /* "real" number of heads */ u8 sect; /* "real" sectors per track */ u8 bios_head; /* BIOS/fdisk/LILO number of heads */ u8 bios_sect; /* BIOS/fdisk/LILO sectors per track */ |
baf08f0be
|
513 514 |
/* delay this long before sending packet command */ u8 pc_delay; |
1da177e4c
|
515 516 |
unsigned int bios_cyl; /* BIOS/fdisk/LILO number of cyls */ unsigned int cyl; /* "real" number of cyls */ |
5bfb151f1
|
517 |
void *drive_data; /* used by set_pio_mode/dev_select() */ |
1da177e4c
|
518 519 |
unsigned int failures; /* current failure count */ unsigned int max_failures; /* maximum allowed failure count */ |
e957b60d1
|
520 |
u64 probed_capacity;/* initial/native media capacity */ |
1da177e4c
|
521 522 523 524 |
u64 capacity64; /* total number of sectors */ int lun; /* logical unit */ int crc_count; /* crc counter to reduce drive speed */ |
b22b2ca4f
|
525 526 |
unsigned long debug_mask; /* debugging levels switch */ |
e3a59b4d9
|
527 528 529 |
#ifdef CONFIG_BLK_DEV_IDEACPI struct ide_acpi_drive_link *acpidata; #endif |
1da177e4c
|
530 531 |
struct list_head list; struct device gendev; |
f36d4024c
|
532 |
struct completion gendev_rel_comp; /* to deal with device release() */ |
d7c26ebb5
|
533 |
|
2b9efba48
|
534 535 |
/* current packet command */ struct ide_atapi_pc *pc; |
5e2040fd0
|
536 537 |
/* last failed packet command */ struct ide_atapi_pc *failed_pc; |
d7c26ebb5
|
538 |
/* callback for packet commands */ |
03a2faaea
|
539 |
int (*pc_callback)(struct ide_drive_s *, int); |
3b8ac5398
|
540 |
|
d6251d448
|
541 |
ide_startstop_t (*irq_handler)(struct ide_drive_s *); |
3b8ac5398
|
542 |
unsigned long atapi_flags; |
67c56364d
|
543 544 |
struct ide_atapi_pc request_sense_pc; |
a1df5169f
|
545 546 547 548 549 |
/* current sense rq and buffer */ bool sense_rq_armed; struct request sense_rq; struct request_sense sense_data; |
d7c26ebb5
|
550 551 552 |
}; typedef struct ide_drive_s ide_drive_t; |
1da177e4c
|
553 |
|
5aeddf907
|
554 555 556 |
#define to_ide_device(dev) container_of(dev, ide_drive_t, gendev) #define to_ide_drv(obj, cont_type) \ |
8fed43684
|
557 |
container_of(obj, struct cont_type, dev) |
5aeddf907
|
558 559 560 |
#define ide_drv_g(disk, cont_type) \ container_of((disk)->private_data, struct cont_type, driver) |
8604affde
|
561 |
|
039788e15
|
562 |
struct ide_port_info; |
1da177e4c
|
563 |
|
374e042c3
|
564 565 566 567 |
struct ide_tp_ops { void (*exec_command)(struct hwif_s *, u8); u8 (*read_status)(struct hwif_s *); u8 (*read_altstatus)(struct hwif_s *); |
ecf3a31d2
|
568 |
void (*write_devctl)(struct hwif_s *, u8); |
374e042c3
|
569 |
|
abb596b25
|
570 |
void (*dev_select)(ide_drive_t *); |
c9ff9e7b6
|
571 |
void (*tf_load)(ide_drive_t *, struct ide_taskfile *, u8); |
3153c26b5
|
572 |
void (*tf_read)(ide_drive_t *, struct ide_taskfile *, u8); |
374e042c3
|
573 |
|
adb1af980
|
574 575 576 577 |
void (*input_data)(ide_drive_t *, struct ide_cmd *, void *, unsigned int); void (*output_data)(ide_drive_t *, struct ide_cmd *, void *, unsigned int); |
374e042c3
|
578 579 580 |
}; extern const struct ide_tp_ops default_tp_ops; |
39b986a6c
|
581 582 583 584 585 586 |
/** * struct ide_port_ops - IDE port operations * * @init_dev: host specific initialization of a device * @set_pio_mode: routine to program host for PIO mode * @set_dma_mode: routine to program host for DMA mode |
39b986a6c
|
587 588 589 590 591 |
* @reset_poll: chipset polling based on hba specifics * @pre_reset: chipset specific changes to default for device-hba resets * @resetproc: routine to reset controller after a disk reset * @maskproc: special host masking for drive selection * @quirkproc: check host's drive quirk list |
bfa7d8e55
|
592 |
* @clear_irq: clear IRQ |
39b986a6c
|
593 594 595 596 597 598 |
* * @mdma_filter: filter MDMA modes * @udma_filter: filter UDMA modes * * @cable_detect: detect cable type */ |
ac95beedf
|
599 |
struct ide_port_ops { |
e6d95bd14
|
600 |
void (*init_dev)(ide_drive_t *); |
e085b3cae
|
601 |
void (*set_pio_mode)(struct hwif_s *, ide_drive_t *); |
8776168ca
|
602 |
void (*set_dma_mode)(struct hwif_s *, ide_drive_t *); |
ac95beedf
|
603 |
int (*reset_poll)(ide_drive_t *); |
ac95beedf
|
604 |
void (*pre_reset)(ide_drive_t *); |
ac95beedf
|
605 |
void (*resetproc)(ide_drive_t *); |
ac95beedf
|
606 |
void (*maskproc)(ide_drive_t *, int); |
ac95beedf
|
607 |
void (*quirkproc)(ide_drive_t *); |
bfa7d8e55
|
608 |
void (*clear_irq)(ide_drive_t *); |
f4d3ffa52
|
609 |
int (*test_irq)(struct hwif_s *); |
ac95beedf
|
610 611 612 613 614 615 |
u8 (*mdma_filter)(ide_drive_t *); u8 (*udma_filter)(ide_drive_t *); u8 (*cable_detect)(struct hwif_s *); }; |
5e37bdc08
|
616 617 |
struct ide_dma_ops { void (*dma_host_set)(struct ide_drive_s *, int); |
229816941
|
618 |
int (*dma_setup)(struct ide_drive_s *, struct ide_cmd *); |
5e37bdc08
|
619 620 621 622 |
void (*dma_start)(struct ide_drive_s *); int (*dma_end)(struct ide_drive_s *); int (*dma_test_irq)(struct ide_drive_s *); void (*dma_lost_irq)(struct ide_drive_s *); |
35c9b4daf
|
623 |
/* below ones are optional */ |
8a4a5738b
|
624 |
int (*dma_check)(struct ide_drive_s *, struct ide_cmd *); |
22117d6ea
|
625 |
int (*dma_timer_expiry)(struct ide_drive_s *); |
35c9b4daf
|
626 |
void (*dma_clear)(struct ide_drive_s *); |
592b53152
|
627 628 629 630 631 |
/* * The following method is optional and only required to be * implemented for the SFF-8038i compatible controllers. */ u8 (*dma_sff_read_status)(struct hwif_s *); |
5e37bdc08
|
632 |
}; |
5880b5de7
|
633 634 635 |
enum { IDE_PFLAG_PROBING = (1 << 0), }; |
08da591e1
|
636 |
struct ide_host; |
1da177e4c
|
637 |
typedef struct hwif_s { |
1da177e4c
|
638 |
struct hwif_s *mate; /* other hwif from same PCI chip */ |
1da177e4c
|
639 |
struct proc_dir_entry *proc; /* /proc/ide/ directory entry */ |
08da591e1
|
640 |
struct ide_host *host; |
1da177e4c
|
641 |
char name[6]; /* name of interface, eg. "ide0" */ |
4c3032d8a
|
642 |
struct ide_io_ports io_ports; |
1da177e4c
|
643 |
unsigned long sata_scr[SATA_NR_PORTS]; |
1da177e4c
|
644 |
|
2bd24a1cf
|
645 |
ide_drive_t *devices[MAX_DRIVES + 1]; |
1da177e4c
|
646 |
|
5880b5de7
|
647 |
unsigned long port_flags; |
1da177e4c
|
648 649 650 |
u8 major; /* our major number */ u8 index; /* 0 for ide0; 1 for ide1; ... */ u8 channel; /* for dual-port chips: 0=primary, 1=secondary */ |
1da177e4c
|
651 |
|
e95d9c6b0
|
652 |
u32 host_flags; |
6a824c92d
|
653 |
|
4099d1432
|
654 |
u8 pio_mask; |
1da177e4c
|
655 656 657 |
u8 ultra_mask; u8 mwdma_mask; u8 swdma_mask; |
49521f97c
|
658 |
u8 cbl; /* cable type */ |
1da177e4c
|
659 |
hwif_chipset_t chipset; /* sub-module for tuning.. */ |
36501650e
|
660 |
struct device *dev; |
1da177e4c
|
661 |
void (*rw_disk)(ide_drive_t *, struct request *); |
374e042c3
|
662 |
const struct ide_tp_ops *tp_ops; |
ac95beedf
|
663 |
const struct ide_port_ops *port_ops; |
f37afdaca
|
664 |
const struct ide_dma_ops *dma_ops; |
bfa14b42a
|
665 |
|
1da177e4c
|
666 667 668 669 |
/* dma physical region descriptor table (cpu view) */ unsigned int *dmatable_cpu; /* dma physical region descriptor table (dma view) */ dma_addr_t dmatable_dma; |
2bbd57cad
|
670 671 672 673 674 |
/* maximum number of PRD table entries */ int prd_max_nents; /* PRD entry size in bytes */ int prd_ent_size; |
1da177e4c
|
675 676 677 |
/* Scatter-gather list used to build the above */ struct scatterlist *sg_table; int sg_max_nents; /* Maximum number of entries in it */ |
1da177e4c
|
678 |
|
22aa4b32a
|
679 |
struct ide_cmd cmd; /* current command */ |
d6ff9f64e
|
680 |
|
1da177e4c
|
681 682 |
int rqsize; /* max sectors per request */ int irq; /* our irq number */ |
1da177e4c
|
683 |
unsigned long dma_base; /* base addr for dma ports */ |
1da177e4c
|
684 |
|
1da177e4c
|
685 686 |
unsigned long config_data; /* for use by chipset-specific code */ unsigned long select_data; /* for use by chipset-specific code */ |
020e322de
|
687 688 |
unsigned long extra_base; /* extra addr for dma ports */ unsigned extra_ports; /* number of extra dma ports */ |
1da177e4c
|
689 |
unsigned present : 1; /* this interface exists */ |
5b31f855f
|
690 |
unsigned busy : 1; /* serializes devices on a port */ |
1da177e4c
|
691 |
|
f74c91413
|
692 693 |
struct device gendev; struct device *portdev; |
f36d4024c
|
694 |
struct completion gendev_rel_comp; /* To deal with device release() */ |
1da177e4c
|
695 696 |
void *hwif_data; /* extra hwif data */ |
e3a59b4d9
|
697 698 699 |
#ifdef CONFIG_BLK_DEV_IDEACPI struct ide_acpi_hwif_link *acpidata; #endif |
b65fac32c
|
700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 |
/* IRQ handler, if active */ ide_startstop_t (*handler)(ide_drive_t *); /* BOOL: polling active & poll_timeout field valid */ unsigned int polling : 1; /* current drive */ ide_drive_t *cur_dev; /* current request */ struct request *rq; /* failsafe timer */ struct timer_list timer; /* timeout value during long polls */ unsigned long poll_timeout; /* queried upon timeouts */ int (*expiry)(ide_drive_t *); int req_gen; int req_gen_timer; spinlock_t lock; |
22fc6eccb
|
724 |
} ____cacheline_internodealigned_in_smp ide_hwif_t; |
1da177e4c
|
725 |
|
a36223b0d
|
726 |
#define MAX_HOST_PORTS 4 |
48c3c1072
|
727 |
struct ide_host { |
2bd24a1cf
|
728 |
ide_hwif_t *ports[MAX_HOST_PORTS + 1]; |
48c3c1072
|
729 |
unsigned int n_ports; |
6cdf6eb35
|
730 |
struct device *dev[2]; |
e354c1d80
|
731 |
|
2ed0ef543
|
732 |
int (*init_chipset)(struct pci_dev *); |
e354c1d80
|
733 734 735 |
void (*get_lock)(irq_handler_t, void *); void (*release_lock)(void); |
849d71300
|
736 |
irq_handler_t irq_handler; |
e354c1d80
|
737 |
|
ef0b04276
|
738 |
unsigned long host_flags; |
255115fb3
|
739 740 |
int irq_flags; |
6cdf6eb35
|
741 |
void *host_priv; |
bd53cbcce
|
742 |
ide_hwif_t *cur_port; /* for hosts requiring serialization */ |
5b31f855f
|
743 744 |
/* used for hosts requiring serialization */ |
e720b9e49
|
745 |
volatile unsigned long host_busy; |
48c3c1072
|
746 |
}; |
5b31f855f
|
747 |
#define IDE_HOST_BUSY 0 |
1da177e4c
|
748 749 750 |
/* * internal ide interrupt handler type */ |
1da177e4c
|
751 752 |
typedef ide_startstop_t (ide_handler_t)(ide_drive_t *); typedef int (ide_expiry_t)(ide_drive_t *); |
0eea6458c
|
753 |
/* used by ide-cd, ide-floppy, etc. */ |
adb1af980
|
754 |
typedef void (xfer_func_t)(ide_drive_t *, struct ide_cmd *, void *, unsigned); |
0eea6458c
|
755 |
|
f9383c426
|
756 |
extern struct mutex ide_setting_mtx; |
1da177e4c
|
757 |
|
92f1f8fd8
|
758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 |
/* * configurable drive settings */ #define DS_SYNC (1 << 0) struct ide_devset { int (*get)(ide_drive_t *); int (*set)(ide_drive_t *, int); unsigned int flags; }; #define __DEVSET(_flags, _get, _set) { \ .flags = _flags, \ .get = _get, \ .set = _set, \ } |
7662d046d
|
775 |
|
8185d5aa9
|
776 |
#define ide_devset_get(name, field) \ |
92f1f8fd8
|
777 |
static int get_##name(ide_drive_t *drive) \ |
8185d5aa9
|
778 779 780 781 782 |
{ \ return drive->field; \ } #define ide_devset_set(name, field) \ |
92f1f8fd8
|
783 |
static int set_##name(ide_drive_t *drive, int arg) \ |
8185d5aa9
|
784 785 786 787 |
{ \ drive->field = arg; \ return 0; \ } |
97100fc81
|
788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 |
#define ide_devset_get_flag(name, flag) \ static int get_##name(ide_drive_t *drive) \ { \ return !!(drive->dev_flags & flag); \ } #define ide_devset_set_flag(name, flag) \ static int set_##name(ide_drive_t *drive, int arg) \ { \ if (arg) \ drive->dev_flags |= flag; \ else \ drive->dev_flags &= ~flag; \ return 0; \ } |
92f1f8fd8
|
803 804 805 806 807 808 809 810 811 812 813 814 |
#define __IDE_DEVSET(_name, _flags, _get, _set) \ const struct ide_devset ide_devset_##_name = \ __DEVSET(_flags, _get, _set) #define IDE_DEVSET(_name, _flags, _get, _set) \ static __IDE_DEVSET(_name, _flags, _get, _set) #define ide_devset_rw(_name, _func) \ IDE_DEVSET(_name, 0, get_##_func, set_##_func) #define ide_devset_w(_name, _func) \ IDE_DEVSET(_name, 0, NULL, set_##_func) |
f87904898
|
815 816 817 818 819 |
#define ide_ext_devset_rw(_name, _func) \ __IDE_DEVSET(_name, 0, get_##_func, set_##_func) #define ide_ext_devset_rw_sync(_name, _func) \ __IDE_DEVSET(_name, DS_SYNC, get_##_func, set_##_func) |
92f1f8fd8
|
820 821 822 823 824 825 826 827 828 |
#define ide_decl_devset(_name) \ extern const struct ide_devset ide_devset_##_name ide_decl_devset(io_32bit); ide_decl_devset(keepsettings); ide_decl_devset(pio_mode); ide_decl_devset(unmaskirq); ide_decl_devset(using_dma); |
7662d046d
|
829 |
#ifdef CONFIG_IDE_PROC_FS |
1da177e4c
|
830 |
/* |
92f1f8fd8
|
831 |
* /proc/ide interface |
1da177e4c
|
832 |
*/ |
92f1f8fd8
|
833 834 835 836 |
#define ide_devset_rw_field(_name, _field) \ ide_devset_get(_name, _field); \ ide_devset_set(_name, _field); \ IDE_DEVSET(_name, DS_SYNC, get_##_name, set_##_name) |
97100fc81
|
837 838 839 840 |
#define ide_devset_rw_flag(_name, _field) \ ide_devset_get_flag(_name, _field); \ ide_devset_set_flag(_name, _field); \ IDE_DEVSET(_name, DS_SYNC, get_##_name, set_##_name) |
92f1f8fd8
|
841 842 843 844 845 846 |
struct ide_proc_devset { const char *name; const struct ide_devset *setting; int min, max; int (*mulf)(ide_drive_t *); int (*divf)(ide_drive_t *); |
8185d5aa9
|
847 |
}; |
92f1f8fd8
|
848 849 850 851 852 853 854 |
#define __IDE_PROC_DEVSET(_name, _min, _max, _mulf, _divf) { \ .name = __stringify(_name), \ .setting = &ide_devset_##_name, \ .min = _min, \ .max = _max, \ .mulf = _mulf, \ .divf = _divf, \ |
8185d5aa9
|
855 |
} |
92f1f8fd8
|
856 857 |
#define IDE_PROC_DEVSET(_name, _min, _max) \ __IDE_PROC_DEVSET(_name, _min, _max, NULL, NULL) |
8185d5aa9
|
858 |
|
1da177e4c
|
859 860 |
typedef struct { const char *name; |
d161a13f9
|
861 |
umode_t mode; |
6d703a81a
|
862 |
const struct file_operations *proc_fops; |
1da177e4c
|
863 |
} ide_proc_entry_t; |
ecfd80e4a
|
864 865 |
void proc_ide_create(void); void proc_ide_destroy(void); |
5cbf79cdb
|
866 |
void ide_proc_register_port(ide_hwif_t *); |
d9270a3f1
|
867 |
void ide_proc_port_register_devices(ide_hwif_t *); |
5b0c4b30a
|
868 |
void ide_proc_unregister_device(ide_drive_t *); |
5cbf79cdb
|
869 |
void ide_proc_unregister_port(ide_hwif_t *); |
7f3c868ba
|
870 871 |
void ide_proc_register_driver(ide_drive_t *, struct ide_driver *); void ide_proc_unregister_driver(ide_drive_t *, struct ide_driver *); |
7662d046d
|
872 |
|
6d703a81a
|
873 874 |
extern const struct file_operations ide_capacity_proc_fops; extern const struct file_operations ide_geometry_proc_fops; |
1da177e4c
|
875 |
#else |
ecfd80e4a
|
876 877 |
static inline void proc_ide_create(void) { ; } static inline void proc_ide_destroy(void) { ; } |
5cbf79cdb
|
878 |
static inline void ide_proc_register_port(ide_hwif_t *hwif) { ; } |
d9270a3f1
|
879 |
static inline void ide_proc_port_register_devices(ide_hwif_t *hwif) { ; } |
5b0c4b30a
|
880 |
static inline void ide_proc_unregister_device(ide_drive_t *drive) { ; } |
5cbf79cdb
|
881 |
static inline void ide_proc_unregister_port(ide_hwif_t *hwif) { ; } |
7f3c868ba
|
882 883 884 885 |
static inline void ide_proc_register_driver(ide_drive_t *drive, struct ide_driver *driver) { ; } static inline void ide_proc_unregister_driver(ide_drive_t *drive, struct ide_driver *driver) { ; } |
1da177e4c
|
886 |
#endif |
e1c7c4641
|
887 888 889 890 891 892 893 894 895 896 897 898 899 900 |
enum { /* enter/exit functions */ IDE_DBG_FUNC = (1 << 0), /* sense key/asc handling */ IDE_DBG_SENSE = (1 << 1), /* packet commands handling */ IDE_DBG_PC = (1 << 2), /* request handling */ IDE_DBG_RQ = (1 << 3), /* driver probing/setup */ IDE_DBG_PROBE = (1 << 4), }; /* DRV_NAME has to be defined in the driver before using the macro below */ |
088b1b886
|
901 902 903 904 905 906 |
#define __ide_debug_log(lvl, fmt, args...) \ { \ if (unlikely(drive->debug_mask & lvl)) \ printk(KERN_INFO DRV_NAME ": %s: " fmt " ", \ __func__, ## args); \ |
e1c7c4641
|
907 |
} |
1da177e4c
|
908 |
/* |
0d346ba07
|
909 |
* Power Management state machine (rq->pm->pm_step). |
1da177e4c
|
910 |
* |
0d346ba07
|
911 |
* For each step, the core calls ide_start_power_step() first. |
1da177e4c
|
912 913 914 915 916 |
* This can return: * - ide_stopped : In this case, the core calls us back again unless * step have been set to ide_power_state_completed. * - ide_started : In this case, the channel is left busy until an * async event (interrupt) occurs. |
0d346ba07
|
917 |
* Typically, ide_start_power_step() will issue a taskfile request with |
1da177e4c
|
918 919 |
* do_rw_taskfile(). * |
0d346ba07
|
920 |
* Upon reception of the interrupt, the core will call ide_complete_power_step() |
1da177e4c
|
921 922 |
* with the error code if any. This routine should update the step value * and return. It should not start a new request. The core will call |
0d346ba07
|
923 924 |
* ide_start_power_step() for the new step value, unless step have been * set to IDE_PM_COMPLETED. |
1da177e4c
|
925 |
*/ |
1da177e4c
|
926 |
enum { |
0d346ba07
|
927 928 929 930 931 932 933 934 935 936 |
IDE_PM_START_SUSPEND, IDE_PM_FLUSH_CACHE = IDE_PM_START_SUSPEND, IDE_PM_STANDBY, IDE_PM_START_RESUME, IDE_PM_RESTORE_PIO = IDE_PM_START_RESUME, IDE_PM_IDLE, IDE_PM_RESTORE_DMA, IDE_PM_COMPLETED, |
1da177e4c
|
937 |
}; |
e2984c628
|
938 939 940 941 942 |
int generic_ide_suspend(struct device *, pm_message_t); int generic_ide_resume(struct device *); void ide_complete_power_step(ide_drive_t *, struct request *); ide_startstop_t ide_start_power_step(ide_drive_t *, struct request *); |
3616b6536
|
943 |
void ide_complete_pm_rq(ide_drive_t *, struct request *); |
e2984c628
|
944 |
void ide_check_pm_state(ide_drive_t *, struct request *); |
1da177e4c
|
945 946 |
/* * Subdrivers support. |
4ef3b8f4a
|
947 948 949 |
* * The gendriver.owner field should be set to the module owner of this driver. * The gendriver.name field should be set to the name of this driver |
1da177e4c
|
950 |
*/ |
7f3c868ba
|
951 |
struct ide_driver { |
1da177e4c
|
952 |
const char *version; |
1da177e4c
|
953 |
ide_startstop_t (*do_request)(ide_drive_t *, struct request *, sector_t); |
1da177e4c
|
954 |
struct device_driver gen_driver; |
4031bbe4b
|
955 956 |
int (*probe)(ide_drive_t *); void (*remove)(ide_drive_t *); |
0d2157f78
|
957 |
void (*resume)(ide_drive_t *); |
4031bbe4b
|
958 |
void (*shutdown)(ide_drive_t *); |
7662d046d
|
959 |
#ifdef CONFIG_IDE_PROC_FS |
79cb38039
|
960 961 |
ide_proc_entry_t * (*proc_entries)(ide_drive_t *); const struct ide_proc_devset * (*proc_devsets)(ide_drive_t *); |
7662d046d
|
962 963 |
#endif }; |
1da177e4c
|
964 |
|
7f3c868ba
|
965 |
#define to_ide_driver(drv) container_of(drv, struct ide_driver, gen_driver) |
4031bbe4b
|
966 |
|
08da591e1
|
967 968 |
int ide_device_get(ide_drive_t *); void ide_device_put(ide_drive_t *); |
aa7687738
|
969 970 971 |
struct ide_ioctl_devset { unsigned int get_ioctl; unsigned int set_ioctl; |
92f1f8fd8
|
972 |
const struct ide_devset *setting; |
aa7687738
|
973 974 975 976 |
}; int ide_setting_ioctl(ide_drive_t *, struct block_device *, unsigned int, unsigned long, const struct ide_ioctl_devset *); |
1bddd9e64
|
977 |
int generic_ide_ioctl(ide_drive_t *, struct block_device *, unsigned, unsigned long); |
1da177e4c
|
978 |
|
ebae41a5a
|
979 980 |
extern int ide_vlb_clk; extern int ide_pci_clk; |
1caf236da
|
981 |
int ide_end_rq(ide_drive_t *, struct request *, int, unsigned int); |
327fa1c29
|
982 |
void ide_kill_rq(ide_drive_t *, struct request *); |
60c0cd02b
|
983 984 |
void __ide_set_handler(ide_drive_t *, ide_handler_t *, unsigned int); void ide_set_handler(ide_drive_t *, ide_handler_t *, unsigned int); |
1da177e4c
|
985 |
|
35b5d0be3
|
986 987 |
void ide_execute_command(ide_drive_t *, struct ide_cmd *, ide_handler_t *, unsigned int); |
1fc142589
|
988 |
|
9f87abe89
|
989 |
void ide_pad_transfer(ide_drive_t *, int, int); |
9892ec549
|
990 |
ide_startstop_t ide_error(ide_drive_t *, const char *, u8); |
1da177e4c
|
991 |
|
4dde4492d
|
992 |
void ide_fix_driveid(u16 *); |
01745112d
|
993 |
|
1da177e4c
|
994 |
extern void ide_fixstring(u8 *, const int, const int); |
28ee9bc5c
|
995 |
int ide_busy_sleep(ide_drive_t *, unsigned long, int); |
b163f46d5
|
996 |
|
fa56d4cb4
|
997 |
int __ide_wait_stat(ide_drive_t *, u8, u8, unsigned long, u8 *); |
74af21cf4
|
998 |
int ide_wait_stat(ide_startstop_t *, ide_drive_t *, u8, u8, unsigned long); |
1da177e4c
|
999 |
|
c4e66c36c
|
1000 |
ide_startstop_t ide_do_park_unpark(ide_drive_t *, struct request *); |
11938c929
|
1001 |
ide_startstop_t ide_do_devset(ide_drive_t *, struct request *); |
c4e66c36c
|
1002 |
|
1da177e4c
|
1003 |
extern ide_startstop_t ide_do_reset (ide_drive_t *); |
92f1f8fd8
|
1004 1005 |
extern int ide_devset_execute(ide_drive_t *drive, const struct ide_devset *setting, int arg); |
22aa4b32a
|
1006 |
void ide_complete_cmd(ide_drive_t *, struct ide_cmd *, u8, u8); |
f974b196f
|
1007 |
int ide_complete_rq(ide_drive_t *, int, unsigned int); |
1da177e4c
|
1008 |
|
3153c26b5
|
1009 |
void ide_tf_readback(ide_drive_t *drive, struct ide_cmd *cmd); |
745483f10
|
1010 |
void ide_tf_dump(const char *, struct ide_cmd *); |
1da177e4c
|
1011 |
|
374e042c3
|
1012 1013 1014 |
void ide_exec_command(ide_hwif_t *, u8); u8 ide_read_status(ide_hwif_t *); u8 ide_read_altstatus(ide_hwif_t *); |
ecf3a31d2
|
1015 |
void ide_write_devctl(ide_hwif_t *, u8); |
374e042c3
|
1016 |
|
abb596b25
|
1017 |
void ide_dev_select(ide_drive_t *); |
c9ff9e7b6
|
1018 |
void ide_tf_load(ide_drive_t *, struct ide_taskfile *, u8); |
3153c26b5
|
1019 |
void ide_tf_read(ide_drive_t *, struct ide_taskfile *, u8); |
374e042c3
|
1020 |
|
adb1af980
|
1021 1022 |
void ide_input_data(ide_drive_t *, struct ide_cmd *, void *, unsigned int); void ide_output_data(ide_drive_t *, struct ide_cmd *, void *, unsigned int); |
374e042c3
|
1023 |
|
ed4af48fd
|
1024 |
void SELECT_MASK(ide_drive_t *, int); |
1da177e4c
|
1025 |
|
92eb43800
|
1026 |
u8 ide_read_error(ide_drive_t *); |
1823649b5
|
1027 |
void ide_read_bcount_and_ireason(ide_drive_t *, u16 *, u8 *); |
92eb43800
|
1028 |
|
103f7033b
|
1029 |
int ide_check_ireason(ide_drive_t *, struct request *, int, int, int); |
51509eec3
|
1030 |
int ide_check_atapi_device(ide_drive_t *, const char *); |
7bf7420a3
|
1031 |
void ide_init_pc(struct ide_atapi_pc *); |
4abdc6ee7
|
1032 1033 1034 1035 1036 1037 |
/* Disk head parking */ extern wait_queue_head_t ide_park_wq; ssize_t ide_park_show(struct device *dev, struct device_attribute *attr, char *buf); ssize_t ide_park_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len); |
7645c1514
|
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 |
/* * Special requests for ide-tape block device strategy routine. * * In order to service a character device command, we add special requests to * the tail of our block device request queue and wait for their completion. */ enum { REQ_IDETAPE_PC1 = (1 << 0), /* packet command (first stage) */ REQ_IDETAPE_PC2 = (1 << 1), /* packet command (second stage) */ REQ_IDETAPE_READ = (1 << 2), REQ_IDETAPE_WRITE = (1 << 3), }; |
5a0e43b5e
|
1050 |
int ide_queue_pc_tail(ide_drive_t *, struct gendisk *, struct ide_atapi_pc *, |
b13345f39
|
1051 |
void *, unsigned int); |
7645c1514
|
1052 |
|
de699ad59
|
1053 |
int ide_do_test_unit_ready(ide_drive_t *, struct gendisk *); |
0c8a6c7ae
|
1054 |
int ide_do_start_stop(ide_drive_t *, struct gendisk *, int); |
0578042db
|
1055 |
int ide_set_media_lock(ide_drive_t *, struct gendisk *, int); |
6b0da28b2
|
1056 |
void ide_create_request_sense_cmd(ide_drive_t *, struct ide_atapi_pc *); |
6b544fcc8
|
1057 |
void ide_retry_pc(ide_drive_t *drive); |
0578042db
|
1058 |
|
a1df5169f
|
1059 |
void ide_prep_sense(ide_drive_t *drive, struct request *rq); |
5c4be5724
|
1060 |
int ide_queue_sense_rq(ide_drive_t *drive, void *special); |
a1df5169f
|
1061 |
|
4cad085ef
|
1062 |
int ide_cd_expiry(ide_drive_t *); |
844b94685
|
1063 |
|
392de1d53
|
1064 |
int ide_cd_get_xferlen(struct request *); |
b788ee9c6
|
1065 |
ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_cmd *); |
594c16d8d
|
1066 |
|
22aa4b32a
|
1067 |
ide_startstop_t do_rw_taskfile(ide_drive_t *, struct ide_cmd *); |
1da177e4c
|
1068 |
|
a08915ba5
|
1069 |
void ide_pio_bytes(ide_drive_t *, struct ide_cmd *, unsigned int, unsigned int); |
adb1af980
|
1070 |
void ide_finish_cmd(ide_drive_t *, struct ide_cmd *, u8); |
4d7a984bd
|
1071 |
|
22aa4b32a
|
1072 1073 |
int ide_raw_taskfile(ide_drive_t *, struct ide_cmd *, u8 *, u16); int ide_no_data_taskfile(ide_drive_t *, struct ide_cmd *); |
9a3c49be5
|
1074 |
|
22aa4b32a
|
1075 |
int ide_taskfile_ioctl(ide_drive_t *, unsigned long); |
1da177e4c
|
1076 |
|
fa56d4cb4
|
1077 |
int ide_dev_read_id(ide_drive_t *, u8, u16 *, int); |
2ebe1d9ef
|
1078 |
|
1da177e4c
|
1079 |
extern int ide_driveid_update(ide_drive_t *); |
1da177e4c
|
1080 1081 |
extern int ide_config_drive_speed(ide_drive_t *, u8); extern u8 eighty_ninty_three (ide_drive_t *); |
1da177e4c
|
1082 1083 1084 |
extern int taskfile_lib_get_identify(ide_drive_t *drive, u8 *); extern int ide_wait_not_busy(ide_hwif_t *hwif, unsigned long timeout); |
1da177e4c
|
1085 |
extern void ide_stall_queue(ide_drive_t *drive, unsigned long timeout); |
1da177e4c
|
1086 |
extern void ide_timer_expiry(unsigned long); |
7d12e780e
|
1087 |
extern irqreturn_t ide_intr(int irq, void *dev_id); |
165125e1e
|
1088 |
extern void do_ide_request(struct request_queue *); |
6072f7491
|
1089 |
extern void ide_requeue_and_plug(ide_drive_t *drive, struct request *rq); |
1da177e4c
|
1090 1091 |
void ide_init_disk(struct gendisk *, ide_drive_t *); |
6d208b39c
|
1092 |
#ifdef CONFIG_IDEPCI_PCIBUS_ORDER |
725522b54
|
1093 1094 |
extern int __ide_pci_register_driver(struct pci_driver *driver, struct module *owner, const char *mod_name); #define ide_pci_register_driver(d) __ide_pci_register_driver(d, THIS_MODULE, KBUILD_MODNAME) |
6d208b39c
|
1095 1096 1097 |
#else #define ide_pci_register_driver(d) pci_register_driver(d) #endif |
6636487e8
|
1098 1099 1100 1101 1102 1103 |
static inline int ide_pci_is_in_compatibility_mode(struct pci_dev *dev) { if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 5) != 5) return 1; return 0; } |
86ccf37c6
|
1104 |
void ide_pci_setup_ports(struct pci_dev *, const struct ide_port_info *, |
9f36d3143
|
1105 |
struct ide_hw *, struct ide_hw **); |
856204360
|
1106 |
void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *); |
1da177e4c
|
1107 |
|
8e882ba11
|
1108 |
#ifdef CONFIG_BLK_DEV_IDEDMA_PCI |
b123f56e0
|
1109 1110 |
int ide_pci_set_master(struct pci_dev *, const char *); unsigned long ide_pci_dma_base(ide_hwif_t *, const struct ide_port_info *); |
ebb00fb55
|
1111 |
int ide_pci_check_simplex(ide_hwif_t *, const struct ide_port_info *); |
b123f56e0
|
1112 |
int ide_hwif_setup_dma(ide_hwif_t *, const struct ide_port_info *); |
c413b9b94
|
1113 |
#else |
b123f56e0
|
1114 1115 1116 1117 1118 |
static inline int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d) { return -EINVAL; } |
c413b9b94
|
1119 |
#endif |
c0ae50234
|
1120 |
struct ide_pci_enablebit { |
1da177e4c
|
1121 1122 1123 |
u8 reg; /* byte pci reg holding the enable-bit */ u8 mask; /* mask to isolate the enable-bit */ u8 val; /* value of masked reg when "enabled" */ |
c0ae50234
|
1124 |
}; |
1da177e4c
|
1125 1126 1127 |
enum { /* Uses ISA control ports not PCI ones. */ |
a5d8c5c83
|
1128 |
IDE_HFLAG_ISA_PORTS = (1 << 0), |
6a824c92d
|
1129 |
/* single port device */ |
a5d8c5c83
|
1130 |
IDE_HFLAG_SINGLE = (1 << 1), |
6a824c92d
|
1131 1132 |
/* don't use legacy PIO blacklist */ IDE_HFLAG_PIO_NO_BLACKLIST = (1 << 2), |
e277f91fe
|
1133 1134 |
/* set for the second port of QD65xx */ IDE_HFLAG_QD_2ND_PORT = (1 << 3), |
26bcb879c
|
1135 1136 1137 1138 1139 1140 |
/* use PIO8/9 for prefetch off/on */ IDE_HFLAG_ABUSE_PREFETCH = (1 << 4), /* use PIO6/7 for fast-devsel off/on */ IDE_HFLAG_ABUSE_FAST_DEVSEL = (1 << 5), /* use 100-102 and 200-202 PIO values to set DMA modes */ IDE_HFLAG_ABUSE_DMA_MODES = (1 << 6), |
aedea5910
|
1141 1142 1143 1144 1145 |
/* * keep DMA setting when programming PIO mode, may be used only * for hosts which have separate PIO and DMA timings (ie. PMAC) */ IDE_HFLAG_SET_PIO_MODE_KEEP_DMA = (1 << 7), |
88b2b32ba
|
1146 1147 1148 1149 |
/* program host for the transfer mode after programming device */ IDE_HFLAG_POST_SET_MODE = (1 << 8), /* don't program host/device for the transfer mode ("smart" hosts) */ IDE_HFLAG_NO_SET_MODE = (1 << 9), |
0ae2e1786
|
1150 1151 |
/* trust BIOS for programming chipset/device for DMA */ IDE_HFLAG_TRUST_BIOS_FOR_DMA = (1 << 10), |
cafa027b8
|
1152 1153 |
/* host is CS5510/CS5520 */ IDE_HFLAG_CS5520 = (1 << 11), |
33c1002ed
|
1154 1155 |
/* ATAPI DMA is unsupported */ IDE_HFLAG_NO_ATAPI_DMA = (1 << 12), |
5e71d9c5a
|
1156 1157 |
/* set if host is a "non-bootable" controller */ IDE_HFLAG_NON_BOOTABLE = (1 << 13), |
47b687882
|
1158 1159 1160 1161 |
/* host doesn't support DMA */ IDE_HFLAG_NO_DMA = (1 << 14), /* check if host is PCI IDE device before allowing DMA */ IDE_HFLAG_NO_AUTODMA = (1 << 15), |
c5dd43ec6
|
1162 1163 |
/* host uses MMIO */ IDE_HFLAG_MMIO = (1 << 16), |
238e4f142
|
1164 1165 1166 1167 |
/* no LBA48 */ IDE_HFLAG_NO_LBA48 = (1 << 17), /* no LBA48 DMA */ IDE_HFLAG_NO_LBA48_DMA = (1 << 18), |
ed67b9238
|
1168 1169 |
/* data FIFO is cleared by an error */ IDE_HFLAG_ERROR_STOPS_FIFO = (1 << 19), |
1c51361a9
|
1170 1171 |
/* serialize ports */ IDE_HFLAG_SERIALIZE = (1 << 20), |
2787cb8ae
|
1172 1173 |
/* host is DTC2278 */ IDE_HFLAG_DTC2278 = (1 << 21), |
c094ea077
|
1174 1175 |
/* 4 devices on a single set of I/O ports */ IDE_HFLAG_4DRIVES = (1 << 22), |
1f66019bd
|
1176 1177 |
/* host is TRM290 */ IDE_HFLAG_TRM290 = (1 << 23), |
caea7602f
|
1178 1179 1180 1181 |
/* use 32-bit I/O ops */ IDE_HFLAG_IO_32BIT = (1 << 24), /* unmask IRQs */ IDE_HFLAG_UNMASK_IRQS = (1 << 25), |
6636487e8
|
1182 |
IDE_HFLAG_BROKEN_ALTSTATUS = (1 << 26), |
1fd189059
|
1183 1184 |
/* serialize ports if DMA is possible (for sl82c105) */ IDE_HFLAG_SERIALIZE_DMA = (1 << 27), |
8ac2b42a4
|
1185 1186 |
/* force host out of "simplex" mode */ IDE_HFLAG_CLEAR_SIMPLEX = (1 << 28), |
4166c1993
|
1187 1188 |
/* DSC overlap is unsupported */ IDE_HFLAG_NO_DSC = (1 << 29), |
807b90d0b
|
1189 1190 1191 1192 |
/* never use 32-bit I/O ops */ IDE_HFLAG_NO_IO_32BIT = (1 << 30), /* never unmask IRQs */ IDE_HFLAG_NO_UNMASK_IRQS = (1 << 31), |
1da177e4c
|
1193 |
}; |
7cab14a79
|
1194 |
#ifdef CONFIG_BLK_DEV_OFFBOARD |
7cab14a79
|
1195 |
# define IDE_HFLAG_OFF_BOARD 0 |
5e71d9c5a
|
1196 1197 |
#else # define IDE_HFLAG_OFF_BOARD IDE_HFLAG_NON_BOOTABLE |
7cab14a79
|
1198 |
#endif |
039788e15
|
1199 |
struct ide_port_info { |
1da177e4c
|
1200 |
char *name; |
e354c1d80
|
1201 |
|
2ed0ef543
|
1202 |
int (*init_chipset)(struct pci_dev *); |
e354c1d80
|
1203 1204 1205 |
void (*get_lock)(irq_handler_t, void *); void (*release_lock)(void); |
1da177e4c
|
1206 1207 |
void (*init_iops)(ide_hwif_t *); void (*init_hwif)(ide_hwif_t *); |
b123f56e0
|
1208 1209 |
int (*init_dma)(ide_hwif_t *, const struct ide_port_info *); |
ac95beedf
|
1210 |
|
374e042c3
|
1211 |
const struct ide_tp_ops *tp_ops; |
ac95beedf
|
1212 |
const struct ide_port_ops *port_ops; |
f37afdaca
|
1213 |
const struct ide_dma_ops *dma_ops; |
ac95beedf
|
1214 |
|
c0ae50234
|
1215 |
struct ide_pci_enablebit enablebits[2]; |
528a572da
|
1216 |
hwif_chipset_t chipset; |
6b4924962
|
1217 1218 |
u16 max_sectors; /* if < than the default one */ |
9ffcf364f
|
1219 |
u32 host_flags; |
255115fb3
|
1220 1221 |
int irq_flags; |
4099d1432
|
1222 |
u8 pio_mask; |
5f8b6c348
|
1223 1224 |
u8 swdma_mask; u8 mwdma_mask; |
181372072
|
1225 |
u8 udma_mask; |
039788e15
|
1226 |
}; |
1da177e4c
|
1227 |
|
a7928c157
|
1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 |
/* * State information carried for REQ_TYPE_ATA_PM_SUSPEND and REQ_TYPE_ATA_PM_RESUME * requests. */ struct ide_pm_state { /* PM state machine step value, currently driver specific */ int pm_step; /* requested PM state value (S1, S2, S3, S4, ...) */ u32 pm_state; void* data; /* for driver use */ }; |
6cdf6eb35
|
1239 1240 1241 |
int ide_pci_init_one(struct pci_dev *, const struct ide_port_info *, void *); int ide_pci_init_two(struct pci_dev *, struct pci_dev *, const struct ide_port_info *, void *); |
ef0b04276
|
1242 |
void ide_pci_remove(struct pci_dev *); |
1da177e4c
|
1243 |
|
feb22b7f8
|
1244 1245 1246 1247 1248 1249 1250 |
#ifdef CONFIG_PM int ide_pci_suspend(struct pci_dev *, pm_message_t); int ide_pci_resume(struct pci_dev *); #else #define ide_pci_suspend NULL #define ide_pci_resume NULL #endif |
229816941
|
1251 |
void ide_map_sg(ide_drive_t *, struct ide_cmd *); |
bf717c0a2
|
1252 |
void ide_init_sg_cmd(struct ide_cmd *, unsigned int); |
1da177e4c
|
1253 1254 1255 |
#define BAD_DMA_DRIVE 0 #define GOOD_DMA_DRIVE 1 |
65e5f2e3b
|
1256 1257 1258 1259 |
struct drive_list_entry { const char *id_model; const char *id_firmware; }; |
4dde4492d
|
1260 |
int ide_in_drive_list(u16 *, const struct drive_list_entry *); |
a5b7e70d7
|
1261 1262 |
#ifdef CONFIG_BLK_DEV_IDEDMA |
2dbe7e919
|
1263 |
int ide_dma_good_drive(ide_drive_t *); |
1da177e4c
|
1264 |
int __ide_dma_bad_drive(ide_drive_t *); |
7670df73f
|
1265 1266 1267 1268 1269 1270 1271 |
u8 ide_find_dma_mode(ide_drive_t *, u8); static inline u8 ide_max_dma_mode(ide_drive_t *drive) { return ide_find_dma_mode(drive, XFER_UDMA_6); } |
4a546e046
|
1272 |
void ide_dma_off_quietly(ide_drive_t *); |
7469aaf6a
|
1273 |
void ide_dma_off(ide_drive_t *); |
4a546e046
|
1274 |
void ide_dma_on(ide_drive_t *); |
3608b5d71
|
1275 |
int ide_set_dma(ide_drive_t *); |
578cfa0d7
|
1276 |
void ide_check_dma_crc(ide_drive_t *); |
1da177e4c
|
1277 |
ide_startstop_t ide_dma_intr(ide_drive_t *); |
2bbd57cad
|
1278 1279 |
int ide_allocate_dma_engine(ide_hwif_t *); void ide_release_dma_engine(ide_hwif_t *); |
5ae5412d9
|
1280 |
int ide_dma_prepare(ide_drive_t *, struct ide_cmd *); |
f094d4d83
|
1281 |
void ide_dma_unmap_sg(ide_drive_t *, struct ide_cmd *); |
062f9f024
|
1282 |
|
8e882ba11
|
1283 |
#ifdef CONFIG_BLK_DEV_IDEDMA_SFF |
2dbe7e919
|
1284 |
int config_drive_for_dma(ide_drive_t *); |
229816941
|
1285 |
int ide_build_dmatable(ide_drive_t *, struct ide_cmd *); |
15ce926ad
|
1286 |
void ide_dma_host_set(ide_drive_t *, int); |
229816941
|
1287 |
int ide_dma_setup(ide_drive_t *, struct ide_cmd *); |
1da177e4c
|
1288 |
extern void ide_dma_start(ide_drive_t *); |
653bcf529
|
1289 |
int ide_dma_end(ide_drive_t *); |
f37afdaca
|
1290 |
int ide_dma_test_irq(ide_drive_t *); |
22117d6ea
|
1291 |
int ide_dma_sff_timer_expiry(ide_drive_t *); |
592b53152
|
1292 |
u8 ide_dma_sff_read_status(ide_hwif_t *); |
71fc9fcc7
|
1293 |
extern const struct ide_dma_ops sff_dma_ops; |
2dbe7e919
|
1294 1295 |
#else static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; } |
8e882ba11
|
1296 |
#endif /* CONFIG_BLK_DEV_IDEDMA_SFF */ |
1da177e4c
|
1297 |
|
de23ec9ca
|
1298 |
void ide_dma_lost_irq(ide_drive_t *); |
65ca53773
|
1299 |
ide_startstop_t ide_dma_timeout_retry(ide_drive_t *, int); |
de23ec9ca
|
1300 |
|
1da177e4c
|
1301 |
#else |
7670df73f
|
1302 |
static inline u8 ide_find_dma_mode(ide_drive_t *drive, u8 speed) { return 0; } |
2d5eaa6dd
|
1303 |
static inline u8 ide_max_dma_mode(ide_drive_t *drive) { return 0; } |
4a546e046
|
1304 |
static inline void ide_dma_off_quietly(ide_drive_t *drive) { ; } |
7469aaf6a
|
1305 |
static inline void ide_dma_off(ide_drive_t *drive) { ; } |
4a546e046
|
1306 |
static inline void ide_dma_on(ide_drive_t *drive) { ; } |
1da177e4c
|
1307 |
static inline void ide_dma_verbose(ide_drive_t *drive) { ; } |
3608b5d71
|
1308 |
static inline int ide_set_dma(ide_drive_t *drive) { return 1; } |
578cfa0d7
|
1309 |
static inline void ide_check_dma_crc(ide_drive_t *drive) { ; } |
22117d6ea
|
1310 |
static inline ide_startstop_t ide_dma_intr(ide_drive_t *drive) { return ide_stopped; } |
65ca53773
|
1311 |
static inline ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error) { return ide_stopped; } |
0d1bad216
|
1312 |
static inline void ide_release_dma_engine(ide_hwif_t *hwif) { ; } |
5ae5412d9
|
1313 1314 |
static inline int ide_dma_prepare(ide_drive_t *drive, struct ide_cmd *cmd) { return 1; } |
f094d4d83
|
1315 1316 |
static inline void ide_dma_unmap_sg(ide_drive_t *drive, struct ide_cmd *cmd) { ; } |
2bbd57cad
|
1317 |
#endif /* CONFIG_BLK_DEV_IDEDMA */ |
1da177e4c
|
1318 |
|
e3a59b4d9
|
1319 |
#ifdef CONFIG_BLK_DEV_IDEACPI |
8b803bd18
|
1320 |
int ide_acpi_init(void); |
2bf427b25
|
1321 |
bool ide_port_acpi(ide_hwif_t *hwif); |
e3a59b4d9
|
1322 1323 1324 |
extern int ide_acpi_exec_tfs(ide_drive_t *drive); extern void ide_acpi_get_timing(ide_hwif_t *hwif); extern void ide_acpi_push_timing(ide_hwif_t *hwif); |
8b803bd18
|
1325 |
void ide_acpi_init_port(ide_hwif_t *); |
eafd88a3b
|
1326 |
void ide_acpi_port_init_devices(ide_hwif_t *); |
5e32132be
|
1327 |
extern void ide_acpi_set_state(ide_hwif_t *hwif, int on); |
e3a59b4d9
|
1328 |
#else |
8b803bd18
|
1329 |
static inline int ide_acpi_init(void) { return 0; } |
2bf427b25
|
1330 |
static inline bool ide_port_acpi(ide_hwif_t *hwif) { return 0; } |
e3a59b4d9
|
1331 1332 1333 |
static inline int ide_acpi_exec_tfs(ide_drive_t *drive) { return 0; } static inline void ide_acpi_get_timing(ide_hwif_t *hwif) { ; } static inline void ide_acpi_push_timing(ide_hwif_t *hwif) { ; } |
8b803bd18
|
1334 |
static inline void ide_acpi_init_port(ide_hwif_t *hwif) { ; } |
eafd88a3b
|
1335 |
static inline void ide_acpi_port_init_devices(ide_hwif_t *hwif) { ; } |
5e32132be
|
1336 |
static inline void ide_acpi_set_state(ide_hwif_t *hwif, int on) {} |
e3a59b4d9
|
1337 |
#endif |
1da177e4c
|
1338 1339 |
void ide_register_region(struct gendisk *); void ide_unregister_region(struct gendisk *); |
8bc1e5aa0
|
1340 |
void ide_check_nien_quirk_list(ide_drive_t *); |
f01393e48
|
1341 |
void ide_undecoded_slave(ide_drive_t *); |
1da177e4c
|
1342 |
|
9fd91d959
|
1343 |
void ide_port_apply_params(ide_hwif_t *); |
ebdab07da
|
1344 |
int ide_sysfs_register_port(ide_hwif_t *); |
9fd91d959
|
1345 |
|
9f36d3143
|
1346 |
struct ide_host *ide_host_alloc(const struct ide_port_info *, struct ide_hw **, |
dca398305
|
1347 |
unsigned int); |
8a69580e1
|
1348 |
void ide_host_free(struct ide_host *); |
48c3c1072
|
1349 |
int ide_host_register(struct ide_host *, const struct ide_port_info *, |
9f36d3143
|
1350 1351 |
struct ide_hw **); int ide_host_add(const struct ide_port_info *, struct ide_hw **, unsigned int, |
6f904d015
|
1352 |
struct ide_host **); |
48c3c1072
|
1353 |
void ide_host_remove(struct ide_host *); |
0bfeee7d4
|
1354 |
int ide_legacy_device_add(const struct ide_port_info *, unsigned long); |
2dde7861a
|
1355 1356 |
void ide_port_unregister_devices(ide_hwif_t *); void ide_port_scan(ide_hwif_t *); |
1da177e4c
|
1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 |
static inline void *ide_get_hwifdata (ide_hwif_t * hwif) { return hwif->hwif_data; } static inline void ide_set_hwifdata (ide_hwif_t * hwif, void *data) { hwif->hwif_data = data; } |
1da177e4c
|
1367 |
extern void ide_toggle_bounce(ide_drive_t *drive, int on); |
1da177e4c
|
1368 |
|
745483f10
|
1369 |
u64 ide_get_lba_addr(struct ide_cmd *, int); |
1da177e4c
|
1370 |
u8 ide_dump_status(ide_drive_t *, const char *, u8); |
3be53f3f2
|
1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 |
struct ide_timing { u8 mode; u8 setup; /* t1 */ u16 act8b; /* t2 for 8-bit io */ u16 rec8b; /* t2i for 8-bit io */ u16 cyc8b; /* t0 for 8-bit io */ u16 active; /* t2 or tD */ u16 recover; /* t2i or tK */ u16 cycle; /* t0 */ u16 udma; /* t2CYCTYP/2 */ }; enum { IDE_TIMING_SETUP = (1 << 0), IDE_TIMING_ACT8B = (1 << 1), IDE_TIMING_REC8B = (1 << 2), IDE_TIMING_CYC8B = (1 << 3), IDE_TIMING_8BIT = IDE_TIMING_ACT8B | IDE_TIMING_REC8B | IDE_TIMING_CYC8B, IDE_TIMING_ACTIVE = (1 << 4), IDE_TIMING_RECOVER = (1 << 5), IDE_TIMING_CYCLE = (1 << 6), IDE_TIMING_UDMA = (1 << 7), IDE_TIMING_ALL = IDE_TIMING_SETUP | IDE_TIMING_8BIT | IDE_TIMING_ACTIVE | IDE_TIMING_RECOVER | IDE_TIMING_CYCLE | IDE_TIMING_UDMA, }; |
f06ab3402
|
1398 |
struct ide_timing *ide_timing_find_mode(u8); |
c9d6c1a23
|
1399 |
u16 ide_pio_cycle_time(ide_drive_t *, u8); |
f06ab3402
|
1400 1401 1402 |
void ide_timing_merge(struct ide_timing *, struct ide_timing *, struct ide_timing *, unsigned int); int ide_timing_compute(ide_drive_t *, u8, struct ide_timing *, int, int); |
7eeaaaa52
|
1403 |
#ifdef CONFIG_IDE_XFER_MODE |
9ad540937
|
1404 |
int ide_scan_pio_blacklist(char *); |
7eeaaaa52
|
1405 |
const char *ide_xfer_verbose(u8); |
c9ef59ff0
|
1406 |
int ide_pio_need_iordy(ide_drive_t *, const u8); |
88b2b32ba
|
1407 1408 |
int ide_set_pio_mode(ide_drive_t *, u8); int ide_set_dma_mode(ide_drive_t *, u8); |
26bcb879c
|
1409 |
void ide_set_pio(ide_drive_t *, u8); |
7eeaaaa52
|
1410 1411 1412 1413 1414 |
int ide_set_xfer_rate(ide_drive_t *, u8); #else static inline void ide_set_pio(ide_drive_t *drive, u8 pio) { ; } static inline int ide_set_xfer_rate(ide_drive_t *drive, u8 rate) { return -1; } #endif |
26bcb879c
|
1415 1416 1417 1418 1419 |
static inline void ide_set_max_pio(ide_drive_t *drive) { ide_set_pio(drive, 255); } |
1da177e4c
|
1420 |
|
ebdab07da
|
1421 |
char *ide_media_string(ide_drive_t *); |
fb3fed792
|
1422 |
extern const struct attribute_group *ide_dev_groups[]; |
1da177e4c
|
1423 |
extern struct bus_type ide_bus_type; |
f74c91413
|
1424 |
extern struct class *ide_port_class; |
1da177e4c
|
1425 |
|
7b9f25b53
|
1426 1427 1428 1429 |
static inline void ide_dump_identify(u8 *id) { print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 2, id, 512, 0); } |
86b378607
|
1430 1431 |
static inline int hwif_to_node(ide_hwif_t *hwif) { |
96f80219b
|
1432 |
return hwif->dev ? dev_to_node(hwif->dev) : -1; |
86b378607
|
1433 |
} |
7e59ea21a
|
1434 |
static inline ide_drive_t *ide_get_pair_dev(ide_drive_t *drive) |
1b6783471
|
1435 |
{ |
5e7f3a466
|
1436 |
ide_drive_t *peer = drive->hwif->devices[(drive->dn ^ 1) & 1]; |
1b6783471
|
1437 |
|
97100fc81
|
1438 |
return (peer->dev_flags & IDE_DFLAG_PRESENT) ? peer : NULL; |
1b6783471
|
1439 |
} |
2bd24a1cf
|
1440 |
|
5bfb151f1
|
1441 1442 1443 1444 1445 1446 1447 1448 1449 |
static inline void *ide_get_drivedata(ide_drive_t *drive) { return drive->drive_data; } static inline void ide_set_drivedata(ide_drive_t *drive, void *data) { drive->drive_data = data; } |
2bd24a1cf
|
1450 1451 |
#define ide_port_for_each_dev(i, dev, port) \ for ((i) = 0; ((dev) = (port)->devices[i]) || (i) < MAX_DRIVES; (i)++) |
7ed5b157d
|
1452 1453 1454 |
#define ide_port_for_each_present_dev(i, dev, port) \ for ((i) = 0; ((dev) = (port)->devices[i]) || (i) < MAX_DRIVES; (i)++) \ if ((dev)->dev_flags & IDE_DFLAG_PRESENT) |
2bd24a1cf
|
1455 1456 |
#define ide_host_for_each_port(i, port, host) \ for ((i) = 0; ((port) = (host)->ports[i]) || (i) < MAX_HOST_PORTS; (i)++) |
b42171ef7
|
1457 |
|
1da177e4c
|
1458 |
#endif /* _IDE_H */ |