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arch/arm64/boot/dts/freescale/fsl-imx8mm-ddr4-evk.dts
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// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2018 NXP */ /dts-v1/; #include "fsl-imx8mm-evk.dts" / { model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; leds { pinctrl-0 = <&pinctrl_gpio_led_2>; status { gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; }; }; usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_gpio>; reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; }; }; &iomuxc { imx8mm-evk { pinctrl_gpmi_nand_1: gpmi-nand-1 { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 >; }; pinctrl_gpio_led_2: gpioled2grp { fsl,pins = < MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 >; }; pinctrl_wlan: wlangrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 >; }; }; }; &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand_1>; status = "okay"; nand-on-flash-bbt; }; ®_sd1_vmmc { status = "disabled"; }; &usdhc1 { #address-cells = <1>; #size-cells = <0>; pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>; cap-power-off-card; /delete-property/ vmmc-supply; mmc-pwrseq = <&usdhc1_pwrseq>; brcmf: bcrmf@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio2>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "host-wake"; }; }; &usdhc3 { status = "disabled"; }; &flexspi { status = "disabled"; }; /* * External OSC is used as PCIe REFCLK on RevC board. * DDR4 board is same to the RevB board, configure * PCIe REFCLK to internal PLL. */ &pcie0{ ext_osc = <0>; status = "okay"; }; |