Eric Lee / smarc-fsl-linux-kernel

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arch/arm64/boot/dts/freescale/fsl-imx8mm-evk.dts 26.3 KB
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81f7e3824   Eric Lee   Initial Release, ... 
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  /*
   * Copyright 2018 NXP
   *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License
   * as published by the Free Software Foundation; either version 2
   * of the License, or (at your option) any later version.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.
   */
  
  /dts-v1/;
  
  #include "fsl-imx8mm.dtsi"
  
  / {
  	firmware {
  		android {
  			compatible = "android,firmware";
  			fstab {
  				compatible = "android,fstab";
  				vendor {
  					compatible = "android,vendor";
  					/* sd card node which used if androidboot.storage_type=sd */
  					dev_sd = "/dev/block/platform/30b50000.mmc/by-name/vendor";
  					/* emmc node which used if androidboot.storage_type=emmc */
  					dev_emmc = "/dev/block/platform/30b60000.mmc/by-name/vendor";
  					type = "ext4";
  					mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
  					fsmgr_flags = "wait,slotselect,avb";
  				};
  			};
  			vbmeta {
  				/*we need use FirstStageMountVBootV2 if we enable avb*/
  				compatible = "android,vbmeta";
  				/*parts means the partition witch can be mount in first stage*/
  				parts = "vbmeta,boot,system,vendor";
  			};
  		};
  	};
  };
  
  / {
  	model = "FSL i.MX8MM EVK board";
  	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
  
  	chosen {
  		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
  		stdout-path = &uart2;
  	};
  
  	leds {
  		compatible = "gpio-leds";
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_gpio_led>;
  
  		status {
  			label = "status";
  			gpios = <&gpio3 16 0>;
  			default-state = "on";
  		};
  	};
  
  	bt_rfkill {
  		compatible = "fsl,mxc_bt_rfkill";
  		bt-power-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
  		status ="okay";
  	};
  
  	ir_recv: ir-receiver {
  		compatible = "gpio-ir-receiver";
  		gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_ir_recv>;
  	};
  
  	regulators {
  		compatible = "simple-bus";
  		#address-cells = <1>;
  		#size-cells = <0>;
  
  		reg_sd1_vmmc: sd1_regulator {
  			compatible = "regulator-fixed";
  			regulator-name = "WLAN_EN";
  			regulator-min-microvolt = <3300000>;
  			regulator-max-microvolt = <3300000>;
  			gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
  			off-on-delay = <20000>;
  			startup-delay-us = <100>;
  			enable-active-high;
  		};
  
  		reg_usdhc2_vmmc: regulator-usdhc2 {
  			compatible = "regulator-fixed";
  			regulator-name = "VSD_3V3";
  			regulator-min-microvolt = <3300000>;
  			regulator-max-microvolt = <3300000>;
  			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  			off-on-delay = <20000>;
  			enable-active-high;
  		};
  
  		reg_audio_board: regulator-audio-board {
  			compatible = "regulator-fixed";
  			regulator-name = "EXT_PWREN";
  			regulator-min-microvolt = <3300000>;
  			regulator-max-microvolt = <3300000>;
  			enable-active-high;
  			startup-delay-us = <300000>;
  			gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>;
  		};
  	};
  
  	wm8524: wm8524 {
  		compatible = "wlf,wm8524";
  		clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  		clock-names = "mclk";
  		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  	};
  
  	sound-wm8524 {
  		compatible = "fsl,imx-audio-wm8524";
  		model = "wm8524-audio";
  		audio-cpu = <&sai3>;
  		audio-codec = <&wm8524>;
  		audio-routing =
  			"Line Out Jack", "LINEVOUTL",
  			"Line Out Jack", "LINEVOUTR";
  	};
  
  	sound-ak4458 {
  		compatible = "fsl,imx-audio-ak4458";
  		model = "ak4458-audio";
  		audio-cpu = <&sai1>;
  		audio-codec = <&ak4458_1>, <&ak4458_2>;
  		ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
  	};
  
  	sound-ak5558 {
  		compatible = "fsl,imx-audio-ak5558";
  		model = "ak5558-audio";
  		audio-cpu = <&sai5>;
  		audio-codec = <&ak5558>;
  		status = "disabled";
  	};
  
  	sound-ak4497 {
  		compatible = "fsl,imx-audio-ak4497";
  		model = "ak4497-audio";
  		audio-cpu = <&sai1>;
  		audio-codec = <&ak4497>;
  		status = "disabled";
  	};
  
  	sound-spdif {
  		compatible = "fsl,imx-audio-spdif";
  		model = "imx-spdif";
  		spdif-controller = <&spdif1>;
  		spdif-out;
  		spdif-in;
  	};
  
  	sound-micfil {
  		compatible = "fsl,imx-audio-micfil";
  		model = "imx-audio-micfil";
  		cpu-dai = <&micfil>;
  	};
  };
  
  &clk {
  	assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
  	assigned-clock-rates = <786432000>, <722534400>;
  };
  
  &iomuxc {
  	pinctrl-names = "default";
  
  	imx8mm-evk {
  		pinctrl_csi_pwn: csi_pwn_grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
  			>;
  		};
  
  		pinctrl_ir_recv: ir_recv {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x14f
  			>;
  		};
  
  		pinctrl_csi_rst: csi_rst_grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
  				MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
  			>;
  		};
  
  		pinctrl_mipi_dsi_en: mipi_dsi_en {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x16
  			>;
  		};
  
  		pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19	/* Touch int */
  			>;
  		};
  
  		pinctrl_fec1: fec1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
  				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
  				MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
  				MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
  				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
  				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
  				MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
  				MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
  				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
  				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
  				MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
  				MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
  				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
  				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
  				MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
  			>;
  		};
  
  		pinctrl_flexspi0: flexspi0grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2
  				MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
  				MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
  				MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
  				MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
  				MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82
  			>;
  		};
  
  		pinctrl_gpio_led: gpioledgrp {
  			fsl,pins = <
  				MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
  			>;
  		};
  
  		pinctrl_i2c1: i2c1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
  				MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
  			>;
  		};
  
  		pinctrl_i2c2: i2c2grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
  				MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
  			>;
  		};
  
  		pinctrl_i2c3: i2c3grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
  				MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
  			>;
  		};
  
  		pinctrl_pcie0: pcie0grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B	0x61 /* open drain, pull up */
  				MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x41
  				MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x41
  			>;
  		};
  
  		pinctrl_pmic: pmicirq {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
  			>;
  		};
  
  		pinctrl_typec1: typec1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
  			>;
  		};
  
  		pinctrl_typec2: typec2grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x159
  			>;
  		};
  
  		pinctrl_sai1: sai1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK	0xd6
  				MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
  				MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC	0xd6
  				MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK	0xd6
  				MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0	0xd6
  				MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1	0xd6
  				MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2	0xd6
  				MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3	0xd6
  				MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4	0xd6
  				MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5	0xd6
  				MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6	0xd6
  				MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7	0xd6
  			>;
  		};
  
  		pinctrl_sai1_dsd: sai1grp_dsd {
  			fsl,pins = <
  				MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK	0xd6
  				MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
  				MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4	0xd6
  				MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK	0xd6
  				MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0	0xd6
  				MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1	0xd6
  				MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2	0xd6
  				MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3	0xd6
  				MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4	0xd6
  				MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5	0xd6
  				MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6	0xd6
  				MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7	0xd6
  			>;
  		};
  
  		pinctrl_sai3: sai3grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
  				MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
  				MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
  				MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
  				MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0xd6
  			>;
  		};
  
  		pinctrl_sai5: sai5grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
  				MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK	0xd6
  				MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
  				MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0	0xd6
  				MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1    0xd6
  				MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2    0xd6
  				MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3    0xd6
  			>;
  		};
  
  		pinctrl_pdm: pdmgrp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK	0xd6
  				MX8MM_IOMUXC_SAI5_RXC_PDM_CLK		0xd6
  				MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC	0xd6
  				MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0	0xd6
  				MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1	0xd6
  				MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2	0xd6
  				MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3	0xd6
  			>;
  		};
  
  		pinctrl_spdif1: spdif1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT	0xd6
  				MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
  			>;
  		};
  
  		pinctrl_uart1: uart1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
  				MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
  				MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
  				MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
  				MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6	0x19
  			>;
  		};
  
  		pinctrl_uart2: uart2grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
  				MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
  			>;
  		};
  
  		pinctrl_uart3: uart3grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
  				MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
  				MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x140
  				MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
  			>;
  		};
  
  		pinctrl_usdhc1_gpio: usdhc1grpgpio {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
  			>;
  		};
  
  		pinctrl_usdhc1: usdhc1grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
  				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
  				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
  				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
  				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
  			>;
  		};
  
  		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
  				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
  				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
  				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
  				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
  			>;
  		};
  
  		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
  				MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
  				MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
  				MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
  				MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
  				MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
  			>;
  		};
  
  		pinctrl_usdhc2_gpio: usdhc2grpgpio {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
  				MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
  			>;
  		};
  
  		pinctrl_usdhc2: usdhc2grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
  				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
  				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
  				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
  				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
  				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
  				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
  			>;
  		};
  
  		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
  				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
  				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
  				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
  				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
  				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
  				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
  			>;
  		};
  
  		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  			fsl,pins = <
  				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
  				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
  				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
  				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
  				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
  				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
  				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
  			>;
  		};
  
  		pinctrl_usdhc3: usdhc3grp {
  			fsl,pins = <
  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
  				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
  				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
  				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
  				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
  				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
  				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
  				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
  				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
  				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
  			>;
  		};
  
  		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  			fsl,pins = <
  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
  				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
  				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
  				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
  				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
  				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
  				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
  				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
  				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
  				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
  			>;
  		};
  
  		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  			fsl,pins = <
  				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
  				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
  				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
  				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
  				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
  				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
  				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
  				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
  				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
  				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
  				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
  			>;
  		};
  
  		pinctrl_wdog: wdoggrp {
  			fsl,pins = <
  				MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
  			>;
  		};
  	};
  };
  
  &csi1_bridge {
  	fsl,mipi-mode;
  	status = "okay";
  	port {
  		csi1_ep: endpoint {
  			remote-endpoint = <&csi1_mipi_ep>;
  		};
  	};
  };
  
  &flexspi {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_flexspi0>;
  	status = "okay";
  
  	flash0: mt25qu256aba@0 {
  		reg = <0>;
  		#address-cells = <1>;
  		#size-cells = <1>;
  		compatible = "micron,mt25qu256aba";
  		spi-max-frequency = <80000000>;
  		spi-nor,ddr-quad-read-dummy = <6>;
  	};
  };
  
  &i2c1 {
  	clock-frequency = <400000>;
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_i2c1>;
  	status = "okay";
  
  	pmic: bd71837@4b {
  		reg = <0x4b>;
  		compatible = "rohm,bd71840", "rohm,bd71837";
  		/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
  		pinctrl-0 = <&pinctrl_pmic>;
  		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
  
  		gpo {
  			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
  		};
  
  		regulators {
  			#address-cells = <1>;
  			#size-cells = <0>;
  
  			bd71837,pmic-buck2-uses-i2c-dvs;
  			bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
  
  			buck1_reg: regulator@0 {
  				reg = <0>;
  				regulator-compatible = "buck1";
  				regulator-min-microvolt = <700000>;
  				regulator-max-microvolt = <1300000>;
  				regulator-boot-on;
  				regulator-always-on;
  				regulator-ramp-delay = <1250>;
  			};
  
  			buck2_reg: regulator@1 {
  				reg = <1>;
  				regulator-compatible = "buck2";
  				regulator-min-microvolt = <700000>;
  				regulator-max-microvolt = <1300000>;
  				regulator-boot-on;
  				regulator-always-on;
  				regulator-ramp-delay = <1250>;
  			};
  
  			buck3_reg: regulator@2 {
  				reg = <2>;
  				regulator-compatible = "buck3";
  				regulator-min-microvolt = <700000>;
  				regulator-max-microvolt = <1300000>;
  			};
  
  			buck4_reg: regulator@3 {
  				reg = <3>;
  				regulator-compatible = "buck4";
  				regulator-min-microvolt = <700000>;
  				regulator-max-microvolt = <1300000>;
  			};
  
  			buck5_reg: regulator@4 {
  				reg = <4>;
  				regulator-compatible = "buck5";
  				regulator-min-microvolt = <700000>;
  				regulator-max-microvolt = <1350000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			buck6_reg: regulator@5 {
  				reg = <5>;
  				regulator-compatible = "buck6";
  				regulator-min-microvolt = <3000000>;
  				regulator-max-microvolt = <3300000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			buck7_reg: regulator@6 {
  				reg = <6>;
  				regulator-compatible = "buck7";
  				regulator-min-microvolt = <1605000>;
  				regulator-max-microvolt = <1995000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			buck8_reg: regulator@7 {
  				reg = <7>;
  				regulator-compatible = "buck8";
  				regulator-min-microvolt = <800000>;
  				regulator-max-microvolt = <1400000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			ldo1_reg: regulator@8 {
  				reg = <8>;
  				regulator-compatible = "ldo1";
54a71b2ab   Eric Lee   dts: correct ldo1... 
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  				regulator-min-microvolt = <1600000>;
  				regulator-max-microvolt = <1900000>;
81f7e3824   Eric Lee   Initial Release, ... 
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  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			ldo2_reg: regulator@9 {
  				reg = <9>;
  				regulator-compatible = "ldo2";
54a71b2ab   Eric Lee   dts: correct ldo1... 
667
 
  				regulator-min-microvolt = <800000>;
81f7e3824   Eric Lee   Initial Release, ... 
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  				regulator-max-microvolt = <900000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			ldo3_reg: regulator@10 {
  				reg = <10>;
  				regulator-compatible = "ldo3";
  				regulator-min-microvolt = <1800000>;
  				regulator-max-microvolt = <3300000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			ldo4_reg: regulator@11 {
  				reg = <11>;
  				regulator-compatible = "ldo4";
  				regulator-min-microvolt = <900000>;
  				regulator-max-microvolt = <1800000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  
  			ldo6_reg: regulator@13 {
  				reg = <13>;
  				regulator-compatible = "ldo6";
  				regulator-min-microvolt = <900000>;
  				regulator-max-microvolt = <1800000>;
  				regulator-boot-on;
  				regulator-always-on;
  			};
  		};
  	};
  };
  
  &i2c2 {
  	clock-frequency = <400000>;
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_i2c2>;
  	status = "okay";
  
  	adv_bridge: adv7535@3d {
  		compatible = "adi,adv7533";
  		reg = <0x3d>;
  		adi,addr-cec = <0x3b>;
  		adi,dsi-lanes = <4>;
  		status = "okay";
  
  		port {
  			adv7535_from_dsim: endpoint {
  				remote-endpoint = <&dsim_to_adv7535>;
  			};
  		};
  	};
  
  	typec1_ptn5110: tcpci@50 {
  		compatible = "usb,tcpci";
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_typec1>;
  		reg = <0x50>;
  		interrupt-parent = <&gpio2>;
  		interrupts = <11 8>;
  		src-pdos = <0x380190c8>;
  		snk-pdos = <0x380190c8>;
  		/* Only can sink 5V for safe */
  		max-snk-mv = <5000>;
  		max-snk-ma = <3000>;
  		op-snk-mw = <10000>;
  		max-snk-mw = <15000>;
  		port-type = "drp";
  		default-role = "sink";
  		status = "okay";
  	};
  
  	typec2_ptn5110: tcpci@52 {
  		compatible = "usb,tcpci";
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_typec2>;
  		reg = <0x52>;
  		interrupt-parent = <&gpio2>;
  		interrupts = <12 8>;
  		src-pdos = <0x380190c8>;
  		snk-pdos = <0x380190c8>;
  		/* Only can sink 5V for safe */
  		max-snk-mv = <5000>;
  		max-snk-ma = <3000>;
  		op-snk-mw = <10000>;
  		max-snk-mw = <15000>;
  		port-type = "drp";
  		default-role = "sink";
  		status = "okay";
  	};
  };
  
  
  &mipi_csi_1 {
  	#address-cells = <1>;
  	#size-cells = <0>;
  	status = "okay";
  	port {
  		mipi1_sensor_ep: endpoint1 {
  			remote-endpoint = <&ov5640_mipi1_ep>;
  			data-lanes = <2>;
  			csis-hs-settle = <13>;
  			csis-clk-settle = <2>;
  			csis-wclk;
  		};
  
  		csi1_mipi_ep: endpoint2 {
  			remote-endpoint = <&csi1_ep>;
  		};
  	};
  };
  
  &i2c3 {
  	clock-frequency = <100000>;
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_i2c3>;
  	status = "okay";
  
  	pca6416: gpio@20 {
  		compatible = "ti,tca6416";
  		reg = <0x20>;
  		gpio-controller;
  		#gpio-cells = <2>;
  	};
  
  	ak4458_1: ak4458@10 {
  		compatible = "asahi-kasei,ak4458";
  		reg = <0x10>;
  		AVDD-supply = <&reg_audio_board>;
  		DVDD-supply = <&reg_audio_board>;
  	};
  
  	ak4458_2: ak4458@12 {
  		compatible = "asahi-kasei,ak4458";
  		reg = <0x12>;
  		AVDD-supply = <&reg_audio_board>;
  		DVDD-supply = <&reg_audio_board>;
  	};
  
  	ak5558: ak5558@13 {
  		compatible = "asahi-kasei,ak5558";
  		reg = <0x13>;
  		ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
  		AVDD-supply = <&reg_audio_board>;
  		DVDD-supply = <&reg_audio_board>;
  	};
  
  	ak4497: ak4497@11 {
  		compatible = "asahi-kasei,ak4497";
  		reg = <0x11>;
  		ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
  		AVDD-supply = <&reg_audio_board>;
  		DVDD-supply = <&reg_audio_board>;
  	};
  
  	ov5640_mipi: ov5640_mipi@3c {
  		compatible = "ovti,ov5640_mipi";
  		reg = <0x3c>;
  		status = "okay";
  		pinctrl-names = "default";
  		pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
  		clocks = <&clk IMX8MM_CLK_CLKO1_DIV>;
  		clock-names = "csi_mclk";
  		assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>,
  				  <&clk IMX8MM_CLK_CLKO1_DIV>;
  		assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
  		assigned-clock-rates = <0>, <24000000>;
  		csi_id = <0>;
  		pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  		mclk = <24000000>;
  		mclk_source = <0>;
  		port {
  			ov5640_mipi1_ep: endpoint {
  				remote-endpoint = <&mipi1_sensor_ep>;
  			};
  		};
  	};
  };
  
  &lcdif {
  	status = "okay";
  };
  
  &mipi_dsi {
  	status = "okay";
  
  	port@1 {
  		dsim_to_adv7535: endpoint {
  			remote-endpoint = <&adv7535_from_dsim>;
  		};
  	};
  };
  
  &mu {
  	status = "okay";
  };
  
  &sai1 {
  	pinctrl-names = "default", "dsd";
  	pinctrl-0 = <&pinctrl_sai1>;
  	pinctrl-1 = <&pinctrl_sai1_dsd>;
  	assigned-clocks = <&clk IMX8MM_CLK_SAI1_SRC>,
  			<&clk IMX8MM_CLK_SAI1_DIV>;
  	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  	assigned-clock-rates = <0>, <49152000>;
  	clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
  		<&clk IMX8MM_AUDIO_PLL2_OUT>;
  	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
  	fsl,sai-multi-lane;
  	fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>;
  	dmas = <&sdma2 0 26 0>, <&sdma2 1 26 0>;
  	status = "okay";
  };
  
  &sai3 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_sai3>;
  	assigned-clocks = <&clk IMX8MM_CLK_SAI3_SRC>,
  			<&clk IMX8MM_CLK_SAI3_DIV>;
  	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  	assigned-clock-rates = <0>, <24576000>;
  	status = "okay";
  };
  
  &sai5 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_sai5>;
  	assigned-clocks = <&clk IMX8MM_CLK_SAI5_SRC>,
  			<&clk IMX8MM_CLK_SAI5_DIV>;
  	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  	assigned-clock-rates = <0>, <49152000>;
  	clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
  		<&clk IMX8MM_AUDIO_PLL2_OUT>;
  	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
  	fsl,sai-asynchronous;
  	status = "disabled";
  };
  
  &spdif1 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_spdif1>;
  	assigned-clocks = <&clk IMX8MM_CLK_SPDIF1_SRC>,
  			<&clk IMX8MM_CLK_SPDIF1_DIV>;
  	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  	assigned-clock-rates = <0>, <24576000>;
  	clocks = <&clk IMX8MM_CLK_AUDIO_AHB_DIV>, <&clk IMX8MM_CLK_24M>,
  		<&clk IMX8MM_CLK_SPDIF1_DIV>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_AUDIO_AHB_DIV>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
  		<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
  	clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
  		"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
  	status = "okay";
  };
  
  &fec1 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_fec1>;
  	phy-mode = "rgmii-id";
  	phy-handle = <&ethphy0>;
  	fsl,magic-packet;
  	status = "okay";
  
  	mdio {
  		#address-cells = <1>;
  		#size-cells = <0>;
  
  		ethphy0: ethernet-phy@0 {
  			compatible = "ethernet-phy-ieee802.3-c22";
  			reg = <0>;
  			at803x,led-act-blind-workaround;
  			at803x,eee-okay;
  			at803x,vddio-1p8v;
  		};
  	};
  };
  
  &pcie0{
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_pcie0>;
  	disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
  	ext_osc = <1>;
  	status = "okay";
  };
  
  &uart1 { /* BT */
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_uart1>;
  	assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>;
  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
  	fsl,uart-has-rtscts;
  	status = "okay";
  };
  
  &uart2 { /* console */
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_uart2>;
  	status = "okay";
  };
  
  &uart3 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_uart3>;
  	assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>;
  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
  	fsl,uart-has-rtscts;
  	status = "okay";
  };
  
  &usbotg1 {
  	dr_mode = "otg";
  	extcon = <0>, <&typec1_ptn5110>;
  	picophy,pre-emp-curr-control = <3>;
  	picophy,dc-vol-level-adjust = <7>;
  	status = "okay";
  };
  
  &usbotg2 {
  	dr_mode = "otg";
  	extcon = <0>, <&typec2_ptn5110>;
  	picophy,pre-emp-curr-control = <3>;
  	picophy,dc-vol-level-adjust = <7>;
  	status = "disabled";
  };
  
  &usdhc1 {
  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
  	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
  	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
  	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
  	bus-width = <4>;
  	vmmc-supply = <&reg_sd1_vmmc>;
  	pm-ignore-notify;
  	keep-power-in-suspend;
  	non-removable;
  	status = "okay";
  };
  
  &usdhc2 {
  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
  	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  	bus-width = <4>;
  	vmmc-supply = <&reg_usdhc2_vmmc>;
  	status = "okay";
  };
  
  &usdhc3 {
  	pinctrl-names = "default", "state_100mhz", "state_200mhz";
  	pinctrl-0 = <&pinctrl_usdhc3>;
  	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
  	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
  	bus-width = <8>;
  	non-removable;
  	status = "okay";
  };
  
  &wdog1 {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_wdog>;
  	fsl,ext-reset-output;
  	status = "okay";
  };
  
  &A53_0 {
  	arm-supply = <&buck2_reg>;
  };
  
  &gpu {
  	status = "okay";
  };
  
  &vpu_g1 {
  	status = "okay";
  };
  
  &vpu_g2 {
  	status = "okay";
  };
  
  &vpu_h1 {
  	status = "okay";
  };
  
  &micfil {
  	pinctrl-names = "default";
  	pinctrl-0 = <&pinctrl_pdm>;
  	assigned-clocks = <&clk IMX8MM_CLK_PDM_SRC>, <&clk IMX8MM_CLK_PDM_DIV>;
  	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  	assigned-clock-rates = <0>, <196608000>;
  	status = "okay";
  };
  
  &crypto {
         status = "disabled";
  };