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arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-hdmi.dts
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Initial Release, ...
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/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8qm-mek-domu.dts"
/*
* Currently we disable the audio part, since audio in domu not ready.
* This file is reused from fsl-imx8qm-mek-hdmi.dts.
*/
/ {
passthrough {
/*
sound-hdmi-tx {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi-tx";
audio-cpu = <&sai_hdmi_tx>;
constraint-rate = <48000>;
protocol = <1>;
hdmi-out;
};
sound-amix-sai {
status = "disabled";
};
sound-hdmi-arc {
compatible = "fsl,imx-audio-spdif";
model = "imx-hdmi-arc";
spdif-controller = <&spdif1>;
spdif-in;
spdif-out;
};
*/
};
};
&hdmi {
compatible = "fsl,imx8qm-hdmi";
assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>,
<&clk IMX8QM_HDMI_PXL_LINK_SEL>,
<&clk IMX8QM_HDMI_PXL_MUX_SEL>;
assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>,
<&clk IMX8QM_HDMI_AV_PLL_CLK>,
<&clk IMX8QM_HDMI_AV_PLL_CLK>;
fsl,cec;
status = "okay";
};
/*
&amix {
status = "disabled";
};
&sai6 {
status = "disabled";
};
&sai7 {
status = "disabled";
};
&sai_hdmi_tx {
assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
<&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>;
fsl,sai-asynchronous;
status = "okay";
};
&sai_hdmi_rx {
fsl,sai-asynchronous;
status = "okay";
};
&spdif1 {
assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>;
status = "okay";
};
*/
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