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drivers/ata/pata_hpt37x.c
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/* * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. * * This driver is heavily based upon: * * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 * * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> * Portions Copyright (C) 2001 Sun Microsystems, Inc. * Portions Copyright (C) 2003 Red Hat Inc |
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* Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
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* * TODO |
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* Look into engine reset on timeout errors. Should not be required. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #define DRV_NAME "pata_hpt37x" |
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#define DRV_VERSION "0.6.23" |
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struct hpt_clock { u8 xfer_speed; u32 timing; }; struct hpt_chip { const char *name; unsigned int base; struct hpt_clock const *clocks[4]; }; /* key for bus clock timings * bit |
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* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. * cycles = value + 1 * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. * cycles = value + 1 * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
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* register access. |
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* 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
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* register access. |
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* 18:20 udma_cycle_time. Clock cycles for UDMA xfer. * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
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* register access. |
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* 28 UDMA enable. * 29 DMA enable. * 30 PIO_MST enable. If set, the chip is in bus master mode during * PIO xfer. * 31 FIFO enable. Only for PIO. |
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*/ |
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static struct hpt_clock hpt37x_timings_33[] = { { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ { XFER_UDMA_5, 0x12446231 }, { XFER_UDMA_4, 0x12446231 }, { XFER_UDMA_3, 0x126c6231 }, { XFER_UDMA_2, 0x12486231 }, { XFER_UDMA_1, 0x124c6233 }, { XFER_UDMA_0, 0x12506297 }, { XFER_MW_DMA_2, 0x22406c31 }, { XFER_MW_DMA_1, 0x22406c33 }, { XFER_MW_DMA_0, 0x22406c97 }, { XFER_PIO_4, 0x06414e31 }, { XFER_PIO_3, 0x06414e42 }, { XFER_PIO_2, 0x06414e53 }, { XFER_PIO_1, 0x06814e93 }, { XFER_PIO_0, 0x06814ea7 } |
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}; |
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static struct hpt_clock hpt37x_timings_50[] = { { XFER_UDMA_6, 0x12848242 }, { XFER_UDMA_5, 0x12848242 }, { XFER_UDMA_4, 0x12ac8242 }, { XFER_UDMA_3, 0x128c8242 }, { XFER_UDMA_2, 0x120c8242 }, { XFER_UDMA_1, 0x12148254 }, { XFER_UDMA_0, 0x121882ea }, { XFER_MW_DMA_2, 0x22808242 }, { XFER_MW_DMA_1, 0x22808254 }, { XFER_MW_DMA_0, 0x228082ea }, { XFER_PIO_4, 0x0a81f442 }, { XFER_PIO_3, 0x0a81f443 }, { XFER_PIO_2, 0x0a81f454 }, { XFER_PIO_1, 0x0ac1f465 }, { XFER_PIO_0, 0x0ac1f48a } |
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}; |
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static struct hpt_clock hpt37x_timings_66[] = { { XFER_UDMA_6, 0x1c869c62 }, { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ { XFER_UDMA_4, 0x1c8a9c62 }, { XFER_UDMA_3, 0x1c8e9c62 }, { XFER_UDMA_2, 0x1c929c62 }, { XFER_UDMA_1, 0x1c9a9c62 }, { XFER_UDMA_0, 0x1c829c62 }, { XFER_MW_DMA_2, 0x2c829c62 }, { XFER_MW_DMA_1, 0x2c829c66 }, { XFER_MW_DMA_0, 0x2c829d2e }, { XFER_PIO_4, 0x0c829c62 }, { XFER_PIO_3, 0x0c829c84 }, { XFER_PIO_2, 0x0c829ca6 }, { XFER_PIO_1, 0x0d029d26 }, { XFER_PIO_0, 0x0d029d5e } |
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}; |
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static const struct hpt_chip hpt370 = { "HPT370", 48, { |
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hpt37x_timings_33, |
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NULL, NULL, |
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NULL |
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} }; static const struct hpt_chip hpt370a = { "HPT370A", 48, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, |
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NULL |
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} }; static const struct hpt_chip hpt372 = { "HPT372", 55, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt302 = { "HPT302", 66, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt371 = { "HPT371", 66, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt372a = { "HPT372A", 66, { |
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hpt37x_timings_33, |
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NULL, |
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hpt37x_timings_50, hpt37x_timings_66 |
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} }; static const struct hpt_chip hpt374 = { "HPT374", 48, { |
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hpt37x_timings_33, |
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NULL, NULL, NULL } }; /** * hpt37x_find_mode - reset the hpt37x bus * @ap: ATA port * @speed: transfer mode * * Return the 32bit register programming information for this channel * that matches the speed provided. */ |
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|
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static u32 hpt37x_find_mode(struct ata_port *ap, int speed) { struct hpt_clock *clocks = ap->host->private_data; |
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|
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while (clocks->xfer_speed) { |
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if (clocks->xfer_speed == speed) return clocks->timing; clocks++; } BUG(); return 0xffffffffU; /* silence compiler warning */ } |
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static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char * const list[]) |
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{ |
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unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
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int i = 0; |
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ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
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|
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while (list[i] != NULL) { if (!strcmp(list[i], model_num)) { |
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pr_warn("%s is not supported for %s ", modestr, list[i]); |
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return 1; } i++; } return 0; } |
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static const char * const bad_ata33[] = { "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", |
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"Maxtor 90510D4", "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", |
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"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", |
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NULL }; |
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static const char * const bad_ata100_5[] = { |
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"IBM-DTLA-307075", "IBM-DTLA-307060", "IBM-DTLA-307045", "IBM-DTLA-307030", "IBM-DTLA-307020", "IBM-DTLA-307015", "IBM-DTLA-305040", "IBM-DTLA-305030", "IBM-DTLA-305020", "IC35L010AVER07-0", "IC35L020AVER07-0", "IC35L030AVER07-0", "IC35L040AVER07-0", "IC35L060AVER07-0", "WDC AC310200R", NULL }; /** * hpt370_filter - mode selection filter |
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* @adev: ATA device * * Block UDMA on devices that cause trouble with this controller. */ |
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|
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static unsigned long hpt370_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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if (adev->class == ATA_DEV_ATA) { |
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if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) mask &= ~ATA_MASK_UDMA; if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
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mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
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} |
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return mask; |
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} /** * hpt370a_filter - mode selection filter |
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* @adev: ATA device * * Block UDMA on devices that cause trouble with this controller. */ |
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static unsigned long hpt370a_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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if (adev->class == ATA_DEV_ATA) { |
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if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) |
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mask &= ~(0xE0 << ATA_SHIFT_UDMA); |
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} |
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return mask; |
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} |
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|
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/** |
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* hpt372_filter - mode selection filter * @adev: ATA device * @mask: mode mask * * The Marvell bridge chips used on the HighPoint SATA cards do not seem * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... */ static unsigned long hpt372_filter(struct ata_device *adev, unsigned long mask) { if (ata_id_is_sata(adev->id)) mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); return mask; } /** |
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* hpt37x_cable_detect - Detect the cable type * @ap: ATA port to detect on * * Return the cable type attached to this port */ static int hpt37x_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 scr2, ata66; pci_read_config_byte(pdev, 0x5B, &scr2); pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); |
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udelay(10); /* debounce */ |
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/* Cable register now active */ pci_read_config_byte(pdev, 0x5A, &ata66); /* Restore state */ pci_write_config_byte(pdev, 0x5B, scr2); if (ata66 & (2 >> ap->port_no)) return ATA_CBL_PATA40; else return ATA_CBL_PATA80; } /** * hpt374_fn1_cable_detect - Detect the cable type * @ap: ATA port to detect on * * Return the cable type attached to this port */ static int hpt374_fn1_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); unsigned int mcrbase = 0x50 + 4 * ap->port_no; u16 mcr3; u8 ata66; /* Do the extra channel work */ pci_read_config_word(pdev, mcrbase + 2, &mcr3); /* Set bit 15 of 0x52 to enable TCBLID as input */ pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000); pci_read_config_byte(pdev, 0x5A, &ata66); /* Reset TCBLID/FCBLID to output */ pci_write_config_word(pdev, mcrbase + 2, mcr3); if (ata66 & (2 >> ap->port_no)) return ATA_CBL_PATA40; else return ATA_CBL_PATA80; } /** |
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* hpt37x_pre_reset - reset the hpt37x bus |
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* @link: ATA link to reset |
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* @deadline: deadline jiffies for the operation |
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* |
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* Perform the initial reset handling for the HPT37x. |
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*/ |
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static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline) |
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{ |
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struct ata_port *ap = link->ap; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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static const struct pci_bits hpt37x_enable_bits[] = { { 0x50, 1, 0x04, 0x04 }, { 0x54, 1, 0x04, 0x04 } }; |
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if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) return -ENOENT; |
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|
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/* Reset the state machine */ |
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pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
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udelay(100); |
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return ata_sff_prereset(link, deadline); |
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} |
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static void hpt370_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) |
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{ struct pci_dev *pdev = to_pci_dev(ap->host->dev); u32 addr1, addr2; |
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u32 reg, timing, mask; |
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u8 fast; addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); addr2 = 0x51 + 4 * ap->port_no; |
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|
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/* Fast interrupt prediction disable, hold off interrupt disable */ pci_read_config_byte(pdev, addr2, &fast); fast &= ~0x02; fast |= 0x01; pci_write_config_byte(pdev, addr2, fast); |
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/* Determine timing mask and find matching mode entry */ if (mode < XFER_MW_DMA_0) mask = 0xcfc3ffff; else if (mode < XFER_UDMA_0) mask = 0x31c001ff; else mask = 0x303c0000; timing = hpt37x_find_mode(ap, mode); |
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pci_read_config_dword(pdev, addr1, ®); |
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reg = (reg & ~mask) | (timing & mask); pci_write_config_dword(pdev, addr1, reg); } /** * hpt370_set_piomode - PIO setup * @ap: ATA interface * @adev: device on the interface * * Perform PIO mode setup. */ static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) { hpt370_set_mode(ap, adev, adev->pio_mode); |
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} /** * hpt370_set_dmamode - DMA timing setup * @ap: ATA interface * @adev: Device being configured * |
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* Set up the channel for MWDMA or UDMA modes. |
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*/ |
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|
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static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) { |
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hpt370_set_mode(ap, adev, adev->dma_mode); |
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} /** |
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* hpt370_bmdma_end - DMA engine stop * @qc: ATA command * * Work around the HPT370 DMA engine. */ |
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|
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463 464 465 466 |
static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
0d5ff5667 libata: convert t... |
467 |
void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
56f46f8c8 pata_hpt37x: use ... |
468 469 |
u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS); u8 dma_cmd; |
85cd7251b [libata #pata-dri... |
470 |
|
56f46f8c8 pata_hpt37x: use ... |
471 |
if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db41 [libata] Add a bu... |
472 |
udelay(20); |
56f46f8c8 pata_hpt37x: use ... |
473 |
dma_stat = ioread8(bmdma + ATA_DMA_STATUS); |
669a5db41 [libata] Add a bu... |
474 |
} |
56f46f8c8 pata_hpt37x: use ... |
475 |
if (dma_stat & ATA_DMA_ACTIVE) { |
669a5db41 [libata] Add a bu... |
476 477 478 479 |
/* Clear the engine */ pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); udelay(10); /* Stop DMA */ |
56f46f8c8 pata_hpt37x: use ... |
480 481 |
dma_cmd = ioread8(bmdma + ATA_DMA_CMD); iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD); |
669a5db41 [libata] Add a bu... |
482 |
/* Clear Error */ |
56f46f8c8 pata_hpt37x: use ... |
483 484 485 |
dma_stat = ioread8(bmdma + ATA_DMA_STATUS); iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, bmdma + ATA_DMA_STATUS); |
669a5db41 [libata] Add a bu... |
486 487 488 489 490 491 |
/* Clear the engine */ pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); udelay(10); } ata_bmdma_stop(qc); } |
1a1b172b9 pata_hpt{37x|3x2n... |
492 493 |
static void hpt372_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode) |
669a5db41 [libata] Add a bu... |
494 495 496 |
{ struct pci_dev *pdev = to_pci_dev(ap->host->dev); u32 addr1, addr2; |
1a1b172b9 pata_hpt{37x|3x2n... |
497 |
u32 reg, timing, mask; |
669a5db41 [libata] Add a bu... |
498 499 500 501 |
u8 fast; addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); addr2 = 0x51 + 4 * ap->port_no; |
85cd7251b [libata #pata-dri... |
502 |
|
669a5db41 [libata] Add a bu... |
503 504 505 506 |
/* Fast interrupt prediction disable, hold off interrupt disable */ pci_read_config_byte(pdev, addr2, &fast); fast &= ~0x07; pci_write_config_byte(pdev, addr2, fast); |
85cd7251b [libata #pata-dri... |
507 |
|
1a1b172b9 pata_hpt{37x|3x2n... |
508 509 510 511 512 513 514 515 516 |
/* Determine timing mask and find matching mode entry */ if (mode < XFER_MW_DMA_0) mask = 0xcfc3ffff; else if (mode < XFER_UDMA_0) mask = 0x31c001ff; else mask = 0x303c0000; timing = hpt37x_find_mode(ap, mode); |
669a5db41 [libata] Add a bu... |
517 |
pci_read_config_dword(pdev, addr1, ®); |
1a1b172b9 pata_hpt{37x|3x2n... |
518 519 520 |
reg = (reg & ~mask) | (timing & mask); pci_write_config_dword(pdev, addr1, reg); } |
85cd7251b [libata #pata-dri... |
521 |
|
1a1b172b9 pata_hpt{37x|3x2n... |
522 523 524 525 526 527 528 529 530 531 532 |
/** * hpt372_set_piomode - PIO setup * @ap: ATA interface * @adev: device on the interface * * Perform PIO mode setup. */ static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) { hpt372_set_mode(ap, adev, adev->pio_mode); |
669a5db41 [libata] Add a bu... |
533 534 535 536 537 538 539 |
} /** * hpt372_set_dmamode - DMA timing setup * @ap: ATA interface * @adev: Device being configured * |
1a1b172b9 pata_hpt{37x|3x2n... |
540 |
* Set up the channel for MWDMA or UDMA modes. |
669a5db41 [libata] Add a bu... |
541 |
*/ |
85cd7251b [libata #pata-dri... |
542 |
|
669a5db41 [libata] Add a bu... |
543 544 |
static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) { |
1a1b172b9 pata_hpt{37x|3x2n... |
545 |
hpt372_set_mode(ap, adev, adev->dma_mode); |
669a5db41 [libata] Add a bu... |
546 547 548 549 550 551 552 553 |
} /** * hpt37x_bmdma_end - DMA engine stop * @qc: ATA command * * Clean up after the HPT372 and later DMA engine */ |
85cd7251b [libata #pata-dri... |
554 |
|
669a5db41 [libata] Add a bu... |
555 556 557 558 |
static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
6929da442 [PATCH] hpt37x: T... |
559 |
int mscreg = 0x50 + 4 * ap->port_no; |
669a5db41 [libata] Add a bu... |
560 |
u8 bwsr_stat, msc_stat; |
85cd7251b [libata #pata-dri... |
561 |
|
669a5db41 [libata] Add a bu... |
562 563 564 565 566 567 568 569 570 |
pci_read_config_byte(pdev, 0x6A, &bwsr_stat); pci_read_config_byte(pdev, mscreg, &msc_stat); if (bwsr_stat & (1 << ap->port_no)) pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); ata_bmdma_stop(qc); } static struct scsi_host_template hpt37x_sht = { |
68d1d07b5 libata: implement... |
571 |
ATA_BMDMA_SHT(DRV_NAME), |
669a5db41 [libata] Add a bu... |
572 573 574 575 576 |
}; /* * Configuration for HPT370 */ |
85cd7251b [libata #pata-dri... |
577 |
|
669a5db41 [libata] Add a bu... |
578 |
static struct ata_port_operations hpt370_port_ops = { |
029cfd6b7 libata: implement... |
579 |
.inherits = &ata_bmdma_port_ops, |
669a5db41 [libata] Add a bu... |
580 |
|
669a5db41 [libata] Add a bu... |
581 |
.bmdma_stop = hpt370_bmdma_stop, |
669a5db41 [libata] Add a bu... |
582 |
|
029cfd6b7 libata: implement... |
583 |
.mode_filter = hpt370_filter, |
9e87be9ed pata_hpt37x: add ... |
584 |
.cable_detect = hpt37x_cable_detect, |
029cfd6b7 libata: implement... |
585 586 |
.set_piomode = hpt370_set_piomode, .set_dmamode = hpt370_set_dmamode, |
a1efdaba2 libata: make rese... |
587 |
.prereset = hpt37x_pre_reset, |
85cd7251b [libata #pata-dri... |
588 |
}; |
669a5db41 [libata] Add a bu... |
589 590 591 592 |
/* * Configuration for HPT370A. Close to 370 but less filters */ |
85cd7251b [libata #pata-dri... |
593 |
|
669a5db41 [libata] Add a bu... |
594 |
static struct ata_port_operations hpt370a_port_ops = { |
029cfd6b7 libata: implement... |
595 |
.inherits = &hpt370_port_ops, |
669a5db41 [libata] Add a bu... |
596 |
.mode_filter = hpt370a_filter, |
85cd7251b [libata #pata-dri... |
597 |
}; |
669a5db41 [libata] Add a bu... |
598 599 |
/* |
8e834c2e6 pata_hpt{37x|3x2n... |
600 601 |
* Configuration for HPT371 and HPT302. Slightly different PIO and DMA * mode setting functionality. |
669a5db41 [libata] Add a bu... |
602 |
*/ |
85cd7251b [libata #pata-dri... |
603 |
|
8e834c2e6 pata_hpt{37x|3x2n... |
604 |
static struct ata_port_operations hpt302_port_ops = { |
029cfd6b7 libata: implement... |
605 |
.inherits = &ata_bmdma_port_ops, |
669a5db41 [libata] Add a bu... |
606 |
|
669a5db41 [libata] Add a bu... |
607 |
.bmdma_stop = hpt37x_bmdma_stop, |
669a5db41 [libata] Add a bu... |
608 |
|
9e87be9ed pata_hpt37x: add ... |
609 |
.cable_detect = hpt37x_cable_detect, |
029cfd6b7 libata: implement... |
610 611 |
.set_piomode = hpt372_set_piomode, .set_dmamode = hpt372_set_dmamode, |
a1efdaba2 libata: make rese... |
612 |
.prereset = hpt37x_pre_reset, |
85cd7251b [libata #pata-dri... |
613 |
}; |
669a5db41 [libata] Add a bu... |
614 615 |
/* |
8e834c2e6 pata_hpt{37x|3x2n... |
616 617 618 619 620 621 622 623 624 625 626 |
* Configuration for HPT372. Mode setting works like 371 and 302 * but we have a mode filter. */ static struct ata_port_operations hpt372_port_ops = { .inherits = &hpt302_port_ops, .mode_filter = hpt372_filter, }; /* * Configuration for HPT374. Mode setting and filtering works like 372 |
a1efdaba2 libata: make rese... |
627 |
* but we have a different cable detection procedure for function 1. |
669a5db41 [libata] Add a bu... |
628 |
*/ |
85cd7251b [libata #pata-dri... |
629 |
|
a1efdaba2 libata: make rese... |
630 |
static struct ata_port_operations hpt374_fn1_port_ops = { |
029cfd6b7 libata: implement... |
631 |
.inherits = &hpt372_port_ops, |
9e87be9ed pata_hpt37x: add ... |
632 |
.cable_detect = hpt374_fn1_cable_detect, |
85cd7251b [libata #pata-dri... |
633 |
}; |
669a5db41 [libata] Add a bu... |
634 635 |
/** |
ad452d64c trivial: fix comm... |
636 |
* hpt37x_clock_slot - Turn timing to PC clock entry |
669a5db41 [libata] Add a bu... |
637 638 639 640 641 642 |
* @freq: Reported frequency timing * @base: Base timing * * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 * and 3 for 66Mhz) */ |
85cd7251b [libata #pata-dri... |
643 |
|
669a5db41 [libata] Add a bu... |
644 645 646 647 648 649 650 651 652 653 654 655 656 657 |
static int hpt37x_clock_slot(unsigned int freq, unsigned int base) { unsigned int f = (base * freq) / 192; /* Mhz */ if (f < 40) return 0; /* 33Mhz slot */ if (f < 45) return 1; /* 40Mhz slot */ if (f < 55) return 2; /* 50Mhz slot */ return 3; /* 60Mhz slot */ } /** * hpt37x_calibrate_dpll - Calibrate the DPLL loop |
85cd7251b [libata #pata-dri... |
658 |
* @dev: PCI device |
669a5db41 [libata] Add a bu... |
659 660 661 662 663 664 665 666 667 668 |
* * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this * succeeds */ static int hpt37x_calibrate_dpll(struct pci_dev *dev) { u8 reg5b; u32 reg5c; int tries; |
85cd7251b [libata #pata-dri... |
669 |
|
49bfbd38b pata_hpt37x: codi... |
670 |
for (tries = 0; tries < 0x5000; tries++) { |
669a5db41 [libata] Add a bu... |
671 672 673 674 |
udelay(50); pci_read_config_byte(dev, 0x5b, ®5b); if (reg5b & 0x80) { /* See if it stays set */ |
49bfbd38b pata_hpt37x: codi... |
675 |
for (tries = 0; tries < 0x1000; tries++) { |
669a5db41 [libata] Add a bu... |
676 677 678 679 680 681 682 |
pci_read_config_byte(dev, 0x5b, ®5b); /* Failed ? */ if ((reg5b & 0x80) == 0) return 0; } /* Turn off tuning, we have the DPLL set */ pci_read_config_dword(dev, 0x5c, ®5c); |
49bfbd38b pata_hpt37x: codi... |
683 |
pci_write_config_dword(dev, 0x5c, reg5c & ~0x100); |
669a5db41 [libata] Add a bu... |
684 685 686 687 688 689 |
return 1; } } /* Never went stable */ return 0; } |
73946f9fc pata_hpt37x: Fix ... |
690 691 692 693 694 |
static u32 hpt374_read_freq(struct pci_dev *pdev) { u32 freq; unsigned long io_base = pci_resource_start(pdev, 4); |
49bfbd38b pata_hpt37x: codi... |
695 |
|
73946f9fc pata_hpt37x: Fix ... |
696 |
if (PCI_FUNC(pdev->devfn) & 1) { |
40f46f178 pata_hpt37x: chec... |
697 698 699 |
struct pci_dev *pdev_0; pdev_0 = pci_get_slot(pdev->bus, pdev->devfn - 1); |
73946f9fc pata_hpt37x: Fix ... |
700 701 702 703 704 705 |
/* Someone hot plugged the controller on us ? */ if (pdev_0 == NULL) return 0; io_base = pci_resource_start(pdev_0, 4); freq = inl(io_base + 0x90); pci_dev_put(pdev_0); |
40f46f178 pata_hpt37x: chec... |
706 |
} else |
73946f9fc pata_hpt37x: Fix ... |
707 708 709 |
freq = inl(io_base + 0x90); return freq; } |
669a5db41 [libata] Add a bu... |
710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 |
/** * hpt37x_init_one - Initialise an HPT37X/302 * @dev: PCI device * @id: Entry in match table * * Initialise an HPT37x device. There are some interesting complications * here. Firstly the chip may report 366 and be one of several variants. * Secondly all the timings depend on the clock for the chip which we must * detect and look up * * This is the known chip mappings. It may be missing a couple of later * releases. * * Chip version PCI Rev Notes * HPT366 4 (HPT366) 0 Other driver * HPT366 4 (HPT366) 1 Other driver * HPT368 4 (HPT366) 2 Other driver * HPT370 4 (HPT366) 3 UDMA100 * HPT370A 4 (HPT366) 4 UDMA100 * HPT372 4 (HPT366) 5 UDMA133 (1) * HPT372N 4 (HPT366) 6 Other driver * HPT372A 5 (HPT372) 1 UDMA133 (1) * HPT372N 5 (HPT372) 2 Other driver * HPT302 6 (HPT302) 1 UDMA133 * HPT302N 6 (HPT302) 2 Other driver * HPT371 7 (HPT371) * UDMA133 * HPT374 8 (HPT374) * UDMA133 4 channel * HPT372N 9 (HPT372N) * Other driver * * (1) UDMA133 support depends on the bus clock */ |
85cd7251b [libata #pata-dri... |
741 |
|
669a5db41 [libata] Add a bu... |
742 743 744 |
static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) { /* HPT370 - UDMA100 */ |
1626aeb88 libata: clean up ... |
745 |
static const struct ata_port_info info_hpt370 = { |
1d2808fd3 [libata] PATA dri... |
746 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
747 748 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85 [libata] Use ATA_... |
749 |
.udma_mask = ATA_UDMA5, |
669a5db41 [libata] Add a bu... |
750 751 752 |
.port_ops = &hpt370_port_ops }; /* HPT370A - UDMA100 */ |
1626aeb88 libata: clean up ... |
753 |
static const struct ata_port_info info_hpt370a = { |
1d2808fd3 [libata] PATA dri... |
754 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
755 756 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85 [libata] Use ATA_... |
757 |
.udma_mask = ATA_UDMA5, |
669a5db41 [libata] Add a bu... |
758 759 |
.port_ops = &hpt370a_port_ops }; |
fc2698d5e pata_hpt37x: actu... |
760 |
/* HPT370 - UDMA66 */ |
1626aeb88 libata: clean up ... |
761 |
static const struct ata_port_info info_hpt370_33 = { |
1d2808fd3 [libata] PATA dri... |
762 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
763 764 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
fc2698d5e pata_hpt37x: actu... |
765 |
.udma_mask = ATA_UDMA4, |
fcc2f69a6 pata_hpt37x: Upda... |
766 767 |
.port_ops = &hpt370_port_ops }; |
fc2698d5e pata_hpt37x: actu... |
768 |
/* HPT370A - UDMA66 */ |
1626aeb88 libata: clean up ... |
769 |
static const struct ata_port_info info_hpt370a_33 = { |
1d2808fd3 [libata] PATA dri... |
770 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
771 772 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
fc2698d5e pata_hpt37x: actu... |
773 |
.udma_mask = ATA_UDMA4, |
fcc2f69a6 pata_hpt37x: Upda... |
774 775 |
.port_ops = &hpt370a_port_ops }; |
8e834c2e6 pata_hpt{37x|3x2n... |
776 |
/* HPT372 - UDMA133 */ |
1626aeb88 libata: clean up ... |
777 |
static const struct ata_port_info info_hpt372 = { |
1d2808fd3 [libata] PATA dri... |
778 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
779 780 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85 [libata] Use ATA_... |
781 |
.udma_mask = ATA_UDMA6, |
669a5db41 [libata] Add a bu... |
782 783 |
.port_ops = &hpt372_port_ops }; |
8e834c2e6 pata_hpt{37x|3x2n... |
784 785 786 787 788 789 790 791 |
/* HPT371, 302 - UDMA133 */ static const struct ata_port_info info_hpt302 = { .flags = ATA_FLAG_SLAVE_POSS, .pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, .udma_mask = ATA_UDMA6, .port_ops = &hpt302_port_ops }; |
defed5593 pata_hpt37x: inhe... |
792 |
/* HPT374 - UDMA100, function 1 uses different cable_detect method */ |
a1efdaba2 libata: make rese... |
793 794 |
static const struct ata_port_info info_hpt374_fn0 = { .flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
795 796 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
a1efdaba2 libata: make rese... |
797 798 799 800 |
.udma_mask = ATA_UDMA5, .port_ops = &hpt372_port_ops }; static const struct ata_port_info info_hpt374_fn1 = { |
1d2808fd3 [libata] PATA dri... |
801 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
802 803 |
.pio_mask = ATA_PIO4, .mwdma_mask = ATA_MWDMA2, |
bf6263a85 [libata] Use ATA_... |
804 |
.udma_mask = ATA_UDMA5, |
a1efdaba2 libata: make rese... |
805 |
.port_ops = &hpt374_fn1_port_ops |
669a5db41 [libata] Add a bu... |
806 807 808 |
}; static const int MHz[4] = { 33, 40, 50, 66 }; |
1626aeb88 libata: clean up ... |
809 |
void *private_data = NULL; |
887125e37 libata: stop over... |
810 |
const struct ata_port_info *ppi[] = { NULL, NULL }; |
89d3b3603 ata: use pci_dev-... |
811 |
u8 rev = dev->revision; |
669a5db41 [libata] Add a bu... |
812 |
u8 irqmask; |
fcc2f69a6 pata_hpt37x: Upda... |
813 |
u8 mcr1; |
669a5db41 [libata] Add a bu... |
814 |
u32 freq; |
fcc2f69a6 pata_hpt37x: Upda... |
815 |
int prefer_dpll = 1; |
a617c09f6 libata: Trim trai... |
816 |
|
fcc2f69a6 pata_hpt37x: Upda... |
817 |
unsigned long iobase = pci_resource_start(dev, 4); |
669a5db41 [libata] Add a bu... |
818 819 820 |
const struct hpt_chip *chip_table; int clock_slot; |
f08048e94 libata: PCI devic... |
821 822 823 824 825 |
int rc; rc = pcim_enable_device(dev); if (rc) return rc; |
669a5db41 [libata] Add a bu... |
826 |
|
910f7bb16 pata_hpt37x: fold... |
827 828 |
switch (dev->device) { case PCI_DEVICE_ID_TTI_HPT366: |
669a5db41 [libata] Add a bu... |
829 830 |
/* May be a later chip in disguise. Check */ /* Older chips are in the HPT366 driver. Ignore them */ |
89d3b3603 ata: use pci_dev-... |
831 |
if (rev < 3) |
669a5db41 [libata] Add a bu... |
832 833 |
return -ENODEV; /* N series chips have their own driver. Ignore */ |
89d3b3603 ata: use pci_dev-... |
834 |
if (rev == 6) |
669a5db41 [libata] Add a bu... |
835 |
return -ENODEV; |
49bfbd38b pata_hpt37x: codi... |
836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 |
switch (rev) { case 3: ppi[0] = &info_hpt370; chip_table = &hpt370; prefer_dpll = 0; break; case 4: ppi[0] = &info_hpt370a; chip_table = &hpt370a; prefer_dpll = 0; break; case 5: ppi[0] = &info_hpt372; chip_table = &hpt372; break; default: |
8d7b1c70b ata: pata: Conver... |
852 853 854 |
pr_err("Unknown HPT366 subtype, please report (%d) ", rev); |
49bfbd38b pata_hpt37x: codi... |
855 |
return -ENODEV; |
669a5db41 [libata] Add a bu... |
856 |
} |
910f7bb16 pata_hpt37x: fold... |
857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 |
break; case PCI_DEVICE_ID_TTI_HPT372: /* 372N if rev >= 2 */ if (rev >= 2) return -ENODEV; ppi[0] = &info_hpt372; chip_table = &hpt372a; break; case PCI_DEVICE_ID_TTI_HPT302: /* 302N if rev > 1 */ if (rev > 1) return -ENODEV; ppi[0] = &info_hpt302; /* Check this */ chip_table = &hpt302; break; case PCI_DEVICE_ID_TTI_HPT371: if (rev > 1) return -ENODEV; ppi[0] = &info_hpt302; chip_table = &hpt371; /* * Single channel device, master is not present but the BIOS * (or us for non x86) must mark it absent */ pci_read_config_byte(dev, 0x50, &mcr1); mcr1 &= ~0x04; pci_write_config_byte(dev, 0x50, mcr1); break; case PCI_DEVICE_ID_TTI_HPT374: chip_table = &hpt374; if (!(PCI_FUNC(dev->devfn) & 1)) *ppi = &info_hpt374_fn0; else *ppi = &info_hpt374_fn1; break; default: |
8d7b1c70b ata: pata: Conver... |
894 895 |
pr_err("PCI table is bogus, please report (%d) ", dev->device); |
910f7bb16 pata_hpt37x: fold... |
896 |
return -ENODEV; |
669a5db41 [libata] Add a bu... |
897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 |
} /* Ok so this is a chip we support */ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); pci_read_config_byte(dev, 0x5A, &irqmask); irqmask &= ~0x10; pci_write_config_byte(dev, 0x5a, irqmask); /* * default to pci clock. make sure MA15/16 are set to output * to prevent drives having problems with 40-pin cables. Needed * for some drives such as IBM-DTLA which will not enter ready * state on reset when PDIAG is a input. */ |
85cd7251b [libata #pata-dri... |
915 |
pci_write_config_byte(dev, 0x5b, 0x23); |
a617c09f6 libata: Trim trai... |
916 |
|
fcc2f69a6 pata_hpt37x: Upda... |
917 918 919 920 921 922 |
/* * HighPoint does this for HPT372A. * NOTE: This register is only writeable via I/O space. */ if (chip_table == &hpt372a) outb(0x0e, iobase + 0x9c); |
85cd7251b [libata #pata-dri... |
923 |
|
49bfbd38b pata_hpt37x: codi... |
924 925 926 927 928 |
/* * Some devices do not let this value be accessed via PCI space * according to the old driver. In addition we must use the value * from FN 0 on the HPT374. */ |
73946f9fc pata_hpt37x: Fix ... |
929 930 931 932 933 934 935 |
if (chip_table == &hpt374) { freq = hpt374_read_freq(dev); if (freq == 0) return -ENODEV; } else freq = inl(iobase + 0x90); |
fcc2f69a6 pata_hpt37x: Upda... |
936 |
|
669a5db41 [libata] Add a bu... |
937 938 939 940 |
if ((freq >> 12) != 0xABCDE) { int i; u8 sr; u32 total = 0; |
85cd7251b [libata #pata-dri... |
941 |
|
8d7b1c70b ata: pata: Conver... |
942 943 |
pr_warn("BIOS has not set timing clocks "); |
85cd7251b [libata #pata-dri... |
944 |
|
669a5db41 [libata] Add a bu... |
945 |
/* This is the process the HPT371 BIOS is reported to use */ |
49bfbd38b pata_hpt37x: codi... |
946 |
for (i = 0; i < 128; i++) { |
669a5db41 [libata] Add a bu... |
947 |
pci_read_config_byte(dev, 0x78, &sr); |
fcc2f69a6 pata_hpt37x: Upda... |
948 |
total += sr & 0x1FF; |
669a5db41 [libata] Add a bu... |
949 950 951 952 953 |
udelay(15); } freq = total / 128; } freq &= 0x1FF; |
85cd7251b [libata #pata-dri... |
954 |
|
669a5db41 [libata] Add a bu... |
955 956 957 958 |
/* * Turn the frequency check into a band and then find a timing * table to match it. */ |
a617c09f6 libata: Trim trai... |
959 |
|
669a5db41 [libata] Add a bu... |
960 |
clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a6 pata_hpt37x: Upda... |
961 |
if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db41 [libata] Add a bu... |
962 963 |
/* * We need to try PLL mode instead |
fcc2f69a6 pata_hpt37x: Upda... |
964 965 966 |
* * For non UDMA133 capable devices we should * use a 50MHz DPLL by choice |
669a5db41 [libata] Add a bu... |
967 |
*/ |
fcc2f69a6 pata_hpt37x: Upda... |
968 |
unsigned int f_low, f_high; |
960c8a10c pata_hpt37x: Furt... |
969 |
int dpll, adjust; |
a617c09f6 libata: Trim trai... |
970 |
|
960c8a10c pata_hpt37x: Furt... |
971 |
/* Compute DPLL */ |
887125e37 libata: stop over... |
972 |
dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; |
a617c09f6 libata: Trim trai... |
973 |
|
960c8a10c pata_hpt37x: Furt... |
974 |
f_low = (MHz[clock_slot] * 48) / MHz[dpll]; |
fcc2f69a6 pata_hpt37x: Upda... |
975 |
f_high = f_low + 2; |
960c8a10c pata_hpt37x: Furt... |
976 977 |
if (clock_slot > 1) f_high += 2; |
fcc2f69a6 pata_hpt37x: Upda... |
978 979 980 |
/* Select the DPLL clock. */ pci_write_config_byte(dev, 0x5b, 0x21); |
49bfbd38b pata_hpt37x: codi... |
981 982 |
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
85cd7251b [libata #pata-dri... |
983 |
|
49bfbd38b pata_hpt37x: codi... |
984 |
for (adjust = 0; adjust < 8; adjust++) { |
669a5db41 [libata] Add a bu... |
985 986 |
if (hpt37x_calibrate_dpll(dev)) break; |
49bfbd38b pata_hpt37x: codi... |
987 988 989 990 |
/* * See if it'll settle at a fractionally * different clock */ |
64a817097 pata_hpt37x: Fix ... |
991 992 993 994 |
if (adjust & 1) f_low -= adjust >> 1; else f_high += adjust >> 1; |
49bfbd38b pata_hpt37x: codi... |
995 996 |
pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
669a5db41 [libata] Add a bu... |
997 998 |
} if (adjust == 8) { |
8d7b1c70b ata: pata: Conver... |
999 1000 |
pr_err("DPLL did not stabilize! "); |
669a5db41 [libata] Add a bu... |
1001 1002 |
return -ENODEV; } |
960c8a10c pata_hpt37x: Furt... |
1003 |
if (dpll == 3) |
1626aeb88 libata: clean up ... |
1004 |
private_data = (void *)hpt37x_timings_66; |
fcc2f69a6 pata_hpt37x: Upda... |
1005 |
else |
1626aeb88 libata: clean up ... |
1006 |
private_data = (void *)hpt37x_timings_50; |
85cd7251b [libata #pata-dri... |
1007 |
|
8d7b1c70b ata: pata: Conver... |
1008 1009 |
pr_info("bus clock %dMHz, using %dMHz DPLL ", |
40d69ba02 pata_hpt{37x|3x2n... |
1010 |
MHz[clock_slot], MHz[dpll]); |
669a5db41 [libata] Add a bu... |
1011 |
} else { |
1626aeb88 libata: clean up ... |
1012 |
private_data = (void *)chip_table->clocks[clock_slot]; |
669a5db41 [libata] Add a bu... |
1013 |
/* |
a47344685 pata_hpt37x: Furt... |
1014 1015 1016 |
* Perform a final fixup. Note that we will have used the * DPLL on the HPT372 which means we don't have to worry * about lack of UDMA133 support on lower clocks |
49bfbd38b pata_hpt37x: codi... |
1017 |
*/ |
85cd7251b [libata #pata-dri... |
1018 |
|
887125e37 libata: stop over... |
1019 1020 1021 1022 |
if (clock_slot < 2 && ppi[0] == &info_hpt370) ppi[0] = &info_hpt370_33; if (clock_slot < 2 && ppi[0] == &info_hpt370a) ppi[0] = &info_hpt370a_33; |
40d69ba02 pata_hpt{37x|3x2n... |
1023 |
|
8d7b1c70b ata: pata: Conver... |
1024 1025 |
pr_info("%s using %dMHz bus clock ", |
40d69ba02 pata_hpt{37x|3x2n... |
1026 |
chip_table->name, MHz[clock_slot]); |
669a5db41 [libata] Add a bu... |
1027 |
} |
fcc2f69a6 pata_hpt37x: Upda... |
1028 |
|
669a5db41 [libata] Add a bu... |
1029 |
/* Now kick off ATA set up */ |
1c5afdf7a libata-sff: separ... |
1030 |
return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0); |
669a5db41 [libata] Add a bu... |
1031 |
} |
2d2744fc8 [libata] PCI ID t... |
1032 1033 1034 1035 1036 1037 1038 1039 |
static const struct pci_device_id hpt37x[] = { { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, { }, |
669a5db41 [libata] Add a bu... |
1040 1041 1042 |
}; static struct pci_driver hpt37x_pci_driver = { |
49bfbd38b pata_hpt37x: codi... |
1043 |
.name = DRV_NAME, |
669a5db41 [libata] Add a bu... |
1044 |
.id_table = hpt37x, |
49bfbd38b pata_hpt37x: codi... |
1045 |
.probe = hpt37x_init_one, |
669a5db41 [libata] Add a bu... |
1046 1047 1048 1049 1050 1051 1052 |
.remove = ata_pci_remove_one }; static int __init hpt37x_init(void) { return pci_register_driver(&hpt37x_pci_driver); } |
669a5db41 [libata] Add a bu... |
1053 1054 1055 1056 |
static void __exit hpt37x_exit(void) { pci_unregister_driver(&hpt37x_pci_driver); } |
669a5db41 [libata] Add a bu... |
1057 1058 1059 1060 1061 1062 1063 1064 |
MODULE_AUTHOR("Alan Cox"); MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); MODULE_LICENSE("GPL"); MODULE_DEVICE_TABLE(pci, hpt37x); MODULE_VERSION(DRV_VERSION); module_init(hpt37x_init); module_exit(hpt37x_exit); |