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drivers/pci/probe.c
84.1 KB
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// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PCI detection and setup code |
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*/ #include <linux/kernel.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/pci.h> |
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#include <linux/msi.h> |
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#include <linux/of_device.h> |
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#include <linux/of_pci.h> |
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#include <linux/pci_hotplug.h> |
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#include <linux/slab.h> #include <linux/module.h> #include <linux/cpumask.h> |
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#include <linux/aer.h> |
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#include <linux/acpi.h> |
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#include <linux/hypervisor.h> |
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#include <linux/irqdomain.h> |
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#include <linux/pm_runtime.h> |
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#include "pci.h" |
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#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ #define CARDBUS_RESERVE_BUSNR 3 |
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|
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static struct resource busn_resource = { |
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.name = "PCI busn", .start = 0, .end = 255, .flags = IORESOURCE_BUS, }; |
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/* Ugh. Need to stop exporting this to modules. */ LIST_HEAD(pci_root_buses); EXPORT_SYMBOL(pci_root_buses); |
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static LIST_HEAD(pci_domain_busn_res_list); struct pci_domain_busn_res { struct list_head list; struct resource res; int domain_nr; }; static struct resource *get_pci_domain_busn_res(int domain_nr) { struct pci_domain_busn_res *r; list_for_each_entry(r, &pci_domain_busn_res_list, list) if (r->domain_nr == domain_nr) return &r->res; r = kzalloc(sizeof(*r), GFP_KERNEL); if (!r) return NULL; r->domain_nr = domain_nr; r->res.start = 0; r->res.end = 0xff; r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; list_add_tail(&r->list, &pci_domain_busn_res_list); return &r->res; } |
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/* |
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* Some device drivers need know if PCI is initiated. * Basically, we think PCI is not initiated when there |
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* is no device to be found on the pci_bus_type. |
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*/ int no_pci_devices(void) { |
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struct device *dev; int no_devices; |
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|
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dev = bus_find_next_device(&pci_bus_type, NULL); |
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no_devices = (dev == NULL); put_device(dev); return no_devices; } |
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EXPORT_SYMBOL(no_pci_devices); |
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/* |
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* PCI Bus Class */ |
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static void release_pcibus_dev(struct device *dev) |
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{ |
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struct pci_bus *pci_bus = to_pci_bus(dev); |
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put_device(pci_bus->bridge); |
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pci_bus_remove_resources(pci_bus); |
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pci_release_bus_of_node(pci_bus); |
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kfree(pci_bus); } static struct class pcibus_class = { .name = "pci_bus", |
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.dev_release = &release_pcibus_dev, |
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.dev_groups = pcibus_groups, |
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}; static int __init pcibus_class_init(void) { return class_register(&pcibus_class); } postcore_initcall(pcibus_class_init); |
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static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
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{ |
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u64 size = mask & maxbase; /* Find the significant bits */ |
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if (!size) return 0; |
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/* * Get the lowest of them to find the decode size, and from that * the extent. */ |
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size = size & ~(size-1); |
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|
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/* * base == maxbase can be valid only if the BAR has already been * programmed with all 1s. */ |
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if (base == maxbase && ((base | (size - 1)) & mask) != mask) |
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return 0; return size; } |
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static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
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{ |
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u32 mem_type; |
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unsigned long flags; |
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|
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if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
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flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; flags |= IORESOURCE_IO; return flags; |
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} |
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flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; flags |= IORESOURCE_MEM; if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) flags |= IORESOURCE_PREFETCH; |
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mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; switch (mem_type) { case PCI_BASE_ADDRESS_MEM_TYPE_32: break; case PCI_BASE_ADDRESS_MEM_TYPE_1M: |
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/* 1M mem BAR treated as 32-bit BAR */ |
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break; case PCI_BASE_ADDRESS_MEM_TYPE_64: |
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flags |= IORESOURCE_MEM_64; break; |
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default: |
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/* mem unknown type treated as 32-bit BAR */ |
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break; } |
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return flags; |
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} |
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#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
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/** |
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* pci_read_base - Read a PCI BAR |
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* @dev: the PCI device * @type: type of the BAR * @res: resource buffer to be filled in * @pos: BAR position in the config space * * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. |
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*/ |
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int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
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struct resource *res, unsigned int pos) |
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{ |
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u32 l = 0, sz = 0, mask; |
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u64 l64, sz64, mask64; |
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u16 orig_cmd; |
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struct pci_bus_region region, inverted_region; |
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|
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mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
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/* No printks while decoding is disabled! */ |
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if (!dev->mmio_always_on) { pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); |
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if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { pci_write_config_word(dev, PCI_COMMAND, orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); } |
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} |
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res->name = pci_name(dev); pci_read_config_dword(dev, pos, &l); |
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pci_write_config_dword(dev, pos, l | mask); |
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pci_read_config_dword(dev, pos, &sz); pci_write_config_dword(dev, pos, l); /* * All bits set in sz means the device isn't working properly. |
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* If the BAR isn't implemented, all bits must be 0. If it's a * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit * 1 must be clear. |
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*/ |
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if (sz == 0xffffffff) sz = 0; |
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/* * I don't know how l can have all bits set. Copied from old code. * Maybe it fixes a bug on some ancient platform. */ if (l == 0xffffffff) l = 0; if (type == pci_bar_unknown) { |
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res->flags = decode_bar(dev, l); res->flags |= IORESOURCE_SIZEALIGN; if (res->flags & IORESOURCE_IO) { |
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l64 = l & PCI_BASE_ADDRESS_IO_MASK; sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; |
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} else { |
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l64 = l & PCI_BASE_ADDRESS_MEM_MASK; sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
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} } else { |
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if (l & PCI_ROM_ADDRESS_ENABLE) res->flags |= IORESOURCE_ROM_ENABLE; |
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l64 = l & PCI_ROM_ADDRESS_MASK; sz64 = sz & PCI_ROM_ADDRESS_MASK; |
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mask64 = PCI_ROM_ADDRESS_MASK; |
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} |
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if (res->flags & IORESOURCE_MEM_64) { |
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pci_read_config_dword(dev, pos + 4, &l); pci_write_config_dword(dev, pos + 4, ~0); pci_read_config_dword(dev, pos + 4, &sz); pci_write_config_dword(dev, pos + 4, l); l64 |= ((u64)l << 32); sz64 |= ((u64)sz << 32); |
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mask64 |= ((u64)~0 << 32); } |
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if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
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if (!sz64) goto fail; |
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sz64 = pci_size(l64, sz64, mask64); |
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if (!sz64) { |
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pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size) ", |
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pos); |
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goto fail; |
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} |
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if (res->flags & IORESOURCE_MEM_64) { |
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if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) && sz64 > 0x100000000ULL) { |
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res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; res->start = 0; res->end = 0; |
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pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx) ", |
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pos, (unsigned long long)sz64); |
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goto out; |
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} |
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if ((sizeof(pci_bus_addr_t) < 8) && l) { |
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/* Above 32-bit boundary; try to reallocate */ |
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res->flags |= IORESOURCE_UNSET; |
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res->start = 0; |
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res->end = sz64 - 1; |
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pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx) ", |
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pos, (unsigned long long)l64); |
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goto out; |
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} |
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} |
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region.start = l64; |
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region.end = l64 + sz64 - 1; |
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pcibios_bus_to_resource(dev->bus, res, ®ion); pcibios_resource_to_bus(dev->bus, &inverted_region, res); |
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/* * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is * the corresponding resource address (the physical address used by * the CPU. Converting that resource address back to a bus address * should yield the original BAR value: * * resource_to_bus(bus_to_resource(A)) == A * * If it doesn't, CPU accesses to "bus_to_resource(A)" will not * be claimed by the device. */ if (inverted_region.start != region.start) { |
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res->flags |= IORESOURCE_UNSET; |
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res->start = 0; |
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res->end = region.end - region.start; |
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pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid ", |
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pos, (unsigned long long)region.start); |
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} |
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goto out; fail: res->flags = 0; out: |
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if (res->flags) |
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pci_info(dev, "reg 0x%x: %pR ", pos, res); |
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return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
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} |
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { |
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unsigned int pos, reg; |
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|
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if (dev->non_compliant_bars) return; |
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/* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ if (dev->is_virtfn) return; |
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for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; |
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reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
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pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
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} |
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if (rom) { |
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struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
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dev->rom_base_reg = rom; |
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res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; |
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__pci_read_base(dev, pci_bar_mem32, res, rom); |
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} } |
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static void pci_read_bridge_windows(struct pci_dev *bridge) { u16 io; u32 pmem, tmp; pci_read_config_word(bridge, PCI_IO_BASE, &io); if (!io) { pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); pci_read_config_word(bridge, PCI_IO_BASE, &io); pci_write_config_word(bridge, PCI_IO_BASE, 0x0); } if (io) bridge->io_window = 1; /* * DECchip 21050 pass 2 errata: the bridge may miss an address * disconnect boundary by one PCI data phase. Workaround: do not * use prefetching on this device. */ if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) return; pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); if (!pmem) { pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0xffe0fff0); pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); } if (!pmem) return; bridge->pref_window = 1; if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { /* * Bridge claims to have a 64-bit prefetchable memory * window; verify that the upper bits are actually * writable. */ pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0xffffffff); pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); if (tmp) bridge->pref_64_window = 1; } } |
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static void pci_read_bridge_io(struct pci_bus *child) |
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{ struct pci_dev *dev = child->self; u8 io_base_lo, io_limit_lo; |
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unsigned long io_mask, io_granularity, base, limit; |
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struct pci_bus_region region; |
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struct resource *res; io_mask = PCI_IO_RANGE_MASK; io_granularity = 0x1000; if (dev->io_window_1k) { /* Support 1K I/O space granularity */ io_mask = PCI_IO_1K_RANGE_MASK; io_granularity = 0x400; } |
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res = child->resource[0]; pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
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base = (io_base_lo & io_mask) << 8; limit = (io_limit_lo & io_mask) << 8; |
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if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { u16 io_base_hi, io_limit_hi; |
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pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); |
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base |= ((unsigned long) io_base_hi << 16); limit |= ((unsigned long) io_limit_hi << 16); |
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} |
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if (base <= limit) { |
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res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
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region.start = base; |
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region.end = limit + io_granularity - 1; |
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pcibios_bus_to_resource(dev->bus, res, ®ion); |
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pci_info(dev, " bridge window %pR ", res); |
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} |
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} |
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static void pci_read_bridge_mmio(struct pci_bus *child) |
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{ struct pci_dev *dev = child->self; u16 mem_base_lo, mem_limit_lo; unsigned long base, limit; |
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struct pci_bus_region region; |
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struct resource *res; |
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res = child->resource[1]; pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); |
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base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; |
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if (base <= limit) { |
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res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
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region.start = base; region.end = limit + 0xfffff; |
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pcibios_bus_to_resource(dev->bus, res, ®ion); |
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pci_info(dev, " bridge window %pR ", res); |
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} |
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} |
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static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
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{ struct pci_dev *dev = child->self; u16 mem_base_lo, mem_limit_lo; |
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450 |
u64 base64, limit64; |
3a9ad0b4f
|
451 |
pci_bus_addr_t base, limit; |
5bfa14ed9
|
452 |
struct pci_bus_region region; |
fa27b2d10
|
453 |
struct resource *res; |
1da177e4c
|
454 455 456 457 |
res = child->resource[2]; pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); |
7fc986d8a
|
458 459 |
base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; |
1da177e4c
|
460 461 462 |
if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { u32 mem_base_hi, mem_limit_hi; |
8f38eaca5
|
463 |
|
1da177e4c
|
464 465 466 467 468 469 470 471 472 |
pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); /* * Some bridges set the base > limit by default, and some * (broken) BIOSes do not initialize them. If we find * this, just assume they are not being used. */ if (mem_base_hi <= mem_limit_hi) { |
7fc986d8a
|
473 474 |
base64 |= (u64) mem_base_hi << 32; limit64 |= (u64) mem_limit_hi << 32; |
1da177e4c
|
475 476 |
} } |
7fc986d8a
|
477 |
|
3a9ad0b4f
|
478 479 |
base = (pci_bus_addr_t) base64; limit = (pci_bus_addr_t) limit64; |
7fc986d8a
|
480 481 |
if (base != base64) { |
7506dc798
|
482 483 |
pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx) ", |
7fc986d8a
|
484 485 486 |
(unsigned long long) base64); return; } |
5dde383e2
|
487 |
if (base <= limit) { |
1f82de10d
|
488 489 490 491 |
res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; if (res->flags & PCI_PREF_RANGE_TYPE_64) res->flags |= IORESOURCE_MEM_64; |
5bfa14ed9
|
492 493 |
region.start = base; region.end = limit + 0xfffff; |
fc2798502
|
494 |
pcibios_bus_to_resource(dev->bus, res, ®ion); |
34c6b7105
|
495 496 |
pci_info(dev, " bridge window %pR ", res); |
1da177e4c
|
497 498 |
} } |
15856ad50
|
499 |
void pci_read_bridge_bases(struct pci_bus *child) |
fa27b2d10
|
500 501 |
{ struct pci_dev *dev = child->self; |
2fe2abf89
|
502 |
struct resource *res; |
fa27b2d10
|
503 504 505 506 |
int i; if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ return; |
7506dc798
|
507 508 |
pci_info(dev, "PCI bridge to %pR%s ", |
b918c62e0
|
509 |
&child->busn_res, |
fa27b2d10
|
510 |
dev->transparent ? " (subtractive decode)" : ""); |
2fe2abf89
|
511 512 513 |
pci_bus_remove_resources(child); for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
fa27b2d10
|
514 515 516 |
pci_read_bridge_io(child); pci_read_bridge_mmio(child); pci_read_bridge_mmio_pref(child); |
2adf75160
|
517 518 |
if (dev->transparent) { |
2fe2abf89
|
519 |
pci_bus_for_each_resource(child->parent, res, i) { |
d739a099d
|
520 |
if (res && res->flags) { |
2fe2abf89
|
521 522 |
pci_bus_add_resource(child, res, PCI_SUBTRACTIVE_DECODE); |
34c6b7105
|
523 524 |
pci_info(dev, " bridge window %pR (subtractive decode) ", |
2fe2abf89
|
525 526 |
res); } |
2adf75160
|
527 528 |
} } |
fa27b2d10
|
529 |
} |
670ba0c88
|
530 |
static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
1da177e4c
|
531 532 |
{ struct pci_bus *b; |
f5afe8064
|
533 |
b = kzalloc(sizeof(*b), GFP_KERNEL); |
050134864
|
534 535 536 537 538 539 540 541 542 543 |
if (!b) return NULL; INIT_LIST_HEAD(&b->node); INIT_LIST_HEAD(&b->children); INIT_LIST_HEAD(&b->devices); INIT_LIST_HEAD(&b->slots); INIT_LIST_HEAD(&b->resources); b->max_bus_speed = PCI_SPEED_UNKNOWN; b->cur_bus_speed = PCI_SPEED_UNKNOWN; |
670ba0c88
|
544 545 546 547 |
#ifdef CONFIG_PCI_DOMAINS_GENERIC if (parent) b->domain_nr = parent->domain_nr; #endif |
1da177e4c
|
548 549 |
return b; } |
9885440b1
|
550 |
static void pci_release_host_bridge_dev(struct device *dev) |
70efde2a2
|
551 552 553 554 555 |
{ struct pci_host_bridge *bridge = to_pci_host_bridge(dev); if (bridge->release_fn) bridge->release_fn(bridge); |
3bbce5317
|
556 557 |
pci_free_resource_list(&bridge->windows); |
7608158df
|
558 |
pci_free_resource_list(&bridge->dma_ranges); |
9885440b1
|
559 |
kfree(bridge); |
70efde2a2
|
560 |
} |
6302bf3ef
|
561 |
static void pci_init_host_bridge(struct pci_host_bridge *bridge) |
7b5436635
|
562 |
{ |
050134864
|
563 |
INIT_LIST_HEAD(&bridge->windows); |
e80a91ad3
|
564 |
INIT_LIST_HEAD(&bridge->dma_ranges); |
37d6a0a6f
|
565 |
|
02bfeb484
|
566 567 568 569 570 571 572 |
/* * We assume we can manage these PCIe features. Some systems may * reserve these for use by the platform itself, e.g., an ACPI BIOS * may implement its own AER handling and use _OSC to prevent the * OS from interfering. */ bridge->native_aer = 1; |
9310f0dc1
|
573 |
bridge->native_pcie_hotplug = 1; |
1df81a6d6
|
574 |
bridge->native_shpc_hotplug = 1; |
02bfeb484
|
575 |
bridge->native_pme = 1; |
af8bb9f89
|
576 |
bridge->native_ltr = 1; |
ac1c8e35a
|
577 |
bridge->native_dpc = 1; |
9885440b1
|
578 579 |
device_initialize(&bridge->dev); |
6302bf3ef
|
580 581 582 583 584 585 586 587 588 589 590 591 |
} struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) { struct pci_host_bridge *bridge; bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); if (!bridge) return NULL; pci_init_host_bridge(bridge); bridge->dev.release = pci_release_host_bridge_dev; |
02bfeb484
|
592 |
|
7b5436635
|
593 594 |
return bridge; } |
a52d1443b
|
595 |
EXPORT_SYMBOL(pci_alloc_host_bridge); |
7b5436635
|
596 |
|
9885440b1
|
597 598 599 600 |
static void devm_pci_alloc_host_bridge_release(void *data) { pci_free_host_bridge(data); } |
5c3f18cce
|
601 602 603 |
struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, size_t priv) { |
9885440b1
|
604 |
int ret; |
5c3f18cce
|
605 |
struct pci_host_bridge *bridge; |
9885440b1
|
606 |
bridge = pci_alloc_host_bridge(priv); |
5c3f18cce
|
607 608 |
if (!bridge) return NULL; |
6a589900d
|
609 |
bridge->dev.parent = dev; |
9885440b1
|
610 611 612 613 |
ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, bridge); if (ret) return NULL; |
5c3f18cce
|
614 |
|
669cbc708
|
615 616 617 |
ret = devm_of_pci_bridge_init(dev, bridge); if (ret) return NULL; |
5c3f18cce
|
618 619 620 |
return bridge; } EXPORT_SYMBOL(devm_pci_alloc_host_bridge); |
dff79b91b
|
621 622 |
void pci_free_host_bridge(struct pci_host_bridge *bridge) { |
9885440b1
|
623 |
put_device(&bridge->dev); |
dff79b91b
|
624 625 |
} EXPORT_SYMBOL(pci_free_host_bridge); |
e56faff57
|
626 |
/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ |
0b950f0f3
|
627 |
static const unsigned char pcix_bus_speed[] = { |
9be60ca04
|
628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 |
PCI_SPEED_UNKNOWN, /* 0 */ PCI_SPEED_66MHz_PCIX, /* 1 */ PCI_SPEED_100MHz_PCIX, /* 2 */ PCI_SPEED_133MHz_PCIX, /* 3 */ PCI_SPEED_UNKNOWN, /* 4 */ PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ PCI_SPEED_UNKNOWN, /* 8 */ PCI_SPEED_66MHz_PCIX_266, /* 9 */ PCI_SPEED_100MHz_PCIX_266, /* A */ PCI_SPEED_133MHz_PCIX_266, /* B */ PCI_SPEED_UNKNOWN, /* C */ PCI_SPEED_66MHz_PCIX_533, /* D */ PCI_SPEED_100MHz_PCIX_533, /* E */ PCI_SPEED_133MHz_PCIX_533 /* F */ }; |
e56faff57
|
645 |
/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ |
343e51ae6
|
646 |
const unsigned char pcie_link_speed[] = { |
3749c51ac
|
647 648 649 |
PCI_SPEED_UNKNOWN, /* 0 */ PCIE_SPEED_2_5GT, /* 1 */ PCIE_SPEED_5_0GT, /* 2 */ |
9dfd97fe1
|
650 |
PCIE_SPEED_8_0GT, /* 3 */ |
1acfb9b7e
|
651 |
PCIE_SPEED_16_0GT, /* 4 */ |
de76cda21
|
652 |
PCIE_SPEED_32_0GT, /* 5 */ |
3749c51ac
|
653 654 655 656 657 658 659 660 661 662 663 |
PCI_SPEED_UNKNOWN, /* 6 */ PCI_SPEED_UNKNOWN, /* 7 */ PCI_SPEED_UNKNOWN, /* 8 */ PCI_SPEED_UNKNOWN, /* 9 */ PCI_SPEED_UNKNOWN, /* A */ PCI_SPEED_UNKNOWN, /* B */ PCI_SPEED_UNKNOWN, /* C */ PCI_SPEED_UNKNOWN, /* D */ PCI_SPEED_UNKNOWN, /* E */ PCI_SPEED_UNKNOWN /* F */ }; |
e56faff57
|
664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 |
EXPORT_SYMBOL_GPL(pcie_link_speed); const char *pci_speed_string(enum pci_bus_speed speed) { /* Indexed by the pci_bus_speed enum */ static const char *speed_strings[] = { "33 MHz PCI", /* 0x00 */ "66 MHz PCI", /* 0x01 */ "66 MHz PCI-X", /* 0x02 */ "100 MHz PCI-X", /* 0x03 */ "133 MHz PCI-X", /* 0x04 */ NULL, /* 0x05 */ NULL, /* 0x06 */ NULL, /* 0x07 */ NULL, /* 0x08 */ "66 MHz PCI-X 266", /* 0x09 */ "100 MHz PCI-X 266", /* 0x0a */ "133 MHz PCI-X 266", /* 0x0b */ "Unknown AGP", /* 0x0c */ "1x AGP", /* 0x0d */ "2x AGP", /* 0x0e */ "4x AGP", /* 0x0f */ "8x AGP", /* 0x10 */ "66 MHz PCI-X 533", /* 0x11 */ "100 MHz PCI-X 533", /* 0x12 */ "133 MHz PCI-X 533", /* 0x13 */ "2.5 GT/s PCIe", /* 0x14 */ "5.0 GT/s PCIe", /* 0x15 */ "8.0 GT/s PCIe", /* 0x16 */ "16.0 GT/s PCIe", /* 0x17 */ "32.0 GT/s PCIe", /* 0x18 */ }; if (speed < ARRAY_SIZE(speed_strings)) return speed_strings[speed]; return "Unknown"; } EXPORT_SYMBOL_GPL(pci_speed_string); |
3749c51ac
|
702 703 704 |
void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) { |
231afea18
|
705 |
bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
3749c51ac
|
706 707 |
} EXPORT_SYMBOL_GPL(pcie_update_link_speed); |
45b4cdd57
|
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 |
static unsigned char agp_speeds[] = { AGP_UNKNOWN, AGP_1X, AGP_2X, AGP_4X, AGP_8X }; static enum pci_bus_speed agp_speed(int agp3, int agpstat) { int index = 0; if (agpstat & 4) index = 3; else if (agpstat & 2) index = 2; else if (agpstat & 1) index = 1; else goto out; |
f7625980f
|
728 |
|
45b4cdd57
|
729 730 731 732 733 734 735 736 737 |
if (agp3) { index += 2; if (index == 5) index = 0; } out: return agp_speeds[index]; } |
9be60ca04
|
738 739 740 741 |
static void pci_set_bus_speed(struct pci_bus *bus) { struct pci_dev *bridge = bus->self; int pos; |
45b4cdd57
|
742 743 744 745 746 747 748 749 750 751 752 753 |
pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); if (!pos) pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); if (pos) { u32 agpstat, agpcmd; pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); } |
9be60ca04
|
754 755 756 757 |
pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); if (pos) { u16 status; enum pci_bus_speed max; |
9be60ca04
|
758 |
|
7793eeabc
|
759 760 761 762 |
pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, &status); if (status & PCI_X_SSTATUS_533MHZ) { |
9be60ca04
|
763 |
max = PCI_SPEED_133MHz_PCIX_533; |
7793eeabc
|
764 |
} else if (status & PCI_X_SSTATUS_266MHZ) { |
9be60ca04
|
765 |
max = PCI_SPEED_133MHz_PCIX_266; |
7793eeabc
|
766 |
} else if (status & PCI_X_SSTATUS_133MHZ) { |
3c78bc61f
|
767 |
if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
9be60ca04
|
768 |
max = PCI_SPEED_133MHz_PCIX_ECC; |
3c78bc61f
|
769 |
else |
9be60ca04
|
770 |
max = PCI_SPEED_133MHz_PCIX; |
9be60ca04
|
771 772 773 774 775 |
} else { max = PCI_SPEED_66MHz_PCIX; } bus->max_bus_speed = max; |
7793eeabc
|
776 777 |
bus->cur_bus_speed = pcix_bus_speed[ (status & PCI_X_SSTATUS_FREQ) >> 6]; |
9be60ca04
|
778 779 780 |
return; } |
fdfe15112
|
781 |
if (pci_is_pcie(bridge)) { |
9be60ca04
|
782 783 |
u32 linkcap; u16 linksta; |
59875ae48
|
784 |
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
231afea18
|
785 |
bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
f0157160b
|
786 |
bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC); |
9be60ca04
|
787 |
|
59875ae48
|
788 |
pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
9be60ca04
|
789 790 791 |
pcie_update_link_speed(bus, linksta); } } |
44aa0c657
|
792 793 |
static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) { |
b165e2b60
|
794 |
struct irq_domain *d; |
44aa0c657
|
795 796 797 798 |
/* * Any firmware interface that can resolve the msi_domain * should be called from here. */ |
b165e2b60
|
799 |
d = pci_host_bridge_of_msi_domain(bus); |
471036b2b
|
800 801 |
if (!d) d = pci_host_bridge_acpi_msi_domain(bus); |
44aa0c657
|
802 |
|
788858ebc
|
803 804 805 806 807 808 809 810 811 812 813 814 815 |
#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN /* * If no IRQ domain was found via the OF tree, try looking it up * directly through the fwnode_handle. */ if (!d) { struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); if (fwnode) d = irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI); } #endif |
b165e2b60
|
816 |
return d; |
44aa0c657
|
817 818 819 820 821 |
} static void pci_set_bus_msi_domain(struct pci_bus *bus) { struct irq_domain *d; |
38ea72bdb
|
822 |
struct pci_bus *b; |
44aa0c657
|
823 824 |
/* |
38ea72bdb
|
825 826 827 |
* The bus can be a root bus, a subordinate bus, or a virtual bus * created by an SR-IOV device. Walk up to the first bridge device * found or derive the domain from the host bridge. |
44aa0c657
|
828 |
*/ |
38ea72bdb
|
829 830 831 832 833 834 835 |
for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { if (b->self) d = dev_get_msi_domain(&b->self->dev); } if (!d) d = pci_host_bridge_msi_domain(b); |
44aa0c657
|
836 837 838 |
dev_set_msi_domain(&bus->dev, d); } |
cea9bc0be
|
839 |
static int pci_register_host_bridge(struct pci_host_bridge *bridge) |
37d6a0a6f
|
840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 |
{ struct device *parent = bridge->dev.parent; struct resource_entry *window, *n; struct pci_bus *bus, *b; resource_size_t offset; LIST_HEAD(resources); struct resource *res; char addr[64], *fmt; const char *name; int err; bus = pci_alloc_bus(NULL); if (!bus) return -ENOMEM; bridge->bus = bus; |
3e466e2d3
|
856 |
/* Temporarily move resources off the list */ |
37d6a0a6f
|
857 858 859 860 861 862 863 864 865 866 867 |
list_splice_init(&bridge->windows, &resources); bus->sysdata = bridge->sysdata; bus->msi = bridge->msi; bus->ops = bridge->ops; bus->number = bus->busn_res.start = bridge->busnr; #ifdef CONFIG_PCI_DOMAINS_GENERIC bus->domain_nr = pci_bus_find_domain_nr(bus, parent); #endif b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); if (b) { |
3e466e2d3
|
868 |
/* Ignore it if we already got here via a different bridge */ |
37d6a0a6f
|
869 870 871 872 873 874 875 876 877 878 879 880 |
dev_dbg(&b->dev, "bus already known "); err = -EEXIST; goto free; } dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), bridge->busnr); err = pcibios_root_bridge_prepare(bridge); if (err) goto free; |
9885440b1
|
881 |
err = device_add(&bridge->dev); |
1b54ae832
|
882 |
if (err) { |
37d6a0a6f
|
883 |
put_device(&bridge->dev); |
1b54ae832
|
884 885 |
goto free; } |
37d6a0a6f
|
886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 |
bus->bridge = get_device(&bridge->dev); device_enable_async_suspend(bus->bridge); pci_set_bus_of_node(bus); pci_set_bus_msi_domain(bus); if (!parent) set_dev_node(bus->bridge, pcibus_to_node(bus)); bus->dev.class = &pcibus_class; bus->dev.parent = bus->bridge; dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); name = dev_name(&bus->dev); err = device_register(&bus->dev); if (err) goto unregister; pcibios_add_bus(bus); |
6e8e104d2
|
905 906 907 908 909 910 |
if (bus->ops->add_bus) { err = bus->ops->add_bus(bus); if (WARN_ON(err < 0)) dev_err(&bus->dev, "failed to add bus: %d ", err); } |
37d6a0a6f
|
911 912 913 914 915 916 917 918 919 |
/* Create legacy_io and legacy_mem files for this bus */ pci_create_legacy_files(bus); if (parent) dev_info(parent, "PCI host bridge to bus %s ", name); else pr_info("PCI host bridge to bus %s ", name); |
ad5086108
|
920 921 922 |
if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced "); |
37d6a0a6f
|
923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 |
/* Add initial resources to the bus */ resource_list_for_each_entry_safe(window, n, &resources) { list_move_tail(&window->node, &bridge->windows); offset = window->offset; res = window->res; if (res->flags & IORESOURCE_BUS) pci_bus_insert_busn_res(bus, bus->number, res->end); else pci_bus_add_resource(bus, res, 0); if (offset) { if (resource_type(res) == IORESOURCE_IO) fmt = " (bus address [%#06llx-%#06llx])"; else fmt = " (bus address [%#010llx-%#010llx])"; snprintf(addr, sizeof(addr), fmt, (unsigned long long)(res->start - offset), (unsigned long long)(res->end - offset)); } else addr[0] = '\0'; dev_info(&bus->dev, "root bus resource %pR%s ", res, addr); } down_write(&pci_bus_sem); list_add_tail(&bus->node, &pci_root_buses); up_write(&pci_bus_sem); return 0; unregister: put_device(&bridge->dev); |
9885440b1
|
958 |
device_del(&bridge->dev); |
37d6a0a6f
|
959 960 961 962 963 |
free: kfree(bus); return err; } |
17e8f0d4c
|
964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 |
static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) { int pos; u32 status; /* * If extended config space isn't accessible on a bridge's primary * bus, we certainly can't access it on the secondary bus. */ if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) return false; /* * PCIe Root Ports and switch ports are PCIe on both sides, so if * extended config space is accessible on the primary, it's also * accessible on the secondary. */ if (pci_is_pcie(bridge) && (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) return true; /* * For the other bridge types: * - PCI-to-PCI bridges * - PCIe-to-PCI/PCI-X forward bridges * - PCI/PCI-X-to-PCIe reverse bridges * extended config space on the secondary side is only accessible * if the bridge supports PCI-X Mode 2. */ pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); if (!pos) return false; pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); } |
cbd4e055f
|
1002 1003 |
static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) |
1da177e4c
|
1004 1005 |
{ struct pci_bus *child; |
07e292950
|
1006 |
struct pci_host_bridge *host; |
1da177e4c
|
1007 |
int i; |
4f535093c
|
1008 |
int ret; |
1da177e4c
|
1009 |
|
3e466e2d3
|
1010 |
/* Allocate a new bus and inherit stuff from the parent */ |
670ba0c88
|
1011 |
child = pci_alloc_bus(parent); |
1da177e4c
|
1012 1013 |
if (!child) return NULL; |
1da177e4c
|
1014 |
child->parent = parent; |
0cbdcfcf4
|
1015 |
child->msi = parent->msi; |
1da177e4c
|
1016 |
child->sysdata = parent->sysdata; |
6e325a62a
|
1017 |
child->bus_flags = parent->bus_flags; |
1da177e4c
|
1018 |
|
07e292950
|
1019 1020 1021 1022 1023 |
host = pci_find_host_bridge(parent); if (host->child_ops) child->ops = host->child_ops; else child->ops = parent->ops; |
3e466e2d3
|
1024 1025 1026 |
/* * Initialize some portions of the bus device, but don't register * it now as the parent is not properly set up yet. |
fd7d1ced2
|
1027 1028 |
*/ child->dev.class = &pcibus_class; |
1a9271331
|
1029 |
dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4c
|
1030 |
|
3e466e2d3
|
1031 |
/* Set up the primary, secondary and subordinate bus numbers */ |
b918c62e0
|
1032 1033 1034 |
child->number = child->busn_res.start = busnr; child->primary = parent->busn_res.start; child->busn_res.end = 0xff; |
1da177e4c
|
1035 |
|
4f535093c
|
1036 1037 1038 1039 |
if (!bridge) { child->dev.parent = parent->bridge; goto add_dev; } |
3789fa8a2
|
1040 1041 1042 |
child->self = bridge; child->bridge = get_device(&bridge->dev); |
4f535093c
|
1043 |
child->dev.parent = child->bridge; |
98d9f30c8
|
1044 |
pci_set_bus_of_node(child); |
9be60ca04
|
1045 |
pci_set_bus_speed(child); |
17e8f0d4c
|
1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 |
/* * Check whether extended config space is accessible on the child * bus. Note that we currently assume it is always accessible on * the root bus. */ if (!pci_bridge_child_ext_cfg_accessible(bridge)) { child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; pci_info(child, "extended config space not accessible "); } |
3e466e2d3
|
1056 |
/* Set up default resource pointers and names */ |
fde09c6d8
|
1057 |
for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4c
|
1058 1059 1060 1061 |
child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; child->resource[i]->name = child->name; } bridge->subordinate = child; |
4f535093c
|
1062 |
add_dev: |
44aa0c657
|
1063 |
pci_set_bus_msi_domain(child); |
4f535093c
|
1064 1065 |
ret = device_register(&child->dev); WARN_ON(ret < 0); |
10a957475
|
1066 |
pcibios_add_bus(child); |
057bd2e05
|
1067 1068 1069 1070 1071 1072 |
if (child->ops->add_bus) { ret = child->ops->add_bus(child); if (WARN_ON(ret < 0)) dev_err(&child->dev, "failed to add bus: %d ", ret); } |
4f535093c
|
1073 1074 |
/* Create legacy_io and legacy_mem files for this bus */ pci_create_legacy_files(child); |
1da177e4c
|
1075 1076 |
return child; } |
3c78bc61f
|
1077 1078 |
struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4c
|
1079 1080 1081 1082 |
{ struct pci_bus *child; child = pci_alloc_child_bus(parent, dev, busnr); |
e4ea9bb7e
|
1083 |
if (child) { |
d71374daf
|
1084 |
down_write(&pci_bus_sem); |
1da177e4c
|
1085 |
list_add_tail(&child->node, &parent->children); |
d71374daf
|
1086 |
up_write(&pci_bus_sem); |
e4ea9bb7e
|
1087 |
} |
1da177e4c
|
1088 1089 |
return child; } |
b7fe94342
|
1090 |
EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4c
|
1091 |
|
f3dbd802b
|
1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 |
static void pci_enable_crs(struct pci_dev *pdev) { u16 root_cap = 0; /* Enable CRS Software Visibility if supported */ pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); if (root_cap & PCI_EXP_RTCAP_CRSVIS) pcie_capability_set_word(pdev, PCI_EXP_RTCTL, PCI_EXP_RTCTL_CRSSVE); } |
1c02ea810
|
1102 1103 |
static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, unsigned int available_buses); |
2dbce5901
|
1104 1105 1106 1107 1108 1109 1110 |
/** * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus * numbers from EA capability. * @dev: Bridge * @sec: updated with secondary bus number from EA * @sub: updated with subordinate bus number from EA * |
73884a708
|
1111 1112 1113 |
* If @dev is a bridge with EA capability that specifies valid secondary * and subordinate bus numbers, return true with the bus numbers in @sec * and @sub. Otherwise return false. |
2dbce5901
|
1114 1115 1116 1117 1118 |
*/ static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) { int ea, offset; u32 dw; |
73884a708
|
1119 |
u8 ea_sec, ea_sub; |
2dbce5901
|
1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 |
if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) return false; /* find PCI EA capability in list */ ea = pci_find_capability(dev, PCI_CAP_ID_EA); if (!ea) return false; offset = ea + PCI_EA_FIRST_ENT; pci_read_config_dword(dev, offset, &dw); |
73884a708
|
1131 1132 1133 1134 1135 1136 1137 |
ea_sec = dw & PCI_EA_SEC_BUS_MASK; ea_sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT; if (ea_sec == 0 || ea_sub < ea_sec) return false; *sec = ea_sec; *sub = ea_sub; |
2dbce5901
|
1138 1139 |
return true; } |
1c02ea810
|
1140 |
|
1da177e4c
|
1141 |
/* |
1c02ea810
|
1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 |
* pci_scan_bridge_extend() - Scan buses behind a bridge * @bus: Parent bus the bridge is on * @dev: Bridge itself * @max: Starting subordinate number of buses behind this bridge * @available_buses: Total number of buses available for this bridge and * the devices below. After the minimal bus space has * been allocated the remaining buses will be * distributed equally between hotplug-capable bridges. * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges * that need to be reconfigured. * |
1da177e4c
|
1153 1154 1155 1156 1157 1158 1159 1160 |
* If it's a bridge, configure it and scan the bus behind it. * For CardBus bridges, we don't scan behind as the devices will * be handled by the bridge driver itself. * * We need to process bridges in two passes -- first we scan those * already configured by the BIOS and after we are done with all of * them, we proceed to assigning numbers to the remaining buses in * order to avoid overlaps between old and new bus numbers. |
70f7880d2
|
1161 1162 |
* * Return: New subordinate number covering all buses behind this bridge. |
1da177e4c
|
1163 |
*/ |
1c02ea810
|
1164 1165 1166 |
static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, int max, unsigned int available_buses, int pass) |
1da177e4c
|
1167 1168 1169 |
{ struct pci_bus *child; int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
498879417
|
1170 |
u32 buses, i, j = 0; |
1da177e4c
|
1171 |
u16 bctl; |
99ddd552f
|
1172 |
u8 primary, secondary, subordinate; |
a1c19894b
|
1173 |
int broken = 0; |
2dbce5901
|
1174 1175 1176 |
bool fixed_buses; u8 fixed_sec, fixed_sub; int next_busnr; |
1da177e4c
|
1177 |
|
d963f6512
|
1178 1179 1180 1181 1182 |
/* * Make sure the bridge is powered on to be able to access config * space of devices below it. */ pm_runtime_get_sync(&dev->dev); |
1da177e4c
|
1183 |
pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
99ddd552f
|
1184 1185 1186 |
primary = buses & 0xFF; secondary = (buses >> 8) & 0xFF; subordinate = (buses >> 16) & 0xFF; |
1da177e4c
|
1187 |
|
7506dc798
|
1188 1189 |
pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d ", |
99ddd552f
|
1190 |
secondary, subordinate, pass); |
1da177e4c
|
1191 |
|
71f6bd4a2
|
1192 |
if (!primary && (primary != bus->number) && secondary && subordinate) { |
7506dc798
|
1193 1194 |
pci_warn(dev, "Primary bus is hard wired to 0 "); |
71f6bd4a2
|
1195 1196 |
primary = bus->number; } |
a1c19894b
|
1197 1198 |
/* Check if setup is sensible at all */ if (!pass && |
1965f66e7
|
1199 |
(primary != bus->number || secondary <= bus->number || |
12d870696
|
1200 |
secondary > subordinate)) { |
7506dc798
|
1201 1202 |
pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring ", |
1965f66e7
|
1203 |
secondary, subordinate); |
a1c19894b
|
1204 1205 |
broken = 1; } |
3e466e2d3
|
1206 1207 1208 1209 |
/* * Disable Master-Abort Mode during probing to avoid reporting of * bus errors in some architectures. */ |
1da177e4c
|
1210 1211 1212 |
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); |
f3dbd802b
|
1213 |
pci_enable_crs(dev); |
99ddd552f
|
1214 1215 1216 |
if ((secondary || subordinate) && !pcibios_assign_all_busses() && !is_cardbus && !broken) { unsigned int cmax; |
3e466e2d3
|
1217 |
|
1da177e4c
|
1218 |
/* |
3e466e2d3
|
1219 1220 |
* Bus already configured by firmware, process it in the * first pass and just note the configuration. |
1da177e4c
|
1221 1222 |
*/ if (pass) |
bbe8f9a3e
|
1223 |
goto out; |
1da177e4c
|
1224 1225 |
/* |
3e466e2d3
|
1226 1227 1228 1229 |
* The bus might already exist for two reasons: Either we * are rescanning the bus or the bus is reachable through * more than one bridge. The second case can happen with * the i450NX chipset. |
1da177e4c
|
1230 |
*/ |
99ddd552f
|
1231 |
child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded8
|
1232 |
if (!child) { |
99ddd552f
|
1233 |
child = pci_add_new_bus(bus, dev, secondary); |
74710ded8
|
1234 1235 |
if (!child) goto out; |
99ddd552f
|
1236 |
child->primary = primary; |
bc76b7310
|
1237 |
pci_bus_insert_busn_res(child, secondary, subordinate); |
74710ded8
|
1238 |
child->bridge_ctl = bctl; |
1da177e4c
|
1239 |
} |
1da177e4c
|
1240 |
cmax = pci_scan_child_bus(child); |
c95b0bd6c
|
1241 |
if (cmax > subordinate) |
7506dc798
|
1242 1243 |
pci_warn(dev, "bridge has subordinate %02x but max busn %02x ", |
c95b0bd6c
|
1244 |
subordinate, cmax); |
3e466e2d3
|
1245 1246 |
/* Subordinate should equal child->busn_res.end */ |
c95b0bd6c
|
1247 1248 |
if (subordinate > max) max = subordinate; |
1da177e4c
|
1249 |
} else { |
3e466e2d3
|
1250 |
|
1da177e4c
|
1251 1252 1253 1254 |
/* * We need to assign a number to this bus which we always * do in the second pass. */ |
12f44f46b
|
1255 |
if (!pass) { |
619c8c310
|
1256 |
if (pcibios_assign_all_busses() || broken || is_cardbus) |
3e466e2d3
|
1257 1258 1259 1260 1261 1262 1263 1264 1265 |
/* * Temporarily disable forwarding of the * configuration cycles on all bridges in * this bus segment to avoid possible * conflicts in the second pass between two * bridges programmed with overlapping bus * ranges. */ |
12f44f46b
|
1266 1267 |
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses & ~0xffffff); |
bbe8f9a3e
|
1268 |
goto out; |
12f44f46b
|
1269 |
} |
1da177e4c
|
1270 1271 1272 |
/* Clear errors */ pci_write_config_word(dev, PCI_STATUS, 0xffff); |
2dbce5901
|
1273 1274 1275 1276 1277 1278 |
/* Read bus numbers from EA Capability (if present) */ fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); if (fixed_buses) next_busnr = fixed_sec; else next_busnr = max + 1; |
3e466e2d3
|
1279 1280 1281 1282 1283 |
/* * Prevent assigning a bus number that already exists. * This can happen when a bridge is hot-plugged, so in this * case we only re-scan this bus. */ |
2dbce5901
|
1284 |
child = pci_find_bus(pci_domain_nr(bus), next_busnr); |
b1a98b695
|
1285 |
if (!child) { |
2dbce5901
|
1286 |
child = pci_add_new_bus(bus, dev, next_busnr); |
b1a98b695
|
1287 1288 |
if (!child) goto out; |
2dbce5901
|
1289 |
pci_bus_insert_busn_res(child, next_busnr, |
a20c7f36b
|
1290 |
bus->busn_res.end); |
b1a98b695
|
1291 |
} |
9a4d7d871
|
1292 |
max++; |
1c02ea810
|
1293 1294 |
if (available_buses) available_buses--; |
1da177e4c
|
1295 1296 |
buses = (buses & 0xff000000) | ((unsigned int)(child->primary) << 0) |
b918c62e0
|
1297 1298 |
| ((unsigned int)(child->busn_res.start) << 8) | ((unsigned int)(child->busn_res.end) << 16); |
1da177e4c
|
1299 1300 1301 1302 1303 1304 1305 1306 1307 |
/* * yenta.c forces a secondary latency timer of 176. * Copy that behaviour here. */ if (is_cardbus) { buses &= ~0xff000000; buses |= CARDBUS_LATENCY_TIMER << 24; } |
7c867c889
|
1308 |
|
3e466e2d3
|
1309 |
/* We need to blast all three values with a single write */ |
1da177e4c
|
1310 1311 1312 |
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); if (!is_cardbus) { |
11949255d
|
1313 |
child->bridge_ctl = bctl; |
1c02ea810
|
1314 |
max = pci_scan_child_bus_extend(child, available_buses); |
1da177e4c
|
1315 |
} else { |
3e466e2d3
|
1316 |
|
1da177e4c
|
1317 |
/* |
3e466e2d3
|
1318 1319 1320 |
* For CardBus bridges, we leave 4 bus numbers as * cards with a PCI-to-PCI bridge can be inserted * later. |
1da177e4c
|
1321 |
*/ |
3c78bc61f
|
1322 |
for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
498879417
|
1323 |
struct pci_bus *parent = bus; |
cc57450f5
|
1324 1325 1326 |
if (pci_find_bus(pci_domain_nr(bus), max+i+1)) break; |
498879417
|
1327 1328 |
while (parent->parent) { if ((!pcibios_assign_all_busses()) && |
b918c62e0
|
1329 1330 |
(parent->busn_res.end > max) && (parent->busn_res.end <= max+i)) { |
498879417
|
1331 1332 1333 1334 1335 |
j = 1; } parent = parent->parent; } if (j) { |
3e466e2d3
|
1336 |
|
498879417
|
1337 |
/* |
3e466e2d3
|
1338 1339 1340 |
* Often, there are two CardBus * bridges -- try to leave one * valid bus number for each one. |
498879417
|
1341 1342 1343 1344 1345 |
*/ i /= 2; break; } } |
cc57450f5
|
1346 |
max += i; |
1da177e4c
|
1347 |
} |
3e466e2d3
|
1348 |
|
2dbce5901
|
1349 1350 1351 1352 1353 1354 1355 |
/* * Set subordinate bus number to its real value. * If fixed subordinate bus number exists from EA * capability then use it. */ if (fixed_buses) max = fixed_sub; |
bc76b7310
|
1356 |
pci_bus_update_busn_res_end(child, max); |
1da177e4c
|
1357 1358 |
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); } |
cb3576fa3
|
1359 1360 1361 |
sprintf(child->name, (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), pci_domain_nr(bus), child->number); |
1da177e4c
|
1362 |
|
e412d63d6
|
1363 |
/* Check that all devices are accessible */ |
498879417
|
1364 |
while (bus->parent) { |
b918c62e0
|
1365 1366 |
if ((child->busn_res.end > bus->busn_res.end) || (child->number > bus->busn_res.end) || |
498879417
|
1367 |
(child->number < bus->number) || |
b918c62e0
|
1368 |
(child->busn_res.end < bus->number)) { |
e412d63d6
|
1369 1370 1371 1372 |
dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them ", &child->busn_res); break; |
498879417
|
1373 1374 1375 |
} bus = bus->parent; } |
bbe8f9a3e
|
1376 1377 |
out: pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); |
d963f6512
|
1378 |
pm_runtime_put(&dev->dev); |
1da177e4c
|
1379 1380 |
return max; } |
1c02ea810
|
1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 |
/* * pci_scan_bridge() - Scan buses behind a bridge * @bus: Parent bus the bridge is on * @dev: Bridge itself * @max: Starting subordinate number of buses behind this bridge * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges * that need to be reconfigured. * * If it's a bridge, configure it and scan the bus behind it. * For CardBus bridges, we don't scan behind as the devices will * be handled by the bridge driver itself. * * We need to process bridges in two passes -- first we scan those * already configured by the BIOS and after we are done with all of * them, we proceed to assigning numbers to the remaining buses in * order to avoid overlaps between old and new bus numbers. |
70f7880d2
|
1398 1399 |
* * Return: New subordinate number covering all buses behind this bridge. |
1c02ea810
|
1400 1401 1402 1403 1404 |
*/ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) { return pci_scan_bridge_extend(bus, dev, max, 0, pass); } |
b7fe94342
|
1405 |
EXPORT_SYMBOL(pci_scan_bridge); |
1da177e4c
|
1406 1407 1408 1409 1410 1411 1412 1413 |
/* * Read interrupt line and base address registers. * The architecture-dependent code can tweak these, of course. */ static void pci_read_irq(struct pci_dev *dev) { unsigned char irq; |
be20f6b06
|
1414 1415 1416 1417 1418 1419 |
/* VFs are not allowed to use INTx, so skip the config reads */ if (dev->is_virtfn) { dev->pin = 0; dev->irq = 0; return; } |
1da177e4c
|
1420 |
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
ffeff788d
|
1421 |
dev->pin = irq; |
1da177e4c
|
1422 1423 1424 1425 |
if (irq) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); dev->irq = irq; } |
bb209c828
|
1426 |
void set_pcie_port_type(struct pci_dev *pdev) |
480b93b78
|
1427 1428 1429 |
{ int pos; u16 reg16; |
d0751b98d
|
1430 1431 |
int type; struct pci_dev *parent; |
480b93b78
|
1432 1433 1434 1435 |
pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); if (!pos) return; |
51ebfc92b
|
1436 |
|
0efea0006
|
1437 |
pdev->pcie_cap = pos; |
480b93b78
|
1438 |
pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
786e22885
|
1439 |
pdev->pcie_flags_reg = reg16; |
b03e7495a
|
1440 1441 |
pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; |
d0751b98d
|
1442 |
|
ca7841040
|
1443 1444 1445 |
parent = pci_upstream_bridge(pdev); if (!parent) return; |
d0751b98d
|
1446 |
/* |
ca7841040
|
1447 1448 1449 |
* Some systems do not identify their upstream/downstream ports * correctly so detect impossible configurations here and correct * the port type accordingly. |
d0751b98d
|
1450 1451 |
*/ type = pci_pcie_type(pdev); |
ca7841040
|
1452 |
if (type == PCI_EXP_TYPE_DOWNSTREAM) { |
b35b1df5e
|
1453 |
/* |
ca7841040
|
1454 1455 1456 |
* If pdev claims to be downstream port but the parent * device is also downstream port assume pdev is actually * upstream port. |
b35b1df5e
|
1457 |
*/ |
ca7841040
|
1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 |
if (pcie_downstream_port(parent)) { pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type "); pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; } } else if (type == PCI_EXP_TYPE_UPSTREAM) { /* * If pdev claims to be upstream port but the parent * device is also upstream port assume pdev is actually * downstream port. */ if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type "); pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; } |
d0751b98d
|
1476 |
} |
480b93b78
|
1477 |
} |
bb209c828
|
1478 |
void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489a
|
1479 |
{ |
28760489a
|
1480 |
u32 reg32; |
59875ae48
|
1481 |
pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
28760489a
|
1482 1483 1484 |
if (reg32 & PCI_EXP_SLTCAP_HPC) pdev->is_hotplug_bridge = 1; } |
8531e283b
|
1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 |
static void set_pcie_thunderbolt(struct pci_dev *dev) { int vsec = 0; u32 header; while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) { pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header); /* Is the device part of a Thunderbolt controller? */ if (dev->vendor == PCI_VENDOR_ID_INTEL && PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) { dev->is_thunderbolt = 1; return; } } } |
617654aae
|
1502 1503 1504 1505 1506 1507 1508 1509 1510 |
static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent; /* * If the upstream bridge is untrusted we treat this device * untrusted as well. */ parent = pci_upstream_bridge(dev); |
99b50be9d
|
1511 |
if (parent && (parent->untrusted || parent->external_facing)) |
617654aae
|
1512 1513 |
dev->untrusted = true; } |
0b950f0f3
|
1514 |
/** |
3e466e2d3
|
1515 |
* pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? |
78916b00f
|
1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 |
* @dev: PCI device * * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that * when forwarding a type1 configuration request the bridge must check that * the extended register address field is zero. The bridge is not permitted * to forward the transactions and must handle it as an Unsupported Request. * Some bridges do not follow this rule and simply drop the extended register * bits, resulting in the standard config space being aliased, every 256 * bytes across the entire configuration space. Test for this condition by * comparing the first dword of each potential alias to the vendor/device ID. * Known offenders: * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) */ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) { #ifdef CONFIG_PCI_QUIRKS int pos; u32 header, tmp; pci_read_config_dword(dev, PCI_VENDOR_ID, &header); for (pos = PCI_CFG_SPACE_SIZE; pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL || header != tmp) return false; } return true; #else return false; #endif } /** |
3e466e2d3
|
1552 |
* pci_cfg_space_size - Get the configuration space size of the PCI device |
0b950f0f3
|
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 |
* @dev: PCI device * * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices * have 4096 bytes. Even if the device is capable, that doesn't mean we can * access it. Maybe we don't have a way to generate extended config space * accesses, or the device is behind a reverse Express bridge. So we try * reading the dword at 0x100 which must either be 0 or a valid extended * capability header. */ static int pci_cfg_space_size_ext(struct pci_dev *dev) { u32 status; int pos = PCI_CFG_SPACE_SIZE; if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
8e5a395a0
|
1568 |
return PCI_CFG_SPACE_SIZE; |
78916b00f
|
1569 |
if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) |
8e5a395a0
|
1570 |
return PCI_CFG_SPACE_SIZE; |
0b950f0f3
|
1571 1572 |
return PCI_CFG_SPACE_EXP_SIZE; |
0b950f0f3
|
1573 1574 1575 1576 1577 1578 1579 |
} int pci_cfg_space_size(struct pci_dev *dev) { int pos; u32 status; u16 class; |
975bb8b4d
|
1580 |
#ifdef CONFIG_PCI_IOV |
06013b647
|
1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 |
/* * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to * implement a PCIe capability and therefore must implement extended * config space. We can skip the NO_EXTCFG test below and the * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of * the fact that the SR-IOV capability on the PF resides in extended * config space and must be accessible and non-aliased to have enabled * support for this VF. This is a micro performance optimization for * systems supporting many VFs. */ if (dev->is_virtfn) return PCI_CFG_SPACE_EXP_SIZE; |
975bb8b4d
|
1593 |
#endif |
17e8f0d4c
|
1594 1595 |
if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) return PCI_CFG_SPACE_SIZE; |
0b950f0f3
|
1596 1597 1598 |
class = dev->class >> 8; if (class == PCI_CLASS_BRIDGE_HOST) return pci_cfg_space_size_ext(dev); |
8e5a395a0
|
1599 1600 |
if (pci_is_pcie(dev)) return pci_cfg_space_size_ext(dev); |
0b950f0f3
|
1601 |
|
8e5a395a0
|
1602 1603 1604 |
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); if (!pos) return PCI_CFG_SPACE_SIZE; |
0b950f0f3
|
1605 |
|
8e5a395a0
|
1606 1607 1608 |
pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) return pci_cfg_space_size_ext(dev); |
0b950f0f3
|
1609 |
|
0b950f0f3
|
1610 1611 |
return PCI_CFG_SPACE_SIZE; } |
cf0921bea
|
1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 |
static u32 pci_class(struct pci_dev *dev) { u32 class; #ifdef CONFIG_PCI_IOV if (dev->is_virtfn) return dev->physfn->sriov->class; #endif pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); return class; } static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) { #ifdef CONFIG_PCI_IOV if (dev->is_virtfn) { *vendor = dev->physfn->sriov->subsystem_vendor; *device = dev->physfn->sriov->subsystem_device; return; } #endif pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); } static u8 pci_hdr_type(struct pci_dev *dev) { u8 hdr_type; #ifdef CONFIG_PCI_IOV if (dev->is_virtfn) return dev->physfn->sriov->hdr_type; #endif pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); return hdr_type; } |
01abc2aa0
|
1648 |
#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d66
|
1649 |
|
e80e7edc5
|
1650 |
static void pci_msi_setup_pci_dev(struct pci_dev *dev) |
1851617cd
|
1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 |
{ /* * Disable the MSI hardware to avoid screaming interrupts * during boot. This is the power on reset default so * usually this should be a noop. */ dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI); if (dev->msi_cap) pci_msi_set_enable(dev, 0); dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX); if (dev->msix_cap) pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0); } |
1da177e4c
|
1665 |
/** |
3e466e2d3
|
1666 |
* pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability |
99b3c58f7
|
1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 |
* @dev: PCI device * * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this * at enumeration-time to avoid modifying PCI_COMMAND at run-time. */ static int pci_intx_mask_broken(struct pci_dev *dev) { u16 orig, toggle, new; pci_read_config_word(dev, PCI_COMMAND, &orig); toggle = orig ^ PCI_COMMAND_INTX_DISABLE; pci_write_config_word(dev, PCI_COMMAND, toggle); pci_read_config_word(dev, PCI_COMMAND, &new); pci_write_config_word(dev, PCI_COMMAND, orig); /* * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI * r2.3, so strictly speaking, a device is not *broken* if it's not * writable. But we'll live with the misnomer for now. */ if (new != toggle) return 1; return 0; } |
11eb0e0e8
|
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 |
static void early_dump_pci_device(struct pci_dev *pdev) { u32 value[256 / 4]; int i; pci_info(pdev, "config space: "); for (i = 0; i < 256; i += 4) pci_read_config_dword(pdev, i, &value[i / 4]); print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, value, 256, false); } |
99b3c58f7
|
1706 |
/** |
3e466e2d3
|
1707 |
* pci_setup_device - Fill in class and map information of a device |
1da177e4c
|
1708 1709 |
* @dev: the device structure to fill * |
f7625980f
|
1710 |
* Initialize the device structure with information about the device's |
3e466e2d3
|
1711 |
* vendor,class,memory and IO-space addresses, IRQ lines etc. |
1da177e4c
|
1712 |
* Called at initialisation of the PCI subsystem and by CardBus services. |
480b93b78
|
1713 1714 |
* Returns 0 on success and negative if unknown type of device (not normal, * bridge or CardBus). |
1da177e4c
|
1715 |
*/ |
480b93b78
|
1716 |
int pci_setup_device(struct pci_dev *dev) |
1da177e4c
|
1717 1718 |
{ u32 class; |
b84106b4e
|
1719 |
u16 cmd; |
480b93b78
|
1720 |
u8 hdr_type; |
bc577d2bb
|
1721 |
int pos = 0; |
5bfa14ed9
|
1722 1723 |
struct pci_bus_region region; struct resource *res; |
480b93b78
|
1724 |
|
cf0921bea
|
1725 |
hdr_type = pci_hdr_type(dev); |
480b93b78
|
1726 1727 1728 1729 1730 1731 |
dev->sysdata = dev->bus->sysdata; dev->dev.parent = dev->bus->bridge; dev->dev.bus = &pci_bus_type; dev->hdr_type = hdr_type & 0x7f; dev->multifunction = !!(hdr_type & 0x80); |
480b93b78
|
1732 1733 |
dev->error_state = pci_channel_io_normal; set_pcie_port_type(dev); |
017ffe64e
|
1734 |
pci_dev_assign_slot(dev); |
3e466e2d3
|
1735 1736 1737 1738 1739 |
/* * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) * set this higher, assuming the system even supports it. */ |
480b93b78
|
1740 |
dev->dma_mask = 0xffffffff; |
1da177e4c
|
1741 |
|
eebfcfb52
|
1742 1743 1744 |
dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); |
1da177e4c
|
1745 |
|
cf0921bea
|
1746 |
class = pci_class(dev); |
b8a3a5214
|
1747 |
dev->revision = class & 0xff; |
2dd8ba921
|
1748 |
dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4c
|
1749 |
|
11eb0e0e8
|
1750 1751 |
if (pci_early_dump) early_dump_pci_device(dev); |
3e466e2d3
|
1752 |
/* Need to have dev->class ready */ |
853346e43
|
1753 |
dev->cfg_size = pci_cfg_space_size(dev); |
3e466e2d3
|
1754 |
/* Need to have dev->cfg_size ready */ |
8531e283b
|
1755 |
set_pcie_thunderbolt(dev); |
617654aae
|
1756 |
set_pcie_untrusted(dev); |
1da177e4c
|
1757 |
/* "Unknown power state" */ |
3fe9d19f9
|
1758 |
dev->current_state = PCI_UNKNOWN; |
1da177e4c
|
1759 1760 1761 |
/* Early fixups, before probing the BARs */ pci_fixup_device(pci_fixup_early, dev); |
3e466e2d3
|
1762 |
|
b7360f609
|
1763 1764 1765 |
pci_info(dev, "[%04x:%04x] type %02x class %#08x ", dev->vendor, dev->device, dev->hdr_type, dev->class); |
3e466e2d3
|
1766 |
/* Device class may be changed after fixup */ |
f79b1b146
|
1767 |
class = dev->class >> 8; |
1da177e4c
|
1768 |
|
b6caa1d8c
|
1769 |
if (dev->non_compliant_bars && !dev->mmio_always_on) { |
b84106b4e
|
1770 1771 |
pci_read_config_word(dev, PCI_COMMAND, &cmd); if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { |
7506dc798
|
1772 1773 |
pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding "); |
b84106b4e
|
1774 1775 1776 1777 1778 |
cmd &= ~PCI_COMMAND_IO; cmd &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, cmd); } } |
99b3c58f7
|
1779 |
dev->broken_intx_masking = pci_intx_mask_broken(dev); |
1da177e4c
|
1780 1781 1782 1783 1784 1785 |
switch (dev->hdr_type) { /* header type */ case PCI_HEADER_TYPE_NORMAL: /* standard header */ if (class == PCI_CLASS_BRIDGE_PCI) goto bad; pci_read_irq(dev); pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
cf0921bea
|
1786 1787 |
pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); |
368c73d4f
|
1788 1789 |
/* |
075eb9e35
|
1790 1791 1792 1793 |
* Do the ugly legacy mode stuff here rather than broken chip * quirk code. Legacy mode ATA controllers have fixed * addresses. These are not always echoed in BAR0-3, and * BAR0-3 in a few cases contain junk! |
368c73d4f
|
1794 1795 1796 1797 1798 |
*/ if (class == PCI_CLASS_STORAGE_IDE) { u8 progif; pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); if ((progif & 1) == 0) { |
5bfa14ed9
|
1799 1800 1801 1802 |
region.start = 0x1F0; region.end = 0x1F7; res = &dev->resource[0]; res->flags = LEGACY_IO_RESOURCE; |
fc2798502
|
1803 |
pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc798
|
1804 1805 |
pci_info(dev, "legacy IDE quirk: reg 0x10: %pR ", |
075eb9e35
|
1806 |
res); |
5bfa14ed9
|
1807 1808 1809 1810 |
region.start = 0x3F6; region.end = 0x3F6; res = &dev->resource[1]; res->flags = LEGACY_IO_RESOURCE; |
fc2798502
|
1811 |
pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc798
|
1812 1813 |
pci_info(dev, "legacy IDE quirk: reg 0x14: %pR ", |
075eb9e35
|
1814 |
res); |
368c73d4f
|
1815 1816 |
} if ((progif & 4) == 0) { |
5bfa14ed9
|
1817 1818 1819 1820 |
region.start = 0x170; region.end = 0x177; res = &dev->resource[2]; res->flags = LEGACY_IO_RESOURCE; |
fc2798502
|
1821 |
pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc798
|
1822 1823 |
pci_info(dev, "legacy IDE quirk: reg 0x18: %pR ", |
075eb9e35
|
1824 |
res); |
5bfa14ed9
|
1825 1826 1827 1828 |
region.start = 0x376; region.end = 0x376; res = &dev->resource[3]; res->flags = LEGACY_IO_RESOURCE; |
fc2798502
|
1829 |
pcibios_bus_to_resource(dev->bus, res, ®ion); |
7506dc798
|
1830 1831 |
pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR ", |
075eb9e35
|
1832 |
res); |
368c73d4f
|
1833 1834 |
} } |
1da177e4c
|
1835 1836 1837 |
break; case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
3e466e2d3
|
1838 1839 1840 1841 1842 |
/* * The PCI-to-PCI bridge spec requires that subtractive * decoding (i.e. transparent) bridge must have programming * interface code of 0x01. */ |
3efd273b4
|
1843 |
pci_read_irq(dev); |
1da177e4c
|
1844 1845 |
dev->transparent = ((dev->class & 0xff) == 1); pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
51c48b310
|
1846 |
pci_read_bridge_windows(dev); |
28760489a
|
1847 |
set_pcie_hotplug_bridge(dev); |
bc577d2bb
|
1848 1849 1850 1851 1852 |
pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); if (pos) { pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); } |
1da177e4c
|
1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 |
break; case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ if (class != PCI_CLASS_BRIDGE_CARDBUS) goto bad; pci_read_irq(dev); pci_read_bases(dev, 1, 0); pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); break; default: /* unknown header */ |
7506dc798
|
1865 1866 |
pci_err(dev, "unknown header type %02x, ignoring device ", |
227f06470
|
1867 |
dev->hdr_type); |
480b93b78
|
1868 |
return -EIO; |
1da177e4c
|
1869 1870 |
bad: |
7506dc798
|
1871 1872 |
pci_err(dev, "ignoring class %#08x (doesn't match header type %02x) ", |
227f06470
|
1873 |
dev->class, dev->hdr_type); |
2b4aed1d1
|
1874 |
dev->class = PCI_CLASS_NOT_DEFINED << 8; |
1da177e4c
|
1875 1876 1877 1878 1879 |
} /* We found a fine healthy device, go go go... */ return 0; } |
9dae3a972
|
1880 1881 1882 |
static void pci_configure_mps(struct pci_dev *dev) { struct pci_dev *bridge = pci_upstream_bridge(dev); |
9f0e89359
|
1883 |
int mps, mpss, p_mps, rc; |
9dae3a972
|
1884 |
|
aa0ce96d7
|
1885 |
if (!pci_is_pcie(dev)) |
9dae3a972
|
1886 |
return; |
3dbe97efe
|
1887 1888 1889 |
/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ if (dev->is_virtfn) return; |
aa0ce96d7
|
1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 |
/* * For Root Complex Integrated Endpoints, program the maximum * supported value unless limited by the PCIE_BUS_PEER2PEER case. */ if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { if (pcie_bus_config == PCIE_BUS_PEER2PEER) mps = 128; else mps = 128 << dev->pcie_mpss; rc = pcie_set_mps(dev, mps); if (rc) { pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug ", mps); } return; } if (!bridge || !pci_is_pcie(bridge)) return; |
9dae3a972
|
1910 1911 1912 1913 1914 1915 1916 |
mps = pcie_get_mps(dev); p_mps = pcie_get_mps(bridge); if (mps == p_mps) return; if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { |
7506dc798
|
1917 1918 |
pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug ", |
9dae3a972
|
1919 1920 1921 |
mps, pci_name(bridge), p_mps); return; } |
27d868b5e
|
1922 1923 1924 1925 1926 1927 1928 |
/* * Fancier MPS configuration is done later by * pcie_bus_configure_settings() */ if (pcie_bus_config != PCIE_BUS_DEFAULT) return; |
9f0e89359
|
1929 1930 1931 1932 1933 1934 1935 1936 |
mpss = 128 << dev->pcie_mpss; if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { pcie_set_mps(bridge, mpss); pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d) ", mpss, p_mps, 128 << bridge->pcie_mpss); p_mps = pcie_get_mps(bridge); } |
27d868b5e
|
1937 1938 |
rc = pcie_set_mps(dev, p_mps); if (rc) { |
7506dc798
|
1939 1940 |
pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug ", |
27d868b5e
|
1941 1942 1943 |
p_mps); return; } |
7506dc798
|
1944 1945 |
pci_info(dev, "Max Payload Size set to %d (was %d, max %d) ", |
9f0e89359
|
1946 |
p_mps, mps, mpss); |
9dae3a972
|
1947 |
} |
62ce94a7a
|
1948 |
int pci_configure_extended_tags(struct pci_dev *dev, void *ign) |
60db3a4d8
|
1949 |
{ |
62ce94a7a
|
1950 1951 1952 |
struct pci_host_bridge *host; u32 cap; u16 ctl; |
60db3a4d8
|
1953 1954 1955 |
int ret; if (!pci_is_pcie(dev)) |
62ce94a7a
|
1956 |
return 0; |
60db3a4d8
|
1957 |
|
62ce94a7a
|
1958 |
ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); |
60db3a4d8
|
1959 |
if (ret) |
62ce94a7a
|
1960 1961 1962 1963 |
return 0; if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) return 0; |
60db3a4d8
|
1964 |
|
62ce94a7a
|
1965 1966 1967 1968 1969 1970 1971 |
ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); if (ret) return 0; host = pci_find_host_bridge(dev->bus); if (!host) return 0; |
60db3a4d8
|
1972 |
|
62ce94a7a
|
1973 1974 1975 1976 1977 1978 |
/* * If some device in the hierarchy doesn't handle Extended Tags * correctly, make sure they're disabled. */ if (host->no_ext_tags) { if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { |
7506dc798
|
1979 1980 |
pci_info(dev, "disabling Extended Tags "); |
62ce94a7a
|
1981 1982 1983 1984 1985 1986 1987 |
pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG); } return 0; } if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { |
7506dc798
|
1988 1989 |
pci_info(dev, "enabling Extended Tags "); |
60db3a4d8
|
1990 1991 |
pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG); |
62ce94a7a
|
1992 1993 |
} return 0; |
60db3a4d8
|
1994 |
} |
a99b646af
|
1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 |
/** * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable * @dev: PCI device to query * * Returns true if the device has enabled relaxed ordering attribute. */ bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) { u16 v; pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); return !!(v & PCI_EXP_DEVCTL_RELAX_EN); } EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); static void pci_configure_relaxed_ordering(struct pci_dev *dev) { struct pci_dev *root; /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */ if (dev->is_virtfn) return; if (!pcie_relaxed_ordering_enabled(dev)) return; /* * For now, we only deal with Relaxed Ordering issues with Root * Ports. Peer-to-Peer DMA is another can of worms. */ |
6ae72bfa6
|
2026 |
root = pcie_find_root_port(dev); |
a99b646af
|
2027 2028 2029 2030 2031 2032 |
if (!root) return; if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); |
7506dc798
|
2033 2034 |
pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it "); |
a99b646af
|
2035 2036 |
} } |
c46fd3580
|
2037 2038 2039 |
static void pci_configure_ltr(struct pci_dev *dev) { #ifdef CONFIG_PCIEASPM |
af8bb9f89
|
2040 |
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); |
c46fd3580
|
2041 |
struct pci_dev *bridge; |
10ecc818e
|
2042 |
u32 cap, ctl; |
af8bb9f89
|
2043 |
|
c46fd3580
|
2044 2045 |
if (!pci_is_pcie(dev)) return; |
ecdf57b4f
|
2046 2047 |
/* Read L1 PM substate capabilities */ dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS); |
c46fd3580
|
2048 2049 2050 |
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_LTR)) return; |
10ecc818e
|
2051 2052 2053 2054 2055 2056 |
pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl); if (ctl & PCI_EXP_DEVCTL2_LTR_EN) { if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) { dev->ltr_path = 1; return; } |
c46fd3580
|
2057 2058 2059 |
bridge = pci_upstream_bridge(dev); if (bridge && bridge->ltr_path) dev->ltr_path = 1; |
10ecc818e
|
2060 2061 |
return; |
c46fd3580
|
2062 |
} |
10ecc818e
|
2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 |
if (!host->native_ltr) return; /* * Software must not enable LTR in an Endpoint unless the Root * Complex and all intermediate Switches indicate support for LTR. * PCIe r4.0, sec 6.18. */ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || ((bridge = pci_upstream_bridge(dev)) && bridge->ltr_path)) { |
c46fd3580
|
2074 2075 |
pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); |
10ecc818e
|
2076 2077 |
dev->ltr_path = 1; } |
c46fd3580
|
2078 2079 |
#endif } |
7ce3f912a
|
2080 2081 2082 2083 |
static void pci_configure_eetlp_prefix(struct pci_dev *dev) { #ifdef CONFIG_PCI_PASID struct pci_dev *bridge; |
9d27e39d3
|
2084 |
int pcie_type; |
7ce3f912a
|
2085 2086 2087 2088 2089 2090 2091 2092 |
u32 cap; if (!pci_is_pcie(dev)) return; pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) return; |
9d27e39d3
|
2093 2094 2095 |
pcie_type = pci_pcie_type(dev); if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || pcie_type == PCI_EXP_TYPE_RC_END) |
7ce3f912a
|
2096 2097 2098 2099 2100 2101 2102 2103 |
dev->eetlp_prefix_path = 1; else { bridge = pci_upstream_bridge(dev); if (bridge && bridge->eetlp_prefix_path) dev->eetlp_prefix_path = 1; } #endif } |
b4f6dcb9d
|
2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 |
static void pci_configure_serr(struct pci_dev *dev) { u16 control; if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { /* * A bridge will not forward ERR_ messages coming from an * endpoint unless SERR# forwarding is enabled. */ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); if (!(control & PCI_BRIDGE_CTL_SERR)) { control |= PCI_BRIDGE_CTL_SERR; pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); } } } |
6cd33649f
|
2121 2122 |
static void pci_configure_device(struct pci_dev *dev) { |
9dae3a972
|
2123 |
pci_configure_mps(dev); |
62ce94a7a
|
2124 |
pci_configure_extended_tags(dev, NULL); |
a99b646af
|
2125 |
pci_configure_relaxed_ordering(dev); |
c46fd3580
|
2126 |
pci_configure_ltr(dev); |
7ce3f912a
|
2127 |
pci_configure_eetlp_prefix(dev); |
b4f6dcb9d
|
2128 |
pci_configure_serr(dev); |
9dae3a972
|
2129 |
|
4a2dbeddd
|
2130 |
pci_acpi_program_hp_params(dev); |
6cd33649f
|
2131 |
} |
201de56eb
|
2132 2133 |
static void pci_release_capabilities(struct pci_dev *dev) { |
db89ccbe5
|
2134 |
pci_aer_exit(dev); |
201de56eb
|
2135 |
pci_vpd_release(dev); |
d1b054da8
|
2136 |
pci_iov_release(dev); |
f796841e4
|
2137 |
pci_free_cap_save_buffers(dev); |
201de56eb
|
2138 |
} |
1da177e4c
|
2139 |
/** |
3e466e2d3
|
2140 2141 |
* pci_release_dev - Free a PCI device structure when all users of it are * finished |
1da177e4c
|
2142 2143 |
* @dev: device that's been disconnected * |
3e466e2d3
|
2144 |
* Will be called only by the device core when all users of this PCI device are |
1da177e4c
|
2145 2146 2147 2148 |
* done. */ static void pci_release_dev(struct device *dev) { |
04480094d
|
2149 |
struct pci_dev *pci_dev; |
1da177e4c
|
2150 |
|
04480094d
|
2151 |
pci_dev = to_pci_dev(dev); |
201de56eb
|
2152 |
pci_release_capabilities(pci_dev); |
98d9f30c8
|
2153 |
pci_release_of_node(pci_dev); |
6ae32c539
|
2154 |
pcibios_release_device(pci_dev); |
8b1fce04d
|
2155 |
pci_bus_put(pci_dev->bus); |
782a985d7
|
2156 |
kfree(pci_dev->driver_override); |
c66357927
|
2157 |
bitmap_free(pci_dev->dma_alias_mask); |
1da177e4c
|
2158 2159 |
kfree(pci_dev); } |
3c6e6ae77
|
2160 |
struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
65891215e
|
2161 2162 2163 2164 2165 2166 |
{ struct pci_dev *dev; dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); if (!dev) return NULL; |
65891215e
|
2167 |
INIT_LIST_HEAD(&dev->bus_list); |
88e7b167a
|
2168 |
dev->dev.type = &pci_dev_type; |
3c6e6ae77
|
2169 |
dev->bus = pci_bus_get(bus); |
65891215e
|
2170 2171 2172 |
return dev; } |
3c6e6ae77
|
2173 |
EXPORT_SYMBOL(pci_alloc_dev); |
62bc6a6f7
|
2174 2175 2176 2177 |
static bool pci_bus_crs_vendor_id(u32 l) { return (l & 0xffff) == 0x0001; } |
6a802ef0a
|
2178 2179 |
static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l, int timeout) |
1da177e4c
|
2180 |
{ |
1da177e4c
|
2181 |
int delay = 1; |
6a802ef0a
|
2182 2183 |
if (!pci_bus_crs_vendor_id(*l)) return true; /* not a CRS completion */ |
1da177e4c
|
2184 |
|
6a802ef0a
|
2185 2186 |
if (!timeout) return false; /* CRS, but caller doesn't want to wait */ |
1da177e4c
|
2187 |
|
89665a6a7
|
2188 |
/* |
6a802ef0a
|
2189 2190 2191 |
* We got the reserved Vendor ID that indicates a completion with * Configuration Request Retry Status (CRS). Retry until we get a * valid Vendor ID or we time out. |
89665a6a7
|
2192 |
*/ |
62bc6a6f7
|
2193 |
while (pci_bus_crs_vendor_id(*l)) { |
6a802ef0a
|
2194 |
if (delay > timeout) { |
e78e661fa
|
2195 2196 2197 2198 |
pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up ", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); |
efdc87dab
|
2199 |
return false; |
1da177e4c
|
2200 |
} |
e78e661fa
|
2201 2202 2203 2204 2205 |
if (delay >= 1000) pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting ", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); |
efdc87dab
|
2206 |
|
1da177e4c
|
2207 2208 |
msleep(delay); delay *= 2; |
9f9827567
|
2209 |
|
efdc87dab
|
2210 2211 |
if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) return false; |
1da177e4c
|
2212 |
} |
e78e661fa
|
2213 2214 2215 2216 2217 |
if (delay >= 1000) pr_info("pci %04x:%02x:%02x.%d: ready after %dms ", pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); |
efdc87dab
|
2218 2219 |
return true; } |
6a802ef0a
|
2220 |
|
aa667c640
|
2221 2222 |
bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, int timeout) |
6a802ef0a
|
2223 2224 2225 |
{ if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) return false; |
3e466e2d3
|
2226 |
/* Some broken boards return 0 or ~0 if a slot is empty: */ |
6a802ef0a
|
2227 2228 2229 2230 2231 2232 |
if (*l == 0xffffffff || *l == 0x00000000 || *l == 0x0000ffff || *l == 0xffff0000) return false; if (pci_bus_crs_vendor_id(*l)) return pci_bus_wait_crs(bus, devfn, l, timeout); |
efdc87dab
|
2233 2234 |
return true; } |
aa667c640
|
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 |
bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, int timeout) { #ifdef CONFIG_PCI_QUIRKS struct pci_dev *bridge = bus->self; /* * Certain IDT switches have an issue where they improperly trigger * ACS Source Validation errors on completions for config reads. */ if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && bridge->device == 0x80b5) return pci_idt_bus_quirk(bus, devfn, l, timeout); #endif return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); } |
efdc87dab
|
2253 2254 2255 |
EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); /* |
3e466e2d3
|
2256 2257 |
* Read the config data for a PCI device, sanity-check it, * and fill in the dev structure. |
efdc87dab
|
2258 2259 2260 2261 2262 2263 2264 2265 |
*/ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) { struct pci_dev *dev; u32 l; if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) return NULL; |
8b1fce04d
|
2266 |
dev = pci_alloc_dev(bus); |
1da177e4c
|
2267 2268 |
if (!dev) return NULL; |
1da177e4c
|
2269 |
dev->devfn = devfn; |
1da177e4c
|
2270 2271 |
dev->vendor = l & 0xffff; dev->device = (l >> 16) & 0xffff; |
cef354db0
|
2272 |
|
98d9f30c8
|
2273 |
pci_set_of_node(dev); |
480b93b78
|
2274 |
if (pci_setup_device(dev)) { |
8b1fce04d
|
2275 |
pci_bus_put(dev->bus); |
1da177e4c
|
2276 2277 2278 |
kfree(dev); return NULL; } |
1da177e4c
|
2279 2280 2281 |
return dev; } |
0fa635aec
|
2282 |
void pcie_report_downtraining(struct pci_dev *dev) |
2d1ce5ec2
|
2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 |
{ if (!pci_is_pcie(dev)) return; /* Look from the device up to avoid downstream ports with no devices */ if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) return; /* Multi-function PCIe devices share the same link/status */ if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) return; /* Print link status only if the device is constrained by the fabric */ __pcie_print_link_status(dev, false); } |
201de56eb
|
2300 2301 |
static void pci_init_capabilities(struct pci_dev *dev) { |
9d8b738bb
|
2302 |
pci_ea_init(dev); /* Enhanced Allocation */ |
938174e59
|
2303 |
|
e80e7edc5
|
2304 2305 |
/* Setup MSI caps & disable MSI/MSI-X interrupts */ pci_msi_setup_pci_dev(dev); |
201de56eb
|
2306 |
|
63f4898ac
|
2307 2308 |
/* Buffers for saving PCIe and PCI-X capabilities */ pci_allocate_cap_save_buffers(dev); |
9d8b738bb
|
2309 2310 2311 2312 2313 |
pci_pm_init(dev); /* Power Management */ pci_vpd_init(dev); /* Vital Product Data */ pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ pci_iov_init(dev); /* Single Root I/O Virtualization */ pci_ats_init(dev); /* Address Translation Services */ |
7e124c405
|
2314 2315 |
pci_pri_init(dev); /* Page Request Interface */ pci_pasid_init(dev); /* Process Address Space ID */ |
52fbf5bde
|
2316 |
pci_acs_init(dev); /* Access Control Services */ |
9d8b738bb
|
2317 2318 |
pci_ptm_init(dev); /* Precision Time Measurement */ pci_aer_init(dev); /* Advanced Error Reporting */ |
270056181
|
2319 |
pci_dpc_init(dev); /* Downstream Port Containment */ |
5b0764cac
|
2320 |
|
2d1ce5ec2
|
2321 |
pcie_report_downtraining(dev); |
5b0764cac
|
2322 2323 |
if (pci_probe_reset_function(dev) == 0) dev->reset_fn = 1; |
201de56eb
|
2324 |
} |
098259eb1
|
2325 |
/* |
3e466e2d3
|
2326 |
* This is the equivalent of pci_host_bridge_msi_domain() that acts on |
098259eb1
|
2327 2328 2329 2330 2331 2332 2333 2334 |
* devices. Firmware interfaces that can select the MSI domain on a * per-device basis should be called from here. */ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) { struct irq_domain *d; /* |
3e466e2d3
|
2335 |
* If a domain has been set through the pcibios_add_device() |
098259eb1
|
2336 2337 2338 2339 2340 |
* callback, then this is the one (platform code knows best). */ d = dev_get_msi_domain(&dev->dev); if (d) return d; |
54fa97eeb
|
2341 2342 2343 2344 2345 2346 2347 |
/* * Let's see if we have a firmware interface able to provide * the domain. */ d = pci_msi_get_device_domain(dev); if (d) return d; |
098259eb1
|
2348 2349 |
return NULL; } |
44aa0c657
|
2350 2351 |
static void pci_set_msi_domain(struct pci_dev *dev) { |
098259eb1
|
2352 |
struct irq_domain *d; |
44aa0c657
|
2353 |
/* |
098259eb1
|
2354 2355 2356 |
* If the platform or firmware interfaces cannot supply a * device-specific MSI domain, then inherit the default domain * from the host bridge itself. |
44aa0c657
|
2357 |
*/ |
098259eb1
|
2358 2359 2360 2361 2362 |
d = pci_dev_msi_domain(dev); if (!d) d = dev_get_msi_domain(&dev->bus->dev); dev_set_msi_domain(&dev->dev, d); |
44aa0c657
|
2363 |
} |
96bde06a2
|
2364 |
void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4c
|
2365 |
{ |
4f535093c
|
2366 |
int ret; |
6cd33649f
|
2367 |
pci_configure_device(dev); |
cdb9b9f73
|
2368 2369 |
device_initialize(&dev->dev); dev->dev.release = pci_release_dev; |
1da177e4c
|
2370 |
|
7629d19a4
|
2371 |
set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f73
|
2372 |
dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfac
|
2373 |
dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f73
|
2374 |
dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4c
|
2375 |
|
b0da3498c
|
2376 |
dma_set_max_seg_size(&dev->dev, 65536); |
a6f44cf9f
|
2377 |
dma_set_seg_boundary(&dev->dev, 0xffffffff); |
4d57cdfac
|
2378 |
|
1da177e4c
|
2379 2380 |
/* Fix up broken headers */ pci_fixup_device(pci_fixup_header, dev); |
2069ecfbe
|
2381 |
pci_reassigndev_resource_alignment(dev); |
4b77b0a2b
|
2382 |
dev->state_saved = false; |
201de56eb
|
2383 |
pci_init_capabilities(dev); |
eb9d0fe40
|
2384 |
|
1da177e4c
|
2385 2386 2387 2388 |
/* * Add the device to our list of discovered devices * and the bus list for fixup functions, etc. */ |
d71374daf
|
2389 |
down_write(&pci_bus_sem); |
1da177e4c
|
2390 |
list_add_tail(&dev->bus_list, &bus->devices); |
d71374daf
|
2391 |
up_write(&pci_bus_sem); |
4f535093c
|
2392 |
|
4f535093c
|
2393 2394 |
ret = pcibios_add_device(dev); WARN_ON(ret < 0); |
3e466e2d3
|
2395 |
/* Set up MSI IRQ domain */ |
44aa0c657
|
2396 |
pci_set_msi_domain(dev); |
4f535093c
|
2397 2398 2399 2400 |
/* Notifier could use PCI capabilities */ dev->match_driver = false; ret = device_add(&dev->dev); WARN_ON(ret < 0); |
cdb9b9f73
|
2401 |
} |
10874f5a0
|
2402 |
struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f73
|
2403 2404 |
{ struct pci_dev *dev; |
90bdb3117
|
2405 2406 2407 2408 2409 |
dev = pci_get_slot(bus, devfn); if (dev) { pci_dev_put(dev); return dev; } |
cdb9b9f73
|
2410 2411 2412 2413 2414 |
dev = pci_scan_device(bus, devfn); if (!dev) return NULL; pci_device_add(dev, bus); |
1da177e4c
|
2415 2416 2417 |
return dev; } |
b73e96878
|
2418 |
EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4c
|
2419 |
|
b1bd58e44
|
2420 |
static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) |
f07852d64
|
2421 |
{ |
b1bd58e44
|
2422 2423 2424 |
int pos; u16 cap = 0; unsigned next_fn; |
4fb88c1a2
|
2425 |
|
b1bd58e44
|
2426 2427 2428 2429 2430 2431 |
if (pci_ari_enabled(bus)) { if (!dev) return 0; pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); if (!pos) return 0; |
4fb88c1a2
|
2432 |
|
b1bd58e44
|
2433 2434 2435 2436 |
pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); next_fn = PCI_ARI_CAP_NFN(cap); if (next_fn <= fn) return 0; /* protect against malformed list */ |
f07852d64
|
2437 |
|
b1bd58e44
|
2438 2439 2440 2441 2442 2443 |
return next_fn; } /* dev may be NULL for non-contiguous multifunction devices */ if (!dev || dev->multifunction) return (fn + 1) % 8; |
f07852d64
|
2444 |
|
f07852d64
|
2445 2446 2447 2448 2449 |
return 0; } static int only_one_child(struct pci_bus *bus) { |
d57f0b8c8
|
2450 |
struct pci_dev *bridge = bus->self; |
284f5f9db
|
2451 |
|
d57f0b8c8
|
2452 2453 2454 2455 2456 |
/* * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so * we scan for all possible devices, not just Device 0. */ if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) |
f07852d64
|
2457 |
return 0; |
5bbe029ff
|
2458 2459 |
/* |
d57f0b8c8
|
2460 2461 2462 |
* A PCIe Downstream Port normally leads to a Link with only Device * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan * only for Device 0 in that situation. |
5bbe029ff
|
2463 |
*/ |
ca7841040
|
2464 |
if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) |
f07852d64
|
2465 |
return 1; |
d57f0b8c8
|
2466 |
|
f07852d64
|
2467 2468 |
return 0; } |
1da177e4c
|
2469 |
/** |
3e466e2d3
|
2470 |
* pci_scan_slot - Scan a PCI slot on a bus for devices |
1da177e4c
|
2471 |
* @bus: PCI bus to scan |
3e466e2d3
|
2472 |
* @devfn: slot number to scan (must have zero function) |
1da177e4c
|
2473 2474 2475 |
* * Scan a PCI slot on the specified PCI bus for devices, adding * discovered devices to the @bus->devices list. New devices |
8a1bc9013
|
2476 |
* will not have is_added set. |
1b69dfc64
|
2477 2478 |
* * Returns the number of new devices found. |
1da177e4c
|
2479 |
*/ |
96bde06a2
|
2480 |
int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4c
|
2481 |
{ |
f07852d64
|
2482 |
unsigned fn, nr = 0; |
1b69dfc64
|
2483 |
struct pci_dev *dev; |
f07852d64
|
2484 2485 2486 |
if (only_one_child(bus) && (devfn > 0)) return 0; /* Already scanned the entire slot */ |
1da177e4c
|
2487 |
|
1b69dfc64
|
2488 |
dev = pci_scan_single_device(bus, devfn); |
4fb88c1a2
|
2489 2490 |
if (!dev) return 0; |
44bda4b7d
|
2491 |
if (!pci_dev_is_added(dev)) |
1b69dfc64
|
2492 |
nr++; |
b1bd58e44
|
2493 |
for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
f07852d64
|
2494 2495 |
dev = pci_scan_single_device(bus, devfn + fn); if (dev) { |
44bda4b7d
|
2496 |
if (!pci_dev_is_added(dev)) |
f07852d64
|
2497 2498 |
nr++; dev->multifunction = 1; |
1da177e4c
|
2499 2500 |
} } |
7d715a6c1
|
2501 |
|
3e466e2d3
|
2502 |
/* Only one slot has PCIe device */ |
149e16372
|
2503 |
if (bus->self && nr) |
7d715a6c1
|
2504 |
pcie_aspm_init_link_state(bus->self); |
1da177e4c
|
2505 2506 |
return nr; } |
b7fe94342
|
2507 |
EXPORT_SYMBOL(pci_scan_slot); |
1da177e4c
|
2508 |
|
b03e7495a
|
2509 2510 2511 2512 2513 2514 |
static int pcie_find_smpss(struct pci_dev *dev, void *data) { u8 *smpss = data; if (!pci_is_pcie(dev)) return 0; |
d4aa68f61
|
2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 |
/* * We don't have a way to change MPS settings on devices that have * drivers attached. A hot-added device might support only the minimum * MPS setting (MPS=128). Therefore, if the fabric contains a bridge * where devices may be hot-added, we limit the fabric MPS to 128 so * hot-added devices will work correctly. * * However, if we hot-add a device to a slot directly below a Root * Port, it's impossible for there to be other existing devices below * the port. We don't limit the MPS in this case because we can * reconfigure MPS on both the Root Port and the hot-added device, * and there are no other devices involved. * * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. |
b03e7495a
|
2529 |
*/ |
d4aa68f61
|
2530 2531 |
if (dev->is_hotplug_bridge && pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) |
b03e7495a
|
2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 |
*smpss = 0; if (*smpss > dev->pcie_mpss) *smpss = dev->pcie_mpss; return 0; } static void pcie_write_mps(struct pci_dev *dev, int mps) { |
62f392ea5
|
2542 |
int rc; |
b03e7495a
|
2543 2544 |
if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { |
62f392ea5
|
2545 |
mps = 128 << dev->pcie_mpss; |
b03e7495a
|
2546 |
|
62f87c0e3
|
2547 2548 |
if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self) |
3e466e2d3
|
2549 2550 2551 |
/* * For "Performance", the assumption is made that |
b03e7495a
|
2552 2553 2554 2555 2556 |
* downstream communication will never be larger than * the MRRS. So, the MPS only needs to be configured * for the upstream communication. This being the case, * walk from the top down and set the MPS of the child * to that of the parent bus. |
62f392ea5
|
2557 2558 2559 2560 2561 |
* * Configure the device MPS with the smaller of the * device MPSS or the bridge MPS (which is assumed to be * properly configured at this point to the largest * allowable MPS based on its parent bus). |
b03e7495a
|
2562 |
*/ |
62f392ea5
|
2563 |
mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495a
|
2564 2565 2566 2567 |
} rc = pcie_set_mps(dev, mps); if (rc) |
7506dc798
|
2568 2569 |
pci_err(dev, "Failed attempting to set the MPS "); |
b03e7495a
|
2570 |
} |
62f392ea5
|
2571 |
static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495a
|
2572 |
{ |
62f392ea5
|
2573 |
int rc, mrrs; |
b03e7495a
|
2574 |
|
3e466e2d3
|
2575 2576 |
/* * In the "safe" case, do not configure the MRRS. There appear to be |
ed2888e90
|
2577 2578 |
* issues with setting MRRS to 0 on a number of devices. */ |
ed2888e90
|
2579 2580 |
if (pcie_bus_config != PCIE_BUS_PERFORMANCE) return; |
3e466e2d3
|
2581 2582 |
/* * For max performance, the MRRS must be set to the largest supported |
ed2888e90
|
2583 |
* value. However, it cannot be configured larger than the MPS the |
62f392ea5
|
2584 |
* device or the bus can support. This should already be properly |
3e466e2d3
|
2585 |
* configured by a prior call to pcie_write_mps(). |
ed2888e90
|
2586 |
*/ |
62f392ea5
|
2587 |
mrrs = pcie_get_mps(dev); |
b03e7495a
|
2588 |
|
3e466e2d3
|
2589 2590 |
/* * MRRS is a R/W register. Invalid values can be written, but a |
ed2888e90
|
2591 |
* subsequent read will verify if the value is acceptable or not. |
b03e7495a
|
2592 2593 |
* If the MRRS value provided is not acceptable (e.g., too large), * shrink the value until it is acceptable to the HW. |
f7625980f
|
2594 |
*/ |
b03e7495a
|
2595 2596 |
while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { rc = pcie_set_readrq(dev, mrrs); |
62f392ea5
|
2597 2598 |
if (!rc) break; |
b03e7495a
|
2599 |
|
7506dc798
|
2600 2601 |
pci_warn(dev, "Failed attempting to set the MRRS "); |
b03e7495a
|
2602 2603 |
mrrs /= 2; } |
62f392ea5
|
2604 2605 |
if (mrrs < 128) |
7506dc798
|
2606 2607 |
pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe "); |
b03e7495a
|
2608 2609 2610 2611 |
} static int pcie_bus_configure_set(struct pci_dev *dev, void *data) { |
a513a99a7
|
2612 |
int mps, orig_mps; |
b03e7495a
|
2613 2614 2615 |
if (!pci_is_pcie(dev)) return 0; |
27d868b5e
|
2616 2617 |
if (pcie_bus_config == PCIE_BUS_TUNE_OFF || pcie_bus_config == PCIE_BUS_DEFAULT) |
5895af791
|
2618 |
return 0; |
5895af791
|
2619 |
|
a513a99a7
|
2620 2621 |
mps = 128 << *(u8 *)data; orig_mps = pcie_get_mps(dev); |
b03e7495a
|
2622 2623 |
pcie_write_mps(dev, mps); |
62f392ea5
|
2624 |
pcie_write_mrrs(dev); |
b03e7495a
|
2625 |
|
7506dc798
|
2626 2627 |
pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d ", |
227f06470
|
2628 |
pcie_get_mps(dev), 128 << dev->pcie_mpss, |
a513a99a7
|
2629 |
orig_mps, pcie_get_readrq(dev)); |
b03e7495a
|
2630 2631 2632 |
return 0; } |
3e466e2d3
|
2633 2634 |
/* * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, |
b03e7495a
|
2635 2636 2637 |
* parents then children fashion. If this changes, then this code will not * work as designed. */ |
a58674ff8
|
2638 |
void pcie_bus_configure_settings(struct pci_bus *bus) |
b03e7495a
|
2639 |
{ |
1e358f94c
|
2640 |
u8 smpss = 0; |
b03e7495a
|
2641 |
|
a58674ff8
|
2642 |
if (!bus->self) |
b03e7495a
|
2643 |
return; |
b03e7495a
|
2644 |
if (!pci_is_pcie(bus->self)) |
5f39e6705
|
2645 |
return; |
3e466e2d3
|
2646 2647 |
/* * FIXME - Peer to peer DMA is possible, though the endpoint would need |
3315472c4
|
2648 |
* to be aware of the MPS of the destination. To work around this, |
5f39e6705
|
2649 2650 2651 2652 |
* simply force the MPS of the entire system to the smallest possible. */ if (pcie_bus_config == PCIE_BUS_PEER2PEER) smpss = 0; |
b03e7495a
|
2653 |
if (pcie_bus_config == PCIE_BUS_SAFE) { |
a58674ff8
|
2654 |
smpss = bus->self->pcie_mpss; |
5f39e6705
|
2655 |
|
b03e7495a
|
2656 2657 2658 2659 2660 2661 2662 |
pcie_find_smpss(bus->self, &smpss); pci_walk_bus(bus, pcie_find_smpss, &smpss); } pcie_bus_configure_set(bus->self, &smpss); pci_walk_bus(bus, pcie_bus_configure_set, &smpss); } |
debc3b778
|
2663 |
EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495a
|
2664 |
|
bccf90d6e
|
2665 2666 2667 2668 2669 2670 2671 2672 |
/* * Called after each bus is probed, but before its children are examined. This * is marked as __weak because multiple architectures define it. */ void __weak pcibios_fixup_bus(struct pci_bus *bus) { /* nothing to do, expected to be removed in the future */ } |
1c02ea810
|
2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 |
/** * pci_scan_child_bus_extend() - Scan devices below a bus * @bus: Bus to scan for devices * @available_buses: Total number of buses available (%0 does not try to * extend beyond the minimal) * * Scans devices below @bus including subordinate buses. Returns new * subordinate number including all the found devices. Passing * @available_buses causes the remaining bus space to be distributed * equally between hotplug-capable bridges to allow future extension of the * hierarchy. */ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, unsigned int available_buses) |
1da177e4c
|
2687 |
{ |
1c02ea810
|
2688 2689 |
unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; unsigned int start = bus->busn_res.start; |
690f43041
|
2690 |
unsigned int devfn, fn, cmax, max = start; |
1da177e4c
|
2691 |
struct pci_dev *dev; |
690f43041
|
2692 |
int nr_devs; |
1da177e4c
|
2693 |
|
0207c356e
|
2694 2695 |
dev_dbg(&bus->dev, "scanning bus "); |
1da177e4c
|
2696 2697 |
/* Go find them, Rover! */ |
690f43041
|
2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 |
for (devfn = 0; devfn < 256; devfn += 8) { nr_devs = pci_scan_slot(bus, devfn); /* * The Jailhouse hypervisor may pass individual functions of a * multi-function device to a guest without passing function 0. * Look for them as well. */ if (jailhouse_paravirt() && nr_devs == 0) { for (fn = 1; fn < 8; fn++) { dev = pci_scan_single_device(bus, devfn + fn); if (dev) dev->multifunction = 1; } } } |
1da177e4c
|
2714 |
|
3e466e2d3
|
2715 |
/* Reserve buses for SR-IOV capability */ |
1c02ea810
|
2716 2717 |
used_buses = pci_iov_bus_range(bus); max += used_buses; |
a28724b0f
|
2718 |
|
1da177e4c
|
2719 2720 2721 2722 |
/* * After performing arch-dependent fixup of the bus, look behind * all PCI-to-PCI bridges on this bus. */ |
74710ded8
|
2723 |
if (!bus->is_added) { |
0207c356e
|
2724 2725 |
dev_dbg(&bus->dev, "fixups for bus "); |
74710ded8
|
2726 |
pcibios_fixup_bus(bus); |
981cf9ea9
|
2727 |
bus->is_added = 1; |
74710ded8
|
2728 |
} |
4147c2fd9
|
2729 |
/* |
1c02ea810
|
2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 |
* Calculate how many hotplug bridges and normal bridges there * are on this bus. We will distribute the additional available * buses between hotplug bridges. */ for_each_pci_bridge(dev, bus) { if (dev->is_hotplug_bridge) hotplug_bridges++; else normal_bridges++; } /* |
4147c2fd9
|
2742 2743 2744 2745 |
* Scan bridges that are already configured. We don't touch them * unless they are misconfigured (which will be done in the second * scan below). */ |
1c02ea810
|
2746 2747 2748 |
for_each_pci_bridge(dev, bus) { cmax = max; max = pci_scan_bridge_extend(bus, dev, max, 0, 0); |
3374c545c
|
2749 2750 2751 2752 2753 2754 2755 2756 |
/* * Reserve one bus for each bridge now to avoid extending * hotplug bridges too much during the second scan below. */ used_buses++; if (cmax - max > 1) used_buses += cmax - max - 1; |
1c02ea810
|
2757 |
} |
4147c2fd9
|
2758 2759 |
/* Scan bridges that need to be reconfigured */ |
1c02ea810
|
2760 2761 2762 2763 |
for_each_pci_bridge(dev, bus) { unsigned int buses = 0; if (!hotplug_bridges && normal_bridges == 1) { |
3e466e2d3
|
2764 |
|
1c02ea810
|
2765 2766 2767 2768 2769 2770 2771 2772 |
/* * There is only one bridge on the bus (upstream * port) so it gets all available buses which it * can then distribute to the possible hotplug * bridges below. */ buses = available_buses; } else if (dev->is_hotplug_bridge) { |
3e466e2d3
|
2773 |
|
1c02ea810
|
2774 2775 2776 2777 2778 |
/* * Distribute the extra buses between hotplug * bridges if any. */ buses = available_buses / hotplug_bridges; |
3374c545c
|
2779 |
buses = min(buses, available_buses - used_buses + 1); |
1c02ea810
|
2780 2781 2782 2783 |
} cmax = max; max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); |
3374c545c
|
2784 2785 2786 |
/* One bus is already accounted so don't add it again */ if (max - cmax > 1) used_buses += max - cmax - 1; |
1c02ea810
|
2787 |
} |
1da177e4c
|
2788 2789 |
/* |
e16b46605
|
2790 |
* Make sure a hotplug bridge has at least the minimum requested |
1c02ea810
|
2791 2792 |
* number of buses but allow it to grow up to the maximum available * bus number of there is room. |
e16b46605
|
2793 |
*/ |
1c02ea810
|
2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 |
if (bus->self && bus->self->is_hotplug_bridge) { used_buses = max_t(unsigned int, available_buses, pci_hotplug_bus_size - 1); if (max - start < used_buses) { max = start + used_buses; /* Do not allocate more buses than we have room left */ if (max > bus->busn_res.end) max = bus->busn_res.end; dev_dbg(&bus->dev, "%pR extended by %#02x ", &bus->busn_res, max - start); } |
e16b46605
|
2808 2809 2810 |
} /* |
1da177e4c
|
2811 2812 2813 2814 2815 2816 |
* We've scanned the bus and so we know all about what's on * the other side of any bridges that may be on this bus plus * any devices. * * Return how far we've got finding sub-buses. */ |
0207c356e
|
2817 2818 |
dev_dbg(&bus->dev, "bus scan returning with max=%02x ", max); |
1da177e4c
|
2819 2820 |
return max; } |
1c02ea810
|
2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 |
/** * pci_scan_child_bus() - Scan devices below a bus * @bus: Bus to scan for devices * * Scans devices below @bus including subordinate buses. Returns new * subordinate number including all the found devices. */ unsigned int pci_scan_child_bus(struct pci_bus *bus) { return pci_scan_child_bus_extend(bus, 0); } |
b7fe94342
|
2833 |
EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1da177e4c
|
2834 |
|
6c0cc950a
|
2835 |
/** |
3e466e2d3
|
2836 2837 |
* pcibios_root_bridge_prepare - Platform-specific host bridge setup * @bridge: Host bridge to set up |
6c0cc950a
|
2838 2839 2840 2841 2842 2843 2844 2845 |
* * Default empty implementation. Replace with an architecture-specific setup * routine, if necessary. */ int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) { return 0; } |
10a957475
|
2846 2847 2848 2849 2850 2851 2852 |
void __weak pcibios_add_bus(struct pci_bus *bus) { } void __weak pcibios_remove_bus(struct pci_bus *bus) { } |
9ee8a1c4a
|
2853 2854 |
struct pci_bus *pci_create_root_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata, struct list_head *resources) |
1da177e4c
|
2855 |
{ |
0efd5aab4
|
2856 |
int error; |
5a21d70db
|
2857 |
struct pci_host_bridge *bridge; |
1da177e4c
|
2858 |
|
590940659
|
2859 |
bridge = pci_alloc_host_bridge(0); |
7b5436635
|
2860 |
if (!bridge) |
37d6a0a6f
|
2861 |
return NULL; |
7b5436635
|
2862 2863 |
bridge->dev.parent = parent; |
a9d9f5276
|
2864 |
|
37d6a0a6f
|
2865 2866 2867 2868 |
list_splice_init(resources, &bridge->windows); bridge->sysdata = sysdata; bridge->busnr = bus; bridge->ops = ops; |
a9d9f5276
|
2869 |
|
37d6a0a6f
|
2870 2871 2872 |
error = pci_register_host_bridge(bridge); if (error < 0) goto err_out; |
a5390aa6d
|
2873 |
|
37d6a0a6f
|
2874 |
return bridge->bus; |
1da177e4c
|
2875 |
|
1da177e4c
|
2876 |
err_out: |
9885440b1
|
2877 |
put_device(&bridge->dev); |
1da177e4c
|
2878 2879 |
return NULL; } |
e6b29deaf
|
2880 |
EXPORT_SYMBOL_GPL(pci_create_root_bus); |
cdb9b9f73
|
2881 |
|
49b8e3f3e
|
2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 |
int pci_host_probe(struct pci_host_bridge *bridge) { struct pci_bus *bus, *child; int ret; ret = pci_scan_root_bus_bridge(bridge); if (ret < 0) { dev_err(bridge->dev.parent, "Scanning root bridge failed"); return ret; } bus = bridge->bus; /* * We insert PCI resources into the iomem_resource and * ioport_resource trees in either pci_bus_claim_resources() * or pci_bus_assign_resources(). */ if (pci_has_flag(PCI_PROBE_ONLY)) { pci_bus_claim_resources(bus); } else { pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); list_for_each_entry(child, &bus->children, node) pcie_bus_configure_settings(child); } pci_bus_add_devices(bus); return 0; } EXPORT_SYMBOL_GPL(pci_host_probe); |
98a358310
|
2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 |
int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) { struct resource *res = &b->busn_res; struct resource *parent_res, *conflict; res->start = bus; res->end = bus_max; res->flags = IORESOURCE_BUS; if (!pci_is_root_bus(b)) parent_res = &b->parent->busn_res; else { parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); res->flags |= IORESOURCE_PCI_FIXED; } |
ced04d155
|
2929 |
conflict = request_resource_conflict(parent_res, res); |
98a358310
|
2930 2931 |
if (conflict) |
34c6b7105
|
2932 |
dev_info(&b->dev, |
98a358310
|
2933 2934 2935 2936 |
"busn_res: can not insert %pR under %s%pR (conflicts with %s %pR) ", res, pci_is_root_bus(b) ? "domain " : "", parent_res, conflict->name, conflict); |
98a358310
|
2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 |
return conflict == NULL; } int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) { struct resource *res = &b->busn_res; struct resource old_res = *res; resource_size_t size; int ret; if (res->start > bus_max) return -EINVAL; size = bus_max - res->start + 1; ret = adjust_resource(res, res->start, size); |
34c6b7105
|
2953 2954 |
dev_info(&b->dev, "busn_res: %pR end %s updated to %02x ", |
98a358310
|
2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 |
&old_res, ret ? "can not be" : "is", bus_max); if (!ret && !res->parent) pci_bus_insert_busn_res(b, res->start, res->end); return ret; } void pci_bus_release_busn_res(struct pci_bus *b) { struct resource *res = &b->busn_res; int ret; if (!res->flags || !res->parent) return; ret = release_resource(res); |
34c6b7105
|
2972 2973 |
dev_info(&b->dev, "busn_res: %pR %s released ", |
98a358310
|
2974 2975 |
res, ret ? "can not be" : "is"); } |
1228c4b6c
|
2976 |
int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) |
a2ebb8279
|
2977 |
{ |
14d76b68f
|
2978 |
struct resource_entry *window; |
4d99f5242
|
2979 |
bool found = false; |
a2ebb8279
|
2980 |
struct pci_bus *b; |
1228c4b6c
|
2981 |
int max, bus, ret; |
4d99f5242
|
2982 |
|
1228c4b6c
|
2983 2984 2985 2986 |
if (!bridge) return -EINVAL; resource_list_for_each_entry(window, &bridge->windows) |
4d99f5242
|
2987 |
if (window->res->flags & IORESOURCE_BUS) { |
4f5c883d7
|
2988 |
bridge->busnr = window->res->start; |
4d99f5242
|
2989 2990 2991 |
found = true; break; } |
a2ebb8279
|
2992 |
|
1228c4b6c
|
2993 2994 2995 2996 2997 2998 |
ret = pci_register_host_bridge(bridge); if (ret < 0) return ret; b = bridge->bus; bus = bridge->busnr; |
a2ebb8279
|
2999 |
|
4d99f5242
|
3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 |
if (!found) { dev_info(&b->dev, "No busn resource found for root bus, will use [bus %02x-ff] ", bus); pci_bus_insert_busn_res(b, bus, 255); } max = pci_scan_child_bus(b); if (!found) pci_bus_update_busn_res_end(b, max); |
1228c4b6c
|
3012 |
return 0; |
a2ebb8279
|
3013 |
} |
1228c4b6c
|
3014 |
EXPORT_SYMBOL(pci_scan_root_bus_bridge); |
d2a7926d4
|
3015 3016 3017 3018 |
struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata, struct list_head *resources) { |
14d76b68f
|
3019 |
struct resource_entry *window; |
4d99f5242
|
3020 |
bool found = false; |
a2ebb8279
|
3021 |
struct pci_bus *b; |
4d99f5242
|
3022 |
int max; |
14d76b68f
|
3023 |
resource_list_for_each_entry(window, resources) |
4d99f5242
|
3024 3025 3026 3027 |
if (window->res->flags & IORESOURCE_BUS) { found = true; break; } |
a2ebb8279
|
3028 |
|
9ee8a1c4a
|
3029 |
b = pci_create_root_bus(parent, bus, ops, sysdata, resources); |
a2ebb8279
|
3030 3031 |
if (!b) return NULL; |
4d99f5242
|
3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 |
if (!found) { dev_info(&b->dev, "No busn resource found for root bus, will use [bus %02x-ff] ", bus); pci_bus_insert_busn_res(b, bus, 255); } max = pci_scan_child_bus(b); if (!found) pci_bus_update_busn_res_end(b, max); |
a2ebb8279
|
3044 |
return b; |
d2a7926d4
|
3045 |
} |
a2ebb8279
|
3046 |
EXPORT_SYMBOL(pci_scan_root_bus); |
15856ad50
|
3047 |
struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
de4b2f76d
|
3048 3049 3050 3051 3052 3053 3054 |
void *sysdata) { LIST_HEAD(resources); struct pci_bus *b; pci_add_resource(&resources, &ioport_resource); pci_add_resource(&resources, &iomem_resource); |
857c3b668
|
3055 |
pci_add_resource(&resources, &busn_resource); |
de4b2f76d
|
3056 3057 |
b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); if (b) { |
857c3b668
|
3058 |
pci_scan_child_bus(b); |
de4b2f76d
|
3059 3060 3061 3062 3063 3064 |
} else { pci_free_resource_list(&resources); } return b; } EXPORT_SYMBOL(pci_scan_bus); |
3ed4fd96b
|
3065 |
/** |
3e466e2d3
|
3066 |
* pci_rescan_bus_bridge_resize - Scan a PCI bus for devices |
2f320521a
|
3067 3068 3069 3070 3071 3072 3073 3074 3075 |
* @bridge: PCI bridge for the bus to scan * * Scan a PCI bus and child buses for new devices, add them, * and enable them, resizing bridge mmio/io resource if necessary * and possible. The caller must ensure the child devices are already * removed for resizing to occur. * * Returns the max number of subordinate bus discovered. */ |
10874f5a0
|
3076 |
unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
2f320521a
|
3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 |
{ unsigned int max; struct pci_bus *bus = bridge->subordinate; max = pci_scan_child_bus(bus); pci_assign_unassigned_bridge_resources(bridge); pci_bus_add_devices(bus); return max; } |
a5213a319
|
3089 |
/** |
3e466e2d3
|
3090 |
* pci_rescan_bus - Scan a PCI bus for devices |
a5213a319
|
3091 3092 |
* @bus: PCI bus to scan * |
3e466e2d3
|
3093 3094 |
* Scan a PCI bus and child buses for new devices, add them, * and enable them. |
a5213a319
|
3095 3096 3097 |
* * Returns the max number of subordinate bus discovered. */ |
10874f5a0
|
3098 |
unsigned int pci_rescan_bus(struct pci_bus *bus) |
a5213a319
|
3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 |
{ unsigned int max; max = pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); pci_bus_add_devices(bus); return max; } EXPORT_SYMBOL_GPL(pci_rescan_bus); |
9d16947b7
|
3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 |
/* * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal * routines should always be executed under this mutex. */ static DEFINE_MUTEX(pci_rescan_remove_lock); void pci_lock_rescan_remove(void) { mutex_lock(&pci_rescan_remove_lock); } EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); void pci_unlock_rescan_remove(void) { mutex_unlock(&pci_rescan_remove_lock); } EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); |
3c78bc61f
|
3126 3127 |
static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fed
|
3128 |
{ |
99178b036
|
3129 3130 |
const struct pci_dev *a = to_pci_dev(d_a); const struct pci_dev *b = to_pci_dev(d_b); |
6b4b78fed
|
3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 |
if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; if (a->bus->number < b->bus->number) return -1; else if (a->bus->number > b->bus->number) return 1; if (a->devfn < b->devfn) return -1; else if (a->devfn > b->devfn) return 1; return 0; } |
5ff580c10
|
3142 |
void __init pci_sort_breadthfirst(void) |
6b4b78fed
|
3143 |
{ |
99178b036
|
3144 |
bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fed
|
3145 |
} |
95e3ba977
|
3146 3147 3148 3149 |
int pci_hp_add_bridge(struct pci_dev *dev) { struct pci_bus *parent = dev->bus; |
4147c2fd9
|
3150 |
int busnr, start = parent->busn_res.start; |
1c02ea810
|
3151 |
unsigned int available_buses = 0; |
95e3ba977
|
3152 3153 3154 3155 3156 3157 3158 |
int end = parent->busn_res.end; for (busnr = start; busnr <= end; busnr++) { if (!pci_find_bus(pci_domain_nr(parent), busnr)) break; } if (busnr-- > end) { |
7506dc798
|
3159 3160 |
pci_err(dev, "No bus number available for hot-added bridge "); |
95e3ba977
|
3161 3162 |
return -1; } |
4147c2fd9
|
3163 3164 3165 |
/* Scan bridges that are already configured */ busnr = pci_scan_bridge(parent, dev, busnr, 0); |
1c02ea810
|
3166 3167 3168 3169 3170 |
/* * Distribute the available bus numbers between hotplug-capable * bridges to make extending the chain later possible. */ available_buses = end - busnr; |
4147c2fd9
|
3171 |
/* Scan bridges that need to be reconfigured */ |
1c02ea810
|
3172 |
pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); |
4147c2fd9
|
3173 |
|
95e3ba977
|
3174 3175 3176 3177 3178 3179 |
if (!dev->subordinate) return -1; return 0; } EXPORT_SYMBOL_GPL(pci_hp_add_bridge); |