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drivers/ata/sata_fsl.c
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/* * drivers/ata/sata_fsl.c * * Freescale 3.0Gbps SATA device driver * * Author: Ashish Kalra <ashish.kalra@freescale.com> * Li Yang <leoli@freescale.com> * |
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* Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. |
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* * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <scsi/scsi_host.h> #include <scsi/scsi_cmnd.h> #include <linux/libata.h> #include <asm/io.h> |
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#include <linux/of_address.h> #include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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static unsigned int intr_coalescing_count; module_param(intr_coalescing_count, int, S_IRUGO); MODULE_PARM_DESC(intr_coalescing_count, "INT coalescing count threshold (1..31)"); static unsigned int intr_coalescing_ticks; module_param(intr_coalescing_ticks, int, S_IRUGO); MODULE_PARM_DESC(intr_coalescing_ticks, "INT coalescing timer threshold in AHB ticks"); |
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/* Controller information */ enum { SATA_FSL_QUEUE_DEPTH = 16, SATA_FSL_MAX_PRD = 63, SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ |
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SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
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ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE), |
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SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), /* * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and |
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* chained indirect PRDEs up to a max count of 63. |
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* We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will |
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* be setup as an indirect descriptor, pointing to it's next |
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* (contiguous) PRDE. Though chained indirect PRDE arrays are |
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* supported,it will be more efficient to use a direct PRDT and * a single chain/link to indirect PRDE array/PRDT. */ SATA_FSL_CMD_DESC_CFIS_SZ = 32, SATA_FSL_CMD_DESC_SFIS_SZ = 32, SATA_FSL_CMD_DESC_ACMD_SZ = 16, SATA_FSL_CMD_DESC_RSRVD = 16, SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + SATA_FSL_CMD_DESC_SFIS_SZ + SATA_FSL_CMD_DESC_ACMD_SZ + SATA_FSL_CMD_DESC_RSRVD + SATA_FSL_MAX_PRD * 16), SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = (SATA_FSL_CMD_DESC_CFIS_SZ + SATA_FSL_CMD_DESC_SFIS_SZ + SATA_FSL_CMD_DESC_ACMD_SZ + SATA_FSL_CMD_DESC_RSRVD), SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + SATA_FSL_CMD_DESC_AR_SZ), /* * MPC8315 has two SATA controllers, SATA1 & SATA2 * (one port per controller) * MPC837x has 2/4 controllers, one port per controller */ SATA_FSL_MAX_PORTS = 1, SATA_FSL_IRQ_FLAG = IRQF_SHARED, }; /* |
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* Interrupt Coalescing Control Register bitdefs */ enum { ICC_MIN_INT_COUNT_THRESHOLD = 1, ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), ICC_MIN_INT_TICKS_THRESHOLD = 0, ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), ICC_SAFE_INT_TICKS = 1, }; /* |
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* Host Controller command register set - per port */ enum { CQ = 0, CA = 8, CC = 0x10, CE = 0x18, DE = 0x20, CHBA = 0x24, HSTATUS = 0x28, HCONTROL = 0x2C, CQPMP = 0x30, SIGNATURE = 0x34, ICC = 0x38, /* * Host Status Register (HStatus) bitdefs */ ONLINE = (1 << 31), GOING_OFFLINE = (1 << 30), BIST_ERR = (1 << 29), |
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CLEAR_ERROR = (1 << 27), |
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FATAL_ERR_HC_MASTER_ERR = (1 << 18), FATAL_ERR_PARITY_ERR_TX = (1 << 17), FATAL_ERR_PARITY_ERR_RX = (1 << 16), FATAL_ERR_DATA_UNDERRUN = (1 << 13), FATAL_ERR_DATA_OVERRUN = (1 << 12), FATAL_ERR_CRC_ERR_TX = (1 << 11), FATAL_ERR_CRC_ERR_RX = (1 << 10), FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | FATAL_ERR_PARITY_ERR_TX | FATAL_ERR_PARITY_ERR_RX | FATAL_ERR_DATA_UNDERRUN | FATAL_ERR_DATA_OVERRUN | FATAL_ERR_CRC_ERR_TX | FATAL_ERR_CRC_ERR_RX | FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, |
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INT_ON_DATA_LENGTH_MISMATCH = (1 << 12), |
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INT_ON_FATAL_ERR = (1 << 5), INT_ON_PHYRDY_CHG = (1 << 4), INT_ON_SIGNATURE_UPDATE = (1 << 3), INT_ON_SNOTIFY_UPDATE = (1 << 2), INT_ON_SINGL_DEVICE_ERR = (1 << 1), INT_ON_CMD_COMPLETE = 1, |
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INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | |
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INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, /* * Host Control Register (HControl) bitdefs */ HCONTROL_ONLINE_PHY_RST = (1 << 31), HCONTROL_FORCE_OFFLINE = (1 << 30), |
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HCONTROL_LEGACY = (1 << 28), |
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HCONTROL_PARITY_PROT_MOD = (1 << 14), HCONTROL_DPATH_PARITY = (1 << 12), HCONTROL_SNOOP_ENABLE = (1 << 10), HCONTROL_PMP_ATTACHED = (1 << 9), HCONTROL_COPYOUT_STATFIS = (1 << 8), IE_ON_FATAL_ERR = (1 << 5), IE_ON_PHYRDY_CHG = (1 << 4), IE_ON_SIGNATURE_UPDATE = (1 << 3), IE_ON_SNOTIFY_UPDATE = (1 << 2), IE_ON_SINGL_DEVICE_ERR = (1 << 1), IE_ON_CMD_COMPLETE = 1, DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | |
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IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | |
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IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), |
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DATA_SNOOP_ENABLE_V1 = (1 << 22), DATA_SNOOP_ENABLE_V2 = (1 << 28), |
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}; /* * SATA Superset Registers */ enum { SSTATUS = 0, SERROR = 4, SCONTROL = 8, SNOTIFY = 0xC, }; /* * Control Status Register Set */ enum { TRANSCFG = 0, TRANSSTATUS = 4, LINKCFG = 8, LINKCFG1 = 0xC, LINKCFG2 = 0x10, LINKSTATUS = 0x14, LINKSTATUS1 = 0x18, PHYCTRLCFG = 0x1C, COMMANDSTAT = 0x20, }; |
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/* TRANSCFG (transport-layer) configuration control */ enum { TRANSCFG_RX_WATER_MARK = (1 << 4), }; |
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/* PHY (link-layer) configuration control */ enum { PHY_BIST_ENABLE = 0x01, }; /* * Command Header Table entry, i.e, command slot * 4 Dwords per command slot, command header size == 64 Dwords. */ struct cmdhdr_tbl_entry { u32 cda; u32 prde_fis_len; u32 ttl; u32 desc_info; }; /* * Description information bitdefs */ enum { |
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CMD_DESC_RES = (1 << 11), |
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VENDOR_SPECIFIC_BIST = (1 << 10), CMD_DESC_SNOOP_ENABLE = (1 << 9), FPDMA_QUEUED_CMD = (1 << 8), SRST_CMD = (1 << 7), BIST = (1 << 6), ATAPI_CMD = (1 << 5), }; /* * Command Descriptor */ struct command_desc { u8 cfis[8 * 4]; u8 sfis[8 * 4]; u8 acmd[4 * 4]; u8 fill[4 * 4]; u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; }; /* * Physical region table descriptor(PRD) */ struct prde { u32 dba; u8 fill[2 * 4]; u32 ddc_and_ext; }; /* * ata_port private data * This is our per-port instance data. */ struct sata_fsl_port_priv { struct cmdhdr_tbl_entry *cmdslot; dma_addr_t cmdslot_paddr; struct command_desc *cmdentry; dma_addr_t cmdentry_paddr; |
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}; /* * ata_port->host_set private data */ struct sata_fsl_host_priv { void __iomem *hcr_base; void __iomem *ssr_base; void __iomem *csr_base; |
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int irq; |
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int data_snoop; |
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struct device_attribute intr_coalescing; |
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struct device_attribute rx_watermark; |
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}; |
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static void fsl_sata_set_irq_coalescing(struct ata_host *host, unsigned int count, unsigned int ticks) { struct sata_fsl_host_priv *host_priv = host->private_data; void __iomem *hcr_base = host_priv->hcr_base; |
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unsigned long flags; |
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if (count > ICC_MAX_INT_COUNT_THRESHOLD) count = ICC_MAX_INT_COUNT_THRESHOLD; else if (count < ICC_MIN_INT_COUNT_THRESHOLD) count = ICC_MIN_INT_COUNT_THRESHOLD; if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) ticks = ICC_MAX_INT_TICKS_THRESHOLD; else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && (count > ICC_MIN_INT_COUNT_THRESHOLD)) ticks = ICC_SAFE_INT_TICKS; |
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spin_lock_irqsave(&host->lock, flags); |
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iowrite32((count << 24 | ticks), hcr_base + ICC); intr_coalescing_count = count; intr_coalescing_ticks = ticks; |
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spin_unlock_irqrestore(&host->lock, flags); |
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DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x ", |
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intr_coalescing_count, intr_coalescing_ticks); DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x ", hcr_base, ioread32(hcr_base + ICC)); } static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, struct device_attribute *attr, char *buf) { return sprintf(buf, "%d %d ", intr_coalescing_count, intr_coalescing_ticks); } static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { unsigned int coalescing_count, coalescing_ticks; if (sscanf(buf, "%d%d", &coalescing_count, &coalescing_ticks) != 2) { printk(KERN_ERR "fsl-sata: wrong parameter format. "); return -EINVAL; } fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), coalescing_count, coalescing_ticks); return strlen(buf); } |
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static ssize_t fsl_sata_rx_watermark_show(struct device *dev, struct device_attribute *attr, char *buf) { unsigned int rx_watermark; unsigned long flags; struct ata_host *host = dev_get_drvdata(dev); struct sata_fsl_host_priv *host_priv = host->private_data; void __iomem *csr_base = host_priv->csr_base; spin_lock_irqsave(&host->lock, flags); rx_watermark = ioread32(csr_base + TRANSCFG); rx_watermark &= 0x1f; spin_unlock_irqrestore(&host->lock, flags); return sprintf(buf, "%d ", rx_watermark); } static ssize_t fsl_sata_rx_watermark_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { unsigned int rx_watermark; unsigned long flags; struct ata_host *host = dev_get_drvdata(dev); struct sata_fsl_host_priv *host_priv = host->private_data; void __iomem *csr_base = host_priv->csr_base; u32 temp; if (sscanf(buf, "%d", &rx_watermark) != 1) { printk(KERN_ERR "fsl-sata: wrong parameter format. "); return -EINVAL; } spin_lock_irqsave(&host->lock, flags); temp = ioread32(csr_base + TRANSCFG); temp &= 0xffffffe0; iowrite32(temp | rx_watermark, csr_base + TRANSCFG); spin_unlock_irqrestore(&host->lock, flags); return strlen(buf); } |
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static inline unsigned int sata_fsl_tag(unsigned int tag, |
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void __iomem *hcr_base) |
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{ /* We let libATA core do actual (queue) tag allocation */ /* all non NCQ/queued commands should have tag#0 */ if (ata_tag_internal(tag)) { DPRINTK("mapping internal cmds to tag#0 "); return 0; } if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { DPRINTK("tag %d invalid : out of range ", tag); return 0; } if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { DPRINTK("tag %d invalid : in use!! ", tag); return 0; } return tag; } static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, unsigned int tag, u32 desc_info, u32 data_xfer_len, u8 num_prde, u8 fis_len) { dma_addr_t cmd_descriptor_address; cmd_descriptor_address = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; /* NOTE: both data_xfer_len & fis_len are Dword counts */ pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); pp->cmdslot[tag].prde_fis_len = cpu_to_le32((num_prde << 16) | (fis_len << 2)); pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); |
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pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); |
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VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x ", pp->cmdslot[tag].cda, pp->cmdslot[tag].prde_fis_len, pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); } static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, |
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u32 *ttl, dma_addr_t cmd_desc_paddr, int data_snoop) |
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{ struct scatterlist *sg; unsigned int num_prde = 0; u32 ttl_dwords = 0; /* |
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* NOTE : direct & indirect prdt's are contiguously allocated |
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*/ struct prde *prd = (struct prde *)&((struct command_desc *) cmd_desc)->prdt; struct prde *prd_ptr_to_indirect_ext = NULL; unsigned indirect_ext_segment_sz = 0; dma_addr_t indirect_ext_segment_paddr; |
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unsigned int si; |
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VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p ", cmd_desc, prd); |
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indirect_ext_segment_paddr = cmd_desc_paddr + SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; |
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for_each_sg(qc->sg, sg, qc->n_elem, si) { |
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dma_addr_t sg_addr = sg_dma_address(sg); u32 sg_len = sg_dma_len(sg); |
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VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d ", (unsigned long long)sg_addr, sg_len); |
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/* warn if each s/g element is not dword aligned */ |
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if (unlikely(sg_addr & 0x03)) |
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ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx ", (unsigned long long)sg_addr); |
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if (unlikely(sg_len & 0x03)) |
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ata_port_err(qc->ap, "s/g len unaligned : 0x%x ", sg_len); |
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if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && sg_next(sg) != NULL) { |
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VPRINTK("setting indirect prde "); prd_ptr_to_indirect_ext = prd; prd->dba = cpu_to_le32(indirect_ext_segment_paddr); indirect_ext_segment_sz = 0; ++prd; ++num_prde; } ttl_dwords += sg_len; prd->dba = cpu_to_le32(sg_addr); |
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prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); |
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VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x ", ttl_dwords, prd->dba, prd->ddc_and_ext); ++num_prde; ++prd; if (prd_ptr_to_indirect_ext) indirect_ext_segment_sz += sg_len; } if (prd_ptr_to_indirect_ext) { /* set indirect extension flag along with indirect ext. size */ prd_ptr_to_indirect_ext->ddc_and_ext = cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | |
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data_snoop | |
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(indirect_ext_segment_sz & ~0x03))); } *ttl = ttl_dwords; return num_prde; } static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct sata_fsl_port_priv *pp = ap->private_data; struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); struct command_desc *cd; |
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u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; |
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u32 num_prde = 0; u32 ttl_dwords = 0; dma_addr_t cd_paddr; cd = (struct command_desc *)pp->cmdentry + tag; cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; |
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ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); |
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VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x ", cd->cfis[0], cd->cfis[1], cd->cfis[2]); if (qc->tf.protocol == ATA_PROT_NCQ) { VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d ", cd->cfis[3], cd->cfis[11]); } /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ |
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if (ata_is_atapi(qc->tf.protocol)) { |
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desc_info |= ATAPI_CMD; memset((void *)&cd->acmd, 0, 32); memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); } if (qc->flags & ATA_QCFLAG_DMAMAP) num_prde = sata_fsl_fill_sg(qc, (void *)cd, |
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&ttl_dwords, cd_paddr, host_priv->data_snoop); |
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if (qc->tf.protocol == ATA_PROT_NCQ) desc_info |= FPDMA_QUEUED_CMD; sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, num_prde, 5); VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d ", desc_info, ttl_dwords, num_prde); } static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x ", ioread32(CQ + hcr_base), ioread32(CA + hcr_base), ioread32(CE + hcr_base), ioread32(CC + hcr_base)); |
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iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); |
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583 584 585 586 587 588 589 590 591 592 593 |
/* Simply queue command to the controller/device */ iowrite32(1 << tag, CQ + hcr_base); VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x ", tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x ", ioread32(CE + hcr_base), ioread32(DE + hcr_base), |
b1f5dc48e
|
594 595 |
ioread32(CC + hcr_base), ioread32(COMMANDSTAT + host_priv->csr_base)); |
faf0b2e5a
|
596 597 598 |
return 0; } |
4c9bf4e79
|
599 600 601 602 603 604 605 606 607 608 609 610 611 |
static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) { struct sata_fsl_port_priv *pp = qc->ap->private_data; struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); struct command_desc *cd; cd = pp->cmdentry + tag; ata_tf_from_fis(cd->sfis, &qc->result_tf); return true; } |
82ef04fb4
|
612 613 |
static int sata_fsl_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
faf0b2e5a
|
614 |
{ |
82ef04fb4
|
615 |
struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; |
faf0b2e5a
|
616 617 618 619 620 |
void __iomem *ssr_base = host_priv->ssr_base; unsigned int sc_reg; switch (sc_reg_in) { case SCR_STATUS: |
faf0b2e5a
|
621 |
case SCR_ERROR: |
faf0b2e5a
|
622 |
case SCR_CONTROL: |
faf0b2e5a
|
623 |
case SCR_ACTIVE: |
9465d5324
|
624 |
sc_reg = sc_reg_in; |
faf0b2e5a
|
625 626 627 628 629 630 631 |
break; default: return -EINVAL; } VPRINTK("xx_scr_write, reg_in = %d ", sc_reg); |
2a52e8d4e
|
632 |
iowrite32(val, ssr_base + (sc_reg * 4)); |
faf0b2e5a
|
633 634 |
return 0; } |
82ef04fb4
|
635 636 |
static int sata_fsl_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
faf0b2e5a
|
637 |
{ |
82ef04fb4
|
638 |
struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; |
faf0b2e5a
|
639 640 641 642 643 |
void __iomem *ssr_base = host_priv->ssr_base; unsigned int sc_reg; switch (sc_reg_in) { case SCR_STATUS: |
faf0b2e5a
|
644 |
case SCR_ERROR: |
faf0b2e5a
|
645 |
case SCR_CONTROL: |
faf0b2e5a
|
646 |
case SCR_ACTIVE: |
9465d5324
|
647 |
sc_reg = sc_reg_in; |
faf0b2e5a
|
648 649 650 651 652 653 654 |
break; default: return -EINVAL; } VPRINTK("xx_scr_read, reg_in = %d ", sc_reg); |
2a52e8d4e
|
655 |
*val = ioread32(ssr_base + (sc_reg * 4)); |
faf0b2e5a
|
656 657 658 659 660 661 662 663 664 665 666 667 668 669 |
return 0; } static void sata_fsl_freeze(struct ata_port *ap) { struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x ", ioread32(CQ + hcr_base), ioread32(CA + hcr_base), ioread32(CE + hcr_base), ioread32(DE + hcr_base)); |
b1f5dc48e
|
670 671 672 |
VPRINTK("CmdStat = 0x%x ", ioread32(host_priv->csr_base + COMMANDSTAT)); |
faf0b2e5a
|
673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 |
/* disable interrupts on the controller/port */ temp = ioread32(hcr_base + HCONTROL); iowrite32((temp & ~0x3F), hcr_base + HCONTROL); VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x ", ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); } static void sata_fsl_thaw(struct ata_port *ap) { struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; /* ack. any pending IRQs for this controller/port */ temp = ioread32(hcr_base + HSTATUS); VPRINTK("xx_thaw, pending IRQs = 0x%x ", (temp & 0x3F)); if (temp & 0x3F) iowrite32((temp & 0x3F), hcr_base + HSTATUS); /* enable interrupts on the controller/port */ temp = ioread32(hcr_base + HCONTROL); iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x ", ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); } |
034d8e8f2
|
706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 |
static void sata_fsl_pmp_attach(struct ata_port *ap) { struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; temp = ioread32(hcr_base + HCONTROL); iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); } static void sata_fsl_pmp_detach(struct ata_port *ap) { struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; temp = ioread32(hcr_base + HCONTROL); temp &= ~HCONTROL_PMP_ATTACHED; iowrite32(temp, hcr_base + HCONTROL); /* enable interrupts on the controller/port */ temp = ioread32(hcr_base + HCONTROL); iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); } |
faf0b2e5a
|
731 732 733 734 |
static int sata_fsl_port_start(struct ata_port *ap) { struct device *dev = ap->host->dev; struct sata_fsl_port_priv *pp; |
faf0b2e5a
|
735 736 737 738 739 740 741 742 743 |
void *mem; dma_addr_t mem_dma; struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; pp = kzalloc(sizeof(*pp), GFP_KERNEL); if (!pp) return -ENOMEM; |
94463a9ca
|
744 745 |
mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); |
faf0b2e5a
|
746 |
if (!mem) { |
faf0b2e5a
|
747 748 749 |
kfree(pp); return -ENOMEM; } |
faf0b2e5a
|
750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 |
pp->cmdslot = mem; pp->cmdslot_paddr = mem_dma; mem += SATA_FSL_CMD_SLOT_SIZE; mem_dma += SATA_FSL_CMD_SLOT_SIZE; pp->cmdentry = mem; pp->cmdentry_paddr = mem_dma; ap->private_data = pp; VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x ", pp->cmdslot_paddr, pp->cmdentry_paddr); /* Now, update the CHBA register in host controller cmd register set */ iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); /* * Now, we can bring the controller on-line & also initiate * the COMINIT sequence, we simply return here and the boot-probing * & device discovery process is re-initiated by libATA using a * Softreset EH (dummy) session. Hence, boot probing and device * discovey will be part of sata_fsl_softreset() callback. */ temp = ioread32(hcr_base + HCONTROL); iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); VPRINTK("HStatus = 0x%x ", ioread32(hcr_base + HSTATUS)); VPRINTK("HControl = 0x%x ", ioread32(hcr_base + HCONTROL)); VPRINTK("CHBA = 0x%x ", ioread32(hcr_base + CHBA)); |
faf0b2e5a
|
786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 |
return 0; } static void sata_fsl_port_stop(struct ata_port *ap) { struct device *dev = ap->host->dev; struct sata_fsl_port_priv *pp = ap->private_data; struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; /* * Force host controller to go off-line, aborting current operations */ temp = ioread32(hcr_base + HCONTROL); temp &= ~HCONTROL_ONLINE_PHY_RST; temp |= HCONTROL_FORCE_OFFLINE; iowrite32(temp, hcr_base + HCONTROL); /* Poll for controller to go offline - should happen immediately */ |
97750cebb
|
806 |
ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); |
faf0b2e5a
|
807 808 809 810 |
ap->private_data = NULL; dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, pp->cmdslot, pp->cmdslot_paddr); |
faf0b2e5a
|
811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 |
kfree(pp); } static unsigned int sata_fsl_dev_classify(struct ata_port *ap) { struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; struct ata_taskfile tf; u32 temp; temp = ioread32(hcr_base + SIGNATURE); VPRINTK("raw sig = 0x%x ", temp); VPRINTK("HStatus = 0x%x ", ioread32(hcr_base + HSTATUS)); VPRINTK("HControl = 0x%x ", ioread32(hcr_base + HCONTROL)); tf.lbah = (temp >> 24) & 0xff; tf.lbam = (temp >> 16) & 0xff; tf.lbal = (temp >> 8) & 0xff; tf.nsect = temp & 0xff; return ata_dev_classify(&tf); } |
a0a74d1ee
|
837 |
static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, |
034d8e8f2
|
838 |
unsigned long deadline) |
faf0b2e5a
|
839 |
{ |
1bf617b71
|
840 |
struct ata_port *ap = link->ap; |
faf0b2e5a
|
841 842 843 |
struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; |
faf0b2e5a
|
844 |
int i = 0; |
faf0b2e5a
|
845 |
unsigned long start_jiffies; |
a0a74d1ee
|
846 847 |
DPRINTK("in xx_hardreset "); |
034d8e8f2
|
848 |
|
faf0b2e5a
|
849 850 851 852 853 854 855 856 857 |
try_offline_again: /* * Force host controller to go off-line, aborting current operations */ temp = ioread32(hcr_base + HCONTROL); temp &= ~HCONTROL_ONLINE_PHY_RST; iowrite32(temp, hcr_base + HCONTROL); /* Poll for controller to go offline */ |
97750cebb
|
858 859 |
temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500); |
faf0b2e5a
|
860 861 |
if (temp & ONLINE) { |
a9a79dfec
|
862 863 |
ata_port_err(ap, "Hardreset failed, not off-lined %d ", i); |
faf0b2e5a
|
864 865 866 867 868 869 870 871 872 873 |
/* * Try to offline controller atleast twice */ i++; if (i == 2) goto err; else goto try_offline_again; } |
a0a74d1ee
|
874 875 |
DPRINTK("hardreset, controller off-lined "); |
faf0b2e5a
|
876 877 878 879 880 881 882 883 |
VPRINTK("HStatus = 0x%x ", ioread32(hcr_base + HSTATUS)); VPRINTK("HControl = 0x%x ", ioread32(hcr_base + HCONTROL)); /* * PHY reset should remain asserted for atleast 1ms */ |
97750cebb
|
884 |
ata_msleep(ap, 1); |
faf0b2e5a
|
885 |
|
29200f12a
|
886 |
sata_set_spd(link); |
faf0b2e5a
|
887 888 889 890 891 892 893 894 895 |
/* * Now, bring the host controller online again, this can take time * as PHY reset and communication establishment, 1st D2H FIS and * device signature update is done, on safe side assume 500ms * NOTE : Host online status may be indicated immediately!! */ temp = ioread32(hcr_base + HCONTROL); temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); |
034d8e8f2
|
896 |
temp |= HCONTROL_PMP_ATTACHED; |
faf0b2e5a
|
897 |
iowrite32(temp, hcr_base + HCONTROL); |
97750cebb
|
898 |
temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); |
faf0b2e5a
|
899 900 |
if (!(temp & ONLINE)) { |
a9a79dfec
|
901 902 |
ata_port_err(ap, "Hardreset failed, not on-lined "); |
faf0b2e5a
|
903 904 |
goto err; } |
a0a74d1ee
|
905 906 |
DPRINTK("hardreset, controller off-lined & on-lined "); |
faf0b2e5a
|
907 908 909 910 911 912 913 914 915 916 |
VPRINTK("HStatus = 0x%x ", ioread32(hcr_base + HSTATUS)); VPRINTK("HControl = 0x%x ", ioread32(hcr_base + HCONTROL)); /* * First, wait for the PHYRDY change to occur before waiting for * the signature, and also verify if SStatus indicates device * presence */ |
97750cebb
|
917 |
temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); |
1bf617b71
|
918 |
if ((!(temp & 0x10)) || ata_link_offline(link)) { |
a9a79dfec
|
919 920 921 |
ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x ", ioread32(hcr_base + HSTATUS)); |
034d8e8f2
|
922 |
*class = ATA_DEV_NONE; |
a0a74d1ee
|
923 |
return 0; |
faf0b2e5a
|
924 925 926 927 928 929 |
} /* * Wait for the first D2H from device,i.e,signature update notification */ start_jiffies = jiffies; |
97750cebb
|
930 |
temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, |
faf0b2e5a
|
931 932 933 |
500, jiffies_to_msecs(deadline - start_jiffies)); if ((temp & 0xFF) != 0x18) { |
a9a79dfec
|
934 935 |
ata_port_warn(ap, "No Signature Update "); |
034d8e8f2
|
936 |
*class = ATA_DEV_NONE; |
a0a74d1ee
|
937 |
goto do_followup_srst; |
faf0b2e5a
|
938 |
} else { |
a9a79dfec
|
939 940 941 |
ata_port_info(ap, "Signature Update detected @ %d msecs ", jiffies_to_msecs(jiffies - start_jiffies)); |
a0a74d1ee
|
942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 |
*class = sata_fsl_dev_classify(ap); return 0; } do_followup_srst: /* * request libATA to perform follow-up softreset */ return -EAGAIN; err: return -EIO; } static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { struct ata_port *ap = link->ap; struct sata_fsl_port_priv *pp = ap->private_data; struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; int pmp = sata_srst_pmp(link); u32 temp; struct ata_taskfile tf; u8 *cfis; u32 Serror; DPRINTK("in xx_softreset "); if (ata_link_offline(link)) { DPRINTK("PHY reports no device "); *class = ATA_DEV_NONE; return 0; |
faf0b2e5a
|
977 978 979 980 981 982 983 984 985 |
} /* * Send a device reset (SRST) explicitly on command slot #0 * Check : will the command queue (reg) be cleared during offlining ?? * Also we will be online only if Phy commn. has been established * and device presence has been detected, therefore if we have * reached here, we can send a command to the target device */ |
faf0b2e5a
|
986 987 |
DPRINTK("Sending SRST/device reset "); |
1bf617b71
|
988 |
ata_tf_init(link->device, &tf); |
520d3a1a8
|
989 |
cfis = (u8 *) &pp->cmdentry->cfis; |
faf0b2e5a
|
990 991 992 |
/* device reset/SRST is a control register update FIS, uses tag0 */ sata_fsl_setup_cmd_hdr_entry(pp, 0, |
d35872438
|
993 |
SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); |
faf0b2e5a
|
994 995 |
tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ |
034d8e8f2
|
996 |
ata_tf_to_fis(&tf, pmp, 0, cfis); |
faf0b2e5a
|
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 |
DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x ", cfis[0], cfis[1], cfis[2], cfis[3]); /* * Queue SRST command to the controller/device, ensure that no * other commands are active on the controller/device */ DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x ", ioread32(CQ + hcr_base), ioread32(CA + hcr_base), ioread32(CC + hcr_base)); iowrite32(0xFFFF, CC + hcr_base); |
a0a74d1ee
|
1013 1014 |
if (pmp != SATA_PMP_CTRL_PORT) iowrite32(pmp, CQPMP + hcr_base); |
faf0b2e5a
|
1015 |
iowrite32(1, CQ + hcr_base); |
97750cebb
|
1016 |
temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); |
faf0b2e5a
|
1017 |
if (temp & 0x1) { |
a9a79dfec
|
1018 1019 |
ata_port_warn(ap, "ATA_SRST issue failed "); |
faf0b2e5a
|
1020 1021 1022 1023 1024 |
DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x ", ioread32(CQ + hcr_base), ioread32(CA + hcr_base), ioread32(CC + hcr_base)); |
82ef04fb4
|
1025 |
sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); |
faf0b2e5a
|
1026 1027 1028 1029 1030 1031 1032 1033 1034 |
DPRINTK("HStatus = 0x%x ", ioread32(hcr_base + HSTATUS)); DPRINTK("HControl = 0x%x ", ioread32(hcr_base + HCONTROL)); DPRINTK("Serror = 0x%x ", Serror); goto err; } |
97750cebb
|
1035 |
ata_msleep(ap, 1); |
faf0b2e5a
|
1036 1037 |
/* |
25985edce
|
1038 |
* SATA device enters reset state after receiving a Control register |
faf0b2e5a
|
1039 1040 1041 1042 1043 |
* FIS with SRST bit asserted and it awaits another H2D Control reg. * FIS with SRST bit cleared, then the device does internal diags & * initialization, followed by indicating it's initialization status * using ATA signature D2H register FIS to the host controller. */ |
d35872438
|
1044 1045 |
sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); |
faf0b2e5a
|
1046 1047 |
tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ |
034d8e8f2
|
1048 |
ata_tf_to_fis(&tf, pmp, 0, cfis); |
faf0b2e5a
|
1049 |
|
034d8e8f2
|
1050 1051 |
if (pmp != SATA_PMP_CTRL_PORT) iowrite32(pmp, CQPMP + hcr_base); |
faf0b2e5a
|
1052 |
iowrite32(1, CQ + hcr_base); |
97750cebb
|
1053 |
ata_msleep(ap, 150); /* ?? */ |
faf0b2e5a
|
1054 1055 1056 1057 1058 1059 1060 |
/* * The above command would have signalled an interrupt on command * complete, which needs special handling, by clearing the Nth * command bit of the CCreg */ iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ |
faf0b2e5a
|
1061 1062 1063 1064 1065 1066 1067 |
DPRINTK("SATA FSL : Now checking device signature "); *class = ATA_DEV_NONE; /* Verify if SStatus indicates device presence */ |
1bf617b71
|
1068 |
if (ata_link_online(link)) { |
faf0b2e5a
|
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 |
/* * if we are here, device presence has been detected, * 1st D2H FIS would have been received, but sfis in * command desc. is not updated, but signature register * would have been updated */ *class = sata_fsl_dev_classify(ap); DPRINTK("class = %d ", *class); VPRINTK("ccreg = 0x%x ", ioread32(hcr_base + CC)); VPRINTK("cereg = 0x%x ", ioread32(hcr_base + CE)); } return 0; err: return -EIO; } |
034d8e8f2
|
1091 1092 1093 1094 1095 1096 1097 1098 |
static void sata_fsl_error_handler(struct ata_port *ap) { DPRINTK("in xx_error_handler "); sata_pmp_error_handler(ap); } |
faf0b2e5a
|
1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 |
static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) { if (qc->flags & ATA_QCFLAG_FAILED) qc->err_mask |= AC_ERR_OTHER; if (qc->err_mask) { /* make DMA engine forget about the failed command */ } } |
faf0b2e5a
|
1109 1110 |
static void sata_fsl_error_intr(struct ata_port *ap) { |
faf0b2e5a
|
1111 1112 |
struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; |
034d8e8f2
|
1113 |
u32 hstatus, dereg=0, cereg = 0, SError = 0; |
faf0b2e5a
|
1114 |
unsigned int err_mask = 0, action = 0; |
034d8e8f2
|
1115 1116 1117 1118 |
int freeze = 0, abort=0; struct ata_link *link = NULL; struct ata_queued_cmd *qc = NULL; struct ata_eh_info *ehi; |
faf0b2e5a
|
1119 1120 1121 |
hstatus = ioread32(hcr_base + HSTATUS); cereg = ioread32(hcr_base + CE); |
034d8e8f2
|
1122 1123 1124 |
/* first, analyze and record host port events */ link = &ap->link; ehi = &link->eh_info; |
faf0b2e5a
|
1125 1126 1127 1128 1129 |
ata_ehi_clear_desc(ehi); /* * Handle & Clear SError */ |
82ef04fb4
|
1130 |
sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); |
fd6c29e3d
|
1131 |
if (unlikely(SError & 0xFFFF0000)) |
82ef04fb4
|
1132 |
sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); |
faf0b2e5a
|
1133 1134 1135 1136 |
DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x ", hstatus, cereg, ioread32(hcr_base + DE), SError); |
034d8e8f2
|
1137 1138 1139 1140 |
/* handle fatal errors */ if (hstatus & FATAL_ERROR_DECODE) { ehi->err_mask |= AC_ERR_ATA_BUS; ehi->action |= ATA_EH_SOFTRESET; |
faf0b2e5a
|
1141 |
|
faf0b2e5a
|
1142 1143 |
freeze = 1; } |
fd6c29e3d
|
1144 1145 1146 |
/* Handle SDB FIS receive & notify update */ if (hstatus & INT_ON_SNOTIFY_UPDATE) sata_async_notification(ap); |
faf0b2e5a
|
1147 1148 1149 1150 1151 1152 1153 |
/* Handle PHYRDY change notification */ if (hstatus & INT_ON_PHYRDY_CHG) { DPRINTK("SATA FSL: PHYRDY change indication "); /* Setup a soft-reset EH action */ ata_ehi_hotplugged(ehi); |
034d8e8f2
|
1154 |
ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); |
faf0b2e5a
|
1155 1156 |
freeze = 1; } |
034d8e8f2
|
1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 |
/* handle single device errors */ if (cereg) { /* * clear the command error, also clears queue to the device * in error, and we can (re)issue commands to this device. * When a device is in error all commands queued into the * host controller and at the device are considered aborted * and the queue for that device is stopped. Now, after * clearing the device error, we can issue commands to the * device to interrogate it to find the source of the error. */ abort = 1; DPRINTK("single device error, CE=0x%x, DE=0x%x ", ioread32(hcr_base + CE), ioread32(hcr_base + DE)); |
faf0b2e5a
|
1173 |
|
034d8e8f2
|
1174 1175 |
/* find out the offending link and qc */ if (ap->nr_pmp_links) { |
4ac7534a7
|
1176 |
unsigned int dev_num; |
034d8e8f2
|
1177 1178 1179 |
dereg = ioread32(hcr_base + DE); iowrite32(dereg, hcr_base + DE); iowrite32(cereg, hcr_base + CE); |
4ac7534a7
|
1180 1181 1182 |
dev_num = ffs(dereg) - 1; if (dev_num < ap->nr_pmp_links && dereg != 0) { link = &ap->pmp_link[dev_num]; |
034d8e8f2
|
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 |
ehi = &link->eh_info; qc = ata_qc_from_tag(ap, link->active_tag); /* * We should consider this as non fatal error, * and TF must be updated as done below. */ err_mask |= AC_ERR_DEV; } else { err_mask |= AC_ERR_HSM; action |= ATA_EH_HARDRESET; freeze = 1; } } else { dereg = ioread32(hcr_base + DE); iowrite32(dereg, hcr_base + DE); iowrite32(cereg, hcr_base + CE); qc = ata_qc_from_tag(ap, link->active_tag); /* * We should consider this as non fatal error, * and TF must be updated as done below. */ err_mask |= AC_ERR_DEV; } } /* record error info */ |
fd6c29e3d
|
1212 |
if (qc) |
faf0b2e5a
|
1213 |
qc->err_mask |= err_mask; |
fd6c29e3d
|
1214 |
else |
faf0b2e5a
|
1215 1216 1217 |
ehi->err_mask |= err_mask; ehi->action |= action; |
faf0b2e5a
|
1218 1219 1220 1221 |
/* freeze or abort */ if (freeze) ata_port_freeze(ap); |
034d8e8f2
|
1222 1223 1224 1225 1226 1227 |
else if (abort) { if (qc) ata_link_abort(qc->dev->link); else ata_port_abort(ap); } |
faf0b2e5a
|
1228 |
} |
faf0b2e5a
|
1229 1230 1231 1232 |
static void sata_fsl_host_intr(struct ata_port *ap) { struct sata_fsl_host_priv *host_priv = ap->host->private_data; void __iomem *hcr_base = host_priv->hcr_base; |
752e386c2
|
1233 |
u32 hstatus, done_mask = 0; |
faf0b2e5a
|
1234 1235 |
struct ata_queued_cmd *qc; u32 SError; |
100f586bd
|
1236 1237 |
u32 tag; u32 status_mask = INT_ON_ERROR; |
faf0b2e5a
|
1238 1239 |
hstatus = ioread32(hcr_base + HSTATUS); |
82ef04fb4
|
1240 |
sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); |
faf0b2e5a
|
1241 |
|
100f586bd
|
1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 |
/* Read command completed register */ done_mask = ioread32(hcr_base + CC); /* Workaround for data length mismatch errata */ if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) { for (tag = 0; tag < ATA_MAX_QUEUE; tag++) { qc = ata_qc_from_tag(ap, tag); if (qc && ata_is_atapi(qc->tf.protocol)) { u32 hcontrol; /* Set HControl[27] to clear error registers */ hcontrol = ioread32(hcr_base + HCONTROL); iowrite32(hcontrol | CLEAR_ERROR, hcr_base + HCONTROL); /* Clear HControl[27] */ iowrite32(hcontrol & ~CLEAR_ERROR, hcr_base + HCONTROL); /* Clear SError[E] bit */ sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); /* Ignore fatal error and device error */ status_mask &= ~(INT_ON_SINGL_DEVICE_ERR | INT_ON_FATAL_ERR); break; } } } |
faf0b2e5a
|
1271 1272 1273 1274 |
if (unlikely(SError & 0xFFFF0000)) { DPRINTK("serror @host_intr : 0x%x ", SError); sata_fsl_error_intr(ap); |
faf0b2e5a
|
1275 |
} |
100f586bd
|
1276 |
if (unlikely(hstatus & status_mask)) { |
faf0b2e5a
|
1277 1278 1279 1280 1281 |
DPRINTK("error interrupt!! "); sata_fsl_error_intr(ap); return; } |
034d8e8f2
|
1282 1283 |
VPRINTK("Status of all queues : "); |
752e386c2
|
1284 1285 1286 |
VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x ", done_mask, |
034d8e8f2
|
1287 1288 1289 1290 |
ioread32(hcr_base + CA), ioread32(hcr_base + CE), ioread32(hcr_base + CQ), ap->qc_active); |
752e386c2
|
1291 |
if (done_mask & ap->qc_active) { |
faf0b2e5a
|
1292 |
int i; |
faf0b2e5a
|
1293 |
/* clear CC bit, this will also complete the interrupt */ |
752e386c2
|
1294 |
iowrite32(done_mask, hcr_base + CC); |
faf0b2e5a
|
1295 1296 1297 |
DPRINTK("Status of all queues : "); |
752e386c2
|
1298 1299 1300 |
DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x ", done_mask, ioread32(hcr_base + CA), |
faf0b2e5a
|
1301 1302 1303 |
ioread32(hcr_base + CE)); for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { |
1aadf5c3b
|
1304 |
if (done_mask & (1 << i)) |
faf0b2e5a
|
1305 1306 1307 1308 1309 |
DPRINTK ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x ", i, ioread32(hcr_base + CC), ioread32(hcr_base + CA)); |
faf0b2e5a
|
1310 |
} |
1aadf5c3b
|
1311 |
ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); |
faf0b2e5a
|
1312 |
return; |
034d8e8f2
|
1313 |
} else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { |
faf0b2e5a
|
1314 |
iowrite32(1, hcr_base + CC); |
034d8e8f2
|
1315 |
qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); |
faf0b2e5a
|
1316 |
|
034d8e8f2
|
1317 1318 1319 |
DPRINTK("completing non-ncq cmd, CC=0x%x ", ioread32(hcr_base + CC)); |
faf0b2e5a
|
1320 |
|
034d8e8f2
|
1321 |
if (qc) { |
faf0b2e5a
|
1322 |
ata_qc_complete(qc); |
034d8e8f2
|
1323 |
} |
faf0b2e5a
|
1324 1325 1326 1327 1328 |
} else { /* Spurious Interrupt!! */ DPRINTK("spurious interrupt!!, CC = 0x%x ", ioread32(hcr_base + CC)); |
752e386c2
|
1329 |
iowrite32(done_mask, hcr_base + CC); |
faf0b2e5a
|
1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 |
return; } } static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) { struct ata_host *host = dev_instance; struct sata_fsl_host_priv *host_priv = host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 interrupt_enables; unsigned handled = 0; struct ata_port *ap; /* ack. any pending IRQs for this controller/port */ interrupt_enables = ioread32(hcr_base + HSTATUS); interrupt_enables &= 0x3F; DPRINTK("interrupt status 0x%x ", interrupt_enables); if (!interrupt_enables) return IRQ_NONE; spin_lock(&host->lock); /* Assuming one port per host controller */ ap = host->ports[0]; if (ap) { sata_fsl_host_intr(ap); } else { |
a44fec1fc
|
1361 1362 |
dev_warn(host->dev, "interrupt on disabled port 0 "); |
faf0b2e5a
|
1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 |
} iowrite32(interrupt_enables, hcr_base + HSTATUS); handled = 1; spin_unlock(&host->lock); return IRQ_RETVAL(handled); } /* * Multiple ports are represented by multiple SATA controllers with * one port per controller */ static int sata_fsl_init_controller(struct ata_host *host) { struct sata_fsl_host_priv *host_priv = host->private_data; void __iomem *hcr_base = host_priv->hcr_base; u32 temp; /* * NOTE : We cannot bring the controller online before setting * the CHBA, hence main controller initialization is done as * part of the port_start() callback */ |
93272b132
|
1388 1389 1390 |
/* sata controller to operate in enterprise mode */ temp = ioread32(hcr_base + HCONTROL); iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); |
faf0b2e5a
|
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 |
/* ack. any pending IRQs for this controller/port */ temp = ioread32(hcr_base + HSTATUS); if (temp & 0x3F) iowrite32((temp & 0x3F), hcr_base + HSTATUS); /* Keep interrupts disabled on the controller */ temp = ioread32(hcr_base + HCONTROL); iowrite32((temp & ~0x3F), hcr_base + HCONTROL); /* Disable interrupt coalescing control(icc), for the moment */ DPRINTK("icc = 0x%x ", ioread32(hcr_base + ICC)); iowrite32(0x01000000, hcr_base + ICC); /* clear error registers, SError is cleared by libATA */ iowrite32(0x00000FFFF, hcr_base + CE); iowrite32(0x00000FFFF, hcr_base + DE); |
6b4b8fc87
|
1408 1409 1410 1411 1412 1413 |
/* * reset the number of command complete bits which will cause the * interrupt to be signaled */ fsl_sata_set_irq_coalescing(host, intr_coalescing_count, intr_coalescing_ticks); |
faf0b2e5a
|
1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 |
/* * host controller will be brought on-line, during xx_port_start() * callback, that should also initiate the OOB, COMINIT sequence */ DPRINTK("HStatus = 0x%x ", ioread32(hcr_base + HSTATUS)); DPRINTK("HControl = 0x%x ", ioread32(hcr_base + HCONTROL)); return 0; } /* * scsi mid-layer and libata interface structures */ static struct scsi_host_template sata_fsl_sht = { |
68d1d07b5
|
1431 |
ATA_NCQ_SHT("sata_fsl"), |
faf0b2e5a
|
1432 |
.can_queue = SATA_FSL_QUEUE_DEPTH, |
faf0b2e5a
|
1433 |
.sg_tablesize = SATA_FSL_MAX_PRD_USABLE, |
faf0b2e5a
|
1434 |
.dma_boundary = ATA_DMA_BOUNDARY, |
faf0b2e5a
|
1435 |
}; |
034d8e8f2
|
1436 1437 |
static struct ata_port_operations sata_fsl_ops = { .inherits = &sata_pmp_port_ops, |
029cfd6b7
|
1438 |
|
f90f613c3
|
1439 |
.qc_defer = ata_std_qc_defer, |
faf0b2e5a
|
1440 1441 |
.qc_prep = sata_fsl_qc_prep, .qc_issue = sata_fsl_qc_issue, |
4c9bf4e79
|
1442 |
.qc_fill_rtf = sata_fsl_qc_fill_rtf, |
faf0b2e5a
|
1443 1444 1445 1446 1447 1448 |
.scr_read = sata_fsl_scr_read, .scr_write = sata_fsl_scr_write, .freeze = sata_fsl_freeze, .thaw = sata_fsl_thaw, |
a1efdaba2
|
1449 |
.softreset = sata_fsl_softreset, |
a0a74d1ee
|
1450 |
.hardreset = sata_fsl_hardreset, |
034d8e8f2
|
1451 1452 |
.pmp_softreset = sata_fsl_softreset, .error_handler = sata_fsl_error_handler, |
faf0b2e5a
|
1453 1454 1455 1456 |
.post_internal_cmd = sata_fsl_post_internal_cmd, .port_start = sata_fsl_port_start, .port_stop = sata_fsl_port_stop, |
034d8e8f2
|
1457 1458 1459 |
.pmp_attach = sata_fsl_pmp_attach, .pmp_detach = sata_fsl_pmp_detach, |
faf0b2e5a
|
1460 1461 1462 1463 1464 |
}; static const struct ata_port_info sata_fsl_port_info[] = { { .flags = SATA_FSL_HOST_FLAGS, |
14bdef982
|
1465 1466 |
.pio_mask = ATA_PIO4, .udma_mask = ATA_UDMA6, |
faf0b2e5a
|
1467 1468 1469 |
.port_ops = &sata_fsl_ops, }, }; |
1c48a5c93
|
1470 |
static int sata_fsl_probe(struct platform_device *ofdev) |
faf0b2e5a
|
1471 |
{ |
e4ac522bd
|
1472 |
int retval = -ENXIO; |
faf0b2e5a
|
1473 1474 1475 1476 |
void __iomem *hcr_base = NULL; void __iomem *ssr_base = NULL; void __iomem *csr_base = NULL; struct sata_fsl_host_priv *host_priv = NULL; |
faf0b2e5a
|
1477 |
int irq; |
6b4b8fc87
|
1478 |
struct ata_host *host = NULL; |
578ca87c9
|
1479 |
u32 temp; |
faf0b2e5a
|
1480 1481 1482 |
struct ata_port_info pi = sata_fsl_port_info[0]; const struct ata_port_info *ppi[] = { &pi, NULL }; |
a44fec1fc
|
1483 1484 |
dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init "); |
faf0b2e5a
|
1485 |
|
61c7a080a
|
1486 |
hcr_base = of_iomap(ofdev->dev.of_node, 0); |
faf0b2e5a
|
1487 1488 1489 1490 1491 |
if (!hcr_base) goto error_exit_with_cleanup; ssr_base = hcr_base + 0x100; csr_base = hcr_base + 0x140; |
578ca87c9
|
1492 1493 1494 1495 1496 |
if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { temp = ioread32(csr_base + TRANSCFG); temp = temp & 0xffffffe0; iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); } |
faf0b2e5a
|
1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 |
DPRINTK("@reset i/o = 0x%x ", ioread32(csr_base + TRANSCFG)); DPRINTK("sizeof(cmd_desc) = %d ", sizeof(struct command_desc)); DPRINTK("sizeof(#define cmd_desc) = %d ", SATA_FSL_CMD_DESC_SIZE); host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); if (!host_priv) goto error_exit_with_cleanup; host_priv->hcr_base = hcr_base; host_priv->ssr_base = ssr_base; host_priv->csr_base = csr_base; |
61c7a080a
|
1511 |
irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); |
aad0b6241
|
1512 |
if (!irq) { |
a44fec1fc
|
1513 1514 |
dev_err(&ofdev->dev, "invalid irq from platform "); |
faf0b2e5a
|
1515 1516 |
goto error_exit_with_cleanup; } |
79b3edc97
|
1517 |
host_priv->irq = irq; |
faf0b2e5a
|
1518 |
|
2f957fc95
|
1519 1520 1521 1522 |
if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; else host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; |
faf0b2e5a
|
1523 1524 |
/* allocate host structure */ host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); |
6b4b8fc87
|
1525 1526 1527 1528 |
if (!host) { retval = -ENOMEM; goto error_exit_with_cleanup; } |
faf0b2e5a
|
1529 1530 1531 |
/* host->iomap is not used currently */ host->private_data = host_priv; |
faf0b2e5a
|
1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 |
/* initialize host controller */ sata_fsl_init_controller(host); /* * Now, register with libATA core, this will also initiate the * device discovery process, invoking our port_start() handler & * error_handler() to execute a dummy Softreset EH session */ ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, &sata_fsl_sht); |
6b4b8fc87
|
1542 1543 1544 1545 1546 1547 1548 1549 |
host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; sysfs_attr_init(&host_priv->intr_coalescing.attr); host_priv->intr_coalescing.attr.name = "intr_coalescing"; host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; retval = device_create_file(host->dev, &host_priv->intr_coalescing); if (retval) goto error_exit_with_cleanup; |
7551c40d9
|
1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 |
host_priv->rx_watermark.show = fsl_sata_rx_watermark_show; host_priv->rx_watermark.store = fsl_sata_rx_watermark_store; sysfs_attr_init(&host_priv->rx_watermark.attr); host_priv->rx_watermark.attr.name = "rx_watermark"; host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR; retval = device_create_file(host->dev, &host_priv->rx_watermark); if (retval) { device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); goto error_exit_with_cleanup; } |
faf0b2e5a
|
1560 1561 1562 |
return 0; error_exit_with_cleanup: |
d89995db5
|
1563 |
if (host) |
6b4b8fc87
|
1564 |
ata_host_detach(host); |
6b4b8fc87
|
1565 |
|
faf0b2e5a
|
1566 1567 |
if (hcr_base) iounmap(hcr_base); |
c99cc9a2f
|
1568 |
kfree(host_priv); |
faf0b2e5a
|
1569 1570 1571 |
return retval; } |
2dc115813
|
1572 |
static int sata_fsl_remove(struct platform_device *ofdev) |
faf0b2e5a
|
1573 |
{ |
d89995db5
|
1574 |
struct ata_host *host = platform_get_drvdata(ofdev); |
faf0b2e5a
|
1575 |
struct sata_fsl_host_priv *host_priv = host->private_data; |
6b4b8fc87
|
1576 |
device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); |
7551c40d9
|
1577 |
device_remove_file(&ofdev->dev, &host_priv->rx_watermark); |
6b4b8fc87
|
1578 |
|
faf0b2e5a
|
1579 |
ata_host_detach(host); |
79b3edc97
|
1580 |
irq_dispose_mapping(host_priv->irq); |
faf0b2e5a
|
1581 1582 1583 1584 1585 |
iounmap(host_priv->hcr_base); kfree(host_priv); return 0; } |
58eb8cd56
|
1586 |
#ifdef CONFIG_PM_SLEEP |
2dc115813
|
1587 |
static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) |
dc77ad4c8
|
1588 |
{ |
d89995db5
|
1589 |
struct ata_host *host = platform_get_drvdata(op); |
dc77ad4c8
|
1590 1591 |
return ata_host_suspend(host, state); } |
2dc115813
|
1592 |
static int sata_fsl_resume(struct platform_device *op) |
dc77ad4c8
|
1593 |
{ |
d89995db5
|
1594 |
struct ata_host *host = platform_get_drvdata(op); |
dc77ad4c8
|
1595 1596 1597 1598 1599 1600 1601 1602 |
struct sata_fsl_host_priv *host_priv = host->private_data; int ret; void __iomem *hcr_base = host_priv->hcr_base; struct ata_port *ap = host->ports[0]; struct sata_fsl_port_priv *pp = ap->private_data; ret = sata_fsl_init_controller(host); if (ret) { |
a44fec1fc
|
1603 1604 |
dev_err(&op->dev, "Error initializing hardware "); |
dc77ad4c8
|
1605 1606 1607 1608 1609 |
return ret; } /* Recovery the CHBA register in host controller cmd register set */ iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); |
93272b132
|
1610 1611 1612 1613 1614 |
iowrite32((ioread32(hcr_base + HCONTROL) | HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); |
dc77ad4c8
|
1615 1616 1617 1618 |
ata_host_resume(host); return 0; } #endif |
e3779f6a4
|
1619 |
static const struct of_device_id fsl_sata_match[] = { |
faf0b2e5a
|
1620 |
{ |
96ce1b6dc
|
1621 |
.compatible = "fsl,pq-sata", |
faf0b2e5a
|
1622 |
}, |
2f957fc95
|
1623 1624 1625 |
{ .compatible = "fsl,pq-sata-v2", }, |
faf0b2e5a
|
1626 1627 1628 1629 |
{}, }; MODULE_DEVICE_TABLE(of, fsl_sata_match); |
1c48a5c93
|
1630 |
static struct platform_driver fsl_sata_driver = { |
4018294b5
|
1631 1632 |
.driver = { .name = "fsl-sata", |
4018294b5
|
1633 1634 |
.of_match_table = fsl_sata_match, }, |
faf0b2e5a
|
1635 1636 |
.probe = sata_fsl_probe, .remove = sata_fsl_remove, |
58eb8cd56
|
1637 |
#ifdef CONFIG_PM_SLEEP |
dc77ad4c8
|
1638 1639 1640 |
.suspend = sata_fsl_suspend, .resume = sata_fsl_resume, #endif |
faf0b2e5a
|
1641 |
}; |
99c8ea3e5
|
1642 |
module_platform_driver(fsl_sata_driver); |
faf0b2e5a
|
1643 1644 1645 1646 1647 |
MODULE_LICENSE("GPL"); MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); MODULE_VERSION("1.10"); |