Blame view
drivers/edac/highbank_mc_edac.c
7.44 KB
a1b01edb2 edac: add support... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 |
/* * Copyright 2011-2012 Calxeda, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License along with * this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/types.h> #include <linux/kernel.h> #include <linux/ctype.h> #include <linux/edac.h> #include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/of_platform.h> #include <linux/uaccess.h> |
a1b01edb2 edac: add support... |
24 25 26 |
#include "edac_module.h" /* DDR Ctrlr Error Registers */ |
a1b01edb2 edac: add support... |
27 |
|
0ec8579e1 edac, highbank: A... |
28 29 30 31 32 33 34 35 36 37 38 39 |
#define HB_DDR_ECC_ERR_BASE 0x128 #define MW_DDR_ECC_ERR_BASE 0x1b4 #define HB_DDR_ECC_OPT 0x00 #define HB_DDR_ECC_U_ERR_ADDR 0x08 #define HB_DDR_ECC_U_ERR_STAT 0x0c #define HB_DDR_ECC_U_ERR_DATAL 0x10 #define HB_DDR_ECC_U_ERR_DATAH 0x14 #define HB_DDR_ECC_C_ERR_ADDR 0x18 #define HB_DDR_ECC_C_ERR_STAT 0x1c #define HB_DDR_ECC_C_ERR_DATAL 0x20 #define HB_DDR_ECC_C_ERR_DATAH 0x24 |
a1b01edb2 edac: add support... |
40 41 42 43 |
#define HB_DDR_ECC_OPT_MODE_MASK 0x3 #define HB_DDR_ECC_OPT_FWC 0x100 #define HB_DDR_ECC_OPT_XOR_SHIFT 16 |
0ec8579e1 edac, highbank: A... |
44 45 46 47 48 49 50 51 52 53 54 55 |
/* DDR Ctrlr Interrupt Registers */ #define HB_DDR_ECC_INT_BASE 0x180 #define MW_DDR_ECC_INT_BASE 0x218 #define HB_DDR_ECC_INT_STATUS 0x00 #define HB_DDR_ECC_INT_ACK 0x04 #define HB_DDR_ECC_INT_STAT_CE 0x8 #define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10 #define HB_DDR_ECC_INT_STAT_UE 0x20 #define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40 |
a1b01edb2 edac: add support... |
56 |
struct hb_mc_drvdata { |
0ec8579e1 edac, highbank: A... |
57 58 |
void __iomem *mc_err_base; void __iomem *mc_int_base; |
a1b01edb2 edac: add support... |
59 60 61 62 63 64 65 66 67 |
}; static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id) { struct mem_ctl_info *mci = dev_id; struct hb_mc_drvdata *drvdata = mci->pvt_info; u32 status, err_addr; /* Read the interrupt status register */ |
0ec8579e1 edac, highbank: A... |
68 |
status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); |
a1b01edb2 edac: add support... |
69 70 |
if (status & HB_DDR_ECC_INT_STAT_UE) { |
0ec8579e1 edac, highbank: A... |
71 |
err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); |
a1b01edb2 edac: add support... |
72 73 74 75 76 77 78 |
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, err_addr >> PAGE_SHIFT, err_addr & ~PAGE_MASK, 0, 0, 0, -1, mci->ctl_name, ""); } if (status & HB_DDR_ECC_INT_STAT_CE) { |
0ec8579e1 edac, highbank: A... |
79 |
u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); |
a1b01edb2 edac: add support... |
80 |
syndrome = (syndrome >> 8) & 0xff; |
0ec8579e1 edac, highbank: A... |
81 |
err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR); |
a1b01edb2 edac: add support... |
82 83 84 85 86 87 88 89 |
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, err_addr >> PAGE_SHIFT, err_addr & ~PAGE_MASK, syndrome, 0, 0, -1, mci->ctl_name, ""); } /* clear the error, clears the interrupt */ |
0ec8579e1 edac, highbank: A... |
90 |
writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK); |
a1b01edb2 edac: add support... |
91 92 |
return IRQ_HANDLED; } |
78cfbf0bb edac, highbank: M... |
93 |
static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd) |
a1b01edb2 edac: add support... |
94 |
{ |
a1b01edb2 edac: add support... |
95 |
struct hb_mc_drvdata *pdata = mci->pvt_info; |
a1b01edb2 edac: add support... |
96 |
u32 reg; |
78cfbf0bb edac, highbank: M... |
97 98 99 100 101 102 103 104 105 106 107 108 109 |
reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); reg &= HB_DDR_ECC_OPT_MODE_MASK; reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC; writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT); } #define to_mci(k) container_of(k, struct mem_ctl_info, dev) static ssize_t highbank_mc_inject_ctrl(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { struct mem_ctl_info *mci = to_mci(dev); |
a1b01edb2 edac: add support... |
110 |
u8 synd; |
78cfbf0bb edac, highbank: M... |
111 112 |
if (kstrtou8(buf, 16, &synd)) return -EINVAL; |
a1b01edb2 edac: add support... |
113 |
|
78cfbf0bb edac, highbank: M... |
114 |
highbank_mc_err_inject(mci, synd); |
a1b01edb2 edac: add support... |
115 116 117 |
return count; } |
78cfbf0bb edac, highbank: M... |
118 |
static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl); |
a1b01edb2 edac: add support... |
119 |
|
fc7cc6b78 EDAC: highbank: U... |
120 121 122 123 124 125 |
static struct attribute *highbank_dev_attrs[] = { &dev_attr_inject_ctrl.attr, NULL }; ATTRIBUTE_GROUPS(highbank_dev); |
0ec8579e1 edac, highbank: A... |
126 127 128 129 130 131 132 133 134 135 136 137 138 139 |
struct hb_mc_settings { int err_offset; int int_offset; }; static struct hb_mc_settings hb_settings = { .err_offset = HB_DDR_ECC_ERR_BASE, .int_offset = HB_DDR_ECC_INT_BASE, }; static struct hb_mc_settings mw_settings = { .err_offset = MW_DDR_ECC_ERR_BASE, .int_offset = MW_DDR_ECC_INT_BASE, }; |
1afaa0551 EDAC: Constify of... |
140 |
static const struct of_device_id hb_ddr_ctrl_of_match[] = { |
0ec8579e1 edac, highbank: A... |
141 142 143 144 145 |
{ .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings }, { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings }, {}, }; MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match); |
9b3c6e85c Drivers: edac: re... |
146 |
static int highbank_mc_probe(struct platform_device *pdev) |
a1b01edb2 edac: add support... |
147 |
{ |
0ec8579e1 edac, highbank: A... |
148 149 |
const struct of_device_id *id; const struct hb_mc_settings *settings; |
a1b01edb2 edac: add support... |
150 151 152 153 154 |
struct edac_mc_layer layers[2]; struct mem_ctl_info *mci; struct hb_mc_drvdata *drvdata; struct dimm_info *dimm; struct resource *r; |
0ec8579e1 edac, highbank: A... |
155 |
void __iomem *base; |
a1b01edb2 edac: add support... |
156 157 158 |
u32 control; int irq; int res = 0; |
0ec8579e1 edac, highbank: A... |
159 160 161 |
id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev); if (!id) return -ENODEV; |
a1b01edb2 edac: add support... |
162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 |
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers[0].size = 1; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = 1; layers[1].is_virt_csrow = false; mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct hb_mc_drvdata)); if (!mci) return -ENOMEM; mci->pdev = &pdev->dev; drvdata = mci->pvt_info; platform_set_drvdata(pdev, mci); if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) return -ENOMEM; r = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!r) { dev_err(&pdev->dev, "Unable to get mem resource "); res = -ENODEV; goto err; } if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), dev_name(&pdev->dev))) { dev_err(&pdev->dev, "Error while requesting mem region "); res = -EBUSY; goto err; } |
0ec8579e1 edac, highbank: A... |
195 196 |
base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); if (!base) { |
a1b01edb2 edac: add support... |
197 198 199 200 201 |
dev_err(&pdev->dev, "Unable to map regs "); res = -ENOMEM; goto err; } |
0ec8579e1 edac, highbank: A... |
202 203 204 205 206 |
settings = id->data; drvdata->mc_err_base = base + settings->err_offset; drvdata->mc_int_base = base + settings->int_offset; control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3; |
a1b01edb2 edac: add support... |
207 208 209 210 211 212 |
if (!control || (control == 0x2)) { dev_err(&pdev->dev, "No ECC present, or ECC disabled "); res = -ENODEV; goto err; } |
a1b01edb2 edac: add support... |
213 214 215 |
mci->mtype_cap = MEM_FLAG_DDR3; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->edac_cap = EDAC_FLAG_SECDED; |
41ec0e8da edac, highbank: I... |
216 |
mci->mod_name = pdev->dev.driver->name; |
a1b01edb2 edac: add support... |
217 |
mci->mod_ver = "1"; |
41ec0e8da edac, highbank: I... |
218 219 |
mci->ctl_name = id->compatible; mci->dev_name = dev_name(&pdev->dev); |
a1b01edb2 edac: add support... |
220 221 222 223 224 225 226 227 228 |
mci->scrub_mode = SCRUB_SW_SRC; /* Only a single 4GB DIMM is supported */ dimm = *mci->dimms; dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1; dimm->grain = 8; dimm->dtype = DEV_X8; dimm->mtype = MEM_DDR3; dimm->edac_mode = EDAC_SECDED; |
fc7cc6b78 EDAC: highbank: U... |
229 |
res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups); |
a1b01edb2 edac: add support... |
230 231 |
if (res < 0) goto err; |
a72b8859f edac, highbank: F... |
232 233 234 235 236 237 238 239 |
irq = platform_get_irq(pdev, 0); res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler, 0, dev_name(&pdev->dev), mci); if (res < 0) { dev_err(&pdev->dev, "Unable to request irq %d ", irq); goto err2; } |
a1b01edb2 edac: add support... |
240 241 |
devres_close_group(&pdev->dev, NULL); return 0; |
a72b8859f edac, highbank: F... |
242 243 |
err2: edac_mc_del_mc(&pdev->dev); |
a1b01edb2 edac: add support... |
244 245 246 247 248 249 250 251 252 253 254 255 256 257 |
err: devres_release_group(&pdev->dev, NULL); edac_mc_free(mci); return res; } static int highbank_mc_remove(struct platform_device *pdev) { struct mem_ctl_info *mci = platform_get_drvdata(pdev); edac_mc_del_mc(&pdev->dev); edac_mc_free(mci); return 0; } |
a1b01edb2 edac: add support... |
258 259 260 261 262 263 264 265 266 267 268 269 270 271 |
static struct platform_driver highbank_mc_edac_driver = { .probe = highbank_mc_probe, .remove = highbank_mc_remove, .driver = { .name = "hb_mc_edac", .of_match_table = hb_ddr_ctrl_of_match, }, }; module_platform_driver(highbank_mc_edac_driver); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Calxeda, Inc."); MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank"); |