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drivers/edac/i5400_edac.c
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/* |
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* Intel 5400 class Memory Controllers kernel module (Seaburg) |
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* * This file may be distributed under the terms of the * GNU General Public License. * * Copyright (c) 2008 by: * Ben Woodard <woodard@redhat.com> |
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* Mauro Carvalho Chehab |
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* * Red Hat Inc. http://www.redhat.com * * Forked and adapted from the i5000_edac driver which was * written by Douglas Thompson Linux Networx <norsk5@xmission.com> * * This module is based on the following document: * * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet * http://developer.intel.com/design/chipsets/datashts/313070.htm * |
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* This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with * 2 channels operating in lockstep no-mirror mode. Each channel can have up to * 4 dimm's, each with up to 8GB. * |
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*/ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/edac.h> #include <linux/mmzone.h> |
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#include "edac_module.h" |
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/* * Alter this version for the I5400 module when modifications are made */ |
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#define I5400_REVISION " Ver: 1.0.0" |
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#define EDAC_MOD_STR "i5400_edac" #define i5400_printk(level, fmt, arg...) \ edac_printk(level, "i5400", fmt, ##arg) #define i5400_mc_printk(mci, level, fmt, arg...) \ edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg) /* Limits for i5400 */ |
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#define MAX_BRANCHES 2 |
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#define CHANNELS_PER_BRANCH 2 |
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#define DIMMS_PER_CHANNEL 4 #define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH) |
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/* Device 16, * Function 0: System Address * Function 1: Memory Branch Map, Control, Errors Register * Function 2: FSB Error Registers * |
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* All 3 functions of Device 16 (0,1,2) share the SAME DID and * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2), * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1 * for device 21 (0,1). |
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*/ |
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/* OFFSETS for Function 0 */ #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ #define MAXCH 0x56 /* Max Channel Number */ #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ /* OFFSETS for Function 1 */ #define TOLM 0x6C #define REDMEMB 0x7C #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */ #define MIR0 0x80 #define MIR1 0x84 #define AMIR0 0x8c #define AMIR1 0x90 /* Fatal error registers */ #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */ #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */ #define NERR_FAT_FBD 0x9c #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */ /* Non-fatal error register */ #define NERR_NF_FBD 0xa4 /* Enable error mask */ #define EMASK_FBD 0xa8 #define ERR0_FBD 0xac #define ERR1_FBD 0xb0 #define ERR2_FBD 0xb4 #define MCERR_FBD 0xb8 /* No OFFSETS for Device 16 Function 2 */ /* * Device 21, * Function 0: Memory Map Branch 0 * * Device 22, * Function 0: Memory Map Branch 1 */ /* OFFSETS for Function 0 */ #define AMBPRESENT_0 0x64 #define AMBPRESENT_1 0x66 #define MTR0 0x80 #define MTR1 0x82 #define MTR2 0x84 #define MTR3 0x86 /* OFFSETS for Function 1 */ #define NRECFGLOG 0x74 #define RECFGLOG 0x78 #define NRECMEMA 0xbe #define NRECMEMB 0xc0 #define NRECFB_DIMMA 0xc4 #define NRECFB_DIMMB 0xc8 #define NRECFB_DIMMC 0xcc #define NRECFB_DIMMD 0xd0 #define NRECFB_DIMME 0xd4 #define NRECFB_DIMMF 0xd8 #define REDMEMA 0xdC #define RECMEMA 0xf0 #define RECMEMB 0xf4 #define RECFB_DIMMA 0xf8 #define RECFB_DIMMB 0xec #define RECFB_DIMMC 0xf0 #define RECFB_DIMMD 0xf4 #define RECFB_DIMME 0xf8 #define RECFB_DIMMF 0xfC /* * Error indicator bits and masks * Error masks are according with Table 5-17 of i5400 datasheet */ enum error_mask { EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */ EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */ EMASK_M3 = 1<<2, /* Reserved */ EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */ EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */ EMASK_M6 = 1<<5, /* Unsupported on i5400 */ EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */ EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */ EMASK_M10 = 1<<9, /* Unsupported on i5400 */ EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */ EMASK_M13 = 1<<12, /* Memory Write error on first attempt */ EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */ EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */ EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */ EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */ EMASK_M18 = 1<<17, /* Unsupported on i5400 */ EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */ EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */ EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */ EMASK_M22 = 1<<21, /* SPD protocol Error */ EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */ EMASK_M24 = 1<<23, /* Refresh error */ EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */ EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */ EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */ EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */ EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */ }; /* * Names to translate bit error into something useful */ |
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static const char *error_name[] = { |
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[0] = "Memory Write error on non-redundant retry", [1] = "Memory or FB-DIMM configuration CRC read error", /* Reserved */ [3] = "Uncorrectable Data ECC on Replay", [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", |
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/* M6 Unsupported on i5400 */ |
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[6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [7] = "Aliased Uncorrectable Patrol Data ECC", [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", |
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/* M10 Unsupported on i5400 */ |
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[10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [11] = "Non-Aliased Uncorrectable Patrol Data ECC", [12] = "Memory Write error on first attempt", [13] = "FB-DIMM Configuration Write error on first attempt", [14] = "Memory or FB-DIMM configuration CRC read error", [15] = "Channel Failed-Over Occurred", [16] = "Correctable Non-Mirrored Demand Data ECC", |
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/* M18 Unsupported on i5400 */ |
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[18] = "Correctable Resilver- or Spare-Copy Data ECC", [19] = "Correctable Patrol Data ECC", [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status", [21] = "SPD protocol Error", [22] = "Non-Redundant Fast Reset Timeout", [23] = "Refresh error", [24] = "Memory Write error on redundant retry", [25] = "Redundant Fast Reset Timeout", [26] = "Correctable Counter Threshold Exceeded", [27] = "DIMM-Spare Copy Completed", [28] = "DIMM-Isolation Completed", }; /* Fatal errors */ #define ERROR_FAT_MASK (EMASK_M1 | \ EMASK_M2 | \ EMASK_M23) /* Correctable errors */ #define ERROR_NF_CORRECTABLE (EMASK_M27 | \ EMASK_M20 | \ EMASK_M19 | \ EMASK_M18 | \ EMASK_M17 | \ EMASK_M16) #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \ EMASK_M28) #define ERROR_NF_SPD_PROTOCOL (EMASK_M22) #define ERROR_NF_NORTH_CRC (EMASK_M21) /* Recoverable errors */ #define ERROR_NF_RECOVERABLE (EMASK_M26 | \ EMASK_M25 | \ EMASK_M24 | \ EMASK_M15 | \ EMASK_M14 | \ EMASK_M13 | \ EMASK_M12 | \ EMASK_M11 | \ EMASK_M9 | \ EMASK_M8 | \ EMASK_M7 | \ EMASK_M5) /* uncorrectable errors */ #define ERROR_NF_UNCORRECTABLE (EMASK_M4) /* mask to all non-fatal errors */ #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \ ERROR_NF_UNCORRECTABLE | \ ERROR_NF_RECOVERABLE | \ ERROR_NF_DIMM_SPARE | \ ERROR_NF_SPD_PROTOCOL | \ ERROR_NF_NORTH_CRC) /* * Define error masks for the several registers */ /* Enable all fatal and non fatal errors */ #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK) /* mask for fatal error registers */ #define FERR_FAT_MASK ERROR_FAT_MASK /* masks for non-fatal error register */ |
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static inline int to_nf_mask(unsigned int mask) { return (mask & EMASK_M29) | (mask >> 3); }; static inline int from_nf_ferr(unsigned int mask) { return (mask & EMASK_M29) | /* Bit 28 */ (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ }; |
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#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK) #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE) #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE) #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL) #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC) #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE) #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE) |
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/* Defines to extract the vaious fields from the * MTRx - Memory Technology Registers */ #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) |
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#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) |
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#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */ static inline int extract_fbdchan_indx(u32 x) { return (x>>28) & 0x3; } |
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/* Device name and register DID (Device ID) */ struct i5400_dev_info { const char *ctl_name; /* name for this device */ u16 fsb_mapping_errors; /* DID for the branchmap,control */ }; /* Table of devices attributes supported by this driver */ static const struct i5400_dev_info i5400_devs[] = { { .ctl_name = "I5400", .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR, }, }; struct i5400_dimm_info { int megabytes; /* size, 0 means not present */ |
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}; /* driver private data structure */ struct i5400_pvt { struct pci_dev *system_address; /* 16.0 */ struct pci_dev *branchmap_werrors; /* 16.1 */ struct pci_dev *fsb_error_regs; /* 16.2 */ struct pci_dev *branch_0; /* 21.0 */ struct pci_dev *branch_1; /* 22.0 */ u16 tolm; /* top of low memory */ |
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union { u64 ambase; /* AMB BAR */ struct { u32 ambase_bottom; u32 ambase_top; } u __packed; }; |
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u16 mir0, mir1; |
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u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ |
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u16 b0_ambpresent0; /* Branch 0, Channel 0 */ u16 b0_ambpresent1; /* Brnach 0, Channel 1 */ |
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u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ |
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u16 b1_ambpresent0; /* Branch 1, Channel 8 */ u16 b1_ambpresent1; /* Branch 1, Channel 1 */ /* DIMM information matrix, allocating architecture maximums */ |
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struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS]; |
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/* Actual values for this controller */ int maxch; /* Max channels */ int maxdimmperch; /* Max DIMMs per channel */ }; /* I5400 MCH error information retrieved from Hardware */ struct i5400_error_info { /* These registers are always read from the MC */ u32 ferr_fat_fbd; /* First Errors Fatal */ u32 nerr_fat_fbd; /* Next Errors Fatal */ u32 ferr_nf_fbd; /* First Errors Non-Fatal */ u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ /* These registers are input ONLY if there was a Recoverable Error */ u32 redmemb; /* Recoverable Mem Data Error log B */ u16 recmema; /* Recoverable Mem Error log A */ u32 recmemb; /* Recoverable Mem Error log B */ |
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/* These registers are input ONLY if there was a Non-Rec Error */ |
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u16 nrecmema; /* Non-Recoverable Mem log A */ u16 nrecmemb; /* Non-Recoverable Mem log B */ }; /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and 5400 better to use an inline function than a macro in this case */ static inline int nrec_bank(struct i5400_error_info *info) { return ((info->nrecmema) >> 12) & 0x7; } static inline int nrec_rank(struct i5400_error_info *info) { return ((info->nrecmema) >> 8) & 0xf; } static inline int nrec_buf_id(struct i5400_error_info *info) { return ((info->nrecmema)) & 0xff; } static inline int nrec_rdwr(struct i5400_error_info *info) { return (info->nrecmemb) >> 31; } /* This applies to both NREC and REC string so it can be used with nrec_rdwr and rec_rdwr */ static inline const char *rdwr_str(int rdwr) { return rdwr ? "Write" : "Read"; } static inline int nrec_cas(struct i5400_error_info *info) { return ((info->nrecmemb) >> 16) & 0x1fff; } static inline int nrec_ras(struct i5400_error_info *info) { return (info->nrecmemb) & 0xffff; } static inline int rec_bank(struct i5400_error_info *info) { return ((info->recmema) >> 12) & 0x7; } static inline int rec_rank(struct i5400_error_info *info) { return ((info->recmema) >> 8) & 0xf; } static inline int rec_rdwr(struct i5400_error_info *info) { return (info->recmemb) >> 31; } static inline int rec_cas(struct i5400_error_info *info) { return ((info->recmemb) >> 16) & 0x1fff; } static inline int rec_ras(struct i5400_error_info *info) { return (info->recmemb) & 0xffff; } static struct edac_pci_ctl_info *i5400_pci; /* * i5400_get_error_info Retrieve the hardware error information from * the hardware and cache it in the 'info' * structure */ static void i5400_get_error_info(struct mem_ctl_info *mci, struct i5400_error_info *info) { struct i5400_pvt *pvt; u32 value; pvt = mci->pvt_info; /* read in the 1st FATAL error register */ pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); /* Mask only the bits that the doc says are valid */ value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); /* If there is an error, then read in the NEXT FATAL error register and the Memory Error Log Register A */ if (value & FERR_FAT_MASK) { info->ferr_fat_fbd = value; /* harvest the various error data we need */ pci_read_config_dword(pvt->branchmap_werrors, NERR_FAT_FBD, &info->nerr_fat_fbd); pci_read_config_word(pvt->branchmap_werrors, NRECMEMA, &info->nrecmema); pci_read_config_word(pvt->branchmap_werrors, NRECMEMB, &info->nrecmemb); /* Clear the error bits, by writing them back */ pci_write_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, value); } else { info->ferr_fat_fbd = 0; info->nerr_fat_fbd = 0; info->nrecmema = 0; info->nrecmemb = 0; } /* read in the 1st NON-FATAL error register */ pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); /* If there is an error, then read in the 1st NON-FATAL error * register as well */ if (value & FERR_NF_MASK) { info->ferr_nf_fbd = value; /* harvest the various error data we need */ pci_read_config_dword(pvt->branchmap_werrors, NERR_NF_FBD, &info->nerr_nf_fbd); pci_read_config_word(pvt->branchmap_werrors, RECMEMA, &info->recmema); pci_read_config_dword(pvt->branchmap_werrors, RECMEMB, &info->recmemb); pci_read_config_dword(pvt->branchmap_werrors, REDMEMB, &info->redmemb); /* Clear the error bits, by writing them back */ pci_write_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, value); } else { info->ferr_nf_fbd = 0; info->nerr_nf_fbd = 0; info->recmema = 0; info->recmemb = 0; info->redmemb = 0; } } /* * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, * struct i5400_error_info *info, * int handle_errors); * * handle the Intel FATAL and unrecoverable errors, if any */ static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, struct i5400_error_info *info, unsigned long allErrors) { char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; int branch; int channel; int bank; int buf_id; int rank; int rdwr; int ras, cas; int errnum; char *type = NULL; |
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enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED; |
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if (!allErrors) return; /* if no error, return now */ |
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if (allErrors & ERROR_FAT_MASK) { |
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type = "FATAL"; |
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tp_event = HW_EVENT_ERR_FATAL; } else if (allErrors & FERR_NF_UNCORRECTABLE) |
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type = "NON-FATAL uncorrected"; else type = "NON-FATAL recoverable"; /* ONLY ONE of the possible error bits will be set, as per the docs */ branch = extract_fbdchan_indx(info->ferr_fat_fbd); channel = branch; /* Use the NON-Recoverable macros to extract data */ bank = nrec_bank(info); rank = nrec_rank(info); buf_id = nrec_buf_id(info); rdwr = nrec_rdwr(info); ras = nrec_ras(info); cas = nrec_cas(info); |
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edac_dbg(0, "\t\tDIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d) ", rank, channel, channel + 1, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas); |
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/* Only 1 bit will be on */ errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); /* Form out message */ snprintf(msg, sizeof(msg), |
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"Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", bank, buf_id, ras, cas, allErrors, error_name[errnum]); |
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edac_mc_handle_error(tp_event, mci, 1, 0, 0, 0, |
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branch >> 1, -1, rank, rdwr ? "Write error" : "Read error", |
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msg); |
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} /* * i5400_process_fatal_error_info(struct mem_ctl_info *mci, * struct i5400_error_info *info, * int handle_errors); * * handle the Intel NON-FATAL errors, if any */ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci, struct i5400_error_info *info) { char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; unsigned long allErrors; int branch; int channel; int bank; int rank; int rdwr; int ras, cas; int errnum; /* mask off the Error bits that are possible */ |
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allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); |
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if (!allErrors) return; /* if no error, return now */ /* ONLY ONE of the possible error bits will be set, as per the docs */ if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) { i5400_proccess_non_recoverable_info(mci, info, allErrors); return; } /* Correctable errors */ if (allErrors & ERROR_NF_CORRECTABLE) { |
956b9ba15 edac: Convert deb... |
597 598 |
edac_dbg(0, "\tCorrected bits= 0x%lx ", allErrors); |
920c8df6a edac: driver for ... |
599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 |
branch = extract_fbdchan_indx(info->ferr_nf_fbd); channel = 0; if (REC_ECC_LOCATOR_ODD(info->redmemb)) channel = 1; /* Convert channel to be based from zero, instead of * from branch base of 0 */ channel += branch; bank = rec_bank(info); rank = rec_rank(info); rdwr = rec_rdwr(info); ras = rec_ras(info); cas = rec_cas(info); /* Only 1 bit will be on */ errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); |
956b9ba15 edac: Convert deb... |
618 619 620 621 |
edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d) ", rank, channel, branch >> 1, bank, rdwr_str(rdwr), ras, cas); |
920c8df6a edac: driver for ... |
622 623 624 |
/* Form out message */ snprintf(msg, sizeof(msg), |
8375d4909 edac: driver for ... |
625 626 627 628 |
"Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " "RAS=%d CAS=%d, CE Err=0x%lx (%s))", branch >> 1, bank, rdwr_str(rdwr), ras, cas, allErrors, error_name[errnum]); |
920c8df6a edac: driver for ... |
629 |
|
9eb07a7fb edac: edac_mc_han... |
630 |
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, |
296da591e i5400_edac: conve... |
631 632 |
branch >> 1, channel % 2, rank, rdwr ? "Write error" : "Read error", |
03f7eae80 edac: remove arch... |
633 |
msg); |
920c8df6a edac: driver for ... |
634 635 636 |
return; } |
25985edce Fix common misspe... |
637 |
/* Miscellaneous errors */ |
920c8df6a edac: driver for ... |
638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 |
errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); branch = extract_fbdchan_indx(info->ferr_nf_fbd); i5400_mc_printk(mci, KERN_EMERG, "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", branch >> 1, allErrors, error_name[errnum]); } /* * i5400_process_error_info Process the error info that is * in the 'info' structure, previously retrieved from hardware */ static void i5400_process_error_info(struct mem_ctl_info *mci, struct i5400_error_info *info) { u32 allErrors; /* First handle any fatal errors that occurred */ allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); i5400_proccess_non_recoverable_info(mci, info, allErrors); /* now handle any non-fatal errors that occurred */ i5400_process_nonfatal_error_info(mci, info); } /* * i5400_clear_error Retrieve any error from the hardware * but do NOT process that error. * Used for 'clearing' out of previous errors * Called by the Core module. */ static void i5400_clear_error(struct mem_ctl_info *mci) { struct i5400_error_info info; i5400_get_error_info(mci, &info); } /* * i5400_check_error Retrieve and process errors reported by the * hardware. Called by the Core module. */ static void i5400_check_error(struct mem_ctl_info *mci) { struct i5400_error_info info; |
956b9ba15 edac: Convert deb... |
683 684 |
edac_dbg(4, "MC%d ", mci->mc_idx); |
920c8df6a edac: driver for ... |
685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 |
i5400_get_error_info(mci, &info); i5400_process_error_info(mci, &info); } /* * i5400_put_devices 'put' all the devices that we have * reserved via 'get' */ static void i5400_put_devices(struct mem_ctl_info *mci) { struct i5400_pvt *pvt; pvt = mci->pvt_info; /* Decrement usage count for devices */ |
8375d4909 edac: driver for ... |
700 701 702 703 |
pci_dev_put(pvt->branch_1); pci_dev_put(pvt->branch_0); pci_dev_put(pvt->fsb_error_regs); pci_dev_put(pvt->branchmap_werrors); |
920c8df6a edac: driver for ... |
704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 |
} /* * i5400_get_devices Find and perform 'get' operation on the MCH's * device/functions we want to reference for this driver * * Need to 'get' device 16 func 1 and func 2 */ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx) { struct i5400_pvt *pvt; struct pci_dev *pdev; pvt = mci->pvt_info; pvt->branchmap_werrors = NULL; pvt->fsb_error_regs = NULL; pvt->branch_0 = NULL; pvt->branch_1 = NULL; /* Attempt to 'get' the MCH register we want */ pdev = NULL; |
0142877aa i5400_edac: Avoid... |
725 |
while (1) { |
920c8df6a edac: driver for ... |
726 727 728 729 730 731 732 |
pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR, pdev); if (!pdev) { /* End of list, leave */ i5400_printk(KERN_ERR, "'system address,Process Bus' " "device not found:" |
0142877aa i5400_edac: Avoid... |
733 |
"vendor 0x%x device 0x%x ERR func 1 " |
920c8df6a edac: driver for ... |
734 735 736 737 |
"(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR); |
0142877aa i5400_edac: Avoid... |
738 |
return -ENODEV; |
920c8df6a edac: driver for ... |
739 |
} |
0142877aa i5400_edac: Avoid... |
740 741 |
/* Store device 16 func 1 */ if (PCI_FUNC(pdev->devfn) == 1) |
920c8df6a edac: driver for ... |
742 |
break; |
0142877aa i5400_edac: Avoid... |
743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 |
} pvt->branchmap_werrors = pdev; pdev = NULL; while (1) { pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR, pdev); if (!pdev) { /* End of list, leave */ i5400_printk(KERN_ERR, "'system address,Process Bus' " "device not found:" "vendor 0x%x device 0x%x ERR func 2 " "(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR); pci_dev_put(pvt->branchmap_werrors); return -ENODEV; |
920c8df6a edac: driver for ... |
763 |
} |
0142877aa i5400_edac: Avoid... |
764 765 766 767 |
/* Store device 16 func 2 */ if (PCI_FUNC(pdev->devfn) == 2) break; |
920c8df6a edac: driver for ... |
768 |
} |
0142877aa i5400_edac: Avoid... |
769 |
pvt->fsb_error_regs = pdev; |
920c8df6a edac: driver for ... |
770 |
|
956b9ba15 edac: Convert deb... |
771 772 773 774 775 776 777 778 779 780 781 782 783 |
edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x ", pci_name(pvt->system_address), pvt->system_address->vendor, pvt->system_address->device); edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x ", pci_name(pvt->branchmap_werrors), pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device); edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x ", pci_name(pvt->fsb_error_regs), pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); |
920c8df6a edac: driver for ... |
784 785 786 787 788 789 790 791 792 |
pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0, NULL); if (!pvt->branch_0) { i5400_printk(KERN_ERR, "MC: 'BRANCH 0' device not found:" "vendor 0x%x device 0x%x Func 0 (broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0); |
0142877aa i5400_edac: Avoid... |
793 794 795 796 |
pci_dev_put(pvt->fsb_error_regs); pci_dev_put(pvt->branchmap_werrors); return -ENODEV; |
920c8df6a edac: driver for ... |
797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 |
} /* If this device claims to have more than 2 channels then * fetch Branch 1's information */ if (pvt->maxch < CHANNELS_PER_BRANCH) return 0; pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD1, NULL); if (!pvt->branch_1) { i5400_printk(KERN_ERR, "MC: 'BRANCH 1' device not found:" "vendor 0x%x device 0x%x Func 0 " "(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD1); |
0142877aa i5400_edac: Avoid... |
815 816 817 818 819 |
pci_dev_put(pvt->branch_0); pci_dev_put(pvt->fsb_error_regs); pci_dev_put(pvt->branchmap_werrors); return -ENODEV; |
920c8df6a edac: driver for ... |
820 821 822 |
} return 0; |
920c8df6a edac: driver for ... |
823 824 825 826 827 |
} /* * determine_amb_present * |
296da591e i5400_edac: conve... |
828 829 |
* the information is contained in DIMMS_PER_CHANNEL different * registers determining which of the DIMMS_PER_CHANNEL requires |
8375d4909 edac: driver for ... |
830 |
* knowing which channel is in question |
920c8df6a edac: driver for ... |
831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 |
* * 2 branches, each with 2 channels * b0_ambpresent0 for channel '0' * b0_ambpresent1 for channel '1' * b1_ambpresent0 for channel '2' * b1_ambpresent1 for channel '3' */ static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel) { int amb_present; if (channel < CHANNELS_PER_BRANCH) { if (channel & 0x1) amb_present = pvt->b0_ambpresent1; else amb_present = pvt->b0_ambpresent0; } else { if (channel & 0x1) amb_present = pvt->b1_ambpresent1; else amb_present = pvt->b1_ambpresent0; } return amb_present; } /* |
296da591e i5400_edac: conve... |
858 |
* determine_mtr(pvt, dimm, channel) |
920c8df6a edac: driver for ... |
859 |
* |
296da591e i5400_edac: conve... |
860 |
* return the proper MTR register as determine by the dimm and desired channel |
920c8df6a edac: driver for ... |
861 |
*/ |
296da591e i5400_edac: conve... |
862 |
static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel) |
920c8df6a edac: driver for ... |
863 864 865 866 867 |
{ int mtr; int n; /* There is one MTR for each slot pair of FB-DIMMs, |
920c8df6a edac: driver for ... |
868 |
Each slot pair may be at branch 0 or branch 1. |
920c8df6a edac: driver for ... |
869 |
*/ |
296da591e i5400_edac: conve... |
870 |
n = dimm; |
920c8df6a edac: driver for ... |
871 |
|
296da591e i5400_edac: conve... |
872 |
if (n >= DIMMS_PER_CHANNEL) { |
956b9ba15 edac: Convert deb... |
873 874 875 |
edac_dbg(0, "ERROR: trying to access an invalid dimm: %d ", dimm); |
920c8df6a edac: driver for ... |
876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 |
return 0; } if (channel < CHANNELS_PER_BRANCH) mtr = pvt->b0_mtr[n]; else mtr = pvt->b1_mtr[n]; return mtr; } /* */ static void decode_mtr(int slot_row, u16 mtr) { int ans; ans = MTR_DIMMS_PRESENT(mtr); |
956b9ba15 edac: Convert deb... |
894 895 896 |
edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent ", slot_row, mtr, ans ? "" : "NOT "); |
920c8df6a edac: driver for ... |
897 898 |
if (!ans) return; |
956b9ba15 edac: Convert deb... |
899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 |
edac_dbg(2, "\t\tWIDTH: x%d ", MTR_DRAM_WIDTH(mtr)); edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s ", MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); edac_dbg(2, "\t\tNUMBANK: %d bank(s) ", MTR_DRAM_BANKS(mtr)); edac_dbg(2, "\t\tNUMRANK: %s ", MTR_DIMM_RANK(mtr) ? "double" : "single"); edac_dbg(2, "\t\tNUMROW: %s ", MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : "65,536 - 16 rows"); edac_dbg(2, "\t\tNUMCOL: %s ", MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : "reserved"); |
920c8df6a edac: driver for ... |
923 |
} |
296da591e i5400_edac: conve... |
924 |
static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, |
920c8df6a edac: driver for ... |
925 926 927 928 929 |
struct i5400_dimm_info *dinfo) { int mtr; int amb_present_reg; int addrBits; |
296da591e i5400_edac: conve... |
930 |
mtr = determine_mtr(pvt, dimm, channel); |
920c8df6a edac: driver for ... |
931 932 933 934 |
if (MTR_DIMMS_PRESENT(mtr)) { amb_present_reg = determine_amb_present_reg(pvt, channel); /* Determine if there is a DIMM present in this DIMM slot */ |
296da591e i5400_edac: conve... |
935 |
if (amb_present_reg & (1 << dimm)) { |
156edd4aa edac: i5400 fix c... |
936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 |
/* Start with the number of bits for a Bank * on the DRAM */ addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); /* Add thenumber of ROW bits */ addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); /* add the number of COLUMN bits */ addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); /* add the number of RANK bits */ addrBits += MTR_DIMM_RANK(mtr); addrBits += 6; /* add 64 bits per DIMM */ addrBits -= 20; /* divide by 2^^20 */ addrBits -= 3; /* 8 bits per bytes */ dinfo->megabytes = 1 << addrBits; |
920c8df6a edac: driver for ... |
951 952 953 954 955 956 957 958 959 960 961 962 963 |
} } } /* * calculate_dimm_size * * also will output a DIMM matrix map, if debug is enabled, for viewing * how the DIMMs are populated */ static void calculate_dimm_size(struct i5400_pvt *pvt) { struct i5400_dimm_info *dinfo; |
296da591e i5400_edac: conve... |
964 |
int dimm, max_dimms; |
920c8df6a edac: driver for ... |
965 966 |
char *p, *mem_buffer; int space, n; |
68d086f89 i5400_edac: impro... |
967 |
int channel, branch; |
920c8df6a edac: driver for ... |
968 969 970 971 972 973 974 975 976 977 |
/* ================= Generate some debug output ================= */ space = PAGE_SIZE; mem_buffer = p = kmalloc(space, GFP_KERNEL); if (p == NULL) { i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed ", __FILE__, __func__); return; } |
296da591e i5400_edac: conve... |
978 |
/* Scan all the actual DIMMS |
920c8df6a edac: driver for ... |
979 |
* and calculate the information for each DIMM |
296da591e i5400_edac: conve... |
980 981 |
* Start with the highest dimm first, to display it first * and work toward the 0th dimm |
920c8df6a edac: driver for ... |
982 |
*/ |
296da591e i5400_edac: conve... |
983 984 |
max_dimms = pvt->maxdimmperch; for (dimm = max_dimms - 1; dimm >= 0; dimm--) { |
920c8df6a edac: driver for ... |
985 |
|
296da591e i5400_edac: conve... |
986 |
/* on an odd dimm, first output a 'boundary' marker, |
920c8df6a edac: driver for ... |
987 |
* then reset the message buffer */ |
296da591e i5400_edac: conve... |
988 |
if (dimm & 0x1) { |
920c8df6a edac: driver for ... |
989 |
n = snprintf(p, space, "---------------------------" |
296da591e i5400_edac: conve... |
990 |
"-------------------------------"); |
920c8df6a edac: driver for ... |
991 992 |
p += n; space -= n; |
956b9ba15 edac: Convert deb... |
993 994 |
edac_dbg(2, "%s ", mem_buffer); |
920c8df6a edac: driver for ... |
995 996 997 |
p = mem_buffer; space = PAGE_SIZE; } |
296da591e i5400_edac: conve... |
998 |
n = snprintf(p, space, "dimm %2d ", dimm); |
920c8df6a edac: driver for ... |
999 1000 1001 1002 |
p += n; space -= n; for (channel = 0; channel < pvt->maxch; channel++) { |
296da591e i5400_edac: conve... |
1003 1004 |
dinfo = &pvt->dimm_info[dimm][channel]; handle_channel(pvt, dimm, channel, dinfo); |
920c8df6a edac: driver for ... |
1005 1006 1007 1008 |
n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); p += n; space -= n; } |
956b9ba15 edac: Convert deb... |
1009 1010 |
edac_dbg(2, "%s ", mem_buffer); |
920c8df6a edac: driver for ... |
1011 1012 1013 1014 1015 1016 |
p = mem_buffer; space = PAGE_SIZE; } /* Output the last bottom 'boundary' marker */ n = snprintf(p, space, "---------------------------" |
296da591e i5400_edac: conve... |
1017 |
"-------------------------------"); |
920c8df6a edac: driver for ... |
1018 1019 |
p += n; space -= n; |
956b9ba15 edac: Convert deb... |
1020 1021 |
edac_dbg(2, "%s ", mem_buffer); |
920c8df6a edac: driver for ... |
1022 1023 1024 1025 |
p = mem_buffer; space = PAGE_SIZE; /* now output the 'channel' labels */ |
296da591e i5400_edac: conve... |
1026 |
n = snprintf(p, space, " "); |
920c8df6a edac: driver for ... |
1027 1028 1029 1030 1031 1032 1033 |
p += n; space -= n; for (channel = 0; channel < pvt->maxch; channel++) { n = snprintf(p, space, "channel %d | ", channel); p += n; space -= n; } |
68d086f89 i5400_edac: impro... |
1034 |
space -= n; |
956b9ba15 edac: Convert deb... |
1035 1036 |
edac_dbg(2, "%s ", mem_buffer); |
68d086f89 i5400_edac: impro... |
1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 |
p = mem_buffer; space = PAGE_SIZE; n = snprintf(p, space, " "); p += n; for (branch = 0; branch < MAX_BRANCHES; branch++) { n = snprintf(p, space, " branch %d | ", branch); p += n; space -= n; } |
920c8df6a edac: driver for ... |
1047 |
/* output the last message and free buffer */ |
956b9ba15 edac: Convert deb... |
1048 1049 |
edac_dbg(2, "%s ", mem_buffer); |
920c8df6a edac: driver for ... |
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 |
kfree(mem_buffer); } /* * i5400_get_mc_regs read in the necessary registers and * cache locally * * Fills in the private data members */ static void i5400_get_mc_regs(struct mem_ctl_info *mci) { struct i5400_pvt *pvt; u32 actual_tolm; u16 limit; int slot_row; int maxch; int maxdimmperch; int way0, way1; pvt = mci->pvt_info; pci_read_config_dword(pvt->system_address, AMBASE, |
f58d0dee0 edac i5000, i5400... |
1072 |
&pvt->u.ambase_bottom); |
920c8df6a edac: driver for ... |
1073 |
pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), |
f58d0dee0 edac i5000, i5400... |
1074 |
&pvt->u.ambase_top); |
920c8df6a edac: driver for ... |
1075 1076 1077 |
maxdimmperch = pvt->maxdimmperch; maxch = pvt->maxch; |
956b9ba15 edac: Convert deb... |
1078 1079 1080 |
edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d ", (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); |
920c8df6a edac: driver for ... |
1081 1082 1083 1084 |
/* Get the Branch Map regs */ pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); pvt->tolm >>= 12; |
956b9ba15 edac: Convert deb... |
1085 1086 1087 1088 |
edac_dbg(2, " TOLM (number of 256M regions) =%u (0x%x) ", pvt->tolm, pvt->tolm); |
920c8df6a edac: driver for ... |
1089 1090 |
actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); |
956b9ba15 edac: Convert deb... |
1091 1092 1093 |
edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x) ", actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); |
920c8df6a edac: driver for ... |
1094 1095 1096 1097 1098 1099 1100 1101 |
pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); /* Get the MIR[0-1] regs */ limit = (pvt->mir0 >> 4) & 0x0fff; way0 = pvt->mir0 & 0x1; way1 = pvt->mir0 & 0x2; |
956b9ba15 edac: Convert deb... |
1102 1103 1104 |
edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x ", limit, way1, way0); |
920c8df6a edac: driver for ... |
1105 1106 1107 |
limit = (pvt->mir1 >> 4) & 0xfff; way0 = pvt->mir1 & 0x1; way1 = pvt->mir1 & 0x2; |
956b9ba15 edac: Convert deb... |
1108 1109 1110 |
edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x ", limit, way1, way0); |
920c8df6a edac: driver for ... |
1111 1112 |
/* Get the set of MTR[0-3] regs by each branch */ |
296da591e i5400_edac: conve... |
1113 |
for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) { |
156edd4aa edac: i5400 fix c... |
1114 |
int where = MTR0 + (slot_row * sizeof(u16)); |
920c8df6a edac: driver for ... |
1115 1116 1117 1118 |
/* Branch 0 set of MTR registers */ pci_read_config_word(pvt->branch_0, where, &pvt->b0_mtr[slot_row]); |
956b9ba15 edac: Convert deb... |
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edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x ", slot_row, where, pvt->b0_mtr[slot_row]); |
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1122 1123 1124 1125 1126 1127 1128 1129 1130 |
if (pvt->maxch < CHANNELS_PER_BRANCH) { pvt->b1_mtr[slot_row] = 0; continue; } /* Branch 1 set of MTR registers */ pci_read_config_word(pvt->branch_1, where, &pvt->b1_mtr[slot_row]); |
956b9ba15 edac: Convert deb... |
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edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x ", slot_row, where, pvt->b1_mtr[slot_row]); |
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1134 1135 1136 |
} /* Read and dump branch 0's MTRs */ |
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edac_dbg(2, "Memory Technology Registers: "); edac_dbg(2, " Branch 0: "); |
296da591e i5400_edac: conve... |
1141 |
for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) |
920c8df6a edac: driver for ... |
1142 1143 1144 1145 |
decode_mtr(slot_row, pvt->b0_mtr[slot_row]); pci_read_config_word(pvt->branch_0, AMBPRESENT_0, &pvt->b0_ambpresent0); |
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edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x: ", pvt->b0_ambpresent0); |
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1148 1149 |
pci_read_config_word(pvt->branch_0, AMBPRESENT_1, &pvt->b0_ambpresent1); |
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edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x: ", pvt->b0_ambpresent1); |
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1152 1153 1154 1155 1156 1157 1158 |
/* Only if we have 2 branchs (4 channels) */ if (pvt->maxch < CHANNELS_PER_BRANCH) { pvt->b1_ambpresent0 = 0; pvt->b1_ambpresent1 = 0; } else { /* Read and dump branch 1's MTRs */ |
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edac_dbg(2, " Branch 1: "); |
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for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) |
920c8df6a edac: driver for ... |
1162 1163 1164 1165 |
decode_mtr(slot_row, pvt->b1_mtr[slot_row]); pci_read_config_word(pvt->branch_1, AMBPRESENT_0, &pvt->b1_ambpresent0); |
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edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x: ", pvt->b1_ambpresent0); |
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1169 1170 |
pci_read_config_word(pvt->branch_1, AMBPRESENT_1, &pvt->b1_ambpresent1); |
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edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x: ", pvt->b1_ambpresent1); |
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1174 1175 1176 1177 1178 1179 1180 1181 |
} /* Go and determine the size of each DIMM and place in an * orderly matrix */ calculate_dimm_size(pvt); } /* |
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1182 |
* i5400_init_dimms Initialize the 'dimms' table within |
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* the mci control structure with the * addressing of memory. * * return: * 0 success * 1 no actual memory found on this MC */ |
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1190 |
static int i5400_init_dimms(struct mem_ctl_info *mci) |
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1191 1192 |
{ struct i5400_pvt *pvt; |
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struct dimm_info *dimm; int ndimms, channel_count; int max_dimms; |
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1196 |
int mtr; |
a895bf8b1 edac: move nr_pag... |
1197 |
int size_mb; |
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int channel, slot; |
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1199 1200 1201 1202 |
pvt = mci->pvt_info; channel_count = pvt->maxch; |
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max_dimms = pvt->maxdimmperch; |
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|
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ndimms = 0; |
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|
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/* * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 * layers here. */ for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; channel++) { for (slot = 0; slot < mci->layers[2].size; slot++) { mtr = determine_mtr(pvt, slot, channel); |
920c8df6a edac: driver for ... |
1215 |
|
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/* if no DIMMS on this slot, continue */ if (!MTR_DIMMS_PRESENT(mtr)) continue; |
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1219 |
|
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1220 1221 |
dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, channel / 2, channel % 2, slot); |
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1222 |
|
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size_mb = pvt->dimm_info[slot][channel].megabytes; |
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edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB ", channel / 2, channel % 2, slot, size_mb / 1000, size_mb % 1000); |
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|
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dimm->nr_pages = size_mb << 8; |
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1230 |
dimm->grain = 8; |
e61555c29 EDAC, i5000, i540... |
1231 1232 |
dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ? DEV_X8 : DEV_X4; |
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dimm->mtype = MEM_FB_DDR2; /* * The eccc mechanism is SDDC (aka SECC), with * is similar to Chipkill. */ |
e61555c29 EDAC, i5000, i540... |
1238 |
dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ? |
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EDAC_S8ECD8ED : EDAC_S4ECD4ED; ndimms++; |
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1241 |
} |
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1242 |
} |
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/* * When just one memory is provided, it should be at location (0,0,0). * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. */ if (ndimms == 1) |
de3910eb7 edac: change the ... |
1248 |
mci->dimms[0]->edac_mode = EDAC_SECDED; |
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return (ndimms == 0); |
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} /* * i5400_enable_error_reporting * Turn on the memory reporting features of the hardware */ static void i5400_enable_error_reporting(struct mem_ctl_info *mci) { struct i5400_pvt *pvt; u32 fbd_error_mask; pvt = mci->pvt_info; /* Read the FBD Error Mask Register */ pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, &fbd_error_mask); /* Enable with a '0' */ fbd_error_mask &= ~(ENABLE_EMASK_ALL); pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, fbd_error_mask); } /* |
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* i5400_probe1 Probe for ONE instance of device to see if it is * present. * return: * 0 for FOUND a device * < 0 for error code */ static int i5400_probe1(struct pci_dev *pdev, int dev_idx) { struct mem_ctl_info *mci; struct i5400_pvt *pvt; |
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1286 |
struct edac_mc_layer layers[3]; |
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|
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if (dev_idx >= ARRAY_SIZE(i5400_devs)) return -EINVAL; |
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edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x ", pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
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/* We only are looking for func 0 of the set */ if (PCI_FUNC(pdev->devfn) != 0) return -ENODEV; |
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/* * allocate a new MC control structure * * This drivers uses the DIMM slot as "csrow" and the rest as "channel". |
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1302 |
*/ |
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layers[0].type = EDAC_MC_LAYER_BRANCH; layers[0].size = MAX_BRANCHES; layers[0].is_virt_csrow = false; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = CHANNELS_PER_BRANCH; layers[1].is_virt_csrow = false; layers[2].type = EDAC_MC_LAYER_SLOT; layers[2].size = DIMMS_PER_CHANNEL; layers[2].is_virt_csrow = true; |
ca0907b9e edac: Remove the ... |
1312 |
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
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1313 1314 |
if (mci == NULL) return -ENOMEM; |
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edac_dbg(0, "MC: mci = %p ", mci); |
920c8df6a edac: driver for ... |
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|
fd687502d edac: Rename the ... |
1318 |
mci->pdev = &pdev->dev; /* record ptr to the generic device */ |
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pvt = mci->pvt_info; pvt->system_address = pdev; /* Record this device in our private */ |
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1322 1323 |
pvt->maxch = MAX_CHANNELS; pvt->maxdimmperch = DIMMS_PER_CHANNEL; |
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/* 'get' the pci devices we want to reserve for our use */ if (i5400_get_devices(mci, dev_idx)) goto fail0; /* Time to get serious */ i5400_get_mc_regs(mci); /* retrieve the hardware registers */ mci->mc_idx = 0; mci->mtype_cap = MEM_FLAG_FB_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; mci->edac_cap = EDAC_FLAG_NONE; mci->mod_name = "i5400_edac.c"; mci->mod_ver = I5400_REVISION; mci->ctl_name = i5400_devs[dev_idx].ctl_name; mci->dev_name = pci_name(pdev); mci->ctl_page_to_phys = NULL; /* Set the function pointer to an actual operation function */ mci->edac_check = i5400_check_error; |
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1344 |
/* initialize the MC control structure 'dimms' table |
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1345 |
* with the mapping and control information */ |
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if (i5400_init_dimms(mci)) { |
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edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value "); |
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1349 |
mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ |
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1350 |
} else { |
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edac_dbg(1, "MC: Enable error reporting now "); |
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i5400_enable_error_reporting(mci); } /* add this new MC control structure to EDAC's list of MCs */ if (edac_mc_add_mc(mci)) { |
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edac_dbg(0, "MC: failed edac_mc_add_mc() "); |
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/* FIXME: perhaps some code should go here that disables error * reporting if we just enabled it */ goto fail1; } i5400_clear_error(mci); /* allocating generic PCI control info */ i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); if (!i5400_pci) { printk(KERN_WARNING "%s(): Unable to create PCI control ", __func__); printk(KERN_WARNING "%s(): PCI error report via EDAC not setup ", __func__); } return 0; /* Error exit unwinding stack */ fail1: i5400_put_devices(mci); fail0: edac_mc_free(mci); return -ENODEV; } /* * i5400_init_one constructor for one instance of device * * returns: * negative on error * count (>= 0) */ |
9b3c6e85c Drivers: edac: re... |
1400 |
static int i5400_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
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1401 1402 |
{ int rc; |
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edac_dbg(0, "MC: "); |
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/* wake up device */ rc = pci_enable_device(pdev); |
b425d5c82 edac: i5400: impr... |
1408 |
if (rc) |
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return rc; /* now probe and enable the device */ return i5400_probe1(pdev, id->driver_data); } /* * i5400_remove_one destructor for one instance of device * */ |
9b3c6e85c Drivers: edac: re... |
1419 |
static void i5400_remove_one(struct pci_dev *pdev) |
920c8df6a edac: driver for ... |
1420 1421 |
{ struct mem_ctl_info *mci; |
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edac_dbg(0, " "); |
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if (i5400_pci) edac_pci_release_generic_ctl(i5400_pci); mci = edac_mc_del_mc(&pdev->dev); if (!mci) return; /* retrieve references to resources, and free those resources */ i5400_put_devices(mci); |
c2e650c49 i5400_edac: Disab... |
1434 |
pci_disable_device(pdev); |
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edac_mc_free(mci); } /* * pci_device_id table for which devices we are looking for * * The "E500P" device is the first device supported. */ |
ba935f409 EDAC: Remove DEFI... |
1443 |
static const struct pci_device_id i5400_pci_tbl[] = { |
920c8df6a edac: driver for ... |
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 |
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)}, {0,} /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, i5400_pci_tbl); /* * i5400_driver pci_driver structure for this module * */ static struct pci_driver i5400_driver = { |
8375d4909 edac: driver for ... |
1455 |
.name = "i5400_edac", |
920c8df6a edac: driver for ... |
1456 |
.probe = i5400_init_one, |
9b3c6e85c Drivers: edac: re... |
1457 |
.remove = i5400_remove_one, |
920c8df6a edac: driver for ... |
1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 |
.id_table = i5400_pci_tbl, }; /* * i5400_init Module entry function * Try to initialize this module for its devices */ static int __init i5400_init(void) { int pci_rc; |
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edac_dbg(2, "MC: "); |
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/* Ensure that the OPSTATE is set correctly for POLL or NMI */ opstate_init(); pci_rc = pci_register_driver(&i5400_driver); return (pci_rc < 0) ? pci_rc : 0; } /* * i5400_exit() Module exit function * Unregister the driver */ static void __exit i5400_exit(void) { |
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edac_dbg(2, "MC: "); |
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1487 1488 1489 1490 1491 1492 1493 |
pci_unregister_driver(&i5400_driver); } module_init(i5400_init); module_exit(i5400_exit); MODULE_LICENSE("GPL"); |
8375d4909 edac: driver for ... |
1494 |
MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>"); |
37e59f876 [media, edac] Cha... |
1495 |
MODULE_AUTHOR("Mauro Carvalho Chehab"); |
8375d4909 edac: driver for ... |
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MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " I5400_REVISION); |
920c8df6a edac: driver for ... |
1499 1500 1501 |
module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |