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drivers/edac/i7300_edac.c
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/* * Intel 7300 class Memory Controllers kernel module (Clarksboro) * * This file may be distributed under the terms of the * GNU General Public License version 2 only. * * Copyright (c) 2010 by: |
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* Mauro Carvalho Chehab |
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* * Red Hat Inc. http://www.redhat.com * * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet * http://www.intel.com/Assets/PDF/datasheet/318082.pdf * * TODO: The chipset allow checking for PCI Express errors also. Currently, * the driver covers only memory error errors * * This driver uses "csrows" EDAC attribute to represent DIMM slot# */ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/edac.h> #include <linux/mmzone.h> |
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#include "edac_module.h" |
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/* * Alter this version for the I7300 module when modifications are made */ |
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#define I7300_REVISION " Ver: 1.0.0" |
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#define EDAC_MOD_STR "i7300_edac" #define i7300_printk(level, fmt, arg...) \ edac_printk(level, "i7300", fmt, ##arg) #define i7300_mc_printk(mci, level, fmt, arg...) \ edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) |
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/*********************************************** * i7300 Limit constants Structs and static vars ***********************************************/ |
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/* * Memory topology is organized as: * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) * Each channel can have to 8 DIMM sets (called as SLOTS) * Slots should generally be filled in pairs * Except on Single Channel mode of operation * just slot 0/channel0 filled on this mode * On normal operation mode, the two channels on a branch should be |
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* filled together for the same SLOT# |
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* When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four * channels on both branches should be filled */ /* Limits for i7300 */ #define MAX_SLOTS 8 #define MAX_BRANCHES 2 #define MAX_CH_PER_BRANCH 2 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) #define MAX_MIR 3 #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) #define to_csrow(slot, ch, branch) \ (to_channel(ch, branch) | ((slot) << 2)) |
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/* Device name and register DID (Device ID) */ struct i7300_dev_info { const char *ctl_name; /* name for this device */ u16 fsb_mapping_errors; /* DID for the branchmap,control */ }; /* Table of devices attributes supported by this driver */ static const struct i7300_dev_info i7300_devs[] = { { .ctl_name = "I7300", .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, }, }; struct i7300_dimm_info { int megabytes; /* size, 0 means not present */ }; /* driver private data structure */ struct i7300_pvt { struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ u16 tolm; /* top of low memory */ u64 ambase; /* AMB BAR */ u32 mc_settings; /* Report several settings */ u32 mc_settings_a; u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ |
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u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ |
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u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ /* DIMM information matrix, allocating architecture maximums */ struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; /* Temporary buffer for use when preparing error messages */ char *tmp_prt_buffer; }; /* FIXME: Why do we need to have this static? */ static struct edac_pci_ctl_info *i7300_pci; /*************************************************** * i7300 Register definitions for memory enumeration ***************************************************/ |
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/* |
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* Device 16, * Function 0: System Address (not documented) * Function 1: Memory Branch Map, Control, Errors Register */ |
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/* OFFSETS for Function 0 */ |
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#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ #define MAXCH 0x56 /* Max Channel Number */ #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ |
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/* OFFSETS for Function 1 */ |
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#define MC_SETTINGS 0x40 |
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#define IS_MIRRORED(mc) ((mc) & (1 << 16)) #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) |
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#define MC_SETTINGS_A 0x58 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) |
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#define TOLM 0x6C |
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#define MIR0 0x80 #define MIR1 0x84 #define MIR2 0x88 |
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/* * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it * seems that we cannot use this information directly for the same usage. * Each memory slot may have up to 2 AMB interfaces, one for income and another * for outcome interface to the next slot. * For now, the driver just stores the AMB present registers, but rely only at * the MTR info to detect memory. * Datasheet is also not clear about how to map each AMBPRESENT registers to * one of the 4 available channels. */ #define AMBPRESENT_0 0x64 #define AMBPRESENT_1 0x66 |
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static const u16 mtr_regs[MAX_SLOTS] = { |
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0x80, 0x84, 0x88, 0x8c, 0x82, 0x86, 0x8a, 0x8e }; |
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/* * Defines to extract the vaious fields from the |
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* MTRx - Memory Technology Registers */ #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) #define MTR_DRAM_BANKS_ADDR_BITS 2 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) |
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/************************************************ * i7300 Register definitions for error detection ************************************************/ |
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/* * Device 16.1: FBD Error Registers */ #define FERR_FAT_FBD 0x98 static const char *ferr_fat_fbd_name[] = { [22] = "Non-Redundant Fast Reset Timeout", [2] = ">Tmid Thermal event with intelligent throttling disabled", [1] = "Memory or FBD configuration CRC read error", [0] = "Memory Write error on non-redundant retry or " "FBD configuration Write error on retry", }; |
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#define GET_FBD_FAT_IDX(fbderr) (((fbderr) >> 28) & 3) #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 22)) |
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#define FERR_NF_FBD 0xa0 static const char *ferr_nf_fbd_name[] = { [24] = "DIMM-Spare Copy Completed", [23] = "DIMM-Spare Copy Initiated", [22] = "Redundant Fast Reset Timeout", [21] = "Memory Write error on redundant retry", [18] = "SPD protocol Error", [17] = "FBD Northbound parity error on FBD Sync Status", [16] = "Correctable Patrol Data ECC", [15] = "Correctable Resilver- or Spare-Copy Data ECC", [14] = "Correctable Mirrored Demand Data ECC", [13] = "Correctable Non-Mirrored Demand Data ECC", [11] = "Memory or FBD configuration CRC read error", [10] = "FBD Configuration Write error on first attempt", [9] = "Memory Write error on first attempt", [8] = "Non-Aliased Uncorrectable Patrol Data ECC", [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", [4] = "Aliased Uncorrectable Patrol Data ECC", [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", [0] = "Uncorrectable Data ECC on Replay", }; |
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#define GET_FBD_NF_IDX(fbderr) (((fbderr) >> 28) & 3) |
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#define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ (1 << 1) | (1 << 0)) #define EMASK_FBD 0xa8 #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ (1 << 1) | (1 << 0)) |
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/* * Device 16.2: Global Error Registers */ |
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#define FERR_GLOBAL_HI 0x48 static const char *ferr_global_hi_name[] = { [3] = "FSB 3 Fatal Error", [2] = "FSB 2 Fatal Error", [1] = "FSB 1 Fatal Error", [0] = "FSB 0 Fatal Error", }; #define ferr_global_hi_is_fatal(errno) 1 |
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#define FERR_GLOBAL_LO 0x40 |
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static const char *ferr_global_lo_name[] = { |
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[31] = "Internal MCH Fatal Error", [30] = "Intel QuickData Technology Device Fatal Error", [29] = "FSB1 Fatal Error", [28] = "FSB0 Fatal Error", [27] = "FBD Channel 3 Fatal Error", [26] = "FBD Channel 2 Fatal Error", [25] = "FBD Channel 1 Fatal Error", [24] = "FBD Channel 0 Fatal Error", [23] = "PCI Express Device 7Fatal Error", [22] = "PCI Express Device 6 Fatal Error", [21] = "PCI Express Device 5 Fatal Error", [20] = "PCI Express Device 4 Fatal Error", [19] = "PCI Express Device 3 Fatal Error", [18] = "PCI Express Device 2 Fatal Error", [17] = "PCI Express Device 1 Fatal Error", [16] = "ESI Fatal Error", [15] = "Internal MCH Non-Fatal Error", [14] = "Intel QuickData Technology Device Non Fatal Error", [13] = "FSB1 Non-Fatal Error", [12] = "FSB 0 Non-Fatal Error", [11] = "FBD Channel 3 Non-Fatal Error", [10] = "FBD Channel 2 Non-Fatal Error", [9] = "FBD Channel 1 Non-Fatal Error", [8] = "FBD Channel 0 Non-Fatal Error", [7] = "PCI Express Device 7 Non-Fatal Error", [6] = "PCI Express Device 6 Non-Fatal Error", [5] = "PCI Express Device 5 Non-Fatal Error", [4] = "PCI Express Device 4 Non-Fatal Error", [3] = "PCI Express Device 3 Non-Fatal Error", [2] = "PCI Express Device 2 Non-Fatal Error", [1] = "PCI Express Device 1 Non-Fatal Error", [0] = "ESI Non-Fatal Error", }; |
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#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) |
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|
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#define NRECMEMA 0xbe #define NRECMEMA_BANK(v) (((v) >> 12) & 7) #define NRECMEMA_RANK(v) (((v) >> 8) & 15) #define NRECMEMB 0xc0 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31)) #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff) #define NRECMEMB_RAS(v) ((v) & 0xffff) |
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#define REDMEMA 0xdc |
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#define REDMEMB 0x7c |
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#define RECMEMA 0xe0 #define RECMEMA_BANK(v) (((v) >> 12) & 7) #define RECMEMA_RANK(v) (((v) >> 8) & 15) #define RECMEMB 0xe4 #define RECMEMB_IS_WR(v) ((v) & (1 << 31)) #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff) #define RECMEMB_RAS(v) ((v) & 0xffff) |
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/******************************************** * i7300 Functions related to error detection ********************************************/ |
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/** * get_err_from_table() - Gets the error message from a table * @table: table name (array of char *) * @size: number of elements at the table * @pos: position of the element to be returned * * This is a small routine that gets the pos-th element of a table. If the * element doesn't exist (or it is empty), it returns "reserved". * Instead of calling it directly, the better is to call via the macro * GET_ERR_FROM_TABLE(), that automatically checks the table size via * ARRAY_SIZE() macro */ static const char *get_err_from_table(const char *table[], int size, int pos) |
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{ |
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if (unlikely(pos >= size)) return "Reserved"; if (unlikely(!table[pos])) |
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return "Reserved"; return table[pos]; |
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} |
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#define GET_ERR_FROM_TABLE(table, pos) \ get_err_from_table(table, ARRAY_SIZE(table), pos) |
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/** * i7300_process_error_global() - Retrieve the hardware error information from * the hardware global error registers and * sends it to dmesg * @mci: struct mem_ctl_info pointer |
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*/ |
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static void i7300_process_error_global(struct mem_ctl_info *mci) |
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{ |
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struct i7300_pvt *pvt; |
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u32 errnum, error_reg; |
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unsigned long errors; const char *specific; bool is_fatal; |
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pvt = mci->pvt_info; |
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/* read in the 1st FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_HI, &error_reg); if (unlikely(error_reg)) { errors = error_reg; |
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errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_global_hi_name)); specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); is_fatal = ferr_global_hi_is_fatal(errnum); |
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/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_HI, error_reg); |
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goto error_global; |
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} |
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pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_LO, &error_reg); if (unlikely(error_reg)) { errors = error_reg; |
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errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_global_lo_name)); specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); is_fatal = ferr_global_lo_is_fatal(errnum); |
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/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
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FERR_GLOBAL_LO, error_reg); |
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goto error_global; } return; |
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error_global: i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s ", is_fatal ? "Fatal" : "NOT fatal", specific); |
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} |
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/** * i7300_process_fbd_error() - Retrieve the hardware error information from * the FBD error registers and sends it via * EDAC error API calls * @mci: struct mem_ctl_info pointer |
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*/ |
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static void i7300_process_fbd_error(struct mem_ctl_info *mci) |
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{ struct i7300_pvt *pvt; |
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u32 errnum, value, error_reg; |
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u16 val16; |
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unsigned branch, channel, bank, rank, cas, ras; |
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u32 syndrome; |
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unsigned long errors; const char *specific; |
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bool is_wr; |
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pvt = mci->pvt_info; /* read in the 1st FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
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FERR_FAT_FBD, &error_reg); if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) { errors = error_reg & FERR_FAT_FBD_ERR_MASK ; |
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errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_fat_fbd_name)); specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); |
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branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; |
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pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, NRECMEMA, &val16); bank = NRECMEMA_BANK(val16); rank = NRECMEMA_RANK(val16); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, NRECMEMB, &value); |
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is_wr = NRECMEMB_IS_WR(value); cas = NRECMEMB_CAS(value); ras = NRECMEMB_RAS(value); |
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/* Clean the error register */ pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, error_reg); |
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snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, |
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"Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))", bank, ras, cas, errors, specific); |
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edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0, |
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branch, -1, rank, is_wr ? "Write error" : "Read error", |
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pvt->tmp_prt_buffer); |
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433 434 435 436 |
} /* read in the 1st NON-FATAL error register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
5f032119d i7300_edac: Fix e... |
437 438 439 |
FERR_NF_FBD, &error_reg); if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) { errors = error_reg & FERR_NF_FBD_ERR_MASK; |
57021918a i7300_edac: Add s... |
440 441 442 |
errnum = find_first_bit(&errors, ARRAY_SIZE(ferr_nf_fbd_name)); specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); |
7e06b7a33 i7300_edac: Fix e... |
443 |
branch = (GET_FBD_NF_IDX(error_reg) == 2) ? 1 : 0; |
57021918a i7300_edac: Add s... |
444 |
|
32f947261 i7300_edac: enric... |
445 446 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, REDMEMA, &syndrome); |
32f947261 i7300_edac: enric... |
447 448 449 450 451 452 453 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, RECMEMA, &val16); bank = RECMEMA_BANK(val16); rank = RECMEMA_RANK(val16); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, RECMEMB, &value); |
32f947261 i7300_edac: enric... |
454 455 456 |
is_wr = RECMEMB_IS_WR(value); cas = RECMEMB_CAS(value); ras = RECMEMB_RAS(value); |
8199d8cc6 i7300_edac: enric... |
457 |
|
37b69cf91 i7300_edac: Prope... |
458 459 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, REDMEMB, &value); |
37b69cf91 i7300_edac: Prope... |
460 |
channel = (branch << 1); |
58fb24cb9 EDAC, i7300: Test... |
461 462 463 |
/* Second channel ? */ channel += !!(value & BIT(17)); |
37b69cf91 i7300_edac: Prope... |
464 |
|
5f032119d i7300_edac: Fix e... |
465 466 467 |
/* Clear the error bit */ pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, error_reg); |
32f947261 i7300_edac: enric... |
468 469 |
/* Form out message */ snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, |
70e2a8379 i7300_edac: conve... |
470 471 |
"DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))", bank, ras, cas, errors, specific); |
9eb07a7fb edac: edac_mc_han... |
472 |
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, |
70e2a8379 i7300_edac: conve... |
473 474 475 |
syndrome, branch >> 1, channel % 2, rank, is_wr ? "Write error" : "Read error", |
03f7eae80 edac: remove arch... |
476 |
pvt->tmp_prt_buffer); |
32f947261 i7300_edac: enric... |
477 478 |
} return; |
57021918a i7300_edac: Add s... |
479 |
} |
d091a6eb1 i7300_edac: Impro... |
480 481 482 |
/** * i7300_check_error() - Calls the error checking subroutines * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
483 |
*/ |
f42774224 i7300_edac: Clean... |
484 |
static void i7300_check_error(struct mem_ctl_info *mci) |
5de6e07ed i7300_edac: Add e... |
485 |
{ |
f42774224 i7300_edac: Clean... |
486 487 |
i7300_process_error_global(mci); i7300_process_fbd_error(mci); |
5de6e07ed i7300_edac: Add e... |
488 |
}; |
fcaf780b2 i7300_edac: start... |
489 |
|
d091a6eb1 i7300_edac: Impro... |
490 491 492 |
/** * i7300_clear_error() - Clears the error registers * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
493 494 495 |
*/ static void i7300_clear_error(struct mem_ctl_info *mci) { |
e43276050 i7300_edac: Add a... |
496 497 498 499 500 501 |
struct i7300_pvt *pvt = mci->pvt_info; u32 value; /* * All error values are RWC - we need to read and write 1 to the * bit that we want to cleanup */ |
fcaf780b2 i7300_edac: start... |
502 |
|
e43276050 i7300_edac: Add a... |
503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 |
/* Clear global error registers */ pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_HI, &value); pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_HI, value); pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_LO, &value); pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, FERR_GLOBAL_LO, value); /* Clear FBD error registers */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, &value); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_FAT_FBD, value); pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, &value); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, FERR_NF_FBD, value); |
fcaf780b2 i7300_edac: start... |
524 |
} |
d091a6eb1 i7300_edac: Impro... |
525 526 527 528 |
/** * i7300_enable_error_reporting() - Enable the memory reporting logic at the * hardware * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
529 530 531 |
*/ static void i7300_enable_error_reporting(struct mem_ctl_info *mci) { |
57021918a i7300_edac: Add s... |
532 533 534 535 536 537 538 539 540 541 542 543 |
struct i7300_pvt *pvt = mci->pvt_info; u32 fbd_error_mask; /* Read the FBD Error Mask Register */ pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, EMASK_FBD, &fbd_error_mask); /* Enable with a '0' */ fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, EMASK_FBD, fbd_error_mask); |
fcaf780b2 i7300_edac: start... |
544 |
} |
5de6e07ed i7300_edac: Add e... |
545 546 547 548 |
/************************************************ * i7300 Functions related to memory enumberation ************************************************/ |
fcaf780b2 i7300_edac: start... |
549 |
|
d091a6eb1 i7300_edac: Impro... |
550 551 552 553 554 555 556 557 |
/** * decode_mtr() - Decodes the MTR descriptor, filling the edac structs * @pvt: pointer to the private data struct used by i7300 driver * @slot: DIMM slot (0 to 7) * @ch: Channel number within the branch (0 or 1) * @branch: Branch number (0 or 1) * @dinfo: Pointer to DIMM info where dimm size is stored * @p_csrow: Pointer to the struct csrow_info that corresponds to that element |
fcaf780b2 i7300_edac: start... |
558 559 560 561 |
*/ static int decode_mtr(struct i7300_pvt *pvt, int slot, int ch, int branch, struct i7300_dimm_info *dinfo, |
a895bf8b1 edac: move nr_pag... |
562 |
struct dimm_info *dimm) |
fcaf780b2 i7300_edac: start... |
563 564 565 566 567 568 569 |
{ int mtr, ans, addrBits, channel; channel = to_channel(ch, branch); mtr = pvt->mtr[slot][branch]; ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; |
956b9ba15 edac: Convert deb... |
570 571 572 |
edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr) ", slot, channel, ans ? "" : "NOT "); |
fcaf780b2 i7300_edac: start... |
573 574 |
/* Determine if there is a DIMM present in this DIMM slot */ |
fcaf780b2 i7300_edac: start... |
575 576 |
if (!ans) return 0; |
fcaf780b2 i7300_edac: start... |
577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 |
/* Start with the number of bits for a Bank * on the DRAM */ addrBits = MTR_DRAM_BANKS_ADDR_BITS; /* Add thenumber of ROW bits */ addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); /* add the number of COLUMN bits */ addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); /* add the number of RANK bits */ addrBits += MTR_DIMM_RANKS(mtr); addrBits += 6; /* add 64 bits per DIMM */ addrBits -= 20; /* divide by 2^^20 */ addrBits -= 3; /* 8 bits per bytes */ dinfo->megabytes = 1 << addrBits; |
956b9ba15 edac: Convert deb... |
593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 |
edac_dbg(2, "\t\tWIDTH: x%d ", MTR_DRAM_WIDTH(mtr)); edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s ", MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); edac_dbg(2, "\t\tNUMBANK: %d bank(s) ", MTR_DRAM_BANKS(mtr)); edac_dbg(2, "\t\tNUMRANK: %s ", MTR_DIMM_RANKS(mtr) ? "double" : "single"); edac_dbg(2, "\t\tNUMROW: %s ", MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : "65,536 - 16 rows"); edac_dbg(2, "\t\tNUMCOL: %s ", MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : "reserved"); edac_dbg(2, "\t\tSIZE: %d MB ", dinfo->megabytes); |
fcaf780b2 i7300_edac: start... |
619 |
|
116389ed2 i7300_edac: Add a... |
620 |
/* |
15154c57c i7300_edac: Prope... |
621 |
* The type of error detection actually depends of the |
116389ed2 i7300_edac: Add a... |
622 |
* mode of operation. When it is just one single memory chip, at |
15154c57c i7300_edac: Prope... |
623 624 |
* socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. * In normal or mirrored mode, it uses Lockstep mode, |
116389ed2 i7300_edac: Add a... |
625 626 627 |
* with the possibility of using an extended algorithm for x8 memories * See datasheet Sections 7.3.6 to 7.3.8 */ |
15154c57c i7300_edac: Prope... |
628 |
|
a895bf8b1 edac: move nr_pag... |
629 |
dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes); |
084a4fcce edac: move dimm p... |
630 631 |
dimm->grain = 8; dimm->mtype = MEM_FB_DDR2; |
15154c57c i7300_edac: Prope... |
632 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) { |
084a4fcce edac: move dimm p... |
633 |
dimm->edac_mode = EDAC_SECDED; |
956b9ba15 edac: Convert deb... |
634 635 |
edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code "); |
15154c57c i7300_edac: Prope... |
636 |
} else { |
956b9ba15 edac: Convert deb... |
637 638 |
edac_dbg(2, "\t\tECC code is on Lockstep mode "); |
28c2ce7c8 i7300_edac: Fix M... |
639 |
if (MTR_DRAM_WIDTH(mtr) == 8) |
084a4fcce edac: move dimm p... |
640 |
dimm->edac_mode = EDAC_S8ECD8ED; |
15154c57c i7300_edac: Prope... |
641 |
else |
084a4fcce edac: move dimm p... |
642 |
dimm->edac_mode = EDAC_S4ECD4ED; |
15154c57c i7300_edac: Prope... |
643 |
} |
fcaf780b2 i7300_edac: start... |
644 645 |
/* ask what device type on this row */ |
28c2ce7c8 i7300_edac: Fix M... |
646 |
if (MTR_DRAM_WIDTH(mtr) == 8) { |
956b9ba15 edac: Convert deb... |
647 648 649 650 |
edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode ", IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? "enhanced" : "normal"); |
d7de2bdb0 i7300_edac: Adds ... |
651 |
|
084a4fcce edac: move dimm p... |
652 |
dimm->dtype = DEV_X8; |
d7de2bdb0 i7300_edac: Adds ... |
653 |
} else |
084a4fcce edac: move dimm p... |
654 |
dimm->dtype = DEV_X4; |
fcaf780b2 i7300_edac: start... |
655 656 657 |
return mtr; } |
d091a6eb1 i7300_edac: Impro... |
658 659 660 |
/** * print_dimm_size() - Prints dump of the memory organization * @pvt: pointer to the private data struct used by i7300 driver |
fcaf780b2 i7300_edac: start... |
661 |
* |
d091a6eb1 i7300_edac: Impro... |
662 |
* Useful for debug. If debug is disabled, this routine do nothing |
fcaf780b2 i7300_edac: start... |
663 664 665 |
*/ static void print_dimm_size(struct i7300_pvt *pvt) { |
d091a6eb1 i7300_edac: Impro... |
666 |
#ifdef CONFIG_EDAC_DEBUG |
fcaf780b2 i7300_edac: start... |
667 |
struct i7300_dimm_info *dinfo; |
85580ea4f i7300_edac: pre-a... |
668 |
char *p; |
fcaf780b2 i7300_edac: start... |
669 670 671 672 |
int space, n; int channel, slot; space = PAGE_SIZE; |
85580ea4f i7300_edac: pre-a... |
673 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
674 675 676 677 678 679 680 681 682 |
n = snprintf(p, space, " "); p += n; space -= n; for (channel = 0; channel < MAX_CHANNELS; channel++) { n = snprintf(p, space, "channel %d | ", channel); p += n; space -= n; } |
956b9ba15 edac: Convert deb... |
683 684 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
685 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
686 687 |
space = PAGE_SIZE; n = snprintf(p, space, "-------------------------------" |
9c6f6b65d i7300-edac: Codin... |
688 |
"------------------------------"); |
fcaf780b2 i7300_edac: start... |
689 690 |
p += n; space -= n; |
956b9ba15 edac: Convert deb... |
691 692 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
693 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
694 695 696 697 698 699 700 701 702 703 704 705 706 |
space = PAGE_SIZE; for (slot = 0; slot < MAX_SLOTS; slot++) { n = snprintf(p, space, "csrow/SLOT %d ", slot); p += n; space -= n; for (channel = 0; channel < MAX_CHANNELS; channel++) { dinfo = &pvt->dimm_info[slot][channel]; n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); p += n; space -= n; } |
956b9ba15 edac: Convert deb... |
707 708 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
709 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
710 711 712 713 |
space = PAGE_SIZE; } n = snprintf(p, space, "-------------------------------" |
9c6f6b65d i7300-edac: Codin... |
714 |
"------------------------------"); |
fcaf780b2 i7300_edac: start... |
715 716 |
p += n; space -= n; |
956b9ba15 edac: Convert deb... |
717 718 |
edac_dbg(2, "%s ", pvt->tmp_prt_buffer); |
85580ea4f i7300_edac: pre-a... |
719 |
p = pvt->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
720 |
space = PAGE_SIZE; |
d091a6eb1 i7300_edac: Impro... |
721 |
#endif |
fcaf780b2 i7300_edac: start... |
722 |
} |
d091a6eb1 i7300_edac: Impro... |
723 724 725 726 727 |
/** * i7300_init_csrows() - Initialize the 'csrows' table within * the mci control structure with the * addressing of memory. * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
728 729 730 731 732 |
*/ static int i7300_init_csrows(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; struct i7300_dimm_info *dinfo; |
d091a6eb1 i7300_edac: Impro... |
733 |
int rc = -ENODEV; |
fcaf780b2 i7300_edac: start... |
734 |
int mtr; |
33ad41263 i7300_edac: Fix m... |
735 |
int ch, branch, slot, channel, max_channel, max_branch; |
084a4fcce edac: move dimm p... |
736 |
struct dimm_info *dimm; |
fcaf780b2 i7300_edac: start... |
737 738 |
pvt = mci->pvt_info; |
956b9ba15 edac: Convert deb... |
739 740 |
edac_dbg(2, "Memory Technology Registers: "); |
fcaf780b2 i7300_edac: start... |
741 |
|
33ad41263 i7300_edac: Fix m... |
742 743 744 745 746 747 748 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) { max_branch = 1; max_channel = 1; } else { max_branch = MAX_BRANCHES; max_channel = MAX_CH_PER_BRANCH; } |
fcaf780b2 i7300_edac: start... |
749 |
/* Get the AMB present registers for the four channels */ |
33ad41263 i7300_edac: Fix m... |
750 |
for (branch = 0; branch < max_branch; branch++) { |
fcaf780b2 i7300_edac: start... |
751 752 |
/* Read and dump branch 0's MTRs */ channel = to_channel(0, branch); |
9c6f6b65d i7300-edac: Codin... |
753 754 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0, |
fcaf780b2 i7300_edac: start... |
755 |
&pvt->ambpresent[channel]); |
956b9ba15 edac: Convert deb... |
756 757 758 |
edac_dbg(2, "\t\tAMB-present CH%d = 0x%x: ", channel, pvt->ambpresent[channel]); |
fcaf780b2 i7300_edac: start... |
759 |
|
33ad41263 i7300_edac: Fix m... |
760 761 |
if (max_channel == 1) continue; |
fcaf780b2 i7300_edac: start... |
762 |
channel = to_channel(1, branch); |
9c6f6b65d i7300-edac: Codin... |
763 764 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1, |
fcaf780b2 i7300_edac: start... |
765 |
&pvt->ambpresent[channel]); |
956b9ba15 edac: Convert deb... |
766 767 768 |
edac_dbg(2, "\t\tAMB-present CH%d = 0x%x: ", channel, pvt->ambpresent[channel]); |
fcaf780b2 i7300_edac: start... |
769 770 771 772 773 |
} /* Get the set of MTR[0-7] regs by each branch */ for (slot = 0; slot < MAX_SLOTS; slot++) { int where = mtr_regs[slot]; |
33ad41263 i7300_edac: Fix m... |
774 |
for (branch = 0; branch < max_branch; branch++) { |
3e57eef64 i7300_edac: Bette... |
775 |
pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], |
fcaf780b2 i7300_edac: start... |
776 777 |
where, &pvt->mtr[slot][branch]); |
33ad41263 i7300_edac: Fix m... |
778 |
for (ch = 0; ch < max_channel; ch++) { |
fcaf780b2 i7300_edac: start... |
779 |
int channel = to_channel(ch, branch); |
70e2a8379 i7300_edac: conve... |
780 781 |
dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, branch, ch, slot); |
fcaf780b2 i7300_edac: start... |
782 |
|
70e2a8379 i7300_edac: conve... |
783 |
dinfo = &pvt->dimm_info[slot][channel]; |
084a4fcce edac: move dimm p... |
784 |
|
fcaf780b2 i7300_edac: start... |
785 |
mtr = decode_mtr(pvt, slot, ch, branch, |
a895bf8b1 edac: move nr_pag... |
786 |
dinfo, dimm); |
fcaf780b2 i7300_edac: start... |
787 788 789 |
/* if no DIMMS on this row, continue */ if (!MTR_DIMMS_PRESENT(mtr)) continue; |
d091a6eb1 i7300_edac: Impro... |
790 |
rc = 0; |
a895bf8b1 edac: move nr_pag... |
791 |
|
fcaf780b2 i7300_edac: start... |
792 793 794 |
} } } |
d091a6eb1 i7300_edac: Impro... |
795 |
return rc; |
fcaf780b2 i7300_edac: start... |
796 |
} |
d091a6eb1 i7300_edac: Impro... |
797 798 799 800 801 |
/** * decode_mir() - Decodes Memory Interleave Register (MIR) info * @int mir_no: number of the MIR register to decode * @mir: array with the MIR data cached on the driver */ |
fcaf780b2 i7300_edac: start... |
802 803 804 |
static void decode_mir(int mir_no, u16 mir[MAX_MIR]) { if (mir[mir_no] & 3) |
956b9ba15 edac: Convert deb... |
805 806 807 808 809 810 |
edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s ", mir_no, (mir[mir_no] >> 4) & 0xfff, (mir[mir_no] & 1) ? "B0" : "", (mir[mir_no] & 2) ? "B1" : ""); |
fcaf780b2 i7300_edac: start... |
811 |
} |
d091a6eb1 i7300_edac: Impro... |
812 813 814 |
/** * i7300_get_mc_regs() - Get the contents of the MC enumeration registers * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
815 |
* |
d091a6eb1 i7300_edac: Impro... |
816 |
* Data read is cached internally for its usage when needed |
fcaf780b2 i7300_edac: start... |
817 818 819 820 821 822 823 824 |
*/ static int i7300_get_mc_regs(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; u32 actual_tolm; int i, rc; pvt = mci->pvt_info; |
3e57eef64 i7300_edac: Bette... |
825 |
pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, |
fcaf780b2 i7300_edac: start... |
826 |
(u32 *) &pvt->ambase); |
956b9ba15 edac: Convert deb... |
827 828 |
edac_dbg(2, "AMBASE= 0x%lx ", (long unsigned int)pvt->ambase); |
fcaf780b2 i7300_edac: start... |
829 830 |
/* Get the Branch Map regs */ |
3e57eef64 i7300_edac: Bette... |
831 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); |
fcaf780b2 i7300_edac: start... |
832 |
pvt->tolm >>= 12; |
956b9ba15 edac: Convert deb... |
833 834 835 |
edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x) ", pvt->tolm, pvt->tolm); |
fcaf780b2 i7300_edac: start... |
836 837 |
actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); |
956b9ba15 edac: Convert deb... |
838 839 840 |
edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x) ", actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); |
fcaf780b2 i7300_edac: start... |
841 |
|
af3d8831e i7300_edac: displ... |
842 |
/* Get memory controller settings */ |
3e57eef64 i7300_edac: Bette... |
843 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, |
af3d8831e i7300_edac: displ... |
844 |
&pvt->mc_settings); |
bb81a2163 i7300_edac: Detec... |
845 846 |
pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, &pvt->mc_settings_a); |
d7de2bdb0 i7300_edac: Adds ... |
847 |
|
bb81a2163 i7300_edac: Detec... |
848 |
if (IS_SINGLE_MODE(pvt->mc_settings_a)) |
956b9ba15 edac: Convert deb... |
849 850 |
edac_dbg(0, "Memory controller operating on single mode "); |
bb81a2163 i7300_edac: Detec... |
851 |
else |
956b9ba15 edac: Convert deb... |
852 853 854 |
edac_dbg(0, "Memory controller operating on %smirrored mode ", IS_MIRRORED(pvt->mc_settings) ? "" : "non-"); |
bb81a2163 i7300_edac: Detec... |
855 |
|
956b9ba15 edac: Convert deb... |
856 857 858 859 860 861 |
edac_dbg(0, "Error detection is %s ", IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); edac_dbg(0, "Retry is %s ", IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); |
af3d8831e i7300_edac: displ... |
862 863 |
/* Get Memory Interleave Range registers */ |
9c6f6b65d i7300-edac: Codin... |
864 865 866 867 868 869 |
pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]); pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]); pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]); |
fcaf780b2 i7300_edac: start... |
870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 |
/* Decode the MIR regs */ for (i = 0; i < MAX_MIR; i++) decode_mir(i, pvt->mir); rc = i7300_init_csrows(mci); if (rc < 0) return rc; /* Go and determine the size of each DIMM and place in an * orderly matrix */ print_dimm_size(pvt); return 0; } |
5de6e07ed i7300_edac: Add e... |
885 886 887 |
/************************************************* * i7300 Functions related to device probe/release *************************************************/ |
d091a6eb1 i7300_edac: Impro... |
888 889 890 |
/** * i7300_put_devices() - Release the PCI devices * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
891 892 893 894 895 896 897 898 899 900 |
*/ static void i7300_put_devices(struct mem_ctl_info *mci) { struct i7300_pvt *pvt; int branch; pvt = mci->pvt_info; /* Decrement usage count for devices */ for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) |
3e57eef64 i7300_edac: Bette... |
901 902 903 |
pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); |
fcaf780b2 i7300_edac: start... |
904 |
} |
d091a6eb1 i7300_edac: Impro... |
905 906 907 908 |
/** * i7300_get_devices() - Find and perform 'get' operation on the MCH's * device/functions we want to reference for this driver * @mci: struct mem_ctl_info pointer |
fcaf780b2 i7300_edac: start... |
909 |
* |
d091a6eb1 i7300_edac: Impro... |
910 911 912 913 914 |
* Access and prepare the several devices for usage: * I7300 devices used by this driver: * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 |
fcaf780b2 i7300_edac: start... |
915 |
*/ |
9b3c6e85c Drivers: edac: re... |
916 |
static int i7300_get_devices(struct mem_ctl_info *mci) |
fcaf780b2 i7300_edac: start... |
917 918 919 920 921 922 923 924 |
{ struct i7300_pvt *pvt; struct pci_dev *pdev; pvt = mci->pvt_info; /* Attempt to 'get' the MCH register we want */ pdev = NULL; |
75135da0d i7300_edac: Fix d... |
925 926 927 |
while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev))) { |
fcaf780b2 i7300_edac: start... |
928 929 930 |
/* Store device 16 funcs 1 and 2 */ switch (PCI_FUNC(pdev->devfn)) { case 1: |
75135da0d i7300_edac: Fix d... |
931 932 933 |
if (!pvt->pci_dev_16_1_fsb_addr_map) pvt->pci_dev_16_1_fsb_addr_map = pci_dev_get(pdev); |
fcaf780b2 i7300_edac: start... |
934 935 |
break; case 2: |
75135da0d i7300_edac: Fix d... |
936 937 938 |
if (!pvt->pci_dev_16_2_fsb_err_regs) pvt->pci_dev_16_2_fsb_err_regs = pci_dev_get(pdev); |
fcaf780b2 i7300_edac: start... |
939 940 941 |
break; } } |
75135da0d i7300_edac: Fix d... |
942 943 944 945 946 947 948 949 950 951 952 |
if (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) { /* At least one device was not found */ i7300_printk(KERN_ERR, "'system address,Process Bus' device not found:" "vendor 0x%x device 0x%x ERR funcs (broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); goto error; } |
956b9ba15 edac: Convert deb... |
953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 |
edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x ", pci_name(pvt->pci_dev_16_0_fsb_ctlr), pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device); edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x ", pci_name(pvt->pci_dev_16_1_fsb_addr_map), pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device); edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x ", pci_name(pvt->pci_dev_16_2_fsb_err_regs), pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device); |
fcaf780b2 i7300_edac: start... |
968 |
|
3e57eef64 i7300_edac: Bette... |
969 |
pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, |
9c6f6b65d i7300-edac: Codin... |
970 |
PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, |
fcaf780b2 i7300_edac: start... |
971 |
NULL); |
3e57eef64 i7300_edac: Bette... |
972 |
if (!pvt->pci_dev_2x_0_fbd_branch[0]) { |
fcaf780b2 i7300_edac: start... |
973 974 975 976 977 978 979 |
i7300_printk(KERN_ERR, "MC: 'BRANCH 0' device not found:" "vendor 0x%x device 0x%x Func 0 (broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); goto error; } |
3e57eef64 i7300_edac: Bette... |
980 |
pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b2 i7300_edac: start... |
981 982 |
PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, NULL); |
3e57eef64 i7300_edac: Bette... |
983 |
if (!pvt->pci_dev_2x_0_fbd_branch[1]) { |
fcaf780b2 i7300_edac: start... |
984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 |
i7300_printk(KERN_ERR, "MC: 'BRANCH 1' device not found:" "vendor 0x%x device 0x%x Func 0 " "(broken BIOS?) ", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); goto error; } return 0; error: i7300_put_devices(mci); return -ENODEV; } |
d091a6eb1 i7300_edac: Impro... |
1000 1001 1002 1003 |
/** * i7300_init_one() - Probe for one instance of the device * @pdev: struct pci_dev pointer * @id: struct pci_device_id pointer - currently unused |
fcaf780b2 i7300_edac: start... |
1004 |
*/ |
9b3c6e85c Drivers: edac: re... |
1005 |
static int i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
fcaf780b2 i7300_edac: start... |
1006 1007 |
{ struct mem_ctl_info *mci; |
70e2a8379 i7300_edac: conve... |
1008 |
struct edac_mc_layer layers[3]; |
fcaf780b2 i7300_edac: start... |
1009 |
struct i7300_pvt *pvt; |
d091a6eb1 i7300_edac: Impro... |
1010 |
int rc; |
fcaf780b2 i7300_edac: start... |
1011 |
|
d091a6eb1 i7300_edac: Impro... |
1012 1013 1014 1015 |
/* wake up device */ rc = pci_enable_device(pdev); if (rc == -EIO) return rc; |
fcaf780b2 i7300_edac: start... |
1016 |
|
956b9ba15 edac: Convert deb... |
1017 1018 1019 1020 |
edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x ", pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); |
fcaf780b2 i7300_edac: start... |
1021 1022 1023 1024 |
/* We only are looking for func 0 of the set */ if (PCI_FUNC(pdev->devfn) != 0) return -ENODEV; |
fcaf780b2 i7300_edac: start... |
1025 |
/* allocate a new MC control structure */ |
70e2a8379 i7300_edac: conve... |
1026 1027 1028 1029 1030 1031 1032 1033 1034 |
layers[0].type = EDAC_MC_LAYER_BRANCH; layers[0].size = MAX_BRANCHES; layers[0].is_virt_csrow = false; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = MAX_CH_PER_BRANCH; layers[1].is_virt_csrow = true; layers[2].type = EDAC_MC_LAYER_SLOT; layers[2].size = MAX_SLOTS; layers[2].is_virt_csrow = true; |
ca0907b9e edac: Remove the ... |
1035 |
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
fcaf780b2 i7300_edac: start... |
1036 1037 |
if (mci == NULL) return -ENOMEM; |
956b9ba15 edac: Convert deb... |
1038 1039 |
edac_dbg(0, "MC: mci = %p ", mci); |
fcaf780b2 i7300_edac: start... |
1040 |
|
fd687502d edac: Rename the ... |
1041 |
mci->pdev = &pdev->dev; /* record ptr to the generic device */ |
fcaf780b2 i7300_edac: start... |
1042 1043 |
pvt = mci->pvt_info; |
3e57eef64 i7300_edac: Bette... |
1044 |
pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ |
fcaf780b2 i7300_edac: start... |
1045 |
|
85580ea4f i7300_edac: pre-a... |
1046 1047 1048 1049 1050 |
pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); if (!pvt->tmp_prt_buffer) { edac_mc_free(mci); return -ENOMEM; } |
fcaf780b2 i7300_edac: start... |
1051 |
/* 'get' the pci devices we want to reserve for our use */ |
d091a6eb1 i7300_edac: Impro... |
1052 |
if (i7300_get_devices(mci)) |
fcaf780b2 i7300_edac: start... |
1053 1054 1055 1056 1057 1058 1059 1060 |
goto fail0; mci->mc_idx = 0; mci->mtype_cap = MEM_FLAG_FB_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; mci->edac_cap = EDAC_FLAG_NONE; mci->mod_name = "i7300_edac.c"; mci->mod_ver = I7300_REVISION; |
d091a6eb1 i7300_edac: Impro... |
1061 |
mci->ctl_name = i7300_devs[0].ctl_name; |
fcaf780b2 i7300_edac: start... |
1062 1063 |
mci->dev_name = pci_name(pdev); mci->ctl_page_to_phys = NULL; |
fcaf780b2 i7300_edac: start... |
1064 1065 |
/* Set the function pointer to an actual operation function */ mci->edac_check = i7300_check_error; |
fcaf780b2 i7300_edac: start... |
1066 1067 1068 1069 |
/* initialize the MC control structure 'csrows' table * with the mapping and control information */ if (i7300_get_mc_regs(mci)) { |
956b9ba15 edac: Convert deb... |
1070 1071 |
edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value "); |
fcaf780b2 i7300_edac: start... |
1072 1073 |
mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ } else { |
956b9ba15 edac: Convert deb... |
1074 1075 |
edac_dbg(1, "MC: Enable error reporting now "); |
fcaf780b2 i7300_edac: start... |
1076 |
i7300_enable_error_reporting(mci); |
fcaf780b2 i7300_edac: start... |
1077 1078 1079 1080 |
} /* add this new MC control structure to EDAC's list of MCs */ if (edac_mc_add_mc(mci)) { |
956b9ba15 edac: Convert deb... |
1081 1082 |
edac_dbg(0, "MC: failed edac_mc_add_mc() "); |
fcaf780b2 i7300_edac: start... |
1083 1084 1085 1086 1087 |
/* FIXME: perhaps some code should go here that disables error * reporting if we just enabled it */ goto fail1; } |
fcaf780b2 i7300_edac: start... |
1088 |
i7300_clear_error(mci); |
fcaf780b2 i7300_edac: start... |
1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 |
/* allocating generic PCI control info */ i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); if (!i7300_pci) { printk(KERN_WARNING "%s(): Unable to create PCI control ", __func__); printk(KERN_WARNING "%s(): PCI error report via EDAC not setup ", __func__); } return 0; /* Error exit unwinding stack */ fail1: i7300_put_devices(mci); fail0: |
85580ea4f i7300_edac: pre-a... |
1111 |
kfree(pvt->tmp_prt_buffer); |
fcaf780b2 i7300_edac: start... |
1112 1113 1114 |
edac_mc_free(mci); return -ENODEV; } |
d091a6eb1 i7300_edac: Impro... |
1115 1116 1117 |
/** * i7300_remove_one() - Remove the driver * @pdev: struct pci_dev pointer |
fcaf780b2 i7300_edac: start... |
1118 |
*/ |
9b3c6e85c Drivers: edac: re... |
1119 |
static void i7300_remove_one(struct pci_dev *pdev) |
fcaf780b2 i7300_edac: start... |
1120 1121 |
{ struct mem_ctl_info *mci; |
85580ea4f i7300_edac: pre-a... |
1122 |
char *tmp; |
fcaf780b2 i7300_edac: start... |
1123 |
|
956b9ba15 edac: Convert deb... |
1124 1125 |
edac_dbg(0, " "); |
fcaf780b2 i7300_edac: start... |
1126 1127 1128 1129 1130 1131 1132 |
if (i7300_pci) edac_pci_release_generic_ctl(i7300_pci); mci = edac_mc_del_mc(&pdev->dev); if (!mci) return; |
85580ea4f i7300_edac: pre-a... |
1133 |
tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer; |
fcaf780b2 i7300_edac: start... |
1134 1135 |
/* retrieve references to resources, and free those resources */ i7300_put_devices(mci); |
85580ea4f i7300_edac: pre-a... |
1136 |
kfree(tmp); |
fcaf780b2 i7300_edac: start... |
1137 1138 1139 1140 |
edac_mc_free(mci); } /* |
d091a6eb1 i7300_edac: Impro... |
1141 |
* pci_device_id: table for which devices we are looking for |
fcaf780b2 i7300_edac: start... |
1142 |
* |
d091a6eb1 i7300_edac: Impro... |
1143 |
* Has only 8086:360c PCI ID |
fcaf780b2 i7300_edac: start... |
1144 |
*/ |
ba935f409 EDAC: Remove DEFI... |
1145 |
static const struct pci_device_id i7300_pci_tbl[] = { |
fcaf780b2 i7300_edac: start... |
1146 1147 1148 1149 1150 1151 1152 |
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, {0,} /* 0 terminated list. */ }; MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); /* |
d091a6eb1 i7300_edac: Impro... |
1153 |
* i7300_driver: pci_driver structure for this module |
fcaf780b2 i7300_edac: start... |
1154 1155 1156 1157 |
*/ static struct pci_driver i7300_driver = { .name = "i7300_edac", .probe = i7300_init_one, |
9b3c6e85c Drivers: edac: re... |
1158 |
.remove = i7300_remove_one, |
fcaf780b2 i7300_edac: start... |
1159 1160 |
.id_table = i7300_pci_tbl, }; |
d091a6eb1 i7300_edac: Impro... |
1161 1162 |
/** * i7300_init() - Registers the driver |
fcaf780b2 i7300_edac: start... |
1163 1164 1165 1166 |
*/ static int __init i7300_init(void) { int pci_rc; |
956b9ba15 edac: Convert deb... |
1167 1168 |
edac_dbg(2, " "); |
fcaf780b2 i7300_edac: start... |
1169 1170 1171 1172 1173 1174 1175 1176 |
/* Ensure that the OPSTATE is set correctly for POLL or NMI */ opstate_init(); pci_rc = pci_register_driver(&i7300_driver); return (pci_rc < 0) ? pci_rc : 0; } |
d091a6eb1 i7300_edac: Impro... |
1177 1178 |
/** * i7300_init() - Unregisters the driver |
fcaf780b2 i7300_edac: start... |
1179 1180 1181 |
*/ static void __exit i7300_exit(void) { |
956b9ba15 edac: Convert deb... |
1182 1183 |
edac_dbg(2, " "); |
fcaf780b2 i7300_edac: start... |
1184 1185 1186 1187 1188 1189 1190 |
pci_unregister_driver(&i7300_driver); } module_init(i7300_init); module_exit(i7300_exit); MODULE_LICENSE("GPL"); |
37e59f876 [media, edac] Cha... |
1191 |
MODULE_AUTHOR("Mauro Carvalho Chehab"); |
fcaf780b2 i7300_edac: start... |
1192 1193 1194 1195 1196 1197 |
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " I7300_REVISION); module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |