Blame view
drivers/edac/tile_edac.c
6.39 KB
5c7707554 drivers/edac: pro... |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
/* * Copyright 2011 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. * Tilera-specific EDAC driver. * * This source code is derived from the following driver: * * Cell MIC driver for ECC counting * * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. * <benh@kernel.crashing.org> * */ #include <linux/module.h> #include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/uaccess.h> #include <linux/edac.h> #include <hv/hypervisor.h> #include <hv/drv_mshim_intf.h> |
78d88e8a3 edac: rename edac... |
32 |
#include "edac_module.h" |
5c7707554 drivers/edac: pro... |
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 |
#define DRV_NAME "tile-edac" /* Number of cs_rows needed per memory controller on TILEPro. */ #define TILE_EDAC_NR_CSROWS 1 /* Number of channels per memory controller on TILEPro. */ #define TILE_EDAC_NR_CHANS 1 /* Granularity of reported error in bytes on TILEPro. */ #define TILE_EDAC_ERROR_GRAIN 8 /* TILE processor has multiple independent memory controllers. */ struct platform_device *mshim_pdev[TILE_MAX_MSHIMS]; struct tile_edac_priv { int hv_devhdl; /* Hypervisor device handle. */ int node; /* Memory controller instance #. */ unsigned int ce_count; /* * Correctable-error counter * kept by the driver. */ }; static void tile_edac_check(struct mem_ctl_info *mci) { struct tile_edac_priv *priv = mci->pvt_info; struct mshim_mem_error mem_error; if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_error, sizeof(struct mshim_mem_error), MSHIM_MEM_ERROR_OFF) != sizeof(struct mshim_mem_error)) { pr_err(DRV_NAME ": MSHIM_MEM_ERROR_OFF pread failure. "); return; } /* Check if the current error count is different from the saved one. */ if (mem_error.sbe_count != priv->ce_count) { |
fd687502d edac: Rename the ... |
72 73 |
dev_dbg(mci->pdev, "ECC CE err on node %d ", priv->node); |
5c7707554 drivers/edac: pro... |
74 |
priv->ce_count = mem_error.sbe_count; |
9eb07a7fb edac: edac_mc_han... |
75 |
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
40467db77 tile_edac: conver... |
76 77 |
0, 0, 0, 0, 0, -1, |
03f7eae80 edac: remove arch... |
78 |
mci->ctl_name, ""); |
5c7707554 drivers/edac: pro... |
79 80 81 82 83 84 85 |
} } /* * Initialize the 'csrows' table within the mci control structure with the * addressing of memory. */ |
9b3c6e85c Drivers: edac: re... |
86 |
static int tile_edac_init_csrows(struct mem_ctl_info *mci) |
5c7707554 drivers/edac: pro... |
87 |
{ |
de3910eb7 edac: change the ... |
88 |
struct csrow_info *csrow = mci->csrows[0]; |
5c7707554 drivers/edac: pro... |
89 90 |
struct tile_edac_priv *priv = mci->pvt_info; struct mshim_mem_info mem_info; |
de3910eb7 edac: change the ... |
91 |
struct dimm_info *dimm = csrow->channels[0]->dimm; |
5c7707554 drivers/edac: pro... |
92 93 94 95 96 97 98 99 100 101 |
if (hv_dev_pread(priv->hv_devhdl, 0, (HV_VirtAddr)&mem_info, sizeof(struct mshim_mem_info), MSHIM_MEM_INFO_OFF) != sizeof(struct mshim_mem_info)) { pr_err(DRV_NAME ": MSHIM_MEM_INFO_OFF pread failure. "); return -1; } if (mem_info.mem_ecc) |
084a4fcce edac: move dimm p... |
102 |
dimm->edac_mode = EDAC_SECDED; |
5c7707554 drivers/edac: pro... |
103 |
else |
084a4fcce edac: move dimm p... |
104 |
dimm->edac_mode = EDAC_NONE; |
5c7707554 drivers/edac: pro... |
105 106 |
switch (mem_info.mem_type) { case DDR2: |
084a4fcce edac: move dimm p... |
107 |
dimm->mtype = MEM_DDR2; |
5c7707554 drivers/edac: pro... |
108 109 110 |
break; case DDR3: |
084a4fcce edac: move dimm p... |
111 |
dimm->mtype = MEM_DDR3; |
5c7707554 drivers/edac: pro... |
112 113 114 115 116 |
break; default: return -1; } |
a895bf8b1 edac: move nr_pag... |
117 |
dimm->nr_pages = mem_info.mem_size >> PAGE_SHIFT; |
084a4fcce edac: move dimm p... |
118 119 |
dimm->grain = TILE_EDAC_ERROR_GRAIN; dimm->dtype = DEV_UNKNOWN; |
5c7707554 drivers/edac: pro... |
120 121 122 |
return 0; } |
9b3c6e85c Drivers: edac: re... |
123 |
static int tile_edac_mc_probe(struct platform_device *pdev) |
5c7707554 drivers/edac: pro... |
124 125 126 127 |
{ char hv_file[32]; int hv_devhdl; struct mem_ctl_info *mci; |
40467db77 tile_edac: conver... |
128 |
struct edac_mc_layer layers[2]; |
5c7707554 drivers/edac: pro... |
129 130 131 132 133 134 135 136 137 |
struct tile_edac_priv *priv; int rc; sprintf(hv_file, "mshim/%d", pdev->id); hv_devhdl = hv_dev_open((HV_VirtAddr)hv_file, 0); if (hv_devhdl < 0) return -EINVAL; /* A TILE MC has a single channel and one chip-select row. */ |
40467db77 tile_edac: conver... |
138 139 140 141 142 143 |
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; layers[0].size = TILE_EDAC_NR_CSROWS; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = TILE_EDAC_NR_CHANS; layers[1].is_virt_csrow = false; |
ca0907b9e edac: Remove the ... |
144 |
mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers, |
40467db77 tile_edac: conver... |
145 |
sizeof(struct tile_edac_priv)); |
5c7707554 drivers/edac: pro... |
146 147 148 149 150 |
if (mci == NULL) return -ENOMEM; priv = mci->pvt_info; priv->node = pdev->id; priv->hv_devhdl = hv_devhdl; |
fd687502d edac: Rename the ... |
151 |
mci->pdev = &pdev->dev; |
5c7707554 drivers/edac: pro... |
152 153 154 155 |
mci->mtype_cap = MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_SECDED; mci->mod_name = DRV_NAME; |
e2e110d75 edac: say "TILEGx... |
156 157 158 |
#ifdef __tilegx__ mci->ctl_name = "TILEGx_Memory_Controller"; #else |
5c7707554 drivers/edac: pro... |
159 |
mci->ctl_name = "TILEPro_Memory_Controller"; |
e2e110d75 edac: say "TILEGx... |
160 |
#endif |
5c7707554 drivers/edac: pro... |
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 |
mci->dev_name = dev_name(&pdev->dev); mci->edac_check = tile_edac_check; /* * Initialize the MC control structure 'csrows' table * with the mapping and control information. */ if (tile_edac_init_csrows(mci)) { /* No csrows found. */ mci->edac_cap = EDAC_FLAG_NONE; } else { mci->edac_cap = EDAC_FLAG_SECDED; } platform_set_drvdata(pdev, mci); /* Register with EDAC core */ rc = edac_mc_add_mc(mci); if (rc) { dev_err(&pdev->dev, "failed to register with EDAC core "); edac_mc_free(mci); return rc; } return 0; } |
9b3c6e85c Drivers: edac: re... |
188 |
static int tile_edac_mc_remove(struct platform_device *pdev) |
5c7707554 drivers/edac: pro... |
189 190 191 192 193 194 195 196 197 198 199 200 |
{ struct mem_ctl_info *mci = platform_get_drvdata(pdev); edac_mc_del_mc(&pdev->dev); if (mci) edac_mc_free(mci); return 0; } static struct platform_driver tile_edac_mc_driver = { .driver = { .name = DRV_NAME, |
5c7707554 drivers/edac: pro... |
201 202 |
}, .probe = tile_edac_mc_probe, |
9b3c6e85c Drivers: edac: re... |
203 |
.remove = tile_edac_mc_remove, |
5c7707554 drivers/edac: pro... |
204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 |
}; /* * Driver init routine. */ static int __init tile_edac_init(void) { char hv_file[32]; struct platform_device *pdev; int i, err, num = 0; /* Only support POLL mode. */ edac_op_state = EDAC_OPSTATE_POLL; err = platform_driver_register(&tile_edac_mc_driver); if (err) return err; for (i = 0; i < TILE_MAX_MSHIMS; i++) { /* * Not all memory controllers are configured such as in the * case of a simulator. So we register only those mshims * that are configured by the hypervisor. */ sprintf(hv_file, "mshim/%d", i); if (hv_dev_open((HV_VirtAddr)hv_file, 0) < 0) continue; pdev = platform_device_register_simple(DRV_NAME, i, NULL, 0); if (IS_ERR(pdev)) continue; mshim_pdev[i] = pdev; num++; } if (num == 0) { platform_driver_unregister(&tile_edac_mc_driver); return -ENODEV; } return 0; } /* * Driver cleanup routine. */ static void __exit tile_edac_exit(void) { int i; for (i = 0; i < TILE_MAX_MSHIMS; i++) { struct platform_device *pdev = mshim_pdev[i]; if (!pdev) continue; |
5c7707554 drivers/edac: pro... |
257 258 259 260 261 262 263 |
platform_device_unregister(pdev); } platform_driver_unregister(&tile_edac_mc_driver); } module_init(tile_edac_init); module_exit(tile_edac_exit); |