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drivers/video/cirrusfb.c
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/* * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets * * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com> * * Contributors (thanks, all!) * * David Eger: * Overhaul for Linux 2.6 * * Jeff Rugen: * Major contributions; Motorola PowerStack (PPC and PCI) support, * GD54xx, 1280x1024 mode support, change MCLK based on VCLK. * * Geert Uytterhoeven: * Excellent code review. * * Lars Hecking: * Amiga updates and testing. * * Original cirrusfb author: Frank Neumann * * Based on retz3fb.c and cirrusfb.c: * Copyright (C) 1997 Jes Sorensen * Copyright (C) 1996 Frank Neumann * *************************************************************** * * Format this code with GNU indent '-kr -i8 -pcs' options. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file COPYING in the main directory of this archive * for more details. * */ |
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#include <linux/module.h> #include <linux/kernel.h> #include <linux/errno.h> #include <linux/string.h> #include <linux/mm.h> |
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#include <linux/slab.h> #include <linux/delay.h> #include <linux/fb.h> #include <linux/init.h> |
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#include <asm/pgtable.h> #ifdef CONFIG_ZORRO #include <linux/zorro.h> #endif #ifdef CONFIG_PCI #include <linux/pci.h> #endif #ifdef CONFIG_AMIGA #include <asm/amigahw.h> #endif #ifdef CONFIG_PPC_PREP |
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#include <asm/machdep.h> |
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#define isPReP machine_is(prep) |
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#else #define isPReP 0 #endif |
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#include <video/vga.h> #include <video/cirrus.h> |
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/***************************************************************** * * debugging and utility macros * */ |
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/* disable runtime assertions? */ /* #define CIRRUSFB_NDEBUG */ |
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/* debugging assertions */ #ifndef CIRRUSFB_NDEBUG #define assert(expr) \ |
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if (!(expr)) { \ printk("Assertion failed! %s,%s,%s,line=%d ", \ |
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#expr, __FILE__, __func__, __LINE__); \ |
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} |
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#else #define assert(expr) #endif |
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#define MB_ (1024 * 1024) |
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/***************************************************************** * * chipset information * */ /* board types */ |
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enum cirrus_board { |
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BT_NONE = 0, |
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BT_SD64, /* GD5434 */ BT_PICCOLO, /* GD5426 */ BT_PICASSO, /* GD5426 or GD5428 */ BT_SPECTRUM, /* GD5426 or GD5428 */ |
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BT_PICASSO4, /* GD5446 */ BT_ALPINE, /* GD543x/4x */ BT_GD5480, |
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BT_LAGUNA, /* GD5462/64 */ BT_LAGUNAB, /* GD5465 */ |
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}; |
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/* * per-board-type information, used for enumerating and abstracting * chip-specific information |
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* NOTE: MUST be in the same order as enum cirrus_board in order to |
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* use direct indexing on this array * NOTE: '__initdata' cannot be used as some of this info * is required at runtime. Maybe separate into an init-only and * a run-time table? */ static const struct cirrusfb_board_info_rec { char *name; /* ASCII name of chipset */ long maxclock[5]; /* maximum video clock */ /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */ |
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bool init_sr07 : 1; /* init SR07 during init_vgachip() */ bool init_sr1f : 1; /* write SR1F during init_vgachip() */ |
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/* construct bit 19 of screen start address */ bool scrn_start_bit19 : 1; |
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/* initial SR07 value, then for each mode */ unsigned char sr07; unsigned char sr07_1bpp; unsigned char sr07_1bpp_mux; unsigned char sr07_8bpp; unsigned char sr07_8bpp_mux; unsigned char sr1f; /* SR1F VGA initial register value */ } cirrusfb_board_info[] = { [BT_SD64] = { .name = "CL SD64", .maxclock = { /* guess */ /* the SD64/P4 have a higher max. videoclock */ |
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135100, 135100, 85500, 85500, 0 |
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}, |
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.init_sr07 = true, .init_sr1f = true, .scrn_start_bit19 = true, |
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.sr07 = 0xF0, .sr07_1bpp = 0xF0, |
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.sr07_1bpp_mux = 0xF6, |
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.sr07_8bpp = 0xF1, |
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.sr07_8bpp_mux = 0xF7, |
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.sr1f = 0x1E |
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}, [BT_PICCOLO] = { .name = "CL Piccolo", .maxclock = { /* guess */ 90000, 90000, 90000, 90000, 90000 }, |
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.init_sr07 = true, .init_sr1f = true, .scrn_start_bit19 = false, |
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.sr07 = 0x80, .sr07_1bpp = 0x80, .sr07_8bpp = 0x81, .sr1f = 0x22 }, [BT_PICASSO] = { .name = "CL Picasso", .maxclock = { /* guess */ 90000, 90000, 90000, 90000, 90000 }, |
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.init_sr07 = true, .init_sr1f = true, .scrn_start_bit19 = false, |
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.sr07 = 0x20, .sr07_1bpp = 0x20, .sr07_8bpp = 0x21, .sr1f = 0x22 }, [BT_SPECTRUM] = { .name = "CL Spectrum", .maxclock = { /* guess */ 90000, 90000, 90000, 90000, 90000 }, |
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.init_sr07 = true, .init_sr1f = true, .scrn_start_bit19 = false, |
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.sr07 = 0x80, .sr07_1bpp = 0x80, .sr07_8bpp = 0x81, .sr1f = 0x22 }, [BT_PICASSO4] = { .name = "CL Picasso4", .maxclock = { 135100, 135100, 85500, 85500, 0 }, |
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.init_sr07 = true, .init_sr1f = false, .scrn_start_bit19 = true, |
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.sr07 = 0xA0, .sr07_1bpp = 0xA0, .sr07_1bpp_mux = 0xA6, .sr07_8bpp = 0xA1, .sr07_8bpp_mux = 0xA7, |
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.sr1f = 0 }, [BT_ALPINE] = { .name = "CL Alpine", .maxclock = { /* for the GD5430. GD5446 can do more... */ 85500, 85500, 50000, 28500, 0 }, |
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.init_sr07 = true, .init_sr1f = true, .scrn_start_bit19 = true, |
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.sr07 = 0xA0, |
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.sr07_1bpp = 0xA0, .sr07_1bpp_mux = 0xA6, |
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.sr07_8bpp = 0xA1, .sr07_8bpp_mux = 0xA7, .sr1f = 0x1C }, [BT_GD5480] = { .name = "CL GD5480", .maxclock = { 135100, 200000, 200000, 135100, 135100 }, |
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.init_sr07 = true, .init_sr1f = true, .scrn_start_bit19 = true, |
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.sr07 = 0x10, .sr07_1bpp = 0x11, .sr07_8bpp = 0x11, .sr1f = 0x1C }, [BT_LAGUNA] = { .name = "CL Laguna", .maxclock = { |
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/* taken from X11 code */ 170000, 170000, 170000, 170000, 135100, }, .init_sr07 = false, .init_sr1f = false, .scrn_start_bit19 = true, }, [BT_LAGUNAB] = { .name = "CL Laguna AGP", .maxclock = { /* taken from X11 code */ 170000, 250000, 170000, 170000, 135100, |
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}, |
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.init_sr07 = false, .init_sr1f = false, .scrn_start_bit19 = true, |
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} }; |
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#ifdef CONFIG_PCI #define CHIP(id, btype) \ |
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{ PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) } |
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static struct pci_device_id cirrusfb_pci_table[] = { |
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CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE), |
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CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64), CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64), |
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CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */ CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE), CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE), CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */ CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */ CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */ CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */ |
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CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/ |
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{ 0, } }; MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table); #undef CHIP #endif /* CONFIG_PCI */ |
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#ifdef CONFIG_ZORRO static const struct zorro_device_id cirrusfb_zorro_table[] = { { .id = ZORRO_PROD_HELFRICH_SD64_RAM, .driver_data = BT_SD64, }, { .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM, .driver_data = BT_PICCOLO, }, { |
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.id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM, |
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.driver_data = BT_PICASSO, }, { .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM, .driver_data = BT_SPECTRUM, }, { .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3, .driver_data = BT_PICASSO4, }, { 0 } }; static const struct { zorro_id id2; unsigned long size; } cirrusfb_zorro_table2[] = { [BT_SD64] = { .id2 = ZORRO_PROD_HELFRICH_SD64_REG, .size = 0x400000 }, [BT_PICCOLO] = { .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG, .size = 0x200000 }, [BT_PICASSO] = { .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG, .size = 0x200000 }, [BT_SPECTRUM] = { .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG, .size = 0x200000 }, [BT_PICASSO4] = { .id2 = 0, .size = 0x400000 } }; #endif /* CONFIG_ZORRO */ |
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#ifdef CIRRUSFB_DEBUG |
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enum cirrusfb_dbg_reg_class { |
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CRT, SEQ |
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}; |
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#endif /* CIRRUSFB_DEBUG */ |
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/* info about board */ struct cirrusfb_info { |
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u8 __iomem *regbase; |
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u8 __iomem *laguna_mmio; |
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enum cirrus_board btype; |
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unsigned char SFR; /* Shadow of special function register */ |
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int multiplexing; |
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int doubleVCLK; |
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int blank_mode; |
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u32 pseudo_palette[16]; |
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void (*unmap)(struct fb_info *info); |
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}; |
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static int noaccel __devinitdata; |
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static char *mode_option __devinitdata = "640x480@60"; |
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/****************************************************************************/ /**** BEGIN PROTOTYPES ******************************************************/ |
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/*--- Interface used by the world ------------------------------------------*/ |
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static int cirrusfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); |
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/*--- Internal routines ----------------------------------------------------*/ |
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static void init_vgachip(struct fb_info *info); |
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static void switch_monitor(struct cirrusfb_info *cinfo, int on); static void WGen(const struct cirrusfb_info *cinfo, int regnum, unsigned char val); static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum); static void AttrOn(const struct cirrusfb_info *cinfo); static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val); static void WSFR(struct cirrusfb_info *cinfo, unsigned char val); static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val); static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red, unsigned char green, unsigned char blue); |
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#if 0 |
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static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red, unsigned char *green, unsigned char *blue); |
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#endif |
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static void cirrusfb_WaitBLT(u8 __iomem *regbase); static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel, u_short curx, u_short cury, u_short destx, u_short desty, u_short width, u_short height, u_short line_length); static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel, u_short x, u_short y, u_short width, u_short height, |
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u32 fg_color, u32 bg_color, u_short line_length, u_char blitmode); |
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static void bestclock(long freq, int *nom, int *den, int *div); |
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#ifdef CIRRUSFB_DEBUG |
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static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase); static void cirrusfb_dbg_print_regs(struct fb_info *info, caddr_t regbase, |
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enum cirrusfb_dbg_reg_class reg_class, ...); |
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#endif /* CIRRUSFB_DEBUG */ /*** END PROTOTYPES ********************************************************/ /*****************************************************************************/ /*** BEGIN Interface Used by the World ***************************************/ |
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static inline int is_laguna(const struct cirrusfb_info *cinfo) { return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB; } |
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static int opencount; |
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/*--- Open /dev/fbx ---------------------------------------------------------*/ |
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static int cirrusfb_open(struct fb_info *info, int user) |
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{ if (opencount++ == 0) |
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switch_monitor(info->par, 1); |
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return 0; } /*--- Close /dev/fbx --------------------------------------------------------*/ |
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static int cirrusfb_release(struct fb_info *info, int user) |
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{ if (--opencount == 0) |
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switch_monitor(info->par, 0); |
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return 0; } /**** END Interface used by the World *************************************/ /****************************************************************************/ /**** BEGIN Hardware specific Routines **************************************/ |
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/* Check if the MCLK is not a better clock source */ |
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static int cirrusfb_check_mclk(struct fb_info *info, long freq) |
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{ |
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struct cirrusfb_info *cinfo = info->par; |
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long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; |
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/* Read MCLK value */ mclk = (14318 * mclk) >> 3; |
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dev_dbg(info->device, "Read MCLK of %ld kHz ", mclk); |
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/* Determine if we should use MCLK instead of VCLK, and if so, what we |
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* should divide it by to get VCLK */ if (abs(freq - mclk) < 250) { |
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dev_dbg(info->device, "Using VCLK = MCLK "); |
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return 1; } else if (abs(freq - (mclk / 2)) < 250) { |
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dev_dbg(info->device, "Using VCLK = MCLK/2 "); |
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return 2; |
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} |
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return 0; |
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} |
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static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var, struct fb_info *info) { long freq; long maxclock; struct cirrusfb_info *cinfo = info->par; unsigned maxclockidx = var->bits_per_pixel >> 3; /* convert from ps to kHz */ freq = PICOS2KHZ(var->pixclock); dev_dbg(info->device, "desired pixclock: %ld kHz ", freq); maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx]; cinfo->multiplexing = 0; /* If the frequency is greater than we can support, we might be able * to use multiplexing for the video mode */ if (freq > maxclock) { |
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dev_err(info->device, "Frequency greater than maxclock (%ld kHz) ", maxclock); return -EINVAL; } /* * Additional constraint: 8bpp uses DAC clock doubling to allow maximum * pixel clock */ if (var->bits_per_pixel == 8) { |
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switch (cinfo->btype) { case BT_ALPINE: |
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case BT_SD64: |
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case BT_PICASSO4: if (freq > 85500) cinfo->multiplexing = 1; break; |
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case BT_GD5480: |
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if (freq > 135100) cinfo->multiplexing = 1; |
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break; default: |
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break; |
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} } |
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/* If we have a 1MB 5434, we need to put ourselves in a mode where |
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* the VCLK is double the pixel clock. */ |
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cinfo->doubleVCLK = 0; if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ && var->bits_per_pixel == 16) { cinfo->doubleVCLK = 1; |
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} |
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return 0; } |
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static int cirrusfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { |
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int yres; /* memory size in pixels */ unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; |
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struct cirrusfb_info *cinfo = info->par; |
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switch (var->bits_per_pixel) { |
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case 1: |
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var->red.offset = 0; var->red.length = 1; |
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var->green = var->red; var->blue = var->red; |
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break; case 8: var->red.offset = 0; |
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var->red.length = 8; |
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var->green = var->red; var->blue = var->red; |
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break; case 16: |
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if (isPReP) { |
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var->red.offset = 2; var->green.offset = -3; var->blue.offset = 8; } else { |
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var->red.offset = 11; |
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var->green.offset = 5; var->blue.offset = 0; } var->red.length = 5; |
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var->green.length = 6; |
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var->blue.length = 5; break; |
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case 24: |
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if (isPReP) { |
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var->red.offset = 0; var->green.offset = 8; var->blue.offset = 16; |
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|
545 546 547 548 549 550 551 552 553 554 555 |
} else { var->red.offset = 16; var->green.offset = 8; var->blue.offset = 0; } var->red.length = 8; var->green.length = 8; var->blue.length = 8; break; default: |
75ed3a17a
|
556 557 558 |
dev_dbg(info->device, "Unsupported bpp size: %d ", var->bits_per_pixel); |
0efb2a03a
|
559 |
return -EINVAL; |
1da177e4c
|
560 |
} |
75ed3a17a
|
561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 |
if (var->xres_virtual < var->xres) var->xres_virtual = var->xres; /* use highest possible virtual resolution */ if (var->yres_virtual == -1) { var->yres_virtual = pixels / var->xres_virtual; dev_info(info->device, "virtual resolution set to maximum of %dx%d ", var->xres_virtual, var->yres_virtual); } if (var->yres_virtual < var->yres) var->yres_virtual = var->yres; if (var->xres_virtual * var->yres_virtual > pixels) { dev_err(info->device, "mode %dx%dx%d rejected... " "virtual resolution too high to fit into video memory! ", var->xres_virtual, var->yres_virtual, var->bits_per_pixel); return -EINVAL; } |
75ed3a17a
|
583 584 585 586 587 588 589 590 591 592 |
if (var->xoffset < 0) var->xoffset = 0; if (var->yoffset < 0) var->yoffset = 0; /* truncate xoffset and yoffset to maximum if too high */ if (var->xoffset > var->xres_virtual - var->xres) var->xoffset = var->xres_virtual - var->xres - 1; if (var->yoffset > var->yres_virtual - var->yres) var->yoffset = var->yres_virtual - var->yres - 1; |
1da177e4c
|
593 594 595 596 597 598 599 600 601 602 603 604 605 606 |
var->red.msb_right = var->green.msb_right = var->blue.msb_right = var->transp.offset = var->transp.length = var->transp.msb_right = 0; yres = var->yres; if (var->vmode & FB_VMODE_DOUBLE) yres *= 2; else if (var->vmode & FB_VMODE_INTERLACED) yres = (yres + 1) / 2; if (yres >= 1280) { |
75ed3a17a
|
607 |
dev_err(info->device, "ERROR: VerticalTotal >= 1280; " |
8503df659
|
608 609 |
"special treatment required! (TODO) "); |
1da177e4c
|
610 611 |
return -EINVAL; } |
99a458475
|
612 613 |
if (cirrusfb_check_pixclock(var, info)) return -EINVAL; |
1da177e4c
|
614 |
|
614c0dc93
|
615 616 |
if (!is_laguna(cinfo)) var->accel_flags = FB_ACCELF_TEXT; |
1da177e4c
|
617 618 |
return 0; } |
75ed3a17a
|
619 |
static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div) |
1da177e4c
|
620 |
{ |
75ed3a17a
|
621 |
struct cirrusfb_info *cinfo = info->par; |
486ff387c
|
622 |
unsigned char old1f, old1e; |
75ed3a17a
|
623 |
|
8503df659
|
624 |
assert(cinfo != NULL); |
486ff387c
|
625 626 627 |
old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; if (div) { |
75ed3a17a
|
628 629 630 |
dev_dbg(info->device, "Set %s as pixclock source. ", (div == 2) ? "MCLK/2" : "MCLK"); |
486ff387c
|
631 632 633 634 |
old1f |= 0x40; old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; if (div == 2) old1e |= 1; |
1da177e4c
|
635 |
|
486ff387c
|
636 |
vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); |
1da177e4c
|
637 |
} |
486ff387c
|
638 |
vga_wseq(cinfo->regbase, CL_SEQR1F, old1f); |
1da177e4c
|
639 640 641 642 643 644 645 |
} /************************************************************************* cirrusfb_set_par_foo() actually writes the values for a new video mode into the hardware, **************************************************************************/ |
8503df659
|
646 |
static int cirrusfb_set_par_foo(struct fb_info *info) |
1da177e4c
|
647 648 649 |
{ struct cirrusfb_info *cinfo = info->par; struct fb_var_screeninfo *var = &info->var; |
1da177e4c
|
650 651 |
u8 __iomem *regbase = cinfo->regbase; unsigned char tmp; |
6683e01e2
|
652 |
int pitch; |
1da177e4c
|
653 |
const struct cirrusfb_board_info_rec *bi; |
9a85cf51f
|
654 655 |
int hdispend, hsyncstart, hsyncend, htotal; int yres, vdispend, vsyncstart, vsyncend, vtotal; |
dafa32c5a
|
656 657 |
long freq; int nom, den, div; |
1b48cb563
|
658 |
unsigned int control = 0, format = 0, threshold = 0; |
1da177e4c
|
659 |
|
75ed3a17a
|
660 661 |
dev_dbg(info->device, "Requested mode: %dx%dx%d ", |
1da177e4c
|
662 |
var->xres, var->yres, var->bits_per_pixel); |
1da177e4c
|
663 |
|
99a458475
|
664 665 666 667 668 |
switch (var->bits_per_pixel) { case 1: info->fix.line_length = var->xres_virtual / 8; info->fix.visual = FB_VISUAL_MONO10; break; |
1da177e4c
|
669 |
|
99a458475
|
670 671 672 673 674 675 |
case 8: info->fix.line_length = var->xres_virtual; info->fix.visual = FB_VISUAL_PSEUDOCOLOR; break; case 16: |
7cade31ca
|
676 |
case 24: |
99a458475
|
677 678 679 680 |
info->fix.line_length = var->xres_virtual * var->bits_per_pixel >> 3; info->fix.visual = FB_VISUAL_TRUECOLOR; break; |
1da177e4c
|
681 |
} |
99a458475
|
682 683 684 |
info->fix.type = FB_TYPE_PACKED_PIXELS; init_vgachip(info); |
1da177e4c
|
685 686 |
bi = &cirrusfb_board_info[cinfo->btype]; |
9a85cf51f
|
687 688 |
hsyncstart = var->xres + var->right_margin; hsyncend = hsyncstart + var->hsync_len; |
8636a9240
|
689 690 691 692 |
htotal = (hsyncend + var->left_margin) / 8; hdispend = var->xres / 8; hsyncstart = hsyncstart / 8; hsyncend = hsyncend / 8; |
9a85cf51f
|
693 |
|
8636a9240
|
694 695 |
vdispend = var->yres; vsyncstart = vdispend + var->lower_margin; |
9a85cf51f
|
696 697 |
vsyncend = vsyncstart + var->vsync_len; vtotal = vsyncend + var->upper_margin; |
9a85cf51f
|
698 699 |
if (var->vmode & FB_VMODE_DOUBLE) { |
8636a9240
|
700 |
vdispend *= 2; |
9a85cf51f
|
701 702 703 704 |
vsyncstart *= 2; vsyncend *= 2; vtotal *= 2; } else if (var->vmode & FB_VMODE_INTERLACED) { |
8636a9240
|
705 |
vdispend = (vdispend + 1) / 2; |
9a85cf51f
|
706 707 708 709 |
vsyncstart = (vsyncstart + 1) / 2; vsyncend = (vsyncend + 1) / 2; vtotal = (vtotal + 1) / 2; } |
8636a9240
|
710 |
yres = vdispend; |
9a85cf51f
|
711 712 713 714 715 716 |
if (yres >= 1024) { vtotal /= 2; vsyncstart /= 2; vsyncend /= 2; vdispend /= 2; } |
8636a9240
|
717 718 719 720 721 |
vdispend -= 1; vsyncstart -= 1; vsyncend -= 1; vtotal -= 2; |
48c329e90
|
722 |
if (cinfo->multiplexing) { |
9a85cf51f
|
723 724 725 726 727 |
htotal /= 2; hsyncstart /= 2; hsyncend /= 2; hdispend /= 2; } |
8636a9240
|
728 729 730 731 732 |
htotal -= 5; hdispend -= 1; hsyncstart += 1; hsyncend += 1; |
1da177e4c
|
733 |
/* unlock register VGA_CRTC_H_TOTAL..CRT7 */ |
8503df659
|
734 |
vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */ |
1da177e4c
|
735 736 |
/* if debugging is enabled, all parameters get output before writing */ |
75ed3a17a
|
737 738 |
dev_dbg(info->device, "CRT0: %d ", htotal); |
9a85cf51f
|
739 |
vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal); |
1da177e4c
|
740 |
|
75ed3a17a
|
741 742 |
dev_dbg(info->device, "CRT1: %d ", hdispend); |
9a85cf51f
|
743 |
vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend); |
1da177e4c
|
744 |
|
75ed3a17a
|
745 746 |
dev_dbg(info->device, "CRT2: %d ", var->xres / 8); |
9a85cf51f
|
747 |
vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8); |
1da177e4c
|
748 |
|
8503df659
|
749 |
/* + 128: Compatible read */ |
75ed3a17a
|
750 751 |
dev_dbg(info->device, "CRT3: 128+%d ", (htotal + 5) % 32); |
8503df659
|
752 |
vga_wcrt(regbase, VGA_CRTC_H_BLANK_END, |
9a85cf51f
|
753 |
128 + ((htotal + 5) % 32)); |
1da177e4c
|
754 |
|
75ed3a17a
|
755 756 |
dev_dbg(info->device, "CRT4: %d ", hsyncstart); |
9a85cf51f
|
757 |
vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart); |
1da177e4c
|
758 |
|
9a85cf51f
|
759 760 |
tmp = hsyncend % 32; if ((htotal + 5) & 32) |
1da177e4c
|
761 |
tmp += 128; |
75ed3a17a
|
762 763 |
dev_dbg(info->device, "CRT5: %d ", tmp); |
8503df659
|
764 |
vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp); |
1da177e4c
|
765 |
|
75ed3a17a
|
766 767 |
dev_dbg(info->device, "CRT6: %d ", vtotal & 0xff); |
9a85cf51f
|
768 |
vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff); |
1da177e4c
|
769 770 |
tmp = 16; /* LineCompare bit #9 */ |
9a85cf51f
|
771 |
if (vtotal & 256) |
1da177e4c
|
772 |
tmp |= 1; |
9a85cf51f
|
773 |
if (vdispend & 256) |
1da177e4c
|
774 |
tmp |= 2; |
9a85cf51f
|
775 |
if (vsyncstart & 256) |
1da177e4c
|
776 |
tmp |= 4; |
9a85cf51f
|
777 |
if ((vdispend + 1) & 256) |
1da177e4c
|
778 |
tmp |= 8; |
9a85cf51f
|
779 |
if (vtotal & 512) |
1da177e4c
|
780 |
tmp |= 32; |
9a85cf51f
|
781 |
if (vdispend & 512) |
1da177e4c
|
782 |
tmp |= 64; |
9a85cf51f
|
783 |
if (vsyncstart & 512) |
1da177e4c
|
784 |
tmp |= 128; |
75ed3a17a
|
785 786 |
dev_dbg(info->device, "CRT7: %d ", tmp); |
8503df659
|
787 |
vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp); |
1da177e4c
|
788 789 |
tmp = 0x40; /* LineCompare bit #8 */ |
9a85cf51f
|
790 |
if ((vdispend + 1) & 512) |
1da177e4c
|
791 792 793 |
tmp |= 0x20; if (var->vmode & FB_VMODE_DOUBLE) tmp |= 0x80; |
75ed3a17a
|
794 795 |
dev_dbg(info->device, "CRT9: %d ", tmp); |
8503df659
|
796 |
vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp); |
1da177e4c
|
797 |
|
75ed3a17a
|
798 799 |
dev_dbg(info->device, "CRT10: %d ", vsyncstart & 0xff); |
9a85cf51f
|
800 |
vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff); |
1da177e4c
|
801 |
|
75ed3a17a
|
802 803 |
dev_dbg(info->device, "CRT11: 64+32+%d ", vsyncend % 16); |
9a85cf51f
|
804 |
vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32); |
1da177e4c
|
805 |
|
75ed3a17a
|
806 807 |
dev_dbg(info->device, "CRT12: %d ", vdispend & 0xff); |
9a85cf51f
|
808 |
vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff); |
1da177e4c
|
809 |
|
75ed3a17a
|
810 811 |
dev_dbg(info->device, "CRT15: %d ", (vdispend + 1) & 0xff); |
9a85cf51f
|
812 |
vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff); |
1da177e4c
|
813 |
|
75ed3a17a
|
814 815 |
dev_dbg(info->device, "CRT16: %d ", vtotal & 0xff); |
9a85cf51f
|
816 |
vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff); |
1da177e4c
|
817 |
|
75ed3a17a
|
818 819 |
dev_dbg(info->device, "CRT18: 0xff "); |
8503df659
|
820 |
vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff); |
1da177e4c
|
821 822 823 824 |
tmp = 0; if (var->vmode & FB_VMODE_INTERLACED) tmp |= 1; |
9a85cf51f
|
825 |
if ((htotal + 5) & 64) |
1da177e4c
|
826 |
tmp |= 16; |
9a85cf51f
|
827 |
if ((htotal + 5) & 128) |
1da177e4c
|
828 |
tmp |= 32; |
9a85cf51f
|
829 |
if (vtotal & 256) |
1da177e4c
|
830 |
tmp |= 64; |
9a85cf51f
|
831 |
if (vtotal & 512) |
1da177e4c
|
832 |
tmp |= 128; |
75ed3a17a
|
833 834 |
dev_dbg(info->device, "CRT1a: %d ", tmp); |
8503df659
|
835 |
vga_wcrt(regbase, CL_CRT1A, tmp); |
1da177e4c
|
836 |
|
dafa32c5a
|
837 |
freq = PICOS2KHZ(var->pixclock); |
df3aafd57
|
838 839 840 |
if (var->bits_per_pixel == 24) if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) freq *= 3; |
dd14f71cc
|
841 842 |
if (cinfo->multiplexing) freq /= 2; |
df3aafd57
|
843 844 |
if (cinfo->doubleVCLK) freq *= 2; |
7cade31ca
|
845 |
|
dafa32c5a
|
846 |
bestclock(freq, &nom, &den, &div); |
75ed3a17a
|
847 848 849 |
dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d ", freq, nom, den, div); |
1da177e4c
|
850 851 852 853 |
/* set VCLK0 */ /* hardware RefClock: 14.31818 MHz */ /* formula: VClk = (OSC * N) / (D * (1+P)) */ /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */ |
8f19e15b8
|
854 855 |
if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 || cinfo->btype == BT_SD64) { |
486ff387c
|
856 857 858 |
/* if freq is close to mclk or mclk/2 select mclk * as clock source */ |
75ed3a17a
|
859 |
int divMCLK = cirrusfb_check_mclk(info, freq); |
df3aafd57
|
860 |
if (divMCLK) |
486ff387c
|
861 |
nom = 0; |
df3aafd57
|
862 |
cirrusfb_set_mclk_as_source(info, divMCLK); |
486ff387c
|
863 |
} |
78d780e07
|
864 |
if (is_laguna(cinfo)) { |
6e30fc086
|
865 866 867 |
long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc); unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); unsigned short tile_control; |
78d780e07
|
868 869 870 871 872 |
if (cinfo->btype == BT_LAGUNAB) { tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4); tile_control &= ~0x80; fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4); } |
6e30fc086
|
873 874 875 876 877 878 879 |
fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc); fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); control = fb_readw(cinfo->laguna_mmio + 0x402); threshold = fb_readw(cinfo->laguna_mmio + 0xea); control &= ~0x6800; format = 0; |
4242a23c9
|
880 |
threshold &= 0xffc0 & 0x3fbf; |
6e30fc086
|
881 |
} |
486ff387c
|
882 |
if (nom) { |
486ff387c
|
883 884 885 |
tmp = den << 1; if (div != 0) tmp |= 1; |
486ff387c
|
886 887 888 889 890 |
/* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */ if ((cinfo->btype == BT_SD64) || (cinfo->btype == BT_ALPINE) || (cinfo->btype == BT_GD5480)) tmp |= 0x80; |
55a4ea6ab
|
891 |
/* Laguna chipset has reversed clock registers */ |
78d780e07
|
892 |
if (is_laguna(cinfo)) { |
55a4ea6ab
|
893 894 895 |
vga_wseq(regbase, CL_SEQRE, tmp); vga_wseq(regbase, CL_SEQR1E, nom); } else { |
df3aafd57
|
896 897 |
vga_wseq(regbase, CL_SEQRE, nom); vga_wseq(regbase, CL_SEQR1E, tmp); |
55a4ea6ab
|
898 |
} |
486ff387c
|
899 |
} |
1da177e4c
|
900 |
|
9a85cf51f
|
901 |
if (yres >= 1024) |
1da177e4c
|
902 |
/* 1280x1024 */ |
8503df659
|
903 |
vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7); |
1da177e4c
|
904 905 906 |
else /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit * address wrap, no compat. */ |
8503df659
|
907 |
vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3); |
1da177e4c
|
908 |
|
1da177e4c
|
909 910 911 |
/* don't know if it would hurt to also program this if no interlaced */ /* mode is used, but I feel better this way.. :-) */ if (var->vmode & FB_VMODE_INTERLACED) |
9a85cf51f
|
912 |
vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2); |
1da177e4c
|
913 |
else |
8503df659
|
914 |
vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */ |
1da177e4c
|
915 |
|
df3aafd57
|
916 |
/* adjust horizontal/vertical sync type (low/high), use VCLK3 */ |
8503df659
|
917 |
/* enable display memory & CRTC I/O address for color mode */ |
df3aafd57
|
918 |
tmp = 0x03 | 0xc; |
1da177e4c
|
919 920 921 922 |
if (var->sync & FB_SYNC_HOR_HIGH_ACT) tmp |= 0x40; if (var->sync & FB_SYNC_VERT_HIGH_ACT) tmp |= 0x80; |
8503df659
|
923 |
WGen(cinfo, VGA_MIS_W, tmp); |
1da177e4c
|
924 |
|
8503df659
|
925 926 927 928 |
/* text cursor on and start line */ vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0); /* text cursor end line */ vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31); |
1da177e4c
|
929 930 931 932 933 934 935 936 937 |
/****************************************************** * * 1 bpp * */ /* programming for different color depths */ if (var->bits_per_pixel == 1) { |
75ed3a17a
|
938 939 |
dev_dbg(info->device, "preparing for 1 bit deep display "); |
8503df659
|
940 |
vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */ |
1da177e4c
|
941 942 943 944 945 946 947 948 949 950 |
/* SR07 */ switch (cinfo->btype) { case BT_SD64: case BT_PICCOLO: case BT_PICASSO: case BT_SPECTRUM: case BT_PICASSO4: case BT_ALPINE: case BT_GD5480: |
8503df659
|
951 |
vga_wseq(regbase, CL_SEQR7, |
48c329e90
|
952 |
cinfo->multiplexing ? |
1da177e4c
|
953 954 955 956 |
bi->sr07_1bpp_mux : bi->sr07_1bpp); break; case BT_LAGUNA: |
78d780e07
|
957 |
case BT_LAGUNAB: |
8503df659
|
958 959 |
vga_wseq(regbase, CL_SEQR7, vga_rseq(regbase, CL_SEQR7) & ~0x01); |
1da177e4c
|
960 961 962 |
break; default: |
75ed3a17a
|
963 964 |
dev_warn(info->device, "unknown Board "); |
1da177e4c
|
965 966 967 968 969 |
break; } /* Extended Sequencer Mode */ switch (cinfo->btype) { |
1da177e4c
|
970 971 |
case BT_PICCOLO: |
060b6002b
|
972 |
case BT_SPECTRUM: |
8503df659
|
973 974 |
/* evtl d0 bei 1 bit? avoid FIFO underruns..? */ vga_wseq(regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
975 976 977 |
break; case BT_PICASSO: |
8503df659
|
978 979 |
/* ## vorher d0 avoid FIFO underruns..? */ vga_wseq(regbase, CL_SEQRF, 0xd0); |
1da177e4c
|
980 |
break; |
8f19e15b8
|
981 |
case BT_SD64: |
1da177e4c
|
982 983 984 985 |
case BT_PICASSO4: case BT_ALPINE: case BT_GD5480: case BT_LAGUNA: |
78d780e07
|
986 |
case BT_LAGUNAB: |
1da177e4c
|
987 988 989 990 |
/* do nothing */ break; default: |
75ed3a17a
|
991 992 |
dev_warn(info->device, "unknown Board "); |
1da177e4c
|
993 994 |
break; } |
8503df659
|
995 996 |
/* pixel mask: pass-through for first plane */ WGen(cinfo, VGA_PEL_MSK, 0x01); |
48c329e90
|
997 |
if (cinfo->multiplexing) |
8503df659
|
998 999 |
/* hidden dac reg: 1280x1024 */ WHDR(cinfo, 0x4a); |
1da177e4c
|
1000 |
else |
8503df659
|
1001 1002 1003 1004 1005 1006 |
/* hidden dac: nothing */ WHDR(cinfo, 0); /* memory mode: odd/even, ext. memory */ vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06); /* plane mask: only write to first plane */ vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01); |
1da177e4c
|
1007 1008 1009 1010 1011 1012 1013 1014 1015 |
} /****************************************************** * * 8 bpp * */ else if (var->bits_per_pixel == 8) { |
75ed3a17a
|
1016 1017 |
dev_dbg(info->device, "preparing for 8 bit deep display "); |
1da177e4c
|
1018 1019 1020 1021 1022 1023 1024 1025 |
switch (cinfo->btype) { case BT_SD64: case BT_PICCOLO: case BT_PICASSO: case BT_SPECTRUM: case BT_PICASSO4: case BT_ALPINE: case BT_GD5480: |
8503df659
|
1026 |
vga_wseq(regbase, CL_SEQR7, |
48c329e90
|
1027 |
cinfo->multiplexing ? |
1da177e4c
|
1028 1029 1030 1031 |
bi->sr07_8bpp_mux : bi->sr07_8bpp); break; case BT_LAGUNA: |
78d780e07
|
1032 |
case BT_LAGUNAB: |
8503df659
|
1033 1034 |
vga_wseq(regbase, CL_SEQR7, vga_rseq(regbase, CL_SEQR7) | 0x01); |
6e30fc086
|
1035 |
threshold |= 0x10; |
1da177e4c
|
1036 1037 1038 |
break; default: |
75ed3a17a
|
1039 1040 |
dev_warn(info->device, "unknown Board "); |
1da177e4c
|
1041 1042 1043 1044 |
break; } switch (cinfo->btype) { |
1da177e4c
|
1045 |
case BT_PICCOLO: |
1da177e4c
|
1046 |
case BT_PICASSO: |
1da177e4c
|
1047 |
case BT_SPECTRUM: |
8503df659
|
1048 1049 |
/* Fast Page-Mode writes */ vga_wseq(regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
1050 1051 1052 1053 |
break; case BT_PICASSO4: #ifdef CONFIG_ZORRO |
8503df659
|
1054 1055 |
/* ### INCOMPLETE!! */ vga_wseq(regbase, CL_SEQRF, 0xb8); |
1da177e4c
|
1056 |
#endif |
1da177e4c
|
1057 |
case BT_ALPINE: |
8f19e15b8
|
1058 |
case BT_SD64: |
1da177e4c
|
1059 1060 |
case BT_GD5480: case BT_LAGUNA: |
78d780e07
|
1061 |
case BT_LAGUNAB: |
1da177e4c
|
1062 1063 1064 1065 |
/* do nothing */ break; default: |
75ed3a17a
|
1066 1067 |
dev_warn(info->device, "unknown board "); |
1da177e4c
|
1068 1069 |
break; } |
8503df659
|
1070 1071 |
/* mode register: 256 color mode */ vga_wgfx(regbase, VGA_GFX_MODE, 64); |
48c329e90
|
1072 |
if (cinfo->multiplexing) |
8503df659
|
1073 1074 |
/* hidden dac reg: 1280x1024 */ WHDR(cinfo, 0x4a); |
1da177e4c
|
1075 |
else |
8503df659
|
1076 1077 |
/* hidden dac: nothing */ WHDR(cinfo, 0); |
1da177e4c
|
1078 1079 1080 1081 1082 1083 1084 1085 1086 |
} /****************************************************** * * 16 bpp * */ else if (var->bits_per_pixel == 16) { |
75ed3a17a
|
1087 1088 |
dev_dbg(info->device, "preparing for 16 bit deep display "); |
1da177e4c
|
1089 |
switch (cinfo->btype) { |
1da177e4c
|
1090 |
case BT_PICCOLO: |
060b6002b
|
1091 |
case BT_SPECTRUM: |
8503df659
|
1092 1093 1094 |
vga_wseq(regbase, CL_SEQR7, 0x87); /* Fast Page-Mode writes */ vga_wseq(regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
1095 1096 1097 |
break; case BT_PICASSO: |
8503df659
|
1098 1099 1100 |
vga_wseq(regbase, CL_SEQR7, 0x27); /* Fast Page-Mode writes */ vga_wseq(regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
1101 |
break; |
8f19e15b8
|
1102 |
case BT_SD64: |
1da177e4c
|
1103 |
case BT_PICASSO4: |
1da177e4c
|
1104 |
case BT_ALPINE: |
8f19e15b8
|
1105 |
/* Extended Sequencer Mode: 256c col. mode */ |
df3aafd57
|
1106 1107 |
vga_wseq(regbase, CL_SEQR7, cinfo->doubleVCLK ? 0xa3 : 0xa7); |
1da177e4c
|
1108 1109 1110 |
break; case BT_GD5480: |
8503df659
|
1111 |
vga_wseq(regbase, CL_SEQR7, 0x17); |
1da177e4c
|
1112 1113 1114 1115 |
/* We already set SRF and SR1F */ break; case BT_LAGUNA: |
78d780e07
|
1116 |
case BT_LAGUNAB: |
8503df659
|
1117 1118 |
vga_wseq(regbase, CL_SEQR7, vga_rseq(regbase, CL_SEQR7) & ~0x01); |
6e30fc086
|
1119 1120 1121 |
control |= 0x2000; format |= 0x1400; threshold |= 0x10; |
1da177e4c
|
1122 1123 1124 |
break; default: |
75ed3a17a
|
1125 1126 |
dev_warn(info->device, "unknown Board "); |
1da177e4c
|
1127 1128 |
break; } |
8503df659
|
1129 1130 |
/* mode register: 256 color mode */ vga_wgfx(regbase, VGA_GFX_MODE, 64); |
1da177e4c
|
1131 |
#ifdef CONFIG_PCI |
df3aafd57
|
1132 |
WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1); |
1da177e4c
|
1133 1134 |
#elif defined(CONFIG_ZORRO) /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */ |
8503df659
|
1135 |
WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */ |
1da177e4c
|
1136 |
#endif |
1da177e4c
|
1137 1138 1139 1140 |
} /****************************************************** * |
7cade31ca
|
1141 |
* 24 bpp |
1da177e4c
|
1142 1143 |
* */ |
7cade31ca
|
1144 1145 1146 |
else if (var->bits_per_pixel == 24) { dev_dbg(info->device, "preparing for 24 bit deep display "); |
1da177e4c
|
1147 |
switch (cinfo->btype) { |
1da177e4c
|
1148 |
case BT_PICCOLO: |
060b6002b
|
1149 |
case BT_SPECTRUM: |
8503df659
|
1150 1151 1152 |
vga_wseq(regbase, CL_SEQR7, 0x85); /* Fast Page-Mode writes */ vga_wseq(regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
1153 1154 1155 |
break; case BT_PICASSO: |
8503df659
|
1156 1157 1158 |
vga_wseq(regbase, CL_SEQR7, 0x25); /* Fast Page-Mode writes */ vga_wseq(regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
1159 |
break; |
8f19e15b8
|
1160 |
case BT_SD64: |
1da177e4c
|
1161 |
case BT_PICASSO4: |
1da177e4c
|
1162 |
case BT_ALPINE: |
8f19e15b8
|
1163 |
/* Extended Sequencer Mode: 256c col. mode */ |
7cade31ca
|
1164 |
vga_wseq(regbase, CL_SEQR7, 0xa5); |
1da177e4c
|
1165 1166 1167 |
break; case BT_GD5480: |
7cade31ca
|
1168 |
vga_wseq(regbase, CL_SEQR7, 0x15); |
1da177e4c
|
1169 1170 1171 1172 |
/* We already set SRF and SR1F */ break; case BT_LAGUNA: |
78d780e07
|
1173 |
case BT_LAGUNAB: |
8503df659
|
1174 1175 |
vga_wseq(regbase, CL_SEQR7, vga_rseq(regbase, CL_SEQR7) & ~0x01); |
7cade31ca
|
1176 1177 |
control |= 0x4000; format |= 0x2400; |
6e30fc086
|
1178 |
threshold |= 0x20; |
1da177e4c
|
1179 1180 1181 |
break; default: |
75ed3a17a
|
1182 1183 |
dev_warn(info->device, "unknown Board "); |
1da177e4c
|
1184 1185 |
break; } |
8503df659
|
1186 1187 |
/* mode register: 256 color mode */ vga_wgfx(regbase, VGA_GFX_MODE, 64); |
8503df659
|
1188 1189 |
/* hidden dac reg: 8-8-8 mode (24 or 32) */ WHDR(cinfo, 0xc5); |
1da177e4c
|
1190 1191 1192 1193 1194 1195 1196 |
} /****************************************************** * * unknown/unsupported bpp * */ |
8503df659
|
1197 |
else |
75ed3a17a
|
1198 1199 1200 |
dev_err(info->device, "What's this? requested color depth == %d. ", |
1da177e4c
|
1201 |
var->bits_per_pixel); |
1da177e4c
|
1202 |
|
6683e01e2
|
1203 1204 |
pitch = info->fix.line_length >> 3; vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff); |
1da177e4c
|
1205 |
tmp = 0x22; |
6683e01e2
|
1206 |
if (pitch & 0x100) |
1da177e4c
|
1207 |
tmp |= 0x10; /* offset overflow bit */ |
8503df659
|
1208 1209 |
/* screen start addr #16-18, fastpagemode cycles */ vga_wcrt(regbase, CL_CRT1B, tmp); |
1da177e4c
|
1210 |
|
213d4bdd8
|
1211 1212 |
/* screen start address bit 19 */ if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) |
6683e01e2
|
1213 |
vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1); |
8503df659
|
1214 |
|
78d780e07
|
1215 |
if (is_laguna(cinfo)) { |
213d4bdd8
|
1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 |
tmp = 0; if ((htotal + 5) & 256) tmp |= 128; if (hdispend & 256) tmp |= 64; if (hsyncstart & 256) tmp |= 48; if (vtotal & 1024) tmp |= 8; if (vdispend & 1024) tmp |= 4; if (vsyncstart & 1024) tmp |= 3; vga_wcrt(regbase, CL_CRT1E, tmp); dev_dbg(info->device, "CRT1e: %d ", tmp); } |
8503df659
|
1234 1235 |
/* pixel panning */ vga_wattr(regbase, CL_AR33, 0); |
1da177e4c
|
1236 1237 1238 |
/* [ EGS: SetOffset(); ] */ /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */ |
8503df659
|
1239 |
AttrOn(cinfo); |
78d780e07
|
1240 |
if (is_laguna(cinfo)) { |
6e30fc086
|
1241 1242 1243 1244 1245 |
/* no tiles */ fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402); fb_writew(format, cinfo->laguna_mmio + 0xc0); fb_writew(threshold, cinfo->laguna_mmio + 0xea); } |
1da177e4c
|
1246 1247 1248 1249 1250 1251 1252 1253 |
/* finally, turn on everything - turn off "FullBandwidth" bit */ /* also, set "DotClock%2" bit where requested */ tmp = 0x01; /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ? if (var->vmode & FB_VMODE_CLOCK_HALVE) tmp |= 0x08; */ |
8503df659
|
1254 |
vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp); |
75ed3a17a
|
1255 1256 |
dev_dbg(info->device, "CL_SEQR1: %d ", tmp); |
1da177e4c
|
1257 |
|
1da177e4c
|
1258 |
#ifdef CIRRUSFB_DEBUG |
75ed3a17a
|
1259 |
cirrusfb_dbg_reg_dump(info, NULL); |
1da177e4c
|
1260 |
#endif |
1da177e4c
|
1261 1262 1263 1264 1265 |
return 0; } /* for some reason incomprehensible to me, cirrusfb requires that you write * the registers twice for the settings to take..grr. -dte */ |
8503df659
|
1266 |
static int cirrusfb_set_par(struct fb_info *info) |
1da177e4c
|
1267 |
{ |
8503df659
|
1268 1269 |
cirrusfb_set_par_foo(info); return cirrusfb_set_par_foo(info); |
1da177e4c
|
1270 |
} |
8503df659
|
1271 1272 1273 |
static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) |
1da177e4c
|
1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 |
{ struct cirrusfb_info *cinfo = info->par; if (regno > 255) return -EINVAL; if (info->fix.visual == FB_VISUAL_TRUECOLOR) { u32 v; red >>= (16 - info->var.red.length); green >>= (16 - info->var.green.length); blue >>= (16 - info->var.blue.length); |
8503df659
|
1285 |
if (regno >= 16) |
1da177e4c
|
1286 1287 1288 1289 |
return 1; v = (red << info->var.red.offset) | (green << info->var.green.offset) | (blue << info->var.blue.offset); |
060b6002b
|
1290 |
cinfo->pseudo_palette[regno] = v; |
1da177e4c
|
1291 1292 |
return 0; } |
8503df659
|
1293 1294 |
if (info->var.bits_per_pixel == 8) WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10); |
1da177e4c
|
1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 |
return 0; } /************************************************************************* cirrusfb_pan_display() performs display panning - provided hardware permits this **************************************************************************/ |
8503df659
|
1305 1306 |
static int cirrusfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
1da177e4c
|
1307 |
{ |
99a458475
|
1308 |
int xoffset; |
1da177e4c
|
1309 |
unsigned long base; |
213d4bdd8
|
1310 |
unsigned char tmp, xpix; |
1da177e4c
|
1311 |
struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
1312 1313 1314 1315 |
/* no range checks for xoffset and yoffset, */ /* as fb_pan_display has already done this */ if (var->vmode & FB_VMODE_YWRAP) return -EINVAL; |
1da177e4c
|
1316 |
xoffset = var->xoffset * info->var.bits_per_pixel / 8; |
1da177e4c
|
1317 |
|
99a458475
|
1318 |
base = var->yoffset * info->fix.line_length + xoffset; |
1da177e4c
|
1319 1320 1321 1322 1323 1324 1325 1326 |
if (info->var.bits_per_pixel == 1) { /* base is already correct */ xpix = (unsigned char) (var->xoffset % 8); } else { base /= 4; xpix = (unsigned char) ((xoffset % 4) * 2); } |
78d780e07
|
1327 |
if (!is_laguna(cinfo)) |
1b48cb563
|
1328 |
cirrusfb_WaitBLT(cinfo->regbase); |
1da177e4c
|
1329 1330 |
/* lower 8 + 8 bits of screen start address */ |
99a458475
|
1331 1332 |
vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); |
1da177e4c
|
1333 |
|
213d4bdd8
|
1334 1335 |
/* 0xf2 is %11110010, exclude tmp bits */ tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; |
1da177e4c
|
1336 1337 1338 1339 1340 1341 1342 |
/* construct bits 16, 17 and 18 of screen start address */ if (base & 0x10000) tmp |= 0x01; if (base & 0x20000) tmp |= 0x04; if (base & 0x40000) tmp |= 0x08; |
213d4bdd8
|
1343 |
vga_wcrt(cinfo->regbase, CL_CRT1B, tmp); |
1da177e4c
|
1344 1345 |
/* construct bit 19 of screen start address */ |
48c329e90
|
1346 |
if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) { |
78d780e07
|
1347 1348 1349 1350 1351 |
tmp = vga_rcrt(cinfo->regbase, CL_CRT1D); if (is_laguna(cinfo)) tmp = (tmp & ~0x18) | ((base >> 16) & 0x18); else tmp = (tmp & ~0x80) | ((base >> 12) & 0x80); |
48c329e90
|
1352 1353 |
vga_wcrt(cinfo->regbase, CL_CRT1D, tmp); } |
1da177e4c
|
1354 |
|
8503df659
|
1355 1356 1357 1358 |
/* write pixel panning value to AR33; this does not quite work in 8bpp * * ### Piccolo..? Will this work? */ |
1da177e4c
|
1359 |
if (info->var.bits_per_pixel == 1) |
8503df659
|
1360 |
vga_wattr(cinfo->regbase, CL_AR33, xpix); |
1da177e4c
|
1361 |
|
8503df659
|
1362 |
return 0; |
1da177e4c
|
1363 |
} |
8503df659
|
1364 |
static int cirrusfb_blank(int blank_mode, struct fb_info *info) |
1da177e4c
|
1365 1366 |
{ /* |
8503df659
|
1367 1368 1369 1370 1371 1372 1373 1374 1375 |
* Blank the screen if blank_mode != 0, else unblank. If blank == NULL * then the caller blanks by setting the CLUT (Color Look Up Table) * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking * failed due to e.g. a video mode which doesn't support it. * Implements VESA suspend and powerdown modes on hardware that * supports disabling hsync/vsync: * blank_mode == 2: suspend vsync * blank_mode == 3: suspend hsync * blank_mode == 4: powerdown |
1da177e4c
|
1376 1377 1378 1379 |
*/ unsigned char val; struct cirrusfb_info *cinfo = info->par; int current_mode = cinfo->blank_mode; |
75ed3a17a
|
1380 1381 |
dev_dbg(info->device, "ENTER, blank mode = %d ", blank_mode); |
1da177e4c
|
1382 1383 1384 |
if (info->state != FBINFO_STATE_RUNNING || current_mode == blank_mode) { |
75ed3a17a
|
1385 1386 |
dev_dbg(info->device, "EXIT, returning 0 "); |
1da177e4c
|
1387 1388 1389 1390 1391 |
return 0; } /* Undo current */ if (current_mode == FB_BLANK_NORMAL || |
213d4bdd8
|
1392 |
current_mode == FB_BLANK_UNBLANK) |
8503df659
|
1393 |
/* clear "FullBandwidth" bit */ |
213d4bdd8
|
1394 1395 |
val = 0; else |
8503df659
|
1396 |
/* set "FullBandwidth" bit */ |
213d4bdd8
|
1397 1398 1399 1400 |
val = 0x20; val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); |
1da177e4c
|
1401 1402 1403 1404 |
switch (blank_mode) { case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: |
213d4bdd8
|
1405 |
val = 0x00; |
1da177e4c
|
1406 1407 |
break; case FB_BLANK_VSYNC_SUSPEND: |
213d4bdd8
|
1408 |
val = 0x04; |
1da177e4c
|
1409 1410 |
break; case FB_BLANK_HSYNC_SUSPEND: |
213d4bdd8
|
1411 |
val = 0x02; |
1da177e4c
|
1412 1413 |
break; case FB_BLANK_POWERDOWN: |
213d4bdd8
|
1414 |
val = 0x06; |
1da177e4c
|
1415 1416 |
break; default: |
75ed3a17a
|
1417 1418 |
dev_dbg(info->device, "EXIT, returning 1 "); |
1da177e4c
|
1419 1420 |
return 1; } |
213d4bdd8
|
1421 |
vga_wgfx(cinfo->regbase, CL_GRE, val); |
1da177e4c
|
1422 |
cinfo->blank_mode = blank_mode; |
75ed3a17a
|
1423 1424 |
dev_dbg(info->device, "EXIT, returning 0 "); |
1da177e4c
|
1425 1426 1427 1428 |
/* Let fbcon do a soft blank for us */ return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; } |
213d4bdd8
|
1429 |
|
1da177e4c
|
1430 1431 1432 |
/**** END Hardware specific Routines **************************************/ /****************************************************************************/ /**** BEGIN Internal Routines ***********************************************/ |
9199ec5c5
|
1433 |
static void init_vgachip(struct fb_info *info) |
1da177e4c
|
1434 |
{ |
9199ec5c5
|
1435 |
struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
1436 |
const struct cirrusfb_board_info_rec *bi; |
8503df659
|
1437 |
assert(cinfo != NULL); |
1da177e4c
|
1438 1439 1440 1441 1442 1443 |
bi = &cirrusfb_board_info[cinfo->btype]; /* reset board globally */ switch (cinfo->btype) { case BT_PICCOLO: |
8503df659
|
1444 1445 1446 1447 |
WSFR(cinfo, 0x01); udelay(500); WSFR(cinfo, 0x51); udelay(500); |
1da177e4c
|
1448 1449 |
break; case BT_PICASSO: |
8503df659
|
1450 1451 |
WSFR2(cinfo, 0xff); udelay(500); |
1da177e4c
|
1452 1453 1454 |
break; case BT_SD64: case BT_SPECTRUM: |
8503df659
|
1455 1456 1457 1458 |
WSFR(cinfo, 0x1f); udelay(500); WSFR(cinfo, 0x4f); udelay(500); |
1da177e4c
|
1459 1460 |
break; case BT_PICASSO4: |
8503df659
|
1461 1462 1463 |
/* disable flickerfixer */ vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); mdelay(100); |
8503df659
|
1464 1465 |
/* mode */ vga_wgfx(cinfo->regbase, CL_GR31, 0x00); |
7cade31ca
|
1466 |
case BT_GD5480: /* fall through */ |
8503df659
|
1467 1468 |
/* from Klaus' NetBSD driver: */ vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); |
7cade31ca
|
1469 1470 1471 |
case BT_ALPINE: /* fall through */ /* put blitter into 542x compat */ vga_wgfx(cinfo->regbase, CL_GR33, 0x00); |
1da177e4c
|
1472 |
break; |
1b48cb563
|
1473 |
case BT_LAGUNA: |
78d780e07
|
1474 |
case BT_LAGUNAB: |
1da177e4c
|
1475 1476 1477 1478 |
/* Nothing to do to reset the board. */ break; default: |
75ed3a17a
|
1479 1480 |
dev_err(info->device, "Warning: Unknown board type "); |
1da177e4c
|
1481 1482 |
break; } |
9199ec5c5
|
1483 1484 |
/* make sure RAM size set by this point */ assert(info->screen_size > 0); |
1da177e4c
|
1485 1486 1487 |
/* the P4 is not fully initialized here; I rely on it having been */ /* inited under AmigaOS already, which seems to work just fine */ |
8503df659
|
1488 |
/* (Klaus advised to do it this way) */ |
1da177e4c
|
1489 1490 |
if (cinfo->btype != BT_PICASSO4) { |
8503df659
|
1491 1492 1493 |
WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */ WGen(cinfo, CL_POS102, 0x01); WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */ |
1da177e4c
|
1494 1495 |
if (cinfo->btype != BT_SD64) |
8503df659
|
1496 |
WGen(cinfo, CL_VSSM2, 0x01); |
1da177e4c
|
1497 |
|
8503df659
|
1498 |
/* reset sequencer logic */ |
1b48cb563
|
1499 |
vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); |
1da177e4c
|
1500 |
|
8503df659
|
1501 1502 |
/* FullBandwidth (video off) and 8/9 dot clock */ vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); |
1da177e4c
|
1503 |
|
8503df659
|
1504 1505 1506 1507 |
/* "magic cookie" - doesn't make any sense to me.. */ /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */ /* unlock all extension registers */ vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); |
1da177e4c
|
1508 |
|
1da177e4c
|
1509 1510 |
switch (cinfo->btype) { case BT_GD5480: |
8503df659
|
1511 |
vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); |
1da177e4c
|
1512 1513 |
break; case BT_ALPINE: |
1b48cb563
|
1514 |
case BT_LAGUNA: |
78d780e07
|
1515 |
case BT_LAGUNAB: |
1da177e4c
|
1516 1517 |
break; case BT_SD64: |
df3aafd57
|
1518 |
#ifdef CONFIG_ZORRO |
8503df659
|
1519 |
vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); |
df3aafd57
|
1520 |
#endif |
1da177e4c
|
1521 1522 |
break; default: |
8503df659
|
1523 1524 |
vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); |
1da177e4c
|
1525 1526 1527 |
break; } } |
8503df659
|
1528 1529 1530 1531 |
/* plane mask: nothing */ vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); /* character map select: doesn't even matter in gx mode */ vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); |
48c329e90
|
1532 1533 |
/* memory mode: chain4, ext. memory */ vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); |
1da177e4c
|
1534 1535 1536 |
/* controller-internal base address of video memory */ if (bi->init_sr07) |
8503df659
|
1537 |
vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07); |
1da177e4c
|
1538 |
|
8503df659
|
1539 1540 |
/* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */ /* EEPROM control: shouldn't be necessary to write to this at all.. */ |
1da177e4c
|
1541 |
|
8503df659
|
1542 1543 1544 1545 1546 1547 1548 1549 |
/* graphics cursor X position (incomplete; position gives rem. 3 bits */ vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); /* graphics cursor Y position (..."... ) */ vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); /* graphics cursor attributes */ vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); /* graphics cursor pattern address */ vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); |
1da177e4c
|
1550 1551 1552 |
/* writing these on a P4 might give problems.. */ if (cinfo->btype != BT_PICASSO4) { |
8503df659
|
1553 1554 1555 1556 |
/* configuration readback and ext. color */ vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); /* signature generator */ vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); |
1da177e4c
|
1557 |
} |
8503df659
|
1558 1559 1560 1561 1562 1563 |
/* Screen A preset row scan: none */ vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); /* Text cursor start: disable text cursor */ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); /* Text cursor end: - */ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); |
8503df659
|
1564 1565 1566 1567 1568 1569 1570 |
/* text cursor location high: 0 */ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); /* text cursor location low: 0 */ vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); /* Underline Row scanline: - */ vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); |
1da177e4c
|
1571 |
/* ### add 0x40 for text modes with > 30 MHz pixclock */ |
8503df659
|
1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 |
/* ext. display controls: ext.adr. wrap */ vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); /* Set/Reset registes: - */ vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); /* Set/Reset enable: - */ vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); /* Color Compare: - */ vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); /* Data Rotate: - */ vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); /* Read Map Select: - */ vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */ vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); /* Miscellaneous: memory map base address, graphics mode */ vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); /* Color Don't care: involve all planes */ vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); /* Bit Mask: no mask at all */ vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); |
1b48cb563
|
1593 |
|
df3aafd57
|
1594 1595 |
if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 || is_laguna(cinfo)) |
8503df659
|
1596 1597 |
/* (5434 can't have bit 3 set for bitblt) */ vga_wgfx(cinfo->regbase, CL_GRB, 0x20); |
1da177e4c
|
1598 |
else |
8503df659
|
1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 |
/* Graphics controller mode extensions: finer granularity, * 8byte data latches */ vga_wgfx(cinfo->regbase, CL_GRB, 0x28); vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ /* Background color byte 1: - */ /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */ /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */ /* Attribute Controller palette registers: "identity mapping" */ vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); /* Attribute Controller mode: graphics mode */ vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); /* Overscan color reg.: reg. 0 */ vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); /* Color Plane enable: Enable all 4 planes */ vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); |
8503df659
|
1635 1636 1637 1638 |
/* Color Select: - */ vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */ |
1da177e4c
|
1639 |
|
8503df659
|
1640 1641 1642 1643 |
/* BLT Start/status: Blitter reset */ vga_wgfx(cinfo->regbase, CL_GR31, 0x04); /* - " - : "end-of-reset" */ vga_wgfx(cinfo->regbase, CL_GR31, 0x00); |
1da177e4c
|
1644 1645 |
/* misc... */ |
8503df659
|
1646 |
WHDR(cinfo, 0); /* Hidden DAC register: - */ |
1da177e4c
|
1647 1648 |
return; } |
8503df659
|
1649 |
static void switch_monitor(struct cirrusfb_info *cinfo, int on) |
1da177e4c
|
1650 1651 1652 |
{ #ifdef CONFIG_ZORRO /* only works on Zorro boards */ static int IsOn = 0; /* XXX not ok for multiple boards */ |
1da177e4c
|
1653 1654 1655 1656 1657 1658 1659 1660 |
if (cinfo->btype == BT_PICASSO4) return; /* nothing to switch */ if (cinfo->btype == BT_ALPINE) return; /* nothing to switch */ if (cinfo->btype == BT_GD5480) return; /* nothing to switch */ if (cinfo->btype == BT_PICASSO) { if ((on && !IsOn) || (!on && IsOn)) |
8503df659
|
1661 |
WSFR(cinfo, 0xff); |
1da177e4c
|
1662 1663 1664 1665 1666 |
return; } if (on) { switch (cinfo->btype) { case BT_SD64: |
8503df659
|
1667 |
WSFR(cinfo, cinfo->SFR | 0x21); |
1da177e4c
|
1668 1669 |
break; case BT_PICCOLO: |
8503df659
|
1670 |
WSFR(cinfo, cinfo->SFR | 0x28); |
1da177e4c
|
1671 1672 |
break; case BT_SPECTRUM: |
8503df659
|
1673 |
WSFR(cinfo, 0x6f); |
1da177e4c
|
1674 1675 1676 1677 1678 1679 |
break; default: /* do nothing */ break; } } else { switch (cinfo->btype) { case BT_SD64: |
8503df659
|
1680 |
WSFR(cinfo, cinfo->SFR & 0xde); |
1da177e4c
|
1681 1682 |
break; case BT_PICCOLO: |
8503df659
|
1683 |
WSFR(cinfo, cinfo->SFR & 0xd7); |
1da177e4c
|
1684 1685 |
break; case BT_SPECTRUM: |
8503df659
|
1686 |
WSFR(cinfo, 0x4f); |
1da177e4c
|
1687 |
break; |
75ed3a17a
|
1688 1689 |
default: /* do nothing */ break; |
1da177e4c
|
1690 1691 |
} } |
1da177e4c
|
1692 1693 |
#endif /* CONFIG_ZORRO */ } |
1da177e4c
|
1694 1695 1696 |
/******************************************/ /* Linux 2.6-style accelerated functions */ /******************************************/ |
8343c89c4
|
1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 |
static int cirrusfb_sync(struct fb_info *info) { struct cirrusfb_info *cinfo = info->par; if (!is_laguna(cinfo)) { while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) cpu_relax(); } return 0; } |
8503df659
|
1707 1708 |
static void cirrusfb_fillrect(struct fb_info *info, const struct fb_fillrect *region) |
1da177e4c
|
1709 |
{ |
1da177e4c
|
1710 1711 |
struct fb_fillrect modded; int vxres, vyres; |
060b6002b
|
1712 1713 1714 1715 |
struct cirrusfb_info *cinfo = info->par; int m = info->var.bits_per_pixel; u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? cinfo->pseudo_palette[region->color] : region->color; |
1da177e4c
|
1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 |
if (info->state != FBINFO_STATE_RUNNING) return; if (info->flags & FBINFO_HWACCEL_DISABLED) { cfb_fillrect(info, region); return; } vxres = info->var.xres_virtual; vyres = info->var.yres_virtual; memcpy(&modded, region, sizeof(struct fb_fillrect)); |
8503df659
|
1728 |
if (!modded.width || !modded.height || |
1da177e4c
|
1729 1730 |
modded.dx >= vxres || modded.dy >= vyres) return; |
8503df659
|
1731 1732 1733 1734 |
if (modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; if (modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; |
1da177e4c
|
1735 |
|
060b6002b
|
1736 1737 1738 1739 |
cirrusfb_RectFill(cinfo->regbase, info->var.bits_per_pixel, (region->dx * m) / 8, region->dy, (region->width * m) / 8, region->height, |
9e8480625
|
1740 1741 |
color, color, info->fix.line_length, 0x40); |
1da177e4c
|
1742 |
} |
8503df659
|
1743 1744 |
static void cirrusfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) |
1da177e4c
|
1745 |
{ |
1da177e4c
|
1746 1747 |
struct fb_copyarea modded; u32 vxres, vyres; |
060b6002b
|
1748 1749 |
struct cirrusfb_info *cinfo = info->par; int m = info->var.bits_per_pixel; |
1da177e4c
|
1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 |
if (info->state != FBINFO_STATE_RUNNING) return; if (info->flags & FBINFO_HWACCEL_DISABLED) { cfb_copyarea(info, area); return; } vxres = info->var.xres_virtual; vyres = info->var.yres_virtual; |
060b6002b
|
1760 |
memcpy(&modded, area, sizeof(struct fb_copyarea)); |
1da177e4c
|
1761 |
|
8503df659
|
1762 |
if (!modded.width || !modded.height || |
1da177e4c
|
1763 1764 1765 |
modded.sx >= vxres || modded.sy >= vyres || modded.dx >= vxres || modded.dy >= vyres) return; |
8503df659
|
1766 1767 1768 1769 1770 1771 1772 1773 |
if (modded.sx + modded.width > vxres) modded.width = vxres - modded.sx; if (modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; if (modded.sy + modded.height > vyres) modded.height = vyres - modded.sy; if (modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; |
1da177e4c
|
1774 |
|
060b6002b
|
1775 1776 1777 1778 |
cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel, (area->sx * m) / 8, area->sy, (area->dx * m) / 8, area->dy, (area->width * m) / 8, area->height, |
0ff1edeef
|
1779 |
info->fix.line_length); |
060b6002b
|
1780 |
|
1da177e4c
|
1781 |
} |
8503df659
|
1782 1783 |
static void cirrusfb_imageblit(struct fb_info *info, const struct fb_image *image) |
1da177e4c
|
1784 1785 |
{ struct cirrusfb_info *cinfo = info->par; |
7cade31ca
|
1786 |
unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4; |
1da177e4c
|
1787 |
|
9e8480625
|
1788 1789 |
if (info->state != FBINFO_STATE_RUNNING) return; |
df3aafd57
|
1790 1791 1792 1793 1794 |
/* Alpine/SD64 does not work at 24bpp ??? */ if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) cfb_imageblit(info, image); else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) && op == 0xc) |
9e8480625
|
1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 |
cfb_imageblit(info, image); else { unsigned size = ((image->width + 7) >> 3) * image->height; int m = info->var.bits_per_pixel; u32 fg, bg; if (info->var.bits_per_pixel == 8) { fg = image->fg_color; bg = image->bg_color; } else { fg = ((u32 *)(info->pseudo_palette))[image->fg_color]; bg = ((u32 *)(info->pseudo_palette))[image->bg_color]; } |
7cade31ca
|
1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 |
if (info->var.bits_per_pixel == 24) { /* clear background first */ cirrusfb_RectFill(cinfo->regbase, info->var.bits_per_pixel, (image->dx * m) / 8, image->dy, (image->width * m) / 8, image->height, bg, bg, info->fix.line_length, 0x40); } |
9e8480625
|
1818 1819 1820 1821 1822 |
cirrusfb_RectFill(cinfo->regbase, info->var.bits_per_pixel, (image->dx * m) / 8, image->dy, (image->width * m) / 8, image->height, fg, bg, |
7cade31ca
|
1823 |
info->fix.line_length, op); |
9e8480625
|
1824 1825 |
memcpy(info->screen_base, image->data, size); } |
1da177e4c
|
1826 |
} |
1da177e4c
|
1827 1828 1829 |
#ifdef CONFIG_PPC_PREP #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000) #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000) |
8503df659
|
1830 |
static void get_prep_addrs(unsigned long *display, unsigned long *registers) |
1da177e4c
|
1831 |
{ |
1da177e4c
|
1832 1833 |
*display = PREP_VIDEO_BASE; *registers = (unsigned long) PREP_IO_BASE; |
1da177e4c
|
1834 1835 1836 |
} #endif /* CONFIG_PPC_PREP */ |
1da177e4c
|
1837 |
#ifdef CONFIG_PCI |
8503df659
|
1838 |
static int release_io_ports; |
1da177e4c
|
1839 1840 1841 1842 1843 |
/* Pulled the logic from XFree86 Cirrus driver to get the memory size, * based on the DRAM bandwidth bit and DRAM bank switching bit. This * works with 1MB, 2MB and 4MB configurations (which the Motorola boards * seem to have. */ |
75ed3a17a
|
1844 1845 |
static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info, u8 __iomem *regbase) |
1da177e4c
|
1846 1847 |
{ unsigned long mem; |
55a4ea6ab
|
1848 |
struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
1849 |
|
78d780e07
|
1850 |
if (is_laguna(cinfo)) { |
55a4ea6ab
|
1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 |
unsigned char SR14 = vga_rseq(regbase, CL_SEQR14); mem = ((SR14 & 7) + 1) << 20; } else { unsigned char SRF = vga_rseq(regbase, CL_SEQRF); switch ((SRF & 0x18)) { case 0x08: mem = 512 * 1024; break; case 0x10: mem = 1024 * 1024; break; /* 64-bit DRAM data bus width; assume 2MB. * Also indicates 2MB memory on the 5430. */ case 0x18: mem = 2048 * 1024; break; default: dev_warn(info->device, "Unknown memory size! "); mem = 1024 * 1024; } /* If DRAM bank switching is enabled, there must be * twice as much memory installed. (4MB on the 5434) */ |
df3aafd57
|
1877 |
if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0) |
55a4ea6ab
|
1878 |
mem *= 2; |
1da177e4c
|
1879 |
} |
8503df659
|
1880 |
|
1da177e4c
|
1881 |
/* TODO: Handling of GD5446/5480 (see XF86 sources ...) */ |
1da177e4c
|
1882 1883 |
return mem; } |
8503df659
|
1884 1885 |
static void get_pci_addrs(const struct pci_dev *pdev, unsigned long *display, unsigned long *registers) |
1da177e4c
|
1886 |
{ |
8503df659
|
1887 1888 1889 |
assert(pdev != NULL); assert(display != NULL); assert(registers != NULL); |
1da177e4c
|
1890 |
|
1da177e4c
|
1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 |
*display = 0; *registers = 0; /* This is a best-guess for now */ if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) { *display = pci_resource_start(pdev, 1); *registers = pci_resource_start(pdev, 0); } else { *display = pci_resource_start(pdev, 0); *registers = pci_resource_start(pdev, 1); } |
8503df659
|
1903 |
assert(*display != 0); |
1da177e4c
|
1904 |
} |
9199ec5c5
|
1905 |
static void cirrusfb_pci_unmap(struct fb_info *info) |
1da177e4c
|
1906 |
{ |
64beab14f
|
1907 |
struct pci_dev *pdev = to_pci_dev(info->device); |
6e30fc086
|
1908 |
struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
1909 |
|
6e30fc086
|
1910 1911 |
if (cinfo->laguna_mmio == NULL) iounmap(cinfo->laguna_mmio); |
9199ec5c5
|
1912 |
iounmap(info->screen_base); |
1da177e4c
|
1913 1914 1915 1916 1917 1918 |
#if 0 /* if system didn't claim this region, we would... */ release_mem_region(0xA0000, 65535); #endif if (release_io_ports) release_region(0x3C0, 32); pci_release_regions(pdev); |
1da177e4c
|
1919 1920 |
} #endif /* CONFIG_PCI */ |
1da177e4c
|
1921 |
#ifdef CONFIG_ZORRO |
f5ee051e7
|
1922 |
static void cirrusfb_zorro_unmap(struct fb_info *info) |
1da177e4c
|
1923 |
{ |
d91f5bb69
|
1924 |
struct cirrusfb_info *cinfo = info->par; |
64beab14f
|
1925 1926 1927 |
struct zorro_dev *zdev = to_zorro_dev(info->device); zorro_release_device(zdev); |
1da177e4c
|
1928 1929 1930 |
if (cinfo->btype == BT_PICASSO4) { cinfo->regbase -= 0x600000; |
8503df659
|
1931 |
iounmap((void *)cinfo->regbase); |
9199ec5c5
|
1932 |
iounmap(info->screen_base); |
1da177e4c
|
1933 |
} else { |
64beab14f
|
1934 |
if (zorro_resource_start(zdev) > 0x01000000) |
9199ec5c5
|
1935 |
iounmap(info->screen_base); |
1da177e4c
|
1936 |
} |
1da177e4c
|
1937 1938 |
} #endif /* CONFIG_ZORRO */ |
48c329e90
|
1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 |
/* function table of the above functions */ static struct fb_ops cirrusfb_ops = { .owner = THIS_MODULE, .fb_open = cirrusfb_open, .fb_release = cirrusfb_release, .fb_setcolreg = cirrusfb_setcolreg, .fb_check_var = cirrusfb_check_var, .fb_set_par = cirrusfb_set_par, .fb_pan_display = cirrusfb_pan_display, .fb_blank = cirrusfb_blank, .fb_fillrect = cirrusfb_fillrect, .fb_copyarea = cirrusfb_copyarea, |
8343c89c4
|
1951 |
.fb_sync = cirrusfb_sync, |
48c329e90
|
1952 1953 |
.fb_imageblit = cirrusfb_imageblit, }; |
c395d3e8c
|
1954 |
static int __devinit cirrusfb_set_fbinfo(struct fb_info *info) |
1da177e4c
|
1955 |
{ |
9199ec5c5
|
1956 |
struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
1957 |
struct fb_var_screeninfo *var = &info->var; |
1da177e4c
|
1958 1959 1960 1961 1962 |
info->pseudo_palette = cinfo->pseudo_palette; info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_XPAN | FBINFO_HWACCEL_YPAN | FBINFO_HWACCEL_FILLRECT |
9e8480625
|
1963 |
| FBINFO_HWACCEL_IMAGEBLIT |
1da177e4c
|
1964 |
| FBINFO_HWACCEL_COPYAREA; |
614c0dc93
|
1965 |
if (noaccel || is_laguna(cinfo)) { |
1da177e4c
|
1966 |
info->flags |= FBINFO_HWACCEL_DISABLED; |
614c0dc93
|
1967 1968 1969 |
info->fix.accel = FB_ACCEL_NONE; } else info->fix.accel = FB_ACCEL_CIRRUS_ALPINE; |
1da177e4c
|
1970 |
info->fbops = &cirrusfb_ops; |
9e8480625
|
1971 |
|
1da177e4c
|
1972 1973 1974 |
if (cinfo->btype == BT_GD5480) { if (var->bits_per_pixel == 16) info->screen_base += 1 * MB_; |
1cea9a9a6
|
1975 |
if (var->bits_per_pixel == 32) |
1da177e4c
|
1976 1977 1978 1979 1980 1981 1982 1983 1984 |
info->screen_base += 2 * MB_; } /* Fill fix common fields */ strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name, sizeof(info->fix.id)); /* monochrome: only 1 memory plane */ /* 8 bit and above: Use whole memory area */ |
9199ec5c5
|
1985 1986 1987 |
info->fix.smem_len = info->screen_size; if (var->bits_per_pixel == 1) info->fix.smem_len /= 4; |
1da177e4c
|
1988 |
info->fix.type_aux = 0; |
1da177e4c
|
1989 1990 1991 |
info->fix.xpanstep = 1; info->fix.ypanstep = 1; info->fix.ywrapstep = 0; |
1da177e4c
|
1992 1993 |
/* FIXME: map region at 0xB8000 if available, fill in here */ |
1da177e4c
|
1994 |
info->fix.mmio_len = 0; |
1da177e4c
|
1995 1996 1997 1998 1999 |
fb_alloc_cmap(&info->cmap, 256, 0); return 0; } |
c395d3e8c
|
2000 |
static int __devinit cirrusfb_register(struct fb_info *info) |
1da177e4c
|
2001 |
{ |
9199ec5c5
|
2002 |
struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
2003 |
int err; |
1da177e4c
|
2004 2005 |
/* sanity checks */ |
48c329e90
|
2006 |
assert(cinfo->btype != BT_NONE); |
1da177e4c
|
2007 |
|
a1d35a7a5
|
2008 2009 |
/* set all the vital stuff */ cirrusfb_set_fbinfo(info); |
75ed3a17a
|
2010 2011 |
dev_dbg(info->device, "(RAM start set to: 0x%p) ", info->screen_base); |
1da177e4c
|
2012 |
|
a1d35a7a5
|
2013 2014 |
err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); if (!err) { |
75ed3a17a
|
2015 2016 |
dev_dbg(info->device, "wrong initial video mode "); |
a1d35a7a5
|
2017 2018 2019 |
err = -EINVAL; goto err_dealloc_cmap; } |
1da177e4c
|
2020 |
info->var.activate = FB_ACTIVATE_NOW; |
99a458475
|
2021 |
err = cirrusfb_check_var(&info->var, info); |
1da177e4c
|
2022 2023 |
if (err < 0) { /* should never happen */ |
75ed3a17a
|
2024 2025 2026 |
dev_dbg(info->device, "choking on default var... umm, no good. "); |
a1d35a7a5
|
2027 |
goto err_dealloc_cmap; |
1da177e4c
|
2028 |
} |
1da177e4c
|
2029 2030 |
err = register_framebuffer(info); if (err < 0) { |
75ed3a17a
|
2031 2032 2033 |
dev_err(info->device, "could not register fb device; err = %d! ", err); |
1da177e4c
|
2034 2035 |
goto err_dealloc_cmap; } |
1da177e4c
|
2036 2037 2038 2039 |
return 0; err_dealloc_cmap: fb_dealloc_cmap(&info->cmap); |
1da177e4c
|
2040 2041 |
return err; } |
8503df659
|
2042 |
static void __devexit cirrusfb_cleanup(struct fb_info *info) |
1da177e4c
|
2043 2044 |
{ struct cirrusfb_info *cinfo = info->par; |
1da177e4c
|
2045 |
|
8503df659
|
2046 |
switch_monitor(cinfo, 0); |
8503df659
|
2047 2048 |
unregister_framebuffer(info); fb_dealloc_cmap(&info->cmap); |
75ed3a17a
|
2049 2050 |
dev_dbg(info->device, "Framebuffer unregistered "); |
9199ec5c5
|
2051 |
cinfo->unmap(info); |
060b6002b
|
2052 |
framebuffer_release(info); |
1da177e4c
|
2053 |
} |
1da177e4c
|
2054 |
#ifdef CONFIG_PCI |
c395d3e8c
|
2055 2056 |
static int __devinit cirrusfb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4c
|
2057 2058 2059 |
{ struct cirrusfb_info *cinfo; struct fb_info *info; |
1da177e4c
|
2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 |
unsigned long board_addr, board_size; int ret; ret = pci_enable_device(pdev); if (ret < 0) { printk(KERN_ERR "cirrusfb: Cannot enable PCI device "); goto err_out; } info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev); if (!info) { printk(KERN_ERR "cirrusfb: could not allocate memory "); ret = -ENOMEM; |
78d780e07
|
2075 |
goto err_out; |
1da177e4c
|
2076 2077 2078 |
} cinfo = info->par; |
48c329e90
|
2079 |
cinfo->btype = (enum cirrus_board) ent->driver_data; |
1da177e4c
|
2080 |
|
75ed3a17a
|
2081 2082 2083 |
dev_dbg(info->device, " Found PCI device, base address 0 is 0x%Lx, btype set to %d ", |
48c329e90
|
2084 |
(unsigned long long)pdev->resource[0].start, cinfo->btype); |
75ed3a17a
|
2085 2086 2087 |
dev_dbg(info->device, " base address 1 is 0x%Lx ", (unsigned long long)pdev->resource[1].start); |
1da177e4c
|
2088 |
|
8503df659
|
2089 2090 |
if (isPReP) { pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000); |
1da177e4c
|
2091 |
#ifdef CONFIG_PPC_PREP |
9199ec5c5
|
2092 |
get_prep_addrs(&board_addr, &info->fix.mmio_start); |
1da177e4c
|
2093 |
#endif |
8503df659
|
2094 |
/* PReP dies if we ioremap the IO registers, but it works w/out... */ |
9199ec5c5
|
2095 |
cinfo->regbase = (char __iomem *) info->fix.mmio_start; |
1da177e4c
|
2096 |
} else { |
75ed3a17a
|
2097 2098 2099 |
dev_dbg(info->device, "Attempt to get PCI info for Cirrus Graphics Card "); |
9199ec5c5
|
2100 |
get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start); |
8503df659
|
2101 2102 |
/* FIXME: this forces VGA. alternatives? */ cinfo->regbase = NULL; |
6e30fc086
|
2103 |
cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000); |
1da177e4c
|
2104 |
} |
75ed3a17a
|
2105 2106 |
dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx ", |
9199ec5c5
|
2107 |
board_addr, info->fix.mmio_start); |
1da177e4c
|
2108 |
|
48c329e90
|
2109 |
board_size = (cinfo->btype == BT_GD5480) ? |
75ed3a17a
|
2110 |
32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase); |
1da177e4c
|
2111 2112 |
ret = pci_request_regions(pdev, "cirrusfb"); |
8503df659
|
2113 |
if (ret < 0) { |
75ed3a17a
|
2114 2115 2116 |
dev_err(info->device, "cannot reserve region 0x%lx, abort ", board_addr); |
1da177e4c
|
2117 2118 2119 2120 |
goto err_release_fb; } #if 0 /* if the system didn't claim this region, we would... */ if (!request_mem_region(0xA0000, 65535, "cirrusfb")) { |
75ed3a17a
|
2121 2122 2123 |
dev_err(info->device, "cannot reserve region 0x%lx, abort ", 0xA0000L); |
1da177e4c
|
2124 2125 2126 2127 2128 2129 |
ret = -EBUSY; goto err_release_regions; } #endif if (request_region(0x3C0, 32, "cirrusfb")) release_io_ports = 1; |
9199ec5c5
|
2130 2131 |
info->screen_base = ioremap(board_addr, board_size); if (!info->screen_base) { |
1da177e4c
|
2132 2133 2134 |
ret = -EIO; goto err_release_legacy; } |
9199ec5c5
|
2135 2136 |
info->fix.smem_start = board_addr; info->screen_size = board_size; |
1da177e4c
|
2137 |
cinfo->unmap = cirrusfb_pci_unmap; |
75ed3a17a
|
2138 2139 2140 2141 |
dev_info(info->device, "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx ", info->screen_size >> 10, board_addr); |
1da177e4c
|
2142 |
pci_set_drvdata(pdev, info); |
9199ec5c5
|
2143 |
ret = cirrusfb_register(info); |
78d780e07
|
2144 2145 |
if (!ret) return 0; |
1da177e4c
|
2146 |
|
78d780e07
|
2147 2148 |
pci_set_drvdata(pdev, NULL); iounmap(info->screen_base); |
1da177e4c
|
2149 2150 2151 2152 2153 2154 2155 2156 2157 |
err_release_legacy: if (release_io_ports) release_region(0x3C0, 32); #if 0 release_mem_region(0xA0000, 65535); err_release_regions: #endif pci_release_regions(pdev); err_release_fb: |
78d780e07
|
2158 |
if (cinfo->laguna_mmio != NULL) |
6e30fc086
|
2159 |
iounmap(cinfo->laguna_mmio); |
1da177e4c
|
2160 |
framebuffer_release(info); |
1da177e4c
|
2161 2162 2163 |
err_out: return ret; } |
8503df659
|
2164 |
static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev) |
1da177e4c
|
2165 2166 |
{ struct fb_info *info = pci_get_drvdata(pdev); |
1da177e4c
|
2167 |
|
8503df659
|
2168 |
cirrusfb_cleanup(info); |
1da177e4c
|
2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 |
} static struct pci_driver cirrusfb_pci_driver = { .name = "cirrusfb", .id_table = cirrusfb_pci_table, .probe = cirrusfb_pci_register, .remove = __devexit_p(cirrusfb_pci_unregister), #ifdef CONFIG_PM #if 0 .suspend = cirrusfb_pci_suspend, .resume = cirrusfb_pci_resume, #endif #endif }; #endif /* CONFIG_PCI */ |
1da177e4c
|
2184 |
#ifdef CONFIG_ZORRO |
c395d3e8c
|
2185 2186 |
static int __devinit cirrusfb_zorro_register(struct zorro_dev *z, const struct zorro_device_id *ent) |
1da177e4c
|
2187 2188 2189 |
{ struct cirrusfb_info *cinfo; struct fb_info *info; |
7345de32d
|
2190 |
enum cirrus_board btype; |
1da177e4c
|
2191 2192 2193 2194 2195 2196 2197 2198 |
struct zorro_dev *z2 = NULL; unsigned long board_addr, board_size, size; int ret; btype = ent->driver_data; if (cirrusfb_zorro_table2[btype].id2) z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL); size = cirrusfb_zorro_table2[btype].size; |
1da177e4c
|
2199 2200 2201 |
info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev); if (!info) { |
8503df659
|
2202 2203 |
printk(KERN_ERR "cirrusfb: could not allocate memory "); |
1da177e4c
|
2204 2205 2206 |
ret = -ENOMEM; goto err_out; } |
75ed3a17a
|
2207 2208 2209 |
dev_info(info->device, "%s board detected ", cirrusfb_board_info[btype].name); |
1da177e4c
|
2210 |
cinfo = info->par; |
1da177e4c
|
2211 |
cinfo->btype = btype; |
36ea96a48
|
2212 |
assert(z); |
8503df659
|
2213 |
assert(btype != BT_NONE); |
1da177e4c
|
2214 |
|
1da177e4c
|
2215 2216 |
board_addr = zorro_resource_start(z); board_size = zorro_resource_len(z); |
9199ec5c5
|
2217 |
info->screen_size = size; |
1da177e4c
|
2218 2219 |
if (!zorro_request_device(z, "cirrusfb")) { |
75ed3a17a
|
2220 2221 2222 |
dev_err(info->device, "cannot reserve region 0x%lx, abort ", board_addr); |
1da177e4c
|
2223 2224 2225 |
ret = -EBUSY; goto err_release_fb; } |
1da177e4c
|
2226 2227 2228 |
ret = -EIO; if (btype == BT_PICASSO4) { |
75ed3a17a
|
2229 2230 |
dev_info(info->device, " REG at $%lx ", board_addr + 0x600000); |
1da177e4c
|
2231 2232 2233 2234 2235 |
/* To be precise, for the P4 this is not the */ /* begin of the board, but the begin of RAM. */ /* for P4, map in its address space in 2 chunks (### TEST! ) */ /* (note the ugly hardcoded 16M number) */ |
8503df659
|
2236 |
cinfo->regbase = ioremap(board_addr, 16777216); |
1da177e4c
|
2237 2238 |
if (!cinfo->regbase) goto err_release_region; |
75ed3a17a
|
2239 2240 |
dev_dbg(info->device, "Virtual address for board set to: $%p ", |
8503df659
|
2241 |
cinfo->regbase); |
1da177e4c
|
2242 |
cinfo->regbase += 0x600000; |
9199ec5c5
|
2243 |
info->fix.mmio_start = board_addr + 0x600000; |
1da177e4c
|
2244 |
|
9199ec5c5
|
2245 2246 2247 |
info->fix.smem_start = board_addr + 16777216; info->screen_base = ioremap(info->fix.smem_start, 16777216); if (!info->screen_base) |
1da177e4c
|
2248 2249 |
goto err_unmap_regbase; } else { |
75ed3a17a
|
2250 2251 2252 |
dev_info(info->device, " REG at $%lx ", (unsigned long) z2->resource.start); |
1da177e4c
|
2253 |
|
9199ec5c5
|
2254 |
info->fix.smem_start = board_addr; |
1da177e4c
|
2255 |
if (board_addr > 0x01000000) |
9199ec5c5
|
2256 |
info->screen_base = ioremap(board_addr, board_size); |
1da177e4c
|
2257 |
else |
9199ec5c5
|
2258 2259 |
info->screen_base = (caddr_t) ZTWO_VADDR(board_addr); if (!info->screen_base) |
1da177e4c
|
2260 2261 2262 |
goto err_release_region; /* set address for REG area of board */ |
8503df659
|
2263 |
cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start); |
9199ec5c5
|
2264 |
info->fix.mmio_start = z2->resource.start; |
1da177e4c
|
2265 |
|
75ed3a17a
|
2266 2267 |
dev_dbg(info->device, "Virtual address for board set to: $%p ", |
8503df659
|
2268 |
cinfo->regbase); |
1da177e4c
|
2269 2270 |
} cinfo->unmap = cirrusfb_zorro_unmap; |
75ed3a17a
|
2271 2272 2273 2274 |
dev_info(info->device, "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx ", board_size / MB_, board_addr); |
1da177e4c
|
2275 |
zorro_set_drvdata(z, info); |
8f19e15b8
|
2276 2277 2278 2279 |
/* MCLK select etc. */ if (cirrusfb_board_info[btype].init_sr1f) vga_wseq(cinfo->regbase, CL_SEQR1F, cirrusfb_board_info[btype].sr1f); |
d91f5bb69
|
2280 |
ret = cirrusfb_register(info); |
bc5d8ac02
|
2281 2282 2283 2284 2285 |
if (!ret) return 0; if (btype == BT_PICASSO4 || board_addr > 0x01000000) iounmap(info->screen_base); |
1da177e4c
|
2286 2287 |
err_unmap_regbase: |
bc5d8ac02
|
2288 2289 |
if (btype == BT_PICASSO4) iounmap(cinfo->regbase - 0x600000); |
1da177e4c
|
2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 |
err_release_region: release_region(board_addr, board_size); err_release_fb: framebuffer_release(info); err_out: return ret; } void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z) { struct fb_info *info = zorro_get_drvdata(z); |
1da177e4c
|
2301 |
|
8503df659
|
2302 |
cirrusfb_cleanup(info); |
1da177e4c
|
2303 2304 2305 2306 2307 2308 2309 2310 2311 |
} static struct zorro_driver cirrusfb_zorro_driver = { .name = "cirrusfb", .id_table = cirrusfb_zorro_table, .probe = cirrusfb_zorro_register, .remove = __devexit_p(cirrusfb_zorro_unregister), }; #endif /* CONFIG_ZORRO */ |
1da177e4c
|
2312 |
#ifndef MODULE |
75ed3a17a
|
2313 2314 |
static int __init cirrusfb_setup(char *options) { |
ee11940f8
|
2315 |
char *this_opt; |
1da177e4c
|
2316 |
|
1da177e4c
|
2317 2318 |
if (!options || !*options) return 0; |
8503df659
|
2319 |
while ((this_opt = strsep(&options, ",")) != NULL) { |
a1d35a7a5
|
2320 2321 |
if (!*this_opt) continue; |
1da177e4c
|
2322 |
|
1da177e4c
|
2323 2324 |
if (!strcmp(this_opt, "noaccel")) noaccel = 1; |
a1d35a7a5
|
2325 2326 2327 2328 |
else if (!strncmp(this_opt, "mode:", 5)) mode_option = this_opt + 5; else mode_option = this_opt; |
1da177e4c
|
2329 2330 2331 2332 |
} return 0; } #endif |
1da177e4c
|
2333 2334 2335 2336 2337 2338 2339 |
/* * Modularization */ MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>"); MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips"); MODULE_LICENSE("GPL"); |
48c329e90
|
2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 |
static int __init cirrusfb_init(void) { int error = 0; #ifndef MODULE char *option = NULL; if (fb_get_options("cirrusfb", &option)) return -ENODEV; cirrusfb_setup(option); #endif #ifdef CONFIG_ZORRO error |= zorro_register_driver(&cirrusfb_zorro_driver); #endif #ifdef CONFIG_PCI error |= pci_register_driver(&cirrusfb_pci_driver); #endif return error; } |
8503df659
|
2360 |
static void __exit cirrusfb_exit(void) |
1da177e4c
|
2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 |
{ #ifdef CONFIG_PCI pci_unregister_driver(&cirrusfb_pci_driver); #endif #ifdef CONFIG_ZORRO zorro_unregister_driver(&cirrusfb_zorro_driver); #endif } module_init(cirrusfb_init); |
a1d35a7a5
|
2371 2372 |
module_param(mode_option, charp, 0); MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); |
55a0dd83e
|
2373 2374 |
module_param(noaccel, bool, 0); MODULE_PARM_DESC(noaccel, "Disable acceleration"); |
a1d35a7a5
|
2375 |
|
1da177e4c
|
2376 2377 2378 |
#ifdef MODULE module_exit(cirrusfb_exit); #endif |
1da177e4c
|
2379 2380 2381 2382 |
/**********************************************************************/ /* about the following functions - I have used the same names for the */ /* functions as Markus Wild did in his Retina driver for NetBSD as */ /* they just made sense for this purpose. Apart from that, I wrote */ |
8503df659
|
2383 |
/* these functions myself. */ |
1da177e4c
|
2384 2385 2386 |
/**********************************************************************/ /*** WGen() - write into one of the external/general registers ***/ |
8503df659
|
2387 |
static void WGen(const struct cirrusfb_info *cinfo, |
1da177e4c
|
2388 2389 2390 2391 2392 2393 |
int regnum, unsigned char val) { unsigned long regofs = 0; if (cinfo->btype == BT_PICASSO) { /* Picasso II specific hack */ |
8503df659
|
2394 2395 |
/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */ |
1da177e4c
|
2396 2397 2398 |
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D) regofs = 0xfff; } |
8503df659
|
2399 |
vga_w(cinfo->regbase, regofs + regnum, val); |
1da177e4c
|
2400 2401 2402 |
} /*** RGen() - read out one of the external/general registers ***/ |
8503df659
|
2403 |
static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum) |
1da177e4c
|
2404 2405 2406 2407 2408 |
{ unsigned long regofs = 0; if (cinfo->btype == BT_PICASSO) { /* Picasso II specific hack */ |
8503df659
|
2409 2410 |
/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || regnum == CL_VSSM2) */ |
1da177e4c
|
2411 2412 2413 |
if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D) regofs = 0xfff; } |
8503df659
|
2414 |
return vga_r(cinfo->regbase, regofs + regnum); |
1da177e4c
|
2415 2416 2417 |
} /*** AttrOn() - turn on VideoEnable for Attribute controller ***/ |
8503df659
|
2418 |
static void AttrOn(const struct cirrusfb_info *cinfo) |
1da177e4c
|
2419 |
{ |
8503df659
|
2420 |
assert(cinfo != NULL); |
1da177e4c
|
2421 |
|
8503df659
|
2422 |
if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { |
1da177e4c
|
2423 2424 |
/* if we're just in "write value" mode, write back the */ /* same value as before to not modify anything */ |
8503df659
|
2425 2426 |
vga_w(cinfo->regbase, VGA_ATT_IW, vga_r(cinfo->regbase, VGA_ATT_R)); |
1da177e4c
|
2427 2428 |
} /* turn on video bit */ |
8503df659
|
2429 2430 |
/* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */ vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); |
1da177e4c
|
2431 2432 |
/* dummy write on Reg0 to be on "write index" mode next time */ |
8503df659
|
2433 |
vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); |
1da177e4c
|
2434 2435 2436 2437 2438 2439 2440 2441 |
} /*** WHDR() - write into the Hidden DAC register ***/ /* as the HDR is the only extension register that requires special treatment * (the other extension registers are accessible just like the "ordinary" * registers of their functional group) here is a specialized routine for * accessing the HDR */ |
8503df659
|
2442 |
static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val) |
1da177e4c
|
2443 2444 |
{ unsigned char dummy; |
78d780e07
|
2445 |
if (is_laguna(cinfo)) |
1b48cb563
|
2446 |
return; |
1da177e4c
|
2447 2448 2449 |
if (cinfo->btype == BT_PICASSO) { /* Klaus' hint for correct access to HDR on some boards */ /* first write 0 to pixel mask (3c6) */ |
8503df659
|
2450 2451 |
WGen(cinfo, VGA_PEL_MSK, 0x00); udelay(200); |
1da177e4c
|
2452 |
/* next read dummy from pixel address (3c8) */ |
8503df659
|
2453 2454 |
dummy = RGen(cinfo, VGA_PEL_IW); udelay(200); |
1da177e4c
|
2455 2456 |
} /* now do the usual stuff to access the HDR */ |
8503df659
|
2457 2458 2459 2460 2461 2462 2463 2464 |
dummy = RGen(cinfo, VGA_PEL_MSK); udelay(200); dummy = RGen(cinfo, VGA_PEL_MSK); udelay(200); dummy = RGen(cinfo, VGA_PEL_MSK); udelay(200); dummy = RGen(cinfo, VGA_PEL_MSK); udelay(200); |
1da177e4c
|
2465 |
|
8503df659
|
2466 2467 |
WGen(cinfo, VGA_PEL_MSK, val); udelay(200); |
1da177e4c
|
2468 2469 2470 |
if (cinfo->btype == BT_PICASSO) { /* now first reset HDR access counter */ |
8503df659
|
2471 2472 |
dummy = RGen(cinfo, VGA_PEL_IW); udelay(200); |
1da177e4c
|
2473 2474 2475 |
/* and at the end, restore the mask value */ /* ## is this mask always 0xff? */ |
8503df659
|
2476 2477 |
WGen(cinfo, VGA_PEL_MSK, 0xff); udelay(200); |
1da177e4c
|
2478 2479 |
} } |
1da177e4c
|
2480 |
/*** WSFR() - write to the "special function register" (SFR) ***/ |
8503df659
|
2481 |
static void WSFR(struct cirrusfb_info *cinfo, unsigned char val) |
1da177e4c
|
2482 2483 |
{ #ifdef CONFIG_ZORRO |
8503df659
|
2484 |
assert(cinfo->regbase != NULL); |
1da177e4c
|
2485 |
cinfo->SFR = val; |
8503df659
|
2486 |
z_writeb(val, cinfo->regbase + 0x8000); |
1da177e4c
|
2487 2488 2489 2490 |
#endif } /* The Picasso has a second register for switching the monitor bit */ |
8503df659
|
2491 |
static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val) |
1da177e4c
|
2492 2493 2494 2495 |
{ #ifdef CONFIG_ZORRO /* writing an arbitrary value to this one causes the monitor switcher */ /* to flip to Amiga display */ |
8503df659
|
2496 |
assert(cinfo->regbase != NULL); |
1da177e4c
|
2497 |
cinfo->SFR = val; |
8503df659
|
2498 |
z_writeb(val, cinfo->regbase + 0x9000); |
1da177e4c
|
2499 2500 |
#endif } |
1da177e4c
|
2501 |
/*** WClut - set CLUT entry (range: 0..63) ***/ |
8503df659
|
2502 |
static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red, |
1da177e4c
|
2503 2504 2505 2506 2507 |
unsigned char green, unsigned char blue) { unsigned int data = VGA_PEL_D; /* address write mode register is not translated.. */ |
8503df659
|
2508 |
vga_w(cinfo->regbase, VGA_PEL_IW, regnum); |
1da177e4c
|
2509 2510 |
if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || |
1b48cb563
|
2511 |
cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 || |
df3aafd57
|
2512 |
cinfo->btype == BT_SD64 || is_laguna(cinfo)) { |
1da177e4c
|
2513 2514 2515 |
/* but DAC data register IS, at least for Picasso II */ if (cinfo->btype == BT_PICASSO) data += 0xfff; |
8503df659
|
2516 2517 2518 |
vga_w(cinfo->regbase, data, red); vga_w(cinfo->regbase, data, green); vga_w(cinfo->regbase, data, blue); |
1da177e4c
|
2519 |
} else { |
8503df659
|
2520 2521 2522 |
vga_w(cinfo->regbase, data, blue); vga_w(cinfo->regbase, data, green); vga_w(cinfo->regbase, data, red); |
1da177e4c
|
2523 2524 |
} } |
1da177e4c
|
2525 2526 |
#if 0 /*** RClut - read CLUT entry (range 0..63) ***/ |
8503df659
|
2527 |
static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red, |
1da177e4c
|
2528 2529 2530 |
unsigned char *green, unsigned char *blue) { unsigned int data = VGA_PEL_D; |
8503df659
|
2531 |
vga_w(cinfo->regbase, VGA_PEL_IR, regnum); |
1da177e4c
|
2532 2533 2534 2535 2536 |
if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) { if (cinfo->btype == BT_PICASSO) data += 0xfff; |
8503df659
|
2537 2538 2539 |
*red = vga_r(cinfo->regbase, data); *green = vga_r(cinfo->regbase, data); *blue = vga_r(cinfo->regbase, data); |
1da177e4c
|
2540 |
} else { |
8503df659
|
2541 2542 2543 |
*blue = vga_r(cinfo->regbase, data); *green = vga_r(cinfo->regbase, data); *red = vga_r(cinfo->regbase, data); |
1da177e4c
|
2544 2545 2546 |
} } #endif |
1da177e4c
|
2547 2548 2549 2550 2551 2552 2553 |
/******************************************************************* cirrusfb_WaitBLT() Wait for the BitBLT engine to complete a possible earlier job *********************************************************************/ /* FIXME: use interrupts instead */ |
8503df659
|
2554 |
static void cirrusfb_WaitBLT(u8 __iomem *regbase) |
1da177e4c
|
2555 |
{ |
8503df659
|
2556 |
while (vga_rgfx(regbase, CL_GR31) & 0x08) |
48c329e90
|
2557 |
cpu_relax(); |
1da177e4c
|
2558 2559 2560 2561 2562 2563 2564 |
} /******************************************************************* cirrusfb_BitBLT() perform accelerated "scrolling" ********************************************************************/ |
8343c89c4
|
2565 2566 2567 2568 |
static void cirrusfb_set_blitter(u8 __iomem *regbase, u_short nwidth, u_short nheight, u_long nsrc, u_long ndest, u_short bltmode, u_short line_length) |
1da177e4c
|
2569 |
|
8343c89c4
|
2570 |
{ |
1da177e4c
|
2571 |
/* pitch: set to line_length */ |
8503df659
|
2572 2573 2574 2575 2576 2577 2578 2579 |
/* dest pitch low */ vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch hi */ vga_wgfx(regbase, CL_GR25, line_length >> 8); /* source pitch low */ vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch hi */ vga_wgfx(regbase, CL_GR27, line_length >> 8); |
1da177e4c
|
2580 2581 |
/* BLT width: actual number of pixels - 1 */ |
8503df659
|
2582 2583 2584 2585 |
/* BLT width low */ vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width hi */ vga_wgfx(regbase, CL_GR21, nwidth >> 8); |
1da177e4c
|
2586 2587 |
/* BLT height: actual number of lines -1 */ |
8503df659
|
2588 2589 2590 2591 |
/* BLT height low */ vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT width hi */ vga_wgfx(regbase, CL_GR23, nheight >> 8); |
1da177e4c
|
2592 2593 |
/* BLT destination */ |
8503df659
|
2594 2595 2596 2597 2598 2599 |
/* BLT dest low */ vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff)); /* BLT dest mid */ vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8)); /* BLT dest hi */ vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16)); |
1da177e4c
|
2600 2601 |
/* BLT source */ |
8503df659
|
2602 2603 2604 2605 2606 2607 |
/* BLT src low */ vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff)); /* BLT src mid */ vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8)); /* BLT src hi */ vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16)); |
1da177e4c
|
2608 2609 |
/* BLT mode */ |
8503df659
|
2610 |
vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */ |
1da177e4c
|
2611 2612 |
/* BLT ROP: SrcCopy */ |
8503df659
|
2613 |
vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */ |
1da177e4c
|
2614 2615 |
/* and finally: GO! */ |
527410ff7
|
2616 |
vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */ |
1da177e4c
|
2617 |
} |
1da177e4c
|
2618 |
/******************************************************************* |
8343c89c4
|
2619 |
cirrusfb_BitBLT() |
1da177e4c
|
2620 |
|
8343c89c4
|
2621 |
perform accelerated "scrolling" |
1da177e4c
|
2622 |
********************************************************************/ |
8343c89c4
|
2623 2624 2625 2626 2627 |
static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel, u_short curx, u_short cury, u_short destx, u_short desty, u_short width, u_short height, u_short line_length) |
1da177e4c
|
2628 |
{ |
8343c89c4
|
2629 2630 2631 2632 |
u_short nwidth = width - 1; u_short nheight = height - 1; u_long nsrc, ndest; u_char bltmode; |
1da177e4c
|
2633 |
|
8343c89c4
|
2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 |
bltmode = 0x00; /* if source adr < dest addr, do the Blt backwards */ if (cury <= desty) { if (cury == desty) { /* if src and dest are on the same line, check x */ if (curx < destx) bltmode |= 0x01; } else bltmode |= 0x01; } /* standard case: forward blitting */ nsrc = (cury * line_length) + curx; ndest = (desty * line_length) + destx; if (bltmode) { /* this means start addresses are at the end, * counting backwards */ nsrc += nheight * line_length + nwidth; ndest += nheight * line_length + nwidth; } |
1da177e4c
|
2654 |
|
8503df659
|
2655 |
cirrusfb_WaitBLT(regbase); |
1da177e4c
|
2656 |
|
8343c89c4
|
2657 2658 2659 |
cirrusfb_set_blitter(regbase, nwidth, nheight, nsrc, ndest, bltmode, line_length); } |
1da177e4c
|
2660 |
|
8343c89c4
|
2661 2662 |
/******************************************************************* cirrusfb_RectFill() |
1da177e4c
|
2663 |
|
8343c89c4
|
2664 2665 |
perform accelerated rectangle fill ********************************************************************/ |
1da177e4c
|
2666 |
|
8343c89c4
|
2667 2668 |
static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel, u_short x, u_short y, u_short width, u_short height, |
9e8480625
|
2669 2670 |
u32 fg_color, u32 bg_color, u_short line_length, u_char blitmode) |
8343c89c4
|
2671 2672 2673 |
{ u_long ndest = (y * line_length) + x; u_char op; |
1da177e4c
|
2674 |
|
8343c89c4
|
2675 |
cirrusfb_WaitBLT(regbase); |
1da177e4c
|
2676 2677 2678 |
/* This is a ColorExpand Blt, using the */ /* same color for foreground and background */ |
9e8480625
|
2679 2680 |
vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color); vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color); |
1da177e4c
|
2681 |
|
9e8480625
|
2682 |
op = 0x80; |
8343c89c4
|
2683 |
if (bits_per_pixel >= 16) { |
9e8480625
|
2684 2685 2686 |
vga_wgfx(regbase, CL_GR10, bg_color >> 8); vga_wgfx(regbase, CL_GR11, fg_color >> 8); op = 0x90; |
8343c89c4
|
2687 |
} |
7cade31ca
|
2688 |
if (bits_per_pixel >= 24) { |
9e8480625
|
2689 2690 |
vga_wgfx(regbase, CL_GR12, bg_color >> 16); vga_wgfx(regbase, CL_GR13, fg_color >> 16); |
7cade31ca
|
2691 2692 2693 |
op = 0xa0; } if (bits_per_pixel == 32) { |
9e8480625
|
2694 2695 2696 |
vga_wgfx(regbase, CL_GR14, bg_color >> 24); vga_wgfx(regbase, CL_GR15, fg_color >> 24); op = 0xb0; |
1da177e4c
|
2697 |
} |
8343c89c4
|
2698 |
cirrusfb_set_blitter(regbase, width - 1, height - 1, |
9e8480625
|
2699 |
0, ndest, op | blitmode, line_length); |
1da177e4c
|
2700 |
} |
1da177e4c
|
2701 2702 2703 2704 |
/************************************************************************** * bestclock() - determine closest possible clock lower(?) than the * desired pixel clock **************************************************************************/ |
dafa32c5a
|
2705 |
static void bestclock(long freq, int *nom, int *den, int *div) |
1da177e4c
|
2706 |
{ |
dafa32c5a
|
2707 2708 |
int n, d; long h, diff; |
1da177e4c
|
2709 |
|
8503df659
|
2710 2711 2712 |
assert(nom != NULL); assert(den != NULL); assert(div != NULL); |
1da177e4c
|
2713 2714 2715 2716 |
*nom = 0; *den = 0; *div = 0; |
1da177e4c
|
2717 2718 |
if (freq < 8000) freq = 8000; |
dafa32c5a
|
2719 |
diff = freq; |
1da177e4c
|
2720 2721 |
for (n = 32; n < 128; n++) { |
7528f5438
|
2722 |
int s = 0; |
dafa32c5a
|
2723 |
d = (14318 * n) / freq; |
1da177e4c
|
2724 |
if ((d >= 7) && (d <= 63)) { |
7528f5438
|
2725 2726 2727 2728 2729 2730 2731 |
int temp = d; if (temp > 31) { s = 1; temp >>= 1; } h = ((14318 * n) / temp) >> s; |
dafa32c5a
|
2732 2733 2734 |
h = h > freq ? h - freq : freq - h; if (h < diff) { diff = h; |
1da177e4c
|
2735 |
*nom = n; |
7528f5438
|
2736 2737 |
*den = temp; *div = s; |
1da177e4c
|
2738 2739 |
} } |
7528f5438
|
2740 |
d++; |
1da177e4c
|
2741 |
if ((d >= 7) && (d <= 63)) { |
7528f5438
|
2742 2743 2744 2745 2746 |
if (d > 31) { s = 1; d >>= 1; } h = ((14318 * n) / d) >> s; |
dafa32c5a
|
2747 2748 2749 |
h = h > freq ? h - freq : freq - h; if (h < diff) { diff = h; |
1da177e4c
|
2750 |
*nom = n; |
7528f5438
|
2751 2752 |
*den = d; *div = s; |
1da177e4c
|
2753 2754 2755 |
} } } |
1da177e4c
|
2756 |
} |
1da177e4c
|
2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 |
/* ------------------------------------------------------------------------- * * debugging functions * * ------------------------------------------------------------------------- */ #ifdef CIRRUSFB_DEBUG /** |
1da177e4c
|
2767 2768 2769 2770 2771 2772 2773 2774 2775 |
* cirrusfb_dbg_print_regs * @base: If using newmmio, the newmmio base address, otherwise %NULL * @reg_class: type of registers to read: %CRT, or %SEQ * * DESCRIPTION: * Dumps the given list of VGA CRTC registers. If @base is %NULL, * old-style I/O ports are queried for information, otherwise MMIO is * used at the given @base address to query the information. */ |
75ed3a17a
|
2776 2777 2778 |
static void cirrusfb_dbg_print_regs(struct fb_info *info, caddr_t regbase, enum cirrusfb_dbg_reg_class reg_class, ...) |
1da177e4c
|
2779 2780 2781 2782 2783 |
{ va_list list; unsigned char val = 0; unsigned reg; char *name; |
8503df659
|
2784 |
va_start(list, reg_class); |
1da177e4c
|
2785 |
|
8503df659
|
2786 |
name = va_arg(list, char *); |
1da177e4c
|
2787 |
while (name != NULL) { |
8503df659
|
2788 |
reg = va_arg(list, int); |
1da177e4c
|
2789 2790 2791 |
switch (reg_class) { case CRT: |
8503df659
|
2792 |
val = vga_rcrt(regbase, (unsigned char) reg); |
1da177e4c
|
2793 2794 |
break; case SEQ: |
8503df659
|
2795 |
val = vga_rseq(regbase, (unsigned char) reg); |
1da177e4c
|
2796 2797 2798 |
break; default: /* should never occur */ |
c930faaed
|
2799 |
assert(false); |
1da177e4c
|
2800 2801 |
break; } |
75ed3a17a
|
2802 2803 |
dev_dbg(info->device, "%8s = 0x%02X ", name, val); |
1da177e4c
|
2804 |
|
8503df659
|
2805 |
name = va_arg(list, char *); |
1da177e4c
|
2806 |
} |
8503df659
|
2807 |
va_end(list); |
1da177e4c
|
2808 |
} |
1da177e4c
|
2809 |
/** |
1da177e4c
|
2810 2811 2812 2813 2814 2815 2816 2817 |
* cirrusfb_dbg_reg_dump * @base: If using newmmio, the newmmio base address, otherwise %NULL * * DESCRIPTION: * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL, * old-style I/O ports are queried for information, otherwise MMIO is * used at the given @base address to query the information. */ |
75ed3a17a
|
2818 |
static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase) |
1da177e4c
|
2819 |
{ |
75ed3a17a
|
2820 2821 |
dev_dbg(info->device, "VGA CRTC register dump: "); |
1da177e4c
|
2822 |
|
75ed3a17a
|
2823 |
cirrusfb_dbg_print_regs(info, regbase, CRT, |
1da177e4c
|
2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 |
"CR00", 0x00, "CR01", 0x01, "CR02", 0x02, "CR03", 0x03, "CR04", 0x04, "CR05", 0x05, "CR06", 0x06, "CR07", 0x07, "CR08", 0x08, "CR09", 0x09, "CR0A", 0x0A, "CR0B", 0x0B, "CR0C", 0x0C, "CR0D", 0x0D, "CR0E", 0x0E, "CR0F", 0x0F, "CR10", 0x10, "CR11", 0x11, "CR12", 0x12, "CR13", 0x13, "CR14", 0x14, "CR15", 0x15, "CR16", 0x16, "CR17", 0x17, "CR18", 0x18, "CR22", 0x22, "CR24", 0x24, "CR26", 0x26, "CR2D", 0x2D, "CR2E", 0x2E, "CR2F", 0x2F, "CR30", 0x30, "CR31", 0x31, "CR32", 0x32, "CR33", 0x33, "CR34", 0x34, "CR35", 0x35, "CR36", 0x36, "CR37", 0x37, "CR38", 0x38, "CR39", 0x39, "CR3A", 0x3A, "CR3B", 0x3B, "CR3C", 0x3C, "CR3D", 0x3D, "CR3E", 0x3E, "CR3F", 0x3F, NULL); |
75ed3a17a
|
2872 2873 |
dev_dbg(info->device, " "); |
1da177e4c
|
2874 |
|
75ed3a17a
|
2875 2876 |
dev_dbg(info->device, "VGA SEQ register dump: "); |
1da177e4c
|
2877 |
|
75ed3a17a
|
2878 |
cirrusfb_dbg_print_regs(info, regbase, SEQ, |
1da177e4c
|
2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 |
"SR00", 0x00, "SR01", 0x01, "SR02", 0x02, "SR03", 0x03, "SR04", 0x04, "SR08", 0x08, "SR09", 0x09, "SR0A", 0x0A, "SR0B", 0x0B, "SR0D", 0x0D, "SR10", 0x10, "SR11", 0x11, "SR12", 0x12, "SR13", 0x13, "SR14", 0x14, "SR15", 0x15, "SR16", 0x16, "SR17", 0x17, "SR18", 0x18, "SR19", 0x19, "SR1A", 0x1A, "SR1B", 0x1B, "SR1C", 0x1C, "SR1D", 0x1D, "SR1E", 0x1E, "SR1F", 0x1F, NULL); |
75ed3a17a
|
2906 2907 |
dev_dbg(info->device, " "); |
1da177e4c
|
2908 2909 2910 |
} #endif /* CIRRUSFB_DEBUG */ |