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drivers/edac/mpc85xx_edac.c
32.3 KB
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/* * Freescale MPC85xx Memory Controller kenel module * * Author: Dave Jiang <djiang@mvista.com> * * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. * */ #include <linux/module.h> #include <linux/init.h> |
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#include <linux/interrupt.h> #include <linux/ctype.h> #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/edac.h> |
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#include <linux/smp.h> |
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#include <linux/gfp.h> |
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#include <linux/of_platform.h> #include <linux/of_device.h> |
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#include "edac_module.h" #include "edac_core.h" #include "mpc85xx_edac.h" static int edac_dev_idx; |
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#ifdef CONFIG_PCI |
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static int edac_pci_idx; |
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#endif |
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static int edac_mc_idx; static u32 orig_ddr_err_disable; static u32 orig_ddr_err_sbe; /* * PCI Err defines */ #ifdef CONFIG_PCI static u32 orig_pci_err_cap_dr; static u32 orig_pci_err_en; #endif static u32 orig_l2_err_disable; |
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#ifdef CONFIG_FSL_SOC_BOOKE |
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static u32 orig_hid1[2]; |
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#endif |
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/************************ MC SYSFS parts ***********************************/ static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, char *data) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI)); } static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, char *data) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO)); } static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); } static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, const char *data, size_t count) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; if (isdigit(*data)) { out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, simple_strtoul(data, NULL, 0)); return count; } return 0; } static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, const char *data, size_t count) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; if (isdigit(*data)) { out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, simple_strtoul(data, NULL, 0)); return count; } return 0; } static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, const char *data, size_t count) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; if (isdigit(*data)) { out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, simple_strtoul(data, NULL, 0)); return count; } return 0; } static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { { .attr = { .name = "inject_data_hi", .mode = (S_IRUGO | S_IWUSR) }, .show = mpc85xx_mc_inject_data_hi_show, .store = mpc85xx_mc_inject_data_hi_store}, { .attr = { .name = "inject_data_lo", .mode = (S_IRUGO | S_IWUSR) }, .show = mpc85xx_mc_inject_data_lo_show, .store = mpc85xx_mc_inject_data_lo_store}, { .attr = { .name = "inject_ctrl", .mode = (S_IRUGO | S_IWUSR) }, .show = mpc85xx_mc_inject_ctrl_show, .store = mpc85xx_mc_inject_ctrl_store}, /* End of list */ { .attr = {.name = NULL} } }; static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) { mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; } /**************************** PCI Err device ***************************/ #ifdef CONFIG_PCI static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) { struct mpc85xx_pci_pdata *pdata = pci->pvt_info; u32 err_detect; err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); /* master aborts can happen during PCI config cycles */ if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); return; } printk(KERN_ERR "PCI error(s) detected "); printk(KERN_ERR "PCI/X ERR_DR register: %#08x ", err_detect); printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x ", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x ", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x ", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); printk(KERN_ERR "PCI/X ERR_DL register: %#08x ", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); printk(KERN_ERR "PCI/X ERR_DH register: %#08x ", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); if (err_detect & PCI_EDE_PERR_MASK) edac_pci_handle_pe(pci, pci->ctl_name); if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) edac_pci_handle_npe(pci, pci->ctl_name); } static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) { struct edac_pci_ctl_info *pci = dev_id; struct mpc85xx_pci_pdata *pdata = pci->pvt_info; u32 err_detect; err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); if (!err_detect) return IRQ_NONE; mpc85xx_pci_check(pci); return IRQ_HANDLED; } |
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static int __devinit mpc85xx_pci_err_probe(struct platform_device *op) |
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{ struct edac_pci_ctl_info *pci; struct mpc85xx_pci_pdata *pdata; |
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struct resource r; |
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int res = 0; |
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if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
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return -ENOMEM; pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); if (!pci) return -ENOMEM; pdata = pci->pvt_info; pdata->name = "mpc85xx_pci_err"; pdata->irq = NO_IRQ; |
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dev_set_drvdata(&op->dev, pci); pci->dev = &op->dev; |
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pci->mod_name = EDAC_MOD_STR; pci->ctl_name = pdata->name; |
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pci->dev_name = dev_name(&op->dev); |
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if (edac_op_state == EDAC_OPSTATE_POLL) pci->edac_check = mpc85xx_pci_check; pdata->edac_idx = edac_pci_idx++; |
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res = of_address_to_resource(op->dev.of_node, 0, &r); |
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if (res) { |
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printk(KERN_ERR "%s: Unable to get resource for " "PCI err regs ", __func__); goto err; } |
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/* we only need the error registers */ r.start += 0xe00; |
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if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), pdata->name)) { |
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printk(KERN_ERR "%s: Error while requesting mem region ", __func__); res = -EBUSY; goto err; } |
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pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
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if (!pdata->pci_vbase) { printk(KERN_ERR "%s: Unable to setup PCI err regs ", __func__); res = -ENOMEM; goto err; } orig_pci_err_cap_dr = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); /* PCI master abort is expected during config cycles */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); /* disable master abort reporting */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { debugf3("%s(): failed edac_pci_add_device() ", __func__); goto err; } if (edac_op_state == EDAC_OPSTATE_INT) { |
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pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
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res = devm_request_irq(&op->dev, pdata->irq, |
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mpc85xx_pci_isr, IRQF_DISABLED, "[EDAC] PCI err", pci); if (res < 0) { printk(KERN_ERR "%s: Unable to requiest irq %d for " "MPC85xx PCI err ", __func__, pdata->irq); |
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irq_dispose_mapping(pdata->irq); |
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res = -ENODEV; goto err2; } printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err ", pdata->irq); } |
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devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
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debugf3("%s(): success ", __func__); printk(KERN_INFO EDAC_MOD_STR " PCI err registered "); return 0; err2: |
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edac_pci_del_device(&op->dev); |
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err: edac_pci_free_ctl_info(pci); |
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devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
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return res; } |
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static int mpc85xx_pci_err_remove(struct platform_device *op) |
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{ |
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struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); |
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struct mpc85xx_pci_pdata *pdata = pci->pvt_info; debugf0("%s() ", __func__); out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, orig_pci_err_cap_dr); out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); edac_pci_del_device(pci->dev); if (edac_op_state == EDAC_OPSTATE_INT) irq_dispose_mapping(pdata->irq); edac_pci_free_ctl_info(pci); return 0; } |
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static struct of_device_id mpc85xx_pci_err_of_match[] = { { .compatible = "fsl,mpc8540-pcix", }, { .compatible = "fsl,mpc8540-pci", }, {}, }; |
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MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match); |
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static struct platform_driver mpc85xx_pci_err_driver = { |
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.probe = mpc85xx_pci_err_probe, .remove = __devexit_p(mpc85xx_pci_err_remove), .driver = { |
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.name = "mpc85xx_pci_err", .owner = THIS_MODULE, .of_match_table = mpc85xx_pci_err_of_match, }, |
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}; #endif /* CONFIG_PCI */ /**************************** L2 Err device ***************************/ /************************ L2 SYSFS parts ***********************************/ static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info *edac_dev, char *data) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); } static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info *edac_dev, char *data) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); } static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info *edac_dev, char *data) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); } static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info *edac_dev, const char *data, size_t count) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; if (isdigit(*data)) { out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, simple_strtoul(data, NULL, 0)); return count; } return 0; } static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info *edac_dev, const char *data, size_t count) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; if (isdigit(*data)) { out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, simple_strtoul(data, NULL, 0)); return count; } return 0; } static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info *edac_dev, const char *data, size_t count) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; if (isdigit(*data)) { out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, simple_strtoul(data, NULL, 0)); return count; } return 0; } static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { { .attr = { .name = "inject_data_hi", .mode = (S_IRUGO | S_IWUSR) }, .show = mpc85xx_l2_inject_data_hi_show, .store = mpc85xx_l2_inject_data_hi_store}, { .attr = { .name = "inject_data_lo", .mode = (S_IRUGO | S_IWUSR) }, .show = mpc85xx_l2_inject_data_lo_show, .store = mpc85xx_l2_inject_data_lo_store}, { .attr = { .name = "inject_ctrl", .mode = (S_IRUGO | S_IWUSR) }, .show = mpc85xx_l2_inject_ctrl_show, .store = mpc85xx_l2_inject_ctrl_store}, /* End of list */ { .attr = {.name = NULL} } }; static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info *edac_dev) { edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; } /***************************** L2 ops ***********************************/ static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) { struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; u32 err_detect; err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); if (!(err_detect & L2_EDE_MASK)) return; printk(KERN_ERR "ECC Error in CPU L2 cache "); printk(KERN_ERR "L2 Error Detect Register: 0x%08x ", err_detect); printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x ", in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x ", in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x ", in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x ", in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x ", in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); /* clear error detect register */ out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); if (err_detect & L2_EDE_CE_MASK) edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); if (err_detect & L2_EDE_UE_MASK) edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); } static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) { struct edac_device_ctl_info *edac_dev = dev_id; struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; u32 err_detect; err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); if (!(err_detect & L2_EDE_MASK)) return IRQ_NONE; mpc85xx_l2_check(edac_dev); return IRQ_HANDLED; } |
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static int __devinit mpc85xx_l2_err_probe(struct platform_device *op) |
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{ struct edac_device_ctl_info *edac_dev; struct mpc85xx_l2_pdata *pdata; struct resource r; int res; if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) return -ENOMEM; edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), "cpu", 1, "L", 1, 2, NULL, 0, edac_dev_idx); if (!edac_dev) { devres_release_group(&op->dev, mpc85xx_l2_err_probe); return -ENOMEM; } pdata = edac_dev->pvt_info; pdata->name = "mpc85xx_l2_err"; pdata->irq = NO_IRQ; edac_dev->dev = &op->dev; dev_set_drvdata(edac_dev->dev, edac_dev); edac_dev->ctl_name = pdata->name; edac_dev->dev_name = pdata->name; |
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res = of_address_to_resource(op->dev.of_node, 0, &r); |
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if (res) { printk(KERN_ERR "%s: Unable to get resource for " "L2 err regs ", __func__); goto err; } /* we only need the error registers */ r.start += 0xe00; |
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if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), pdata->name)) { |
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printk(KERN_ERR "%s: Error while requesting mem region ", __func__); res = -EBUSY; goto err; } |
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pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
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if (!pdata->l2_vbase) { printk(KERN_ERR "%s: Unable to setup L2 err regs ", __func__); res = -ENOMEM; goto err; } out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); /* clear the err_dis */ out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); edac_dev->mod_name = EDAC_MOD_STR; if (edac_op_state == EDAC_OPSTATE_POLL) edac_dev->edac_check = mpc85xx_l2_check; mpc85xx_set_l2_sysfs_attributes(edac_dev); pdata->edac_idx = edac_dev_idx++; if (edac_device_add_device(edac_dev) > 0) { debugf3("%s(): failed edac_device_add_device() ", __func__); goto err; } if (edac_op_state == EDAC_OPSTATE_INT) { |
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pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
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res = devm_request_irq(&op->dev, pdata->irq, mpc85xx_l2_isr, IRQF_DISABLED, "[EDAC] L2 err", edac_dev); if (res < 0) { printk(KERN_ERR "%s: Unable to requiest irq %d for " "MPC85xx L2 err ", __func__, pdata->irq); irq_dispose_mapping(pdata->irq); res = -ENODEV; goto err2; } printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err ", pdata->irq); edac_dev->op_state = OP_RUNNING_INTERRUPT; out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); } devres_remove_group(&op->dev, mpc85xx_l2_err_probe); debugf3("%s(): success ", __func__); printk(KERN_INFO EDAC_MOD_STR " L2 err registered "); return 0; err2: edac_device_del_device(&op->dev); err: devres_release_group(&op->dev, mpc85xx_l2_err_probe); edac_device_free_ctl_info(edac_dev); return res; } |
2dc115813 of/device: Replac... |
631 |
static int mpc85xx_l2_err_remove(struct platform_device *op) |
a9a753d53 drivers-edac: add... |
632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 |
{ struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; debugf0("%s() ", __func__); if (edac_op_state == EDAC_OPSTATE_INT) { out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); irq_dispose_mapping(pdata->irq); } out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); edac_device_del_device(&op->dev); edac_device_free_ctl_info(edac_dev); return 0; } static struct of_device_id mpc85xx_l2_err_of_match[] = { |
29d6cf26a edac: fix mpc85xx... |
651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 |
/* deprecate the fsl,85.. forms in the future, 2.6.30? */ { .compatible = "fsl,8540-l2-cache-controller", }, { .compatible = "fsl,8541-l2-cache-controller", }, { .compatible = "fsl,8544-l2-cache-controller", }, { .compatible = "fsl,8548-l2-cache-controller", }, { .compatible = "fsl,8555-l2-cache-controller", }, { .compatible = "fsl,8568-l2-cache-controller", }, { .compatible = "fsl,mpc8536-l2-cache-controller", }, { .compatible = "fsl,mpc8540-l2-cache-controller", }, { .compatible = "fsl,mpc8541-l2-cache-controller", }, { .compatible = "fsl,mpc8544-l2-cache-controller", }, { .compatible = "fsl,mpc8548-l2-cache-controller", }, { .compatible = "fsl,mpc8555-l2-cache-controller", }, { .compatible = "fsl,mpc8560-l2-cache-controller", }, { .compatible = "fsl,mpc8568-l2-cache-controller", }, |
cd1542c81 edac: mpc85xx: ad... |
666 |
{ .compatible = "fsl,mpc8569-l2-cache-controller", }, |
29d6cf26a edac: fix mpc85xx... |
667 |
{ .compatible = "fsl,mpc8572-l2-cache-controller", }, |
cd1542c81 edac: mpc85xx: ad... |
668 669 |
{ .compatible = "fsl,p1020-l2-cache-controller", }, { .compatible = "fsl,p1021-l2-cache-controller", }, |
a014554e6 edac: mpc85xx add... |
670 |
{ .compatible = "fsl,p2020-l2-cache-controller", }, |
a9a753d53 drivers-edac: add... |
671 672 |
{}, }; |
952e1c663 edac: mpc85xx: fi... |
673 |
MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); |
a9a753d53 drivers-edac: add... |
674 |
|
000061245 dt/powerpc: Elimi... |
675 |
static struct platform_driver mpc85xx_l2_err_driver = { |
a9a753d53 drivers-edac: add... |
676 677 678 |
.probe = mpc85xx_l2_err_probe, .remove = mpc85xx_l2_err_remove, .driver = { |
4018294b5 of: Remove duplic... |
679 680 681 682 |
.name = "mpc85xx_l2_err", .owner = THIS_MODULE, .of_match_table = mpc85xx_l2_err_of_match, }, |
a9a753d53 drivers-edac: add... |
683 684 685 |
}; /**************************** MC Err device ***************************/ |
dcca7c3d0 edac: mpc85xx imp... |
686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 |
/* * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the * MPC8572 User's Manual. Each line represents a syndrome bit column as a * 64-bit value, but split into an upper and lower 32-bit chunk. The labels * below correspond to Freescale's manuals. */ static unsigned int ecc_table[16] = { /* MSB LSB */ /* [0:31] [32:63] */ 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ 0x00ff00ff, 0x00fff0ff, 0x0f0f0f0f, 0x0f0fff00, 0x11113333, 0x7777000f, 0x22224444, 0x8888222f, 0x44448888, 0xffff4441, 0x8888ffff, 0x11118882, 0xffff1111, 0x22221114, /* Syndrome bit 0 */ }; /* * Calculate the correct ECC value for a 64-bit value specified by high:low */ static u8 calculate_ecc(u32 high, u32 low) { u32 mask_low; u32 mask_high; int bit_cnt; u8 ecc = 0; int i; int j; for (i = 0; i < 8; i++) { mask_high = ecc_table[i * 2]; mask_low = ecc_table[i * 2 + 1]; bit_cnt = 0; for (j = 0; j < 32; j++) { if ((mask_high >> j) & 1) bit_cnt ^= (high >> j) & 1; if ((mask_low >> j) & 1) bit_cnt ^= (low >> j) & 1; } ecc |= bit_cnt << i; } return ecc; } /* * Create the syndrome code which is generated if the data line specified by * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 * User's Manual and 9-61 in the MPC8572 User's Manual. */ static u8 syndrome_from_bit(unsigned int bit) { int i; u8 syndrome = 0; /* * Cycle through the upper or lower 32-bit portion of each value in * ecc_table depending on if 'bit' is in the upper or lower half of * 64-bit data. */ for (i = bit < 32; i < 16; i += 2) syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); return syndrome; } /* * Decode data and ecc syndrome to determine what went wrong * Note: This can only decode single-bit errors */ static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, int *bad_data_bit, int *bad_ecc_bit) { int i; u8 syndrome; *bad_data_bit = -1; *bad_ecc_bit = -1; /* * Calculate the ECC of the captured data and XOR it with the captured * ECC to find an ECC syndrome value we can search for */ syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; /* Check if a data line is stuck... */ for (i = 0; i < 64; i++) { if (syndrome == syndrome_from_bit(i)) { *bad_data_bit = i; return; } } /* If data is correct, check ECC bits for errors... */ for (i = 0; i < 8; i++) { if ((syndrome >> i) & 0x1) { *bad_ecc_bit = i; return; } } } |
a9a753d53 drivers-edac: add... |
790 791 792 793 |
static void mpc85xx_mc_check(struct mem_ctl_info *mci) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; struct csrow_info *csrow; |
21768639b edac: mpc85xx mas... |
794 |
u32 bus_width; |
a9a753d53 drivers-edac: add... |
795 796 797 798 799 |
u32 err_detect; u32 syndrome; u32 err_addr; u32 pfn; int row_index; |
dcca7c3d0 edac: mpc85xx imp... |
800 801 802 803 |
u32 cap_high; u32 cap_low; int bad_data_bit; int bad_ecc_bit; |
a9a753d53 drivers-edac: add... |
804 805 |
err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); |
55e5750b3 edac: ppc mpc85xx... |
806 |
if (!err_detect) |
a9a753d53 drivers-edac: add... |
807 808 809 810 811 812 813 814 815 816 817 818 819 |
return; mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x ", err_detect); /* no more processing if not ECC bit errors */ if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); return; } syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); |
21768639b edac: mpc85xx mas... |
820 821 822 823 824 825 826 827 |
/* Mask off appropriate bits of syndrome based on bus width */ bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & DSC_DBW_MASK) ? 32 : 64; if (bus_width == 64) syndrome &= 0xff; else syndrome &= 0xffff; |
a9a753d53 drivers-edac: add... |
828 829 830 831 832 833 834 835 |
err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); pfn = err_addr >> PAGE_SHIFT; for (row_index = 0; row_index < mci->nr_csrows; row_index++) { csrow = &mci->csrows[row_index]; if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) break; } |
dcca7c3d0 edac: mpc85xx imp... |
836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 |
cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); /* * Analyze single-bit errors on 64-bit wide buses * TODO: Add support for 32-bit wide buses */ if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { sbe_ecc_decode(cap_high, cap_low, syndrome, &bad_data_bit, &bad_ecc_bit); if (bad_data_bit != -1) mpc85xx_mc_printk(mci, KERN_ERR, "Faulty Data bit: %d ", bad_data_bit); if (bad_ecc_bit != -1) mpc85xx_mc_printk(mci, KERN_ERR, "Faulty ECC bit: %d ", bad_ecc_bit); mpc85xx_mc_printk(mci, KERN_ERR, "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x ", cap_high ^ (1 << (bad_data_bit - 32)), cap_low ^ (1 << bad_data_bit), syndrome ^ (1 << bad_ecc_bit)); } mpc85xx_mc_printk(mci, KERN_ERR, "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x ", cap_high, cap_low, syndrome); mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x ", err_addr); |
a9a753d53 drivers-edac: add... |
870 871 872 873 874 875 876 877 878 |
mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x ", pfn); /* we are out of range */ if (row_index == mci->nr_csrows) mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range! "); if (err_detect & DDR_EDE_SBE) |
444d29212 drivers/edac/mpc8... |
879 |
edac_mc_handle_ce(mci, pfn, err_addr & ~PAGE_MASK, |
a9a753d53 drivers-edac: add... |
880 881 882 |
syndrome, row_index, 0, mci->ctl_name); if (err_detect & DDR_EDE_MBE) |
444d29212 drivers/edac/mpc8... |
883 |
edac_mc_handle_ue(mci, pfn, err_addr & ~PAGE_MASK, |
a9a753d53 drivers-edac: add... |
884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 |
row_index, mci->ctl_name); out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); } static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) { struct mem_ctl_info *mci = dev_id; struct mpc85xx_mc_pdata *pdata = mci->pvt_info; u32 err_detect; err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); if (!err_detect) return IRQ_NONE; mpc85xx_mc_check(mci); return IRQ_HANDLED; } static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) { struct mpc85xx_mc_pdata *pdata = mci->pvt_info; struct csrow_info *csrow; u32 sdram_ctl; u32 sdtype; enum mem_type mtype; u32 cs_bnds; int index; sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); sdtype = sdram_ctl & DSC_SDTYPE_MASK; if (sdram_ctl & DSC_RD_EN) { switch (sdtype) { case DSC_SDTYPE_DDR: mtype = MEM_RDDR; break; case DSC_SDTYPE_DDR2: mtype = MEM_RDDR2; break; |
b1cfebc92 edac: add DDR3 me... |
925 926 927 |
case DSC_SDTYPE_DDR3: mtype = MEM_RDDR3; break; |
a9a753d53 drivers-edac: add... |
928 929 930 931 932 933 934 935 936 937 938 939 |
default: mtype = MEM_UNKNOWN; break; } } else { switch (sdtype) { case DSC_SDTYPE_DDR: mtype = MEM_DDR; break; case DSC_SDTYPE_DDR2: mtype = MEM_DDR2; break; |
b1cfebc92 edac: add DDR3 me... |
940 941 942 |
case DSC_SDTYPE_DDR3: mtype = MEM_DDR3; break; |
a9a753d53 drivers-edac: add... |
943 944 945 946 947 948 949 950 951 952 953 954 955 |
default: mtype = MEM_UNKNOWN; break; } } for (index = 0; index < mci->nr_csrows; index++) { u32 start; u32 end; csrow = &mci->csrows[index]; cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + (index * MPC85XX_MC_CS_BNDS_OFS)); |
b48462517 edac: mpc85xx add... |
956 957 958 |
start = (cs_bnds & 0xffff0000) >> 16; end = (cs_bnds & 0x0000ffff); |
a9a753d53 drivers-edac: add... |
959 960 961 |
if (start == end) continue; /* not populated */ |
b48462517 edac: mpc85xx add... |
962 963 964 |
start <<= (24 - PAGE_SHIFT); end <<= (24 - PAGE_SHIFT); end |= (1 << (24 - PAGE_SHIFT)) - 1; |
cff9279e4 edac: mpc85xx fix... |
965 966 |
csrow->first_page = start; csrow->last_page = end; |
b48462517 edac: mpc85xx add... |
967 |
csrow->nr_pages = end + 1 - start; |
a9a753d53 drivers-edac: add... |
968 969 970 971 972 973 974 975 |
csrow->grain = 8; csrow->mtype = mtype; csrow->dtype = DEV_UNKNOWN; if (sdram_ctl & DSC_X32_EN) csrow->dtype = DEV_X32; csrow->edac_mode = EDAC_SECDED; } } |
000061245 dt/powerpc: Elimi... |
976 |
static int __devinit mpc85xx_mc_err_probe(struct platform_device *op) |
a9a753d53 drivers-edac: add... |
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 |
{ struct mem_ctl_info *mci; struct mpc85xx_mc_pdata *pdata; struct resource r; u32 sdram_ctl; int res; if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) return -ENOMEM; mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); if (!mci) { devres_release_group(&op->dev, mpc85xx_mc_err_probe); return -ENOMEM; } pdata = mci->pvt_info; pdata->name = "mpc85xx_mc_err"; pdata->irq = NO_IRQ; mci->dev = &op->dev; pdata->edac_idx = edac_mc_idx++; dev_set_drvdata(mci->dev, mci); mci->ctl_name = pdata->name; mci->dev_name = pdata->name; |
a26f95fed of/edac: fix buil... |
1001 |
res = of_address_to_resource(op->dev.of_node, 0, &r); |
a9a753d53 drivers-edac: add... |
1002 1003 1004 1005 1006 1007 |
if (res) { printk(KERN_ERR "%s: Unable to get resource for MC err regs ", __func__); goto err; } |
28f65c11f treewide: Convert... |
1008 1009 |
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), pdata->name)) { |
a9a753d53 drivers-edac: add... |
1010 1011 1012 1013 1014 1015 |
printk(KERN_ERR "%s: Error while requesting mem region ", __func__); res = -EBUSY; goto err; } |
28f65c11f treewide: Convert... |
1016 |
pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d53 drivers-edac: add... |
1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 |
if (!pdata->mc_vbase) { printk(KERN_ERR "%s: Unable to setup MC err regs ", __func__); res = -ENOMEM; goto err; } sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); if (!(sdram_ctl & DSC_ECC_EN)) { /* no ECC */ printk(KERN_WARNING "%s: No ECC DIMMs discovered ", __func__); res = -ENODEV; goto err; } debugf3("%s(): init mci ", __func__); mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | MEM_FLAG_DDR | MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; mci->edac_cap = EDAC_FLAG_SECDED; mci->mod_name = EDAC_MOD_STR; mci->mod_ver = MPC85XX_REVISION; if (edac_op_state == EDAC_OPSTATE_POLL) mci->edac_check = mpc85xx_mc_check; mci->ctl_page_to_phys = NULL; mci->scrub_mode = SCRUB_SW_SRC; mpc85xx_set_mc_sysfs_attributes(mci); mpc85xx_init_csrows(mci); |
a9a753d53 drivers-edac: add... |
1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 |
/* store the original error disable bits */ orig_ddr_err_disable = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); /* clear all error bits */ out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); if (edac_mc_add_mc(mci)) { debugf3("%s(): failed edac_mc_add_mc() ", __func__); goto err; } if (edac_op_state == EDAC_OPSTATE_INT) { out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, DDR_EIE_MBEE | DDR_EIE_SBEE); /* store the original error management threshold */ orig_ddr_err_sbe = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE) & 0xff0000; /* set threshold to 1 error per interrupt */ out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); /* register interrupts */ |
a26f95fed of/edac: fix buil... |
1078 |
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
a9a753d53 drivers-edac: add... |
1079 |
res = devm_request_irq(&op->dev, pdata->irq, |
60be75515 edac mpc85xx: add... |
1080 1081 |
mpc85xx_mc_isr, IRQF_DISABLED | IRQF_SHARED, |
a9a753d53 drivers-edac: add... |
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 |
"[EDAC] MC err", mci); if (res < 0) { printk(KERN_ERR "%s: Unable to request irq %d for " "MPC85xx DRAM ERR ", __func__, pdata->irq); irq_dispose_mapping(pdata->irq); res = -ENODEV; goto err2; } printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC ", pdata->irq); } devres_remove_group(&op->dev, mpc85xx_mc_err_probe); debugf3("%s(): success ", __func__); printk(KERN_INFO EDAC_MOD_STR " MC err registered "); return 0; err2: edac_mc_del_mc(&op->dev); err: devres_release_group(&op->dev, mpc85xx_mc_err_probe); edac_mc_free(mci); return res; } |
2dc115813 of/device: Replac... |
1112 |
static int mpc85xx_mc_err_remove(struct platform_device *op) |
a9a753d53 drivers-edac: add... |
1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 |
{ struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; debugf0("%s() ", __func__); if (edac_op_state == EDAC_OPSTATE_INT) { out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); irq_dispose_mapping(pdata->irq); } out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, orig_ddr_err_disable); out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); edac_mc_del_mc(&op->dev); edac_mc_free(mci); return 0; } static struct of_device_id mpc85xx_mc_err_of_match[] = { |
29d6cf26a edac: fix mpc85xx... |
1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 |
/* deprecate the fsl,85.. forms in the future, 2.6.30? */ { .compatible = "fsl,8540-memory-controller", }, { .compatible = "fsl,8541-memory-controller", }, { .compatible = "fsl,8544-memory-controller", }, { .compatible = "fsl,8548-memory-controller", }, { .compatible = "fsl,8555-memory-controller", }, { .compatible = "fsl,8568-memory-controller", }, { .compatible = "fsl,mpc8536-memory-controller", }, { .compatible = "fsl,mpc8540-memory-controller", }, { .compatible = "fsl,mpc8541-memory-controller", }, { .compatible = "fsl,mpc8544-memory-controller", }, { .compatible = "fsl,mpc8548-memory-controller", }, { .compatible = "fsl,mpc8555-memory-controller", }, { .compatible = "fsl,mpc8560-memory-controller", }, { .compatible = "fsl,mpc8568-memory-controller", }, |
5528e229f edac: mpc85xx: ad... |
1150 |
{ .compatible = "fsl,mpc8569-memory-controller", }, |
29d6cf26a edac: fix mpc85xx... |
1151 |
{ .compatible = "fsl,mpc8572-memory-controller", }, |
b48462517 edac: mpc85xx add... |
1152 |
{ .compatible = "fsl,mpc8349-memory-controller", }, |
cd1542c81 edac: mpc85xx: ad... |
1153 1154 |
{ .compatible = "fsl,p1020-memory-controller", }, { .compatible = "fsl,p1021-memory-controller", }, |
a014554e6 edac: mpc85xx add... |
1155 |
{ .compatible = "fsl,p2020-memory-controller", }, |
86f9a4330 drivers/edac/mpc8... |
1156 |
{ .compatible = "fsl,qoriq-memory-controller", }, |
a9a753d53 drivers-edac: add... |
1157 1158 |
{}, }; |
952e1c663 edac: mpc85xx: fi... |
1159 |
MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); |
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|
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static struct platform_driver mpc85xx_mc_err_driver = { |
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.probe = mpc85xx_mc_err_probe, .remove = mpc85xx_mc_err_remove, .driver = { |
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.name = "mpc85xx_mc_err", .owner = THIS_MODULE, .of_match_table = mpc85xx_mc_err_of_match, }, |
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1169 |
}; |
bd1688dcd edac: add wissing... |
1170 |
#ifdef CONFIG_FSL_SOC_BOOKE |
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static void __init mpc85xx_mc_clear_rfxe(void *data) { orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); |
a94d7b350 edac/mpc85xx: Lim... |
1174 |
mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); |
60be75515 edac mpc85xx: add... |
1175 |
} |
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#endif |
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1177 |
|
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static int __init mpc85xx_mc_init(void) { int res = 0; |
a94d7b350 edac/mpc85xx: Lim... |
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u32 pvr = 0; |
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printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " "(C) 2006 Montavista Software "); /* make sure error reporting method is sane */ switch (edac_op_state) { case EDAC_OPSTATE_POLL: case EDAC_OPSTATE_INT: break; default: edac_op_state = EDAC_OPSTATE_INT; break; } |
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res = platform_driver_register(&mpc85xx_mc_err_driver); |
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if (res) printk(KERN_WARNING EDAC_MOD_STR "MC fails to register "); |
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res = platform_driver_register(&mpc85xx_l2_err_driver); |
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if (res) printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register "); #ifdef CONFIG_PCI |
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1206 |
res = platform_driver_register(&mpc85xx_pci_err_driver); |
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if (res) printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register "); #endif |
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1211 |
#ifdef CONFIG_FSL_SOC_BOOKE |
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1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 |
pvr = mfspr(SPRN_PVR); if ((PVR_VER(pvr) == PVR_VER_E500V1) || (PVR_VER(pvr) == PVR_VER_E500V2)) { /* * need to clear HID1[RFXE] to disable machine check int * so we can catch it */ if (edac_op_state == EDAC_OPSTATE_INT) on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); } |
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1223 |
#endif |
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1224 1225 1226 1227 1228 |
return 0; } module_init(mpc85xx_mc_init); |
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1229 |
#ifdef CONFIG_FSL_SOC_BOOKE |
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static void __exit mpc85xx_mc_restore_hid1(void *data) { mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); } |
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1234 |
#endif |
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|
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static void __exit mpc85xx_mc_exit(void) { |
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1238 |
#ifdef CONFIG_FSL_SOC_BOOKE |
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1239 1240 1241 1242 1243 1244 |
u32 pvr = mfspr(SPRN_PVR); if ((PVR_VER(pvr) == PVR_VER_E500V1) || (PVR_VER(pvr) == PVR_VER_E500V2)) { on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); } |
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1245 |
#endif |
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#ifdef CONFIG_PCI |
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1247 |
platform_driver_unregister(&mpc85xx_pci_err_driver); |
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1248 |
#endif |
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platform_driver_unregister(&mpc85xx_l2_err_driver); platform_driver_unregister(&mpc85xx_mc_err_driver); |
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} module_exit(mpc85xx_mc_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Montavista Software, Inc."); module_param(edac_op_state, int, 0444); MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |