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drivers/regulator/palmas-regulator.c
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// SPDX-License-Identifier: GPL-2.0-or-later |
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/* * Driver for Regulator part of Palmas PMIC Chips * |
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* Copyright 2011-2013 Texas Instruments Inc. |
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* * Author: Graeme Gregory <gg@slimlogic.co.uk> |
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* Author: Ian Lartey <ian@slimlogic.co.uk> |
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*/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/init.h> #include <linux/err.h> #include <linux/platform_device.h> #include <linux/regulator/driver.h> #include <linux/regulator/machine.h> #include <linux/slab.h> #include <linux/regmap.h> #include <linux/mfd/palmas.h> |
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#include <linux/of.h> #include <linux/of_platform.h> #include <linux/regulator/of_regulator.h> |
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static const struct regulator_linear_range smps_low_ranges[] = { |
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REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), |
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REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000), REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0), }; static const struct regulator_linear_range smps_high_ranges[] = { |
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REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), |
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REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0), REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000), REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), }; |
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static struct palmas_regs_info palmas_generic_regs_info[] = { |
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{ .name = "SMPS12", |
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.sname = "smps1-in", |
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.vsel_addr = PALMAS_SMPS12_VOLTAGE, .ctrl_addr = PALMAS_SMPS12_CTRL, .tstep_addr = PALMAS_SMPS12_TSTEP, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12, |
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}, { .name = "SMPS123", |
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.sname = "smps1-in", |
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.vsel_addr = PALMAS_SMPS12_VOLTAGE, .ctrl_addr = PALMAS_SMPS12_CTRL, .tstep_addr = PALMAS_SMPS12_TSTEP, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12, |
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}, { .name = "SMPS3", |
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.sname = "smps3-in", |
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.vsel_addr = PALMAS_SMPS3_VOLTAGE, .ctrl_addr = PALMAS_SMPS3_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3, |
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}, { .name = "SMPS45", |
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.sname = "smps4-in", |
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.vsel_addr = PALMAS_SMPS45_VOLTAGE, .ctrl_addr = PALMAS_SMPS45_CTRL, .tstep_addr = PALMAS_SMPS45_TSTEP, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45, |
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}, { .name = "SMPS457", |
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.sname = "smps4-in", |
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.vsel_addr = PALMAS_SMPS45_VOLTAGE, .ctrl_addr = PALMAS_SMPS45_CTRL, .tstep_addr = PALMAS_SMPS45_TSTEP, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45, |
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}, { .name = "SMPS6", |
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.sname = "smps6-in", |
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.vsel_addr = PALMAS_SMPS6_VOLTAGE, .ctrl_addr = PALMAS_SMPS6_CTRL, .tstep_addr = PALMAS_SMPS6_TSTEP, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6, |
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}, { .name = "SMPS7", |
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.sname = "smps7-in", |
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.vsel_addr = PALMAS_SMPS7_VOLTAGE, .ctrl_addr = PALMAS_SMPS7_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7, |
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}, { .name = "SMPS8", |
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.sname = "smps8-in", |
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.vsel_addr = PALMAS_SMPS8_VOLTAGE, .ctrl_addr = PALMAS_SMPS8_CTRL, .tstep_addr = PALMAS_SMPS8_TSTEP, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8, |
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}, { .name = "SMPS9", |
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.sname = "smps9-in", |
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.vsel_addr = PALMAS_SMPS9_VOLTAGE, .ctrl_addr = PALMAS_SMPS9_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9, |
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}, { |
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.name = "SMPS10_OUT2", |
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.sname = "smps10-in", |
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.ctrl_addr = PALMAS_SMPS10_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10, |
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}, { |
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.name = "SMPS10_OUT1", .sname = "smps10-out2", .ctrl_addr = PALMAS_SMPS10_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10, |
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}, { |
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.name = "LDO1", |
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.sname = "ldo1-in", |
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.vsel_addr = PALMAS_LDO1_VOLTAGE, .ctrl_addr = PALMAS_LDO1_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1, |
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}, { .name = "LDO2", |
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.sname = "ldo2-in", |
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.vsel_addr = PALMAS_LDO2_VOLTAGE, .ctrl_addr = PALMAS_LDO2_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2, |
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}, { .name = "LDO3", |
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.sname = "ldo3-in", |
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.vsel_addr = PALMAS_LDO3_VOLTAGE, .ctrl_addr = PALMAS_LDO3_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3, |
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}, { .name = "LDO4", |
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.sname = "ldo4-in", |
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.vsel_addr = PALMAS_LDO4_VOLTAGE, .ctrl_addr = PALMAS_LDO4_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4, |
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}, { .name = "LDO5", |
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.sname = "ldo5-in", |
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.vsel_addr = PALMAS_LDO5_VOLTAGE, .ctrl_addr = PALMAS_LDO5_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5, |
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}, { .name = "LDO6", |
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.sname = "ldo6-in", |
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.vsel_addr = PALMAS_LDO6_VOLTAGE, .ctrl_addr = PALMAS_LDO6_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6, |
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}, { .name = "LDO7", |
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.sname = "ldo7-in", |
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.vsel_addr = PALMAS_LDO7_VOLTAGE, .ctrl_addr = PALMAS_LDO7_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7, |
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}, { .name = "LDO8", |
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.sname = "ldo8-in", |
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.vsel_addr = PALMAS_LDO8_VOLTAGE, .ctrl_addr = PALMAS_LDO8_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8, |
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}, { .name = "LDO9", |
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.sname = "ldo9-in", |
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.vsel_addr = PALMAS_LDO9_VOLTAGE, .ctrl_addr = PALMAS_LDO9_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9, |
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}, { .name = "LDOLN", |
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.sname = "ldoln-in", |
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.vsel_addr = PALMAS_LDOLN_VOLTAGE, .ctrl_addr = PALMAS_LDOLN_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN, |
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}, { .name = "LDOUSB", |
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.sname = "ldousb-in", |
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.vsel_addr = PALMAS_LDOUSB_VOLTAGE, .ctrl_addr = PALMAS_LDOUSB_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, |
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}, |
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{ .name = "REGEN1", .ctrl_addr = PALMAS_REGEN1_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1, |
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}, { .name = "REGEN2", .ctrl_addr = PALMAS_REGEN2_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2, |
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}, { .name = "REGEN3", .ctrl_addr = PALMAS_REGEN3_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3, |
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}, { .name = "SYSEN1", .ctrl_addr = PALMAS_SYSEN1_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, |
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}, { .name = "SYSEN2", .ctrl_addr = PALMAS_SYSEN2_CTRL, |
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.sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, |
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}, |
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}; |
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static struct palmas_regs_info tps65917_regs_info[] = { |
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{ .name = "SMPS1", .sname = "smps1-in", .vsel_addr = TPS65917_SMPS1_VOLTAGE, .ctrl_addr = TPS65917_SMPS1_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1, }, { .name = "SMPS2", .sname = "smps2-in", .vsel_addr = TPS65917_SMPS2_VOLTAGE, .ctrl_addr = TPS65917_SMPS2_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2, }, { .name = "SMPS3", .sname = "smps3-in", .vsel_addr = TPS65917_SMPS3_VOLTAGE, .ctrl_addr = TPS65917_SMPS3_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3, }, { .name = "SMPS4", .sname = "smps4-in", .vsel_addr = TPS65917_SMPS4_VOLTAGE, .ctrl_addr = TPS65917_SMPS4_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4, }, { .name = "SMPS5", .sname = "smps5-in", .vsel_addr = TPS65917_SMPS5_VOLTAGE, .ctrl_addr = TPS65917_SMPS5_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5, }, { |
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.name = "SMPS12", .sname = "smps1-in", .vsel_addr = TPS65917_SMPS1_VOLTAGE, .ctrl_addr = TPS65917_SMPS1_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12, }, { |
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.name = "LDO1", .sname = "ldo1-in", .vsel_addr = TPS65917_LDO1_VOLTAGE, .ctrl_addr = TPS65917_LDO1_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1, }, { .name = "LDO2", .sname = "ldo2-in", .vsel_addr = TPS65917_LDO2_VOLTAGE, .ctrl_addr = TPS65917_LDO2_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2, }, { .name = "LDO3", .sname = "ldo3-in", .vsel_addr = TPS65917_LDO3_VOLTAGE, .ctrl_addr = TPS65917_LDO3_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3, }, { .name = "LDO4", .sname = "ldo4-in", .vsel_addr = TPS65917_LDO4_VOLTAGE, .ctrl_addr = TPS65917_LDO4_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4, }, { .name = "LDO5", .sname = "ldo5-in", .vsel_addr = TPS65917_LDO5_VOLTAGE, .ctrl_addr = TPS65917_LDO5_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5, }, { .name = "REGEN1", .ctrl_addr = TPS65917_REGEN1_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1, }, { .name = "REGEN2", .ctrl_addr = TPS65917_REGEN2_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2, }, { .name = "REGEN3", .ctrl_addr = TPS65917_REGEN3_CTRL, .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3, }, }; |
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#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \ [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \ .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \ .reg_offset = _offset, \ .bit_pos = _pos, \ } |
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static struct palmas_sleep_requestor_info palma_sleep_req_info[] = { |
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EXTERNAL_REQUESTOR(REGEN1, 0, 0), EXTERNAL_REQUESTOR(REGEN2, 0, 1), EXTERNAL_REQUESTOR(SYSEN1, 0, 2), EXTERNAL_REQUESTOR(SYSEN2, 0, 3), EXTERNAL_REQUESTOR(CLK32KG, 0, 4), EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5), EXTERNAL_REQUESTOR(REGEN3, 0, 6), EXTERNAL_REQUESTOR(SMPS12, 1, 0), EXTERNAL_REQUESTOR(SMPS3, 1, 1), EXTERNAL_REQUESTOR(SMPS45, 1, 2), EXTERNAL_REQUESTOR(SMPS6, 1, 3), EXTERNAL_REQUESTOR(SMPS7, 1, 4), EXTERNAL_REQUESTOR(SMPS8, 1, 5), EXTERNAL_REQUESTOR(SMPS9, 1, 6), EXTERNAL_REQUESTOR(SMPS10, 1, 7), EXTERNAL_REQUESTOR(LDO1, 2, 0), EXTERNAL_REQUESTOR(LDO2, 2, 1), EXTERNAL_REQUESTOR(LDO3, 2, 2), EXTERNAL_REQUESTOR(LDO4, 2, 3), EXTERNAL_REQUESTOR(LDO5, 2, 4), EXTERNAL_REQUESTOR(LDO6, 2, 5), EXTERNAL_REQUESTOR(LDO7, 2, 6), EXTERNAL_REQUESTOR(LDO8, 2, 7), EXTERNAL_REQUESTOR(LDO9, 3, 0), EXTERNAL_REQUESTOR(LDOLN, 3, 1), EXTERNAL_REQUESTOR(LDOUSB, 3, 2), }; |
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#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \ [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \ .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \ .reg_offset = _offset, \ .bit_pos = _pos, \ } static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = { EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0), EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1), EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6), EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0), EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1), EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2), EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3), EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4), |
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EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5), |
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EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0), EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1), EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2), EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3), EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4), }; |
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static const unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500}; |
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#define SMPS_CTRL_MODE_OFF 0x00 #define SMPS_CTRL_MODE_ON 0x01 #define SMPS_CTRL_MODE_ECO 0x02 #define SMPS_CTRL_MODE_PWM 0x03 |
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#define PALMAS_SMPS_NUM_VOLTAGES 122 |
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#define PALMAS_SMPS10_NUM_VOLTAGES 2 #define PALMAS_LDO_NUM_VOLTAGES 50 #define SMPS10_VSEL (1<<3) #define SMPS10_BOOST_EN (1<<2) #define SMPS10_BYPASS_EN (1<<1) #define SMPS10_SWITCH_EN (1<<0) #define REGULATOR_SLAVE 0 static int palmas_smps_read(struct palmas *palmas, unsigned int reg, unsigned int *dest) { unsigned int addr; addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); } static int palmas_smps_write(struct palmas *palmas, unsigned int reg, unsigned int value) { unsigned int addr; addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); } static int palmas_ldo_read(struct palmas *palmas, unsigned int reg, unsigned int *dest) { unsigned int addr; addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); } static int palmas_ldo_write(struct palmas *palmas, unsigned int reg, unsigned int value) { unsigned int addr; addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); } |
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static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode) { |
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int id = rdev_get_id(dev); |
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int ret; |
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struct palmas_pmic *pmic = rdev_get_drvdata(dev); |
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struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
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struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
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unsigned int reg; |
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bool rail_enable = true; |
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ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, ®); if (ret) return ret; |
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reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
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if (reg == SMPS_CTRL_MODE_OFF) rail_enable = false; |
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switch (mode) { case REGULATOR_MODE_NORMAL: reg |= SMPS_CTRL_MODE_ON; break; case REGULATOR_MODE_IDLE: reg |= SMPS_CTRL_MODE_ECO; break; case REGULATOR_MODE_FAST: reg |= SMPS_CTRL_MODE_PWM; break; default: return -EINVAL; } |
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pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; if (rail_enable) |
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464 |
palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg); |
318dbb02b
|
465 466 467 |
/* Switch the enable value to ensure this is used for enable */ pmic->desc[id].enable_val = pmic->current_reg_mode[id]; |
e5ce4208f
|
468 469 470 471 472 473 474 475 |
return 0; } static unsigned int palmas_get_mode_smps(struct regulator_dev *dev) { struct palmas_pmic *pmic = rdev_get_drvdata(dev); int id = rdev_get_id(dev); unsigned int reg; |
51d3a0c99
|
476 |
reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208f
|
477 478 479 480 481 482 483 484 485 486 487 488 |
switch (reg) { case SMPS_CTRL_MODE_ON: return REGULATOR_MODE_NORMAL; case SMPS_CTRL_MODE_ECO: return REGULATOR_MODE_IDLE; case SMPS_CTRL_MODE_PWM: return REGULATOR_MODE_FAST; } return 0; } |
28d1e8cd6
|
489 490 491 |
static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) { |
cf910b6b7
|
492 |
int id = rdev_get_id(rdev); |
28d1e8cd6
|
493 |
struct palmas_pmic *pmic = rdev_get_drvdata(rdev); |
cac9e9162
|
494 |
struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b7
|
495 |
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
28d1e8cd6
|
496 |
unsigned int reg = 0; |
28d1e8cd6
|
497 |
int ret; |
f22c2bae2
|
498 499 500 501 502 503 |
/* SMPS3 and SMPS7 do not have tstep_addr setting */ switch (id) { case PALMAS_REG_SMPS3: case PALMAS_REG_SMPS7: return 0; } |
28d1e8cd6
|
504 505 |
if (ramp_delay <= 0) reg = 0; |
0ea34b578
|
506 |
else if (ramp_delay <= 2500) |
28d1e8cd6
|
507 |
reg = 3; |
0ea34b578
|
508 |
else if (ramp_delay <= 5000) |
28d1e8cd6
|
509 510 511 |
reg = 2; else reg = 1; |
cf910b6b7
|
512 |
ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg); |
28d1e8cd6
|
513 514 515 516 517 518 519 520 521 |
if (ret < 0) { dev_err(pmic->palmas->dev, "TSTEP write failed: %d ", ret); return ret; } pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg]; return ret; } |
0e5a76800
|
522 |
static const struct regulator_ops palmas_ops_smps = { |
dbabd624d
|
523 524 525 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, |
e5ce4208f
|
526 527 |
.set_mode = palmas_set_mode_smps, .get_mode = palmas_get_mode_smps, |
bdc4baace
|
528 529 |
.get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, |
dbabd624d
|
530 531 532 |
.list_voltage = regulator_list_voltage_linear_range, .map_voltage = regulator_map_voltage_linear_range, .set_voltage_time_sel = regulator_set_voltage_time_sel, |
28d1e8cd6
|
533 |
.set_ramp_delay = palmas_smps_set_ramp_delay, |
e5ce4208f
|
534 |
}; |
0e5a76800
|
535 |
static const struct regulator_ops palmas_ops_ext_control_smps = { |
32b6d3f60
|
536 537 538 539 |
.set_mode = palmas_set_mode_smps, .get_mode = palmas_get_mode_smps, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, |
dbabd624d
|
540 541 542 |
.list_voltage = regulator_list_voltage_linear_range, .map_voltage = regulator_map_voltage_linear_range, .set_voltage_time_sel = regulator_set_voltage_time_sel, |
32b6d3f60
|
543 544 |
.set_ramp_delay = palmas_smps_set_ramp_delay, }; |
0e5a76800
|
545 |
static const struct regulator_ops palmas_ops_smps10 = { |
e5ce4208f
|
546 547 548 549 550 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, |
8029a0068
|
551 552 |
.list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, |
77409d9bc
|
553 554 |
.set_bypass = regulator_set_bypass_regmap, .get_bypass = regulator_get_bypass_regmap, |
e5ce4208f
|
555 |
}; |
0e5a76800
|
556 |
static const struct regulator_ops tps65917_ops_smps = { |
d6f83370e
|
557 558 559 560 561 562 563 564 565 566 567 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, .set_mode = palmas_set_mode_smps, .get_mode = palmas_get_mode_smps, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .list_voltage = regulator_list_voltage_linear_range, .map_voltage = regulator_map_voltage_linear_range, .set_voltage_time_sel = regulator_set_voltage_time_sel, }; |
0e5a76800
|
568 |
static const struct regulator_ops tps65917_ops_ext_control_smps = { |
d6f83370e
|
569 570 571 572 573 574 575 |
.set_mode = palmas_set_mode_smps, .get_mode = palmas_get_mode_smps, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .list_voltage = regulator_list_voltage_linear_range, .map_voltage = regulator_map_voltage_linear_range, }; |
e5ce4208f
|
576 577 |
static int palmas_is_enabled_ldo(struct regulator_dev *dev) { |
cf910b6b7
|
578 |
int id = rdev_get_id(dev); |
e5ce4208f
|
579 |
struct palmas_pmic *pmic = rdev_get_drvdata(dev); |
cac9e9162
|
580 |
struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b7
|
581 |
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
e5ce4208f
|
582 |
unsigned int reg; |
cf910b6b7
|
583 |
palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, ®); |
e5ce4208f
|
584 585 586 587 588 |
reg &= PALMAS_LDO1_CTRL_STATUS; return !!(reg); } |
0e5a76800
|
589 |
static const struct regulator_ops palmas_ops_ldo = { |
e5ce4208f
|
590 591 592 |
.is_enabled = palmas_is_enabled_ldo, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, |
4a247a961
|
593 594 |
.get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, |
9119ff6af
|
595 596 |
.list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, |
e5ce4208f
|
597 |
}; |
0e5a76800
|
598 |
static const struct regulator_ops palmas_ops_ldo9 = { |
b554e1450
|
599 600 601 602 603 604 605 606 607 608 |
.is_enabled = palmas_is_enabled_ldo, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, .set_bypass = regulator_set_bypass_regmap, .get_bypass = regulator_get_bypass_regmap, }; |
0e5a76800
|
609 |
static const struct regulator_ops palmas_ops_ext_control_ldo = { |
32b6d3f60
|
610 611 612 613 614 |
.get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, }; |
0e5a76800
|
615 |
static const struct regulator_ops palmas_ops_extreg = { |
aa07f0279
|
616 617 618 619 |
.is_enabled = regulator_is_enabled_regmap, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, }; |
0e5a76800
|
620 |
static const struct regulator_ops palmas_ops_ext_control_extreg = { |
32b6d3f60
|
621 |
}; |
0e5a76800
|
622 |
static const struct regulator_ops tps65917_ops_ldo = { |
d6f83370e
|
623 624 625 626 627 628 629 630 631 |
.is_enabled = palmas_is_enabled_ldo, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, .set_voltage_time_sel = regulator_set_voltage_time_sel, }; |
0e5a76800
|
632 |
static const struct regulator_ops tps65917_ops_ldo_1_2 = { |
b554e1450
|
633 634 635 636 637 638 639 640 641 642 643 |
.is_enabled = palmas_is_enabled_ldo, .enable = regulator_enable_regmap, .disable = regulator_disable_regmap, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, .set_voltage_time_sel = regulator_set_voltage_time_sel, .set_bypass = regulator_set_bypass_regmap, .get_bypass = regulator_get_bypass_regmap, }; |
32b6d3f60
|
644 645 646 |
static int palmas_regulator_config_external(struct palmas *palmas, int id, struct palmas_reg_init *reg_init) { |
cf910b6b7
|
647 648 |
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
32b6d3f60
|
649 |
int ret; |
cf910b6b7
|
650 651 |
ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id, reg_init->roof_floor, true); |
32b6d3f60
|
652 653 654 655 656 657 658 |
if (ret < 0) dev_err(palmas->dev, "Ext control config for regulator %d failed %d ", id, ret); return ret; } |
e5ce4208f
|
659 660 661 662 663 664 665 666 667 668 |
/* * setup the hardware based sleep configuration of the SMPS/LDO regulators * from the platform data. This is different to the software based control * supported by the regulator framework as it is controlled by toggling * pins on the PMIC such as PREQ, SYSEN, ... */ static int palmas_smps_init(struct palmas *palmas, int id, struct palmas_reg_init *reg_init) { unsigned int reg; |
e5ce4208f
|
669 |
int ret; |
cac9e9162
|
670 |
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b7
|
671 672 |
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; unsigned int addr = rinfo->ctrl_addr; |
e5ce4208f
|
673 674 675 676 |
ret = palmas_smps_read(palmas, addr, ®); if (ret) return ret; |
fedd89b1a
|
677 |
switch (id) { |
77409d9bc
|
678 679 |
case PALMAS_REG_SMPS10_OUT1: case PALMAS_REG_SMPS10_OUT2: |
30590d048
|
680 681 |
reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; if (reg_init->mode_sleep) |
fedd89b1a
|
682 683 |
reg |= reg_init->mode_sleep << PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT; |
fedd89b1a
|
684 685 |
break; default: |
e5ce4208f
|
686 687 |
if (reg_init->warm_reset) reg |= PALMAS_SMPS12_CTRL_WR_S; |
30590d048
|
688 689 |
else reg &= ~PALMAS_SMPS12_CTRL_WR_S; |
e5ce4208f
|
690 691 692 |
if (reg_init->roof_floor) reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; |
30590d048
|
693 694 |
else reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; |
e5ce4208f
|
695 |
|
30590d048
|
696 697 |
reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; if (reg_init->mode_sleep) |
e5ce4208f
|
698 699 |
reg |= reg_init->mode_sleep << PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT; |
e5ce4208f
|
700 |
} |
fedd89b1a
|
701 |
|
e5ce4208f
|
702 703 704 |
ret = palmas_smps_write(palmas, addr, reg); if (ret) return ret; |
cf910b6b7
|
705 |
if (rinfo->vsel_addr && reg_init->vsel) { |
e5ce4208f
|
706 707 |
reg = reg_init->vsel; |
cf910b6b7
|
708 |
ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg); |
e5ce4208f
|
709 710 711 |
if (ret) return ret; } |
32b6d3f60
|
712 713 714 |
if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) && (id != PALMAS_REG_SMPS10_OUT2)) { /* Enable externally controlled regulator */ |
32b6d3f60
|
715 716 717 |
ret = palmas_smps_read(palmas, addr, ®); if (ret < 0) return ret; |
e5ce4208f
|
718 |
|
32b6d3f60
|
719 720 721 722 723 724 725 726 |
if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) { reg |= SMPS_CTRL_MODE_ON; ret = palmas_smps_write(palmas, addr, reg); if (ret < 0) return ret; } return palmas_regulator_config_external(palmas, id, reg_init); } |
e5ce4208f
|
727 728 729 730 731 732 733 734 735 |
return 0; } static int palmas_ldo_init(struct palmas *palmas, int id, struct palmas_reg_init *reg_init) { unsigned int reg; unsigned int addr; int ret; |
cac9e9162
|
736 |
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b7
|
737 |
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
cac9e9162
|
738 |
|
cf910b6b7
|
739 |
addr = rinfo->ctrl_addr; |
e5ce4208f
|
740 |
|
2735daeb1
|
741 |
ret = palmas_ldo_read(palmas, addr, ®); |
e5ce4208f
|
742 743 744 745 746 |
if (ret) return ret; if (reg_init->warm_reset) reg |= PALMAS_LDO1_CTRL_WR_S; |
30590d048
|
747 748 |
else reg &= ~PALMAS_LDO1_CTRL_WR_S; |
e5ce4208f
|
749 750 751 |
if (reg_init->mode_sleep) reg |= PALMAS_LDO1_CTRL_MODE_SLEEP; |
30590d048
|
752 753 |
else reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP; |
e5ce4208f
|
754 |
|
2735daeb1
|
755 |
ret = palmas_ldo_write(palmas, addr, reg); |
e5ce4208f
|
756 757 |
if (ret) return ret; |
32b6d3f60
|
758 759 |
if (reg_init->roof_floor) { /* Enable externally controlled regulator */ |
32b6d3f60
|
760 761 762 763 764 765 766 767 768 769 770 771 |
ret = palmas_update_bits(palmas, PALMAS_LDO_BASE, addr, PALMAS_LDO1_CTRL_MODE_ACTIVE, PALMAS_LDO1_CTRL_MODE_ACTIVE); if (ret < 0) { dev_err(palmas->dev, "LDO Register 0x%02x update failed %d ", addr, ret); return ret; } return palmas_regulator_config_external(palmas, id, reg_init); } |
e5ce4208f
|
772 773 |
return 0; } |
aa07f0279
|
774 775 776 777 778 779 |
static int palmas_extreg_init(struct palmas *palmas, int id, struct palmas_reg_init *reg_init) { unsigned int addr; int ret; unsigned int val = 0; |
cac9e9162
|
780 |
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b7
|
781 |
struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
cac9e9162
|
782 |
|
cf910b6b7
|
783 |
addr = rinfo->ctrl_addr; |
aa07f0279
|
784 785 786 787 788 789 790 791 792 793 794 795 |
if (reg_init->mode_sleep) val = PALMAS_REGEN1_CTRL_MODE_SLEEP; ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val); if (ret < 0) { dev_err(palmas->dev, "Resource reg 0x%02x update failed %d ", addr, ret); return ret; } |
32b6d3f60
|
796 797 798 |
if (reg_init->roof_floor) { /* Enable externally controlled regulator */ |
32b6d3f60
|
799 800 801 802 803 804 805 806 807 808 809 810 |
ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE, PALMAS_REGEN1_CTRL_MODE_ACTIVE); if (ret < 0) { dev_err(palmas->dev, "Resource Register 0x%02x update failed %d ", addr, ret); return ret; } return palmas_regulator_config_external(palmas, id, reg_init); } |
aa07f0279
|
811 812 |
return 0; } |
17c11a760
|
813 814 815 816 817 |
static void palmas_enable_ldo8_track(struct palmas *palmas) { unsigned int reg; unsigned int addr; int ret; |
cac9e9162
|
818 |
struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b7
|
819 |
struct palmas_regs_info *rinfo; |
cac9e9162
|
820 |
|
cf910b6b7
|
821 822 |
rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8]; addr = rinfo->ctrl_addr; |
17c11a760
|
823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 |
ret = palmas_ldo_read(palmas, addr, ®); if (ret) { dev_err(palmas->dev, "Error in reading ldo8 control reg "); return; } reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN; ret = palmas_ldo_write(palmas, addr, reg); if (ret < 0) { dev_err(palmas->dev, "Error in enabling tracking mode "); return; } /* * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two, * and can be set from 0.45 to 1.65 V. */ |
cf910b6b7
|
843 |
addr = rinfo->vsel_addr; |
17c11a760
|
844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 |
ret = palmas_ldo_read(palmas, addr, ®); if (ret) { dev_err(palmas->dev, "Error in reading ldo8 voltage reg "); return; } reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK; ret = palmas_ldo_write(palmas, addr, reg); if (ret < 0) dev_err(palmas->dev, "Error in setting ldo8 voltage reg "); return; } |
cac9e9162
|
859 860 861 862 863 |
static int palmas_ldo_registration(struct palmas_pmic *pmic, struct palmas_pmic_driver_data *ddata, struct palmas_pmic_platform_data *pdata, const char *pdev_name, struct regulator_config config) |
a361cd9f2
|
864 |
{ |
cac9e9162
|
865 866 867 |
int id, ret; struct regulator_dev *rdev; struct palmas_reg_init *reg_init; |
cf910b6b7
|
868 |
struct palmas_regs_info *rinfo; |
429222d00
|
869 |
struct regulator_desc *desc; |
a361cd9f2
|
870 |
|
cac9e9162
|
871 872 873 874 875 |
for (id = ddata->ldo_begin; id < ddata->max_reg; id++) { if (pdata && pdata->reg_init[id]) reg_init = pdata->reg_init[id]; else reg_init = NULL; |
a361cd9f2
|
876 |
|
cf910b6b7
|
877 |
rinfo = &ddata->palmas_regs_info[id]; |
cac9e9162
|
878 879 880 |
/* Miss out regulators which are not available due * to alternate functions. */ |
a361cd9f2
|
881 |
|
cac9e9162
|
882 |
/* Register the regulators */ |
429222d00
|
883 884 885 886 887 |
desc = &pmic->desc[id]; desc->name = rinfo->name; desc->id = id; desc->type = REGULATOR_VOLTAGE; desc->owner = THIS_MODULE; |
a361cd9f2
|
888 |
|
cac9e9162
|
889 |
if (id < PALMAS_REG_REGEN1) { |
429222d00
|
890 |
desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES; |
cac9e9162
|
891 |
if (reg_init && reg_init->roof_floor) |
429222d00
|
892 |
desc->ops = &palmas_ops_ext_control_ldo; |
cac9e9162
|
893 |
else |
429222d00
|
894 895 896 897 898 899 900 901 902 903 904 |
desc->ops = &palmas_ops_ldo; desc->min_uV = 900000; desc->uV_step = 50000; desc->linear_min_sel = 1; desc->enable_time = 500; desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, rinfo->vsel_addr); desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK; desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, rinfo->ctrl_addr); desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; |
a361cd9f2
|
905 |
|
cac9e9162
|
906 907 908 909 |
/* Check if LDO8 is in tracking mode or not */ if (pdata && (id == PALMAS_REG_LDO8) && pdata->enable_ldo8_tracking) { palmas_enable_ldo8_track(pmic->palmas); |
429222d00
|
910 911 |
desc->min_uV = 450000; desc->uV_step = 25000; |
cac9e9162
|
912 |
} |
a361cd9f2
|
913 |
|
cac9e9162
|
914 915 916 |
/* LOD6 in vibrator mode will have enable time 2000us */ if (pdata && pdata->ldo6_vibrator && (id == PALMAS_REG_LDO6)) |
429222d00
|
917 |
desc->enable_time = 2000; |
b554e1450
|
918 919 920 921 |
if (id == PALMAS_REG_LDO9) { desc->ops = &palmas_ops_ldo9; desc->bypass_reg = desc->enable_reg; |
e0341f173
|
922 923 |
desc->bypass_val_on = PALMAS_LDO9_CTRL_LDO_BYPASS_EN; |
b554e1450
|
924 925 926 |
desc->bypass_mask = PALMAS_LDO9_CTRL_LDO_BYPASS_EN; } |
cac9e9162
|
927 |
} else { |
e999c7289
|
928 929 |
if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3) continue; |
429222d00
|
930 |
desc->n_voltages = 1; |
cac9e9162
|
931 |
if (reg_init && reg_init->roof_floor) |
429222d00
|
932 |
desc->ops = &palmas_ops_ext_control_extreg; |
cac9e9162
|
933 |
else |
429222d00
|
934 935 |
desc->ops = &palmas_ops_extreg; desc->enable_reg = |
cac9e9162
|
936 |
PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, |
cf910b6b7
|
937 |
rinfo->ctrl_addr); |
429222d00
|
938 |
desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; |
cac9e9162
|
939 |
} |
a361cd9f2
|
940 |
|
cac9e9162
|
941 942 943 944 |
if (pdata) config.init_data = pdata->reg_data[id]; else config.init_data = NULL; |
32b6d3f60
|
945 |
|
429222d00
|
946 |
desc->supply_name = rinfo->sname; |
cac9e9162
|
947 |
config.of_node = ddata->palmas_matches[id].of_node; |
a361cd9f2
|
948 |
|
429222d00
|
949 |
rdev = devm_regulator_register(pmic->dev, desc, &config); |
cac9e9162
|
950 951 952 953 954 955 956 |
if (IS_ERR(rdev)) { dev_err(pmic->dev, "failed to register %s regulator ", pdev_name); return PTR_ERR(rdev); } |
a361cd9f2
|
957 |
|
cac9e9162
|
958 959 960 961 962 963 964 965 966 967 968 969 970 971 |
/* Initialise sleep/init values from platform data */ if (pdata) { reg_init = pdata->reg_init[id]; if (reg_init) { if (id <= ddata->ldo_end) ret = palmas_ldo_init(pmic->palmas, id, reg_init); else ret = palmas_extreg_init(pmic->palmas, id, reg_init); if (ret) return ret; } } |
a361cd9f2
|
972 |
} |
cac9e9162
|
973 |
return 0; |
a361cd9f2
|
974 |
} |
d6f83370e
|
975 976 977 978 979 980 981 982 983 |
static int tps65917_ldo_registration(struct palmas_pmic *pmic, struct palmas_pmic_driver_data *ddata, struct palmas_pmic_platform_data *pdata, const char *pdev_name, struct regulator_config config) { int id, ret; struct regulator_dev *rdev; struct palmas_reg_init *reg_init; |
cf910b6b7
|
984 |
struct palmas_regs_info *rinfo; |
429222d00
|
985 |
struct regulator_desc *desc; |
d6f83370e
|
986 987 988 989 990 991 992 993 994 995 |
for (id = ddata->ldo_begin; id < ddata->max_reg; id++) { if (pdata && pdata->reg_init[id]) reg_init = pdata->reg_init[id]; else reg_init = NULL; /* Miss out regulators which are not available due * to alternate functions. */ |
cf910b6b7
|
996 |
rinfo = &ddata->palmas_regs_info[id]; |
d6f83370e
|
997 998 |
/* Register the regulators */ |
429222d00
|
999 1000 1001 1002 1003 |
desc = &pmic->desc[id]; desc->name = rinfo->name; desc->id = id; desc->type = REGULATOR_VOLTAGE; desc->owner = THIS_MODULE; |
d6f83370e
|
1004 1005 |
if (id < TPS65917_REG_REGEN1) { |
429222d00
|
1006 |
desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES; |
d6f83370e
|
1007 |
if (reg_init && reg_init->roof_floor) |
429222d00
|
1008 |
desc->ops = &palmas_ops_ext_control_ldo; |
d6f83370e
|
1009 |
else |
429222d00
|
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 |
desc->ops = &tps65917_ops_ldo; desc->min_uV = 900000; desc->uV_step = 50000; desc->linear_min_sel = 1; desc->enable_time = 500; desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, rinfo->vsel_addr); desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK; desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, rinfo->ctrl_addr); desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; |
d6f83370e
|
1021 1022 1023 1024 |
/* * To be confirmed. Discussion on going with PMIC Team. * It is of the order of ~60mV/uS. */ |
429222d00
|
1025 |
desc->ramp_delay = 2500; |
b554e1450
|
1026 1027 1028 1029 |
if (id == TPS65917_REG_LDO1 || id == TPS65917_REG_LDO2) { desc->ops = &tps65917_ops_ldo_1_2; desc->bypass_reg = desc->enable_reg; |
e0341f173
|
1030 1031 |
desc->bypass_val_on = TPS65917_LDO1_CTRL_BYPASS_EN; |
b554e1450
|
1032 1033 1034 |
desc->bypass_mask = TPS65917_LDO1_CTRL_BYPASS_EN; } |
d6f83370e
|
1035 |
} else { |
429222d00
|
1036 |
desc->n_voltages = 1; |
d6f83370e
|
1037 |
if (reg_init && reg_init->roof_floor) |
429222d00
|
1038 |
desc->ops = &palmas_ops_ext_control_extreg; |
d6f83370e
|
1039 |
else |
429222d00
|
1040 1041 |
desc->ops = &palmas_ops_extreg; desc->enable_reg = |
d6f83370e
|
1042 |
PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, |
cf910b6b7
|
1043 |
rinfo->ctrl_addr); |
429222d00
|
1044 |
desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; |
d6f83370e
|
1045 1046 1047 1048 1049 1050 |
} if (pdata) config.init_data = pdata->reg_data[id]; else config.init_data = NULL; |
429222d00
|
1051 |
desc->supply_name = rinfo->sname; |
d6f83370e
|
1052 |
config.of_node = ddata->palmas_matches[id].of_node; |
429222d00
|
1053 |
rdev = devm_regulator_register(pmic->dev, desc, &config); |
d6f83370e
|
1054 1055 1056 1057 1058 1059 1060 |
if (IS_ERR(rdev)) { dev_err(pmic->dev, "failed to register %s regulator ", pdev_name); return PTR_ERR(rdev); } |
d6f83370e
|
1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 |
/* Initialise sleep/init values from platform data */ if (pdata) { reg_init = pdata->reg_init[id]; if (reg_init) { if (id < TPS65917_REG_REGEN1) ret = palmas_ldo_init(pmic->palmas, id, reg_init); else ret = palmas_extreg_init(pmic->palmas, id, reg_init); if (ret) return ret; } } } return 0; } |
cac9e9162
|
1079 1080 1081 1082 1083 |
static int palmas_smps_registration(struct palmas_pmic *pmic, struct palmas_pmic_driver_data *ddata, struct palmas_pmic_platform_data *pdata, const char *pdev_name, struct regulator_config config) |
e5ce4208f
|
1084 |
{ |
cac9e9162
|
1085 1086 |
int id, ret; unsigned int addr, reg; |
e5ce4208f
|
1087 |
struct regulator_dev *rdev; |
e5ce4208f
|
1088 |
struct palmas_reg_init *reg_init; |
cf910b6b7
|
1089 |
struct palmas_regs_info *rinfo; |
429222d00
|
1090 |
struct regulator_desc *desc; |
e5ce4208f
|
1091 |
|
cac9e9162
|
1092 |
for (id = ddata->smps_start; id <= ddata->smps_end; id++) { |
28d1e8cd6
|
1093 |
bool ramp_delay_support = false; |
e5ce4208f
|
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 |
/* * Miss out regulators which are not available due * to slaving configurations. */ switch (id) { case PALMAS_REG_SMPS12: case PALMAS_REG_SMPS3: if (pmic->smps123) continue; |
28d1e8cd6
|
1104 1105 |
if (id == PALMAS_REG_SMPS12) ramp_delay_support = true; |
e5ce4208f
|
1106 1107 1108 1109 |
break; case PALMAS_REG_SMPS123: if (!pmic->smps123) continue; |
28d1e8cd6
|
1110 |
ramp_delay_support = true; |
e5ce4208f
|
1111 1112 1113 1114 1115 |
break; case PALMAS_REG_SMPS45: case PALMAS_REG_SMPS7: if (pmic->smps457) continue; |
28d1e8cd6
|
1116 1117 |
if (id == PALMAS_REG_SMPS45) ramp_delay_support = true; |
e5ce4208f
|
1118 1119 1120 1121 |
break; case PALMAS_REG_SMPS457: if (!pmic->smps457) continue; |
28d1e8cd6
|
1122 1123 |
ramp_delay_support = true; break; |
77409d9bc
|
1124 1125 |
case PALMAS_REG_SMPS10_OUT1: case PALMAS_REG_SMPS10_OUT2: |
cac9e9162
|
1126 |
if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST)) |
1ffb0be3a
|
1127 |
continue; |
28d1e8cd6
|
1128 |
} |
cf910b6b7
|
1129 |
rinfo = &ddata->palmas_regs_info[id]; |
429222d00
|
1130 |
desc = &pmic->desc[id]; |
28d1e8cd6
|
1131 |
|
3f4d63640
|
1132 |
if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8)) |
28d1e8cd6
|
1133 1134 1135 |
ramp_delay_support = true; if (ramp_delay_support) { |
cf910b6b7
|
1136 |
addr = rinfo->tstep_addr; |
28d1e8cd6
|
1137 1138 |
ret = palmas_smps_read(pmic->palmas, addr, ®); if (ret < 0) { |
cac9e9162
|
1139 |
dev_err(pmic->dev, |
28d1e8cd6
|
1140 1141 |
"reading TSTEP reg failed: %d ", ret); |
51c86b3eb
|
1142 |
return ret; |
28d1e8cd6
|
1143 |
} |
429222d00
|
1144 1145 |
desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3]; pmic->ramp_delay[id] = desc->ramp_delay; |
e5ce4208f
|
1146 |
} |
bdc4baace
|
1147 1148 1149 |
/* Initialise sleep/init values from platform data */ if (pdata && pdata->reg_init[id]) { reg_init = pdata->reg_init[id]; |
cac9e9162
|
1150 |
ret = palmas_smps_init(pmic->palmas, id, reg_init); |
bdc4baace
|
1151 |
if (ret) |
51c86b3eb
|
1152 |
return ret; |
32b6d3f60
|
1153 1154 |
} else { reg_init = NULL; |
bdc4baace
|
1155 |
} |
e5ce4208f
|
1156 |
/* Register the regulators */ |
429222d00
|
1157 1158 |
desc->name = rinfo->name; desc->id = id; |
e5ce4208f
|
1159 |
|
fedd89b1a
|
1160 |
switch (id) { |
77409d9bc
|
1161 1162 |
case PALMAS_REG_SMPS10_OUT1: case PALMAS_REG_SMPS10_OUT2: |
429222d00
|
1163 1164 1165 1166 1167 1168 1169 |
desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES; desc->ops = &palmas_ops_smps10; desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, PALMAS_SMPS10_CTRL); desc->vsel_mask = SMPS10_VSEL; desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, PALMAS_SMPS10_CTRL); |
77409d9bc
|
1170 |
if (id == PALMAS_REG_SMPS10_OUT1) |
429222d00
|
1171 |
desc->enable_mask = SMPS10_SWITCH_EN; |
77409d9bc
|
1172 |
else |
429222d00
|
1173 1174 1175 |
desc->enable_mask = SMPS10_BOOST_EN; desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, PALMAS_SMPS10_CTRL); |
e0341f173
|
1176 |
desc->bypass_val_on = SMPS10_BYPASS_EN; |
429222d00
|
1177 1178 1179 |
desc->bypass_mask = SMPS10_BYPASS_EN; desc->min_uV = 3750000; desc->uV_step = 1250000; |
fedd89b1a
|
1180 1181 |
break; default: |
bdc4baace
|
1182 1183 1184 |
/* * Read and store the RANGE bit for later use * This must be done before regulator is probed, |
51d3a0c99
|
1185 1186 |
* otherwise we error in probe with unsupportable * ranges. Read the current smps mode for later use. |
bdc4baace
|
1187 |
*/ |
cf910b6b7
|
1188 |
addr = rinfo->vsel_addr; |
429222d00
|
1189 |
desc->n_linear_ranges = 3; |
e5ce4208f
|
1190 1191 1192 |
ret = palmas_smps_read(pmic->palmas, addr, ®); if (ret) |
51c86b3eb
|
1193 |
return ret; |
e5ce4208f
|
1194 1195 |
if (reg & PALMAS_SMPS12_VOLTAGE_RANGE) pmic->range[id] = 1; |
dbabd624d
|
1196 |
if (pmic->range[id]) |
429222d00
|
1197 |
desc->linear_ranges = smps_high_ranges; |
dbabd624d
|
1198 |
else |
429222d00
|
1199 |
desc->linear_ranges = smps_low_ranges; |
bdc4baace
|
1200 |
|
32b6d3f60
|
1201 |
if (reg_init && reg_init->roof_floor) |
429222d00
|
1202 |
desc->ops = &palmas_ops_ext_control_smps; |
32b6d3f60
|
1203 |
else |
429222d00
|
1204 1205 1206 1207 1208 |
desc->ops = &palmas_ops_smps; desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES; desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, rinfo->vsel_addr); desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK; |
51d3a0c99
|
1209 1210 |
/* Read the smps mode for later use. */ |
cf910b6b7
|
1211 |
addr = rinfo->ctrl_addr; |
51d3a0c99
|
1212 1213 |
ret = palmas_smps_read(pmic->palmas, addr, ®); if (ret) |
51c86b3eb
|
1214 |
return ret; |
51d3a0c99
|
1215 1216 |
pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
318dbb02b
|
1217 |
|
429222d00
|
1218 1219 1220 |
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, rinfo->ctrl_addr); desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
318dbb02b
|
1221 |
/* set_mode overrides this value */ |
429222d00
|
1222 |
desc->enable_val = SMPS_CTRL_MODE_ON; |
e5ce4208f
|
1223 |
} |
429222d00
|
1224 1225 |
desc->type = REGULATOR_VOLTAGE; desc->owner = THIS_MODULE; |
bdc4baace
|
1226 |
|
a361cd9f2
|
1227 |
if (pdata) |
e5ce4208f
|
1228 1229 1230 |
config.init_data = pdata->reg_data[id]; else config.init_data = NULL; |
429222d00
|
1231 |
desc->supply_name = rinfo->sname; |
cac9e9162
|
1232 |
config.of_node = ddata->palmas_matches[id].of_node; |
a361cd9f2
|
1233 |
|
429222d00
|
1234 |
rdev = devm_regulator_register(pmic->dev, desc, &config); |
e5ce4208f
|
1235 |
if (IS_ERR(rdev)) { |
cac9e9162
|
1236 |
dev_err(pmic->dev, |
e5ce4208f
|
1237 1238 |
"failed to register %s regulator ", |
cac9e9162
|
1239 |
pdev_name); |
51c86b3eb
|
1240 |
return PTR_ERR(rdev); |
e5ce4208f
|
1241 |
} |
e5ce4208f
|
1242 |
} |
cac9e9162
|
1243 1244 |
return 0; } |
e5ce4208f
|
1245 |
|
d6f83370e
|
1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 |
static int tps65917_smps_registration(struct palmas_pmic *pmic, struct palmas_pmic_driver_data *ddata, struct palmas_pmic_platform_data *pdata, const char *pdev_name, struct regulator_config config) { int id, ret; unsigned int addr, reg; struct regulator_dev *rdev; struct palmas_reg_init *reg_init; |
cf910b6b7
|
1256 |
struct palmas_regs_info *rinfo; |
429222d00
|
1257 |
struct regulator_desc *desc; |
d6f83370e
|
1258 1259 1260 1261 1262 1263 |
for (id = ddata->smps_start; id <= ddata->smps_end; id++) { /* * Miss out regulators which are not available due * to slaving configurations. */ |
429222d00
|
1264 1265 |
desc = &pmic->desc[id]; desc->n_linear_ranges = 3; |
be0353031
|
1266 1267 |
if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) && pmic->smps12) |
d6f83370e
|
1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 |
continue; /* Initialise sleep/init values from platform data */ if (pdata && pdata->reg_init[id]) { reg_init = pdata->reg_init[id]; ret = palmas_smps_init(pmic->palmas, id, reg_init); if (ret) return ret; } else { reg_init = NULL; } |
cf910b6b7
|
1279 |
rinfo = &ddata->palmas_regs_info[id]; |
d6f83370e
|
1280 1281 |
/* Register the regulators */ |
429222d00
|
1282 1283 |
desc->name = rinfo->name; desc->id = id; |
d6f83370e
|
1284 1285 1286 1287 1288 1289 1290 |
/* * Read and store the RANGE bit for later use * This must be done before regulator is probed, * otherwise we error in probe with unsupportable * ranges. Read the current smps mode for later use. */ |
cf910b6b7
|
1291 |
addr = rinfo->vsel_addr; |
d6f83370e
|
1292 1293 1294 1295 1296 1297 1298 1299 |
ret = palmas_smps_read(pmic->palmas, addr, ®); if (ret) return ret; if (reg & TPS65917_SMPS1_VOLTAGE_RANGE) pmic->range[id] = 1; if (pmic->range[id]) |
429222d00
|
1300 1301 1302 |
desc->linear_ranges = smps_high_ranges; else desc->linear_ranges = smps_low_ranges; |
d6f83370e
|
1303 1304 |
if (reg_init && reg_init->roof_floor) |
429222d00
|
1305 |
desc->ops = &tps65917_ops_ext_control_smps; |
d6f83370e
|
1306 |
else |
429222d00
|
1307 1308 1309 1310 1311 1312 |
desc->ops = &tps65917_ops_smps; desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES; desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, rinfo->vsel_addr); desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK; desc->ramp_delay = 2500; |
d6f83370e
|
1313 1314 |
/* Read the smps mode for later use. */ |
cf910b6b7
|
1315 |
addr = rinfo->ctrl_addr; |
d6f83370e
|
1316 1317 1318 1319 1320 |
ret = palmas_smps_read(pmic->palmas, addr, ®); if (ret) return ret; pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
b632815e9
|
1321 1322 1323 1324 1325 |
desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, rinfo->ctrl_addr); desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; /* set_mode overrides this value */ desc->enable_val = SMPS_CTRL_MODE_ON; |
d6f83370e
|
1326 |
|
429222d00
|
1327 1328 |
desc->type = REGULATOR_VOLTAGE; desc->owner = THIS_MODULE; |
d6f83370e
|
1329 1330 1331 1332 1333 |
if (pdata) config.init_data = pdata->reg_data[id]; else config.init_data = NULL; |
429222d00
|
1334 |
desc->supply_name = rinfo->sname; |
d6f83370e
|
1335 |
config.of_node = ddata->palmas_matches[id].of_node; |
429222d00
|
1336 |
rdev = devm_regulator_register(pmic->dev, desc, &config); |
d6f83370e
|
1337 1338 1339 1340 1341 1342 1343 |
if (IS_ERR(rdev)) { dev_err(pmic->dev, "failed to register %s regulator ", pdev_name); return PTR_ERR(rdev); } |
d6f83370e
|
1344 1345 1346 1347 |
} return 0; } |
cac9e9162
|
1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 |
static struct of_regulator_match palmas_matches[] = { { .name = "smps12", }, { .name = "smps123", }, { .name = "smps3", }, { .name = "smps45", }, { .name = "smps457", }, { .name = "smps6", }, { .name = "smps7", }, { .name = "smps8", }, { .name = "smps9", }, { .name = "smps10_out2", }, { .name = "smps10_out1", }, { .name = "ldo1", }, { .name = "ldo2", }, { .name = "ldo3", }, { .name = "ldo4", }, { .name = "ldo5", }, { .name = "ldo6", }, { .name = "ldo7", }, { .name = "ldo8", }, { .name = "ldo9", }, { .name = "ldoln", }, { .name = "ldousb", }, { .name = "regen1", }, { .name = "regen2", }, { .name = "regen3", }, { .name = "sysen1", }, { .name = "sysen2", }, }; |
e5ce4208f
|
1377 |
|
d6f83370e
|
1378 1379 1380 1381 1382 1383 |
static struct of_regulator_match tps65917_matches[] = { { .name = "smps1", }, { .name = "smps2", }, { .name = "smps3", }, { .name = "smps4", }, { .name = "smps5", }, |
be0353031
|
1384 |
{ .name = "smps12",}, |
d6f83370e
|
1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 |
{ .name = "ldo1", }, { .name = "ldo2", }, { .name = "ldo3", }, { .name = "ldo4", }, { .name = "ldo5", }, { .name = "regen1", }, { .name = "regen2", }, { .name = "regen3", }, { .name = "sysen1", }, { .name = "sysen2", }, }; |
4b09e17b6
|
1396 |
static struct palmas_pmic_driver_data palmas_ddata = { |
cac9e9162
|
1397 1398 1399 1400 1401 |
.smps_start = PALMAS_REG_SMPS12, .smps_end = PALMAS_REG_SMPS10_OUT1, .ldo_begin = PALMAS_REG_LDO1, .ldo_end = PALMAS_REG_LDOUSB, .max_reg = PALMAS_NUM_REGS, |
e999c7289
|
1402 |
.has_regen3 = true, |
6839cd6f6
|
1403 |
.palmas_regs_info = palmas_generic_regs_info, |
cac9e9162
|
1404 1405 1406 1407 1408 |
.palmas_matches = palmas_matches, .sleep_req_info = palma_sleep_req_info, .smps_register = palmas_smps_registration, .ldo_register = palmas_ldo_registration, }; |
aa07f0279
|
1409 |
|
4b09e17b6
|
1410 |
static struct palmas_pmic_driver_data tps65917_ddata = { |
d6f83370e
|
1411 |
.smps_start = TPS65917_REG_SMPS1, |
be0353031
|
1412 |
.smps_end = TPS65917_REG_SMPS12, |
d6f83370e
|
1413 1414 1415 |
.ldo_begin = TPS65917_REG_LDO1, .ldo_end = TPS65917_REG_LDO5, .max_reg = TPS65917_NUM_REGS, |
e999c7289
|
1416 |
.has_regen3 = true, |
d6f83370e
|
1417 1418 1419 1420 1421 1422 |
.palmas_regs_info = tps65917_regs_info, .palmas_matches = tps65917_matches, .sleep_req_info = tps65917_sleep_req_info, .smps_register = tps65917_smps_registration, .ldo_register = tps65917_ldo_registration, }; |
7f091e53c
|
1423 1424 1425 1426 |
static int palmas_dt_to_pdata(struct device *dev, struct device_node *node, struct palmas_pmic_platform_data *pdata, struct palmas_pmic_driver_data *ddata) |
cac9e9162
|
1427 1428 1429 1430 |
{ struct device_node *regulators; u32 prop; int idx, ret; |
17c11a760
|
1431 |
|
cac9e9162
|
1432 1433 1434 1435 |
regulators = of_get_child_by_name(node, "regulators"); if (!regulators) { dev_info(dev, "regulator node not found "); |
7f091e53c
|
1436 |
return 0; |
cac9e9162
|
1437 |
} |
087d30e30
|
1438 |
|
cac9e9162
|
1439 1440 1441 1442 1443 1444 |
ret = of_regulator_match(dev, regulators, ddata->palmas_matches, ddata->max_reg); of_node_put(regulators); if (ret < 0) { dev_err(dev, "Error parsing regulator init data: %d ", ret); |
7f091e53c
|
1445 |
return 0; |
cac9e9162
|
1446 |
} |
e5ce4208f
|
1447 |
|
cac9e9162
|
1448 |
for (idx = 0; idx < ddata->max_reg; idx++) { |
96e4f5232
|
1449 |
struct of_regulator_match *match; |
1b42443db
|
1450 |
struct palmas_reg_init *rinit; |
6c7d614fa
|
1451 |
struct device_node *np; |
036d193d3
|
1452 1453 |
match = &ddata->palmas_matches[idx]; |
6c7d614fa
|
1454 |
np = match->of_node; |
036d193d3
|
1455 |
|
6c7d614fa
|
1456 |
if (!match->init_data || !np) |
cac9e9162
|
1457 |
continue; |
e5ce4208f
|
1458 |
|
1b42443db
|
1459 |
rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL); |
7f091e53c
|
1460 1461 |
if (!rinit) return -ENOMEM; |
036d193d3
|
1462 |
pdata->reg_data[idx] = match->init_data; |
1b42443db
|
1463 |
pdata->reg_init[idx] = rinit; |
a361cd9f2
|
1464 |
|
6c7d614fa
|
1465 1466 |
rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset"); ret = of_property_read_u32(np, "ti,roof-floor", &prop); |
cac9e9162
|
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 |
/* EINVAL: Property not found */ if (ret != -EINVAL) { int econtrol; /* use default value, when no value is specified */ econtrol = PALMAS_EXT_CONTROL_NSLEEP; if (!ret) { switch (prop) { case 1: econtrol = PALMAS_EXT_CONTROL_ENABLE1; break; case 2: econtrol = PALMAS_EXT_CONTROL_ENABLE2; break; case 3: econtrol = PALMAS_EXT_CONTROL_NSLEEP; break; default: WARN_ON(1); dev_warn(dev, "%s: Invalid roof-floor option: %u ", |
036d193d3
|
1489 |
match->name, prop); |
cac9e9162
|
1490 1491 |
break; } |
e5ce4208f
|
1492 |
} |
1b42443db
|
1493 |
rinit->roof_floor = econtrol; |
e5ce4208f
|
1494 |
} |
e5ce4208f
|
1495 |
|
6c7d614fa
|
1496 |
ret = of_property_read_u32(np, "ti,mode-sleep", &prop); |
cac9e9162
|
1497 |
if (!ret) |
1b42443db
|
1498 |
rinit->mode_sleep = prop; |
17c11a760
|
1499 |
|
6c7d614fa
|
1500 |
ret = of_property_read_bool(np, "ti,smps-range"); |
cac9e9162
|
1501 |
if (ret) |
1b42443db
|
1502 |
rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE; |
cac9e9162
|
1503 1504 1505 |
if (idx == PALMAS_REG_LDO8) pdata->enable_ldo8_tracking = of_property_read_bool( |
6c7d614fa
|
1506 |
np, "ti,enable-ldo8-tracking"); |
cac9e9162
|
1507 1508 1509 |
} pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator"); |
7f091e53c
|
1510 1511 |
return 0; |
e5ce4208f
|
1512 |
} |
cdbf6f0e8
|
1513 |
static const struct of_device_id of_palmas_match_tbl[] = { |
cac9e9162
|
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 |
{ .compatible = "ti,palmas-pmic", .data = &palmas_ddata, }, { .compatible = "ti,twl6035-pmic", .data = &palmas_ddata, }, { .compatible = "ti,twl6036-pmic", .data = &palmas_ddata, }, { .compatible = "ti,twl6037-pmic", .data = &palmas_ddata, }, { .compatible = "ti,tps65913-pmic", .data = &palmas_ddata, }, { .compatible = "ti,tps65914-pmic", .data = &palmas_ddata, }, { .compatible = "ti,tps80036-pmic", .data = &palmas_ddata, }, { .compatible = "ti,tps659038-pmic", .data = &palmas_ddata, }, |
d6f83370e
|
1546 1547 1548 1549 |
{ .compatible = "ti,tps65917-pmic", .data = &tps65917_ddata, }, |
a361cd9f2
|
1550 1551 |
{ /* end */ } }; |
cac9e9162
|
1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 |
static int palmas_regulators_probe(struct platform_device *pdev) { struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev); struct device_node *node = pdev->dev.of_node; struct palmas_pmic_driver_data *driver_data; struct regulator_config config = { }; struct palmas_pmic *pmic; const char *pdev_name; const struct of_device_id *match; int ret = 0; unsigned int reg; match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev); if (!match) return -ENODATA; driver_data = (struct palmas_pmic_driver_data *)match->data; pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) return -ENOMEM; |
e999c7289
|
1578 |
if (of_device_is_compatible(node, "ti,tps659038-pmic")) { |
e03826d50
|
1579 1580 |
palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr = TPS659038_REGEN2_CTRL; |
e999c7289
|
1581 1582 |
palmas_ddata.has_regen3 = false; } |
e03826d50
|
1583 |
|
cac9e9162
|
1584 1585 1586 1587 1588 |
pmic->dev = &pdev->dev; pmic->palmas = palmas; palmas->pmic = pmic; platform_set_drvdata(pdev, pmic); pmic->palmas->pmic_ddata = driver_data; |
7f091e53c
|
1589 1590 1591 |
ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data); if (ret) return ret; |
cac9e9162
|
1592 1593 1594 1595 |
ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®); if (ret) return ret; |
be0353031
|
1596 |
if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) { |
cac9e9162
|
1597 |
pmic->smps123 = 1; |
be0353031
|
1598 1599 |
pmic->smps12 = 1; } |
cac9e9162
|
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 |
if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN) pmic->smps457 = 1; config.regmap = palmas->regmap[REGULATOR_SLAVE]; config.dev = &pdev->dev; config.driver_data = pmic; pdev_name = pdev->name; ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name, config); if (ret) return ret; ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name, config); return ret; } |
e5ce4208f
|
1619 1620 1621 |
static struct platform_driver palmas_driver = { .driver = { .name = "palmas-pmic", |
a361cd9f2
|
1622 |
.of_match_table = of_palmas_match_tbl, |
e5ce4208f
|
1623 |
}, |
bbcf50b1d
|
1624 |
.probe = palmas_regulators_probe, |
e5ce4208f
|
1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 |
}; static int __init palmas_init(void) { return platform_driver_register(&palmas_driver); } subsys_initcall(palmas_init); static void __exit palmas_exit(void) { platform_driver_unregister(&palmas_driver); } module_exit(palmas_exit); MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); MODULE_DESCRIPTION("Palmas voltage regulator driver"); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:palmas-pmic"); |
a361cd9f2
|
1643 |
MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); |