/*
   * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
   *

   *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

   *

   * Licensed under GPLv2.

   */

  #include "at91sam9260.dtsi"

  
  / {
  	model = "Atmel AT91SAM9G20 family SoC";
  	compatible = "atmel,at91sam9g20";

  	memory {

  		reg = <0x20000000 0x08000000>;
  	};

  	sram0: sram@002ff000 {
  		status = "disabled";
  	};
  
  	sram1: sram@002fc000 {
  		compatible = "mmio-sram";
  		reg = <0x002fc000 0x8000>;
  	};

  	ahb {
  		apb {

  			i2c0: i2c@fffac000 {
  				compatible = "atmel,at91sam9g20-i2c";
  			};

  			ssc0: ssc@fffbc000 {
  				compatible = "atmel,at91sam9rl-ssc";
  			};

  			adc0: adc@fffe0000 {
  				atmel,adc-startup-time = <40>;
  			};

  
  			pmc: pmc@fffffc00 {
  				plla: pllack {
  					atmel,clk-input-range = <2000000 32000000>;
  					atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
  								<695000000 750000000 1 0>,
  								<645000000 700000000 2 0>,
  								<595000000 650000000 3 0>,
  								<545000000 600000000 0 1>,
  								<495000000 550000000 1 1>,
  								<445000000 500000000 2 1>,
  								<400000000 450000000 3 1>;
  				};
  
  				pllb: pllbck {

  					compatible = "atmel,at91sam9g20-clk-pllb";

  					atmel,clk-input-range = <2000000 32000000>;
  					atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
  				};
  
  				mck: masterck {
  					atmel,clk-output-range = <0 133000000>;
  					atmel,clk-divisors = <1 2 4 6>;
  				};
  			};

  		};
  	};

  };