Blame view
drivers/dma/pch_dma.c
26.4 KB
0c42bd0e4 dmaengine: Driver... |
1 2 3 |
/* * Topcliff PCH DMA controller driver * Copyright (c) 2010 Intel Corporation |
2cdf2455a pch_dma: support ... |
4 |
* Copyright (C) 2011 OKI SEMICONDUCTOR CO., LTD. |
0c42bd0e4 dmaengine: Driver... |
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 |
* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/pch_dma.h> #define DRV_NAME "pch-dma" #define DMA_CTL0_DISABLE 0x0 #define DMA_CTL0_SG 0x1 #define DMA_CTL0_ONESHOT 0x2 #define DMA_CTL0_MODE_MASK_BITS 0x3 #define DMA_CTL0_DIR_SHIFT_BITS 2 #define DMA_CTL0_BITS_PER_CH 4 #define DMA_CTL2_START_SHIFT_BITS 8 #define DMA_CTL2_IRQ_ENABLE_MASK ((1UL << DMA_CTL2_START_SHIFT_BITS) - 1) #define DMA_STATUS_IDLE 0x0 #define DMA_STATUS_DESC_READ 0x1 #define DMA_STATUS_WAIT 0x2 #define DMA_STATUS_ACCESS 0x3 #define DMA_STATUS_BITS_PER_CH 2 #define DMA_STATUS_MASK_BITS 0x3 #define DMA_STATUS_SHIFT_BITS 16 #define DMA_STATUS_IRQ(x) (0x1 << (x)) |
c3d4913cd pch_dma: fix DMA ... |
48 49 |
#define DMA_STATUS0_ERR(x) (0x1 << ((x) + 8)) #define DMA_STATUS2_ERR(x) (0x1 << (x)) |
0c42bd0e4 dmaengine: Driver... |
50 51 52 53 54 55 56 57 58 59 60 61 |
#define DMA_DESC_WIDTH_SHIFT_BITS 12 #define DMA_DESC_WIDTH_1_BYTE (0x3 << DMA_DESC_WIDTH_SHIFT_BITS) #define DMA_DESC_WIDTH_2_BYTES (0x2 << DMA_DESC_WIDTH_SHIFT_BITS) #define DMA_DESC_WIDTH_4_BYTES (0x0 << DMA_DESC_WIDTH_SHIFT_BITS) #define DMA_DESC_MAX_COUNT_1_BYTE 0x3FF #define DMA_DESC_MAX_COUNT_2_BYTES 0x3FF #define DMA_DESC_MAX_COUNT_4_BYTES 0x7FF #define DMA_DESC_END_WITHOUT_IRQ 0x0 #define DMA_DESC_END_WITH_IRQ 0x1 #define DMA_DESC_FOLLOW_WITHOUT_IRQ 0x2 #define DMA_DESC_FOLLOW_WITH_IRQ 0x3 |
c43f15086 pch_dma: Fix susp... |
62 |
#define MAX_CHAN_NR 12 |
0c42bd0e4 dmaengine: Driver... |
63 |
|
0b052f4a0 pch_dma: Fix CTL ... |
64 65 |
#define DMA_MASK_CTL0_MODE 0x33333333 #define DMA_MASK_CTL2_MODE 0x00003333 |
0c42bd0e4 dmaengine: Driver... |
66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 |
static unsigned int init_nr_desc_per_channel = 64; module_param(init_nr_desc_per_channel, uint, 0644); MODULE_PARM_DESC(init_nr_desc_per_channel, "initial descriptors per channel (default: 64)"); struct pch_dma_desc_regs { u32 dev_addr; u32 mem_addr; u32 size; u32 next; }; struct pch_dma_regs { u32 dma_ctl0; u32 dma_ctl1; u32 dma_ctl2; |
194f5f270 pch_dma: Support ... |
82 |
u32 dma_ctl3; |
0c42bd0e4 dmaengine: Driver... |
83 84 |
u32 dma_sts0; u32 dma_sts1; |
194f5f270 pch_dma: Support ... |
85 |
u32 dma_sts2; |
0c42bd0e4 dmaengine: Driver... |
86 |
u32 reserved3; |
26d890f0d pch_dma: set the ... |
87 |
struct pch_dma_desc_regs desc[MAX_CHAN_NR]; |
0c42bd0e4 dmaengine: Driver... |
88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 |
}; struct pch_dma_desc { struct pch_dma_desc_regs regs; struct dma_async_tx_descriptor txd; struct list_head desc_node; struct list_head tx_list; }; struct pch_dma_chan { struct dma_chan chan; void __iomem *membase; enum dma_data_direction dir; struct tasklet_struct tasklet; unsigned long err_status; spinlock_t lock; dma_cookie_t completed_cookie; struct list_head active_list; struct list_head queue; struct list_head free_list; unsigned int descs_allocated; }; #define PDC_DEV_ADDR 0x00 #define PDC_MEM_ADDR 0x04 #define PDC_SIZE 0x08 #define PDC_NEXT 0x0C #define channel_readl(pdc, name) \ readl((pdc)->membase + PDC_##name) #define channel_writel(pdc, name, val) \ writel((val), (pdc)->membase + PDC_##name) struct pch_dma { struct dma_device dma; void __iomem *membase; struct pci_pool *pool; struct pch_dma_regs regs; struct pch_dma_desc_regs ch_regs[MAX_CHAN_NR]; |
26d890f0d pch_dma: set the ... |
129 |
struct pch_dma_chan channels[MAX_CHAN_NR]; |
0c42bd0e4 dmaengine: Driver... |
130 131 132 133 134 |
}; #define PCH_DMA_CTL0 0x00 #define PCH_DMA_CTL1 0x04 #define PCH_DMA_CTL2 0x08 |
194f5f270 pch_dma: Support ... |
135 |
#define PCH_DMA_CTL3 0x0C |
0c42bd0e4 dmaengine: Driver... |
136 137 |
#define PCH_DMA_STS0 0x10 #define PCH_DMA_STS1 0x14 |
c3d4913cd pch_dma: fix DMA ... |
138 |
#define PCH_DMA_STS2 0x18 |
0c42bd0e4 dmaengine: Driver... |
139 140 |
#define dma_readl(pd, name) \ |
61cd22037 DMAENGINE: pch_dm... |
141 |
readl((pd)->membase + PCH_DMA_##name) |
0c42bd0e4 dmaengine: Driver... |
142 |
#define dma_writel(pd, name, val) \ |
61cd22037 DMAENGINE: pch_dm... |
143 |
writel((val), (pd)->membase + PCH_DMA_##name) |
0c42bd0e4 dmaengine: Driver... |
144 |
|
08645fdc7 pch_dma: modify f... |
145 146 |
static inline struct pch_dma_desc *to_pd_desc(struct dma_async_tx_descriptor *txd) |
0c42bd0e4 dmaengine: Driver... |
147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 |
{ return container_of(txd, struct pch_dma_desc, txd); } static inline struct pch_dma_chan *to_pd_chan(struct dma_chan *chan) { return container_of(chan, struct pch_dma_chan, chan); } static inline struct pch_dma *to_pd(struct dma_device *ddev) { return container_of(ddev, struct pch_dma, dma); } static inline struct device *chan2dev(struct dma_chan *chan) { return &chan->dev->device; } static inline struct device *chan2parent(struct dma_chan *chan) { return chan->dev->device.parent; } |
08645fdc7 pch_dma: modify f... |
170 171 |
static inline struct pch_dma_desc *pdc_first_active(struct pch_dma_chan *pd_chan) |
0c42bd0e4 dmaengine: Driver... |
172 173 174 175 |
{ return list_first_entry(&pd_chan->active_list, struct pch_dma_desc, desc_node); } |
08645fdc7 pch_dma: modify f... |
176 177 |
static inline struct pch_dma_desc *pdc_first_queued(struct pch_dma_chan *pd_chan) |
0c42bd0e4 dmaengine: Driver... |
178 179 180 181 182 183 184 185 186 |
{ return list_first_entry(&pd_chan->queue, struct pch_dma_desc, desc_node); } static void pdc_enable_irq(struct dma_chan *chan, int enable) { struct pch_dma *pd = to_pd(chan->device); u32 val; |
c3d4913cd pch_dma: fix DMA ... |
187 188 189 190 191 192 |
int pos; if (chan->chan_id < 8) pos = chan->chan_id; else pos = chan->chan_id + 8; |
0c42bd0e4 dmaengine: Driver... |
193 194 195 196 |
val = dma_readl(pd, CTL2); if (enable) |
c3d4913cd pch_dma: fix DMA ... |
197 |
val |= 0x1 << pos; |
0c42bd0e4 dmaengine: Driver... |
198 |
else |
c3d4913cd pch_dma: fix DMA ... |
199 |
val &= ~(0x1 << pos); |
0c42bd0e4 dmaengine: Driver... |
200 201 202 203 204 205 206 207 208 209 210 211 212 |
dma_writel(pd, CTL2, val); dev_dbg(chan2dev(chan), "pdc_enable_irq: chan %d -> %x ", chan->chan_id, val); } static void pdc_set_dir(struct dma_chan *chan) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); struct pch_dma *pd = to_pd(chan->device); u32 val; |
0b052f4a0 pch_dma: Fix CTL ... |
213 214 |
u32 mask_mode; u32 mask_ctl; |
0c42bd0e4 dmaengine: Driver... |
215 |
|
194f5f270 pch_dma: Support ... |
216 217 |
if (chan->chan_id < 8) { val = dma_readl(pd, CTL0); |
0c42bd0e4 dmaengine: Driver... |
218 |
|
0b052f4a0 pch_dma: Fix CTL ... |
219 220 221 222 223 |
mask_mode = DMA_CTL0_MODE_MASK_BITS << (DMA_CTL0_BITS_PER_CH * chan->chan_id); mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS << (DMA_CTL0_BITS_PER_CH * chan->chan_id)); val &= mask_mode; |
194f5f270 pch_dma: Support ... |
224 225 226 227 228 229 |
if (pd_chan->dir == DMA_TO_DEVICE) val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + DMA_CTL0_DIR_SHIFT_BITS); else val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id + DMA_CTL0_DIR_SHIFT_BITS)); |
0b052f4a0 pch_dma: Fix CTL ... |
230 |
val |= mask_ctl; |
194f5f270 pch_dma: Support ... |
231 232 233 234 |
dma_writel(pd, CTL0, val); } else { int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */ val = dma_readl(pd, CTL3); |
0c42bd0e4 dmaengine: Driver... |
235 |
|
0b052f4a0 pch_dma: Fix CTL ... |
236 237 238 239 240 |
mask_mode = DMA_CTL0_MODE_MASK_BITS << (DMA_CTL0_BITS_PER_CH * ch); mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS << (DMA_CTL0_BITS_PER_CH * ch)); val &= mask_mode; |
194f5f270 pch_dma: Support ... |
241 242 243 244 245 246 |
if (pd_chan->dir == DMA_TO_DEVICE) val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch + DMA_CTL0_DIR_SHIFT_BITS); else val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch + DMA_CTL0_DIR_SHIFT_BITS)); |
0b052f4a0 pch_dma: Fix CTL ... |
247 |
val |= mask_ctl; |
194f5f270 pch_dma: Support ... |
248 249 |
dma_writel(pd, CTL3, val); } |
0c42bd0e4 dmaengine: Driver... |
250 251 252 253 254 255 256 257 258 259 |
dev_dbg(chan2dev(chan), "pdc_set_dir: chan %d -> %x ", chan->chan_id, val); } static void pdc_set_mode(struct dma_chan *chan, u32 mode) { struct pch_dma *pd = to_pd(chan->device); u32 val; |
0b052f4a0 pch_dma: Fix CTL ... |
260 261 |
u32 mask_ctl; u32 mask_dir; |
0c42bd0e4 dmaengine: Driver... |
262 |
|
194f5f270 pch_dma: Support ... |
263 |
if (chan->chan_id < 8) { |
0b052f4a0 pch_dma: Fix CTL ... |
264 265 266 267 |
mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS << (DMA_CTL0_BITS_PER_CH * chan->chan_id)); mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\ DMA_CTL0_DIR_SHIFT_BITS); |
194f5f270 pch_dma: Support ... |
268 |
val = dma_readl(pd, CTL0); |
0b052f4a0 pch_dma: Fix CTL ... |
269 |
val &= mask_dir; |
194f5f270 pch_dma: Support ... |
270 |
val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id); |
0b052f4a0 pch_dma: Fix CTL ... |
271 |
val |= mask_ctl; |
194f5f270 pch_dma: Support ... |
272 273 274 |
dma_writel(pd, CTL0, val); } else { int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */ |
0b052f4a0 pch_dma: Fix CTL ... |
275 276 277 278 |
mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS << (DMA_CTL0_BITS_PER_CH * ch)); mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\ DMA_CTL0_DIR_SHIFT_BITS); |
194f5f270 pch_dma: Support ... |
279 |
val = dma_readl(pd, CTL3); |
0b052f4a0 pch_dma: Fix CTL ... |
280 |
val &= mask_dir; |
194f5f270 pch_dma: Support ... |
281 |
val |= mode << (DMA_CTL0_BITS_PER_CH * ch); |
0b052f4a0 pch_dma: Fix CTL ... |
282 |
val |= mask_ctl; |
194f5f270 pch_dma: Support ... |
283 |
dma_writel(pd, CTL3, val); |
194f5f270 pch_dma: Support ... |
284 |
} |
0c42bd0e4 dmaengine: Driver... |
285 286 287 288 289 |
dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x ", chan->chan_id, val); } |
c3d4913cd pch_dma: fix DMA ... |
290 |
static u32 pdc_get_status0(struct pch_dma_chan *pd_chan) |
0c42bd0e4 dmaengine: Driver... |
291 292 293 294 295 296 297 298 |
{ struct pch_dma *pd = to_pd(pd_chan->chan.device); u32 val; val = dma_readl(pd, STS0); return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS + DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id)); } |
c3d4913cd pch_dma: fix DMA ... |
299 300 301 302 303 304 305 306 307 |
static u32 pdc_get_status2(struct pch_dma_chan *pd_chan) { struct pch_dma *pd = to_pd(pd_chan->chan.device); u32 val; val = dma_readl(pd, STS2); return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS + DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8))); } |
0c42bd0e4 dmaengine: Driver... |
308 309 |
static bool pdc_is_idle(struct pch_dma_chan *pd_chan) { |
c3d4913cd pch_dma: fix DMA ... |
310 311 312 313 314 315 316 317 318 |
u32 sts; if (pd_chan->chan.chan_id < 8) sts = pdc_get_status0(pd_chan); else sts = pdc_get_status2(pd_chan); if (sts == DMA_STATUS_IDLE) |
0c42bd0e4 dmaengine: Driver... |
319 320 321 322 323 324 325 |
return true; else return false; } static void pdc_dostart(struct pch_dma_chan *pd_chan, struct pch_dma_desc* desc) { |
0c42bd0e4 dmaengine: Driver... |
326 327 328 329 330 331 |
if (!pdc_is_idle(pd_chan)) { dev_err(chan2dev(&pd_chan->chan), "BUG: Attempt to start non-idle channel "); return; } |
0c42bd0e4 dmaengine: Driver... |
332 333 334 335 336 337 338 339 340 341 342 343 |
dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> dev_addr: %x ", pd_chan->chan.chan_id, desc->regs.dev_addr); dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> mem_addr: %x ", pd_chan->chan.chan_id, desc->regs.mem_addr); dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> size: %x ", pd_chan->chan.chan_id, desc->regs.size); dev_dbg(chan2dev(&pd_chan->chan), "chan %d -> next: %x ", pd_chan->chan.chan_id, desc->regs.next); |
943d8d8bc dma : EG20T PCH: ... |
344 345 346 347 348 |
if (list_empty(&desc->tx_list)) { channel_writel(pd_chan, DEV_ADDR, desc->regs.dev_addr); channel_writel(pd_chan, MEM_ADDR, desc->regs.mem_addr); channel_writel(pd_chan, SIZE, desc->regs.size); channel_writel(pd_chan, NEXT, desc->regs.next); |
0c42bd0e4 dmaengine: Driver... |
349 |
pdc_set_mode(&pd_chan->chan, DMA_CTL0_ONESHOT); |
943d8d8bc dma : EG20T PCH: ... |
350 351 |
} else { channel_writel(pd_chan, NEXT, desc->txd.phys); |
0c42bd0e4 dmaengine: Driver... |
352 |
pdc_set_mode(&pd_chan->chan, DMA_CTL0_SG); |
943d8d8bc dma : EG20T PCH: ... |
353 |
} |
0c42bd0e4 dmaengine: Driver... |
354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 |
} static void pdc_chain_complete(struct pch_dma_chan *pd_chan, struct pch_dma_desc *desc) { struct dma_async_tx_descriptor *txd = &desc->txd; dma_async_tx_callback callback = txd->callback; void *param = txd->callback_param; list_splice_init(&desc->tx_list, &pd_chan->free_list); list_move(&desc->desc_node, &pd_chan->free_list); if (callback) callback(param); } static void pdc_complete_all(struct pch_dma_chan *pd_chan) { struct pch_dma_desc *desc, *_d; LIST_HEAD(list); BUG_ON(!pdc_is_idle(pd_chan)); if (!list_empty(&pd_chan->queue)) pdc_dostart(pd_chan, pdc_first_queued(pd_chan)); list_splice_init(&pd_chan->active_list, &list); list_splice_init(&pd_chan->queue, &pd_chan->active_list); list_for_each_entry_safe(desc, _d, &list, desc_node) pdc_chain_complete(pd_chan, desc); } static void pdc_handle_error(struct pch_dma_chan *pd_chan) { struct pch_dma_desc *bad_desc; bad_desc = pdc_first_active(pd_chan); list_del(&bad_desc->desc_node); list_splice_init(&pd_chan->queue, pd_chan->active_list.prev); if (!list_empty(&pd_chan->active_list)) pdc_dostart(pd_chan, pdc_first_active(pd_chan)); dev_crit(chan2dev(&pd_chan->chan), "Bad descriptor submitted "); dev_crit(chan2dev(&pd_chan->chan), "descriptor cookie: %d ", bad_desc->txd.cookie); pdc_chain_complete(pd_chan, bad_desc); } static void pdc_advance_work(struct pch_dma_chan *pd_chan) { if (list_empty(&pd_chan->active_list) || list_is_singular(&pd_chan->active_list)) { pdc_complete_all(pd_chan); } else { pdc_chain_complete(pd_chan, pdc_first_active(pd_chan)); pdc_dostart(pd_chan, pdc_first_active(pd_chan)); } } static dma_cookie_t pdc_assign_cookie(struct pch_dma_chan *pd_chan, struct pch_dma_desc *desc) { dma_cookie_t cookie = pd_chan->chan.cookie; if (++cookie < 0) cookie = 1; pd_chan->chan.cookie = cookie; desc->txd.cookie = cookie; return cookie; } static dma_cookie_t pd_tx_submit(struct dma_async_tx_descriptor *txd) { struct pch_dma_desc *desc = to_pd_desc(txd); struct pch_dma_chan *pd_chan = to_pd_chan(txd->chan); dma_cookie_t cookie; |
c5a9f9d08 pch_dma: fix kern... |
438 |
spin_lock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
439 440 441 442 443 444 445 446 |
cookie = pdc_assign_cookie(pd_chan, desc); if (list_empty(&pd_chan->active_list)) { list_add_tail(&desc->desc_node, &pd_chan->active_list); pdc_dostart(pd_chan, desc); } else { list_add_tail(&desc->desc_node, &pd_chan->queue); } |
c5a9f9d08 pch_dma: fix kern... |
447 |
spin_unlock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
448 449 450 451 452 453 454 455 |
return 0; } static struct pch_dma_desc *pdc_alloc_desc(struct dma_chan *chan, gfp_t flags) { struct pch_dma_desc *desc = NULL; struct pch_dma *pd = to_pd(chan->device); dma_addr_t addr; |
c5a9f9d08 pch_dma: fix kern... |
456 |
desc = pci_pool_alloc(pd->pool, flags, &addr); |
0c42bd0e4 dmaengine: Driver... |
457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 |
if (desc) { memset(desc, 0, sizeof(struct pch_dma_desc)); INIT_LIST_HEAD(&desc->tx_list); dma_async_tx_descriptor_init(&desc->txd, chan); desc->txd.tx_submit = pd_tx_submit; desc->txd.flags = DMA_CTRL_ACK; desc->txd.phys = addr; } return desc; } static struct pch_dma_desc *pdc_desc_get(struct pch_dma_chan *pd_chan) { struct pch_dma_desc *desc, *_d; struct pch_dma_desc *ret = NULL; |
364de7783 drivers, pch_dma:... |
473 |
int i = 0; |
0c42bd0e4 dmaengine: Driver... |
474 |
|
c5a9f9d08 pch_dma: fix kern... |
475 |
spin_lock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
476 477 478 479 480 481 482 483 484 485 |
list_for_each_entry_safe(desc, _d, &pd_chan->free_list, desc_node) { i++; if (async_tx_test_ack(&desc->txd)) { list_del(&desc->desc_node); ret = desc; break; } dev_dbg(chan2dev(&pd_chan->chan), "desc %p not ACKed ", desc); } |
c5a9f9d08 pch_dma: fix kern... |
486 |
spin_unlock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
487 488 489 490 491 492 |
dev_dbg(chan2dev(&pd_chan->chan), "scanned %d descriptors ", i); if (!ret) { ret = pdc_alloc_desc(&pd_chan->chan, GFP_NOIO); if (ret) { |
c5a9f9d08 pch_dma: fix kern... |
493 |
spin_lock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
494 |
pd_chan->descs_allocated++; |
c5a9f9d08 pch_dma: fix kern... |
495 |
spin_unlock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
496 497 498 499 500 501 502 503 504 505 506 507 508 509 |
} else { dev_err(chan2dev(&pd_chan->chan), "failed to alloc desc "); } } return ret; } static void pdc_desc_put(struct pch_dma_chan *pd_chan, struct pch_dma_desc *desc) { if (desc) { |
c5a9f9d08 pch_dma: fix kern... |
510 |
spin_lock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
511 512 |
list_splice_init(&desc->tx_list, &pd_chan->free_list); list_add(&desc->desc_node, &pd_chan->free_list); |
c5a9f9d08 pch_dma: fix kern... |
513 |
spin_unlock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 |
} } static int pd_alloc_chan_resources(struct dma_chan *chan) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); struct pch_dma_desc *desc; LIST_HEAD(tmp_list); int i; if (!pdc_is_idle(pd_chan)) { dev_dbg(chan2dev(chan), "DMA channel not idle ? "); return -EIO; } if (!list_empty(&pd_chan->free_list)) return pd_chan->descs_allocated; for (i = 0; i < init_nr_desc_per_channel; i++) { desc = pdc_alloc_desc(chan, GFP_KERNEL); if (!desc) { dev_warn(chan2dev(chan), "Only allocated %d initial descriptors ", i); break; } list_add_tail(&desc->desc_node, &tmp_list); } |
70f189158 pch_dma: Fix chan... |
545 |
spin_lock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
546 547 548 |
list_splice(&tmp_list, &pd_chan->free_list); pd_chan->descs_allocated = i; pd_chan->completed_cookie = chan->cookie = 1; |
70f189158 pch_dma: Fix chan... |
549 |
spin_unlock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
550 551 |
pdc_enable_irq(chan, 1); |
0c42bd0e4 dmaengine: Driver... |
552 553 554 555 556 557 558 559 560 561 562 563 564 565 |
return pd_chan->descs_allocated; } static void pd_free_chan_resources(struct dma_chan *chan) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); struct pch_dma *pd = to_pd(chan->device); struct pch_dma_desc *desc, *_d; LIST_HEAD(tmp_list); BUG_ON(!pdc_is_idle(pd_chan)); BUG_ON(!list_empty(&pd_chan->active_list)); BUG_ON(!list_empty(&pd_chan->queue)); |
70f189158 pch_dma: Fix chan... |
566 |
spin_lock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
567 568 |
list_splice_init(&pd_chan->free_list, &tmp_list); pd_chan->descs_allocated = 0; |
70f189158 pch_dma: Fix chan... |
569 |
spin_unlock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
570 571 572 573 574 575 576 577 578 579 580 581 582 583 |
list_for_each_entry_safe(desc, _d, &tmp_list, desc_node) pci_pool_free(pd->pool, desc, desc->txd.phys); pdc_enable_irq(chan, 0); } static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie, struct dma_tx_state *txstate) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); dma_cookie_t last_used; dma_cookie_t last_completed; int ret; |
70f189158 pch_dma: Fix chan... |
584 |
spin_lock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
585 586 |
last_completed = pd_chan->completed_cookie; last_used = chan->cookie; |
70f189158 pch_dma: Fix chan... |
587 |
spin_unlock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
588 589 590 591 592 593 594 595 596 597 598 599 600 |
ret = dma_async_is_complete(cookie, last_completed, last_used); dma_set_tx_state(txstate, last_completed, last_used, 0); return ret; } static void pd_issue_pending(struct dma_chan *chan) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); if (pdc_is_idle(pd_chan)) { |
c5a9f9d08 pch_dma: fix kern... |
601 |
spin_lock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
602 |
pdc_advance_work(pd_chan); |
c5a9f9d08 pch_dma: fix kern... |
603 |
spin_unlock(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 |
} } static struct dma_async_tx_descriptor *pd_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, enum dma_data_direction direction, unsigned long flags) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); struct pch_dma_slave *pd_slave = chan->private; struct pch_dma_desc *first = NULL; struct pch_dma_desc *prev = NULL; struct pch_dma_desc *desc = NULL; struct scatterlist *sg; dma_addr_t reg; int i; if (unlikely(!sg_len)) { dev_info(chan2dev(chan), "prep_slave_sg: length is zero! "); return NULL; } if (direction == DMA_FROM_DEVICE) reg = pd_slave->rx_reg; else if (direction == DMA_TO_DEVICE) reg = pd_slave->tx_reg; else return NULL; |
c8fcba600 pch_dma: fix dma ... |
632 633 |
pd_chan->dir = direction; pdc_set_dir(chan); |
0c42bd0e4 dmaengine: Driver... |
634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 |
for_each_sg(sgl, sg, sg_len, i) { desc = pdc_desc_get(pd_chan); if (!desc) goto err_desc_get; desc->regs.dev_addr = reg; desc->regs.mem_addr = sg_phys(sg); desc->regs.size = sg_dma_len(sg); desc->regs.next = DMA_DESC_FOLLOW_WITHOUT_IRQ; switch (pd_slave->width) { case PCH_DMA_WIDTH_1_BYTE: if (desc->regs.size > DMA_DESC_MAX_COUNT_1_BYTE) goto err_desc_get; desc->regs.size |= DMA_DESC_WIDTH_1_BYTE; break; case PCH_DMA_WIDTH_2_BYTES: if (desc->regs.size > DMA_DESC_MAX_COUNT_2_BYTES) goto err_desc_get; desc->regs.size |= DMA_DESC_WIDTH_2_BYTES; break; case PCH_DMA_WIDTH_4_BYTES: if (desc->regs.size > DMA_DESC_MAX_COUNT_4_BYTES) goto err_desc_get; desc->regs.size |= DMA_DESC_WIDTH_4_BYTES; break; default: goto err_desc_get; } |
0c42bd0e4 dmaengine: Driver... |
664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 |
if (!first) { first = desc; } else { prev->regs.next |= desc->txd.phys; list_add_tail(&desc->desc_node, &first->tx_list); } prev = desc; } if (flags & DMA_PREP_INTERRUPT) desc->regs.next = DMA_DESC_END_WITH_IRQ; else desc->regs.next = DMA_DESC_END_WITHOUT_IRQ; first->txd.cookie = -EBUSY; desc->txd.flags = flags; return &first->txd; err_desc_get: dev_err(chan2dev(chan), "failed to get desc or wrong parameters "); pdc_desc_put(pd_chan, first); return NULL; } static int pd_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) { struct pch_dma_chan *pd_chan = to_pd_chan(chan); struct pch_dma_desc *desc, *_d; LIST_HEAD(list); if (cmd != DMA_TERMINATE_ALL) return -ENXIO; |
70f189158 pch_dma: Fix chan... |
700 |
spin_lock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
701 702 703 704 705 706 707 708 |
pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE); list_splice_init(&pd_chan->active_list, &list); list_splice_init(&pd_chan->queue, &list); list_for_each_entry_safe(desc, _d, &list, desc_node) pdc_chain_complete(pd_chan, desc); |
70f189158 pch_dma: Fix chan... |
709 |
spin_unlock_irq(&pd_chan->lock); |
0c42bd0e4 dmaengine: Driver... |
710 |
|
0c42bd0e4 dmaengine: Driver... |
711 712 713 714 715 716 |
return 0; } static void pdc_tasklet(unsigned long data) { struct pch_dma_chan *pd_chan = (struct pch_dma_chan *)data; |
c5a9f9d08 pch_dma: fix kern... |
717 |
unsigned long flags; |
0c42bd0e4 dmaengine: Driver... |
718 719 720 721 722 723 724 |
if (!pdc_is_idle(pd_chan)) { dev_err(chan2dev(&pd_chan->chan), "BUG: handle non-idle channel in tasklet "); return; } |
c5a9f9d08 pch_dma: fix kern... |
725 |
spin_lock_irqsave(&pd_chan->lock, flags); |
0c42bd0e4 dmaengine: Driver... |
726 727 728 729 |
if (test_and_clear_bit(0, &pd_chan->err_status)) pdc_handle_error(pd_chan); else pdc_advance_work(pd_chan); |
c5a9f9d08 pch_dma: fix kern... |
730 |
spin_unlock_irqrestore(&pd_chan->lock, flags); |
0c42bd0e4 dmaengine: Driver... |
731 732 733 734 735 736 737 |
} static irqreturn_t pd_irq(int irq, void *devid) { struct pch_dma *pd = (struct pch_dma *)devid; struct pch_dma_chan *pd_chan; u32 sts0; |
c3d4913cd pch_dma: fix DMA ... |
738 |
u32 sts2; |
0c42bd0e4 dmaengine: Driver... |
739 |
int i; |
c3d4913cd pch_dma: fix DMA ... |
740 741 |
int ret0 = IRQ_NONE; int ret2 = IRQ_NONE; |
0c42bd0e4 dmaengine: Driver... |
742 743 |
sts0 = dma_readl(pd, STS0); |
c3d4913cd pch_dma: fix DMA ... |
744 |
sts2 = dma_readl(pd, STS2); |
0c42bd0e4 dmaengine: Driver... |
745 746 747 748 749 750 |
dev_dbg(pd->dma.dev, "pd_irq sts0: %x ", sts0); for (i = 0; i < pd->dma.chancnt; i++) { pd_chan = &pd->channels[i]; |
c3d4913cd pch_dma: fix DMA ... |
751 752 753 754 |
if (i < 8) { if (sts0 & DMA_STATUS_IRQ(i)) { if (sts0 & DMA_STATUS0_ERR(i)) set_bit(0, &pd_chan->err_status); |
0c42bd0e4 dmaengine: Driver... |
755 |
|
c3d4913cd pch_dma: fix DMA ... |
756 757 758 759 760 761 762 |
tasklet_schedule(&pd_chan->tasklet); ret0 = IRQ_HANDLED; } } else { if (sts2 & DMA_STATUS_IRQ(i - 8)) { if (sts2 & DMA_STATUS2_ERR(i)) set_bit(0, &pd_chan->err_status); |
0c42bd0e4 dmaengine: Driver... |
763 |
|
c3d4913cd pch_dma: fix DMA ... |
764 765 766 767 |
tasklet_schedule(&pd_chan->tasklet); ret2 = IRQ_HANDLED; } } |
0c42bd0e4 dmaengine: Driver... |
768 769 770 |
} /* clear interrupt bits in status register */ |
c3d4913cd pch_dma: fix DMA ... |
771 772 773 774 |
if (ret0) dma_writel(pd, STS0, sts0); if (ret2) dma_writel(pd, STS2, sts2); |
0c42bd0e4 dmaengine: Driver... |
775 |
|
c3d4913cd pch_dma: fix DMA ... |
776 |
return ret0 | ret2; |
0c42bd0e4 dmaengine: Driver... |
777 |
} |
0b863b333 drivers, pch_dma:... |
778 |
#ifdef CONFIG_PM |
0c42bd0e4 dmaengine: Driver... |
779 780 781 782 783 784 785 786 787 |
static void pch_dma_save_regs(struct pch_dma *pd) { struct pch_dma_chan *pd_chan; struct dma_chan *chan, *_c; int i = 0; pd->regs.dma_ctl0 = dma_readl(pd, CTL0); pd->regs.dma_ctl1 = dma_readl(pd, CTL1); pd->regs.dma_ctl2 = dma_readl(pd, CTL2); |
194f5f270 pch_dma: Support ... |
788 |
pd->regs.dma_ctl3 = dma_readl(pd, CTL3); |
0c42bd0e4 dmaengine: Driver... |
789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 |
list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { pd_chan = to_pd_chan(chan); pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR); pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR); pd->ch_regs[i].size = channel_readl(pd_chan, SIZE); pd->ch_regs[i].next = channel_readl(pd_chan, NEXT); i++; } } static void pch_dma_restore_regs(struct pch_dma *pd) { struct pch_dma_chan *pd_chan; struct dma_chan *chan, *_c; int i = 0; dma_writel(pd, CTL0, pd->regs.dma_ctl0); dma_writel(pd, CTL1, pd->regs.dma_ctl1); dma_writel(pd, CTL2, pd->regs.dma_ctl2); |
194f5f270 pch_dma: Support ... |
811 |
dma_writel(pd, CTL3, pd->regs.dma_ctl3); |
0c42bd0e4 dmaengine: Driver... |
812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 |
list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { pd_chan = to_pd_chan(chan); channel_writel(pd_chan, DEV_ADDR, pd->ch_regs[i].dev_addr); channel_writel(pd_chan, MEM_ADDR, pd->ch_regs[i].mem_addr); channel_writel(pd_chan, SIZE, pd->ch_regs[i].size); channel_writel(pd_chan, NEXT, pd->ch_regs[i].next); i++; } } static int pch_dma_suspend(struct pci_dev *pdev, pm_message_t state) { struct pch_dma *pd = pci_get_drvdata(pdev); if (pd) pch_dma_save_regs(pd); pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); return 0; } static int pch_dma_resume(struct pci_dev *pdev) { struct pch_dma *pd = pci_get_drvdata(pdev); int err; pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); err = pci_enable_device(pdev); if (err) { dev_dbg(&pdev->dev, "failed to enable device "); return err; } if (pd) pch_dma_restore_regs(pd); return 0; } |
0b863b333 drivers, pch_dma:... |
859 |
#endif |
0c42bd0e4 dmaengine: Driver... |
860 861 862 863 864 865 866 867 868 869 870 |
static int __devinit pch_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pch_dma *pd; struct pch_dma_regs *regs; unsigned int nr_channels; int err; int i; nr_channels = id->driver_data; |
01631243d pch_dma: Reduce w... |
871 |
pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
0c42bd0e4 dmaengine: Driver... |
872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 |
if (!pd) return -ENOMEM; pci_set_drvdata(pdev, pd); err = pci_enable_device(pdev); if (err) { dev_err(&pdev->dev, "Cannot enable PCI device "); goto err_free_mem; } if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { dev_err(&pdev->dev, "Cannot find proper base address "); goto err_disable_pdev; } err = pci_request_regions(pdev, DRV_NAME); if (err) { dev_err(&pdev->dev, "Cannot obtain PCI resources "); goto err_disable_pdev; } err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (err) { dev_err(&pdev->dev, "Cannot set proper DMA config "); goto err_free_res; } regs = pd->membase = pci_iomap(pdev, 1, 0); if (!pd->membase) { dev_err(&pdev->dev, "Cannot map MMIO registers "); err = -ENOMEM; goto err_free_res; } pci_set_master(pdev); err = request_irq(pdev->irq, pd_irq, IRQF_SHARED, DRV_NAME, pd); if (err) { dev_err(&pdev->dev, "Failed to request IRQ "); goto err_iounmap; } pd->pool = pci_pool_create("pch_dma_desc_pool", pdev, sizeof(struct pch_dma_desc), 4, 0); if (!pd->pool) { dev_err(&pdev->dev, "Failed to alloc DMA descriptors "); err = -ENOMEM; goto err_free_irq; } pd->dma.dev = &pdev->dev; |
0c42bd0e4 dmaengine: Driver... |
931 932 933 934 935 936 937 938 |
INIT_LIST_HEAD(&pd->dma.channels); for (i = 0; i < nr_channels; i++) { struct pch_dma_chan *pd_chan = &pd->channels[i]; pd_chan->chan.device = &pd->dma; pd_chan->chan.cookie = 1; |
0c42bd0e4 dmaengine: Driver... |
939 940 |
pd_chan->membase = ®s->desc[i]; |
0c42bd0e4 dmaengine: Driver... |
941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 |
spin_lock_init(&pd_chan->lock); INIT_LIST_HEAD(&pd_chan->active_list); INIT_LIST_HEAD(&pd_chan->queue); INIT_LIST_HEAD(&pd_chan->free_list); tasklet_init(&pd_chan->tasklet, pdc_tasklet, (unsigned long)pd_chan); list_add_tail(&pd_chan->chan.device_node, &pd->dma.channels); } dma_cap_zero(pd->dma.cap_mask); dma_cap_set(DMA_PRIVATE, pd->dma.cap_mask); dma_cap_set(DMA_SLAVE, pd->dma.cap_mask); pd->dma.device_alloc_chan_resources = pd_alloc_chan_resources; pd->dma.device_free_chan_resources = pd_free_chan_resources; pd->dma.device_tx_status = pd_tx_status; pd->dma.device_issue_pending = pd_issue_pending; pd->dma.device_prep_slave_sg = pd_prep_slave_sg; pd->dma.device_control = pd_device_control; err = dma_async_device_register(&pd->dma); if (err) { dev_err(&pdev->dev, "Failed to register DMA device "); goto err_free_pool; } return 0; err_free_pool: pci_pool_destroy(pd->pool); err_free_irq: free_irq(pdev->irq, pd); err_iounmap: pci_iounmap(pdev, pd->membase); err_free_res: pci_release_regions(pdev); err_disable_pdev: pci_disable_device(pdev); err_free_mem: return err; } static void __devexit pch_dma_remove(struct pci_dev *pdev) { struct pch_dma *pd = pci_get_drvdata(pdev); struct pch_dma_chan *pd_chan; struct dma_chan *chan, *_c; if (pd) { dma_async_device_unregister(&pd->dma); list_for_each_entry_safe(chan, _c, &pd->dma.channels, device_node) { pd_chan = to_pd_chan(chan); tasklet_disable(&pd_chan->tasklet); tasklet_kill(&pd_chan->tasklet); } pci_pool_destroy(pd->pool); free_irq(pdev->irq, pd); pci_iounmap(pdev, pd->membase); pci_release_regions(pdev); pci_disable_device(pdev); kfree(pd); } } /* PCI Device ID of DMA device */ |
2cdf2455a pch_dma: support ... |
1013 1014 1015 1016 1017 1018 |
#define PCI_VENDOR_ID_ROHM 0x10DB #define PCI_DEVICE_ID_EG20T_PCH_DMA_8CH 0x8810 #define PCI_DEVICE_ID_EG20T_PCH_DMA_4CH 0x8815 #define PCI_DEVICE_ID_ML7213_DMA1_8CH 0x8026 #define PCI_DEVICE_ID_ML7213_DMA2_8CH 0x802B #define PCI_DEVICE_ID_ML7213_DMA3_4CH 0x8034 |
194f5f270 pch_dma: Support ... |
1019 |
#define PCI_DEVICE_ID_ML7213_DMA4_12CH 0x8032 |
c0dfc04ac pch_dma: Support ... |
1020 1021 1022 1023 |
#define PCI_DEVICE_ID_ML7223_DMA1_4CH 0x800B #define PCI_DEVICE_ID_ML7223_DMA2_4CH 0x800E #define PCI_DEVICE_ID_ML7223_DMA3_4CH 0x8017 #define PCI_DEVICE_ID_ML7223_DMA4_4CH 0x803B |
0c42bd0e4 dmaengine: Driver... |
1024 |
|
eb8590b50 pch_dma: modify p... |
1025 |
DEFINE_PCI_DEVICE_TABLE(pch_dma_id_table) = { |
2cdf2455a pch_dma: support ... |
1026 1027 1028 1029 1030 |
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_8CH), 8 }, { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_EG20T_PCH_DMA_4CH), 4 }, { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA1_8CH), 8}, /* UART Video */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA2_8CH), 8}, /* PCMIF SPI */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA3_4CH), 4}, /* FPGA */ |
194f5f270 pch_dma: Support ... |
1031 |
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_DMA4_12CH), 12}, /* I2S */ |
c0dfc04ac pch_dma: Support ... |
1032 1033 1034 1035 |
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA1_4CH), 4}, /* UART */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA2_4CH), 4}, /* Video SPI */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA3_4CH), 4}, /* Security */ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_DMA4_4CH), 4}, /* FPGA */ |
87acf5ad8 NULL-terminate al... |
1036 |
{ 0, }, |
0c42bd0e4 dmaengine: Driver... |
1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 |
}; static struct pci_driver pch_dma_driver = { .name = DRV_NAME, .id_table = pch_dma_id_table, .probe = pch_dma_probe, .remove = __devexit_p(pch_dma_remove), #ifdef CONFIG_PM .suspend = pch_dma_suspend, .resume = pch_dma_resume, #endif }; static int __init pch_dma_init(void) { return pci_register_driver(&pch_dma_driver); } static void __exit pch_dma_exit(void) { pci_unregister_driver(&pch_dma_driver); } module_init(pch_dma_init); module_exit(pch_dma_exit); |
2cdf2455a pch_dma: support ... |
1062 1063 |
MODULE_DESCRIPTION("Intel EG20T PCH / OKI SEMICONDUCTOR ML7213 IOH " "DMA controller driver"); |
0c42bd0e4 dmaengine: Driver... |
1064 1065 |
MODULE_AUTHOR("Yong Wang <yong.y.wang@intel.com>"); MODULE_LICENSE("GPL v2"); |