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drivers/rtc/rtc-bfin.c
12.8 KB
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/* * Blackfin On-Chip Real Time Clock Driver |
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* Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x |
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* |
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* Copyright 2004-2010 Analog Devices Inc. |
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* * Enter bugs at http://blackfin.uclinux.org/ * * Licensed under the GPL-2 or later. */ /* The biggest issue we deal with in this driver is that register writes are * synced to the RTC frequency of 1Hz. So if you write to a register and * attempt to write again before the first write has completed, the new write * is simply discarded. This can easily be troublesome if userspace disables * one event (say periodic) and then right after enables an event (say alarm). * Since all events are maintained in the same interrupt mask register, if * we wrote to it to disable the first event and then wrote to it again to * enable the second event, that second event would not be enabled as the * write would be discarded and things quickly fall apart. * * To keep this delay from significantly degrading performance (we, in theory, |
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* would have to sleep for up to 1 second every time we wanted to write a |
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* register), we only check the write pending status before we start to issue |
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* a new write. We bank on the idea that it doesn't matter when the sync |
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* happens so long as we don't attempt another write before it does. The only * time userspace would take this penalty is when they try and do multiple * operations right after another ... but in this case, they need to take the * sync penalty, so we should be OK. * * Also note that the RTC_ISTAT register does not suffer this penalty; its * writes to clear status registers complete immediately. */ |
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/* It may seem odd that there is no SWCNT code in here (which would be exposed * via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral * runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ * (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs. * The same exact behavior can be accomplished by using the update interrupt * event (UIE). Maybe down the line the RTC peripheral will suck less in which * case we can re-introduce PIE support. */ |
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#include <linux/bcd.h> |
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#include <linux/completion.h> #include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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#include <linux/seq_file.h> |
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#include <linux/slab.h> |
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#include <asm/blackfin.h> |
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#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am ", __func__, __LINE__) |
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struct bfin_rtc { struct rtc_device *rtc_dev; struct rtc_time rtc_alarm; |
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u16 rtc_wrote_regs; |
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}; /* Bit values for the ISTAT / ICTL registers */ #define RTC_ISTAT_WRITE_COMPLETE 0x8000 #define RTC_ISTAT_WRITE_PENDING 0x4000 #define RTC_ISTAT_ALARM_DAY 0x0040 #define RTC_ISTAT_24HR 0x0020 #define RTC_ISTAT_HOUR 0x0010 #define RTC_ISTAT_MIN 0x0008 #define RTC_ISTAT_SEC 0x0004 #define RTC_ISTAT_ALARM 0x0002 #define RTC_ISTAT_STOPWATCH 0x0001 /* Shift values for RTC_STAT register */ #define DAY_BITS_OFF 17 #define HOUR_BITS_OFF 12 #define MIN_BITS_OFF 6 #define SEC_BITS_OFF 0 /* Some helper functions to convert between the common RTC notion of time |
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* and the internal Blackfin notion that is encoded in 32bits. |
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*/ static inline u32 rtc_time_to_bfin(unsigned long now) { u32 sec = (now % 60); u32 min = (now % (60 * 60)) / 60; u32 hour = (now % (60 * 60 * 24)) / (60 * 60); u32 days = (now / (60 * 60 * 24)); return (sec << SEC_BITS_OFF) + (min << MIN_BITS_OFF) + (hour << HOUR_BITS_OFF) + (days << DAY_BITS_OFF); } static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin) { return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) + (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) + (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) + (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24); } static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm) { rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm); } |
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/** * bfin_rtc_sync_pending - make sure pending writes have complete * * Wait for the previous write to a RTC register to complete. |
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* Unfortunately, we can't sleep here as that introduces a race condition when * turning on interrupt events. Consider this: * - process sets alarm * - process enables alarm * - process sleeps while waiting for rtc write to sync * - interrupt fires while process is sleeping * - interrupt acks the event by writing to ISTAT * - interrupt sets the WRITE PENDING bit * - interrupt handler finishes * - process wakes up, sees WRITE PENDING bit set, goes to sleep * - interrupt fires while process is sleeping * If anyone can point out the obvious solution here, i'm listening :). This * shouldn't be an issue on an SMP or preempt system as this function should * only be called with the rtc lock held. |
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* * Other options: * - disable PREN so the sync happens at 32.768kHZ ... but this changes the * inc rate for all RTC registers from 1HZ to 32.768kHZ ... * - use the write complete IRQ |
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*/ |
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/* static void bfin_rtc_sync_pending_polled(void) |
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{ |
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while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE)) |
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if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)) break; |
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bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE); } |
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*/ static DECLARE_COMPLETION(bfin_write_complete); static void bfin_rtc_sync_pending(struct device *dev) { dev_dbg_stamp(dev); while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) wait_for_completion_timeout(&bfin_write_complete, HZ * 5); dev_dbg_stamp(dev); } |
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|
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/** * bfin_rtc_reset - set RTC to sane/known state * * Initialize the RTC. Enable pre-scaler to scale RTC clock * to 1Hz and clear interrupt/status registers. */ |
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static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl) |
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{ |
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struct bfin_rtc *rtc = dev_get_drvdata(dev); |
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dev_dbg_stamp(dev); bfin_rtc_sync_pending(dev); |
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bfin_write_RTC_PREN(0x1); |
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bfin_write_RTC_ICTL(rtc_ictl); |
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bfin_write_RTC_ALARM(0); bfin_write_RTC_ISTAT(0xFFFF); |
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rtc->rtc_wrote_regs = 0; |
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} |
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/** * bfin_rtc_interrupt - handle interrupt from RTC * * Since we handle all RTC events here, we have to make sure the requested * interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT) * always gets updated regardless of the interrupt being enabled. So when one * even we care about (e.g. stopwatch) goes off, we don't want to turn around * and say that other events have happened as well (e.g. second). We do not * have to worry about pending writes to the RTC_ICTL register as interrupts * only fire if they are enabled in the RTC_ICTL register. */ |
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static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id) { |
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struct device *dev = dev_id; struct bfin_rtc *rtc = dev_get_drvdata(dev); |
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unsigned long events = 0; |
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bool write_complete = false; |
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u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits; |
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dev_dbg_stamp(dev); |
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|
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rtc_istat = bfin_read_RTC_ISTAT(); |
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rtc_ictl = bfin_read_RTC_ICTL(); |
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rtc_istat_clear = 0; |
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|
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bits = RTC_ISTAT_WRITE_COMPLETE; if (rtc_istat & bits) { rtc_istat_clear |= bits; |
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write_complete = true; complete(&bfin_write_complete); |
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} |
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bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY); if (rtc_ictl & bits) { if (rtc_istat & bits) { rtc_istat_clear |= bits; |
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events |= RTC_AF | RTC_IRQF; } |
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} |
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bits = RTC_ISTAT_SEC; if (rtc_ictl & bits) { if (rtc_istat & bits) { rtc_istat_clear |= bits; |
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events |= RTC_UF | RTC_IRQF; } } |
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|
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if (events) rtc_update_irq(rtc->rtc_dev, 1, events); |
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|
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if (write_complete || events) { bfin_write_RTC_ISTAT(rtc_istat_clear); |
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return IRQ_HANDLED; |
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} else |
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return IRQ_NONE; |
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} |
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static void bfin_rtc_int_set(u16 rtc_int) |
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{ bfin_write_RTC_ISTAT(rtc_int); bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int); } |
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static void bfin_rtc_int_clear(u16 rtc_int) |
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{ bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int); } static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc) { /* Blackfin has different bits for whether the alarm is * more than 24 hours away. */ |
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bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY); |
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} |
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static int bfin_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) { struct bfin_rtc *rtc = dev_get_drvdata(dev); dev_dbg_stamp(dev); if (enabled) bfin_rtc_int_set_alarm(rtc); else bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); |
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return 0; |
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} |
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static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm) { struct bfin_rtc *rtc = dev_get_drvdata(dev); |
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dev_dbg_stamp(dev); |
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|
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if (rtc->rtc_wrote_regs & 0x1) bfin_rtc_sync_pending(dev); |
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rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm); |
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return 0; } static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm) { struct bfin_rtc *rtc = dev_get_drvdata(dev); int ret; unsigned long now; |
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dev_dbg_stamp(dev); |
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|
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ret = rtc_tm_to_time(tm, &now); if (ret == 0) { |
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if (rtc->rtc_wrote_regs & 0x1) bfin_rtc_sync_pending(dev); |
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bfin_write_RTC_STAT(rtc_time_to_bfin(now)); |
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rtc->rtc_wrote_regs = 0x1; |
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} |
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return ret; } static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) { struct bfin_rtc *rtc = dev_get_drvdata(dev); |
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dev_dbg_stamp(dev); |
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alrm->time = rtc->rtc_alarm; |
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bfin_rtc_sync_pending(dev); |
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alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)); |
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return 0; } static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) { struct bfin_rtc *rtc = dev_get_drvdata(dev); |
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unsigned long rtc_alarm; |
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dev_dbg_stamp(dev); |
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if (rtc_tm_to_time(&alrm->time, &rtc_alarm)) return -EINVAL; |
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rtc->rtc_alarm = alrm->time; |
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bfin_rtc_sync_pending(dev); bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm)); if (alrm->enabled) bfin_rtc_int_set_alarm(rtc); |
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return 0; } static int bfin_rtc_proc(struct device *dev, struct seq_file *seq) { |
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#define yesno(x) ((x) ? "yes" : "no") |
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u16 ictl = bfin_read_RTC_ICTL(); |
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dev_dbg_stamp(dev); |
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seq_printf(seq, "alarm_IRQ\t: %s " "wkalarm_IRQ\t: %s " |
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"seconds_IRQ\t: %s ", |
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yesno(ictl & RTC_ISTAT_ALARM), yesno(ictl & RTC_ISTAT_ALARM_DAY), |
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yesno(ictl & RTC_ISTAT_SEC)); |
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return 0; |
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#undef yesno |
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} |
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static struct rtc_class_ops bfin_rtc_ops = { |
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.read_time = bfin_rtc_read_time, .set_time = bfin_rtc_set_time, .read_alarm = bfin_rtc_read_alarm, .set_alarm = bfin_rtc_set_alarm, .proc = bfin_rtc_proc, |
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.alarm_irq_enable = bfin_rtc_alarm_irq_enable, |
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}; |
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static int bfin_rtc_probe(struct platform_device *pdev) |
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{ struct bfin_rtc *rtc; |
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struct device *dev = &pdev->dev; |
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int ret; |
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unsigned long timeout = jiffies + HZ; |
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dev_dbg_stamp(dev); |
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/* Allocate memory for our RTC struct */ |
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rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL); |
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if (unlikely(!rtc)) return -ENOMEM; |
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platform_set_drvdata(pdev, rtc); |
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device_init_wakeup(dev, 1); |
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|
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/* Register our RTC with the RTC framework */ |
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rtc->rtc_dev = devm_rtc_device_register(dev, pdev->name, &bfin_rtc_ops, |
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THIS_MODULE); |
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if (IS_ERR(rtc->rtc_dev)) |
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return PTR_ERR(rtc->rtc_dev); |
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|
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/* Grab the IRQ and init the hardware */ |
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ret = devm_request_irq(dev, IRQ_RTC, bfin_rtc_interrupt, 0, pdev->name, dev); |
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if (unlikely(ret)) |
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dev_err(&pdev->dev, "unable to request IRQ; alarm won't work, " "and writes will be delayed "); |
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/* sometimes the bootloader touched things, but the write complete was not * enabled, so let's just do a quick timeout here since the IRQ will not fire ... */ |
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while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING) if (time_after(jiffies, timeout)) break; |
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bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE); |
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bfin_write_RTC_SWCNT(0); |
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|
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return 0; |
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} |
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static int bfin_rtc_remove(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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bfin_rtc_reset(dev, 0); |
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return 0; } |
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#ifdef CONFIG_PM_SLEEP static int bfin_rtc_suspend(struct device *dev) |
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{ |
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dev_dbg_stamp(dev); if (device_may_wakeup(dev)) { |
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enable_irq_wake(IRQ_RTC); |
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bfin_rtc_sync_pending(dev); |
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} else |
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bfin_rtc_int_clear(0); |
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|
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return 0; } |
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static int bfin_rtc_resume(struct device *dev) |
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{ |
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dev_dbg_stamp(dev); if (device_may_wakeup(dev)) |
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disable_irq_wake(IRQ_RTC); |
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/* * Since only some of the RTC bits are maintained externally in the * Vbat domain, we need to wait for the RTC MMRs to be synced into * the core after waking up. This happens every RTC 1HZ. Once that * has happened, we can go ahead and re-enable the important write * complete interrupt event. */ while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC)) continue; bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE); |
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|
5aeb776d0 blackfin RTC driv... |
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return 0; } #endif |
b4df8f6ca rtc: rtc-bfin: co... |
414 |
static SIMPLE_DEV_PM_OPS(bfin_rtc_pm_ops, bfin_rtc_suspend, bfin_rtc_resume); |
8cc75c9a1 Blackfin: on-chip... |
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static struct platform_driver bfin_rtc_driver = { .driver = { .name = "rtc-bfin", |
b4df8f6ca rtc: rtc-bfin: co... |
418 |
.pm = &bfin_rtc_pm_ops, |
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419 420 |
}, .probe = bfin_rtc_probe, |
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421 |
.remove = bfin_rtc_remove, |
8cc75c9a1 Blackfin: on-chip... |
422 |
}; |
0c4eae665 rtc: convert driv... |
423 |
module_platform_driver(bfin_rtc_driver); |
8cc75c9a1 Blackfin: on-chip... |
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MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver"); MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>"); MODULE_LICENSE("GPL"); |
ad28a07bc rtc: fix platform... |
428 |
MODULE_ALIAS("platform:rtc-bfin"); |