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drivers/ata/pata_bf54x.c
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/* * File: drivers/ata/pata_bf54x.c * Author: Sonic Zhang <sonic.zhang@analog.com> * * Created: * Description: PATA Driver for blackfin 54x * * Modified: * Copyright 2007 Analog Devices Inc. * * Bugs: Enter bugs at http://blackfin.uclinux.org/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see the file COPYING, or write * to the Free Software Foundation, Inc., * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/init.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <linux/device.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #include <linux/platform_device.h> #include <asm/dma.h> #include <asm/gpio.h> #include <asm/portmux.h> #define DRV_NAME "pata-bf54x" #define DRV_VERSION "0.9" #define ATA_REG_CTRL 0x0E #define ATA_REG_ALTSTATUS ATA_REG_CTRL /* These are the offset of the controller's registers */ #define ATAPI_OFFSET_CONTROL 0x00 #define ATAPI_OFFSET_STATUS 0x04 #define ATAPI_OFFSET_DEV_ADDR 0x08 #define ATAPI_OFFSET_DEV_TXBUF 0x0c #define ATAPI_OFFSET_DEV_RXBUF 0x10 #define ATAPI_OFFSET_INT_MASK 0x14 #define ATAPI_OFFSET_INT_STATUS 0x18 #define ATAPI_OFFSET_XFER_LEN 0x1c #define ATAPI_OFFSET_LINE_STATUS 0x20 #define ATAPI_OFFSET_SM_STATE 0x24 #define ATAPI_OFFSET_TERMINATE 0x28 #define ATAPI_OFFSET_PIO_TFRCNT 0x2c #define ATAPI_OFFSET_DMA_TFRCNT 0x30 #define ATAPI_OFFSET_UMAIN_TFRCNT 0x34 #define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38 #define ATAPI_OFFSET_REG_TIM_0 0x40 #define ATAPI_OFFSET_PIO_TIM_0 0x44 #define ATAPI_OFFSET_PIO_TIM_1 0x48 #define ATAPI_OFFSET_MULTI_TIM_0 0x50 #define ATAPI_OFFSET_MULTI_TIM_1 0x54 #define ATAPI_OFFSET_MULTI_TIM_2 0x58 #define ATAPI_OFFSET_ULTRA_TIM_0 0x60 #define ATAPI_OFFSET_ULTRA_TIM_1 0x64 #define ATAPI_OFFSET_ULTRA_TIM_2 0x68 #define ATAPI_OFFSET_ULTRA_TIM_3 0x6c #define ATAPI_GET_CONTROL(base)\ bfin_read16(base + ATAPI_OFFSET_CONTROL) #define ATAPI_SET_CONTROL(base, val)\ bfin_write16(base + ATAPI_OFFSET_CONTROL, val) #define ATAPI_GET_STATUS(base)\ bfin_read16(base + ATAPI_OFFSET_STATUS) #define ATAPI_GET_DEV_ADDR(base)\ bfin_read16(base + ATAPI_OFFSET_DEV_ADDR) #define ATAPI_SET_DEV_ADDR(base, val)\ bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val) #define ATAPI_GET_DEV_TXBUF(base)\ bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF) #define ATAPI_SET_DEV_TXBUF(base, val)\ bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val) #define ATAPI_GET_DEV_RXBUF(base)\ bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF) #define ATAPI_SET_DEV_RXBUF(base, val)\ bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val) #define ATAPI_GET_INT_MASK(base)\ bfin_read16(base + ATAPI_OFFSET_INT_MASK) #define ATAPI_SET_INT_MASK(base, val)\ bfin_write16(base + ATAPI_OFFSET_INT_MASK, val) #define ATAPI_GET_INT_STATUS(base)\ bfin_read16(base + ATAPI_OFFSET_INT_STATUS) #define ATAPI_SET_INT_STATUS(base, val)\ bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val) #define ATAPI_GET_XFER_LEN(base)\ bfin_read16(base + ATAPI_OFFSET_XFER_LEN) #define ATAPI_SET_XFER_LEN(base, val)\ bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val) #define ATAPI_GET_LINE_STATUS(base)\ bfin_read16(base + ATAPI_OFFSET_LINE_STATUS) #define ATAPI_GET_SM_STATE(base)\ bfin_read16(base + ATAPI_OFFSET_SM_STATE) #define ATAPI_GET_TERMINATE(base)\ bfin_read16(base + ATAPI_OFFSET_TERMINATE) #define ATAPI_SET_TERMINATE(base, val)\ bfin_write16(base + ATAPI_OFFSET_TERMINATE, val) #define ATAPI_GET_PIO_TFRCNT(base)\ bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT) #define ATAPI_GET_DMA_TFRCNT(base)\ bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT) #define ATAPI_GET_UMAIN_TFRCNT(base)\ bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT) #define ATAPI_GET_UDMAOUT_TFRCNT(base)\ bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT) #define ATAPI_GET_REG_TIM_0(base)\ bfin_read16(base + ATAPI_OFFSET_REG_TIM_0) #define ATAPI_SET_REG_TIM_0(base, val)\ bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val) #define ATAPI_GET_PIO_TIM_0(base)\ bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0) #define ATAPI_SET_PIO_TIM_0(base, val)\ bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val) #define ATAPI_GET_PIO_TIM_1(base)\ bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1) #define ATAPI_SET_PIO_TIM_1(base, val)\ bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val) #define ATAPI_GET_MULTI_TIM_0(base)\ bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0) #define ATAPI_SET_MULTI_TIM_0(base, val)\ bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val) #define ATAPI_GET_MULTI_TIM_1(base)\ bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1) #define ATAPI_SET_MULTI_TIM_1(base, val)\ bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val) #define ATAPI_GET_MULTI_TIM_2(base)\ bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2) #define ATAPI_SET_MULTI_TIM_2(base, val)\ bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val) #define ATAPI_GET_ULTRA_TIM_0(base)\ bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0) #define ATAPI_SET_ULTRA_TIM_0(base, val)\ bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val) #define ATAPI_GET_ULTRA_TIM_1(base)\ bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1) #define ATAPI_SET_ULTRA_TIM_1(base, val)\ bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val) #define ATAPI_GET_ULTRA_TIM_2(base)\ bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2) #define ATAPI_SET_ULTRA_TIM_2(base, val)\ bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val) #define ATAPI_GET_ULTRA_TIM_3(base)\ bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3) #define ATAPI_SET_ULTRA_TIM_3(base, val)\ bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val) /** * PIO Mode - Frequency compatibility */ /* mode: 0 1 2 3 4 */ static const u32 pio_fsclk[] = { 33333333, 33333333, 33333333, 33333333, 33333333 }; /** * MDMA Mode - Frequency compatibility */ /* mode: 0 1 2 */ static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 }; /** * UDMA Mode - Frequency compatibility * * UDMA5 - 100 MB/s - SCLK = 133 MHz * UDMA4 - 66 MB/s - SCLK >= 80 MHz * UDMA3 - 44.4 MB/s - SCLK >= 50 MHz * UDMA2 - 33 MB/s - SCLK >= 40 MHz */ /* mode: 0 1 2 3 4 5 */ static const u32 udma_fsclk[] = { 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 }; /** * Register transfer timing table */ /* mode: 0 1 2 3 4 */ /* Cycle Time */ static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 }; /* DIOR/DIOW to end cycle */ static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 }; /* DIOR/DIOW asserted pulse width */ static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 }; /** * PIO timing table */ /* mode: 0 1 2 3 4 */ /* Cycle Time */ static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 }; /* Address valid to DIOR/DIORW */ static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 }; /* DIOR/DIOW to end cycle */ static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 }; /* DIOR/DIOW asserted pulse width */ static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 }; /* DIOW data hold */ static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 }; /* ****************************************************************** * Multiword DMA timing table * ****************************************************************** */ /* mode: 0 1 2 */ /* Cycle Time */ static const u32 mdma_t0min[] = { 480, 150, 120 }; /* DIOR/DIOW asserted pulse width */ static const u32 mdma_tdmin[] = { 215, 80, 70 }; /* DMACK to read data released */ static const u32 mdma_thmin[] = { 20, 15, 10 }; /* DIOR/DIOW to DMACK hold */ static const u32 mdma_tjmin[] = { 20, 5, 5 }; /* DIOR negated pulse width */ static const u32 mdma_tkrmin[] = { 50, 50, 25 }; /* DIOR negated pulse width */ static const u32 mdma_tkwmin[] = { 215, 50, 25 }; /* CS[1:0] valid to DIOR/DIOW */ static const u32 mdma_tmmin[] = { 50, 30, 25 }; /* DMACK to read data released */ static const u32 mdma_tzmax[] = { 20, 25, 25 }; /** * Ultra DMA timing table */ /* mode: 0 1 2 3 4 5 */ static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 }; static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 }; static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 }; static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 }; static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 }; static const u32 udma_tmlimin = 20; static const u32 udma_tzahmin = 20; static const u32 udma_tenvmin = 20; static const u32 udma_tackmin = 20; static const u32 udma_tssmin = 50; |
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#define BFIN_MAX_SG_SEGMENTS 4 |
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/** * * Function: num_clocks_min * * Description: * calculate number of SCLK cycles to meet minimum timing */ static unsigned short num_clocks_min(unsigned long tmin, unsigned long fsclk) { unsigned long tmp ; unsigned short result; tmp = tmin * (fsclk/1000/1000) / 1000; result = (unsigned short)tmp; if ((tmp*1000*1000) < (tmin*(fsclk/1000))) { result++; } return result; } /** * bfin_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: um * * Set PIO mode for device. * * LOCKING: * None (inherited from caller). */ static void bfin_set_piomode(struct ata_port *ap, struct ata_device *adev) { int mode = adev->pio_mode - XFER_PIO_0; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; unsigned int fsclk = get_sclk(); unsigned short teoc_reg, t2_reg, teoc_pio; unsigned short t4_reg, t2_pio, t1_reg; unsigned short n0, n6, t6min = 5; /* the most restrictive timing value is t6 and tc, the DIOW - data hold * If one SCLK pulse is longer than this minimum value then register * transfers cannot be supported at this frequency. */ n6 = num_clocks_min(t6min, fsclk); if (mode >= 0 && mode <= 4 && n6 >= 1) { |
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dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud ", mode, fsclk); |
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/* calculate the timing values for register transfers. */ while (mode > 0 && pio_fsclk[mode] > fsclk) mode--; /* DIOR/DIOW to end cycle time */ t2_reg = num_clocks_min(reg_t2min[mode], fsclk); /* DIOR/DIOW asserted pulse width */ teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk); /* Cycle Time */ n0 = num_clocks_min(reg_t0min[mode], fsclk); /* increase t2 until we meed the minimum cycle length */ if (t2_reg + teoc_reg < n0) t2_reg = n0 - teoc_reg; /* calculate the timing values for pio transfers. */ /* DIOR/DIOW to end cycle time */ t2_pio = num_clocks_min(pio_t2min[mode], fsclk); /* DIOR/DIOW asserted pulse width */ teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk); /* Cycle Time */ n0 = num_clocks_min(pio_t0min[mode], fsclk); /* increase t2 until we meed the minimum cycle length */ if (t2_pio + teoc_pio < n0) t2_pio = n0 - teoc_pio; /* Address valid to DIOR/DIORW */ t1_reg = num_clocks_min(pio_t1min[mode], fsclk); /* DIOW data hold */ t4_reg = num_clocks_min(pio_t4min[mode], fsclk); ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg)); ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg)); ATAPI_SET_PIO_TIM_1(base, teoc_pio); if (mode > 2) { ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | IORDY_EN); } else { ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~IORDY_EN); } /* Disable host ATAPI PIO interrupts */ ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base) & ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK)); SSYNC(); } } /** * bfin_set_dmamode - Initialize host controller PATA DMA timings * @ap: Port whose timings we are configuring * @adev: um |
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* * Set UDMA mode for device. * * LOCKING: * None (inherited from caller). */ static void bfin_set_dmamode(struct ata_port *ap, struct ata_device *adev) { int mode; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; unsigned long fsclk = get_sclk(); unsigned short tenv, tack, tcyc_tdvs, tdvs, tmli, tss, trp, tzah; unsigned short tm, td, tkr, tkw, teoc, th; unsigned short n0, nf, tfmin = 5; unsigned short nmin, tcyc; mode = adev->dma_mode - XFER_UDMA_0; if (mode >= 0 && mode <= 5) { |
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dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d ", mode); |
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/* the most restrictive timing value is t6 and tc, * the DIOW - data hold. If one SCLK pulse is longer * than this minimum value then register * transfers cannot be supported at this frequency. */ while (mode > 0 && udma_fsclk[mode] > fsclk) mode--; nmin = num_clocks_min(udma_tmin[mode], fsclk); if (nmin >= 1) { /* calculate the timing values for Ultra DMA. */ tdvs = num_clocks_min(udma_tdvsmin[mode], fsclk); tcyc = num_clocks_min(udma_tcycmin[mode], fsclk); tcyc_tdvs = 2; /* increase tcyc - tdvs (tcyc_tdvs) until we meed * the minimum cycle length */ if (tdvs + tcyc_tdvs < tcyc) tcyc_tdvs = tcyc - tdvs; /* Mow assign the values required for the timing * registers */ if (tcyc_tdvs < 2) tcyc_tdvs = 2; if (tdvs < 2) tdvs = 2; tack = num_clocks_min(udma_tackmin, fsclk); tss = num_clocks_min(udma_tssmin, fsclk); tmli = num_clocks_min(udma_tmlimin, fsclk); tzah = num_clocks_min(udma_tzahmin, fsclk); trp = num_clocks_min(udma_trpmin[mode], fsclk); tenv = num_clocks_min(udma_tenvmin, fsclk); if (tenv <= udma_tenvmax[mode]) { ATAPI_SET_ULTRA_TIM_0(base, (tenv<<8 | tack)); ATAPI_SET_ULTRA_TIM_1(base, (tcyc_tdvs<<8 | tdvs)); ATAPI_SET_ULTRA_TIM_2(base, (tmli<<8 | tss)); ATAPI_SET_ULTRA_TIM_3(base, (trp<<8 | tzah)); |
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} } } mode = adev->dma_mode - XFER_MW_DMA_0; if (mode >= 0 && mode <= 2) { |
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dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d ", mode); |
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/* the most restrictive timing value is tf, the DMACK to * read data released. If one SCLK pulse is longer than * this maximum value then the MDMA mode * cannot be supported at this frequency. */ while (mode > 0 && mdma_fsclk[mode] > fsclk) mode--; nf = num_clocks_min(tfmin, fsclk); if (nf >= 1) { /* calculate the timing values for Multi-word DMA. */ /* DIOR/DIOW asserted pulse width */ td = num_clocks_min(mdma_tdmin[mode], fsclk); /* DIOR negated pulse width */ tkw = num_clocks_min(mdma_tkwmin[mode], fsclk); /* Cycle Time */ n0 = num_clocks_min(mdma_t0min[mode], fsclk); /* increase tk until we meed the minimum cycle length */ if (tkw + td < n0) tkw = n0 - td; /* DIOR negated pulse width - read */ tkr = num_clocks_min(mdma_tkrmin[mode], fsclk); /* CS{1:0] valid to DIOR/DIOW */ tm = num_clocks_min(mdma_tmmin[mode], fsclk); /* DIOR/DIOW to DMACK hold */ teoc = num_clocks_min(mdma_tjmin[mode], fsclk); /* DIOW Data hold */ th = num_clocks_min(mdma_thmin[mode], fsclk); ATAPI_SET_MULTI_TIM_0(base, (tm<<8 | td)); ATAPI_SET_MULTI_TIM_1(base, (tkr<<8 | tkw)); ATAPI_SET_MULTI_TIM_2(base, (teoc<<8 | th)); |
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SSYNC(); } } return; } /** * * Function: wait_complete * * Description: Waits the interrupt from device * */ static inline void wait_complete(void __iomem *base, unsigned short mask) { unsigned short status; unsigned int i = 0; #define PATA_BF54X_WAIT_TIMEOUT 10000 for (i = 0; i < PATA_BF54X_WAIT_TIMEOUT; i++) { status = ATAPI_GET_INT_STATUS(base) & mask; if (status) break; } ATAPI_SET_INT_STATUS(base, mask); } /** * * Function: write_atapi_register * * Description: Writes to ATA Device Resgister * */ static void write_atapi_register(void __iomem *base, unsigned long ata_reg, unsigned short value) { /* Program the ATA_DEV_TXBUF register with write data (to be * written into the device). */ ATAPI_SET_DEV_TXBUF(base, value); /* Program the ATA_DEV_ADDR register with address of the * device register (0x01 to 0x0F). */ ATAPI_SET_DEV_ADDR(base, ata_reg); /* Program the ATA_CTRL register with dir set to write (1) */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); /* ensure PIO DMA is not set */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); /* and start the transfer */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); /* Wait for the interrupt to indicate the end of the transfer. * (We need to wait on and clear rhe ATA_DEV_INT interrupt status) */ wait_complete(base, PIO_DONE_INT); } /** * * Function: read_atapi_register * *Description: Reads from ATA Device Resgister * */ static unsigned short read_atapi_register(void __iomem *base, unsigned long ata_reg) { /* Program the ATA_DEV_ADDR register with address of the * device register (0x01 to 0x0F). */ ATAPI_SET_DEV_ADDR(base, ata_reg); /* Program the ATA_CTRL register with dir set to read (0) and */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); /* ensure PIO DMA is not set */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); /* and start the transfer */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); /* Wait for the interrupt to indicate the end of the transfer. * (PIO_DONE interrupt is set and it doesn't seem to matter * that we don't clear it) */ wait_complete(base, PIO_DONE_INT); /* Read the ATA_DEV_RXBUF register with write data (to be * written into the device). */ return ATAPI_GET_DEV_RXBUF(base); } /** * * Function: write_atapi_register_data * * Description: Writes to ATA Device Resgister * */ static void write_atapi_data(void __iomem *base, int len, unsigned short *buf) { int i; /* Set transfer length to 1 */ ATAPI_SET_XFER_LEN(base, 1); /* Program the ATA_DEV_ADDR register with address of the * ATA_REG_DATA */ ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); /* Program the ATA_CTRL register with dir set to write (1) */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); /* ensure PIO DMA is not set */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); for (i = 0; i < len; i++) { /* Program the ATA_DEV_TXBUF register with write data (to be * written into the device). */ ATAPI_SET_DEV_TXBUF(base, buf[i]); /* and start the transfer */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); /* Wait for the interrupt to indicate the end of the transfer. * (We need to wait on and clear rhe ATA_DEV_INT * interrupt status) */ wait_complete(base, PIO_DONE_INT); } } /** * * Function: read_atapi_register_data * * Description: Reads from ATA Device Resgister * */ static void read_atapi_data(void __iomem *base, int len, unsigned short *buf) { int i; /* Set transfer length to 1 */ ATAPI_SET_XFER_LEN(base, 1); /* Program the ATA_DEV_ADDR register with address of the * ATA_REG_DATA */ ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA); /* Program the ATA_CTRL register with dir set to read (0) and */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); /* ensure PIO DMA is not set */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA)); for (i = 0; i < len; i++) { /* and start the transfer */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START)); /* Wait for the interrupt to indicate the end of the transfer. * (PIO_DONE interrupt is set and it doesn't seem to matter * that we don't clear it) */ wait_complete(base, PIO_DONE_INT); /* Read the ATA_DEV_RXBUF register with write data (to be * written into the device). */ buf[i] = ATAPI_GET_DEV_RXBUF(base); } } /** * bfin_tf_load - send taskfile registers to host controller * @ap: Port to which output is sent * @tf: ATA taskfile register set * |
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* Note: Original code is ata_sff_tf_load(). |
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*/ static void bfin_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; if (tf->ctl != ap->last_ctl) { write_atapi_register(base, ATA_REG_CTRL, tf->ctl); ap->last_ctl = tf->ctl; ata_wait_idle(ap); } if (is_addr) { if (tf->flags & ATA_TFLAG_LBA48) { write_atapi_register(base, ATA_REG_FEATURE, tf->hob_feature); write_atapi_register(base, ATA_REG_NSECT, tf->hob_nsect); write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal); write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam); write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah); |
f92041125 Blackfin pata-bf5... |
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dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X " |
d830d1731 libata driver for... |
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"0x%X 0x%X ", tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam, tf->hob_lbah); } write_atapi_register(base, ATA_REG_FEATURE, tf->feature); write_atapi_register(base, ATA_REG_NSECT, tf->nsect); write_atapi_register(base, ATA_REG_LBAL, tf->lbal); write_atapi_register(base, ATA_REG_LBAM, tf->lbam); write_atapi_register(base, ATA_REG_LBAH, tf->lbah); |
f92041125 Blackfin pata-bf5... |
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dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X ", |
d830d1731 libata driver for... |
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tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah); } if (tf->flags & ATA_TFLAG_DEVICE) { write_atapi_register(base, ATA_REG_DEVICE, tf->device); |
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dev_dbg(ap->dev, "device 0x%X ", tf->device); |
d830d1731 libata driver for... |
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} ata_wait_idle(ap); } /** * bfin_check_status - Read device status reg & clear interrupt * @ap: port where the device is * * Note: Original code is ata_check_status(). */ static u8 bfin_check_status(struct ata_port *ap) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; return read_atapi_register(base, ATA_REG_STATUS); } /** * bfin_tf_read - input device's ATA taskfile shadow registers * @ap: Port from which input is read * @tf: ATA taskfile register set for storing input * |
9363c3825 libata: rename SF... |
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* Note: Original code is ata_sff_tf_read(). |
d830d1731 libata driver for... |
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*/ static void bfin_tf_read(struct ata_port *ap, struct ata_taskfile *tf) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; tf->command = bfin_check_status(ap); tf->feature = read_atapi_register(base, ATA_REG_ERR); tf->nsect = read_atapi_register(base, ATA_REG_NSECT); tf->lbal = read_atapi_register(base, ATA_REG_LBAL); tf->lbam = read_atapi_register(base, ATA_REG_LBAM); tf->lbah = read_atapi_register(base, ATA_REG_LBAH); tf->device = read_atapi_register(base, ATA_REG_DEVICE); if (tf->flags & ATA_TFLAG_LBA48) { write_atapi_register(base, ATA_REG_CTRL, tf->ctl | ATA_HOB); tf->hob_feature = read_atapi_register(base, ATA_REG_ERR); tf->hob_nsect = read_atapi_register(base, ATA_REG_NSECT); tf->hob_lbal = read_atapi_register(base, ATA_REG_LBAL); tf->hob_lbam = read_atapi_register(base, ATA_REG_LBAM); tf->hob_lbah = read_atapi_register(base, ATA_REG_LBAH); } } /** * bfin_exec_command - issue ATA command to host controller * @ap: port to which command is being issued * @tf: ATA taskfile register set * |
9363c3825 libata: rename SF... |
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* Note: Original code is ata_sff_exec_command(). |
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*/ static void bfin_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; |
f92041125 Blackfin pata-bf5... |
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dev_dbg(ap->dev, "ata%u: cmd 0x%X ", ap->print_id, tf->command); |
d830d1731 libata driver for... |
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write_atapi_register(base, ATA_REG_CMD, tf->command); |
9363c3825 libata: rename SF... |
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ata_sff_pause(ap); |
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} /** * bfin_check_altstatus - Read device alternate status reg * @ap: port where the device is */ static u8 bfin_check_altstatus(struct ata_port *ap) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; return read_atapi_register(base, ATA_REG_ALTSTATUS); } /** |
9363c3825 libata: rename SF... |
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* bfin_dev_select - Select device 0/1 on ATA bus |
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* @ap: ATA channel to manipulate * @device: ATA device (numbered from zero) to select * |
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* Note: Original code is ata_sff_dev_select(). |
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*/ |
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static void bfin_dev_select(struct ata_port *ap, unsigned int device) |
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{ void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; u8 tmp; if (device == 0) tmp = ATA_DEVICE_OBS; else tmp = ATA_DEVICE_OBS | ATA_DEV1; write_atapi_register(base, ATA_REG_DEVICE, tmp); |
9363c3825 libata: rename SF... |
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ata_sff_pause(ap); |
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} /** |
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* bfin_set_devctl - Write device control reg * @ap: port where the device is * @ctl: value to write */ |
c0695733d pata_bf54x: fix r... |
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static void bfin_set_devctl(struct ata_port *ap, u8 ctl) |
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{ void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; write_atapi_register(base, ATA_REG_CTRL, ctl); } /** |
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* bfin_bmdma_setup - Set up IDE DMA transaction * @qc: Info associated with this ATA transaction. * * Note: Original code is ata_bmdma_setup(). */ static void bfin_bmdma_setup(struct ata_queued_cmd *qc) { |
81b0287d3 [libata] pata_bf5... |
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struct ata_port *ap = qc->ap; struct dma_desc_array *dma_desc_cpu = (struct dma_desc_array *)ap->bmdma_prd; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; unsigned short config = DMAFLOW_ARRAY | NDSIZE_5 | RESTART | WDSIZE_16 | DMAEN; |
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struct scatterlist *sg; |
ff2aeb1eb libata: convert t... |
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unsigned int si; |
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unsigned int channel; unsigned int dir; unsigned int size = 0; |
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|
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dev_dbg(qc->ap->dev, "in atapi dma setup "); |
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/* Program the ATA_CTRL register with dir */ if (qc->tf.flags & ATA_TFLAG_WRITE) { |
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channel = CH_ATAPI_TX; dir = DMA_TO_DEVICE; |
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} else { |
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channel = CH_ATAPI_RX; dir = DMA_FROM_DEVICE; |
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config |= WNR; |
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} |
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|
81b0287d3 [libata] pata_bf5... |
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dma_map_sg(ap->dev, qc->sg, qc->n_elem, dir); |
d830d1731 libata driver for... |
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|
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/* fill the ATAPI DMA controller */ for_each_sg(qc->sg, sg, qc->n_elem, si) { dma_desc_cpu[si].start_addr = sg_dma_address(sg); dma_desc_cpu[si].cfg = config; dma_desc_cpu[si].x_count = sg_dma_len(sg) >> 1; dma_desc_cpu[si].x_modify = 2; size += sg_dma_len(sg); } |
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|
81b0287d3 [libata] pata_bf5... |
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/* Set the last descriptor to stop mode */ dma_desc_cpu[qc->n_elem - 1].cfg &= ~(DMAFLOW | NDSIZE); |
d830d1731 libata driver for... |
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|
81b0287d3 [libata] pata_bf5... |
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flush_dcache_range((unsigned int)dma_desc_cpu, (unsigned int)dma_desc_cpu + qc->n_elem * sizeof(struct dma_desc_array)); /* Enable ATA DMA operation*/ set_dma_curr_desc_addr(channel, (unsigned long *)ap->bmdma_prd_dma); set_dma_x_count(channel, 0); set_dma_x_modify(channel, 0); set_dma_config(channel, config); SSYNC(); |
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|
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/* Send ATA DMA command */ bfin_exec_command(ap, &qc->tf); |
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|
81b0287d3 [libata] pata_bf5... |
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if (qc->tf.flags & ATA_TFLAG_WRITE) { |
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/* set ATA DMA write direction */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR)); } else { |
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/* set ATA DMA read direction */ ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR)); } /* Reset all transfer count */ ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST); |
b6e7b4479 pata-bf54x: Set A... |
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/* Set ATAPI state machine contorl in terminate sequence */ ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | END_ON_TERM); |
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/* Set transfer length to the total size of sg buffers */ ATAPI_SET_XFER_LEN(base, size >> 1); } |
d830d1731 libata driver for... |
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|
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/** * bfin_bmdma_start - Start an IDE DMA transaction * @qc: Info associated with this ATA transaction. * * Note: Original code is ata_bmdma_start(). */ static void bfin_bmdma_start(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; dev_dbg(qc->ap->dev, "in atapi dma start "); if (!(ap->udma_mask || ap->mwdma_mask)) return; /* start ATAPI transfer*/ |
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if (ap->udma_mask) ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | ULTRA_START); else ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | MULTI_START); } /** * bfin_bmdma_stop - Stop IDE DMA transfer * @qc: Command we are ending DMA for */ static void bfin_bmdma_stop(struct ata_queued_cmd *qc) { struct ata_port *ap = qc->ap; |
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unsigned int dir; |
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|
f92041125 Blackfin pata-bf5... |
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dev_dbg(qc->ap->dev, "in atapi dma stop "); |
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|
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if (!(ap->udma_mask || ap->mwdma_mask)) return; /* stop ATAPI DMA controller*/ |
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if (qc->tf.flags & ATA_TFLAG_WRITE) { dir = DMA_TO_DEVICE; |
d830d1731 libata driver for... |
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disable_dma(CH_ATAPI_TX); |
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} else { dir = DMA_FROM_DEVICE; |
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disable_dma(CH_ATAPI_RX); |
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} |
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dma_unmap_sg(ap->dev, qc->sg, qc->n_elem, dir); |
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} /** * bfin_devchk - PATA device presence detection * @ap: ATA channel to examine * @device: Device to examine (starting at zero) * * Note: Original code is ata_devchk(). */ static unsigned int bfin_devchk(struct ata_port *ap, unsigned int device) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; u8 nsect, lbal; |
9363c3825 libata: rename SF... |
974 |
bfin_dev_select(ap, device); |
d830d1731 libata driver for... |
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write_atapi_register(base, ATA_REG_NSECT, 0x55); write_atapi_register(base, ATA_REG_LBAL, 0xaa); write_atapi_register(base, ATA_REG_NSECT, 0xaa); write_atapi_register(base, ATA_REG_LBAL, 0x55); write_atapi_register(base, ATA_REG_NSECT, 0x55); write_atapi_register(base, ATA_REG_LBAL, 0xaa); nsect = read_atapi_register(base, ATA_REG_NSECT); lbal = read_atapi_register(base, ATA_REG_LBAL); if ((nsect == 0x55) && (lbal == 0xaa)) return 1; /* we found a device */ return 0; /* nothing found */ } /** * bfin_bus_post_reset - PATA device post reset * * Note: Original code is ata_bus_post_reset(). */ static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; unsigned int dev0 = devmask & (1 << 0); unsigned int dev1 = devmask & (1 << 1); |
341c2c958 libata: consisten... |
1005 |
unsigned long deadline; |
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/* if device 0 was found in ata_devchk, wait for its * BSY bit to clear */ if (dev0) |
9363c3825 libata: rename SF... |
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ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); |
d830d1731 libata driver for... |
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/* if device 1 was found in ata_devchk, wait for * register access, then wait for BSY to clear */ |
341c2c958 libata: consisten... |
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deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT); |
d830d1731 libata driver for... |
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while (dev1) { u8 nsect, lbal; |
9363c3825 libata: rename SF... |
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bfin_dev_select(ap, 1); |
d830d1731 libata driver for... |
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nsect = read_atapi_register(base, ATA_REG_NSECT); lbal = read_atapi_register(base, ATA_REG_LBAL); if ((nsect == 1) && (lbal == 1)) break; |
341c2c958 libata: consisten... |
1024 |
if (time_after(jiffies, deadline)) { |
d830d1731 libata driver for... |
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dev1 = 0; break; } |
97750cebb libata: add @ap t... |
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ata_msleep(ap, 50); /* give drive a breather */ |
d830d1731 libata driver for... |
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} if (dev1) |
9363c3825 libata: rename SF... |
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ata_sff_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT); |
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/* is all this really necessary? */ |
9363c3825 libata: rename SF... |
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bfin_dev_select(ap, 0); |
d830d1731 libata driver for... |
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if (dev1) |
9363c3825 libata: rename SF... |
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bfin_dev_select(ap, 1); |
d830d1731 libata driver for... |
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if (dev0) |
9363c3825 libata: rename SF... |
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bfin_dev_select(ap, 0); |
d830d1731 libata driver for... |
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} /** * bfin_bus_softreset - PATA device software reset * * Note: Original code is ata_bus_softreset(). */ static unsigned int bfin_bus_softreset(struct ata_port *ap, unsigned int devmask) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; /* software reset. causes dev0 to be selected */ write_atapi_register(base, ATA_REG_CTRL, ap->ctl); udelay(20); write_atapi_register(base, ATA_REG_CTRL, ap->ctl | ATA_SRST); udelay(20); write_atapi_register(base, ATA_REG_CTRL, ap->ctl); /* spec mandates ">= 2ms" before checking status. * We wait 150ms, because that was the magic delay used for * ATAPI devices in Hale Landis's ATADRVR, for the period of time * between when the ATA command register is written, and then * status is checked. Because waiting for "a while" before * checking status is fine, post SRST, we perform this magic * delay here as well. * * Old drivers/ide uses the 2mS rule and then waits for ready */ |
97750cebb libata: add @ap t... |
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ata_msleep(ap, 150); |
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/* Before we perform post reset processing we want to see if * the bus shows 0xFF because the odd clown forgets the D7 * pulldown resistor. */ if (bfin_check_status(ap) == 0xFF) return 0; bfin_bus_post_reset(ap, devmask); return 0; } /** |
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* bfin_softreset - reset host port via ATA SRST |
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* @ap: port to reset * @classes: resulting classes of attached devices * |
9363c3825 libata: rename SF... |
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* Note: Original code is ata_sff_softreset(). |
d830d1731 libata driver for... |
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*/ |
9363c3825 libata: rename SF... |
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static int bfin_softreset(struct ata_link *link, unsigned int *classes, unsigned long deadline) |
d830d1731 libata driver for... |
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{ |
858c9c406 Update libata dri... |
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struct ata_port *ap = link->ap; |
d830d1731 libata driver for... |
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unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; unsigned int devmask = 0, err_mask; u8 err; |
d830d1731 libata driver for... |
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/* determine if device 0/1 are present */ if (bfin_devchk(ap, 0)) devmask |= (1 << 0); if (slave_possible && bfin_devchk(ap, 1)) devmask |= (1 << 1); /* select device 0 again */ |
9363c3825 libata: rename SF... |
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bfin_dev_select(ap, 0); |
d830d1731 libata driver for... |
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/* issue bus reset */ err_mask = bfin_bus_softreset(ap, devmask); if (err_mask) { |
a9a79dfec ata: Convert ata_... |
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ata_port_err(ap, "SRST failed (err_mask=0x%x) ", |
d830d1731 libata driver for... |
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err_mask); return -EIO; } /* determine by signature whether we have ATA or ATAPI devices */ |
9363c3825 libata: rename SF... |
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classes[0] = ata_sff_dev_classify(&ap->link.device[0], |
858c9c406 Update libata dri... |
1117 |
devmask & (1 << 0), &err); |
d830d1731 libata driver for... |
1118 |
if (slave_possible && err != 0x81) |
9363c3825 libata: rename SF... |
1119 |
classes[1] = ata_sff_dev_classify(&ap->link.device[1], |
858c9c406 Update libata dri... |
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devmask & (1 << 1), &err); |
d830d1731 libata driver for... |
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|
d830d1731 libata driver for... |
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return 0; } /** * bfin_bmdma_status - Read IDE DMA status * @ap: Port associated with this ATA transaction. */ static unsigned char bfin_bmdma_status(struct ata_port *ap) { unsigned char host_stat = 0; void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; |
d830d1731 libata driver for... |
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|
909fefc25 pata_bf54x: fix B... |
1135 |
if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON | ULTRA_XFER_ON)) |
dc86f6d41 libata: Return pr... |
1136 |
host_stat |= ATA_DMA_ACTIVE; |
909fefc25 pata_bf54x: fix B... |
1137 |
if (ATAPI_GET_INT_STATUS(base) & ATAPI_DEV_INT) |
dc86f6d41 libata: Return pr... |
1138 |
host_stat |= ATA_DMA_INTR; |
d830d1731 libata driver for... |
1139 |
|
f92041125 Blackfin pata-bf5... |
1140 1141 |
dev_dbg(ap->dev, "ATAPI: host_stat=0x%x ", host_stat); |
d830d1731 libata driver for... |
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return host_stat; } /** * bfin_data_xfer - Transfer data by PIO * @adev: device for this I/O * @buf: data buffer * @buflen: buffer length * @write_data: read/write * |
9363c3825 libata: rename SF... |
1152 |
* Note: Original code is ata_sff_data_xfer(). |
d830d1731 libata driver for... |
1153 |
*/ |
55dba3120 libata: update ->... |
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static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf, unsigned int buflen, int rw) |
d830d1731 libata driver for... |
1156 |
{ |
55dba3120 libata: update ->... |
1157 |
struct ata_port *ap = dev->link->ap; |
d830d1731 libata driver for... |
1158 |
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; |
55dba3120 libata: update ->... |
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unsigned int words = buflen >> 1; unsigned short *buf16 = (u16 *)buf; |
d830d1731 libata driver for... |
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/* Transfer multiple of 2 bytes */ |
55dba3120 libata: update ->... |
1163 |
if (rw == READ) |
d830d1731 libata driver for... |
1164 |
read_atapi_data(base, words, buf16); |
55dba3120 libata: update ->... |
1165 1166 |
else write_atapi_data(base, words, buf16); |
d830d1731 libata driver for... |
1167 1168 1169 1170 1171 |
/* Transfer trailing 1 byte, if any. */ if (unlikely(buflen & 0x01)) { unsigned short align_buf[1] = { 0 }; unsigned char *trailing_buf = buf + buflen - 1; |
55dba3120 libata: update ->... |
1172 |
if (rw == READ) { |
d830d1731 libata driver for... |
1173 1174 |
read_atapi_data(base, 1, align_buf); memcpy(trailing_buf, align_buf, 1); |
55dba3120 libata: update ->... |
1175 1176 1177 |
} else { memcpy(align_buf, trailing_buf, 1); write_atapi_data(base, 1, align_buf); |
d830d1731 libata driver for... |
1178 |
} |
55dba3120 libata: update ->... |
1179 |
words++; |
d830d1731 libata driver for... |
1180 |
} |
55dba3120 libata: update ->... |
1181 1182 |
return words << 1; |
d830d1731 libata driver for... |
1183 1184 1185 1186 1187 1188 |
} /** * bfin_irq_clear - Clear ATAPI interrupt. * @ap: Port associated with this ATA transaction. * |
37f65b8bc libata-sff: ata_s... |
1189 |
* Note: Original code is ata_bmdma_irq_clear(). |
d830d1731 libata driver for... |
1190 1191 1192 1193 1194 |
*/ static void bfin_irq_clear(struct ata_port *ap) { void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; |
f92041125 Blackfin pata-bf5... |
1195 1196 |
dev_dbg(ap->dev, "in atapi irq clear "); |
858c9c406 Update libata dri... |
1197 1198 1199 |
ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT); |
d830d1731 libata driver for... |
1200 1201 1202 |
} /** |
9363c3825 libata: rename SF... |
1203 |
* bfin_thaw - Thaw DMA controller port |
d830d1731 libata driver for... |
1204 1205 |
* @ap: port to thaw * |
9363c3825 libata: rename SF... |
1206 |
* Note: Original code is ata_sff_thaw(). |
d830d1731 libata driver for... |
1207 |
*/ |
9363c3825 libata: rename SF... |
1208 |
void bfin_thaw(struct ata_port *ap) |
d830d1731 libata driver for... |
1209 |
{ |
65c0d4e54 Fix bug - Impleme... |
1210 1211 |
dev_dbg(ap->dev, "in atapi dma thaw "); |
d830d1731 libata driver for... |
1212 |
bfin_check_status(ap); |
e42a542ba libata: make sff_... |
1213 |
ata_sff_irq_on(ap); |
d830d1731 libata driver for... |
1214 1215 1216 |
} /** |
9363c3825 libata: rename SF... |
1217 |
* bfin_postreset - standard postreset callback |
d830d1731 libata driver for... |
1218 1219 1220 |
* @ap: the target ata_port * @classes: classes of attached devices * |
9363c3825 libata: rename SF... |
1221 |
* Note: Original code is ata_sff_postreset(). |
d830d1731 libata driver for... |
1222 |
*/ |
9363c3825 libata: rename SF... |
1223 |
static void bfin_postreset(struct ata_link *link, unsigned int *classes) |
d830d1731 libata driver for... |
1224 |
{ |
858c9c406 Update libata dri... |
1225 |
struct ata_port *ap = link->ap; |
d830d1731 libata driver for... |
1226 1227 1228 |
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr; /* re-enable interrupts */ |
e42a542ba libata: make sff_... |
1229 |
ata_sff_irq_on(ap); |
d830d1731 libata driver for... |
1230 1231 1232 |
/* is double-select really necessary? */ if (classes[0] != ATA_DEV_NONE) |
9363c3825 libata: rename SF... |
1233 |
bfin_dev_select(ap, 1); |
d830d1731 libata driver for... |
1234 |
if (classes[1] != ATA_DEV_NONE) |
9363c3825 libata: rename SF... |
1235 |
bfin_dev_select(ap, 0); |
d830d1731 libata driver for... |
1236 1237 1238 1239 1240 1241 1242 1243 1244 |
/* bail out if no device is present */ if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { return; } /* set up device control */ write_atapi_register(base, ATA_REG_CTRL, ap->ctl); } |
d830d1731 libata driver for... |
1245 1246 |
static void bfin_port_stop(struct ata_port *ap) { |
f92041125 Blackfin pata-bf5... |
1247 1248 |
dev_dbg(ap->dev, "in atapi port stop "); |
d830d1731 libata driver for... |
1249 |
if (ap->udma_mask != 0 || ap->mwdma_mask != 0) { |
81b0287d3 [libata] pata_bf5... |
1250 1251 1252 1253 |
dma_free_coherent(ap->dev, BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), ap->bmdma_prd, ap->bmdma_prd_dma); |
d830d1731 libata driver for... |
1254 1255 1256 1257 1258 1259 1260 |
free_dma(CH_ATAPI_RX); free_dma(CH_ATAPI_TX); } } static int bfin_port_start(struct ata_port *ap) { |
f92041125 Blackfin pata-bf5... |
1261 1262 |
dev_dbg(ap->dev, "in atapi port start "); |
d830d1731 libata driver for... |
1263 1264 |
if (!(ap->udma_mask || ap->mwdma_mask)) return 0; |
81b0287d3 [libata] pata_bf5... |
1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 |
ap->bmdma_prd = dma_alloc_coherent(ap->dev, BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), &ap->bmdma_prd_dma, GFP_KERNEL); if (ap->bmdma_prd == NULL) { dev_info(ap->dev, "Unable to allocate DMA descriptor array. "); goto out; } |
d830d1731 libata driver for... |
1275 1276 1277 1278 1279 1280 |
if (request_dma(CH_ATAPI_RX, "BFIN ATAPI RX DMA") >= 0) { if (request_dma(CH_ATAPI_TX, "BFIN ATAPI TX DMA") >= 0) return 0; free_dma(CH_ATAPI_RX); |
81b0287d3 [libata] pata_bf5... |
1281 1282 1283 1284 |
dma_free_coherent(ap->dev, BFIN_MAX_SG_SEGMENTS * sizeof(struct dma_desc_array), ap->bmdma_prd, ap->bmdma_prd_dma); |
d830d1731 libata driver for... |
1285 |
} |
81b0287d3 [libata] pata_bf5... |
1286 |
out: |
d830d1731 libata driver for... |
1287 1288 1289 1290 1291 1292 1293 1294 |
ap->udma_mask = 0; ap->mwdma_mask = 0; dev_err(ap->dev, "Unable to request ATAPI DMA!" " Continue in PIO mode. "); return 0; } |
65c0d4e54 Fix bug - Impleme... |
1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 |
static unsigned int bfin_ata_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc) { struct ata_eh_info *ehi = &ap->link.eh_info; u8 status, host_stat = 0; VPRINTK("ata%u: protocol %d task_state %d ", ap->print_id, qc->tf.protocol, ap->hsm_task_state); /* Check whether we are expecting interrupt in this state */ switch (ap->hsm_task_state) { case HSM_ST_FIRST: /* Some pre-ATAPI-4 devices assert INTRQ * at this state when ready to receive CDB. */ /* Check the ATA_DFLAG_CDB_INTR flag is enough here. * The flag was turned on only for atapi devices. * No need to check is_atapi_taskfile(&qc->tf) again. */ if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) goto idle_irq; break; case HSM_ST_LAST: if (qc->tf.protocol == ATA_PROT_DMA || qc->tf.protocol == ATAPI_PROT_DMA) { /* check status of DMA engine */ host_stat = ap->ops->bmdma_status(ap); VPRINTK("ata%u: host_stat 0x%X ", ap->print_id, host_stat); /* if it's not our irq... */ if (!(host_stat & ATA_DMA_INTR)) goto idle_irq; /* before we do anything else, clear DMA-Start bit */ ap->ops->bmdma_stop(qc); if (unlikely(host_stat & ATA_DMA_ERR)) { |
25985edce Fix common misspe... |
1336 |
/* error when transferring data to/from memory */ |
65c0d4e54 Fix bug - Impleme... |
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 |
qc->err_mask |= AC_ERR_HOST_BUS; ap->hsm_task_state = HSM_ST_ERR; } } break; case HSM_ST: break; default: goto idle_irq; } /* check altstatus */ status = ap->ops->sff_check_altstatus(ap); if (status & ATA_BUSY) goto busy_ata; /* check main status, clearing INTRQ */ status = ap->ops->sff_check_status(ap); if (unlikely(status & ATA_BUSY)) goto busy_ata; /* ack bmdma irq events */ ap->ops->sff_irq_clear(ap); ata_sff_hsm_move(ap, qc, status, 0); if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || qc->tf.protocol == ATAPI_PROT_DMA)) ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); busy_ata: return 1; /* irq handled */ idle_irq: ap->stats.idle_irq++; #ifdef ATA_IRQ_TRAP if ((ap->stats.idle_irq % 1000) == 0) { ap->ops->irq_ack(ap, 0); /* debug trap */ |
a9a79dfec ata: Convert ata_... |
1376 1377 |
ata_port_warn(ap, "irq trap "); |
65c0d4e54 Fix bug - Impleme... |
1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 |
return 1; } #endif return 0; /* irq not handled */ } static irqreturn_t bfin_ata_interrupt(int irq, void *dev_instance) { struct ata_host *host = dev_instance; unsigned int i; unsigned int handled = 0; unsigned long flags; /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ spin_lock_irqsave(&host->lock, flags); for (i = 0; i < host->n_ports; i++) { |
3e4ec3443 libata: kill ATA_... |
1395 1396 |
struct ata_port *ap = host->ports[i]; struct ata_queued_cmd *qc; |
65c0d4e54 Fix bug - Impleme... |
1397 |
|
3e4ec3443 libata: kill ATA_... |
1398 1399 1400 |
qc = ata_qc_from_tag(ap, ap->link.active_tag); if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) handled |= bfin_ata_host_intr(ap, qc); |
65c0d4e54 Fix bug - Impleme... |
1401 1402 1403 1404 1405 1406 |
} spin_unlock_irqrestore(&host->lock, flags); return IRQ_RETVAL(handled); } |
d830d1731 libata driver for... |
1407 |
static struct scsi_host_template bfin_sht = { |
68d1d07b5 libata: implement... |
1408 |
ATA_BASE_SHT(DRV_NAME), |
81b0287d3 [libata] pata_bf5... |
1409 |
.sg_tablesize = BFIN_MAX_SG_SEGMENTS, |
d830d1731 libata driver for... |
1410 |
.dma_boundary = ATA_DMA_BOUNDARY, |
d830d1731 libata driver for... |
1411 |
}; |
65c0d4e54 Fix bug - Impleme... |
1412 |
static struct ata_port_operations bfin_pata_ops = { |
8930ff254 libata-sff: clean... |
1413 |
.inherits = &ata_bmdma_port_ops, |
029cfd6b7 libata: implement... |
1414 |
|
d830d1731 libata driver for... |
1415 1416 |
.set_piomode = bfin_set_piomode, .set_dmamode = bfin_set_dmamode, |
5682ed33a libata: rename SF... |
1417 1418 1419 1420 1421 1422 |
.sff_tf_load = bfin_tf_load, .sff_tf_read = bfin_tf_read, .sff_exec_command = bfin_exec_command, .sff_check_status = bfin_check_status, .sff_check_altstatus = bfin_check_altstatus, .sff_dev_select = bfin_dev_select, |
41dec29bc libata: introduce... |
1423 |
.sff_set_devctl = bfin_set_devctl, |
d830d1731 libata driver for... |
1424 1425 1426 1427 1428 |
.bmdma_setup = bfin_bmdma_setup, .bmdma_start = bfin_bmdma_start, .bmdma_stop = bfin_bmdma_stop, .bmdma_status = bfin_bmdma_status, |
5682ed33a libata: rename SF... |
1429 |
.sff_data_xfer = bfin_data_xfer, |
d830d1731 libata driver for... |
1430 1431 |
.qc_prep = ata_noop_qc_prep, |
d830d1731 libata driver for... |
1432 |
|
9363c3825 libata: rename SF... |
1433 1434 1435 |
.thaw = bfin_thaw, .softreset = bfin_softreset, .postreset = bfin_postreset, |
d830d1731 libata driver for... |
1436 |
|
5682ed33a libata: rename SF... |
1437 |
.sff_irq_clear = bfin_irq_clear, |
d830d1731 libata driver for... |
1438 1439 1440 1441 1442 1443 1444 |
.port_start = bfin_port_start, .port_stop = bfin_port_stop, }; static struct ata_port_info bfin_port_info[] = { { |
9cbe056f6 libata: remove AT... |
1445 |
.flags = ATA_FLAG_SLAVE_POSS, |
14bdef982 [libata] convert ... |
1446 |
.pio_mask = ATA_PIO4, |
d830d1731 libata driver for... |
1447 |
.mwdma_mask = 0, |
d830d1731 libata driver for... |
1448 |
.udma_mask = 0, |
d830d1731 libata driver for... |
1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 |
.port_ops = &bfin_pata_ops, }, }; /** * bfin_reset_controller - initialize BF54x ATAPI controller. */ static int bfin_reset_controller(struct ata_host *host) { void __iomem *base = (void __iomem *)host->ports[0]->ioaddr.ctl_addr; int count; unsigned short status; /* Disable all ATAPI interrupts */ ATAPI_SET_INT_MASK(base, 0); SSYNC(); /* Assert the RESET signal 25us*/ ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST); udelay(30); /* Negate the RESET signal for 2ms*/ ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST); msleep(2); /* Wait on Busy flag to clear */ count = 10000000; do { status = read_atapi_register(base, ATA_REG_STATUS); |
f9d424917 pata_bf54x: decre... |
1479 |
} while (--count && (status & ATA_BUSY)); |
d830d1731 libata driver for... |
1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 |
/* Enable only ATAPI Device interrupt */ ATAPI_SET_INT_MASK(base, 1); SSYNC(); return (!count); } /** * atapi_io_port - define atapi peripheral port pins. */ static unsigned short atapi_io_port[] = { P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY, |
3439d6506 pata_bf54x: handl... |
1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 |
P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A, P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, |
d830d1731 libata driver for... |
1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 |
0 }; /** * bfin_atapi_probe - attach a bfin atapi interface * @pdev: platform device * * Register a bfin atapi interface. * * * Platform devices are expected to contain 2 resources per port: * * - I/O Base (IORESOURCE_IO) * - IRQ (IORESOURCE_IRQ) * */ |
0ec249146 Drivers: ata: rem... |
1536 |
static int bfin_atapi_probe(struct platform_device *pdev) |
d830d1731 libata driver for... |
1537 1538 1539 1540 |
{ int board_idx = 0; struct resource *res; struct ata_host *host; |
f88c480da Set proper ATA UD... |
1541 1542 |
unsigned int fsclk = get_sclk(); int udma_mode = 5; |
d830d1731 libata driver for... |
1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 |
const struct ata_port_info *ppi[] = { &bfin_port_info[board_idx], NULL }; /* * Simple resource validation .. */ if (unlikely(pdev->num_resources != 2)) { dev_err(&pdev->dev, "invalid number of resources "); return -EINVAL; } /* * Get the register base first */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) return -EINVAL; |
ed722d3d3 [libata] pata_bf5... |
1561 1562 |
while (bfin_port_info[board_idx].udma_mask > 0 && udma_fsclk[udma_mode] > fsclk) { |
f88c480da Set proper ATA UD... |
1563 1564 1565 |
udma_mode--; bfin_port_info[board_idx].udma_mask >>= 1; } |
d830d1731 libata driver for... |
1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 |
/* * Now that that's out of the way, wire up the port.. */ host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1); if (!host) return -ENOMEM; host->ports[0]->ioaddr.ctl_addr = (void *)res->start; if (peripheral_request_list(atapi_io_port, "atapi-io-port")) { |
426d31071 fix printk typo '... |
1576 1577 |
dev_err(&pdev->dev, "Requesting Peripherals failed "); |
d830d1731 libata driver for... |
1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 |
return -EFAULT; } if (bfin_reset_controller(host)) { peripheral_free_list(atapi_io_port); dev_err(&pdev->dev, "Fail to reset ATAPI device "); return -EFAULT; } if (ata_host_activate(host, platform_get_irq(pdev, 0), |
65c0d4e54 Fix bug - Impleme... |
1589 |
bfin_ata_interrupt, IRQF_SHARED, &bfin_sht) != 0) { |
d830d1731 libata driver for... |
1590 1591 1592 1593 1594 |
peripheral_free_list(atapi_io_port); dev_err(&pdev->dev, "Fail to attach ATAPI device "); return -ENODEV; } |
d89995db5 ata: use platform... |
1595 |
platform_set_drvdata(pdev, host); |
67e3e221d [libata] pata_bf5... |
1596 |
|
d830d1731 libata driver for... |
1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 |
return 0; } /** * bfin_atapi_remove - unplug a bfin atapi interface * @pdev: platform device * * A bfin atapi device has been unplugged. Perform the needed * cleanup. Also called on module unload for any active devices. */ |
0ec249146 Drivers: ata: rem... |
1607 |
static int bfin_atapi_remove(struct platform_device *pdev) |
d830d1731 libata driver for... |
1608 |
{ |
d89995db5 ata: use platform... |
1609 |
struct ata_host *host = platform_get_drvdata(pdev); |
d830d1731 libata driver for... |
1610 1611 1612 1613 1614 1615 1616 |
ata_host_detach(host); peripheral_free_list(atapi_io_port); return 0; } |
58eb8cd56 ata: use CONFIG_P... |
1617 |
#ifdef CONFIG_PM_SLEEP |
67e3e221d [libata] pata_bf5... |
1618 |
static int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state) |
d830d1731 libata driver for... |
1619 |
{ |
d89995db5 ata: use platform... |
1620 |
struct ata_host *host = platform_get_drvdata(pdev); |
67e3e221d [libata] pata_bf5... |
1621 1622 1623 1624 |
if (host) return ata_host_suspend(host, state); else return 0; |
d830d1731 libata driver for... |
1625 |
} |
67e3e221d [libata] pata_bf5... |
1626 |
static int bfin_atapi_resume(struct platform_device *pdev) |
d830d1731 libata driver for... |
1627 |
{ |
d89995db5 ata: use platform... |
1628 |
struct ata_host *host = platform_get_drvdata(pdev); |
67e3e221d [libata] pata_bf5... |
1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 |
int ret; if (host) { ret = bfin_reset_controller(host); if (ret) { printk(KERN_ERR DRV_NAME ": Error during HW init "); return ret; } ata_host_resume(host); } |
d830d1731 libata driver for... |
1640 1641 |
return 0; } |
67e3e221d [libata] pata_bf5... |
1642 1643 1644 |
#else #define bfin_atapi_suspend NULL #define bfin_atapi_resume NULL |
d830d1731 libata driver for... |
1645 1646 1647 1648 |
#endif static struct platform_driver bfin_atapi_driver = { .probe = bfin_atapi_probe, |
0ec249146 Drivers: ata: rem... |
1649 |
.remove = bfin_atapi_remove, |
67e3e221d [libata] pata_bf5... |
1650 1651 |
.suspend = bfin_atapi_suspend, .resume = bfin_atapi_resume, |
d830d1731 libata driver for... |
1652 1653 |
.driver = { .name = DRV_NAME, |
d830d1731 libata driver for... |
1654 1655 |
}, }; |
858c9c406 Update libata dri... |
1656 1657 |
#define ATAPI_MODE_SIZE 10 static char bfin_atapi_mode[ATAPI_MODE_SIZE]; |
d830d1731 libata driver for... |
1658 1659 1660 1661 |
static int __init bfin_atapi_init(void) { pr_info("register bfin atapi driver "); |
858c9c406 Update libata dri... |
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 |
switch(bfin_atapi_mode[0]) { case 'p': case 'P': break; case 'm': case 'M': bfin_port_info[0].mwdma_mask = ATA_MWDMA2; break; default: bfin_port_info[0].udma_mask = ATA_UDMA5; }; |
d830d1731 libata driver for... |
1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 |
return platform_driver_register(&bfin_atapi_driver); } static void __exit bfin_atapi_exit(void) { platform_driver_unregister(&bfin_atapi_driver); } module_init(bfin_atapi_init); module_exit(bfin_atapi_exit); |
858c9c406 Update libata dri... |
1684 1685 1686 1687 1688 1689 1690 |
/* * ATAPI mode: * pio/PIO * udma/UDMA (default) * mwdma/MWDMA */ module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0); |
d830d1731 libata driver for... |
1691 1692 1693 1694 1695 |
MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>"); MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); |
458622fcd ATA/IDE: fix plat... |
1696 |
MODULE_ALIAS("platform:" DRV_NAME); |