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drivers/dma/stm32-dma.c
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// SPDX-License-Identifier: GPL-2.0-only |
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/* * Driver for STM32 DMA controller * * Inspired by dma-jz4740.c and tegra20-apb-dma.c * * Copyright (C) M'boumba Cedric Madianga 2015 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> |
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* Pierre-Yves Mordret <pierre-yves.mordret@st.com> |
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*/ #include <linux/clk.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/init.h> |
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#include <linux/iopoll.h> |
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#include <linux/jiffies.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_dma.h> #include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> #include <linux/sched.h> #include <linux/slab.h> #include "virt-dma.h" #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ |
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#define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ |
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#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ |
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#define STM32_DMA_MASKI (STM32_DMA_TCI \ | STM32_DMA_TEI \ | STM32_DMA_DMEI \ | STM32_DMA_FEI) |
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/* DMA Stream x Configuration Register */ #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25) #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23) #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23) #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21) #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21) #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16) #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16) #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13) #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13) #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11) #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11) #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11) #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6) #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6) #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ |
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#define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable */ |
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#define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \ | STM32_DMA_SCR_MINC \ | STM32_DMA_SCR_PINCOS \ | STM32_DMA_SCR_PL_MASK) #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \ | STM32_DMA_SCR_TEIE \ | STM32_DMA_SCR_DMEIE) /* DMA Stream x number of data register */ #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x)) /* DMA stream peripheral address register */ #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x)) /* DMA stream x memory 0 address register */ #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x)) /* DMA stream x memory 1 address register */ #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x)) /* DMA stream x FIFO control register */ #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x)) #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0) #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK) #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \ | STM32_DMA_SFCR_DMDIS) /* DMA direction */ #define STM32_DMA_DEV_TO_MEM 0x00 #define STM32_DMA_MEM_TO_DEV 0x01 #define STM32_DMA_MEM_TO_MEM 0x02 /* DMA priority level */ #define STM32_DMA_PRIORITY_LOW 0x00 #define STM32_DMA_PRIORITY_MEDIUM 0x01 #define STM32_DMA_PRIORITY_HIGH 0x02 #define STM32_DMA_PRIORITY_VERY_HIGH 0x03 /* DMA FIFO threshold selection */ #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02 #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 |
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#define STM32_DMA_FIFO_THRESHOLD_NONE 0x04 |
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#define STM32_DMA_MAX_DATA_ITEMS 0xffff |
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/* * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter * gather at boundary. Thus it's safer to round down this value on FIFO * size (16 Bytes) */ #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) |
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#define STM32_DMA_MAX_CHANNELS 0x08 #define STM32_DMA_MAX_REQUEST_ID 0x08 #define STM32_DMA_MAX_DATA_PARAM 0x03 |
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#define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */ #define STM32_DMA_MIN_BURST 4 |
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#define STM32_DMA_MAX_BURST 16 |
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/* DMA Features */ #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0) #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK) |
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#define STM32_DMA_DIRECT_MODE_MASK BIT(2) #define STM32_DMA_DIRECT_MODE_GET(n) (((n) & STM32_DMA_DIRECT_MODE_MASK) \ >> 2) |
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enum stm32_dma_width { STM32_DMA_BYTE, STM32_DMA_HALF_WORD, STM32_DMA_WORD, }; enum stm32_dma_burst_size { STM32_DMA_BURST_SINGLE, STM32_DMA_BURST_INCR4, STM32_DMA_BURST_INCR8, STM32_DMA_BURST_INCR16, }; |
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/** * struct stm32_dma_cfg - STM32 DMA custom configuration * @channel_id: channel ID * @request_line: DMA request * @stream_config: 32bit mask specifying the DMA channel configuration * @features: 32bit mask specifying the DMA Feature list */ |
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struct stm32_dma_cfg { u32 channel_id; u32 request_line; u32 stream_config; |
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u32 features; |
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}; struct stm32_dma_chan_reg { u32 dma_lisr; u32 dma_hisr; u32 dma_lifcr; u32 dma_hifcr; u32 dma_scr; u32 dma_sndtr; u32 dma_spar; u32 dma_sm0ar; u32 dma_sm1ar; u32 dma_sfcr; }; struct stm32_dma_sg_req { u32 len; struct stm32_dma_chan_reg chan_reg; }; struct stm32_dma_desc { struct virt_dma_desc vdesc; bool cyclic; u32 num_sgs; struct stm32_dma_sg_req sg_req[]; }; struct stm32_dma_chan { struct virt_dma_chan vchan; bool config_init; bool busy; u32 id; u32 irq; struct stm32_dma_desc *desc; u32 next_sg; struct dma_slave_config dma_sconfig; struct stm32_dma_chan_reg chan_reg; |
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u32 threshold; |
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u32 mem_burst; u32 mem_width; |
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}; struct stm32_dma_device { struct dma_device ddev; void __iomem *base; struct clk *clk; |
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bool mem2mem; struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; }; static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) { return container_of(chan->vchan.chan.device, struct stm32_dma_device, ddev); } static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c) { return container_of(c, struct stm32_dma_chan, vchan.chan); } static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) { return container_of(vdesc, struct stm32_dma_desc, vdesc); } static struct device *chan2dev(struct stm32_dma_chan *chan) { return &chan->vchan.chan.dev->device; } static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) { return readl_relaxed(dmadev->base + reg); } static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) { writel_relaxed(val, dmadev->base + reg); } |
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static int stm32_dma_get_width(struct stm32_dma_chan *chan, enum dma_slave_buswidth width) { switch (width) { case DMA_SLAVE_BUSWIDTH_1_BYTE: return STM32_DMA_BYTE; case DMA_SLAVE_BUSWIDTH_2_BYTES: return STM32_DMA_HALF_WORD; case DMA_SLAVE_BUSWIDTH_4_BYTES: return STM32_DMA_WORD; default: dev_err(chan2dev(chan), "Dma bus width not supported "); return -EINVAL; } } |
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static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len, u32 threshold) { enum dma_slave_buswidth max_width; if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) max_width = DMA_SLAVE_BUSWIDTH_4_BYTES; else max_width = DMA_SLAVE_BUSWIDTH_2_BYTES; while ((buf_len < max_width || buf_len % max_width) && max_width > DMA_SLAVE_BUSWIDTH_1_BYTE) max_width = max_width >> 1; return max_width; } static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold, enum dma_slave_buswidth width) { u32 remaining; |
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if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) return false; |
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if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) { if (burst != 0) { /* * If number of beats fit in several whole bursts * this configuration is allowed. */ remaining = ((STM32_DMA_FIFO_SIZE / width) * (threshold + 1) / 4) % burst; if (remaining == 0) return true; } else { return true; } } return false; } static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold) { |
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/* If FIFO direct mode, burst is not possible */ if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) return false; |
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/* * Buffer or period length has to be aligned on FIFO depth. * Otherwise bytes may be stuck within FIFO at buffer or period * length. */ return ((buf_len % ((threshold + 1) * 4)) == 0); |
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} static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold, enum dma_slave_buswidth width) { u32 best_burst = max_burst; if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold)) return 0; while ((buf_len < best_burst * width && best_burst > 1) || !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold, width)) { if (best_burst > STM32_DMA_MIN_BURST) best_burst = best_burst >> 1; else best_burst = 0; } return best_burst; } |
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static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) { switch (maxburst) { case 0: case 1: return STM32_DMA_BURST_SINGLE; case 4: return STM32_DMA_BURST_INCR4; case 8: return STM32_DMA_BURST_INCR8; case 16: return STM32_DMA_BURST_INCR16; default: dev_err(chan2dev(chan), "Dma burst size not supported "); return -EINVAL; } } static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, |
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u32 src_burst, u32 dst_burst) |
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{ chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; |
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if (!src_burst && !dst_burst) { |
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/* Using direct mode */ chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; } else { /* Using FIFO mode */ chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; } } static int stm32_dma_slave_config(struct dma_chan *c, struct dma_slave_config *config) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); memcpy(&chan->dma_sconfig, config, sizeof(*config)); chan->config_init = true; return 0; } static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); u32 flags, dma_isr; /* * Read "flags" from DMA_xISR register corresponding to the selected * DMA channel at the correct bit offset inside that register. * * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. */ if (chan->id & 4) dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); else dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); |
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return flags & STM32_DMA_MASKI; |
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} static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); u32 dma_ifcr; /* * Write "flags" to the DMA_xIFCR register corresponding to the selected * DMA channel at the correct bit offset inside that register. * * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. */ |
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flags &= STM32_DMA_MASKI; |
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dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); if (chan->id & 4) stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); else stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); } static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); |
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u32 dma_scr, id, reg; |
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id = chan->id; |
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reg = STM32_DMA_SCR(id); dma_scr = stm32_dma_read(dmadev, reg); |
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if (dma_scr & STM32_DMA_SCR_EN) { dma_scr &= ~STM32_DMA_SCR_EN; |
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stm32_dma_write(dmadev, reg, dma_scr); return readl_relaxed_poll_timeout_atomic(dmadev->base + reg, dma_scr, !(dma_scr & STM32_DMA_SCR_EN), 10, 1000000); |
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} return 0; } static void stm32_dma_stop(struct stm32_dma_chan *chan) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); u32 dma_scr, dma_sfcr, status; int ret; /* Disable interrupts */ dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); dma_sfcr &= ~STM32_DMA_SFCR_FEIE; stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); /* Disable DMA */ ret = stm32_dma_disable_chan(chan); if (ret < 0) return; /* Clear interrupt status if it is there */ status = stm32_dma_irq_status(chan); if (status) { dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x ", __func__, status); stm32_dma_irq_clear(chan, status); } chan->busy = false; } static int stm32_dma_terminate_all(struct dma_chan *c) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); unsigned long flags; LIST_HEAD(head); spin_lock_irqsave(&chan->vchan.lock, flags); |
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if (chan->desc) { vchan_terminate_vdesc(&chan->desc->vdesc); if (chan->busy) stm32_dma_stop(chan); |
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chan->desc = NULL; } vchan_get_all_descriptors(&chan->vchan, &head); spin_unlock_irqrestore(&chan->vchan.lock, flags); vchan_dma_desc_free_list(&chan->vchan, &head); return 0; } |
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static void stm32_dma_synchronize(struct dma_chan *c) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); vchan_synchronize(&chan->vchan); } |
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static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); dev_dbg(chan2dev(chan), "SCR: 0x%08x ", scr); dev_dbg(chan2dev(chan), "NDTR: 0x%08x ", ndtr); dev_dbg(chan2dev(chan), "SPAR: 0x%08x ", spar); dev_dbg(chan2dev(chan), "SM0AR: 0x%08x ", sm0ar); dev_dbg(chan2dev(chan), "SM1AR: 0x%08x ", sm1ar); dev_dbg(chan2dev(chan), "SFCR: 0x%08x ", sfcr); } |
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static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan); |
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static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) |
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{ struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); struct virt_dma_desc *vdesc; struct stm32_dma_sg_req *sg_req; struct stm32_dma_chan_reg *reg; u32 status; int ret; ret = stm32_dma_disable_chan(chan); if (ret < 0) |
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return; |
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if (!chan->desc) { vdesc = vchan_next_desc(&chan->vchan); if (!vdesc) |
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return; |
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list_del(&vdesc->node); |
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chan->desc = to_stm32_dma_desc(vdesc); chan->next_sg = 0; } if (chan->next_sg == chan->desc->num_sgs) chan->next_sg = 0; sg_req = &chan->desc->sg_req[chan->next_sg]; reg = &sg_req->chan_reg; |
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reg->dma_scr &= ~STM32_DMA_SCR_EN; |
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stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); chan->next_sg++; /* Clear interrupt status if it is there */ status = stm32_dma_irq_status(chan); if (status) stm32_dma_irq_clear(chan, status); |
e57cb3b3f dmaengine: stm32-... |
570 571 |
if (chan->desc->cyclic) stm32_dma_configure_next_sg(chan); |
d8b468394 dmaengine: Add ST... |
572 573 574 575 576 577 578 |
stm32_dma_dump_reg(chan); /* Start DMA */ reg->dma_scr |= STM32_DMA_SCR_EN; stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); chan->busy = true; |
90ec93cb6 dmaengine: stm32:... |
579 580 |
dev_dbg(chan2dev(chan), "vchan %pK: started ", &chan->vchan); |
d8b468394 dmaengine: Add ST... |
581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 |
} static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); struct stm32_dma_sg_req *sg_req; u32 dma_scr, dma_sm0ar, dma_sm1ar, id; id = chan->id; dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); if (dma_scr & STM32_DMA_SCR_DBM) { if (chan->next_sg == chan->desc->num_sgs) chan->next_sg = 0; sg_req = &chan->desc->sg_req[chan->next_sg]; if (dma_scr & STM32_DMA_SCR_CT) { dma_sm0ar = sg_req->chan_reg.dma_sm0ar; stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x ", stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); } else { dma_sm1ar = sg_req->chan_reg.dma_sm1ar; stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x ", stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); } |
d8b468394 dmaengine: Add ST... |
611 612 613 614 615 616 617 618 |
} } static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) { if (chan->desc) { if (chan->desc->cyclic) { vchan_cyclic_callback(&chan->desc->vdesc); |
2b12c5580 dmaengine: stm32-... |
619 |
chan->next_sg++; |
d8b468394 dmaengine: Add ST... |
620 621 622 623 |
stm32_dma_configure_next_sg(chan); } else { chan->busy = false; if (chan->next_sg == chan->desc->num_sgs) { |
d8b468394 dmaengine: Add ST... |
624 625 626 627 628 629 630 631 632 633 634 635 |
vchan_cookie_complete(&chan->desc->vdesc); chan->desc = NULL; } stm32_dma_start_transfer(chan); } } } static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) { struct stm32_dma_chan *chan = devid; struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); |
ca4c72c01 dmaengine: stm32-... |
636 |
u32 status, scr, sfcr; |
d8b468394 dmaengine: Add ST... |
637 638 639 640 641 |
spin_lock(&chan->vchan.lock); status = stm32_dma_irq_status(chan); scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); |
ca4c72c01 dmaengine: stm32-... |
642 |
sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); |
d8b468394 dmaengine: Add ST... |
643 |
|
c2d86b1cd dmaengine: stm32-... |
644 |
if (status & STM32_DMA_TCI) { |
d8b468394 dmaengine: Add ST... |
645 |
stm32_dma_irq_clear(chan, STM32_DMA_TCI); |
c2d86b1cd dmaengine: stm32-... |
646 647 648 649 650 651 652 653 654 655 656 |
if (scr & STM32_DMA_SCR_TCIE) stm32_dma_handle_chan_done(chan); status &= ~STM32_DMA_TCI; } if (status & STM32_DMA_HTI) { stm32_dma_irq_clear(chan, STM32_DMA_HTI); status &= ~STM32_DMA_HTI; } if (status & STM32_DMA_FEI) { stm32_dma_irq_clear(chan, STM32_DMA_FEI); status &= ~STM32_DMA_FEI; |
ca4c72c01 dmaengine: stm32-... |
657 658 659 660 661 662 663 664 |
if (sfcr & STM32_DMA_SFCR_FEIE) { if (!(scr & STM32_DMA_SCR_EN)) dev_err(chan2dev(chan), "FIFO Error "); else dev_dbg(chan2dev(chan), "FIFO over/underrun "); } |
c2d86b1cd dmaengine: stm32-... |
665 |
} |
955b17665 dmaengine: stm32-... |
666 667 668 669 670 671 672 |
if (status & STM32_DMA_DMEI) { stm32_dma_irq_clear(chan, STM32_DMA_DMEI); status &= ~STM32_DMA_DMEI; if (sfcr & STM32_DMA_SCR_DMEIE) dev_dbg(chan2dev(chan), "Direct mode overrun "); } |
c2d86b1cd dmaengine: stm32-... |
673 |
if (status) { |
d8b468394 dmaengine: Add ST... |
674 675 676 |
stm32_dma_irq_clear(chan, status); dev_err(chan2dev(chan), "DMA error: status=0x%08x ", status); |
c2d86b1cd dmaengine: stm32-... |
677 678 679 |
if (!(scr & STM32_DMA_SCR_EN)) dev_err(chan2dev(chan), "chan disabled by HW "); |
d8b468394 dmaengine: Add ST... |
680 681 682 683 684 685 686 687 688 689 690 |
} spin_unlock(&chan->vchan.lock); return IRQ_HANDLED; } static void stm32_dma_issue_pending(struct dma_chan *c) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); unsigned long flags; |
d8b468394 dmaengine: Add ST... |
691 692 |
spin_lock_irqsave(&chan->vchan.lock, flags); |
8d1b76f03 dmaengine: stm32-... |
693 |
if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { |
90ec93cb6 dmaengine: stm32:... |
694 695 |
dev_dbg(chan2dev(chan), "vchan %pK: issued ", &chan->vchan); |
8d1b76f03 dmaengine: stm32-... |
696 |
stm32_dma_start_transfer(chan); |
e57cb3b3f dmaengine: stm32-... |
697 |
|
d8b468394 dmaengine: Add ST... |
698 699 700 701 702 703 |
} spin_unlock_irqrestore(&chan->vchan.lock, flags); } static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, enum dma_transfer_direction direction, |
a2b6103b7 dmaengine: stm32-... |
704 705 |
enum dma_slave_buswidth *buswidth, u32 buf_len) |
d8b468394 dmaengine: Add ST... |
706 707 708 709 |
{ enum dma_slave_buswidth src_addr_width, dst_addr_width; int src_bus_width, dst_bus_width; int src_burst_size, dst_burst_size; |
a2b6103b7 dmaengine: stm32-... |
710 |
u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst; |
955b17665 dmaengine: stm32-... |
711 |
u32 dma_scr, fifoth; |
d8b468394 dmaengine: Add ST... |
712 713 714 715 716 |
src_addr_width = chan->dma_sconfig.src_addr_width; dst_addr_width = chan->dma_sconfig.dst_addr_width; src_maxburst = chan->dma_sconfig.src_maxburst; dst_maxburst = chan->dma_sconfig.dst_maxburst; |
955b17665 dmaengine: stm32-... |
717 |
fifoth = chan->threshold; |
d8b468394 dmaengine: Add ST... |
718 719 720 |
switch (direction) { case DMA_MEM_TO_DEV: |
a2b6103b7 dmaengine: stm32-... |
721 |
/* Set device data size */ |
d8b468394 dmaengine: Add ST... |
722 723 724 |
dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); if (dst_bus_width < 0) return dst_bus_width; |
a2b6103b7 dmaengine: stm32-... |
725 726 727 |
/* Set device burst size */ dst_best_burst = stm32_dma_get_best_burst(buf_len, dst_maxburst, |
955b17665 dmaengine: stm32-... |
728 |
fifoth, |
a2b6103b7 dmaengine: stm32-... |
729 730 731 |
dst_addr_width); dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); |
d8b468394 dmaengine: Add ST... |
732 733 |
if (dst_burst_size < 0) return dst_burst_size; |
a2b6103b7 dmaengine: stm32-... |
734 |
/* Set memory data size */ |
955b17665 dmaengine: stm32-... |
735 |
src_addr_width = stm32_dma_get_max_width(buf_len, fifoth); |
a2b6103b7 dmaengine: stm32-... |
736 |
chan->mem_width = src_addr_width; |
d8b468394 dmaengine: Add ST... |
737 738 739 |
src_bus_width = stm32_dma_get_width(chan, src_addr_width); if (src_bus_width < 0) return src_bus_width; |
a2b6103b7 dmaengine: stm32-... |
740 741 742 743 |
/* Set memory burst size */ src_maxburst = STM32_DMA_MAX_BURST; src_best_burst = stm32_dma_get_best_burst(buf_len, src_maxburst, |
955b17665 dmaengine: stm32-... |
744 |
fifoth, |
a2b6103b7 dmaengine: stm32-... |
745 746 |
src_addr_width); src_burst_size = stm32_dma_get_burst(chan, src_best_burst); |
d8b468394 dmaengine: Add ST... |
747 748 749 750 751 752 753 754 |
if (src_burst_size < 0) return src_burst_size; dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) | STM32_DMA_SCR_PSIZE(dst_bus_width) | STM32_DMA_SCR_MSIZE(src_bus_width) | STM32_DMA_SCR_PBURST(dst_burst_size) | STM32_DMA_SCR_MBURST(src_burst_size); |
a2b6103b7 dmaengine: stm32-... |
755 756 |
/* Set FIFO threshold */ chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; |
955b17665 dmaengine: stm32-... |
757 758 |
if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); |
a2b6103b7 dmaengine: stm32-... |
759 760 |
/* Set peripheral address */ |
d8b468394 dmaengine: Add ST... |
761 762 763 764 765 |
chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; *buswidth = dst_addr_width; break; case DMA_DEV_TO_MEM: |
a2b6103b7 dmaengine: stm32-... |
766 |
/* Set device data size */ |
d8b468394 dmaengine: Add ST... |
767 768 769 |
src_bus_width = stm32_dma_get_width(chan, src_addr_width); if (src_bus_width < 0) return src_bus_width; |
a2b6103b7 dmaengine: stm32-... |
770 771 772 |
/* Set device burst size */ src_best_burst = stm32_dma_get_best_burst(buf_len, src_maxburst, |
955b17665 dmaengine: stm32-... |
773 |
fifoth, |
a2b6103b7 dmaengine: stm32-... |
774 775 776 |
src_addr_width); chan->mem_burst = src_best_burst; src_burst_size = stm32_dma_get_burst(chan, src_best_burst); |
d8b468394 dmaengine: Add ST... |
777 778 |
if (src_burst_size < 0) return src_burst_size; |
a2b6103b7 dmaengine: stm32-... |
779 |
/* Set memory data size */ |
955b17665 dmaengine: stm32-... |
780 |
dst_addr_width = stm32_dma_get_max_width(buf_len, fifoth); |
a2b6103b7 dmaengine: stm32-... |
781 |
chan->mem_width = dst_addr_width; |
d8b468394 dmaengine: Add ST... |
782 783 784 |
dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); if (dst_bus_width < 0) return dst_bus_width; |
a2b6103b7 dmaengine: stm32-... |
785 786 787 788 |
/* Set memory burst size */ dst_maxburst = STM32_DMA_MAX_BURST; dst_best_burst = stm32_dma_get_best_burst(buf_len, dst_maxburst, |
955b17665 dmaengine: stm32-... |
789 |
fifoth, |
a2b6103b7 dmaengine: stm32-... |
790 791 792 |
dst_addr_width); chan->mem_burst = dst_best_burst; dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); |
d8b468394 dmaengine: Add ST... |
793 794 795 796 797 798 799 800 |
if (dst_burst_size < 0) return dst_burst_size; dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) | STM32_DMA_SCR_PSIZE(src_bus_width) | STM32_DMA_SCR_MSIZE(dst_bus_width) | STM32_DMA_SCR_PBURST(src_burst_size) | STM32_DMA_SCR_MBURST(dst_burst_size); |
a2b6103b7 dmaengine: stm32-... |
801 802 |
/* Set FIFO threshold */ chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; |
955b17665 dmaengine: stm32-... |
803 804 |
if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); |
a2b6103b7 dmaengine: stm32-... |
805 806 |
/* Set peripheral address */ |
d8b468394 dmaengine: Add ST... |
807 808 809 810 811 812 813 814 815 |
chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; *buswidth = chan->dma_sconfig.src_addr_width; break; default: dev_err(chan2dev(chan), "Dma direction is not supported "); return -EINVAL; } |
a2b6103b7 dmaengine: stm32-... |
816 |
stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); |
d8b468394 dmaengine: Add ST... |
817 |
|
a2b6103b7 dmaengine: stm32-... |
818 |
/* Set DMA control register */ |
d8b468394 dmaengine: Add ST... |
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 |
chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK | STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK); chan->chan_reg.dma_scr |= dma_scr; return 0; } static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs) { memset(regs, 0, sizeof(struct stm32_dma_chan_reg)); } static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( struct dma_chan *c, struct scatterlist *sgl, u32 sg_len, enum dma_transfer_direction direction, unsigned long flags, void *context) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); struct stm32_dma_desc *desc; struct scatterlist *sg; enum dma_slave_buswidth buswidth; u32 nb_data_items; int i, ret; if (!chan->config_init) { dev_err(chan2dev(chan), "dma channel is not configured "); return NULL; } if (sg_len < 1) { dev_err(chan2dev(chan), "Invalid segment length %d ", sg_len); return NULL; } |
402096cb5 dmaengine: stm32-... |
855 |
desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT); |
d8b468394 dmaengine: Add ST... |
856 857 |
if (!desc) return NULL; |
d8b468394 dmaengine: Add ST... |
858 859 860 861 862 863 864 |
/* Set peripheral flow controller */ if (chan->dma_sconfig.device_fc) chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; else chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; for_each_sg(sgl, sg, sg_len, i) { |
a2b6103b7 dmaengine: stm32-... |
865 866 867 868 |
ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, sg_dma_len(sg)); if (ret < 0) goto err; |
d8b468394 dmaengine: Add ST... |
869 870 871 |
desc->sg_req[i].len = sg_dma_len(sg); nb_data_items = desc->sg_req[i].len / buswidth; |
80a76952a dmaengine: stm32-... |
872 |
if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { |
d8b468394 dmaengine: Add ST... |
873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 |
dev_err(chan2dev(chan), "nb items not supported "); goto err; } stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; } desc->num_sgs = sg_len; desc->cyclic = false; return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); err: kfree(desc); return NULL; } static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, size_t period_len, enum dma_transfer_direction direction, unsigned long flags) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); struct stm32_dma_desc *desc; enum dma_slave_buswidth buswidth; u32 num_periods, nb_data_items; int i, ret; if (!buf_len || !period_len) { dev_err(chan2dev(chan), "Invalid buffer/period len "); return NULL; } if (!chan->config_init) { dev_err(chan2dev(chan), "dma channel is not configured "); return NULL; } if (buf_len % period_len) { dev_err(chan2dev(chan), "buf_len not multiple of period_len "); return NULL; } /* * We allow to take more number of requests till DMA is * not started. The driver will loop over all requests. * Once DMA is started then new requests can be queued only after * terminating the DMA. */ if (chan->busy) { dev_err(chan2dev(chan), "Request not allowed when dma busy "); return NULL; } |
a2b6103b7 dmaengine: stm32-... |
937 |
ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len); |
d8b468394 dmaengine: Add ST... |
938 939 940 941 |
if (ret < 0) return NULL; nb_data_items = period_len / buswidth; |
80a76952a dmaengine: stm32-... |
942 |
if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { |
d8b468394 dmaengine: Add ST... |
943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 |
dev_err(chan2dev(chan), "number of items not supported "); return NULL; } /* Enable Circular mode or double buffer mode */ if (buf_len == period_len) chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; else chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; /* Clear periph ctrl if client set it */ chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; num_periods = buf_len / period_len; |
402096cb5 dmaengine: stm32-... |
958 |
desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT); |
d8b468394 dmaengine: Add ST... |
959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 |
if (!desc) return NULL; for (i = 0; i < num_periods; i++) { desc->sg_req[i].len = period_len; stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; buf_addr += period_len; } desc->num_sgs = num_periods; desc->cyclic = true; return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( struct dma_chan *c, dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); |
a2b6103b7 dmaengine: stm32-... |
986 |
enum dma_slave_buswidth max_width; |
d8b468394 dmaengine: Add ST... |
987 988 |
struct stm32_dma_desc *desc; size_t xfer_count, offset; |
a2b6103b7 dmaengine: stm32-... |
989 |
u32 num_sgs, best_burst, dma_burst, threshold; |
d8b468394 dmaengine: Add ST... |
990 |
int i; |
80a76952a dmaengine: stm32-... |
991 |
num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); |
402096cb5 dmaengine: stm32-... |
992 |
desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT); |
d8b468394 dmaengine: Add ST... |
993 994 |
if (!desc) return NULL; |
a2b6103b7 dmaengine: stm32-... |
995 |
threshold = chan->threshold; |
d8b468394 dmaengine: Add ST... |
996 997 |
for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { xfer_count = min_t(size_t, len - offset, |
80a76952a dmaengine: stm32-... |
998 |
STM32_DMA_ALIGNED_MAX_DATA_ITEMS); |
d8b468394 dmaengine: Add ST... |
999 |
|
a2b6103b7 dmaengine: stm32-... |
1000 1001 1002 1003 1004 |
/* Compute best burst size */ max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST, threshold, max_width); dma_burst = stm32_dma_get_burst(chan, best_burst); |
d8b468394 dmaengine: Add ST... |
1005 1006 1007 1008 |
stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); desc->sg_req[i].chan_reg.dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) | |
a2b6103b7 dmaengine: stm32-... |
1009 1010 |
STM32_DMA_SCR_PBURST(dma_burst) | STM32_DMA_SCR_MBURST(dma_burst) | |
d8b468394 dmaengine: Add ST... |
1011 1012 1013 1014 |
STM32_DMA_SCR_MINC | STM32_DMA_SCR_PINC | STM32_DMA_SCR_TCIE | STM32_DMA_SCR_TEIE; |
a2b6103b7 dmaengine: stm32-... |
1015 1016 1017 |
desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold); |
d8b468394 dmaengine: Add ST... |
1018 1019 1020 |
desc->sg_req[i].chan_reg.dma_spar = src + offset; desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; |
a2b6103b7 dmaengine: stm32-... |
1021 |
desc->sg_req[i].len = xfer_count; |
d8b468394 dmaengine: Add ST... |
1022 1023 1024 1025 1026 1027 1028 |
} desc->num_sgs = num_sgs; desc->cyclic = false; return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); } |
2b12c5580 dmaengine: stm32-... |
1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 |
static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) { u32 dma_scr, width, ndtr; struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); width = STM32_DMA_SCR_PSIZE_GET(dma_scr); ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); return ndtr << width; } |
2a4885abf dmaengine: stm32-... |
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 |
/** * stm32_dma_is_current_sg - check that expected sg_req is currently transferred * @chan: dma channel * * This function called when IRQ are disable, checks that the hardware has not * switched on the next transfer in double buffer mode. The test is done by * comparing the next_sg memory address with the hardware related register * (based on CT bit value). * * Returns true if expected current transfer is still running or double * buffer mode is not activated. */ static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) { struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); struct stm32_dma_sg_req *sg_req; u32 dma_scr, dma_smar, id; id = chan->id; dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); if (!(dma_scr & STM32_DMA_SCR_DBM)) return true; sg_req = &chan->desc->sg_req[chan->next_sg]; if (dma_scr & STM32_DMA_SCR_CT) { dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)); return (dma_smar == sg_req->chan_reg.dma_sm0ar); } dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)); return (dma_smar == sg_req->chan_reg.dma_sm1ar); } |
d8b468394 dmaengine: Add ST... |
1075 1076 1077 1078 |
static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, struct stm32_dma_desc *desc, u32 next_sg) { |
a2b6103b7 dmaengine: stm32-... |
1079 |
u32 modulo, burst_size; |
2a4885abf dmaengine: stm32-... |
1080 1081 1082 |
u32 residue; u32 n_sg = next_sg; struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; |
d8b468394 dmaengine: Add ST... |
1083 |
int i; |
2b12c5580 dmaengine: stm32-... |
1084 |
/* |
2a4885abf dmaengine: stm32-... |
1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 |
* Calculate the residue means compute the descriptors * information: * - the sg_req currently transferred * - the Hardware remaining position in this sg (NDTR bits field). * * A race condition may occur if DMA is running in cyclic or double * buffer mode, since the DMA register are automatically reloaded at end * of period transfer. The hardware may have switched to the next * transfer (CT bit updated) just before the position (SxNDTR reg) is * read. * In this case the SxNDTR reg could (or not) correspond to the new * transfer position, and not the expected one. * The strategy implemented in the stm32 driver is to: * - read the SxNDTR register * - crosscheck that hardware is still in current transfer. * In case of switch, we can assume that the DMA is at the beginning of * the next transfer. So we approximate the residue in consequence, by * pointing on the beginning of next transfer. * * This race condition doesn't apply for none cyclic mode, as double * buffer is not used. In such situation registers are updated by the * software. |
2b12c5580 dmaengine: stm32-... |
1107 |
*/ |
2a4885abf dmaengine: stm32-... |
1108 1109 1110 1111 1112 1113 1114 1115 |
residue = stm32_dma_get_remaining_bytes(chan); if (!stm32_dma_is_current_sg(chan)) { n_sg++; if (n_sg == chan->desc->num_sgs) n_sg = 0; residue = sg_req->len; |
a2b6103b7 dmaengine: stm32-... |
1116 |
} |
d8b468394 dmaengine: Add ST... |
1117 |
|
2b12c5580 dmaengine: stm32-... |
1118 |
/* |
2a4885abf dmaengine: stm32-... |
1119 1120 1121 1122 1123 |
* In cyclic mode, for the last period, residue = remaining bytes * from NDTR, * else for all other periods in cyclic mode, and in sg mode, * residue = remaining bytes from NDTR + remaining * periods/sg to be transferred |
2b12c5580 dmaengine: stm32-... |
1124 |
*/ |
2a4885abf dmaengine: stm32-... |
1125 1126 1127 |
if (!chan->desc->cyclic || n_sg != 0) for (i = n_sg; i < desc->num_sgs; i++) residue += desc->sg_req[i].len; |
d8b468394 dmaengine: Add ST... |
1128 |
|
a2b6103b7 dmaengine: stm32-... |
1129 1130 1131 1132 1133 1134 1135 |
if (!chan->mem_burst) return residue; burst_size = chan->mem_burst * chan->mem_width; modulo = residue % burst_size; if (modulo) residue = residue - modulo + burst_size; |
d8b468394 dmaengine: Add ST... |
1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 |
return residue; } static enum dma_status stm32_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie, struct dma_tx_state *state) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); struct virt_dma_desc *vdesc; enum dma_status status; unsigned long flags; |
57b5a3213 dmaengine: stm32-... |
1147 |
u32 residue = 0; |
d8b468394 dmaengine: Add ST... |
1148 1149 |
status = dma_cookie_status(c, cookie, state); |
249d55311 dmaengine: stm32-... |
1150 |
if (status == DMA_COMPLETE || !state) |
d8b468394 dmaengine: Add ST... |
1151 1152 1153 1154 |
return status; spin_lock_irqsave(&chan->vchan.lock, flags); vdesc = vchan_find_desc(&chan->vchan, cookie); |
57b5a3213 dmaengine: stm32-... |
1155 |
if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) |
d8b468394 dmaengine: Add ST... |
1156 1157 |
residue = stm32_dma_desc_residue(chan, chan->desc, chan->next_sg); |
57b5a3213 dmaengine: stm32-... |
1158 |
else if (vdesc) |
d8b468394 dmaengine: Add ST... |
1159 1160 |
residue = stm32_dma_desc_residue(chan, to_stm32_dma_desc(vdesc), 0); |
d8b468394 dmaengine: Add ST... |
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 |
dma_set_residue(state, residue); spin_unlock_irqrestore(&chan->vchan.lock, flags); return status; } static int stm32_dma_alloc_chan_resources(struct dma_chan *c) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); int ret; chan->config_init = false; |
48bc73ba1 dmaengine: stm32-... |
1175 1176 1177 |
ret = pm_runtime_get_sync(dmadev->ddev.dev); if (ret < 0) |
d8b468394 dmaengine: Add ST... |
1178 |
return ret; |
d8b468394 dmaengine: Add ST... |
1179 1180 1181 |
ret = stm32_dma_disable_chan(chan); if (ret < 0) |
48bc73ba1 dmaengine: stm32-... |
1182 |
pm_runtime_put(dmadev->ddev.dev); |
d8b468394 dmaengine: Add ST... |
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 |
return ret; } static void stm32_dma_free_chan_resources(struct dma_chan *c) { struct stm32_dma_chan *chan = to_stm32_dma_chan(c); struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); unsigned long flags; dev_dbg(chan2dev(chan), "Freeing channel %d ", chan->id); if (chan->busy) { spin_lock_irqsave(&chan->vchan.lock, flags); stm32_dma_stop(chan); chan->desc = NULL; spin_unlock_irqrestore(&chan->vchan.lock, flags); } |
48bc73ba1 dmaengine: stm32-... |
1202 |
pm_runtime_put(dmadev->ddev.dev); |
d8b468394 dmaengine: Add ST... |
1203 1204 1205 1206 1207 1208 1209 1210 |
vchan_free_chan_resources(to_virt_chan(c)); } static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) { kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); } |
e97adb49b dmaengine: stm32-... |
1211 |
static void stm32_dma_set_config(struct stm32_dma_chan *chan, |
249d55311 dmaengine: stm32-... |
1212 |
struct stm32_dma_cfg *cfg) |
d8b468394 dmaengine: Add ST... |
1213 1214 1215 1216 1217 1218 1219 1220 |
{ stm32_dma_clear_reg(&chan->chan_reg); chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); /* Enable Interrupts */ chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; |
951f44cb6 dmaengine: stm32-... |
1221 |
chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); |
955b17665 dmaengine: stm32-... |
1222 1223 |
if (STM32_DMA_DIRECT_MODE_GET(cfg->features)) chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; |
d8b468394 dmaengine: Add ST... |
1224 1225 1226 1227 1228 1229 |
} static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec, struct of_dma *ofdma) { struct stm32_dma_device *dmadev = ofdma->of_dma_data; |
5df4eb453 dmaengine: stm32-... |
1230 |
struct device *dev = dmadev->ddev.dev; |
d8b468394 dmaengine: Add ST... |
1231 1232 1233 |
struct stm32_dma_cfg cfg; struct stm32_dma_chan *chan; struct dma_chan *c; |
5df4eb453 dmaengine: stm32-... |
1234 1235 1236 |
if (dma_spec->args_count < 4) { dev_err(dev, "Bad number of cells "); |
d8b468394 dmaengine: Add ST... |
1237 |
return NULL; |
5df4eb453 dmaengine: stm32-... |
1238 |
} |
d8b468394 dmaengine: Add ST... |
1239 1240 1241 1242 |
cfg.channel_id = dma_spec->args[0]; cfg.request_line = dma_spec->args[1]; cfg.stream_config = dma_spec->args[2]; |
951f44cb6 dmaengine: stm32-... |
1243 |
cfg.features = dma_spec->args[3]; |
d8b468394 dmaengine: Add ST... |
1244 |
|
249d55311 dmaengine: stm32-... |
1245 1246 |
if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS || cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) { |
5df4eb453 dmaengine: stm32-... |
1247 1248 |
dev_err(dev, "Bad channel and/or request id "); |
d8b468394 dmaengine: Add ST... |
1249 |
return NULL; |
5df4eb453 dmaengine: stm32-... |
1250 |
} |
d8b468394 dmaengine: Add ST... |
1251 |
|
d8b468394 dmaengine: Add ST... |
1252 1253 1254 |
chan = &dmadev->chan[cfg.channel_id]; c = dma_get_slave_channel(&chan->vchan.chan); |
5df4eb453 dmaengine: stm32-... |
1255 |
if (!c) { |
041cf7e06 dmaengine: stm32-... |
1256 1257 |
dev_err(dev, "No more channels available "); |
5df4eb453 dmaengine: stm32-... |
1258 1259 1260 1261 |
return NULL; } stm32_dma_set_config(chan, &cfg); |
d8b468394 dmaengine: Add ST... |
1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 |
return c; } static const struct of_device_id stm32_dma_of_match[] = { { .compatible = "st,stm32-dma", }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, stm32_dma_of_match); static int stm32_dma_probe(struct platform_device *pdev) { struct stm32_dma_chan *chan; struct stm32_dma_device *dmadev; struct dma_device *dd; const struct of_device_id *match; struct resource *res; |
8cf1e0fc5 dmaengine: stm32-... |
1279 |
struct reset_control *rst; |
d8b468394 dmaengine: Add ST... |
1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 |
int i, ret; match = of_match_device(stm32_dma_of_match, &pdev->dev); if (!match) { dev_err(&pdev->dev, "Error: No device match found "); return -ENODEV; } dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); if (!dmadev) return -ENOMEM; dd = &dmadev->ddev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); dmadev->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(dmadev->base)) return PTR_ERR(dmadev->base); dmadev->clk = devm_clk_get(&pdev->dev, NULL); |
1c966e1d9 dmaengine: stm32:... |
1301 1302 1303 |
if (IS_ERR(dmadev->clk)) return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock "); |
d8b468394 dmaengine: Add ST... |
1304 |
|
48bc73ba1 dmaengine: stm32-... |
1305 1306 1307 1308 1309 1310 |
ret = clk_prepare_enable(dmadev->clk); if (ret < 0) { dev_err(&pdev->dev, "clk_prep_enable error: %d ", ret); return ret; } |
d8b468394 dmaengine: Add ST... |
1311 1312 |
dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, "st,mem2mem"); |
8cf1e0fc5 dmaengine: stm32-... |
1313 |
rst = devm_reset_control_get(&pdev->dev, NULL); |
615eee2c4 dmaengine: stm32-... |
1314 1315 1316 1317 1318 |
if (IS_ERR(rst)) { ret = PTR_ERR(rst); if (ret == -EPROBE_DEFER) goto clk_free; } else { |
8cf1e0fc5 dmaengine: stm32-... |
1319 |
reset_control_assert(rst); |
d8b468394 dmaengine: Add ST... |
1320 |
udelay(2); |
8cf1e0fc5 dmaengine: stm32-... |
1321 |
reset_control_deassert(rst); |
d8b468394 dmaengine: Add ST... |
1322 |
} |
d7a9e4260 dmaengine: stm32-... |
1323 |
dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); |
d8b468394 dmaengine: Add ST... |
1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 |
dma_cap_set(DMA_SLAVE, dd->cap_mask); dma_cap_set(DMA_PRIVATE, dd->cap_mask); dma_cap_set(DMA_CYCLIC, dd->cap_mask); dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; dd->device_free_chan_resources = stm32_dma_free_chan_resources; dd->device_tx_status = stm32_dma_tx_status; dd->device_issue_pending = stm32_dma_issue_pending; dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; dd->device_config = stm32_dma_slave_config; dd->device_terminate_all = stm32_dma_terminate_all; |
dc8086751 dmaengine: stm32-... |
1335 |
dd->device_synchronize = stm32_dma_synchronize; |
d8b468394 dmaengine: Add ST... |
1336 1337 1338 1339 1340 1341 1342 1343 |
dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
32ce10883 dmaengine: stm32-... |
1344 |
dd->copy_align = DMAENGINE_ALIGN_32_BYTES; |
276b0046f dmaengine: stm32-... |
1345 |
dd->max_burst = STM32_DMA_MAX_BURST; |
22a0bb297 dmaengine: stm32-... |
1346 |
dd->descriptor_reuse = true; |
d8b468394 dmaengine: Add ST... |
1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 |
dd->dev = &pdev->dev; INIT_LIST_HEAD(&dd->channels); if (dmadev->mem2mem) { dma_cap_set(DMA_MEMCPY, dd->cap_mask); dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; dd->directions |= BIT(DMA_MEM_TO_MEM); } for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { chan = &dmadev->chan[i]; chan->id = i; chan->vchan.desc_free = stm32_dma_desc_free; vchan_init(&chan->vchan, dd); } ret = dma_async_device_register(dd); if (ret) |
48bc73ba1 dmaengine: stm32-... |
1365 |
goto clk_free; |
d8b468394 dmaengine: Add ST... |
1366 1367 1368 |
for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { chan = &dmadev->chan[i]; |
c6504be53 dmaengine: stm32-... |
1369 |
ret = platform_get_irq(pdev, i); |
e17be6e1b dmaengine: Remove... |
1370 |
if (ret < 0) |
d8b468394 dmaengine: Add ST... |
1371 |
goto err_unregister; |
c6504be53 dmaengine: stm32-... |
1372 |
chan->irq = ret; |
d8b468394 dmaengine: Add ST... |
1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 |
ret = devm_request_irq(&pdev->dev, chan->irq, stm32_dma_chan_irq, 0, dev_name(chan2dev(chan)), chan); if (ret) { dev_err(&pdev->dev, "request_irq failed with err %d channel %d ", ret, i); goto err_unregister; } } ret = of_dma_controller_register(pdev->dev.of_node, stm32_dma_of_xlate, dmadev); if (ret < 0) { dev_err(&pdev->dev, "STM32 DMA DMA OF registration failed %d ", ret); goto err_unregister; } platform_set_drvdata(pdev, dmadev); |
48bc73ba1 dmaengine: stm32-... |
1395 1396 1397 1398 |
pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); pm_runtime_get_noresume(&pdev->dev); pm_runtime_put(&pdev->dev); |
d8b468394 dmaengine: Add ST... |
1399 1400 1401 1402 1403 1404 1405 |
dev_info(&pdev->dev, "STM32 DMA driver registered "); return 0; err_unregister: dma_async_device_unregister(dd); |
48bc73ba1 dmaengine: stm32-... |
1406 1407 |
clk_free: clk_disable_unprepare(dmadev->clk); |
d8b468394 dmaengine: Add ST... |
1408 1409 1410 |
return ret; } |
48bc73ba1 dmaengine: stm32-... |
1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 |
#ifdef CONFIG_PM static int stm32_dma_runtime_suspend(struct device *dev) { struct stm32_dma_device *dmadev = dev_get_drvdata(dev); clk_disable_unprepare(dmadev->clk); return 0; } static int stm32_dma_runtime_resume(struct device *dev) { struct stm32_dma_device *dmadev = dev_get_drvdata(dev); int ret; ret = clk_prepare_enable(dmadev->clk); if (ret) { dev_err(dev, "failed to prepare_enable clock "); return ret; } return 0; } #endif |
05f8740a0 dmaengine: stm32-... |
1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 |
#ifdef CONFIG_PM_SLEEP static int stm32_dma_suspend(struct device *dev) { struct stm32_dma_device *dmadev = dev_get_drvdata(dev); int id, ret, scr; ret = pm_runtime_get_sync(dev); if (ret < 0) return ret; for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) { scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); if (scr & STM32_DMA_SCR_EN) { dev_warn(dev, "Suspend is prevented by Chan %i ", id); return -EBUSY; } } pm_runtime_put_sync(dev); pm_runtime_force_suspend(dev); return 0; } static int stm32_dma_resume(struct device *dev) { return pm_runtime_force_resume(dev); } #endif |
48bc73ba1 dmaengine: stm32-... |
1467 |
static const struct dev_pm_ops stm32_dma_pm_ops = { |
05f8740a0 dmaengine: stm32-... |
1468 |
SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume) |
48bc73ba1 dmaengine: stm32-... |
1469 1470 1471 |
SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend, stm32_dma_runtime_resume, NULL) }; |
d8b468394 dmaengine: Add ST... |
1472 1473 1474 1475 |
static struct platform_driver stm32_dma_driver = { .driver = { .name = "stm32-dma", .of_match_table = stm32_dma_of_match, |
48bc73ba1 dmaengine: stm32-... |
1476 |
.pm = &stm32_dma_pm_ops, |
d8b468394 dmaengine: Add ST... |
1477 |
}, |
615eee2c4 dmaengine: stm32-... |
1478 |
.probe = stm32_dma_probe, |
d8b468394 dmaengine: Add ST... |
1479 1480 1481 1482 |
}; static int __init stm32_dma_init(void) { |
615eee2c4 dmaengine: stm32-... |
1483 |
return platform_driver_register(&stm32_dma_driver); |
d8b468394 dmaengine: Add ST... |
1484 1485 |
} subsys_initcall(stm32_dma_init); |