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drivers/watchdog/of_xilinx_wdt.c
7.39 KB
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// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Watchdog Device Driver for Xilinx axi/xps_timebase_wdt * |
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* (C) Copyright 2013 - 2014 Xilinx, Inc. |
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* (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/module.h> #include <linux/types.h> #include <linux/kernel.h> |
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#include <linux/ioport.h> #include <linux/watchdog.h> #include <linux/io.h> |
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#include <linux/of.h> #include <linux/of_device.h> #include <linux/of_address.h> /* Register offsets for the Wdt device */ #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ /* Control/Status Register Masks */ #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ /* Control/Status Register 0/1 bits */ #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ /* SelfTest constants */ #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 #define XWT_TIMER_FAILED 0xFFFFFFFF #define WATCHDOG_NAME "Xilinx Watchdog" |
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struct xwdt_device { |
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void __iomem *base; |
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u32 wdt_interval; |
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spinlock_t spinlock; struct watchdog_device xilinx_wdt_wdd; |
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struct clk *clk; |
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}; |
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static int xilinx_wdt_start(struct watchdog_device *wdd) |
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{ |
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int ret; |
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u32 control_status_reg; |
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struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
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ret = clk_enable(xdev->clk); if (ret) { dev_err(wdd->parent, "Failed to enable clock "); return ret; } |
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spin_lock(&xdev->spinlock); |
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/* Clean previous status and enable the watchdog timer */ |
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control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
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control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), |
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xdev->base + XWT_TWCSR0_OFFSET); |
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iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); |
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spin_unlock(&xdev->spinlock); |
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return 0; |
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} |
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static int xilinx_wdt_stop(struct watchdog_device *wdd) |
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{ |
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u32 control_status_reg; |
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struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
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spin_lock(&xdev->spinlock); |
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control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
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iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), |
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xdev->base + XWT_TWCSR0_OFFSET); |
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iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); |
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spin_unlock(&xdev->spinlock); |
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clk_disable(xdev->clk); |
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pr_info("Stopped! "); |
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return 0; |
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} |
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static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
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{ |
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u32 control_status_reg; |
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struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
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spin_lock(&xdev->spinlock); |
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control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
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control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
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iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); |
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spin_unlock(&xdev->spinlock); |
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return 0; } |
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static const struct watchdog_info xilinx_wdt_ident = { .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .firmware_version = 1, .identity = WATCHDOG_NAME, }; |
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static const struct watchdog_ops xilinx_wdt_ops = { .owner = THIS_MODULE, .start = xilinx_wdt_start, .stop = xilinx_wdt_stop, .ping = xilinx_wdt_keepalive, }; |
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static u32 xwdt_selftest(struct xwdt_device *xdev) |
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{ int i; u32 timer_value1; u32 timer_value2; |
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spin_lock(&xdev->spinlock); |
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timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
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for (i = 0; ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && (timer_value2 == timer_value1)); i++) { |
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timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
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} |
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spin_unlock(&xdev->spinlock); |
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if (timer_value2 != timer_value1) return ~XWT_TIMER_FAILED; else return XWT_TIMER_FAILED; } |
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static void xwdt_clk_disable_unprepare(void *data) { clk_disable_unprepare(data); } |
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static int xwdt_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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int rc; |
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u32 pfreq = 0, enable_once = 0; |
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struct xwdt_device *xdev; |
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struct watchdog_device *xilinx_wdt_wdd; |
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xdev = devm_kzalloc(dev, sizeof(*xdev), GFP_KERNEL); |
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if (!xdev) return -ENOMEM; xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; xilinx_wdt_wdd->info = &xilinx_wdt_ident; xilinx_wdt_wdd->ops = &xilinx_wdt_ops; |
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xilinx_wdt_wdd->parent = dev; |
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xdev->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(xdev->base)) return PTR_ERR(xdev->base); |
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rc = of_property_read_u32(dev->of_node, "xlnx,wdt-interval", |
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&xdev->wdt_interval); |
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if (rc) |
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dev_warn(dev, "Parameter \"xlnx,wdt-interval\" not found "); |
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rc = of_property_read_u32(dev->of_node, "xlnx,wdt-enable-once", |
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&enable_once); if (rc) |
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dev_warn(dev, |
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"Parameter \"xlnx,wdt-enable-once\" not found "); |
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watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); |
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xdev->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(xdev->clk)) { if (PTR_ERR(xdev->clk) != -ENOENT) return PTR_ERR(xdev->clk); /* * Clock framework support is optional, continue on * anyways if we don't find a matching clock. */ xdev->clk = NULL; |
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rc = of_property_read_u32(dev->of_node, "clock-frequency", |
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&pfreq); if (rc) |
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dev_warn(dev, |
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"The watchdog clock freq cannot be obtained "); } else { pfreq = clk_get_rate(xdev->clk); } |
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/* * Twice of the 2^wdt_interval / freq because the first wdt overflow is * ignored (interrupt), reset is only generated at second wdt overflow */ |
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if (pfreq && xdev->wdt_interval) |
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xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / |
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pfreq); |
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spin_lock_init(&xdev->spinlock); watchdog_set_drvdata(xilinx_wdt_wdd, xdev); |
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rc = clk_prepare_enable(xdev->clk); if (rc) { |
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dev_err(dev, "unable to enable clock "); |
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return rc; } |
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rc = devm_add_action_or_reset(dev, xwdt_clk_disable_unprepare, xdev->clk); if (rc) return rc; |
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rc = xwdt_selftest(xdev); |
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if (rc == XWT_TIMER_FAILED) { |
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dev_err(dev, "SelfTest routine error "); return rc; |
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} |
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rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd); |
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if (rc) |
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return rc; |
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clk_disable(xdev->clk); |
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dev_info(dev, "Xilinx Watchdog Timer at %p with timeout %ds ", |
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xdev->base, xilinx_wdt_wdd->timeout); platform_set_drvdata(pdev, xdev); |
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return 0; |
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} |
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/** * xwdt_suspend - Suspend the device. * * @dev: handle to the device structure. * Return: 0 always. */ static int __maybe_unused xwdt_suspend(struct device *dev) { |
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struct xwdt_device *xdev = dev_get_drvdata(dev); |
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if (watchdog_active(&xdev->xilinx_wdt_wdd)) xilinx_wdt_stop(&xdev->xilinx_wdt_wdd); return 0; } /** * xwdt_resume - Resume the device. * * @dev: handle to the device structure. * Return: 0 on success, errno otherwise. */ static int __maybe_unused xwdt_resume(struct device *dev) { |
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struct xwdt_device *xdev = dev_get_drvdata(dev); |
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int ret = 0; if (watchdog_active(&xdev->xilinx_wdt_wdd)) ret = xilinx_wdt_start(&xdev->xilinx_wdt_wdd); return ret; } static SIMPLE_DEV_PM_OPS(xwdt_pm_ops, xwdt_suspend, xwdt_resume); |
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/* Match table for of_platform binding */ |
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static const struct of_device_id xwdt_of_match[] = { |
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{ .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
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{ .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, {}, }; MODULE_DEVICE_TABLE(of, xwdt_of_match); static struct platform_driver xwdt_driver = { .probe = xwdt_probe, |
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.driver = { |
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.name = WATCHDOG_NAME, .of_match_table = xwdt_of_match, |
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.pm = &xwdt_pm_ops, |
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}, }; |
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module_platform_driver(xwdt_driver); |
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MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); MODULE_DESCRIPTION("Xilinx Watchdog driver"); |
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MODULE_LICENSE("GPL"); |