Eric Lee / smarc-fsl-linux-kernel

Blame view

arch/arm64/boot/dts/freescale/fsl-imx8qm-enet2-tja1100.dtsi 2.02 KB
edit raw normal view history
81f7e3824   Eric Lee   Initial Release, ... 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
 
  /*
   * Copyright 2018 NXP
   *
   * This program is free software; you can redistribute it and/or
   * modify it under the terms of the GNU General Public License
   * as published by the Free Software Foundation; either version 2
   * of the License, or (at your option) any later version.
   *
   * This program is distributed in the hope that it will be useful,
   * but WITHOUT ANY WARRANTY; without even the implied warranty of
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   * GNU General Public License for more details.
   */
  
  /* fec1 cannot attach to ethphy0 since the PHY address
   * conflict with ethphy2. So eth0 should not work.
   * There still enable fec1 to share the MDIO bus for fec2 due
   * to board limitation.
   */
  &fec1 {
  	/* PHY address should rework to 2 */
  	phy-handle = <&ethphy2>;
  
  	mdio {
  		#address-cells = <1>;
  		#size-cells = <0>;
  
  		ethphy0: ethernet-phy@0 {
  			compatible = "ethernet-phy-ieee802.3-c22";
  			reg = <0>;
  			tja110x,refclk_in;
  			/delete-property/ at803x,eee-disabled;
  			/delete-property/ at803x,vddio-1p8v;
  		};
  
  		ethphy2: ethernet-phy@2 {
  			compatible = "ethernet-phy-ieee802.3-c22";
  			reg = <2>;
  			at803x,eee-disabled;
  			at803x,vddio-1p8v;
  		};
  	};
  };
  
  &fec2 {
  	pinctrl-0 = <&pinctrl_fec2_rmii>;
  	clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
  		 <&clk IMX8QM_ENET1_AHB_CLK>,
  		 <&clk IMX8QM_ENET1_REF_50MHZ_CLK>,
  		 <&clk IMX8QM_ENET1_PTP_CLK>,
  		 <&clk IMX8QM_ENET1_TX_CLK>;
  	phy-mode = "rmii";
  	phy-handle = <&ethphy0>;
  	/delete-property/ phy-supply;
  };
  
  &iomuxc {
  	imx8qm-mek {
  		pinctrl_fec2_rmii: fec2rmiigrp {
  			fsl,pins = <
  				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT	0x06000020
  				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000020
  				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000020
  				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER	0x06000020
  				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000020
  				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000020
  				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000020
  				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000020
  			>;
  		};
  	};
  };