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drivers/clocksource/sh_tmu.c
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/* * SuperH Timer Support - TMU * * Copyright (C) 2009 Magnus Damm * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. |
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*/ |
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#include <linux/clk.h> #include <linux/clockchips.h> #include <linux/clocksource.h> #include <linux/delay.h> #include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/irq.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_domain.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/sh_timer.h> #include <linux/slab.h> #include <linux/spinlock.h> |
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enum sh_tmu_model { |
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SH_TMU, SH_TMU_SH3, }; |
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struct sh_tmu_device; |
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struct sh_tmu_channel { |
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struct sh_tmu_device *tmu; |
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unsigned int index; |
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|
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void __iomem *base; |
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int irq; |
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|
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unsigned long periodic; struct clock_event_device ced; struct clocksource cs; |
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bool cs_enabled; |
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unsigned int enable_count; |
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}; |
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struct sh_tmu_device { |
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struct platform_device *pdev; void __iomem *mapbase; struct clk *clk; |
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unsigned long rate; |
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|
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enum sh_tmu_model model; |
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raw_spinlock_t lock; /* Protect the shared start/stop register */ |
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struct sh_tmu_channel *channels; unsigned int num_channels; |
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bool has_clockevent; bool has_clocksource; |
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}; |
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#define TSTR -1 /* shared register */ #define TCOR 0 /* channel register */ #define TCNT 1 /* channel register */ #define TCR 2 /* channel register */ |
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#define TCR_UNF (1 << 8) #define TCR_UNIE (1 << 5) #define TCR_TPSC_CLK4 (0 << 0) #define TCR_TPSC_CLK16 (1 << 0) #define TCR_TPSC_CLK64 (2 << 0) #define TCR_TPSC_CLK256 (3 << 0) #define TCR_TPSC_CLK1024 (4 << 0) #define TCR_TPSC_MASK (7 << 0) |
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static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) |
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{ |
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unsigned long offs; |
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if (reg_nr == TSTR) { switch (ch->tmu->model) { |
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case SH_TMU_SH3: return ioread8(ch->tmu->mapbase + 2); case SH_TMU: return ioread8(ch->tmu->mapbase + 4); } } |
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offs = reg_nr << 2; if (reg_nr == TCR) |
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return ioread16(ch->base + offs); |
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else |
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return ioread32(ch->base + offs); |
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} |
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static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, |
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unsigned long value) { |
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unsigned long offs; if (reg_nr == TSTR) { |
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switch (ch->tmu->model) { |
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case SH_TMU_SH3: return iowrite8(value, ch->tmu->mapbase + 2); case SH_TMU: return iowrite8(value, ch->tmu->mapbase + 4); } |
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} offs = reg_nr << 2; if (reg_nr == TCR) |
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iowrite16(value, ch->base + offs); |
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else |
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iowrite32(value, ch->base + offs); |
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} |
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static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) |
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{ |
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unsigned long flags, value; /* start stop register shared by multiple timer channels */ |
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raw_spin_lock_irqsave(&ch->tmu->lock, flags); |
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value = sh_tmu_read(ch, TSTR); |
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if (start) |
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value |= 1 << ch->index; |
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else |
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value &= ~(1 << ch->index); |
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sh_tmu_write(ch, TSTR, value); |
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raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); |
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} |
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static int __sh_tmu_enable(struct sh_tmu_channel *ch) |
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{ |
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int ret; |
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/* enable clock */ |
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ret = clk_enable(ch->tmu->clk); |
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if (ret) { |
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dev_err(&ch->tmu->pdev->dev, "ch%u: cannot enable clock ", ch->index); |
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return ret; } /* make sure channel is disabled */ |
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sh_tmu_start_stop_ch(ch, 0); |
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/* maximum timeout */ |
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sh_tmu_write(ch, TCOR, 0xffffffff); sh_tmu_write(ch, TCNT, 0xffffffff); |
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/* configure channel to parent clock / 4, irq off */ |
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sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
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/* enable channel */ |
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sh_tmu_start_stop_ch(ch, 1); |
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return 0; } |
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static int sh_tmu_enable(struct sh_tmu_channel *ch) |
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{ |
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if (ch->enable_count++ > 0) |
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return 0; |
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pm_runtime_get_sync(&ch->tmu->pdev->dev); dev_pm_syscore_device(&ch->tmu->pdev->dev, true); |
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return __sh_tmu_enable(ch); |
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} |
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static void __sh_tmu_disable(struct sh_tmu_channel *ch) |
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{ /* disable channel */ |
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sh_tmu_start_stop_ch(ch, 0); |
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/* disable interrupts in TMU block */ |
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sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
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/* stop clock */ |
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clk_disable(ch->tmu->clk); |
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} |
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static void sh_tmu_disable(struct sh_tmu_channel *ch) |
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{ |
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if (WARN_ON(ch->enable_count == 0)) |
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return; |
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if (--ch->enable_count > 0) |
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return; |
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__sh_tmu_disable(ch); |
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dev_pm_syscore_device(&ch->tmu->pdev->dev, false); pm_runtime_put(&ch->tmu->pdev->dev); |
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} |
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static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, |
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int periodic) { /* stop timer */ |
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sh_tmu_start_stop_ch(ch, 0); |
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/* acknowledge interrupt */ |
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sh_tmu_read(ch, TCR); |
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/* enable interrupt */ |
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sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
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/* reload delta value in case of periodic timer */ if (periodic) |
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sh_tmu_write(ch, TCOR, delta); |
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else |
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sh_tmu_write(ch, TCOR, 0xffffffff); |
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sh_tmu_write(ch, TCNT, delta); |
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/* start timer */ |
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sh_tmu_start_stop_ch(ch, 1); |
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} static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id) { |
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struct sh_tmu_channel *ch = dev_id; |
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/* disable or acknowledge interrupt */ |
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if (clockevent_state_oneshot(&ch->ced)) |
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sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); |
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else |
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sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); |
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/* notify clockevent layer */ |
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ch->ced.event_handler(&ch->ced); |
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return IRQ_HANDLED; } |
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static struct sh_tmu_channel *cs_to_sh_tmu(struct clocksource *cs) |
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{ |
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return container_of(cs, struct sh_tmu_channel, cs); |
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} |
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static u64 sh_tmu_clocksource_read(struct clocksource *cs) |
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{ |
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
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return sh_tmu_read(ch, TCNT) ^ 0xffffffff; |
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} static int sh_tmu_clocksource_enable(struct clocksource *cs) { |
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
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int ret; |
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if (WARN_ON(ch->cs_enabled)) |
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return 0; |
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ret = sh_tmu_enable(ch); |
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if (!ret) |
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ch->cs_enabled = true; |
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return ret; |
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} static void sh_tmu_clocksource_disable(struct clocksource *cs) { |
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
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if (WARN_ON(!ch->cs_enabled)) |
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return; |
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sh_tmu_disable(ch); ch->cs_enabled = false; |
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} static void sh_tmu_clocksource_suspend(struct clocksource *cs) { |
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
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if (!ch->cs_enabled) |
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return; |
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if (--ch->enable_count == 0) { __sh_tmu_disable(ch); pm_genpd_syscore_poweroff(&ch->tmu->pdev->dev); |
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} |
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} static void sh_tmu_clocksource_resume(struct clocksource *cs) { |
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struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); |
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if (!ch->cs_enabled) |
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return; |
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if (ch->enable_count++ == 0) { pm_genpd_syscore_poweron(&ch->tmu->pdev->dev); __sh_tmu_enable(ch); |
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} |
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} |
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static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, |
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const char *name) |
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{ |
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struct clocksource *cs = &ch->cs; |
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cs->name = name; |
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cs->rating = 200; |
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cs->read = sh_tmu_clocksource_read; cs->enable = sh_tmu_clocksource_enable; cs->disable = sh_tmu_clocksource_disable; |
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cs->suspend = sh_tmu_clocksource_suspend; cs->resume = sh_tmu_clocksource_resume; |
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cs->mask = CLOCKSOURCE_MASK(32); cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; |
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dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source ", ch->index); |
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clocksource_register_hz(cs, ch->tmu->rate); |
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return 0; } |
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static struct sh_tmu_channel *ced_to_sh_tmu(struct clock_event_device *ced) |
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{ |
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return container_of(ced, struct sh_tmu_channel, ced); |
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} |
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static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) |
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{ |
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sh_tmu_enable(ch); |
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if (periodic) { |
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ch->periodic = (ch->tmu->rate + HZ/2) / HZ; |
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sh_tmu_set_next(ch, ch->periodic, 1); |
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} } |
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static int sh_tmu_clock_event_shutdown(struct clock_event_device *ced) { struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
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if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) sh_tmu_disable(ch); |
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return 0; } static int sh_tmu_clock_event_set_state(struct clock_event_device *ced, int periodic) |
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{ |
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struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
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/* deal with old setting first */ |
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if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) |
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sh_tmu_disable(ch); |
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dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events ", ch->index, periodic ? "periodic" : "oneshot"); sh_tmu_clock_event_start(ch, periodic); return 0; } static int sh_tmu_clock_event_set_oneshot(struct clock_event_device *ced) { return sh_tmu_clock_event_set_state(ced, 0); } static int sh_tmu_clock_event_set_periodic(struct clock_event_device *ced) { return sh_tmu_clock_event_set_state(ced, 1); |
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} static int sh_tmu_clock_event_next(unsigned long delta, struct clock_event_device *ced) { |
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struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); |
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BUG_ON(!clockevent_state_oneshot(ced)); |
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/* program new delta value */ |
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sh_tmu_set_next(ch, delta, 0); |
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return 0; } |
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static void sh_tmu_clock_event_suspend(struct clock_event_device *ced) { |
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pm_genpd_syscore_poweroff(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
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} static void sh_tmu_clock_event_resume(struct clock_event_device *ced) { |
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pm_genpd_syscore_poweron(&ced_to_sh_tmu(ced)->tmu->pdev->dev); |
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} |
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static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, |
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const char *name) |
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{ |
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struct clock_event_device *ced = &ch->ced; |
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int ret; |
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ced->name = name; ced->features = CLOCK_EVT_FEAT_PERIODIC; ced->features |= CLOCK_EVT_FEAT_ONESHOT; |
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ced->rating = 200; |
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ced->cpumask = cpu_possible_mask; |
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ced->set_next_event = sh_tmu_clock_event_next; |
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ced->set_state_shutdown = sh_tmu_clock_event_shutdown; ced->set_state_periodic = sh_tmu_clock_event_set_periodic; ced->set_state_oneshot = sh_tmu_clock_event_set_oneshot; |
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ced->suspend = sh_tmu_clock_event_suspend; ced->resume = sh_tmu_clock_event_resume; |
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dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events ", ch->index); |
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clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); |
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ret = request_irq(ch->irq, sh_tmu_interrupt, |
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IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
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dev_name(&ch->tmu->pdev->dev), ch); |
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if (ret) { |
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dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d ", ch->index, ch->irq); |
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return; } |
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} |
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414 |
static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, |
f1010ed1a
|
415 |
bool clockevent, bool clocksource) |
9570ef204
|
416 |
{ |
8c7f21e67
|
417 418 |
if (clockevent) { ch->tmu->has_clockevent = true; |
f1010ed1a
|
419 |
sh_tmu_register_clockevent(ch, name); |
8c7f21e67
|
420 421 |
} else if (clocksource) { ch->tmu->has_clocksource = true; |
f1010ed1a
|
422 |
sh_tmu_register_clocksource(ch, name); |
8c7f21e67
|
423 |
} |
9570ef204
|
424 425 426 |
return 0; } |
8c7f21e67
|
427 428 |
static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, bool clockevent, bool clocksource, |
a94ddaa6f
|
429 430 |
struct sh_tmu_device *tmu) { |
8c7f21e67
|
431 432 433 |
/* Skip unused channels. */ if (!clockevent && !clocksource) return 0; |
a94ddaa6f
|
434 |
|
a94ddaa6f
|
435 |
ch->tmu = tmu; |
681b9e852
|
436 |
ch->index = index; |
a94ddaa6f
|
437 |
|
681b9e852
|
438 439 440 441 |
if (tmu->model == SH_TMU_SH3) ch->base = tmu->mapbase + 4 + ch->index * 12; else ch->base = tmu->mapbase + 8 + ch->index * 12; |
fe68eb802
|
442 |
|
c54697ae1
|
443 |
ch->irq = platform_get_irq(tmu->pdev, index); |
a94ddaa6f
|
444 |
if (ch->irq < 0) { |
fe68eb802
|
445 446 447 |
dev_err(&tmu->pdev->dev, "ch%u: failed to get irq ", ch->index); |
a94ddaa6f
|
448 449 450 451 452 |
return ch->irq; } ch->cs_enabled = false; ch->enable_count = 0; |
84876d050
|
453 |
return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), |
8c7f21e67
|
454 |
clockevent, clocksource); |
a94ddaa6f
|
455 |
} |
8c7f21e67
|
456 |
static int sh_tmu_map_memory(struct sh_tmu_device *tmu) |
9570ef204
|
457 |
{ |
9570ef204
|
458 |
struct resource *res; |
9570ef204
|
459 |
|
0a72aa39c
|
460 |
res = platform_get_resource(tmu->pdev, IORESOURCE_MEM, 0); |
9570ef204
|
461 |
if (!res) { |
0a72aa39c
|
462 463 |
dev_err(&tmu->pdev->dev, "failed to get I/O memory "); |
8c7f21e67
|
464 |
return -ENXIO; |
9570ef204
|
465 |
} |
8c7f21e67
|
466 467 468 |
tmu->mapbase = ioremap_nocache(res->start, resource_size(res)); if (tmu->mapbase == NULL) return -ENXIO; |
8c7f21e67
|
469 470 |
return 0; } |
de693461b
|
471 |
|
3e29b5543
|
472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 |
static int sh_tmu_parse_dt(struct sh_tmu_device *tmu) { struct device_node *np = tmu->pdev->dev.of_node; tmu->model = SH_TMU; tmu->num_channels = 3; of_property_read_u32(np, "#renesas,channels", &tmu->num_channels); if (tmu->num_channels != 2 && tmu->num_channels != 3) { dev_err(&tmu->pdev->dev, "invalid number of channels %u ", tmu->num_channels); return -EINVAL; } return 0; } |
8c7f21e67
|
490 491 |
static int sh_tmu_setup(struct sh_tmu_device *tmu, struct platform_device *pdev) { |
8c7f21e67
|
492 493 |
unsigned int i; int ret; |
8c7f21e67
|
494 |
tmu->pdev = pdev; |
8c7f21e67
|
495 |
|
2b027f1f0
|
496 |
raw_spin_lock_init(&tmu->lock); |
3e29b5543
|
497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 |
if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { ret = sh_tmu_parse_dt(tmu); if (ret < 0) return ret; } else if (pdev->dev.platform_data) { const struct platform_device_id *id = pdev->id_entry; struct sh_timer_config *cfg = pdev->dev.platform_data; tmu->model = id->driver_data; tmu->num_channels = hweight8(cfg->channels_mask); } else { dev_err(&tmu->pdev->dev, "missing platform data "); return -ENXIO; } |
8c7f21e67
|
512 |
/* Get hold of clock. */ |
681b9e852
|
513 |
tmu->clk = clk_get(&tmu->pdev->dev, "fck"); |
0a72aa39c
|
514 515 516 |
if (IS_ERR(tmu->clk)) { dev_err(&tmu->pdev->dev, "cannot get clock "); |
8c7f21e67
|
517 |
return PTR_ERR(tmu->clk); |
9570ef204
|
518 |
} |
1c09eb3e2
|
519 |
|
0a72aa39c
|
520 |
ret = clk_prepare(tmu->clk); |
1c09eb3e2
|
521 |
if (ret < 0) |
8c7f21e67
|
522 |
goto err_clk_put; |
c3c0a20df
|
523 524 525 526 527 528 529 |
/* Determine clock rate. */ ret = clk_enable(tmu->clk); if (ret < 0) goto err_clk_unprepare; tmu->rate = clk_get_rate(tmu->clk) / 4; clk_disable(tmu->clk); |
8c7f21e67
|
530 531 532 533 534 535 536 |
/* Map the memory resource. */ ret = sh_tmu_map_memory(tmu); if (ret < 0) { dev_err(&tmu->pdev->dev, "failed to remap I/O memory "); goto err_clk_unprepare; } |
1c09eb3e2
|
537 |
|
8c7f21e67
|
538 |
/* Allocate and setup the channels. */ |
8c7f21e67
|
539 540 |
tmu->channels = kzalloc(sizeof(*tmu->channels) * tmu->num_channels, GFP_KERNEL); |
a5de49f43
|
541 542 |
if (tmu->channels == NULL) { ret = -ENOMEM; |
8c7f21e67
|
543 |
goto err_unmap; |
a5de49f43
|
544 |
} |
681b9e852
|
545 546 547 548 549 550 551 |
/* * Use the first channel as a clock event device and the second channel * as a clock source. */ for (i = 0; i < tmu->num_channels; ++i) { ret = sh_tmu_channel_setup(&tmu->channels[i], i, i == 0, i == 1, tmu); |
8c7f21e67
|
552 553 |
if (ret < 0) goto err_unmap; |
8c7f21e67
|
554 |
} |
a5de49f43
|
555 |
|
8c7f21e67
|
556 |
platform_set_drvdata(pdev, tmu); |
394a4486f
|
557 558 |
return 0; |
8c7f21e67
|
559 |
err_unmap: |
a5de49f43
|
560 |
kfree(tmu->channels); |
681b9e852
|
561 |
iounmap(tmu->mapbase); |
8c7f21e67
|
562 |
err_clk_unprepare: |
0a72aa39c
|
563 |
clk_unprepare(tmu->clk); |
8c7f21e67
|
564 |
err_clk_put: |
0a72aa39c
|
565 |
clk_put(tmu->clk); |
9570ef204
|
566 567 |
return ret; } |
1850514b3
|
568 |
static int sh_tmu_probe(struct platform_device *pdev) |
9570ef204
|
569 |
{ |
0a72aa39c
|
570 |
struct sh_tmu_device *tmu = platform_get_drvdata(pdev); |
9570ef204
|
571 |
int ret; |
eaa49a8cd
|
572 |
if (!is_early_platform_device(pdev)) { |
61a53bfaa
|
573 574 |
pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); |
eaa49a8cd
|
575 |
} |
2ee619f94
|
576 |
|
0a72aa39c
|
577 |
if (tmu) { |
214a607a4
|
578 579 |
dev_info(&pdev->dev, "kept as earlytimer "); |
61a53bfaa
|
580 |
goto out; |
9570ef204
|
581 |
} |
3b77a83ee
|
582 |
tmu = kzalloc(sizeof(*tmu), GFP_KERNEL); |
814876b0b
|
583 |
if (tmu == NULL) |
9570ef204
|
584 |
return -ENOMEM; |
9570ef204
|
585 |
|
0a72aa39c
|
586 |
ret = sh_tmu_setup(tmu, pdev); |
9570ef204
|
587 |
if (ret) { |
0a72aa39c
|
588 |
kfree(tmu); |
61a53bfaa
|
589 590 |
pm_runtime_idle(&pdev->dev); return ret; |
9570ef204
|
591 |
} |
61a53bfaa
|
592 593 594 595 |
if (is_early_platform_device(pdev)) return 0; out: |
8c7f21e67
|
596 |
if (tmu->has_clockevent || tmu->has_clocksource) |
61a53bfaa
|
597 598 599 600 601 |
pm_runtime_irq_safe(&pdev->dev); else pm_runtime_idle(&pdev->dev); return 0; |
9570ef204
|
602 |
} |
1850514b3
|
603 |
static int sh_tmu_remove(struct platform_device *pdev) |
9570ef204
|
604 605 606 |
{ return -EBUSY; /* cannot unregister clockevent and clocksource */ } |
8c7f21e67
|
607 |
static const struct platform_device_id sh_tmu_id_table[] = { |
8c7f21e67
|
608 609 610 611 612 |
{ "sh-tmu", SH_TMU }, { "sh-tmu-sh3", SH_TMU_SH3 }, { } }; MODULE_DEVICE_TABLE(platform, sh_tmu_id_table); |
3e29b5543
|
613 614 615 616 617 |
static const struct of_device_id sh_tmu_of_table[] __maybe_unused = { { .compatible = "renesas,tmu" }, { } }; MODULE_DEVICE_TABLE(of, sh_tmu_of_table); |
9570ef204
|
618 619 |
static struct platform_driver sh_tmu_device_driver = { .probe = sh_tmu_probe, |
1850514b3
|
620 |
.remove = sh_tmu_remove, |
9570ef204
|
621 622 |
.driver = { .name = "sh_tmu", |
3e29b5543
|
623 |
.of_match_table = of_match_ptr(sh_tmu_of_table), |
8c7f21e67
|
624 625 |
}, .id_table = sh_tmu_id_table, |
9570ef204
|
626 627 628 629 630 631 632 633 634 635 636 637 638 |
}; static int __init sh_tmu_init(void) { return platform_driver_register(&sh_tmu_device_driver); } static void __exit sh_tmu_exit(void) { platform_driver_unregister(&sh_tmu_device_driver); } early_platform_init("earlytimer", &sh_tmu_device_driver); |
b9773c3f5
|
639 |
subsys_initcall(sh_tmu_init); |
9570ef204
|
640 641 642 643 644 |
module_exit(sh_tmu_exit); MODULE_AUTHOR("Magnus Damm"); MODULE_DESCRIPTION("SuperH TMU Timer Driver"); MODULE_LICENSE("GPL v2"); |