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drivers/irqchip/irq-s3c24xx.c
41.7 KB
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/* * S3C24XX IRQ handling |
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* |
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* Copyright (c) 2003-2004 Simtec Electronics |
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* Ben Dooks <ben@simtec.co.uk> |
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* Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> |
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* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. |
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*/ #include <linux/init.h> |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/io.h> #include <linux/err.h> |
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#include <linux/interrupt.h> #include <linux/ioport.h> |
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#include <linux/device.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_address.h> |
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#include <asm/exception.h> |
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#include <asm/mach/irq.h> |
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#include <mach/regs-irq.h> #include <mach/regs-gpio.h> |
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#include <plat/cpu.h> |
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#include <plat/regs-irqtype.h> |
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#include <plat/pm.h> |
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#define S3C_IRQTYPE_NONE 0 #define S3C_IRQTYPE_EINT 1 #define S3C_IRQTYPE_EDGE 2 #define S3C_IRQTYPE_LEVEL 3 |
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struct s3c_irq_data { unsigned int type; |
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unsigned long offset; |
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unsigned long parent_irq; |
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/* data gets filled during init */ struct s3c_irq_intc *intc; unsigned long sub_bits; struct s3c_irq_intc *sub_intc; |
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}; |
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/* * Sructure holding the controller data * @reg_pending register holding pending irqs * @reg_intpnd special register intpnd in main intc * @reg_mask mask register * @domain irq_domain of the controller * @parent parent controller for ext and sub irqs * @irqs irq-data, always s3c_irq_data[32] */ struct s3c_irq_intc { void __iomem *reg_pending; void __iomem *reg_intpnd; void __iomem *reg_mask; struct irq_domain *domain; struct s3c_irq_intc *parent; struct s3c_irq_data *irqs; |
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}; |
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/* * Array holding pointers to the global controller structs * [0] ... main_intc * [1] ... sub_intc * [2] ... main_intc2 on s3c2416 */ static struct s3c_irq_intc *s3c_intc[3]; |
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static void s3c_irq_mask(struct irq_data *data) |
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{ |
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struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); struct s3c_irq_intc *intc = irq_data->intc; |
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struct s3c_irq_intc *parent_intc = intc->parent; |
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struct s3c_irq_data *parent_data; |
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unsigned long mask; |
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unsigned int irqno; |
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mask = readl_relaxed(intc->reg_mask); |
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mask |= (1UL << irq_data->offset); |
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writel_relaxed(mask, intc->reg_mask); |
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if (parent_intc) { |
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parent_data = &parent_intc->irqs[irq_data->parent_irq]; |
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/* check to see if we need to mask the parent IRQ * The parent_irq is always in main_intc, so the hwirq * for find_mapping does not need an offset in any case. */ |
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if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { irqno = irq_find_mapping(parent_intc->domain, irq_data->parent_irq); s3c_irq_mask(irq_get_irq_data(irqno)); } } |
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} |
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static void s3c_irq_unmask(struct irq_data *data) |
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{ |
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struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); struct s3c_irq_intc *intc = irq_data->intc; |
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struct s3c_irq_intc *parent_intc = intc->parent; |
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unsigned long mask; |
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unsigned int irqno; |
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mask = readl_relaxed(intc->reg_mask); |
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mask &= ~(1UL << irq_data->offset); |
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writel_relaxed(mask, intc->reg_mask); |
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if (parent_intc) { |
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irqno = irq_find_mapping(parent_intc->domain, irq_data->parent_irq); s3c_irq_unmask(irq_get_irq_data(irqno)); |
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} } |
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static inline void s3c_irq_ack(struct irq_data *data) |
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{ |
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struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); struct s3c_irq_intc *intc = irq_data->intc; unsigned long bitval = 1UL << irq_data->offset; |
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writel_relaxed(bitval, intc->reg_pending); |
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if (intc->reg_intpnd) |
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writel_relaxed(bitval, intc->reg_intpnd); |
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} |
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static int s3c_irq_type(struct irq_data *data, unsigned int type) { switch (type) { case IRQ_TYPE_NONE: break; case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_BOTH: irq_set_handler(data->irq, handle_edge_irq); break; case IRQ_TYPE_LEVEL_LOW: case IRQ_TYPE_LEVEL_HIGH: irq_set_handler(data->irq, handle_level_irq); break; default: pr_err("No such irq type %d", type); return -EINVAL; } return 0; } |
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static int s3c_irqext_type_set(void __iomem *gpcon_reg, void __iomem *extint_reg, unsigned long gpcon_offset, unsigned long extint_offset, unsigned int type) |
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{ |
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unsigned long newvalue = 0, value; |
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/* Set the GPIO to external interrupt mode */ |
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value = readl_relaxed(gpcon_reg); |
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value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); |
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writel_relaxed(value, gpcon_reg); |
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/* Set the external interrupt to pointed trigger type */ switch (type) { |
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case IRQ_TYPE_NONE: |
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pr_warn("No edge setting! "); |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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newvalue = S3C2410_EXTINT_RISEEDGE; break; |
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case IRQ_TYPE_EDGE_FALLING: |
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newvalue = S3C2410_EXTINT_FALLEDGE; break; |
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case IRQ_TYPE_EDGE_BOTH: |
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newvalue = S3C2410_EXTINT_BOTHEDGE; break; |
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case IRQ_TYPE_LEVEL_LOW: |
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newvalue = S3C2410_EXTINT_LOWLEV; break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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newvalue = S3C2410_EXTINT_HILEV; break; default: |
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pr_err("No such irq type %d", type); return -EINVAL; |
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} |
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value = readl_relaxed(extint_reg); |
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value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); |
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writel_relaxed(value, extint_reg); |
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return 0; } |
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static int s3c_irqext_type(struct irq_data *data, unsigned int type) |
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{ |
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void __iomem *extint_reg; void __iomem *gpcon_reg; unsigned long gpcon_offset, extint_offset; |
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if ((data->hwirq >= 4) && (data->hwirq <= 7)) { gpcon_reg = S3C2410_GPFCON; extint_reg = S3C24XX_EXTINT0; gpcon_offset = (data->hwirq) * 2; extint_offset = (data->hwirq) * 4; } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { gpcon_reg = S3C2410_GPGCON; extint_reg = S3C24XX_EXTINT1; gpcon_offset = (data->hwirq - 8) * 2; extint_offset = (data->hwirq - 8) * 4; } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { gpcon_reg = S3C2410_GPGCON; extint_reg = S3C24XX_EXTINT2; gpcon_offset = (data->hwirq - 8) * 2; extint_offset = (data->hwirq - 16) * 4; } else { return -EINVAL; } |
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return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, extint_offset, type); |
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} |
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static int s3c_irqext0_type(struct irq_data *data, unsigned int type) |
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{ |
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void __iomem *extint_reg; void __iomem *gpcon_reg; unsigned long gpcon_offset, extint_offset; |
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if ((data->hwirq >= 0) && (data->hwirq <= 3)) { gpcon_reg = S3C2410_GPFCON; extint_reg = S3C24XX_EXTINT0; gpcon_offset = (data->hwirq) * 2; extint_offset = (data->hwirq) * 4; } else { return -EINVAL; } |
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return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, extint_offset, type); |
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} |
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static struct irq_chip s3c_irq_chip = { |
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.name = "s3c", .irq_ack = s3c_irq_ack, .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, |
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.irq_set_type = s3c_irq_type, |
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.irq_set_wake = s3c_irq_wake |
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}; |
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static struct irq_chip s3c_irq_level_chip = { |
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.name = "s3c-level", .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_ack = s3c_irq_ack, |
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.irq_set_type = s3c_irq_type, |
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}; |
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static struct irq_chip s3c_irqext_chip = { .name = "s3c-ext", .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_ack = s3c_irq_ack, .irq_set_type = s3c_irqext_type, .irq_set_wake = s3c_irqext_wake |
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}; |
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static struct irq_chip s3c_irq_eint0t4 = { .name = "s3c-ext0", .irq_ack = s3c_irq_ack, .irq_mask = s3c_irq_mask, .irq_unmask = s3c_irq_unmask, .irq_set_wake = s3c_irq_wake, .irq_set_type = s3c_irqext0_type, }; |
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static void s3c_irq_demux(struct irq_desc *desc) |
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{ |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc); |
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struct s3c_irq_intc *intc = irq_data->intc; |
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struct s3c_irq_intc *sub_intc = irq_data->sub_intc; |
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unsigned int n, offset, irq; unsigned long src, msk; |
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/* we're using individual domains for the non-dt case * and one big domain for the dt case where the subintc * starts at hwirq number 32. */ |
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offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; |
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chained_irq_enter(chip, desc); |
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src = readl_relaxed(sub_intc->reg_pending); msk = readl_relaxed(sub_intc->reg_mask); |
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src &= ~msk; src &= irq_data->sub_bits; while (src) { n = __ffs(src); src &= ~(1 << n); |
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irq = irq_find_mapping(sub_intc->domain, offset + n); generic_handle_irq(irq); |
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} |
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chained_irq_exit(chip, desc); |
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} |
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static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, |
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struct pt_regs *regs, int intc_offset) |
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{ int pnd; int offset; |
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pnd = readl_relaxed(intc->reg_intpnd); |
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if (!pnd) return false; |
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/* non-dt machines use individual domains */ |
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if (!irq_domain_get_of_node(intc->domain)) |
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intc_offset = 0; |
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/* We have a problem that the INTOFFSET register does not always * show one interrupt. Occasionally we get two interrupts through * the prioritiser, and this causes the INTOFFSET register to show * what looks like the logical-or of the two interrupt numbers. * * Thanks to Klaus, Shannon, et al for helping to debug this problem */ |
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offset = readl_relaxed(intc->reg_intpnd + 4); |
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/* Find the bit manually, when the offset is wrong. * The pending register only ever contains the one bit of the next * interrupt to handle. */ if (!(pnd & (1 << offset))) offset = __ffs(pnd); |
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handle_domain_irq(intc->domain, intc_offset + offset, regs); |
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return true; } asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) { do { |
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if (likely(s3c_intc[0])) |
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if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) |
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continue; |
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if (s3c_intc[2]) |
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if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) |
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continue; break; } while (1); } |
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#ifdef CONFIG_FIQ /** * s3c24xx_set_fiq - set the FIQ routing * @irq: IRQ number to route to FIQ on processor. * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. * * Change the state of the IRQ to FIQ routing depending on @irq and @on. If * @on is true, the @irq is checked to see if it can be routed and the * interrupt controller updated to route the IRQ. If @on is false, the FIQ * routing is cleared, regardless of which @irq is specified. */ int s3c24xx_set_fiq(unsigned int irq, bool on) { u32 intmod; unsigned offs; if (on) { offs = irq - FIQ_START; if (offs > 31) return -EINVAL; intmod = 1 << offs; } else { intmod = 0; } |
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writel_relaxed(intmod, S3C2410_INTMOD); |
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return 0; } |
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EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); |
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#endif |
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static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) |
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{ |
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struct s3c_irq_intc *intc = h->host_data; struct s3c_irq_data *irq_data = &intc->irqs[hw]; struct s3c_irq_intc *parent_intc; struct s3c_irq_data *parent_irq_data; unsigned int irqno; |
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/* attach controller pointer to irq_data */ irq_data->intc = intc; |
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irq_data->offset = hw; |
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parent_intc = intc->parent; |
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/* set handler and flags */ switch (irq_data->type) { case S3C_IRQTYPE_NONE: return 0; case S3C_IRQTYPE_EINT: |
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/* On the S3C2412, the EINT0to3 have a parent irq * but need the s3c_irq_eint0t4 chip */ |
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if (parent_intc && (!soc_is_s3c2412() || hw >= 4)) |
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irq_set_chip_and_handler(virq, &s3c_irqext_chip, handle_edge_irq); else irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, handle_edge_irq); break; case S3C_IRQTYPE_EDGE: |
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if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) |
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip, handle_edge_irq); else irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq); break; case S3C_IRQTYPE_LEVEL: |
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if (parent_intc) |
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irq_set_chip_and_handler(virq, &s3c_irq_level_chip, handle_level_irq); else irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_level_irq); break; default: pr_err("irq-s3c24xx: unsupported irqtype %d ", irq_data->type); return -EINVAL; |
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} |
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irq_set_chip_data(virq, irq_data); |
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if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { |
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if (irq_data->parent_irq > 31) { pr_err("irq-s3c24xx: parent irq %lu is out of range ", irq_data->parent_irq); |
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return -EINVAL; |
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} |
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445 |
parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; |
1f629b7a3
|
446 447 |
parent_irq_data->sub_intc = intc; parent_irq_data->sub_bits |= (1UL << hw); |
a21765a70
|
448 |
|
1f629b7a3
|
449 450 451 452 453 454 455 |
/* attach the demuxer to the parent irq */ irqno = irq_find_mapping(parent_intc->domain, irq_data->parent_irq); if (!irqno) { pr_err("irq-s3c24xx: could not find mapping for parent irq %lu ", irq_data->parent_irq); |
d17cab445
|
456 |
return -EINVAL; |
1f629b7a3
|
457 458 |
} irq_set_chained_handler(irqno, s3c_irq_demux); |
a21765a70
|
459 |
} |
1f629b7a3
|
460 |
return 0; |
1f629b7a3
|
461 |
} |
a21765a70
|
462 |
|
960097365
|
463 |
static const struct irq_domain_ops s3c24xx_irq_ops = { |
1f629b7a3
|
464 465 466 |
.map = s3c24xx_irq_map, .xlate = irq_domain_xlate_twocell, }; |
a21765a70
|
467 |
|
1f629b7a3
|
468 469 470 471 472 473 |
static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) { void __iomem *reg_source; unsigned long pend; unsigned long last; int i; |
a21765a70
|
474 |
|
1f629b7a3
|
475 476 |
/* if intpnd is set, read the next pending irq from there */ reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; |
a21765a70
|
477 |
|
1f629b7a3
|
478 479 |
last = 0; for (i = 0; i < 4; i++) { |
353332855
|
480 |
pend = readl_relaxed(reg_source); |
a21765a70
|
481 |
|
1f629b7a3
|
482 |
if (pend == 0 || pend == last) |
a21765a70
|
483 |
break; |
353332855
|
484 |
writel_relaxed(pend, intc->reg_pending); |
1f629b7a3
|
485 |
if (intc->reg_intpnd) |
353332855
|
486 |
writel_relaxed(pend, intc->reg_intpnd); |
a21765a70
|
487 |
|
1f629b7a3
|
488 489 490 |
pr_info("irq: clearing pending status %08x ", (int)pend); last = pend; |
a21765a70
|
491 |
} |
1f629b7a3
|
492 |
} |
a21765a70
|
493 |
|
bc8fd900c
|
494 |
static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np, |
1f629b7a3
|
495 496 497 498 499 500 501 502 |
struct s3c_irq_data *irq_data, struct s3c_irq_intc *parent, unsigned long address) { struct s3c_irq_intc *intc; void __iomem *base = (void *)0xf6000000; /* static mapping */ int irq_num; int irq_start; |
1f629b7a3
|
503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 |
int ret; intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); if (!intc) return ERR_PTR(-ENOMEM); intc->irqs = irq_data; if (parent) intc->parent = parent; /* select the correct data for the controller. * Need to hard code the irq num start and offset * to preserve the static mapping for now */ switch (address) { case 0x4a000000: pr_debug("irq: found main intc "); intc->reg_pending = base; intc->reg_mask = base + 0x08; intc->reg_intpnd = base + 0x10; irq_num = 32; irq_start = S3C2410_IRQ(0); |
1f629b7a3
|
527 528 529 530 531 532 533 534 |
break; case 0x4a000018: pr_debug("irq: found subintc "); intc->reg_pending = base + 0x18; intc->reg_mask = base + 0x1c; irq_num = 29; irq_start = S3C2410_IRQSUB(0); |
1f629b7a3
|
535 536 537 538 539 540 541 542 543 |
break; case 0x4a000040: pr_debug("irq: found intc2 "); intc->reg_pending = base + 0x40; intc->reg_mask = base + 0x48; intc->reg_intpnd = base + 0x50; irq_num = 8; irq_start = S3C2416_IRQ(0); |
1f629b7a3
|
544 545 546 547 548 549 550 |
break; case 0x560000a4: pr_debug("irq: found eintc "); base = (void *)0xfd000000; intc->reg_mask = base + 0xa4; |
646dd2f0a
|
551 |
intc->reg_pending = base + 0xa8; |
5424f2188
|
552 |
irq_num = 24; |
1f629b7a3
|
553 |
irq_start = S3C2410_IRQ(32); |
1f629b7a3
|
554 555 556 557 558 559 560 |
break; default: pr_err("irq: unsupported controller address "); ret = -EINVAL; goto err; } |
a21765a70
|
561 |
|
1f629b7a3
|
562 563 564 |
/* now that all the data is complete, init the irq-domain */ s3c24xx_clear_intc(intc); intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, |
5424f2188
|
565 |
0, &s3c24xx_irq_ops, |
1f629b7a3
|
566 567 568 569 570 571 572 |
intc); if (!intc->domain) { pr_err("irq: could not create irq-domain "); ret = -EINVAL; goto err; } |
a21765a70
|
573 |
|
17453dd2e
|
574 |
set_handle_irq(s3c24xx_handle_irq); |
1f629b7a3
|
575 |
return intc; |
a21765a70
|
576 |
|
1f629b7a3
|
577 578 579 580 |
err: kfree(intc); return ERR_PTR(ret); } |
a21765a70
|
581 |
|
eb249a119
|
582 |
static struct s3c_irq_data __maybe_unused init_eint[32] = { |
f182aa1df
|
583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 |
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ }; |
a21765a70
|
608 |
|
f182aa1df
|
609 610 |
#ifdef CONFIG_CPU_S3C2410 static struct s3c_irq_data init_s3c2410base[32] = { |
1f629b7a3
|
611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 |
{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ }; |
a21765a70
|
644 |
|
f182aa1df
|
645 |
static struct s3c_irq_data init_s3c2410subint[32] = { |
1f629b7a3
|
646 647 648 649 650 651 652 653 654 655 656 657 |
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ }; |
a21765a70
|
658 |
|
f182aa1df
|
659 |
void __init s3c2410_init_irq(void) |
1f629b7a3
|
660 |
{ |
1f629b7a3
|
661 662 663 |
#ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif |
a21765a70
|
664 |
|
658dc8fb9
|
665 666 667 |
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, 0x4a000000); if (IS_ERR(s3c_intc[0])) { |
1f629b7a3
|
668 669 670 |
pr_err("irq: could not create main interrupt controller "); return; |
a21765a70
|
671 |
} |
658dc8fb9
|
672 673 674 |
s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0], s3c_intc[0], 0x4a000018); s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); |
a21765a70
|
675 |
} |
f182aa1df
|
676 |
#endif |
ef602eb53
|
677 |
|
d3d5a2c9e
|
678 |
#ifdef CONFIG_CPU_S3C2412 |
4245944c7
|
679 |
static struct s3c_irq_data init_s3c2412base[32] = { |
1c8408e31
|
680 681 682 683 |
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */ |
4245944c7
|
684 685 |
{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ |
1f629b7a3
|
686 |
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
4245944c7
|
687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 |
{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ |
1f629b7a3
|
704 |
{ .type = S3C_IRQTYPE_NONE, }, /* reserved */ |
4245944c7
|
705 706 707 708 709 710 711 712 |
{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ }; |
d3d5a2c9e
|
713 |
|
1c8408e31
|
714 715 716 717 718 |
static struct s3c_irq_data init_s3c2412eint[32] = { { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */ |
1f629b7a3
|
719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 |
{ .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ }; |
a21765a70
|
740 |
|
4245944c7
|
741 |
static struct s3c_irq_data init_s3c2412subint[32] = { |
1f629b7a3
|
742 743 744 745 746 747 748 749 750 751 752 |
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
4245944c7
|
753 754 755 756 |
{ .type = S3C_IRQTYPE_NONE, }, { .type = S3C_IRQTYPE_NONE, }, { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ |
1f629b7a3
|
757 |
}; |
a21765a70
|
758 |
|
bc8fd900c
|
759 |
void __init s3c2412_init_irq(void) |
1f629b7a3
|
760 |
{ |
4245944c7
|
761 762 |
pr_info("S3C2412: IRQ Support "); |
a21765a70
|
763 |
|
1f629b7a3
|
764 765 766 |
#ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif |
a21765a70
|
767 |
|
658dc8fb9
|
768 769 770 |
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, 0x4a000000); if (IS_ERR(s3c_intc[0])) { |
1f629b7a3
|
771 772 773 |
pr_err("irq: could not create main interrupt controller "); return; |
a21765a70
|
774 |
} |
658dc8fb9
|
775 776 777 |
s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4); s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0], s3c_intc[0], 0x4a000018); |
a21765a70
|
778 |
} |
d3d5a2c9e
|
779 |
#endif |
ef602eb53
|
780 781 |
#ifdef CONFIG_CPU_S3C2416 |
20f6c781c
|
782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 |
static struct s3c_irq_data init_s3c2416base[32] = { { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ { .type = S3C_IRQTYPE_NONE, }, /* reserved */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ { .type = S3C_IRQTYPE_NONE, }, { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
ef602eb53
|
815 |
}; |
20f6c781c
|
816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 |
static struct s3c_irq_data init_s3c2416subint[32] = { { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ |
ef602eb53
|
846 |
}; |
20f6c781c
|
847 848 |
static struct s3c_irq_data init_s3c2416_second[32] = { { .type = S3C_IRQTYPE_EDGE }, /* 2D */ |
1ebc7e83b
|
849 |
{ .type = S3C_IRQTYPE_NONE }, /* reserved */ |
20f6c781c
|
850 851 852 |
{ .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ |
1ebc7e83b
|
853 |
{ .type = S3C_IRQTYPE_NONE }, /* reserved */ |
20f6c781c
|
854 |
{ .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ |
ef602eb53
|
855 |
}; |
4a282dd3b
|
856 |
void __init s3c2416_init_irq(void) |
ef602eb53
|
857 |
{ |
20f6c781c
|
858 859 |
pr_info("S3C2416: IRQ Support "); |
ef602eb53
|
860 |
|
20f6c781c
|
861 862 863 |
#ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif |
ef602eb53
|
864 |
|
658dc8fb9
|
865 866 867 |
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, 0x4a000000); if (IS_ERR(s3c_intc[0])) { |
20f6c781c
|
868 869 870 871 |
pr_err("irq: could not create main interrupt controller "); return; } |
ef602eb53
|
872 |
|
658dc8fb9
|
873 874 875 |
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0], s3c_intc[0], 0x4a000018); |
ef602eb53
|
876 |
|
658dc8fb9
|
877 878 |
s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0], NULL, 0x4a000040); |
ef602eb53
|
879 |
} |
ef602eb53
|
880 |
#endif |
6b6289171
|
881 |
|
ce6c164bf
|
882 |
#ifdef CONFIG_CPU_S3C2440 |
f0301673f
|
883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 |
static struct s3c_irq_data init_s3c2440base[32] = { { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ }; |
2286cf467
|
917 |
|
f0301673f
|
918 919 920 921 922 923 924 925 926 927 928 929 |
static struct s3c_irq_data init_s3c2440subint[32] = { { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
e2714f79e
|
930 931 |
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ |
f0301673f
|
932 933 |
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ |
2286cf467
|
934 |
}; |
7cefed5e6
|
935 |
void __init s3c2440_init_irq(void) |
2286cf467
|
936 |
{ |
f0301673f
|
937 938 |
pr_info("S3C2440: IRQ Support "); |
ef602eb53
|
939 |
|
f0301673f
|
940 941 942 |
#ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif |
6f8d7ea27
|
943 |
|
658dc8fb9
|
944 945 946 |
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000); if (IS_ERR(s3c_intc[0])) { |
f0301673f
|
947 948 949 |
pr_err("irq: could not create main interrupt controller "); return; |
6f8d7ea27
|
950 |
} |
7cefed5e6
|
951 |
|
658dc8fb9
|
952 953 954 |
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0], s3c_intc[0], 0x4a000018); |
ef602eb53
|
955 |
} |
ce6c164bf
|
956 |
#endif |
ef602eb53
|
957 |
|
ce6c164bf
|
958 |
#ifdef CONFIG_CPU_S3C2442 |
70644ade4
|
959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 |
static struct s3c_irq_data init_s3c2442base[32] = { { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ }; |
6f8d7ea27
|
993 |
|
70644ade4
|
994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 |
static struct s3c_irq_data init_s3c2442subint[32] = { { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ |
e2714f79e
|
1006 1007 |
{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ |
70644ade4
|
1008 |
}; |
6f8d7ea27
|
1009 |
|
70644ade4
|
1010 1011 |
void __init s3c2442_init_irq(void) { |
70644ade4
|
1012 1013 |
pr_info("S3C2442: IRQ Support "); |
6f8d7ea27
|
1014 |
|
70644ade4
|
1015 1016 1017 |
#ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif |
ce6c164bf
|
1018 |
|
658dc8fb9
|
1019 1020 1021 |
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, 0x4a000000); if (IS_ERR(s3c_intc[0])) { |
70644ade4
|
1022 1023 1024 |
pr_err("irq: could not create main interrupt controller "); return; |
ce6c164bf
|
1025 |
} |
70644ade4
|
1026 |
|
658dc8fb9
|
1027 1028 1029 |
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0], s3c_intc[0], 0x4a000018); |
6f8d7ea27
|
1030 |
} |
ef602eb53
|
1031 |
#endif |
6b6289171
|
1032 1033 |
#ifdef CONFIG_CPU_S3C2443 |
f44ddba36
|
1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 |
static struct s3c_irq_data init_s3c2443base[32] = { { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ |
6b6289171
|
1067 |
}; |
6b6289171
|
1068 |
|
f44ddba36
|
1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 |
static struct s3c_irq_data init_s3c2443subint[32] = { { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ { .type = S3C_IRQTYPE_NONE }, /* reserved */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ |
6b6289171
|
1099 |
}; |
b499b7a87
|
1100 |
void __init s3c2443_init_irq(void) |
6b6289171
|
1101 |
{ |
f44ddba36
|
1102 1103 |
pr_info("S3C2443: IRQ Support "); |
6b6289171
|
1104 |
|
f44ddba36
|
1105 1106 1107 |
#ifdef CONFIG_FIQ init_FIQ(FIQ_START); #endif |
6b6289171
|
1108 |
|
658dc8fb9
|
1109 1110 1111 |
s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, 0x4a000000); if (IS_ERR(s3c_intc[0])) { |
f44ddba36
|
1112 1113 1114 1115 |
pr_err("irq: could not create main interrupt controller "); return; } |
6b6289171
|
1116 |
|
658dc8fb9
|
1117 1118 1119 |
s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0], s3c_intc[0], 0x4a000018); |
6b6289171
|
1120 |
} |
6b6289171
|
1121 |
#endif |
f0774d41d
|
1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 |
#ifdef CONFIG_OF static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq, irq_hw_number_t hw) { unsigned int ctrl_num = hw / 32; unsigned int intc_hw = hw % 32; struct s3c_irq_intc *intc = s3c_intc[ctrl_num]; struct s3c_irq_intc *parent_intc = intc->parent; struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; /* attach controller pointer to irq_data */ irq_data->intc = intc; irq_data->offset = intc_hw; if (!parent_intc) irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq); else irq_set_chip_and_handler(virq, &s3c_irq_level_chip, handle_edge_irq); irq_set_chip_data(virq, irq_data); |
f0774d41d
|
1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 |
return 0; } /* Translate our of irq notation * format: <ctrl_num ctrl_irq parent_irq type> */ static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { struct s3c_irq_intc *intc; struct s3c_irq_intc *parent_intc; struct s3c_irq_data *irq_data; struct s3c_irq_data *parent_irq_data; int irqno; if (WARN_ON(intsize < 4)) return -EINVAL; if (intspec[0] > 2 || !s3c_intc[intspec[0]]) { pr_err("controller number %d invalid ", intspec[0]); return -EINVAL; } intc = s3c_intc[intspec[0]]; *out_hwirq = intspec[0] * 32 + intspec[2]; *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; parent_intc = intc->parent; if (parent_intc) { irq_data = &intc->irqs[intspec[2]]; irq_data->parent_irq = intspec[1]; parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; parent_irq_data->sub_intc = intc; parent_irq_data->sub_bits |= (1UL << intspec[2]); /* parent_intc is always s3c_intc[0], so no offset */ irqno = irq_create_mapping(parent_intc->domain, intspec[1]); if (irqno < 0) { pr_err("irq: could not map parent interrupt "); return irqno; } irq_set_chained_handler(irqno, s3c_irq_demux); } return 0; } |
960097365
|
1194 |
static const struct irq_domain_ops s3c24xx_irq_ops_of = { |
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.map = s3c24xx_irq_map_of, .xlate = s3c24xx_irq_xlate_of, }; struct s3c24xx_irq_of_ctrl { char *name; unsigned long offset; struct s3c_irq_intc **handle; struct s3c_irq_intc **parent; struct irq_domain_ops *ops; }; static int __init s3c_init_intc_of(struct device_node *np, struct device_node *interrupt_parent, struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl) { struct s3c_irq_intc *intc; struct s3c24xx_irq_of_ctrl *ctrl; struct irq_domain *domain; void __iomem *reg_base; int i; reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("irq-s3c24xx: could not map irq registers "); return -EINVAL; } domain = irq_domain_add_linear(np, num_ctrl * 32, &s3c24xx_irq_ops_of, NULL); if (!domain) { pr_err("irq: could not create irq-domain "); return -EINVAL; } for (i = 0; i < num_ctrl; i++) { ctrl = &s3c_ctrl[i]; pr_debug("irq: found controller %s ", ctrl->name); intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); if (!intc) return -ENOMEM; intc->domain = domain; intc->irqs = kzalloc(sizeof(struct s3c_irq_data) * 32, GFP_KERNEL); if (!intc->irqs) { kfree(intc); return -ENOMEM; } if (ctrl->parent) { intc->reg_pending = reg_base + ctrl->offset; intc->reg_mask = reg_base + ctrl->offset + 0x4; if (*(ctrl->parent)) { intc->parent = *(ctrl->parent); } else { pr_warn("irq: parent of %s missing ", ctrl->name); kfree(intc->irqs); kfree(intc); continue; } } else { intc->reg_pending = reg_base + ctrl->offset; intc->reg_mask = reg_base + ctrl->offset + 0x08; intc->reg_intpnd = reg_base + ctrl->offset + 0x10; } s3c24xx_clear_intc(intc); s3c_intc[i] = intc; } set_handle_irq(s3c24xx_handle_irq); return 0; } static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { { .name = "intc", .offset = 0, }, { .name = "subintc", .offset = 0x18, .parent = &s3c_intc[0], } }; int __init s3c2410_init_intc_of(struct device_node *np, |
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struct device_node *interrupt_parent) |
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{ return s3c_init_intc_of(np, interrupt_parent, s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl)); } IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of); static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { { .name = "intc", .offset = 0, }, { .name = "subintc", .offset = 0x18, .parent = &s3c_intc[0], }, { .name = "intc2", .offset = 0x40, } }; int __init s3c2416_init_intc_of(struct device_node *np, |
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struct device_node *interrupt_parent) |
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{ return s3c_init_intc_of(np, interrupt_parent, s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl)); |
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} |
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IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of); |
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#endif |